1 // Copyright (C) 2022 Beken Corporation 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #include "sys_hal.h" 16 #include "sys_driver.h" 17 #include "sys_driver_common.h" 18 19 /** Audio Start **/ 20 sys_drv_aud_select_clock(uint32_t value)21uint32_t sys_drv_aud_select_clock(uint32_t value) 22 { 23 uint32_t int_level = rtos_disable_int(); 24 uint32_t ret = SYS_DRV_FAILURE; 25 ret = sys_amp_res_acquire(); 26 27 sys_hal_aud_select_clock(value); 28 29 if(!ret) 30 ret = sys_amp_res_release(); 31 rtos_enable_int(int_level); 32 33 return ret; 34 } 35 sys_drv_aud_clock_en(uint32_t value)36uint32_t sys_drv_aud_clock_en(uint32_t value) 37 { 38 uint32_t int_level = rtos_disable_int(); 39 uint32_t ret = SYS_DRV_FAILURE; 40 ret = sys_amp_res_acquire(); 41 42 sys_hal_aud_clock_en(value); 43 44 if(!ret) 45 ret = sys_amp_res_release(); 46 47 rtos_enable_int(int_level); 48 return ret; 49 } 50 sys_drv_aud_vdd1v_en(uint32_t value)51uint32_t sys_drv_aud_vdd1v_en(uint32_t value) 52 { 53 uint32_t int_level = rtos_disable_int(); 54 55 sys_hal_aud_vdd1v_en(value); 56 rtos_enable_int(int_level); 57 return SYS_DRV_SUCCESS; 58 } 59 sys_drv_aud_vdd1v5_en(uint32_t value)60uint32_t sys_drv_aud_vdd1v5_en(uint32_t value) 61 { 62 uint32_t int_level = rtos_disable_int(); 63 64 sys_hal_aud_vdd1v5_en(value); 65 rtos_enable_int(int_level); 66 return SYS_DRV_SUCCESS; 67 } 68 sys_drv_aud_mic1_en(uint32_t value)69uint32_t sys_drv_aud_mic1_en(uint32_t value) 70 { 71 uint32_t int_level = rtos_disable_int(); 72 73 sys_hal_aud_mic1_en(value); 74 rtos_enable_int(int_level); 75 return SYS_DRV_SUCCESS; 76 } 77 sys_drv_aud_mic2_en(uint32_t value)78uint32_t sys_drv_aud_mic2_en(uint32_t value) 79 { 80 uint32_t int_level = rtos_disable_int(); 81 82 sys_hal_aud_mic2_en(value); 83 rtos_enable_int(int_level); 84 return SYS_DRV_SUCCESS; 85 } 86 sys_drv_aud_audpll_en(uint32_t value)87uint32_t sys_drv_aud_audpll_en(uint32_t value) 88 { 89 uint32_t int_level = rtos_disable_int(); 90 91 sys_hal_aud_audpll_en(value); 92 rtos_enable_int(int_level); 93 return SYS_DRV_SUCCESS; 94 } 95 sys_drv_aud_aud_en(uint32_t value)96uint32_t sys_drv_aud_aud_en(uint32_t value) 97 { 98 uint32_t int_level = rtos_disable_int(); 99 100 sys_hal_aud_aud_en(value); 101 rtos_enable_int(int_level); 102 return SYS_DRV_SUCCESS; 103 } 104 sys_drv_aud_dacdrv_en(uint32_t value)105uint32_t sys_drv_aud_dacdrv_en(uint32_t value) 106 { 107 uint32_t int_level = rtos_disable_int(); 108 109 sys_hal_aud_dacdrv_en(value); 110 rtos_enable_int(int_level); 111 return SYS_DRV_SUCCESS; 112 } 113 sys_drv_aud_bias_en(uint32_t value)114uint32_t sys_drv_aud_bias_en(uint32_t value) 115 { 116 uint32_t int_level = rtos_disable_int(); 117 118 sys_hal_aud_bias_en(value); 119 rtos_enable_int(int_level); 120 return SYS_DRV_SUCCESS; 121 } 122 sys_drv_aud_dacr_en(uint32_t value)123uint32_t sys_drv_aud_dacr_en(uint32_t value) 124 { 125 uint32_t int_level = rtos_disable_int(); 126 127 sys_hal_aud_dacr_en(value); 128 rtos_enable_int(int_level); 129 return SYS_DRV_SUCCESS; 130 } 131 sys_drv_aud_dacl_en(uint32_t value)132uint32_t sys_drv_aud_dacl_en(uint32_t value) 133 { 134 uint32_t int_level = rtos_disable_int(); 135 136 sys_hal_aud_dacl_en(value); 137 rtos_enable_int(int_level); 138 return SYS_DRV_SUCCESS; 139 } 140 sys_drv_aud_diffen_en(uint32_t value)141uint32_t sys_drv_aud_diffen_en(uint32_t value) 142 { 143 uint32_t int_level = rtos_disable_int(); 144 145 sys_hal_aud_diffen_en(value); 146 rtos_enable_int(int_level); 147 return SYS_DRV_SUCCESS; 148 } 149 sys_drv_aud_rvcmd_en(uint32_t value)150uint32_t sys_drv_aud_rvcmd_en(uint32_t value) 151 { 152 uint32_t int_level = rtos_disable_int(); 153 154 sys_hal_aud_rvcmd_en(value); 155 rtos_enable_int(int_level); 156 return SYS_DRV_SUCCESS; 157 } 158 sys_drv_aud_lvcmd_en(uint32_t value)159uint32_t sys_drv_aud_lvcmd_en(uint32_t value) 160 { 161 uint32_t int_level = rtos_disable_int(); 162 163 sys_hal_aud_lvcmd_en(value); 164 rtos_enable_int(int_level); 165 return SYS_DRV_SUCCESS; 166 } 167 sys_drv_aud_micbias1v_en(uint32_t value)168uint32_t sys_drv_aud_micbias1v_en(uint32_t value) 169 { 170 uint32_t int_level = rtos_disable_int(); 171 172 sys_hal_aud_micbias1v_en(value); 173 rtos_enable_int(int_level); 174 return SYS_DRV_SUCCESS; 175 } 176 sys_drv_aud_micbias_trim_set(uint32_t value)177uint32_t sys_drv_aud_micbias_trim_set(uint32_t value) 178 { 179 uint32_t int_level = rtos_disable_int(); 180 181 sys_hal_aud_micbias_trim_set(value); 182 rtos_enable_int(int_level); 183 return SYS_DRV_SUCCESS; 184 } 185 sys_drv_aud_mic_rst_set(uint32_t value)186uint32_t sys_drv_aud_mic_rst_set(uint32_t value) 187 { 188 uint32_t int_level = rtos_disable_int(); 189 190 sys_hal_aud_mic_rst_set(value); 191 rtos_enable_int(int_level); 192 return SYS_DRV_SUCCESS; 193 } 194 sys_drv_aud_mic1_gain_set(uint32_t value)195uint32_t sys_drv_aud_mic1_gain_set(uint32_t value) 196 { 197 uint32_t int_level = rtos_disable_int(); 198 199 sys_hal_aud_mic1_gain_set(value); 200 rtos_enable_int(int_level); 201 return SYS_DRV_SUCCESS; 202 } 203 sys_drv_aud_mic2_gain_set(uint32_t value)204uint32_t sys_drv_aud_mic2_gain_set(uint32_t value) 205 { 206 uint32_t int_level = rtos_disable_int(); 207 208 sys_hal_aud_mic2_gain_set(value); 209 rtos_enable_int(int_level); 210 return SYS_DRV_SUCCESS; 211 } 212 sys_drv_aud_int_en(uint32_t value)213uint32_t sys_drv_aud_int_en(uint32_t value) 214 { 215 uint32_t int_level = rtos_disable_int(); 216 217 sys_hal_aud_int_en(value); 218 rtos_enable_int(int_level); 219 return SYS_DRV_SUCCESS; 220 } 221 sys_drv_sbc_int_en(uint32_t value)222uint32_t sys_drv_sbc_int_en(uint32_t value) 223 { 224 uint32_t int_level = rtos_disable_int(); 225 226 sys_hal_sbc_int_en(value); 227 228 rtos_enable_int(int_level); 229 return SYS_DRV_SUCCESS; 230 } 231 sys_drv_aud_power_en(uint32_t value)232uint32_t sys_drv_aud_power_en(uint32_t value) 233 { 234 uint32_t int_level = rtos_disable_int(); 235 uint32_t ret = SYS_DRV_FAILURE; 236 ret = sys_amp_res_acquire(); 237 238 sys_hal_aud_power_en(value); 239 240 if(!ret) 241 ret = sys_amp_res_release(); 242 243 rtos_enable_int(int_level); 244 return ret; 245 } 246 247 /** Audio End **/ 248 249 /** I2S Start **/ 250 sys_drv_apll_en(uint32_t value)251uint32_t sys_drv_apll_en(uint32_t value) 252 { 253 uint32_t int_level = rtos_disable_int(); 254 255 sys_hal_apll_en(value); 256 rtos_enable_int(int_level); 257 return SYS_DRV_SUCCESS; 258 } 259 sys_drv_cb_manu_val_set(uint32_t value)260uint32_t sys_drv_cb_manu_val_set(uint32_t value) 261 { 262 uint32_t int_level = rtos_disable_int(); 263 264 sys_hal_cb_manu_val_set(value); 265 rtos_enable_int(int_level); 266 return SYS_DRV_SUCCESS; 267 } 268 sys_drv_ana_reg11_vsel_set(uint32_t value)269uint32_t sys_drv_ana_reg11_vsel_set(uint32_t value) 270 { 271 uint32_t int_level = rtos_disable_int(); 272 273 sys_hal_ana_reg11_vsel_set(value); 274 rtos_enable_int(int_level); 275 return SYS_DRV_SUCCESS; 276 } 277 sys_drv_ana_reg10_sdm_val_set(uint32_t value)278uint32_t sys_drv_ana_reg10_sdm_val_set(uint32_t value) 279 { 280 uint32_t int_level = rtos_disable_int(); 281 282 sys_hal_ana_reg10_sdm_val_set(value); 283 rtos_enable_int(int_level); 284 return SYS_DRV_SUCCESS; 285 } 286 sys_drv_ana_reg11_spi_trigger_set(uint32_t value)287uint32_t sys_drv_ana_reg11_spi_trigger_set(uint32_t value) 288 { 289 uint32_t int_level = rtos_disable_int(); 290 291 sys_hal_ana_reg11_spi_trigger_set(value); 292 rtos_enable_int(int_level); 293 return SYS_DRV_SUCCESS; 294 } 295 296 /** I2S End **/ 297 298 299