1 // Copyright (C) 2022 Beken Corporation
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 #include "sys_hal.h"
16 #include "sys_driver.h"
17
18 //NOTICE:This function is disable the INTERRUPT SOURCE, not the INTERRUPT TARGET.
sys_drv_int_disable(uint32 param)19 int32 sys_drv_int_disable(uint32 param)
20 {
21 int32 ret = 0;
22 uint32_t int_level = rtos_disable_int();
23 ret = sys_hal_int_disable(param);
24 rtos_enable_int(int_level);
25 return ret;
26 }
27
28 //NOTICE:This function is enable the INTERRUPT SOURCE, not the INTERRUPT TARGET.
sys_drv_int_enable(uint32 param)29 int32 sys_drv_int_enable(uint32 param)
30 {
31 int32 ret = 0;
32 uint32_t int_level = rtos_disable_int();
33 ret = sys_hal_int_enable(param);
34 rtos_enable_int(int_level);
35 return ret;
36 }
37
38 //NOTICE:Temp add for BK7256 product which has more then 32 Interrupt sources
sys_drv_int_group2_disable(uint32 param)39 int32 sys_drv_int_group2_disable(uint32 param)
40 {
41 int32 ret = 0;
42 uint32_t int_level = rtos_disable_int();
43 ret = sys_hal_int_group2_disable(param);
44 rtos_enable_int(int_level);
45 return ret;
46 }
47
48 //NOTICE:Temp add for BK7256 product which has more then 32 Interrupt sources
sys_drv_int_group2_enable(uint32 param)49 int32 sys_drv_int_group2_enable(uint32 param)
50 {
51 int32 ret = 0;
52 uint32_t int_level = rtos_disable_int();
53 ret = sys_hal_int_group2_enable(param);
54 rtos_enable_int(int_level);
55 return ret;
56 }
57
sys_drv_fiq_disable(uint32 param)58 int32 sys_drv_fiq_disable(uint32 param)
59 {
60 int32 ret = 0;
61 uint32_t int_level = rtos_disable_int();
62 ret = sys_hal_fiq_disable(param);
63 rtos_enable_int(int_level);
64 return ret;
65 }
66
sys_drv_fiq_enable(uint32 param)67 int32 sys_drv_fiq_enable(uint32 param)
68 {
69 int32 ret = 0;
70 uint32_t int_level = rtos_disable_int();
71 ret = sys_hal_fiq_enable(param);
72 rtos_enable_int(int_level);
73 return ret;
74 }
75
76 // uint32_t int_level = rtos_disable_int();
sys_drv_global_int_disable(uint32 param)77 int32 sys_drv_global_int_disable(uint32 param)
78 {
79 int32 ret = 0;
80
81 return ret;
82 }
83
84 // rtos_enable_int(int_level);
sys_drv_global_int_enable(uint32 param)85 int32 sys_drv_global_int_enable(uint32 param)
86 {
87 int32 ret = 0;
88 uint32_t int_level = rtos_disable_int();
89 ret = sys_hal_global_int_enable(param);
90 rtos_enable_int(int_level);
91 return ret;
92 }
93
94 //NOTICE:INT source status, not INT target status(IRQ,FIQ,NVIC,PLIC,INTC status)
sys_drv_get_int_source_status(void)95 uint32 sys_drv_get_int_source_status(void)
96 {
97 uint32 ret = 0;
98 uint32_t int_level = rtos_disable_int();
99 ret = sys_hal_get_int_status();
100 rtos_enable_int(int_level);
101 return ret;
102 }
103
sys_drv_get_cpu0_gpio_int_st(void)104 uint32_t sys_drv_get_cpu0_gpio_int_st(void)
105 {
106 return sys_hal_get_cpu0_gpio_int_st();
107 }
108
109 //NOTICE:INT source status is read only and can't be set, we'll delete them.
sys_drv_set_int_source_status(uint32 param)110 int32 sys_drv_set_int_source_status(uint32 param)
111 {
112 int32 ret = 0;
113 uint32_t int_level = rtos_disable_int();
114 ret = sys_hal_set_int_status(param);
115 rtos_enable_int(int_level);
116 return ret;
117 }
118
sys_drv_get_fiq_reg_status(void)119 uint32 sys_drv_get_fiq_reg_status(void)
120 {
121 int32 ret = 0;
122 uint32_t int_level = rtos_disable_int();
123 ret = sys_hal_get_fiq_reg_status();
124 rtos_enable_int(int_level);
125 return ret;
126 }
127
sys_drv_set_fiq_reg_status(uint32 param)128 uint32 sys_drv_set_fiq_reg_status(uint32 param)
129 {
130 int32 ret = 0;
131 uint32_t int_level = rtos_disable_int();
132 ret = sys_hal_set_fiq_reg_status(param);
133 rtos_enable_int(int_level);
134 return ret;
135 }
136
sys_drv_get_intr_raw_status(void)137 uint32 sys_drv_get_intr_raw_status(void)
138 {
139 int32 ret = 0;
140 uint32_t int_level = rtos_disable_int();
141 ret = sys_hal_get_intr_raw_status();
142 rtos_enable_int(int_level);
143 return ret;
144 }
145
sys_drv_set_intr_raw_status(uint32 param)146 uint32 sys_drv_set_intr_raw_status(uint32 param)
147 {
148 int32 ret = 0;
149 uint32_t int_level = rtos_disable_int();
150 ret = sys_hal_set_intr_raw_status(param);
151 rtos_enable_int(int_level);
152 return ret;
153 }
154
sys_drv_sadc_int_enable(void)155 void sys_drv_sadc_int_enable(void)
156 {
157 uint32_t int_level = rtos_disable_int();
158 sys_hal_sadc_int_enable();
159 rtos_enable_int(int_level);
160 }
161
sys_drv_sadc_int_disable(void)162 void sys_drv_sadc_int_disable(void)
163 {
164 uint32_t int_level = rtos_disable_int();
165 sys_hal_sadc_int_disable();
166 rtos_enable_int(int_level);
167 }
168
sys_drv_cpu_fft_int_en(uint32_t value)169 uint32_t sys_drv_cpu_fft_int_en(uint32_t value)
170 {
171 uint32_t int_level = rtos_disable_int();
172
173 sys_hal_cpu_fft_int_en(value);
174 rtos_enable_int(int_level);
175 return SYS_DRV_SUCCESS;
176 }
177
178 #if CONFIG_SDIO_V2P0
sys_driver_set_cpu0_sdio_int_en(uint32_t value)179 void sys_driver_set_cpu0_sdio_int_en(uint32_t value)
180 {
181 uint32_t int_level = rtos_disable_int();
182
183 sys_hal_set_cpu0_sdio_int_en(value);
184
185 rtos_enable_int(int_level);
186 }
187
sys_driver_set_cpu1_sdio_int_en(uint32_t value)188 void sys_driver_set_cpu1_sdio_int_en(uint32_t value)
189 {
190 uint32_t int_level = rtos_disable_int();
191
192 sys_hal_set_cpu1_sdio_int_en(value);
193
194 rtos_enable_int(int_level);
195 }
196 #endif
197
sys_drv_i2s_int_en(uint32_t value)198 uint32_t sys_drv_i2s_int_en(uint32_t value)
199 {
200 uint32_t int_level = rtos_disable_int();
201
202 sys_hal_i2s_int_en(value);
203 rtos_enable_int(int_level);
204 return SYS_DRV_SUCCESS;
205 }
206
207