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1 /*
2 // Copyright (C) 2022 Beken Corporation
3  * Licensed under the Apache License, Version 2.0 (the "License");
4  * you may not use this file except in compliance with the License.
5  * You may obtain a copy of the License at
6  *
7  *     http://www.apache.org/licenses/LICENSE-2.0
8  *
9  * Unless required by applicable law or agreed to in writing, software
10  * distributed under the License is distributed on an "AS IS" BASIS,
11  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12  * See the License for the specific language governing permissions and
13  * limitations under the License.
14  */
15 #ifndef _SYS_DRV_H_
16 #define _SYS_DRV_H_
17 
18 #include <common/sys_config.h>
19 #include <common/bk_include.h>
20 #include <soc/soc.h>
21 #include <components/log.h>
22 #include "sys_types.h"
23 #include "sys_hal.h"
24 
25 #define SYS_DRV_DEBUG   0
26 
27 #if SYS_DRV_DEBUG
28 #define SYS_DRV_PRT      os_printf
29 #else
30 #define SYS_DRV_PRT      os_null_printf
31 #endif
32 
33 #define SYSTEM_TAG "system"
34 #define SYSTEM_LOGI(...) BK_LOGI(SYSTEM_TAG, ##__VA_ARGS__)
35 #define SYSTEM_LOGW(...) BK_LOGW(SYSTEM_TAG, ##__VA_ARGS__)
36 #define SYSTEM_LOGE(...) BK_LOGE(SYSTEM_TAG, ##__VA_ARGS__)
37 #define SYSTEM_LOGD(...) BK_LOGD(SYSTEM_TAG, ##__VA_ARGS__)
38 
39 #define SYS_DRV_FAILURE        ((UINT32)-1)
40 #define SYS_DRV_SUCCESS        (0)
41 
42 #define SYS_DRV_PWR_UP        (1)
43 #define SYS_DRV_PWR_DOWN      (0)
44 
45 #define SYS_DRV_CLK_ON        (1)
46 #define SYS_DRV_CLK_OFF       (0)
47 
48 
49 /**  Platform Start **/
50 //Platform
51 
52 /* Platform Misc Start **/
53 void sys_drv_init();
54 /* Platform Misc End **/
55 
56 
57 #if CONFIG_USB    //功能宏开关
58 void sys_drv_usb_power_down(void);
59 
60 void sys_drv_usb_clock_ctrl(bool ctrl, void *arg);
61 
62 uint32_t sys_drv_usb_analog_phy_en(bool ctrl, void *arg);
63 
64 uint32_t sys_drv_usb_analog_speed_en(bool ctrl, void *arg);
65 
66 uint32_t sys_drv_usb_analog_ckmcu_en(bool ctrl, void *arg);
67 
68 void sys_drv_usb_charge_ctrl(bool ctrl, void *arg);
69 
70 void sys_drv_usb_charge_cal(sys_drv_charge_step_t step, void *arg);
71 #endif	//CONFIG_USB
72 
73 /* Platform UART Start **/
74 void sys_drv_uart_select_clock(uart_id_t id, uart_src_clk_t mode);
75 /* Platform UART End **/
76 
77 void sys_drv_pwm_set_clock(uint32_t mode, uint32_t param);
78 
79 void sys_drv_pwm_select_clock(sys_sel_pwm_t num, pwm_src_clk_t mode);
80 
81 void sys_drv_timer_select_clock(sys_sel_timer_t num, timer_src_clk_t mode);
82 
83 void sys_drv_flash_set_dco(void);
84 
85 void sys_drv_flash_set_dpll(void);
86 
87 void sys_drv_flash_cksel(uint32_t value);
88 
89 void sys_drv_flash_set_clk_div(uint32_t value);
90 
91 uint32_t sys_drv_flash_get_clk_sel(void);
92 
93 uint32_t sys_drv_flash_get_clk_div(void);
94 
95 void sys_drv_set_qspi_vddram_voltage(uint32_t param);
96 
97 void sys_drv_set_qspi_io_voltage(uint32_t param);
98 
99 void sys_drv_qspi_clk_sel(uint32_t param);
100 
101 void sys_drv_qspi_set_src_clk_div(uint32_t value);
102 
103 void sys_drv_nmi_wdt_set_clk_div(uint32_t value);
104 
105 uint32_t sys_drv_nmi_wdt_get_clk_div(void);
106 
107 void sys_drv_trng_disckg_set(uint32_t value);
108 
109 #if CONFIG_SDIO_V2P0
110 void sys_driver_set_sdio_clk_en(uint32_t value);
111 
112 void sys_driver_set_cpu0_sdio_int_en(uint32_t value);
113 void sys_driver_set_cpu1_sdio_int_en(uint32_t value);
114 void sys_driver_set_sdio_clk_div(uint32_t value);
115 uint32_t sys_driver_get_sdio_clk_div();
116 void sys_driver_set_sdio_clk_sel(uint32_t value);
117 uint32_t sys_driver_get_sdio_clk_sel();
118 #endif
119 
120 void sys_drv_enter_deep_sleep(void * param);
121 
122 void sys_drv_enter_normal_sleep(uint32_t peri_clk);
123 
124 void sys_drv_enter_normal_wakeup();
125 void sys_drv_enter_low_voltage();
126 
127 /*for low power  function start*/
128 void sys_drv_module_power_ctrl(power_module_name_t module,power_module_state_t power_state);
129 
130 int32 sys_drv_module_power_state_get(power_module_name_t module);
131 
132 void sys_drv_module_RF_power_ctrl (module_name_t module,power_module_state_t power_state);
133 
134 void sys_drv_core_bus_clock_ctrl(high_clock_module_name_t core, uint32_t clksel,uint32_t clkdiv, high_clock_module_name_t bus,uint32_t bus_clksel,uint32_t bus_clkdiv);
135 
136 void sys_drv_cpu0_main_int_ctrl(dev_clk_pwr_ctrl_t clock_state);
137 
138 void sys_drv_cpu1_main_int_ctrl(dev_clk_pwr_ctrl_t clock_state);
139 
140 void sys_drv_set_cpu1_boot_address_offset(uint32_t address_offset);
141 
142 void sys_drv_set_cpu1_reset(uint32_t reset_value);
143 
144 void sys_drv_enable_mac_wakeup_source();
145 void sys_drv_enable_bt_wakeup_source();
146 void sys_drv_all_modules_clk_div_set(clk_div_reg_e reg, uint32_t value);
147 uint32_t sys_drv_all_modules_clk_div_get(clk_div_reg_e reg);
148 void sys_drv_wakeup_interrupt_clear(wakeup_source_t interrupt_source);
149 void sys_drv_wakeup_interrupt_set(wakeup_source_t interrupt_source);
150 void sys_drv_touch_wakeup_enable(uint8_t index);
151 void sys_drv_usb_wakeup_enable(uint8_t index);
152 void sys_drv_cpu_clk_div_set(uint32_t core_index, uint32_t value);
153 uint32_t sys_drv_cpu_clk_div_get(uint32_t core_index);
154 void sys_drv_low_power_hardware_init();
155 int32 sys_drv_lp_vol_set(uint32_t value);
156 uint32_t sys_drv_lp_vol_get();
157 /*for  low power  function end*/
158 uint32 sys_drv_get_device_id(void); // CMD_GET_DEVICE_ID
159 uint32 sys_drv_get_chip_id(void); // CMD_GET_CHIP_ID
160 
161 
162 int32 sys_drv_int_disable(uint32 param);
163 int32 sys_drv_int_enable(uint32 param);
164 int32 sys_drv_int_group2_disable(uint32 param);
165 int32 sys_drv_int_group2_enable(uint32 param);
166 int32 sys_drv_fiq_disable(uint32 param);
167 int32 sys_drv_fiq_enable(uint32 param);
168 int32 sys_drv_global_int_disable(uint32 param);
169 int32 sys_drv_global_int_enable(uint32 param);
170 uint32 sys_drv_get_int_source_status(void);
171 uint32_t sys_drv_get_cpu0_gpio_int_st(void);
172 int32 sys_drv_set_int_source_status(uint32 param);
173 uint32 sys_drv_get_fiq_reg_status(void);
174 uint32 sys_drv_set_fiq_reg_status(uint32 param);
175 uint32 sys_drv_get_intr_raw_status(void);
176 uint32 sys_drv_set_intr_raw_status(uint32 param);
177 int32 sys_drv_set_jtag_mode(uint32 param);
178 uint32 sys_drv_get_jtag_mode(void);
179 
180 /*clock power control start*/
181 void sys_drv_dev_clk_pwr_up(dev_clk_pwr_id_t dev, dev_clk_pwr_ctrl_t power_up);
182 void sys_drv_set_clk_select(dev_clk_select_id_t dev, dev_clk_select_t clk_sel);
183 //DCO divider is valid for all of the peri-devices.
184 void sys_drv_set_dco_div(dev_clk_dco_div_t div);
185 //DCO divider is valid for all of the peri-devices.
186 dev_clk_dco_div_t sys_drv_get_dco_div(void);
187 
188 /*clock power control end*/
189 
190 /*wake up control start*/
191 void sys_drv_arm_wakeup_enable(uint32_t param);
192 void sys_drv_arm_wakeup_disable(uint32_t param);
193 uint32_t sys_drv_get_arm_wakeup(void);
194 /*wake up control end*/
195 
196 void sys_drv_sadc_int_enable(void);
197 void sys_drv_sadc_int_disable(void);
198 void sys_drv_sadc_pwr_up(void);
199 void sys_drv_sadc_pwr_down(void);
200 void sys_drv_en_tempdet(uint32_t value);
201 
202 /**  Platform End **/
203 
204 
205 /**  BT Start **/
206 //BT
207 uint32_t sys_drv_mclk_mux_get(void);
208 uint32_t sys_drv_mclk_div_get(void);
209 void sys_drv_mclk_select(uint32_t value);
210 void sys_drv_mclk_div_set(uint32_t value);
211 
212 void sys_drv_bt_power_ctrl(bool power_up);
213 
214 void sys_drv_bt_clock_ctrl(bool en);
215 void sys_drv_xvr_clock_ctrl(bool en);
216 
217 uint32_t sys_drv_interrupt_status_get(void);
218 void sys_drv_interrupt_status_set(uint32_t value);
219 
220 void sys_drv_btdm_interrupt_ctrl(bool en);
221 void sys_drv_ble_interrupt_ctrl(bool en);
222 void sys_drv_bt_interrupt_ctrl(bool en);
223 
224 void sys_drv_bt_rf_ctrl(bool en);
225 uint32_t sys_drv_bt_rf_status_get(void);
226 
227 void sys_drv_bt_sleep_exit_ctrl(bool en);
228 
229 /**  BT End **/
230 
231 
232 
233 
234 /**  Audio Start **/
235 //Audio
236 /**  Audio End **/
237 
238 
239 /**  Video Start **/
240 /**
241   * @brief	lcd_disp  system config
242   * param1: clk source sel 0:clk_320M      1:clk_480M,
243   * param2: clk_div  F/(1+clkdiv_disp_l+clkdiv_disp_h*2)
244   * param3: int_en eanble lcd cpu int
245   * param4: clk_always_on, BUS_CLK ENABLE,0: bus clock open when module is select,1:bus clock always open,  0 by defult
246   * return none
247   */
248 uint32_t sys_drv_lcd_set(uint8_t clk_src_sel, uint8_t clk_div_l, uint8_t clk_div_h, uint8_t int_en,uint8_t clk_always_on);
249 
250 /**
251   * @brief	lcd clk close and int disable, reg value recover default.
252   * return none
253   */
254 uint32_t  sys_drv_lcd_close(void);
255 
256 /**
257   * @brief	dma2d system config
258   * param1: clk source sel 0:clk_320M	   1:clk_480M,
259   * param2: clk_always_on  ENABLE,0: bus clock open when module is select,1:bus clock always open
260   * param3: int_en eanble lcd cpu int
261   * return none
262   */
263 uint32_t sys_drv_dma2d_set(uint8_t clk_always_on, uint8_t sys_int_en);
264 
265 /**
266   * @brief	jpeg dec system config
267   * param1: clk_always_on  ENABLE,0: bus clock open when module is select,1:bus clock always open
268   * param2: int_en eanble lcd cpu int
269   * return none
270   */
271 uint32_t sys_drv_jpeg_dec_set(uint8_t clk_always_on, uint8_t int_en);
272 
273 /**  Video End **/
274 
275 
276 
277 
278 /**  WIFI Start **/
279 //WIFI
280 
281 //Yantao Add Start
282 //CMD_SCTRL_RESET_SET, CMD_SCTRL_RESET_CLR
283 uint32_t sys_drv_reset_ctrl(uint32_t value);
284 //CMD_SCTRL_MODEM_CORE_RESET
285 uint32_t sys_drv_modem_core_reset(void);
286 //CMD_SCTRL_MPIF_CLK_INVERT
287 uint32_t sys_drv_mpif_invert(void);
288 //CMD_SCTRL_MODEM_SUBCHIP_RESET
289 uint32_t sys_drv_modem_subsys_reset(void);
290 //CMD_SCTRL_MAC_SUBSYS_RESET
291 uint32_t sys_drv_mac_subsys_reset(void);
292 //CMD_SCTRL_USB_SUBSYS_RESET
293 uint32_t sys_drv_usb_subsys_reset(void);
294 //CMD_SCTRL_DSP_SUBSYS_RESET
295 uint32_t sys_drv_dsp_subsys_reset(void);
296 //CMD_SCTRL_MAC_POWERDOWN, CMD_SCTRL_MAC_POWERUP
297 uint32_t sys_drv_mac_power_ctrl(bool power_on);
298 //CMD_SCTRL_MODEM_POWERDOWN, CMD_SCTRL_MODEM_POWERUP
299 uint32_t sys_drv_modem_power_ctrl(bool power_on);\
300 //CMD_BLE_RF_PTA_EN, CMD_BLE_RF_PTA_DIS
301 uint32_t sys_drv_pta_ctrl(bool pta_en);
302 //CMD_SCTRL_MODEM_AHB_CLOCK_DISABLE, CMD_SCTRL_MODEM_AHB_CLOCK_ENABLE
303 uint32_t sys_drv_modem_bus_clk_ctrl(bool clk_en);
304 //CMD_SCTRL_MODEM_CLOCK480M_DISABLE, CMD_SCTRL_MODEM_CLOCK480M_ENABLE
305 uint32_t sys_drv_modem_clk_ctrl(bool clk_en);
306 //CMD_SCTRL_MAC_AHB_CLOCK_DISABLE, CMD_SCTRL_MAC_AHB_CLOCK_ENABLE
307 uint32_t sys_drv_mac_bus_clk_ctrl(bool clk_en);
308 //CMD_SCTRL_MAC_CLOCK480M_DISABLE,CMD_SCTRL_MAC_CLOCK480M_ENABLE
309 uint32_t sys_drv_mac_clk_ctrl(bool clk_en);
310 //CMD_SCTRL_SET_VDD_VALUE
311 uint32_t sys_drv_set_vdd_value(uint32_t param);
312 //CMD_SCTRL_GET_VDD_VALUE
313 uint32_t sys_drv_get_vdd_value(void);
314 //CMD_SCTRL_BLOCK_EN_MUX_SET
315 uint32_t sys_drv_block_en_mux_set(uint32_t param);
316 //enable MAC and PHY interrupt
317 uint32_t sys_drv_enable_mac_gen_int(void);
318 uint32_t sys_drv_enable_mac_prot_int(void);
319 uint32_t sys_drv_enable_mac_tx_trigger_int(void);
320 uint32_t sys_drv_enable_mac_rx_trigger_int(void);
321 uint32_t sys_drv_enable_mac_txrx_misc_int(void);
322 uint32_t sys_drv_enable_mac_txrx_timer_int(void);
323 uint32_t sys_drv_enable_modem_int(void);
324 uint32_t sys_drv_enable_modem_rc_int(void);
325 
326 
327 //Yantao Add End
328 
329 /**  Audio Start  **/
330 uint32_t  sys_drv_aud_select_clock(uint32_t value);
331 uint32_t  sys_drv_aud_clock_en(uint32_t value);
332 uint32_t sys_drv_aud_vdd1v_en(uint32_t value);
333 uint32_t sys_drv_aud_vdd1v5_en(uint32_t value);
334 uint32_t sys_drv_aud_mic1_en(uint32_t value);
335 uint32_t sys_drv_aud_mic2_en(uint32_t value);
336 uint32_t sys_drv_aud_audpll_en(uint32_t value);
337 uint32_t sys_drv_aud_aud_en(uint32_t value);
338 uint32_t sys_drv_aud_dacdrv_en(uint32_t value);
339 uint32_t sys_drv_aud_bias_en(uint32_t value);
340 uint32_t sys_drv_aud_dacr_en(uint32_t value);
341 uint32_t sys_drv_aud_dacl_en(uint32_t value);
342 uint32_t sys_drv_aud_diffen_en(uint32_t value);
343 uint32_t sys_drv_aud_rvcmd_en(uint32_t value);
344 uint32_t sys_drv_aud_lvcmd_en(uint32_t value);
345 uint32_t sys_drv_aud_micbias1v_en(uint32_t value);
346 uint32_t sys_drv_aud_micbias_trim_set(uint32_t value);
347 uint32_t sys_drv_aud_mic_rst_set(uint32_t value);
348 uint32_t sys_drv_aud_mic1_gain_set(uint32_t value);
349 uint32_t sys_drv_aud_mic2_gain_set(uint32_t value);
350 uint32_t sys_drv_aud_int_en(uint32_t value);
351 uint32_t sys_drv_sbc_int_en(uint32_t value);
352 uint32_t sys_drv_aud_power_en(uint32_t value);
353 
354 /**  Audio End  **/
355 
356 /**  FFT Start  **/
357 uint32_t sys_drv_fft_disckg_set(uint32_t value);
358 uint32_t sys_drv_cpu_fft_int_en(uint32_t value);
359 /**  FFT End  **/
360 
361 /**  I2S Start  **/
362 uint32_t  sys_drv_i2s_select_clock(uint32_t value);
363 uint32_t  sys_drv_i2s_clock_en(uint32_t value);
364 uint32_t sys_drv_i2s_disckg_set(uint32_t value);
365 uint32_t sys_drv_i2s_int_en(uint32_t value);
366 uint32_t sys_drv_apll_en(uint32_t value);
367 uint32_t sys_drv_cb_manu_val_set(uint32_t value);
368 uint32_t sys_drv_ana_reg11_vsel_set(uint32_t value);
369 uint32_t sys_drv_ana_reg10_sdm_val_set(uint32_t value);
370 uint32_t sys_drv_ana_reg11_spi_trigger_set(uint32_t value);
371 /**  I2S End  **/
372 
373 
374 /**  Touch Start **/
375 uint32_t sys_drv_touch_power_down(uint32_t enable);
376 uint32_t sys_drv_touch_sensitivity_level_set(uint32_t value);
377 uint32_t sys_drv_touch_scan_mode_enable(uint32_t enable);
378 uint32_t sys_drv_touch_detect_threshold_set(uint32_t value);
379 uint32_t sys_drv_touch_detect_range_set(uint32_t value);
380 uint32_t sys_drv_touch_calib_enable(uint32_t enable);
381 uint32_t sys_drv_touch_manul_mode_calib_value_set(uint32_t value);
382 uint32_t sys_drv_touch_manul_mode_enable(uint32_t enable);
383 uint32_t sys_drv_touch_scan_mode_chann_set(uint32_t value);
384 uint32_t sys_drv_touch_int_enable(uint32_t value);
385 
386 /**  Touch End **/
387 
388 /**  jPEG Start **/
389 uint32_t sys_drv_mclk_mux_set(uint32_t value);
390 uint32_t sys_drv_set_jpeg_clk_sel(uint32_t value);
391 uint32_t sys_drv_set_clk_div_mode1_clkdiv_jpeg(uint32_t value);
392 uint32_t sys_drv_set_jpeg_disckg(uint32_t value);
393 uint32_t sys_drv_set_cpu_clk_div_mode1_clkdiv_bus(uint32_t value);
394 uint32_t sys_drv_video_power_en(uint32_t value);
395 uint32_t sys_drv_set_auxs(uint32_t cksel, uint32_t ckdiv);
396 
397 /**  jPEG End **/
398 
399 /**  psram Start **/
400 uint32_t sys_drv_psram_volstage_sel(uint32_t value);
401 uint32_t sys_drv_psram_xtall_osc_enable(uint32_t value);
402 uint32_t sys_drv_psram_dco_enable(uint32_t value);
403 uint32_t sys_drv_psram_dpll_enable(uint32_t value);
404 uint32_t sys_drv_psram_ldo_enable(uint32_t value);
405 uint32_t sys_drv_psram_clk_sel(uint32_t value);
406 uint32_t sys_drv_psram_set_clkdiv(uint32_t value);
407 uint32_t sys_drv_psram_power_enable(void);
408 uint32_t sys_drv_psram_psldo_vsel(uint32_t value);
409 
410 /**  psram End **/
411 
412 uint32_t sys_drv_cali_dpll(uint32_t param);
413 uint32_t sys_drv_bias_reg_set(uint32_t param);
414 uint32_t sys_drv_bias_reg_clean(uint32_t param);
415 uint32_t sys_drv_bias_reg_read(void);
416 uint32_t sys_drv_bias_reg_write(uint32_t param);
417 #if 0
418 uint32_t sys_drv_bias_get_cali_out(void);
419 #endif
420 uint32_t sys_drv_analog_reg4_bits_or(uint32_t param);
421 uint32_t sys_drv_analog_ctrl9_real_set(uint32_t param);
422 uint32_t sys_drv_analog_set_xtalh_ctune(uint32_t param);
423 uint32_t sys_drv_analog_get_xtalh_ctune(void);
424 uint32_t sys_drv_analog_reg1_set(uint32_t param);
425 uint32_t sys_drv_analog_reg2_set(uint32_t param);
426 uint32_t sys_drv_analog_reg3_set(uint32_t param);
427 uint32_t sys_drv_analog_reg4_set(uint32_t param);
428 uint32_t sys_drv_analog_reg6_set(uint32_t param);
429 uint32_t sys_drv_analog_reg7_set(uint32_t param);
430 uint32_t sys_drv_analog_reg1_get(void);
431 uint32_t sys_drv_analog_reg2_get(void);
432 uint32_t sys_drv_analog_reg4_get(void);
433 uint32_t sys_drv_analog_reg6_get(void);
434 uint32_t sys_drv_analog_reg7_get(void);
435 uint32_t sys_drv_analog_reg12_set(uint32_t param);
436 uint32_t sys_drv_analog_reg13_set(uint32_t param);
437 uint32_t sys_drv_analog_reg14_set(uint32_t param);
438 uint32_t sys_drv_analog_reg15_set(uint32_t param);
439 uint32_t sys_drv_analog_reg16_set(uint32_t param);
440 uint32_t sys_drv_analog_reg17_set(uint32_t param);
441 uint32_t sys_drv_get_bgcalm(void);
442 uint32_t sys_drv_set_bgcalm(uint32_t param);
443 uint32_t sys_drv_set_dpll_for_i2s(void);
444 uint32_t sys_drv_set_gadc_ten(uint32_t param);
445 void sys_drv_analog_set(analog_reg_t reg, uint32_t value);
446 uint32_t sys_drv_analog_get(analog_reg_t reg);
447 void sys_drv_set_ana_trxt_tst_enable(uint32_t value);
448 void sys_drv_set_ana_scal_en(uint32_t value);
449 void sys_drv_set_ana_gadc_buf_ictrl(uint32_t value);
450 void sys_drv_set_ana_gadc_cmp_ictrl(uint32_t value);
451 void sys_drv_set_ana_pwd_gadc_buf(uint32_t value);
452 void sys_drv_set_ana_vref_sel(uint32_t value);
453 void sys_drv_set_ana_cb_cal_manu(uint32_t value);
454 void sys_drv_set_ana_cb_cal_trig(uint32_t value);
455 void sys_drv_set_ana_cb_cal_manu_val(uint32_t value);
456 void sys_drv_set_ana_vlsel_ldodig(uint32_t value);
457 void sys_drv_set_ana_vhsel_ldodig(uint32_t value);
458 void sys_drv_set_ana_vctrl_sysldo(uint32_t value);
459 void sys_drv_set_ana_vtempsel(uint32_t value);
460 
461 uint32_t sys_drv_get_cpu_storage_connect_op_select_flash_sel(void);
462 void sys_drv_set_cpu_storage_connect_op_select_flash_sel(uint32_t value);
463 
464 /**  WIFI End **/
465 
466 
467 
468 
469 /**  Misc Start **/
470 //Misc
471 /**  Misc End **/
472 
473 
474 #endif //_SYS_DRV_H_
475 // eof
476 
477