1 /* 2 * 3 * SPDX-License-Identifier: GPL-2.0 4 * 5 * Copyright (C) 2011-2018 ARM or its affiliates 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; version 2. 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * for more details. 14 * You should have received a copy of the GNU General Public License along 15 * with this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 17 * 18 */ 19 20 #ifndef __SYSTEM_AM_MD_H__ 21 #define __SYSTEM_AM_MD_H__ 22 #include <linux/module.h> 23 #include <linux/of.h> 24 #include <linux/slab.h> 25 #include "acamera_command_api.h" 26 #include "acamera_firmware_settings.h" 27 #include "acamera.h" 28 #include "acamera_fw.h" 29 #include <linux/kfifo.h> 30 #include <linux/ioport.h> 31 32 #define ISP_MD_REG_START 0xfe023e00 33 34 #define MD_TOP_GCLK ISP_MD_REG_START + 4*0x0 // 35 //Bit 31: 0 reg_md_gclk // unsigned , RW, default = 0 clock gate control 36 #define MD_TOP_CTRL ISP_MD_REG_START + 4*0x1 // 37 //Bit 31: 0 reg_md_top_ctrl // unsigned , RW, default = 32'h204 md top ntrol 38 #define MD_WR_CTRL0 ISP_MD_REG_START + 4*0x2 // 39 //Bit 31 reg_wr_axi_wr_en // unsigned , RW, default = 1 axi wr enable 40 //Bit 30 reg_wr_axi_req_en // unsigned , RW, default = 1 axi request enable 41 //Bit 29 reg_wr_axi_bypass // unsigned , RW, default = 0 bypass axi wr 42 //Bit 28 reg_wr_frame_int // unsigned , RW, default = 0 init wr frame 43 //Bit 27:24 reserved 44 //Bit 23: 0 reg_wr_total_size // unsigned , RW, default = 57600 pixels hsize * vsize 45 #define MD_WR_CTRL1 ISP_MD_REG_START + 4*0x3 // 46 //Bit 31: 0 reg_wr_base_addr // unsigned , RW, default = 32'h80000000 wr axi base address 47 #define MD_WR_CTRL2 ISP_MD_REG_START + 4*0x4 // 48 //Bit 31:23 reserved 49 //Bit 22:20 reg_wr_burst_lens // unsigned , RW, default = 2 burst_lens limiation, burst_size: 0: 1x128, 1: 2x128, 2~3: 4x128 50 //Bit 19:16 reg_wr_req_th // unsigned , RW, default = 4 fifo depth req_th * 8 *128 bits in fifo. 51 //Bit 15: 0 reg_wr_urgent_ctrl // unsigned , RW, default = 0 urgent control 52 #define MD_WR_CTRL3 ISP_MD_REG_START + 4*0x5 // 53 //Bit 31:24 reg_wr_awid // unsigned , RW, default = 0 wr id 54 //Bit 23:21 reg_wr_awprot // unsigned , RW, default = 0 awprot for security control 55 //Bit 20: 0 reserved 56 #define MD_RO_WR_ST0 ISP_MD_REG_START + 4*0x6 // 57 //Bit 31: 0 ro_wr_st0 // unsigned , RW, default = 0 58 #define MD_RO_WR_ST1 ISP_MD_REG_START + 4*0x7 // 59 //Bit 31: 0 ro_wr_st1 // unsigned , RW, default = 0 60 #define MD_RO_WR_ST2 ISP_MD_REG_START + 4*0x8 // 61 //Bit 31: 0 ro_wr_st2 // unsigned , RW, default = 0 62 #define MD_RD_CTRL0 ISP_MD_REG_START + 4*0x9 // 63 //Bit 31 reg_rd_axi_rd_en // unsigned , RW, default = 1 axi rd enable 64 //Bit 30 reg_rd_axi_req_en // unsigned , RW, default = 1 axi request enable 65 //Bit 29:24 reserved 66 //Bit 23: 0 reg_rd_total_size // unsigned , RW, default = 57600 total size hsize*vsize, <= 1024*1024 67 #define MD_RD_CTRL1 ISP_MD_REG_START + 4*0xa // 68 //Bit 31: 0 reg_rd_base_addr // unsigned , RW, default = 32'h80000000 69 #define MD_RD_CTRL2 ISP_MD_REG_START + 4*0xb // 70 //Bit 31:23 reserved 71 //Bit 22:20 reg_rd_burst_lens // unsigned , RW, default = 2 burst_lens limiation, burst_size: 0: 1x128, 1: 2x128, 2~3: 4x128 72 //Bit 19:16 reg_rd_req_th // unsigned , RW, default = 4 fifo depth req_th * 8 *128 bits in fifo. 73 //Bit 15: 0 reg_rd_urgent_ctrl // unsigned , RW, default = 0 urgent control 74 #define MD_RD_CTRL3 ISP_MD_REG_START + 4*0xc // 75 //Bit 31:24 reg_rd_arid // unsigned , RW, default = 0 wr id 76 //Bit 23:21 reg_rd_arprot // unsigned , RW, default = 0 awprot for security control 77 //Bit 20: 0 reserved 78 #define MD_RO_RD_ST0 ISP_MD_REG_START + 4*0xd // 79 //Bit 31: 0 ro_rd_st0 // unsigned , RW, default = 0 80 #define MD_RO_RD_ST1 ISP_MD_REG_START + 4*0xe // 81 //Bit 31: 0 ro_rd_st1 // unsigned , RW, default = 0 82 #define MD_INPUT_CTRL0 ISP_MD_REG_START + 4*0xf // 83 //Bit 31 reg_md_enable // unsigned , RW, default = 1 lp motion detection enable, 0: disable; 1: enable 84 //Bit 30 reg_md_raw_xphase_ofst // unsigned , RW, default = 0 horizontal phase of the raw data, 0: start wz R-col (RGGB or GBRG); 1: start wz B-col (GRBG or BGGR) 85 //Bit 29 reg_md_raw_yphase_ofst // unsigned , RW, default = 0 vertical phase of the raw data, 0: start wz R-row (RGGB or GRBG); 1: start wz B-row (GRBG or BGGR) 86 //Bit 28 reg_md_is_on_raw // unsigned , RW, default = 1 the md_sel is on raw data, set together with md_sel. 0: YUV/RGB; 1:RAW 87 //Bit 27:24 reg_md_input_sel // unsigned , RW, default = 1 data selection for the lp motion detection. 0: raw sensor input; 1: raw WDR stitch; 2:raw fed_out(nr_in); 3:raw mirror_in; 4�� RGB after dms; 5: IRout; 6:RGB/YUV after gamma; 7: fe_o yuv bypass , default=1 88 //Bit 23:20 reg_md_input_ls // unsigned , RW, default = 0 E domain data left shift bit num to align with u20 Odomain data and will clip to u10 by droping 10lsb, e.g. yuv is u12, then ls = 8; 89 //Bit 19: 0 reserved 90 #define MD_INPUT_SIZE ISP_MD_REG_START + 4*0x10 // 91 //Bit 31:28 reserved 92 //Bit 27:16 reg_md_input_xsize // unsigned , RW, default = 1920 xsize of the input in pixels, set to image xsize 93 //Bit 15:12 reserved 94 //Bit 11: 0 reg_md_input_ysize // unsigned , RW, default = 1080 ysize of the input in pixels, set to image ysize 95 #define MD_WINXY_0 ISP_MD_REG_START + 4*0x11 // 96 //Bit 31:28 reserved 97 //Bit 27:16 reg_md_inpc_winxxyy_0 // unsigned , RW, default = 0 input combined window for processing. 98 //Bit 15:12 reserved 99 //Bit 11: 0 reg_md_inpc_winxxyy_1 // unsigned , RW, default = 960 input combined window for processing. 100 #define MD_WINXY_1 ISP_MD_REG_START + 4*0x12 // 101 //Bit 31:28 reserved 102 //Bit 27:16 reg_md_inpc_winxxyy_2 // unsigned , RW, default = 0 input combined window for processing. 103 //Bit 15:12 reserved 104 //Bit 11: 0 reg_md_inpc_winxxyy_3 // unsigned , RW, default = 540 input combined window for processing. 105 #define MD_RGGB_OFSET_0 ISP_MD_REG_START + 4*0x13 // 106 //Bit 31:20 reserved 107 //Bit 19: 0 reg_md_rggb_ofset_0 // signed , RW, default = 0 ofset to the components, same as the ISP mission mode ofset 108 #define MD_RGGB_OFSET_1 ISP_MD_REG_START + 4*0x14 // 109 //Bit 31:20 reserved 110 //Bit 19: 0 reg_md_rggb_ofset_1 // signed , RW, default = 0 ofset to the components, same as the ISP mission mode ofset 111 #define MD_RGGB_OFSET_2 ISP_MD_REG_START + 4*0x15 // 112 //Bit 31:20 reserved 113 //Bit 19: 0 reg_md_rggb_ofset_2 // signed , RW, default = 0 ofset to the components, same as the ISP mission mode ofset 114 #define MD_RGGB_OFSET_3 ISP_MD_REG_START + 4*0x16 // 115 //Bit 31:20 reserved 116 //Bit 19: 0 reg_md_rggb_ofset_3 // signed , RW, default = 0 ofset to the components, same as the ISP mission mode ofset 117 #define MD_RGGB_GAIN_0 ISP_MD_REG_START + 4*0x17 // 118 //Bit 31:28 reserved 119 //Bit 27:16 reg_md_rggb_gain_0 // unsigned , RW, default = 1024 gain to different channel, normalize to 1024 as "1.0" 120 //Bit 15:12 reserved 121 //Bit 11: 0 reg_md_rggb_gain_1 // unsigned , RW, default = 1024 gain to different channel, normalize to 1024 as "1.0" 122 #define MD_RGGB_GAIN_1 ISP_MD_REG_START + 4*0x18 // 123 //Bit 31:28 reserved 124 //Bit 27:16 reg_md_rggb_gain_2 // unsigned , RW, default = 1024 gain to different channel, normalize to 1024 as "1.0" 125 //Bit 15:12 reserved 126 //Bit 11: 0 reg_md_rggb_gain_3 // unsigned , RW, default = 1024 gain to different channel, normalize to 1024 as "1.0" 127 #define MD_RGGB_COEF ISP_MD_REG_START + 4*0x19 // 128 //Bit 31:24 reg_md_bld_coefs_0 // unsigned , RW, default = 32 blender coef of the components to Y, normalize to 128 as "1" 129 //Bit 23:16 reg_md_bld_coefs_1 // unsigned , RW, default = 32 blender coef of the components to Y, normalize to 128 as "1" 130 //Bit 15: 8 reg_md_bld_coefs_2 // unsigned , RW, default = 32 blender coef of the components to Y, normalize to 128 as "1" 131 //Bit 7: 0 reg_md_bld_coefs_3 // unsigned , RW, default = 32 blender coef of the components to Y, normalize to 128 as "1" 132 #define MD_COMB_EOTF_0 ISP_MD_REG_START + 4*0x1a // 133 //Bit 31:22 reg_md_comb_eotf_0 // unsigned , RW, default = 0 piec wise lut 134 //Bit 21:12 reg_md_comb_eotf_1 // unsigned , RW, default = 0 piec wise lut 135 //Bit 11: 2 reg_md_comb_eotf_2 // unsigned , RW, default = 1 piec wise lut 136 //Bit 1: 0 reserved 137 #define MD_COMB_EOTF_1 ISP_MD_REG_START + 4*0x1b // 138 //Bit 31:22 reg_md_comb_eotf_3 // unsigned , RW, default = 1 piec wise lut 139 //Bit 21:12 reg_md_comb_eotf_4 // unsigned , RW, default = 1 piec wise lut 140 //Bit 11: 2 reg_md_comb_eotf_5 // unsigned , RW, default = 1 piec wise lut 141 //Bit 1: 0 reserved 142 #define MD_COMB_EOTF_2 ISP_MD_REG_START + 4*0x1c // 143 //Bit 31:22 reg_md_comb_eotf_6 // unsigned , RW, default = 2 piec wise lut 144 //Bit 21:12 reg_md_comb_eotf_7 // unsigned , RW, default = 2 piec wise lut 145 //Bit 11: 2 reg_md_comb_eotf_8 // unsigned , RW, default = 2 piec wise lut 146 //Bit 1: 0 reserved 147 #define MD_COMB_EOTF_3 ISP_MD_REG_START + 4*0x1d // 148 //Bit 31:22 reg_md_comb_eotf_9 // unsigned , RW, default = 3 piec wise lut 149 //Bit 21:12 reg_md_comb_eotf_10 // unsigned , RW, default = 3 piec wise lut 150 //Bit 11: 2 reg_md_comb_eotf_11 // unsigned , RW, default = 4 piec wise lut 151 //Bit 1: 0 reserved 152 #define MD_COMB_EOTF_4 ISP_MD_REG_START + 4*0x1e // 153 //Bit 31:22 reg_md_comb_eotf_12 // unsigned , RW, default = 4 piec wise lut 154 //Bit 21:12 reg_md_comb_eotf_13 // unsigned , RW, default = 5 piec wise lut 155 //Bit 11: 2 reg_md_comb_eotf_14 // unsigned , RW, default = 6 piec wise lut 156 //Bit 1: 0 reserved 157 #define MD_COMB_EOTF_5 ISP_MD_REG_START + 4*0x1f // 158 //Bit 31:22 reg_md_comb_eotf_15 // unsigned , RW, default = 7 piec wise lut 159 //Bit 21:12 reg_md_comb_eotf_16 // unsigned , RW, default = 8 piec wise lut 160 //Bit 11: 2 reg_md_comb_eotf_17 // unsigned , RW, default = 10 piec wise lut 161 //Bit 1: 0 reserved 162 #define MD_COMB_EOTF_6 ISP_MD_REG_START + 4*0x20 // 163 //Bit 31:22 reg_md_comb_eotf_18 // unsigned , RW, default = 12 piec wise lut 164 //Bit 21:12 reg_md_comb_eotf_19 // unsigned , RW, default = 14 piec wise lut 165 //Bit 11: 2 reg_md_comb_eotf_20 // unsigned , RW, default = 16 piec wise lut 166 //Bit 1: 0 reserved 167 #define MD_COMB_EOTF_7 ISP_MD_REG_START + 4*0x21 // 168 //Bit 31:22 reg_md_comb_eotf_21 // unsigned , RW, default = 20 piec wise lut 169 //Bit 21:12 reg_md_comb_eotf_22 // unsigned , RW, default = 24 piec wise lut 170 //Bit 11: 2 reg_md_comb_eotf_23 // unsigned , RW, default = 28 piec wise lut 171 //Bit 1: 0 reserved 172 #define MD_COMB_EOTF_8 ISP_MD_REG_START + 4*0x22 // 173 //Bit 31:22 reg_md_comb_eotf_24 // unsigned , RW, default = 32 piec wise lut 174 //Bit 21:12 reg_md_comb_eotf_25 // unsigned , RW, default = 40 piec wise lut 175 //Bit 11: 2 reg_md_comb_eotf_26 // unsigned , RW, default = 48 piec wise lut 176 //Bit 1: 0 reserved 177 #define MD_COMB_EOTF_9 ISP_MD_REG_START + 4*0x23 // 178 //Bit 31:22 reg_md_comb_eotf_27 // unsigned , RW, default = 56 piec wise lut 179 //Bit 21:12 reg_md_comb_eotf_28 // unsigned , RW, default = 64 piec wise lut 180 //Bit 11: 2 reg_md_comb_eotf_29 // unsigned , RW, default = 80 piec wise lut 181 //Bit 1: 0 reserved 182 #define MD_COMB_EOTF_10 ISP_MD_REG_START + 4*0x24 // 183 //Bit 31:22 reg_md_comb_eotf_30 // unsigned , RW, default = 96 piec wise lut 184 //Bit 21:12 reg_md_comb_eotf_31 // unsigned , RW, default = 112 piec wise lut 185 //Bit 11: 2 reg_md_comb_eotf_32 // unsigned , RW, default = 128 piec wise lut 186 //Bit 1: 0 reserved 187 #define MD_COMB_EOTF_11 ISP_MD_REG_START + 4*0x25 // 188 //Bit 31:22 reg_md_comb_eotf_33 // unsigned , RW, default = 160 piec wise lut 189 //Bit 21:12 reg_md_comb_eotf_34 // unsigned , RW, default = 192 piec wise lut 190 //Bit 11: 2 reg_md_comb_eotf_35 // unsigned , RW, default = 223 piec wise lut 191 //Bit 1: 0 reserved 192 #define MD_COMB_EOTF_12 ISP_MD_REG_START + 4*0x26 // 193 //Bit 31:22 reg_md_comb_eotf_36 // unsigned , RW, default = 256 piec wise lut 194 //Bit 21:12 reg_md_comb_eotf_37 // unsigned , RW, default = 288 piec wise lut 195 //Bit 11: 2 reg_md_comb_eotf_38 // unsigned , RW, default = 320 piec wise lut 196 //Bit 1: 0 reserved 197 #define MD_COMB_EOTF_13 ISP_MD_REG_START + 4*0x27 // 198 //Bit 31:22 reg_md_comb_eotf_39 // unsigned , RW, default = 352 piec wise lut 199 //Bit 21:12 reg_md_comb_eotf_40 // unsigned , RW, default = 384 piec wise lut 200 //Bit 11: 2 reg_md_comb_eotf_41 // unsigned , RW, default = 416 piec wise lut 201 //Bit 1: 0 reserved 202 #define MD_COMB_EOTF_14 ISP_MD_REG_START + 4*0x28 // 203 //Bit 31:22 reg_md_comb_eotf_42 // unsigned , RW, default = 448 piec wise lut 204 //Bit 21:12 reg_md_comb_eotf_43 // unsigned , RW, default = 480 piec wise lut 205 //Bit 11: 2 reg_md_comb_eotf_44 // unsigned , RW, default = 512 piec wise lut 206 //Bit 1: 0 reserved 207 #define MD_COMB_EOTF_15 ISP_MD_REG_START + 4*0x29 // 208 //Bit 31:22 reg_md_comb_eotf_45 // unsigned , RW, default = 544 piec wise lut 209 //Bit 21:12 reg_md_comb_eotf_46 // unsigned , RW, default = 576 piec wise lut 210 //Bit 11: 2 reg_md_comb_eotf_47 // unsigned , RW, default = 608 piec wise lut 211 //Bit 1: 0 reserved 212 #define MD_COMB_EOTF_16 ISP_MD_REG_START + 4*0x2a // 213 //Bit 31:22 reg_md_comb_eotf_48 // unsigned , RW, default = 640 piec wise lut 214 //Bit 21:12 reg_md_comb_eotf_49 // unsigned , RW, default = 672 piec wise lut 215 //Bit 11: 2 reg_md_comb_eotf_50 // unsigned , RW, default = 704 piec wise lut 216 //Bit 1: 0 reserved 217 #define MD_COMB_EOTF_17 ISP_MD_REG_START + 4*0x2b // 218 //Bit 31:22 reg_md_comb_eotf_51 // unsigned , RW, default = 736 piec wise lut 219 //Bit 21:12 reg_md_comb_eotf_52 // unsigned , RW, default = 768 piec wise lut 220 //Bit 11: 2 reg_md_comb_eotf_53 // unsigned , RW, default = 800 piec wise lut 221 //Bit 1: 0 reserved 222 #define MD_COMB_EOTF_18 ISP_MD_REG_START + 4*0x2c // 223 //Bit 31:22 reg_md_comb_eotf_54 // unsigned , RW, default = 832 piec wise lut 224 //Bit 21:12 reg_md_comb_eotf_55 // unsigned , RW, default = 864 piec wise lut 225 //Bit 11: 2 reg_md_comb_eotf_56 // unsigned , RW, default = 896 piec wise lut 226 //Bit 1: 0 reserved 227 #define MD_COMB_EOTF_19 ISP_MD_REG_START + 4*0x2d // 228 //Bit 31:22 reg_md_comb_eotf_57 // unsigned , RW, default = 928 piec wise lut 229 //Bit 21:12 reg_md_comb_eotf_58 // unsigned , RW, default = 960 piec wise lut 230 //Bit 11: 2 reg_md_comb_eotf_59 // unsigned , RW, default = 992 piec wise lut 231 //Bit 1: 0 reserved 232 #define MD_COMB_EOTF_20 ISP_MD_REG_START + 4*0x2e // 233 //Bit 31:10 reserved 234 //Bit 9: 0 reg_md_comb_eotf_60 // unsigned , RW, default = 1023 piec wise lut 235 #define MD_EOTF ISP_MD_REG_START + 4*0x2f // 236 //Bit 31: 2 reserved 237 //Bit 1 reg_md_bld_use_max // unsigned , RW, default = 0 use max of the components for the blender, 0: no max, 1:max (more sensitive) 238 //Bit 0 reg_md_eotf_en // unsigned , RW, default = 1 piece wise lut enable 239 #define MD_DS_STEP ISP_MD_REG_START + 4*0x30 // 240 //Bit 31:20 reserved 241 //Bit 19:16 reg_ds_hstep // unsigned , RW, default = 3 integer pixel ratio for horizontal scalar, o2i_ratio= 1/step, 1~15 242 //Bit 15: 4 reserved 243 //Bit 3: 0 reg_ds_vstep // unsigned , RW, default = 3 integer pixel ratio for vertical scalar, o2i_ratio= 1/step��1~15 244 #define MD_DS_OSIZE ISP_MD_REG_START + 4*0x31 // 245 //Bit 31:28 reserved 246 //Bit 27:16 reg_ds_ocol // unsigned , RW, default = 320 actual downscaled field buffer col number. 247 //Bit 15:12 reserved 248 //Bit 11: 0 reg_ds_orow // unsigned , RW, default = 180 actual downscaled field buffer row number. 249 #define MD_DS_CTRL ISP_MD_REG_START + 4*0x32 // 250 //Bit 31:11 reserved 251 //Bit 10 reg_ds_inp8b // unsigned , RW, default = 0 input to ds accum cell use 8bits instead of 10bits,only set to 1 when (v_step*h_step>64) 0: input 10bits, 1: input 8bits 252 //Bit 9: 0 reg_ds_norm // unsigned , RW, default = 256 normalization gain to the accum to get the 8bits data for ddr, norm = (inp8b? 4096:1024)/pixelnum(v_step*h_step) 253 #define MD_CORE_CTRL0 ISP_MD_REG_START + 4*0x33 // 254 //Bit 31:28 reserved 255 //Bit 27:25 reg_md_sad_mode // unsigned , RW, default = 2 window size for sad, 0: no sad, 1: 1x7, 2:3x3; 3:3x5, else 3x7 256 //Bit 24 reg_md_edge_mode // unsigned , RW, default = 0 mode for the pre and cur edge calculation, 0: min(edge_pre, edge_cur); 1: avg(edge_pre, edge_cur) 257 //Bit 23:16 reg_md_coring // unsigned , RW, default = 6 coring for sad for noise robustness. sad_core = max(sad-coring,0); 258 //Bit 15:14 reserved 259 //Bit 13: 8 reg_md_edge_ratio // unsigned , RW, default = 4 ratio to edge as dynamic coring part, final_coring or 1b_thrd = (edge*ratio + coring); norm to 16 as '1' 260 //Bit 7: 0 reserved 261 #define MD_WIN_XXYY0 ISP_MD_REG_START + 4*0x34 // 262 //Bit 31:26 reserved 263 //Bit 25:16 reg_md_win_xxyy_0 // unsigned , RW, default = 0 for motion sum statistics on down-scaled image. [x_st x_ed; y_st y_ed]*4 264 //Bit 15:10 reserved 265 //Bit 9: 0 reg_md_win_xxyy_1 // unsigned , RW, default = 1023 for motion sum statistics on down-scaled image. [x_st x_ed; y_st y_ed]*4 266 #define MD_WIN_XXYY1 ISP_MD_REG_START + 4*0x35 // 267 //Bit 31:26 reserved 268 //Bit 25:16 reg_md_win_xxyy_2 // unsigned , RW, default = 0 for motion sum statistics on down-scaled image. [x_st x_ed; y_st y_ed]*4 269 //Bit 15:10 reserved 270 //Bit 9: 0 reg_md_win_xxyy_3 // unsigned , RW, default = 1023 for motion sum statistics on down-scaled image. [x_st x_ed; y_st y_ed]*4 271 #define RO_MD_SAD_SUM ISP_MD_REG_START + 4*0x36 // 272 //Bit 31:28 reserved 273 //Bit 27: 0 ro_md_sad_sum // unsigned , RW, default = 0 sum of the motion sad for all the pixels within the window; 274 #define RO_MD_1BM_SUM ISP_MD_REG_START + 4*0x37 // 275 //Bit 31:20 reserved 276 //Bit 19: 0 ro_md_1bm_sum // unsigned , RW, default = 0 sum of the 1bit motion for all the pixels within the window; 277 #define RO_MD_EDG_SUM ISP_MD_REG_START + 4*0x38 // 278 //Bit 31:28 reserved 279 //Bit 27: 0 ro_md_edg_sum // unsigned , RW, default = 0 sum of the edge info for all the pixels within the window; 280 #define MD_ISMOT_SAD_THRD ISP_MD_REG_START + 4*0x39 // 281 //Bit 31:24 reserved 282 //Bit 23: 0 reg_ismot_sad_thrd // unsigned , RW, default = 65536 threshold to sum_sad for current frame is motion 283 #define MD_ISMOT_1BM_THRD ISP_MD_REG_START + 4*0x3a // 284 //Bit 31:16 reserved 285 //Bit 15: 0 reg_ismot_1bm_thrd // unsigned , RW, default = 4096 threshold to sum_1bm for current frame consider as motion 286 #define MD_WR_P_BADDR ISP_MD_REG_START + 4*0x3b // 287 //Bit 31: 0 reg_rd_base_addr_p // unsigned , RW, default = 32'h80000000 288 #define MD_RD_P_BADDR ISP_MD_REG_START + 4*0x3c // 289 //Bit 31: 0 reg_wr_base_addr_p // unsigned , RW, default = 32'h80000000 wr axi base address 290 291 292 typedef struct { 293 //RTL Control 294 int reg_md_gclk ; // u32: clock gate control 295 int reg_md_top_ctrl ; // u32: md top ntrol 296 int reg_wr_axi_wr_en ; //u1: axi wr enable 297 int reg_wr_axi_req_en ; //u1: axi request enable 298 int reg_wr_axi_bypass ; //u1: bypass axi wr 299 int reg_wr_total_size ; //u24: pixels hsize * vsize 300 int reg_wr_base_addr ; //u32: wr axi base address 301 int reg_wr_burst_lens; //u3: burst_lens limiation, burst_size: 0: 1x128, 1: 2x128, 2��3: 4x128 302 int reg_wr_req_th ; //u4: fifo depth req_th * 8 *128 bits in fifo. 303 int reg_wr_urgent_ctrl ; //u16: urgent control 304 int reg_wr_awid ; //u8: wr id 305 int reg_wr_awprot ; //u3: awprot for security control 306 int RO_wr_st0 ; //u32 307 int RO_wr_st1 ; //u32 308 int RO_wr_st2 ; //u32 309 310 int reg_rd_axi_rd_en ; //u1: axi rd enable 311 int reg_rd_axi_req_en ; //u1: axi request enable 312 int reg_rd_total_size ; //u24: total size hsize*vsize, <= 1024*1024 313 int reg_rd_base_addr ; //u32 314 int reg_rd_burst_lens ; //u3: burst_lens limiation, burst_size: 0: 1x128, 1: 2x128, 2��3: 4x128 315 int reg_rd_req_th ; //u4: fifo depth req_th * 8 *128 bits in fifo. 316 int reg_rd_urgent_ctrl ; //u16: urgent control 317 int reg_rd_arid ; //u8: wr id 318 int reg_rd_arprot ; //u3: awprot for security control 319 int RO_rd_st0 ; //u32 320 int RO_rd_st1 ; //u32 321 322 // the motion detection part 323 int reg_md_enable; //u1: lp motion detection enable, 0: disable; 1: enable 324 int reg_md_raw_xphase_ofst; //u1: horizontal phase of the raw data, 0: start wz R-col (RGGB or GBRG); 1: start wz B-col (GRBG or BGGR) 325 int reg_md_raw_yphase_ofst; //u1: vertical phase of the raw data, 0: start wz R-row (RGGB or GRBG); 1: start wz B-row (GRBG or BGGR) 326 int reg_md_input_sel; //u4: data selection for the lp motion detection. 0: raw sensor input; 1: raw WDR stitch; 2:raw fed_out(nr_in); 3:raw mirror_in; 4?? RGB after dms; 5: IRout; 6:RGB/YUV after gamma; 7: fe_o yuv bypass , 8: output port, default=1 327 int reg_md_is_on_raw; //u1: the md_sel is on raw data, set together with md_sel. 0: YUV/RGB; 1:RAW 328 int reg_md_input_ls; //u4, E domain data left shift bit num to align with u20 Odomain data and will clip to u10 by droping 10lsb, e.g. yuv is u12, then ls = 8; 329 int reg_md_input_xsize; //u12, xsize of the input in pixels, set to image xsize 330 int reg_md_input_ysize; //u12, ysize of the input in pixels, set to image ysize 331 332 //step-I O domain reg_RGGB data do the black-level sub, gain, OETF 333 int reg_md_inpc_winxxyy[4]; //u12x4, input combine window for processing. 334 int reg_md_rggb_ofset[4]; //S20x4, ofset to the components, same as the ISP mission mode ofset 335 int reg_md_rggb_gain[4]; //u12x4, gain to different channel, normalize to 1024 as "1.0" 336 int reg_md_bld_coefs[4]; //u8x4, blender coef of the components to Y, normalize to 128 as "1" 337 int reg_md_comb_eotf[61]; //u10x61,OETF, piece wise lut 338 339 int reg_md_eotf_en; //u1,OETF, piece wise lut enable 340 int reg_md_bld_use_max; //u1, use max of the components for the blender, 0: no max, 1:maxa 341 342 //step-II the downscaled frame buffer size 343 int reg_ds_ocol; //u12: actual downscaled field buffer col number.(<=1024) 344 int reg_ds_orow; //u12: actual downscaled field buffer row number. 345 int reg_ds_hstep; //u4: integer pixel ratio for horizontal scalar, o2i_ratio= 1/step, 1��15 346 int reg_ds_vstep; //u4: integer pixel ratio for vertical scalar, o2i_ratio= 1/step??1��15 347 int reg_ds_inp8b; //u1, input to ds accum cell use 8bits instead of 10bits,only set to 1 when (v_step*h_step>64) 0: input 10bits, 1: input 8bits 348 int reg_ds_norm ; //u10; normalization gain to the accum to get the 8bits data for ddr, norm = (inp8b)?4096:1024/pixelnum(v_step*h_step) 349 350 //step-III do the sad calculation and sum-up for RO 351 int reg_md_sad_mode; //u3, window size for sad, 0: no sad, 1: 1x7, 2:3x3; 3:3x5, else 3x7 352 int reg_md_edge_mode; //u1: mode for the pre and cur edge calculation, 0: min(edge_pre, edge_cur); 1: avg(edge_pre, edge_cur) 353 int reg_md_coring; //u8; coring for sad for noise robustness. sad_core = max(sad-coring,0); 354 int reg_md_edge_ratio; //u6: ratio to edge as dynamic coring part, final_coring or 1b_thrd = (edge*ratio + coring); norm to 16 as '1' 355 int reg_md_win_xxyy[4]; //u8x4: window for motion sum statistics on down-scaled image. [x_st x_ed; y_st y_ed]*4 356 357 // the output sum of motion 358 int RO_md_sad_sum; //u28, sum of the motion sad for all the pixels within the window; 359 int RO_md_1bm_sum; //u20, sum of the 1bit motion for all the pixels within the window; 360 int RO_md_edg_sum; //u28, sum of the edge info for all the pixels within the window; 361 362 // to HW decision on is_motion and send out interupt to CPU 363 int reg_ismot_sad_thrd; //u24, threshold to sum_sad for current frame is motion 364 int reg_ismot_1bm_thrd; //u16, threshold to sum_1bm for current frame consider as motion 365 366 int reg_wr_base_addr_p; 367 int reg_rd_base_addr_p; 368 369 }T_MD_PRM; 370 371 struct am_md { 372 struct device_node *of_node; 373 struct platform_device *p_dev; 374 struct resource reg; 375 void __iomem *base_addr; 376 int irq; 377 }; 378 379 int am_md_parse_dt(struct device_node *node); 380 int param_md_init(T_MD_PRM *reg); 381 int param_md_input(T_MD_PRM *reg, int hsize_i, int vsize_i, int in_sel); 382 int param_md_scale(T_MD_PRM *reg, int hsize_i, int vsize_i, int hsize_s, int vsize_o, int32_t base_axi_addr); 383 int param_md_detect(T_MD_PRM *reg, int md_sad_thrd, int md_1bm_thrd); 384 int param_md_set(T_MD_PRM *reg); 385 void am_md_init(void); 386 void am_md_deinit(void); 387 388 389 #endif // __SYSTEM_UART_H__ 390