1 /* 2 * 3 * SPDX-License-Identifier: GPL-2.0 4 * 5 * Copyright (C) 2018 Amlogic or its affiliates 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; version 2. 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * for more details. 14 * You should have received a copy of the GNU General Public License along 15 * with this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 17 * 18 */ 19 20 #ifndef __SYSTEM_AM_SC_H__ 21 #define __SYSTEM_AM_SC_H__ 22 23 #include <linux/module.h> 24 #include <linux/of.h> 25 #include <linux/slab.h> 26 #include <linux/i2c.h> 27 #include "acamera_command_api.h" 28 #include "acamera_firmware_settings.h" 29 #include "acamera.h" 30 #include "acamera_fw.h" 31 #include <linux/kfifo.h> 32 33 #define ISP_SCWR_TOP_CTRL (0x30 << 2) 34 #define ISP_SCWR_GCLK_CTRL (0x31 << 2) 35 #define ISP_SCWR_SYNC_DLY (0x32 << 2) 36 #define ISP_SCWR_HOLD_DLY (0x33 << 2) 37 #define ISP_SCWR_SC_CTRL0 (0x34 << 2) 38 #define ISP_SCWR_SC_CTRL1 (0x35 << 2) 39 #define ISP_SCWR_MIF_CTRL0 (0x36 << 2) 40 #define ISP_SCWR_MIF_CTRL1 (0x37 << 2) 41 #define ISP_SCWR_MIF_CTRL2 (0x38 << 2) 42 #define ISP_SCWR_MIF_CTRL3 (0x39 << 2) 43 #define ISP_SCWR_MIF_CTRL4 (0x3a << 2) 44 #define ISP_SCWR_MIF_CTRL5 (0x3b << 2) 45 #define ISP_SCWR_MIF_CTRL6 (0x3c << 2) 46 #define ISP_SCWR_MIF_CTRL7 (0x3d << 2) 47 #define ISP_SCWR_MIF_CTRL8 (0x3e << 2) 48 #define ISP_SCWR_MIF_CTRL9 (0x3f << 2) 49 #define ISP_SCWR_MIF_CTRL10 (0x40 << 2) 50 #define ISP_SCWR_MIF_CTRL11 (0x41 << 2) 51 #define ISP_SCWR_MIF_CTRL12 (0x42 << 2) 52 #define ISP_SCWR_MIF_CTRL13 (0x43 << 2) 53 #define ISP_SCWR_TOP_DBG0 (0x4a << 2) 54 #define ISP_SCWR_TOP_DBG1 (0x4b << 2) 55 #define ISP_SCWR_TOP_DBG2 (0x4c << 2) 56 #define ISP_SCWR_TOP_DBG3 (0x4d << 2) 57 #define ISP_SCO_FIFO_CTRL (0x4e << 2) 58 #define ISP_SC_DUMMY_DATA (0x50 << 2) 59 #define ISP_SC_LINE_IN_LENGTH (0x51 << 2) 60 #define ISP_SC_PIC_IN_HEIGHT (0x52 << 2) 61 #define ISP_SC_COEF_IDX (0x53 << 2) 62 #define ISP_SC_COEF (0x54 << 2) 63 #define ISP_VSC_REGION12_STARTP (0x55 << 2) 64 #define ISP_VSC_REGION34_STARTP (0x56 << 2) 65 #define ISP_VSC_REGION4_ENDP (0x57 << 2) 66 #define ISP_VSC_START_PHASE_STEP (0x58 << 2) 67 #define ISP_VSC_REGION0_PHASE_SLOPE (0x59 << 2) 68 #define ISP_VSC_REGION1_PHASE_SLOPE (0x5a << 2) 69 #define ISP_VSC_REGION3_PHASE_SLOPE (0x5b << 2) 70 #define ISP_VSC_REGION4_PHASE_SLOPE (0x5c << 2) 71 #define ISP_VSC_PHASE_CTRL (0x5d << 2) 72 #define ISP_VSC_INI_PHASE (0x5e << 2) 73 #define ISP_HSC_REGION12_STARTP (0x60 << 2) 74 #define ISP_HSC_REGION34_STARTP (0x61 << 2) 75 #define ISP_HSC_REGION4_ENDP (0x62 << 2) 76 #define ISP_HSC_START_PHASE_STEP (0x63 << 2) 77 #define ISP_HSC_REGION0_PHASE_SLOPE (0x64 << 2) 78 #define ISP_HSC_REGION1_PHASE_SLOPE (0x65 << 2) 79 #define ISP_HSC_REGION3_PHASE_SLOPE (0x66 << 2) 80 #define ISP_HSC_REGION4_PHASE_SLOPE (0x67 << 2) 81 #define ISP_HSC_PHASE_CTRL (0x68 << 2) 82 #define ISP_SC_MISC (0x69 << 2) 83 #define ISP_HSC_PHASE_CTRL1 (0x6a << 2) 84 #define ISP_HSC_INI_PAT_CTRL (0x6b << 2) 85 #define ISP_SC_GCLK_CTRL (0x6c << 2) 86 #define ISP_MATRIX_COEF00_01 (0x70 << 2) 87 #define ISP_MATRIX_COEF02_10 (0x71 << 2) 88 #define ISP_MATRIX_COEF11_12 (0x72 << 2) 89 #define ISP_MATRIX_COEF20_21 (0x73 << 2) 90 #define ISP_MATRIX_COEF22 (0x74 << 2) 91 #define ISP_MATRIX_COEF30_31 (0x75 << 2) 92 #define ISP_MATRIX_COEF32_40 (0x76 << 2) 93 #define ISP_MATRIX_COEF41_42 (0x77 << 2) 94 #define ISP_MATRIX_CLIP (0x78 << 2) 95 #define ISP_MATRIX_OFFSET0_1 (0x79 << 2) 96 #define ISP_MATRIX_OFFSET2 (0x7a << 2) 97 #define ISP_MATRIX_PRE_OFFSET0_1 (0x7b << 2) 98 #define ISP_MATRIX_PRE_OFFSET2 (0x7c << 2) 99 #define ISP_MATRIX_EN_CTRL (0x7d << 2) 100 101 struct am_sc_info { 102 uint32_t src_w; 103 uint32_t src_h; 104 uint32_t out_w; 105 uint32_t out_h; 106 uint32_t in_fmt; 107 uint32_t out_fmt; 108 uint32_t csc_mode; 109 }; 110 111 struct am_sc { 112 struct device_node *of_node; 113 struct platform_device *p_dev; 114 struct resource reg; 115 void __iomem *base_addr; 116 int irq; 117 spinlock_t sc_lock; 118 struct kfifo sc_fifo_in; 119 int req_buf_num; 120 struct am_sc_info info; 121 acamera_context_ptr_t ctx; 122 buffer_callback_t callback; 123 }; 124 125 extern int am_sc_parse_dt(struct device_node *node); 126 extern void am_sc_deinit_parse_dt(void); 127 extern void am_sc_api_dma_buffer(tframe_t * data, unsigned int index); 128 extern uint32_t am_sc_get_width(void); 129 extern void am_sc_set_width(uint32_t src_w, uint32_t out_w); 130 extern uint32_t am_sc_get_height(void); 131 uint32_t am_sc_get_output_format(void); 132 extern void am_sc_set_height(uint32_t src_h, uint32_t out_h); 133 extern void am_sc_set_input_format(uint32_t value); 134 extern void am_sc_set_output_format(uint32_t value); 135 extern void am_sc_set_buf_num(uint32_t num); 136 extern int am_sc_set_callback(acamera_context_ptr_t p_ctx, buffer_callback_t ds2_callback); 137 extern int am_sc_system_init(void); 138 extern int am_sc_hw_init(void); 139 extern int am_sc_start(void); 140 extern int am_sc_reset(void); 141 extern int am_sc_stop(void); 142 extern int am_sc_system_deinit(void); 143 extern int am_sc_hw_deinit(void); 144 extern void am_sc_set_src_width(uint32_t src_w); 145 extern void am_sc_set_src_height(uint32_t src_h); 146 147 148 #endif 149 150