1 /* 2 * Allwinner SoCs display driver. 3 * 4 * Copyright (C) 2016 Allwinner. 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 */ 10 11 #ifndef __DE_DSI_H_ 12 #define __DE_DSI_H_ 13 14 #include "../../include.h" 15 16 extern u32 dsi_bits_per_pixel[4]; 17 18 enum __dsi_dt_t { 19 /* 20 * Processor to Peripheral Direction (Processor-Sourced) 21 * Packet Data Types 22 */ 23 DSI_DT_VSS = 0x01, 24 DSI_DT_VSE = 0x11, 25 DSI_DT_HSS = 0x21, 26 DSI_DT_HSE = 0x31, 27 DSI_DT_EOT = 0x08, 28 DSI_DT_CM_OFF = 0x02, 29 DSI_DT_CM_ON = 0x12, 30 DSI_DT_SHUT_DOWN = 0x22, 31 DSI_DT_TURN_ON = 0x32, 32 DSI_DT_GEN_WR_P0 = 0x03, 33 DSI_DT_GEN_WR_P1 = 0x13, 34 DSI_DT_GEN_WR_P2 = 0x23, 35 DSI_DT_GEN_RD_P0 = 0x04, 36 DSI_DT_GEN_RD_P1 = 0x14, 37 DSI_DT_GEN_RD_P2 = 0x24, 38 DSI_DT_DCS_WR_P0 = 0x05, 39 DSI_DT_DCS_WR_P1 = 0x15, 40 DSI_DT_DCS_RD_P0 = 0x06, 41 DSI_DT_MAX_RET_SIZE = 0x37, 42 DSI_DT_NULL = 0x09, 43 DSI_DT_BLK = 0x19, 44 DSI_DT_GEN_LONG_WR = 0x29, 45 DSI_DT_DCS_LONG_WR = 0x39, 46 DSI_DT_PIXEL_RGB565 = 0x0E, 47 DSI_DT_PIXEL_RGB666P = 0x1E, 48 DSI_DT_PIXEL_RGB666 = 0x2E, 49 DSI_DT_PIXEL_RGB888 = 0x3E, 50 51 /* Data Types for Peripheral-sourced Packets */ 52 DSI_DT_ACK_ERR = 0x02, 53 DSI_DT_EOT_PERI = 0x08, 54 DSI_DT_GEN_RD_R1 = 0x11, 55 DSI_DT_GEN_RD_R2 = 0x12, 56 DSI_DT_GEN_LONG_RD_R = 0x1A, 57 DSI_DT_DCS_LONG_RD_R = 0x1C, 58 DSI_DT_DCS_RD_R1 = 0x21, 59 DSI_DT_DCS_RD_R2 = 0x22, 60 }; 61 62 enum __dsi_dcs_t { 63 DSI_DCS_ENTER_IDLE_MODE = 0x39, 64 DSI_DCS_ENTER_INVERT_MODE = 0x21, 65 DSI_DCS_ENTER_NORMAL_MODE = 0x13, 66 DSI_DCS_ENTER_PARTIAL_MODE = 0x12, 67 DSI_DCS_ENTER_SLEEP_MODE = 0x10, 68 DSI_DCS_EXIT_IDLE_MODE = 0x38, 69 DSI_DCS_EXIT_INVERT_MODE = 0x20, 70 DSI_DCS_EXIT_SLEEP_MODE = 0x11, 71 DSI_DCS_GET_ADDRESS_MODE = 0x0b, 72 DSI_DCS_GET_BLUE_CHANNEL = 0x08, 73 DSI_DCS_GET_DIAGNOSTIC_RESULT = 0x0f, 74 DSI_DCS_GET_DISPLAY_MODE = 0x0d, 75 DSI_DCS_GET_GREEN_CHANNEL = 0x07, 76 DSI_DCS_GET_PIXEL_FORMAT = 0x0c, 77 DSI_DCS_GET_POWER_MODE = 0x0a, 78 DSI_DCS_GET_RED_CHANNEL = 0x06, 79 DSI_DCS_GET_SCANLINE = 0x45, 80 DSI_DCS_GET_SIGNAL_MODE = 0x0e, 81 DSI_DCS_NOP = 0x00, 82 DSI_DCS_READ_DDB_CONTINUE = 0xa8, 83 DSI_DCS_READ_DDB_START = 0xa1, 84 DSI_DCS_READ_MEMORY_CONTINUE = 0x3e, 85 DSI_DCS_READ_MEMORY_START = 0x2e, 86 DSI_DCS_SET_ADDRESS_MODE = 0x36, 87 DSI_DCS_SET_COLUMN_ADDRESS = 0x2a, 88 DSI_DCS_SET_DISPLAY_OFF = 0x28, 89 DSI_DCS_SET_DISPLAY_ON = 0x29, 90 DSI_DCS_SET_GAMMA_CURVE = 0x26, 91 DSI_DCS_SET_PAGE_ADDRESS = 0x2b, 92 DSI_DCS_SET_PARTIAL_AREA = 0x30, 93 DSI_DCS_SET_PIXEL_FORMAT = 0x3a, 94 DSI_DCS_SET_SCROLL_AREA = 0x33, 95 DSI_DCS_SET_SCROLL_START = 0x37, 96 DSI_DCS_SET_TEAR_OFF = 0x34, 97 DSI_DCS_SET_TEAR_ON = 0x35, 98 DSI_DCS_SET_TEAR_SCANLINE = 0x44, 99 DSI_DCS_SOFT_RESET = 0x01, 100 DSI_DCS_WRITE_LUT = 0x2d, 101 DSI_DCS_WRITE_MEMORY_CONTINUE = 0x3c, 102 DSI_DCS_WRITE_MEMORY_START = 0x2c, 103 }; 104 105 enum __dsi_start_t { 106 DSI_START_LP11 = 0, 107 DSI_START_TBA = 1, 108 DSI_START_HSTX = 2, 109 DSI_START_LPTX = 3, 110 DSI_START_LPRX = 4, 111 DSI_START_HSC = 5, 112 DSI_START_HSD = 6, 113 }; 114 115 enum __dsi_inst_id_t { 116 DSI_INST_ID_LP11 = 0, 117 DSI_INST_ID_TBA = 1, 118 DSI_INST_ID_HSC = 2, 119 DSI_INST_ID_HSD = 3, 120 DSI_INST_ID_LPDT = 4, 121 DSI_INST_ID_HSCEXIT = 5, 122 DSI_INST_ID_NOP = 6, 123 DSI_INST_ID_DLY = 7, 124 DSI_INST_ID_END = 15, 125 }; 126 127 enum __dsi_inst_mode_t { 128 DSI_INST_MODE_STOP = 0, 129 DSI_INST_MODE_TBA = 1, 130 DSI_INST_MODE_HS = 2, 131 DSI_INST_MODE_ESCAPE = 3, 132 DSI_INST_MODE_HSCEXIT = 4, 133 DSI_INST_MODE_NOP = 5, 134 }; 135 136 enum __dsi_inst_escape_t { 137 DSI_INST_ESCA_LPDT = 0, 138 DSI_INST_ESCA_ULPS = 1, 139 DSI_INST_ESCA_UN1 = 2, 140 DSI_INST_ESCA_UN2 = 3, 141 DSI_INST_ESCA_RESET = 4, 142 DSI_INST_ESCA_UN3 = 5, 143 DSI_INST_ESCA_UN4 = 6, 144 DSI_INST_ESCA_UN5 = 7, 145 }; 146 147 enum __dsi_inst_packet_t { 148 DSI_INST_PACK_PIXEL = 0, 149 DSI_INST_PACK_COMMAND = 1, 150 }; 151 152 s32 dsi_delay_ms(u32 ms); 153 s32 dsi_delay_us(u32 us); 154 s32 dsi_set_reg_base(u32 sel, uintptr_t base); 155 u32 dsi_get_reg_base(u32 sel); 156 u32 dsi_irq_query(u32 sel, enum __dsi_irq_id_t id); 157 s32 dsi_cfg(u32 sel, struct disp_panel_para *panel); 158 s32 dsi_exit(u32 sel); 159 s32 dsi_open(u32 sel, struct disp_panel_para *panel); 160 s32 dsi_close(u32 sel); 161 s32 dsi_inst_busy(u32 sel); 162 s32 dsi_tri_start(u32 sel); 163 s32 dsi_dcs_wr(u32 sel, u8 cmd, u8 *para_p, u32 para_num); 164 s32 dsi_dcs_wr_index(u32 sel, u8 index); 165 s32 dsi_dcs_wr_data(u32 sel, u8 data); 166 u32 dsi_get_start_delay(u32 sel); 167 u32 dsi_get_cur_line(u32 sel); 168 u32 dsi_io_open(u32 sel, struct disp_panel_para *panel); 169 u32 dsi_io_close(u32 sel); 170 s32 dsi_clk_enable(u32 sel, u32 en); 171 u32 dsi_dphy_get_reg_base(u32 sel); 172 s32 dsi_irq_enable(u32 sel, enum __dsi_irq_id_t id); 173 s32 dsi_irq_disable(u32 sel, enum __dsi_irq_id_t id); 174 s32 dsi_dcs_wr_0para(u32 sel, u8 cmd); 175 s32 dsi_dcs_wr_1para(u32 sel, u8 cmd, u8 para); 176 s32 dsi_dcs_wr_2para(u32 sel, u8 cmd, u8 para1, u8 para2); 177 s32 dsi_dcs_wr_3para(u32 sel, u8 cmd, u8 para1, u8 para2, u8 para3); 178 s32 dsi_dcs_wr_4para(u32 sel, u8 cmd, u8 para1, u8 para2, u8 para3, u8 para4); 179 s32 dsi_dcs_wr_5para(u32 sel, u8 cmd, u8 para1, u8 para2, u8 para3, u8 para4, 180 u8 para5); 181 s32 dsi_dcs_wr_memory(u32 sel, u32 *p_data, u32 length); 182 s32 dsi_dcs_rd(u32 sel, u8 cmd, u8 *para_p, u32 *num_p); 183 s32 dsi_dcs_rd_memory(u32 sel, u32 *p_data, u32 length); 184 s32 dsi_start(u32 sel, enum __dsi_start_t func); 185 s32 dsi_command_enable(u32 sel, u32 cmd_en, u32 is_lp); 186 s32 dsi_set_max_ret_size(u32 sel, u32 size); 187 s32 dsi_gen_wr(u32 sel, u8 cmd, u8 *para_p, u32 para_num); 188 s32 dsi_gen_wr_0para(u32 sel, u8 cmd); 189 s32 dsi_gen_wr_1para(u32 sel, u8 cmd, u8 para); 190 s32 dsi_gen_wr_2para(u32 sel, u8 cmd, u8 para1, u8 para2); 191 s32 dsi_gen_wr_3para(u32 sel, u8 cmd, u8 para1, u8 para2, u8 para3); 192 s32 dsi_gen_wr_4para(u32 sel, u8 cmd, u8 para1, u8 para2, u8 para3, u8 para4); 193 s32 dsi_gen_wr_5para(u32 sel, u8 cmd, u8 para1, u8 para2, u8 para3, u8 para4, 194 u8 para5); 195 196 s32 dsi_dphy_cfg_0data(u32 sel, u32 code); 197 s32 dsi_dphy_cfg_1data(u32 sel, u32 code, u32 data); 198 s32 dsi_dphy_cfg_2data(u32 sel, u32 code, u32 data0, u32 data1); 199 s32 dsi_gen_short_rd(__u32 sel, __u8 *para_p, __u8 para_num, __u8 *result); 200 201 extern u32 dsi_pixel_bits[4]; 202 extern u32 dsi_lane_den[4]; 203 extern u32 tcon_div; 204 s32 dsi_hs_clk(u32 sel, u32 on_off); 205 u8 dsi_ecc_pro(u32 dsi_ph); 206 u16 dsi_crc_pro_pd_repeat(u8 pd, u32 pd_bytes); 207 u16 dsi_crc_pro(u8 *pd_p, u32 pd_bytes); 208 s32 dsi_mode_switch(__u32 sel, __u32 cmd_en, __u32 lp_en); 209 s32 dsi_get_status(u32 sel); 210 #endif 211