1 /* 2 * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE 3 * 4 * NOTE: This header file is not meant to be included directly. 5 */ 6 7 /* This header file contains assembly-language definitions (assembly 8 macros, etc.) for this specific Xtensa processor's TIE extensions 9 and options. It is customized to this Xtensa processor configuration. 10 11 Customer ID=11657; Build=0x5fe96; Copyright (c) 1999-2016 Cadence Design Systems Inc. 12 13 Permission is hereby granted, free of charge, to any person obtaining 14 a copy of this software and associated documentation files (the 15 "Software"), to deal in the Software without restriction, including 16 without limitation the rights to use, copy, modify, merge, publish, 17 distribute, sublicense, and/or sell copies of the Software, and to 18 permit persons to whom the Software is furnished to do so, subject to 19 the following conditions: 20 21 The above copyright notice and this permission notice shall be included 22 in all copies or substantial portions of the Software. 23 24 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 27 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 28 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 29 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 30 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ 31 32 #ifndef _XTENSA_CORE_TIE_ASM_H 33 #define _XTENSA_CORE_TIE_ASM_H 34 35 /* Selection parameter values for save-area save/restore macros: */ 36 /* Option vs. TIE: */ 37 #define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */ 38 #define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */ 39 #define XTHAL_SAS_ANYOT 0x0003 /* both of the above */ 40 /* Whether used automatically by compiler: */ 41 #define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */ 42 #define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */ 43 #define XTHAL_SAS_ANYCC 0x000C /* both of the above */ 44 /* ABI handling across function calls: */ 45 #define XTHAL_SAS_CALR 0x0010 /* caller-saved */ 46 #define XTHAL_SAS_CALE 0x0020 /* callee-saved */ 47 #define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */ 48 #define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */ 49 /* Misc */ 50 #define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */ 51 #define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \ 52 | ((ccuse) & XTHAL_SAS_ANYCC) \ 53 | ((abi) & XTHAL_SAS_ANYABI) ) 54 55 56 /* 57 * Macro to store all non-coprocessor (extra) custom TIE and optional state 58 * (not including zero-overhead loop registers). 59 * Required parameters: 60 * ptr Save area pointer address register (clobbered) 61 * (register must contain a 4 byte aligned address). 62 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS 63 * registers are clobbered, the remaining are unused). 64 * Optional parameters: 65 * continue If macro invoked as part of a larger store sequence, set to 1 66 * if this is not the first in the sequence. Defaults to 0. 67 * ofs Offset from start of larger sequence (from value of first ptr 68 * in sequence) at which to store. Defaults to next available space 69 * (or 0 if <continue> is 0). 70 * select Select what category(ies) of registers to store, as a bitmask 71 * (see XTHAL_SAS_xxx constants). Defaults to all registers. 72 * alloc Select what category(ies) of registers to allocate; if any 73 * category is selected here that is not in <select>, space for 74 * the corresponding registers is skipped without doing any store. 75 */ 76 .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 77 xchal_sa_start \continue, \ofs 78 // Optional global registers used by default by the compiler: 79 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select) 80 xchal_sa_align \ptr, 0, 1016, 4, 4 81 rur.THREADPTR \at1 // threadptr option 82 s32i \at1, \ptr, .Lxchal_ofs_+0 83 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 84 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0 85 xchal_sa_align \ptr, 0, 1016, 4, 4 86 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 87 .endif 88 // Optional caller-saved registers used by default by the compiler: 89 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select) 90 xchal_sa_align \ptr, 0, 1012, 4, 4 91 rsr.ACCLO \at1 // MAC16 option 92 s32i \at1, \ptr, .Lxchal_ofs_+0 93 rsr.ACCHI \at1 // MAC16 option 94 s32i \at1, \ptr, .Lxchal_ofs_+4 95 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 96 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 97 xchal_sa_align \ptr, 0, 1012, 4, 4 98 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 99 .endif 100 // Optional caller-saved registers not used by default by the compiler: 101 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 102 xchal_sa_align \ptr, 0, 996, 4, 4 103 rsr.BR \at1 // boolean option 104 s32i \at1, \ptr, .Lxchal_ofs_+0 105 rsr.SCOMPARE1 \at1 // conditional store option 106 s32i \at1, \ptr, .Lxchal_ofs_+4 107 rsr.M0 \at1 // MAC16 option 108 s32i \at1, \ptr, .Lxchal_ofs_+8 109 rsr.M1 \at1 // MAC16 option 110 s32i \at1, \ptr, .Lxchal_ofs_+12 111 rsr.M2 \at1 // MAC16 option 112 s32i \at1, \ptr, .Lxchal_ofs_+16 113 rsr.M3 \at1 // MAC16 option 114 s32i \at1, \ptr, .Lxchal_ofs_+20 115 .set .Lxchal_ofs_, .Lxchal_ofs_ + 24 116 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 117 xchal_sa_align \ptr, 0, 996, 4, 4 118 .set .Lxchal_ofs_, .Lxchal_ofs_ + 24 119 .endif 120 // Custom caller-saved registers not used by default by the compiler: 121 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 122 xchal_sa_align \ptr, 0, 1008, 4, 4 123 rur.F64R_LO \at1 // ureg 234 124 s32i \at1, \ptr, .Lxchal_ofs_+0 125 rur.F64R_HI \at1 // ureg 235 126 s32i \at1, \ptr, .Lxchal_ofs_+4 127 rur.F64S \at1 // ureg 236 128 s32i \at1, \ptr, .Lxchal_ofs_+8 129 .set .Lxchal_ofs_, .Lxchal_ofs_ + 12 130 .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 131 xchal_sa_align \ptr, 0, 1008, 4, 4 132 .set .Lxchal_ofs_, .Lxchal_ofs_ + 12 133 .endif 134 .endm // xchal_ncp_store 135 136 /* 137 * Macro to load all non-coprocessor (extra) custom TIE and optional state 138 * (not including zero-overhead loop registers). 139 * Required parameters: 140 * ptr Save area pointer address register (clobbered) 141 * (register must contain a 4 byte aligned address). 142 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS 143 * registers are clobbered, the remaining are unused). 144 * Optional parameters: 145 * continue If macro invoked as part of a larger load sequence, set to 1 146 * if this is not the first in the sequence. Defaults to 0. 147 * ofs Offset from start of larger sequence (from value of first ptr 148 * in sequence) at which to load. Defaults to next available space 149 * (or 0 if <continue> is 0). 150 * select Select what category(ies) of registers to load, as a bitmask 151 * (see XTHAL_SAS_xxx constants). Defaults to all registers. 152 * alloc Select what category(ies) of registers to allocate; if any 153 * category is selected here that is not in <select>, space for 154 * the corresponding registers is skipped without doing any load. 155 */ 156 .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 157 xchal_sa_start \continue, \ofs 158 // Optional global registers used by default by the compiler: 159 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select) 160 xchal_sa_align \ptr, 0, 1016, 4, 4 161 l32i \at1, \ptr, .Lxchal_ofs_+0 162 wur.THREADPTR \at1 // threadptr option 163 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 164 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0 165 xchal_sa_align \ptr, 0, 1016, 4, 4 166 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 167 .endif 168 // Optional caller-saved registers used by default by the compiler: 169 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select) 170 xchal_sa_align \ptr, 0, 1012, 4, 4 171 l32i \at1, \ptr, .Lxchal_ofs_+0 172 wsr.ACCLO \at1 // MAC16 option 173 l32i \at1, \ptr, .Lxchal_ofs_+4 174 wsr.ACCHI \at1 // MAC16 option 175 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 176 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 177 xchal_sa_align \ptr, 0, 1012, 4, 4 178 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 179 .endif 180 // Optional caller-saved registers not used by default by the compiler: 181 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 182 xchal_sa_align \ptr, 0, 996, 4, 4 183 l32i \at1, \ptr, .Lxchal_ofs_+0 184 wsr.BR \at1 // boolean option 185 l32i \at1, \ptr, .Lxchal_ofs_+4 186 wsr.SCOMPARE1 \at1 // conditional store option 187 l32i \at1, \ptr, .Lxchal_ofs_+8 188 wsr.M0 \at1 // MAC16 option 189 l32i \at1, \ptr, .Lxchal_ofs_+12 190 wsr.M1 \at1 // MAC16 option 191 l32i \at1, \ptr, .Lxchal_ofs_+16 192 wsr.M2 \at1 // MAC16 option 193 l32i \at1, \ptr, .Lxchal_ofs_+20 194 wsr.M3 \at1 // MAC16 option 195 .set .Lxchal_ofs_, .Lxchal_ofs_ + 24 196 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 197 xchal_sa_align \ptr, 0, 996, 4, 4 198 .set .Lxchal_ofs_, .Lxchal_ofs_ + 24 199 .endif 200 // Custom caller-saved registers not used by default by the compiler: 201 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 202 xchal_sa_align \ptr, 0, 1008, 4, 4 203 l32i \at1, \ptr, .Lxchal_ofs_+0 204 wur.F64R_LO \at1 // ureg 234 205 l32i \at1, \ptr, .Lxchal_ofs_+4 206 wur.F64R_HI \at1 // ureg 235 207 l32i \at1, \ptr, .Lxchal_ofs_+8 208 wur.F64S \at1 // ureg 236 209 .set .Lxchal_ofs_, .Lxchal_ofs_ + 12 210 .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 211 xchal_sa_align \ptr, 0, 1008, 4, 4 212 .set .Lxchal_ofs_, .Lxchal_ofs_ + 12 213 .endif 214 .endm // xchal_ncp_load 215 216 217 #define XCHAL_NCP_NUM_ATMPS 1 218 219 /* 220 * Macro to store the state of TIE coprocessor FPU. 221 * Required parameters: 222 * ptr Save area pointer address register (clobbered) 223 * (register must contain a 4 byte aligned address). 224 * at1..at4 Four temporary address registers (first XCHAL_CP0_NUM_ATMPS 225 * registers are clobbered, the remaining are unused). 226 * Optional parameters are the same as for xchal_ncp_store. 227 */ 228 #define xchal_cp_FPU_store xchal_cp0_store 229 .macro xchal_cp0_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 230 xchal_sa_start \continue, \ofs 231 // Custom caller-saved registers not used by default by the compiler: 232 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 233 xchal_sa_align \ptr, 0, 948, 4, 4 234 rur.FCR \at1 // ureg 232 235 s32i \at1, \ptr, .Lxchal_ofs_+0 236 rur.FSR \at1 // ureg 233 237 s32i \at1, \ptr, .Lxchal_ofs_+4 238 ssi f0, \ptr, .Lxchal_ofs_+8 239 ssi f1, \ptr, .Lxchal_ofs_+12 240 ssi f2, \ptr, .Lxchal_ofs_+16 241 ssi f3, \ptr, .Lxchal_ofs_+20 242 ssi f4, \ptr, .Lxchal_ofs_+24 243 ssi f5, \ptr, .Lxchal_ofs_+28 244 ssi f6, \ptr, .Lxchal_ofs_+32 245 ssi f7, \ptr, .Lxchal_ofs_+36 246 ssi f8, \ptr, .Lxchal_ofs_+40 247 ssi f9, \ptr, .Lxchal_ofs_+44 248 ssi f10, \ptr, .Lxchal_ofs_+48 249 ssi f11, \ptr, .Lxchal_ofs_+52 250 ssi f12, \ptr, .Lxchal_ofs_+56 251 ssi f13, \ptr, .Lxchal_ofs_+60 252 ssi f14, \ptr, .Lxchal_ofs_+64 253 ssi f15, \ptr, .Lxchal_ofs_+68 254 .set .Lxchal_ofs_, .Lxchal_ofs_ + 72 255 .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 256 xchal_sa_align \ptr, 0, 948, 4, 4 257 .set .Lxchal_ofs_, .Lxchal_ofs_ + 72 258 .endif 259 .endm // xchal_cp0_store 260 261 /* 262 * Macro to load the state of TIE coprocessor FPU. 263 * Required parameters: 264 * ptr Save area pointer address register (clobbered) 265 * (register must contain a 4 byte aligned address). 266 * at1..at4 Four temporary address registers (first XCHAL_CP0_NUM_ATMPS 267 * registers are clobbered, the remaining are unused). 268 * Optional parameters are the same as for xchal_ncp_load. 269 */ 270 #define xchal_cp_FPU_load xchal_cp0_load 271 .macro xchal_cp0_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 272 xchal_sa_start \continue, \ofs 273 // Custom caller-saved registers not used by default by the compiler: 274 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 275 xchal_sa_align \ptr, 0, 948, 4, 4 276 l32i \at1, \ptr, .Lxchal_ofs_+0 277 wur.FCR \at1 // ureg 232 278 l32i \at1, \ptr, .Lxchal_ofs_+4 279 wur.FSR \at1 // ureg 233 280 lsi f0, \ptr, .Lxchal_ofs_+8 281 lsi f1, \ptr, .Lxchal_ofs_+12 282 lsi f2, \ptr, .Lxchal_ofs_+16 283 lsi f3, \ptr, .Lxchal_ofs_+20 284 lsi f4, \ptr, .Lxchal_ofs_+24 285 lsi f5, \ptr, .Lxchal_ofs_+28 286 lsi f6, \ptr, .Lxchal_ofs_+32 287 lsi f7, \ptr, .Lxchal_ofs_+36 288 lsi f8, \ptr, .Lxchal_ofs_+40 289 lsi f9, \ptr, .Lxchal_ofs_+44 290 lsi f10, \ptr, .Lxchal_ofs_+48 291 lsi f11, \ptr, .Lxchal_ofs_+52 292 lsi f12, \ptr, .Lxchal_ofs_+56 293 lsi f13, \ptr, .Lxchal_ofs_+60 294 lsi f14, \ptr, .Lxchal_ofs_+64 295 lsi f15, \ptr, .Lxchal_ofs_+68 296 .set .Lxchal_ofs_, .Lxchal_ofs_ + 72 297 .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 298 xchal_sa_align \ptr, 0, 948, 4, 4 299 .set .Lxchal_ofs_, .Lxchal_ofs_ + 72 300 .endif 301 .endm // xchal_cp0_load 302 303 #define XCHAL_CP0_NUM_ATMPS 1 304 #define XCHAL_SA_NUM_ATMPS 1 305 306 /* Empty macros for unconfigured coprocessors: */ 307 .macro xchal_cp1_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 308 .macro xchal_cp1_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 309 .macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 310 .macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 311 .macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 312 .macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 313 .macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 314 .macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 315 .macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 316 .macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 317 .macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 318 .macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 319 .macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 320 .macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 321 322 #endif /*_XTENSA_CORE_TIE_ASM_H*/ 323