1 /* 2 * xtensa/config/core.h -- HAL definitions dependent on CORE configuration 3 * 4 * This header file is sometimes referred to as the "compile-time HAL" or CHAL. 5 * It pulls definitions tailored for a specific Xtensa processor configuration. 6 * 7 * Sources for binaries meant to be configuration-independent generally avoid 8 * including this file (they may use the configuration-specific HAL library). 9 * It is normal for the HAL library source itself to include this file. 10 */ 11 12 /* 13 * Copyright (c) 2005-2014 Cadence Design Systems, Inc. 14 * 15 * Permission is hereby granted, free of charge, to any person obtaining 16 * a copy of this software and associated documentation files (the 17 * "Software"), to deal in the Software without restriction, including 18 * without limitation the rights to use, copy, modify, merge, publish, 19 * distribute, sublicense, and/or sell copies of the Software, and to 20 * permit persons to whom the Software is furnished to do so, subject to 21 * the following conditions: 22 * 23 * The above copyright notice and this permission notice shall be included 24 * in all copies or substantial portions of the Software. 25 * 26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 29 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 30 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 31 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 32 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 33 */ 34 35 36 #ifndef XTENSA_CONFIG_CORE_H 37 #define XTENSA_CONFIG_CORE_H 38 39 /* CONFIGURATION INDEPENDENT DEFINITIONS: */ 40 #ifdef __XTENSA__ 41 #include <xtensa/hal.h> 42 #include <xtensa/xtensa-versions.h> 43 #else 44 #include "xtensa/hal.h" 45 #include "xtensa/xtensa-versions.h" 46 #endif 47 48 /* CONFIGURATION SPECIFIC DEFINITIONS: */ 49 #ifdef __XTENSA__ 50 #include <xtensa/config/core-isa.h> 51 #include <xtensa/config/core-matmap.h> 52 #include <xtensa/config/tie.h> 53 #else 54 #include "core-isa.h" 55 #include "core-matmap.h" 56 #include "tie.h" 57 #endif 58 59 #if defined (_ASMLANGUAGE) || defined (__ASSEMBLER__) 60 #ifdef __XTENSA__ 61 #include <xtensa/config/tie-asm.h> 62 #else 63 #include "tie-asm.h" 64 #endif 65 #endif /*_ASMLANGUAGE or __ASSEMBLER__*/ 66 67 68 /*---------------------------------------------------------------------- 69 GENERAL 70 ----------------------------------------------------------------------*/ 71 72 /* 73 * Separators for macros that expand into arrays. 74 * These can be predefined by files that #include this one, 75 * when different separators are required. 76 */ 77 /* Element separator for macros that expand into 1-dimensional arrays: */ 78 #ifndef XCHAL_SEP 79 #define XCHAL_SEP , 80 #endif 81 /* Array separator for macros that expand into 2-dimensional arrays: */ 82 #ifndef XCHAL_SEP2 83 #define XCHAL_SEP2 },{ 84 #endif 85 86 87 88 /*---------------------------------------------------------------------- 89 ISA 90 ----------------------------------------------------------------------*/ 91 92 #if XCHAL_HAVE_BE 93 # define XCHAL_HAVE_LE 0 94 # define XCHAL_MEMORY_ORDER XTHAL_BIGENDIAN 95 #else 96 # define XCHAL_HAVE_LE 1 97 # define XCHAL_MEMORY_ORDER XTHAL_LITTLEENDIAN 98 #endif 99 100 101 102 /*---------------------------------------------------------------------- 103 INTERRUPTS 104 ----------------------------------------------------------------------*/ 105 106 /* Indexing macros: */ 107 #define _XCHAL_INTLEVEL_MASK(n) XCHAL_INTLEVEL ## n ## _MASK 108 #define XCHAL_INTLEVEL_MASK(n) _XCHAL_INTLEVEL_MASK(n) /* n = 0 .. 15 */ 109 #define _XCHAL_INTLEVEL_ANDBELOWMASK(n) XCHAL_INTLEVEL ## n ## _ANDBELOW_MASK 110 #define XCHAL_INTLEVEL_ANDBELOW_MASK(n) _XCHAL_INTLEVEL_ANDBELOWMASK(n) /* n = 0 .. 15 */ 111 #define _XCHAL_INTLEVEL_NUM(n) XCHAL_INTLEVEL ## n ## _NUM 112 #define XCHAL_INTLEVEL_NUM(n) _XCHAL_INTLEVEL_NUM(n) /* n = 0 .. 15 */ 113 #define _XCHAL_INT_LEVEL(n) XCHAL_INT ## n ## _LEVEL 114 #define XCHAL_INT_LEVEL(n) _XCHAL_INT_LEVEL(n) /* n = 0 .. 31 */ 115 #define _XCHAL_INT_TYPE(n) XCHAL_INT ## n ## _TYPE 116 #define XCHAL_INT_TYPE(n) _XCHAL_INT_TYPE(n) /* n = 0 .. 31 */ 117 #define _XCHAL_TIMER_INTERRUPT(n) XCHAL_TIMER ## n ## _INTERRUPT 118 #define XCHAL_TIMER_INTERRUPT(n) _XCHAL_TIMER_INTERRUPT(n) /* n = 0 .. 3 */ 119 120 121 #define XCHAL_HAVE_HIGHLEVEL_INTERRUPTS XCHAL_HAVE_HIGHPRI_INTERRUPTS 122 #define XCHAL_NUM_LOWPRI_LEVELS 1 /* number of low-priority interrupt levels (always 1) */ 123 #define XCHAL_FIRST_HIGHPRI_LEVEL (XCHAL_NUM_LOWPRI_LEVELS+1) /* level of first high-priority interrupt (always 2) */ 124 /* Note: 1 <= LOWPRI_LEVELS <= EXCM_LEVEL < DEBUGLEVEL <= NUM_INTLEVELS < NMILEVEL <= 15 */ 125 126 /* These values are constant for existing Xtensa processor implementations: */ 127 #define XCHAL_INTLEVEL0_MASK 0x00000000 128 #define XCHAL_INTLEVEL8_MASK 0x00000000 129 #define XCHAL_INTLEVEL9_MASK 0x00000000 130 #define XCHAL_INTLEVEL10_MASK 0x00000000 131 #define XCHAL_INTLEVEL11_MASK 0x00000000 132 #define XCHAL_INTLEVEL12_MASK 0x00000000 133 #define XCHAL_INTLEVEL13_MASK 0x00000000 134 #define XCHAL_INTLEVEL14_MASK 0x00000000 135 #define XCHAL_INTLEVEL15_MASK 0x00000000 136 137 /* Array of masks of interrupts at each interrupt level: */ 138 #define XCHAL_INTLEVEL_MASKS XCHAL_INTLEVEL0_MASK \ 139 XCHAL_SEP XCHAL_INTLEVEL1_MASK \ 140 XCHAL_SEP XCHAL_INTLEVEL2_MASK \ 141 XCHAL_SEP XCHAL_INTLEVEL3_MASK \ 142 XCHAL_SEP XCHAL_INTLEVEL4_MASK \ 143 XCHAL_SEP XCHAL_INTLEVEL5_MASK \ 144 XCHAL_SEP XCHAL_INTLEVEL6_MASK \ 145 XCHAL_SEP XCHAL_INTLEVEL7_MASK \ 146 XCHAL_SEP XCHAL_INTLEVEL8_MASK \ 147 XCHAL_SEP XCHAL_INTLEVEL9_MASK \ 148 XCHAL_SEP XCHAL_INTLEVEL10_MASK \ 149 XCHAL_SEP XCHAL_INTLEVEL11_MASK \ 150 XCHAL_SEP XCHAL_INTLEVEL12_MASK \ 151 XCHAL_SEP XCHAL_INTLEVEL13_MASK \ 152 XCHAL_SEP XCHAL_INTLEVEL14_MASK \ 153 XCHAL_SEP XCHAL_INTLEVEL15_MASK 154 155 /* These values are constant for existing Xtensa processor implementations: */ 156 #define XCHAL_INTLEVEL0_ANDBELOW_MASK 0x00000000 157 #define XCHAL_INTLEVEL8_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK 158 #define XCHAL_INTLEVEL9_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK 159 #define XCHAL_INTLEVEL10_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK 160 #define XCHAL_INTLEVEL11_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK 161 #define XCHAL_INTLEVEL12_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK 162 #define XCHAL_INTLEVEL13_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK 163 #define XCHAL_INTLEVEL14_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK 164 #define XCHAL_INTLEVEL15_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK 165 166 /* Mask of all low-priority interrupts: */ 167 #define XCHAL_LOWPRI_MASK XCHAL_INTLEVEL1_ANDBELOW_MASK 168 169 /* Mask of all interrupts masked by PS.EXCM (or CEXCM): */ 170 #define XCHAL_EXCM_MASK XCHAL_INTLEVEL_ANDBELOW_MASK(XCHAL_EXCM_LEVEL) 171 172 /* Array of masks of interrupts at each range 1..n of interrupt levels: */ 173 #define XCHAL_INTLEVEL_ANDBELOW_MASKS XCHAL_INTLEVEL0_ANDBELOW_MASK \ 174 XCHAL_SEP XCHAL_INTLEVEL1_ANDBELOW_MASK \ 175 XCHAL_SEP XCHAL_INTLEVEL2_ANDBELOW_MASK \ 176 XCHAL_SEP XCHAL_INTLEVEL3_ANDBELOW_MASK \ 177 XCHAL_SEP XCHAL_INTLEVEL4_ANDBELOW_MASK \ 178 XCHAL_SEP XCHAL_INTLEVEL5_ANDBELOW_MASK \ 179 XCHAL_SEP XCHAL_INTLEVEL6_ANDBELOW_MASK \ 180 XCHAL_SEP XCHAL_INTLEVEL7_ANDBELOW_MASK \ 181 XCHAL_SEP XCHAL_INTLEVEL8_ANDBELOW_MASK \ 182 XCHAL_SEP XCHAL_INTLEVEL9_ANDBELOW_MASK \ 183 XCHAL_SEP XCHAL_INTLEVEL10_ANDBELOW_MASK \ 184 XCHAL_SEP XCHAL_INTLEVEL11_ANDBELOW_MASK \ 185 XCHAL_SEP XCHAL_INTLEVEL12_ANDBELOW_MASK \ 186 XCHAL_SEP XCHAL_INTLEVEL13_ANDBELOW_MASK \ 187 XCHAL_SEP XCHAL_INTLEVEL14_ANDBELOW_MASK \ 188 XCHAL_SEP XCHAL_INTLEVEL15_ANDBELOW_MASK 189 190 #if 0 /*XCHAL_HAVE_NMI*/ 191 /* NMI "interrupt level" (for use with EXCSAVE_n, EPS_n, EPC_n, RFI n): */ 192 # define XCHAL_NMILEVEL (XCHAL_NUM_INTLEVELS+1) 193 #endif 194 195 /* Array of levels of each possible interrupt: */ 196 #define XCHAL_INT_LEVELS XCHAL_INT0_LEVEL \ 197 XCHAL_SEP XCHAL_INT1_LEVEL \ 198 XCHAL_SEP XCHAL_INT2_LEVEL \ 199 XCHAL_SEP XCHAL_INT3_LEVEL \ 200 XCHAL_SEP XCHAL_INT4_LEVEL \ 201 XCHAL_SEP XCHAL_INT5_LEVEL \ 202 XCHAL_SEP XCHAL_INT6_LEVEL \ 203 XCHAL_SEP XCHAL_INT7_LEVEL \ 204 XCHAL_SEP XCHAL_INT8_LEVEL \ 205 XCHAL_SEP XCHAL_INT9_LEVEL \ 206 XCHAL_SEP XCHAL_INT10_LEVEL \ 207 XCHAL_SEP XCHAL_INT11_LEVEL \ 208 XCHAL_SEP XCHAL_INT12_LEVEL \ 209 XCHAL_SEP XCHAL_INT13_LEVEL \ 210 XCHAL_SEP XCHAL_INT14_LEVEL \ 211 XCHAL_SEP XCHAL_INT15_LEVEL \ 212 XCHAL_SEP XCHAL_INT16_LEVEL \ 213 XCHAL_SEP XCHAL_INT17_LEVEL \ 214 XCHAL_SEP XCHAL_INT18_LEVEL \ 215 XCHAL_SEP XCHAL_INT19_LEVEL \ 216 XCHAL_SEP XCHAL_INT20_LEVEL \ 217 XCHAL_SEP XCHAL_INT21_LEVEL \ 218 XCHAL_SEP XCHAL_INT22_LEVEL \ 219 XCHAL_SEP XCHAL_INT23_LEVEL \ 220 XCHAL_SEP XCHAL_INT24_LEVEL \ 221 XCHAL_SEP XCHAL_INT25_LEVEL \ 222 XCHAL_SEP XCHAL_INT26_LEVEL \ 223 XCHAL_SEP XCHAL_INT27_LEVEL \ 224 XCHAL_SEP XCHAL_INT28_LEVEL \ 225 XCHAL_SEP XCHAL_INT29_LEVEL \ 226 XCHAL_SEP XCHAL_INT30_LEVEL \ 227 XCHAL_SEP XCHAL_INT31_LEVEL 228 229 /* Array of types of each possible interrupt: */ 230 #define XCHAL_INT_TYPES XCHAL_INT0_TYPE \ 231 XCHAL_SEP XCHAL_INT1_TYPE \ 232 XCHAL_SEP XCHAL_INT2_TYPE \ 233 XCHAL_SEP XCHAL_INT3_TYPE \ 234 XCHAL_SEP XCHAL_INT4_TYPE \ 235 XCHAL_SEP XCHAL_INT5_TYPE \ 236 XCHAL_SEP XCHAL_INT6_TYPE \ 237 XCHAL_SEP XCHAL_INT7_TYPE \ 238 XCHAL_SEP XCHAL_INT8_TYPE \ 239 XCHAL_SEP XCHAL_INT9_TYPE \ 240 XCHAL_SEP XCHAL_INT10_TYPE \ 241 XCHAL_SEP XCHAL_INT11_TYPE \ 242 XCHAL_SEP XCHAL_INT12_TYPE \ 243 XCHAL_SEP XCHAL_INT13_TYPE \ 244 XCHAL_SEP XCHAL_INT14_TYPE \ 245 XCHAL_SEP XCHAL_INT15_TYPE \ 246 XCHAL_SEP XCHAL_INT16_TYPE \ 247 XCHAL_SEP XCHAL_INT17_TYPE \ 248 XCHAL_SEP XCHAL_INT18_TYPE \ 249 XCHAL_SEP XCHAL_INT19_TYPE \ 250 XCHAL_SEP XCHAL_INT20_TYPE \ 251 XCHAL_SEP XCHAL_INT21_TYPE \ 252 XCHAL_SEP XCHAL_INT22_TYPE \ 253 XCHAL_SEP XCHAL_INT23_TYPE \ 254 XCHAL_SEP XCHAL_INT24_TYPE \ 255 XCHAL_SEP XCHAL_INT25_TYPE \ 256 XCHAL_SEP XCHAL_INT26_TYPE \ 257 XCHAL_SEP XCHAL_INT27_TYPE \ 258 XCHAL_SEP XCHAL_INT28_TYPE \ 259 XCHAL_SEP XCHAL_INT29_TYPE \ 260 XCHAL_SEP XCHAL_INT30_TYPE \ 261 XCHAL_SEP XCHAL_INT31_TYPE 262 263 /* Array of masks of interrupts for each type of interrupt: */ 264 #define XCHAL_INTTYPE_MASKS XCHAL_INTTYPE_MASK_UNCONFIGURED \ 265 XCHAL_SEP XCHAL_INTTYPE_MASK_SOFTWARE \ 266 XCHAL_SEP XCHAL_INTTYPE_MASK_EXTERN_EDGE \ 267 XCHAL_SEP XCHAL_INTTYPE_MASK_EXTERN_LEVEL \ 268 XCHAL_SEP XCHAL_INTTYPE_MASK_TIMER \ 269 XCHAL_SEP XCHAL_INTTYPE_MASK_NMI \ 270 XCHAL_SEP XCHAL_INTTYPE_MASK_WRITE_ERROR 271 272 /* Interrupts that can be cleared using the INTCLEAR special register: */ 273 #define XCHAL_INTCLEARABLE_MASK (XCHAL_INTTYPE_MASK_SOFTWARE+XCHAL_INTTYPE_MASK_EXTERN_EDGE+XCHAL_INTTYPE_MASK_WRITE_ERROR) 274 /* Interrupts that can be triggered using the INTSET special register: */ 275 #define XCHAL_INTSETTABLE_MASK XCHAL_INTTYPE_MASK_SOFTWARE 276 277 /* Array of interrupts assigned to each timer (CCOMPARE0 to CCOMPARE3): */ 278 #define XCHAL_TIMER_INTERRUPTS XCHAL_TIMER0_INTERRUPT \ 279 XCHAL_SEP XCHAL_TIMER1_INTERRUPT \ 280 XCHAL_SEP XCHAL_TIMER2_INTERRUPT \ 281 XCHAL_SEP XCHAL_TIMER3_INTERRUPT 282 283 284 285 /* For backward compatibility and for the array macros, define macros for 286 * each unconfigured interrupt number (unfortunately, the value of 287 * XTHAL_INTTYPE_UNCONFIGURED is not zero): */ 288 #if XCHAL_NUM_INTERRUPTS == 0 289 # define XCHAL_INT0_LEVEL 0 290 # define XCHAL_INT0_TYPE XTHAL_INTTYPE_UNCONFIGURED 291 #endif 292 #if XCHAL_NUM_INTERRUPTS <= 1 293 # define XCHAL_INT1_LEVEL 0 294 # define XCHAL_INT1_TYPE XTHAL_INTTYPE_UNCONFIGURED 295 #endif 296 #if XCHAL_NUM_INTERRUPTS <= 2 297 # define XCHAL_INT2_LEVEL 0 298 # define XCHAL_INT2_TYPE XTHAL_INTTYPE_UNCONFIGURED 299 #endif 300 #if XCHAL_NUM_INTERRUPTS <= 3 301 # define XCHAL_INT3_LEVEL 0 302 # define XCHAL_INT3_TYPE XTHAL_INTTYPE_UNCONFIGURED 303 #endif 304 #if XCHAL_NUM_INTERRUPTS <= 4 305 # define XCHAL_INT4_LEVEL 0 306 # define XCHAL_INT4_TYPE XTHAL_INTTYPE_UNCONFIGURED 307 #endif 308 #if XCHAL_NUM_INTERRUPTS <= 5 309 # define XCHAL_INT5_LEVEL 0 310 # define XCHAL_INT5_TYPE XTHAL_INTTYPE_UNCONFIGURED 311 #endif 312 #if XCHAL_NUM_INTERRUPTS <= 6 313 # define XCHAL_INT6_LEVEL 0 314 # define XCHAL_INT6_TYPE XTHAL_INTTYPE_UNCONFIGURED 315 #endif 316 #if XCHAL_NUM_INTERRUPTS <= 7 317 # define XCHAL_INT7_LEVEL 0 318 # define XCHAL_INT7_TYPE XTHAL_INTTYPE_UNCONFIGURED 319 #endif 320 #if XCHAL_NUM_INTERRUPTS <= 8 321 # define XCHAL_INT8_LEVEL 0 322 # define XCHAL_INT8_TYPE XTHAL_INTTYPE_UNCONFIGURED 323 #endif 324 #if XCHAL_NUM_INTERRUPTS <= 9 325 # define XCHAL_INT9_LEVEL 0 326 # define XCHAL_INT9_TYPE XTHAL_INTTYPE_UNCONFIGURED 327 #endif 328 #if XCHAL_NUM_INTERRUPTS <= 10 329 # define XCHAL_INT10_LEVEL 0 330 # define XCHAL_INT10_TYPE XTHAL_INTTYPE_UNCONFIGURED 331 #endif 332 #if XCHAL_NUM_INTERRUPTS <= 11 333 # define XCHAL_INT11_LEVEL 0 334 # define XCHAL_INT11_TYPE XTHAL_INTTYPE_UNCONFIGURED 335 #endif 336 #if XCHAL_NUM_INTERRUPTS <= 12 337 # define XCHAL_INT12_LEVEL 0 338 # define XCHAL_INT12_TYPE XTHAL_INTTYPE_UNCONFIGURED 339 #endif 340 #if XCHAL_NUM_INTERRUPTS <= 13 341 # define XCHAL_INT13_LEVEL 0 342 # define XCHAL_INT13_TYPE XTHAL_INTTYPE_UNCONFIGURED 343 #endif 344 #if XCHAL_NUM_INTERRUPTS <= 14 345 # define XCHAL_INT14_LEVEL 0 346 # define XCHAL_INT14_TYPE XTHAL_INTTYPE_UNCONFIGURED 347 #endif 348 #if XCHAL_NUM_INTERRUPTS <= 15 349 # define XCHAL_INT15_LEVEL 0 350 # define XCHAL_INT15_TYPE XTHAL_INTTYPE_UNCONFIGURED 351 #endif 352 #if XCHAL_NUM_INTERRUPTS <= 16 353 # define XCHAL_INT16_LEVEL 0 354 # define XCHAL_INT16_TYPE XTHAL_INTTYPE_UNCONFIGURED 355 #endif 356 #if XCHAL_NUM_INTERRUPTS <= 17 357 # define XCHAL_INT17_LEVEL 0 358 # define XCHAL_INT17_TYPE XTHAL_INTTYPE_UNCONFIGURED 359 #endif 360 #if XCHAL_NUM_INTERRUPTS <= 18 361 # define XCHAL_INT18_LEVEL 0 362 # define XCHAL_INT18_TYPE XTHAL_INTTYPE_UNCONFIGURED 363 #endif 364 #if XCHAL_NUM_INTERRUPTS <= 19 365 # define XCHAL_INT19_LEVEL 0 366 # define XCHAL_INT19_TYPE XTHAL_INTTYPE_UNCONFIGURED 367 #endif 368 #if XCHAL_NUM_INTERRUPTS <= 20 369 # define XCHAL_INT20_LEVEL 0 370 # define XCHAL_INT20_TYPE XTHAL_INTTYPE_UNCONFIGURED 371 #endif 372 #if XCHAL_NUM_INTERRUPTS <= 21 373 # define XCHAL_INT21_LEVEL 0 374 # define XCHAL_INT21_TYPE XTHAL_INTTYPE_UNCONFIGURED 375 #endif 376 #if XCHAL_NUM_INTERRUPTS <= 22 377 # define XCHAL_INT22_LEVEL 0 378 # define XCHAL_INT22_TYPE XTHAL_INTTYPE_UNCONFIGURED 379 #endif 380 #if XCHAL_NUM_INTERRUPTS <= 23 381 # define XCHAL_INT23_LEVEL 0 382 # define XCHAL_INT23_TYPE XTHAL_INTTYPE_UNCONFIGURED 383 #endif 384 #if XCHAL_NUM_INTERRUPTS <= 24 385 # define XCHAL_INT24_LEVEL 0 386 # define XCHAL_INT24_TYPE XTHAL_INTTYPE_UNCONFIGURED 387 #endif 388 #if XCHAL_NUM_INTERRUPTS <= 25 389 # define XCHAL_INT25_LEVEL 0 390 # define XCHAL_INT25_TYPE XTHAL_INTTYPE_UNCONFIGURED 391 #endif 392 #if XCHAL_NUM_INTERRUPTS <= 26 393 # define XCHAL_INT26_LEVEL 0 394 # define XCHAL_INT26_TYPE XTHAL_INTTYPE_UNCONFIGURED 395 #endif 396 #if XCHAL_NUM_INTERRUPTS <= 27 397 # define XCHAL_INT27_LEVEL 0 398 # define XCHAL_INT27_TYPE XTHAL_INTTYPE_UNCONFIGURED 399 #endif 400 #if XCHAL_NUM_INTERRUPTS <= 28 401 # define XCHAL_INT28_LEVEL 0 402 # define XCHAL_INT28_TYPE XTHAL_INTTYPE_UNCONFIGURED 403 #endif 404 #if XCHAL_NUM_INTERRUPTS <= 29 405 # define XCHAL_INT29_LEVEL 0 406 # define XCHAL_INT29_TYPE XTHAL_INTTYPE_UNCONFIGURED 407 #endif 408 #if XCHAL_NUM_INTERRUPTS <= 30 409 # define XCHAL_INT30_LEVEL 0 410 # define XCHAL_INT30_TYPE XTHAL_INTTYPE_UNCONFIGURED 411 #endif 412 #if XCHAL_NUM_INTERRUPTS <= 31 413 # define XCHAL_INT31_LEVEL 0 414 # define XCHAL_INT31_TYPE XTHAL_INTTYPE_UNCONFIGURED 415 #endif 416 417 418 /* 419 * Masks and levels corresponding to each *external* interrupt. 420 */ 421 422 #define XCHAL_EXTINT0_MASK (1 << XCHAL_EXTINT0_NUM) 423 #define XCHAL_EXTINT0_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT0_NUM) 424 #define XCHAL_EXTINT1_MASK (1 << XCHAL_EXTINT1_NUM) 425 #define XCHAL_EXTINT1_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT1_NUM) 426 #define XCHAL_EXTINT2_MASK (1 << XCHAL_EXTINT2_NUM) 427 #define XCHAL_EXTINT2_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT2_NUM) 428 #define XCHAL_EXTINT3_MASK (1 << XCHAL_EXTINT3_NUM) 429 #define XCHAL_EXTINT3_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT3_NUM) 430 #define XCHAL_EXTINT4_MASK (1 << XCHAL_EXTINT4_NUM) 431 #define XCHAL_EXTINT4_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT4_NUM) 432 #define XCHAL_EXTINT5_MASK (1 << XCHAL_EXTINT5_NUM) 433 #define XCHAL_EXTINT5_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT5_NUM) 434 #define XCHAL_EXTINT6_MASK (1 << XCHAL_EXTINT6_NUM) 435 #define XCHAL_EXTINT6_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT6_NUM) 436 #define XCHAL_EXTINT7_MASK (1 << XCHAL_EXTINT7_NUM) 437 #define XCHAL_EXTINT7_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT7_NUM) 438 #define XCHAL_EXTINT8_MASK (1 << XCHAL_EXTINT8_NUM) 439 #define XCHAL_EXTINT8_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT8_NUM) 440 #define XCHAL_EXTINT9_MASK (1 << XCHAL_EXTINT9_NUM) 441 #define XCHAL_EXTINT9_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT9_NUM) 442 #define XCHAL_EXTINT10_MASK (1 << XCHAL_EXTINT10_NUM) 443 #define XCHAL_EXTINT10_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT10_NUM) 444 #define XCHAL_EXTINT11_MASK (1 << XCHAL_EXTINT11_NUM) 445 #define XCHAL_EXTINT11_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT11_NUM) 446 #define XCHAL_EXTINT12_MASK (1 << XCHAL_EXTINT12_NUM) 447 #define XCHAL_EXTINT12_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT12_NUM) 448 #define XCHAL_EXTINT13_MASK (1 << XCHAL_EXTINT13_NUM) 449 #define XCHAL_EXTINT13_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT13_NUM) 450 #define XCHAL_EXTINT14_MASK (1 << XCHAL_EXTINT14_NUM) 451 #define XCHAL_EXTINT14_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT14_NUM) 452 #define XCHAL_EXTINT15_MASK (1 << XCHAL_EXTINT15_NUM) 453 #define XCHAL_EXTINT15_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT15_NUM) 454 #define XCHAL_EXTINT16_MASK (1 << XCHAL_EXTINT16_NUM) 455 #define XCHAL_EXTINT16_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT16_NUM) 456 #define XCHAL_EXTINT17_MASK (1 << XCHAL_EXTINT17_NUM) 457 #define XCHAL_EXTINT17_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT17_NUM) 458 #define XCHAL_EXTINT18_MASK (1 << XCHAL_EXTINT18_NUM) 459 #define XCHAL_EXTINT18_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT18_NUM) 460 #define XCHAL_EXTINT19_MASK (1 << XCHAL_EXTINT19_NUM) 461 #define XCHAL_EXTINT19_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT19_NUM) 462 #define XCHAL_EXTINT20_MASK (1 << XCHAL_EXTINT20_NUM) 463 #define XCHAL_EXTINT20_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT20_NUM) 464 #define XCHAL_EXTINT21_MASK (1 << XCHAL_EXTINT21_NUM) 465 #define XCHAL_EXTINT21_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT21_NUM) 466 #define XCHAL_EXTINT22_MASK (1 << XCHAL_EXTINT22_NUM) 467 #define XCHAL_EXTINT22_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT22_NUM) 468 #define XCHAL_EXTINT23_MASK (1 << XCHAL_EXTINT23_NUM) 469 #define XCHAL_EXTINT23_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT23_NUM) 470 #define XCHAL_EXTINT24_MASK (1 << XCHAL_EXTINT24_NUM) 471 #define XCHAL_EXTINT24_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT24_NUM) 472 #define XCHAL_EXTINT25_MASK (1 << XCHAL_EXTINT25_NUM) 473 #define XCHAL_EXTINT25_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT25_NUM) 474 #define XCHAL_EXTINT26_MASK (1 << XCHAL_EXTINT26_NUM) 475 #define XCHAL_EXTINT26_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT26_NUM) 476 #define XCHAL_EXTINT27_MASK (1 << XCHAL_EXTINT27_NUM) 477 #define XCHAL_EXTINT27_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT27_NUM) 478 #define XCHAL_EXTINT28_MASK (1 << XCHAL_EXTINT28_NUM) 479 #define XCHAL_EXTINT28_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT28_NUM) 480 #define XCHAL_EXTINT29_MASK (1 << XCHAL_EXTINT29_NUM) 481 #define XCHAL_EXTINT29_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT29_NUM) 482 #define XCHAL_EXTINT30_MASK (1 << XCHAL_EXTINT30_NUM) 483 #define XCHAL_EXTINT30_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT30_NUM) 484 #define XCHAL_EXTINT31_MASK (1 << XCHAL_EXTINT31_NUM) 485 #define XCHAL_EXTINT31_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT31_NUM) 486 487 488 /*---------------------------------------------------------------------- 489 EXCEPTIONS and VECTORS 490 ----------------------------------------------------------------------*/ 491 492 /* For backward compatibility ONLY -- DO NOT USE (will be removed in future release): */ 493 #define XCHAL_HAVE_OLD_EXC_ARCH XCHAL_HAVE_XEA1 /* (DEPRECATED) 1 if old exception architecture (XEA1), 0 otherwise (eg. XEA2) */ 494 #define XCHAL_HAVE_EXCM XCHAL_HAVE_XEA2 /* (DEPRECATED) 1 if PS.EXCM bit exists (currently equals XCHAL_HAVE_TLBS) */ 495 #ifdef XCHAL_USER_VECTOR_VADDR 496 #define XCHAL_PROGRAMEXC_VECTOR_VADDR XCHAL_USER_VECTOR_VADDR 497 #define XCHAL_USEREXC_VECTOR_VADDR XCHAL_USER_VECTOR_VADDR 498 #endif 499 #ifdef XCHAL_USER_VECTOR_PADDR 500 # define XCHAL_PROGRAMEXC_VECTOR_PADDR XCHAL_USER_VECTOR_PADDR 501 # define XCHAL_USEREXC_VECTOR_PADDR XCHAL_USER_VECTOR_PADDR 502 #endif 503 #ifdef XCHAL_KERNEL_VECTOR_VADDR 504 # define XCHAL_STACKEDEXC_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR 505 # define XCHAL_KERNELEXC_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR 506 #endif 507 #ifdef XCHAL_KERNEL_VECTOR_PADDR 508 # define XCHAL_STACKEDEXC_VECTOR_PADDR XCHAL_KERNEL_VECTOR_PADDR 509 # define XCHAL_KERNELEXC_VECTOR_PADDR XCHAL_KERNEL_VECTOR_PADDR 510 #endif 511 512 #if 0 513 #if XCHAL_HAVE_DEBUG 514 # define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL_VECTOR_VADDR(XCHAL_DEBUGLEVEL) 515 /* This one should only get defined if the corresponding intlevel paddr macro exists: */ 516 # define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL_VECTOR_PADDR(XCHAL_DEBUGLEVEL) 517 #endif 518 #endif 519 520 /* Indexing macros: */ 521 #define _XCHAL_INTLEVEL_VECTOR_VADDR(n) XCHAL_INTLEVEL ## n ## _VECTOR_VADDR 522 #define XCHAL_INTLEVEL_VECTOR_VADDR(n) _XCHAL_INTLEVEL_VECTOR_VADDR(n) /* n = 0 .. 15 */ 523 524 /* 525 * General Exception Causes 526 * (values of EXCCAUSE special register set by general exceptions, 527 * which vector to the user, kernel, or double-exception vectors). 528 * 529 * DEPRECATED. Please use the equivalent EXCCAUSE_xxx macros 530 * defined in <xtensa/corebits.h>. (Note that these have slightly 531 * different names, they don't just have the XCHAL_ prefix removed.) 532 */ 533 #define XCHAL_EXCCAUSE_ILLEGAL_INSTRUCTION 0 /* Illegal Instruction */ 534 #define XCHAL_EXCCAUSE_SYSTEM_CALL 1 /* System Call */ 535 #define XCHAL_EXCCAUSE_INSTRUCTION_FETCH_ERROR 2 /* Instruction Fetch Error */ 536 #define XCHAL_EXCCAUSE_LOAD_STORE_ERROR 3 /* Load Store Error */ 537 #define XCHAL_EXCCAUSE_LEVEL1_INTERRUPT 4 /* Level 1 Interrupt */ 538 #define XCHAL_EXCCAUSE_ALLOCA 5 /* Stack Extension Assist */ 539 #define XCHAL_EXCCAUSE_INTEGER_DIVIDE_BY_ZERO 6 /* Integer Divide by Zero */ 540 #define XCHAL_EXCCAUSE_SPECULATION 7 /* Speculation */ 541 #define XCHAL_EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction */ 542 #define XCHAL_EXCCAUSE_UNALIGNED 9 /* Unaligned Load Store */ 543 /*10..15 reserved*/ 544 #define XCHAL_EXCCAUSE_ITLB_MISS 16 /* ITlb Miss Exception */ 545 #define XCHAL_EXCCAUSE_ITLB_MULTIHIT 17 /* ITlb Mutltihit Exception */ 546 #define XCHAL_EXCCAUSE_ITLB_PRIVILEGE 18 /* ITlb Privilege Exception */ 547 #define XCHAL_EXCCAUSE_ITLB_SIZE_RESTRICTION 19 /* ITlb Size Restriction Exception */ 548 #define XCHAL_EXCCAUSE_FETCH_CACHE_ATTRIBUTE 20 /* Fetch Cache Attribute Exception */ 549 /*21..23 reserved*/ 550 #define XCHAL_EXCCAUSE_DTLB_MISS 24 /* DTlb Miss Exception */ 551 #define XCHAL_EXCCAUSE_DTLB_MULTIHIT 25 /* DTlb Multihit Exception */ 552 #define XCHAL_EXCCAUSE_DTLB_PRIVILEGE 26 /* DTlb Privilege Exception */ 553 #define XCHAL_EXCCAUSE_DTLB_SIZE_RESTRICTION 27 /* DTlb Size Restriction Exception */ 554 #define XCHAL_EXCCAUSE_LOAD_CACHE_ATTRIBUTE 28 /* Load Cache Attribute Exception */ 555 #define XCHAL_EXCCAUSE_STORE_CACHE_ATTRIBUTE 29 /* Store Cache Attribute Exception */ 556 /*30..31 reserved*/ 557 #define XCHAL_EXCCAUSE_COPROCESSOR0_DISABLED 32 /* Coprocessor 0 disabled */ 558 #define XCHAL_EXCCAUSE_COPROCESSOR1_DISABLED 33 /* Coprocessor 1 disabled */ 559 #define XCHAL_EXCCAUSE_COPROCESSOR2_DISABLED 34 /* Coprocessor 2 disabled */ 560 #define XCHAL_EXCCAUSE_COPROCESSOR3_DISABLED 35 /* Coprocessor 3 disabled */ 561 #define XCHAL_EXCCAUSE_COPROCESSOR4_DISABLED 36 /* Coprocessor 4 disabled */ 562 #define XCHAL_EXCCAUSE_COPROCESSOR5_DISABLED 37 /* Coprocessor 5 disabled */ 563 #define XCHAL_EXCCAUSE_COPROCESSOR6_DISABLED 38 /* Coprocessor 6 disabled */ 564 #define XCHAL_EXCCAUSE_COPROCESSOR7_DISABLED 39 /* Coprocessor 7 disabled */ 565 /*40..63 reserved*/ 566 567 568 /* 569 * Miscellaneous special register fields. 570 * 571 * For each special register, and each field within each register: 572 * XCHAL_<regname>_VALIDMASK is the set of bits defined in the register. 573 * XCHAL_<regname>_<field>_BITS is the number of bits in the field. 574 * XCHAL_<regname>_<field>_NUM is 2^bits, the number of possible values 575 * of the field. 576 * XCHAL_<regname>_<field>_SHIFT is the position of the field within 577 * the register, starting from the least significant bit. 578 * 579 * DEPRECATED. Please use the equivalent macros defined in 580 * <xtensa/corebits.h>. (Note that these have different names.) 581 */ 582 583 /* DBREAKC (special register number 160): */ 584 #define XCHAL_DBREAKC_VALIDMASK 0xC000003F 585 #define XCHAL_DBREAKC_MASK_BITS 6 586 #define XCHAL_DBREAKC_MASK_NUM 64 587 #define XCHAL_DBREAKC_MASK_SHIFT 0 588 #define XCHAL_DBREAKC_MASK_MASK 0x0000003F 589 #define XCHAL_DBREAKC_LOADBREAK_BITS 1 590 #define XCHAL_DBREAKC_LOADBREAK_NUM 2 591 #define XCHAL_DBREAKC_LOADBREAK_SHIFT 30 592 #define XCHAL_DBREAKC_LOADBREAK_MASK 0x40000000 593 #define XCHAL_DBREAKC_STOREBREAK_BITS 1 594 #define XCHAL_DBREAKC_STOREBREAK_NUM 2 595 #define XCHAL_DBREAKC_STOREBREAK_SHIFT 31 596 #define XCHAL_DBREAKC_STOREBREAK_MASK 0x80000000 597 /* PS (special register number 230): */ 598 #define XCHAL_PS_VALIDMASK 0x00070F3F 599 #define XCHAL_PS_INTLEVEL_BITS 4 600 #define XCHAL_PS_INTLEVEL_NUM 16 601 #define XCHAL_PS_INTLEVEL_SHIFT 0 602 #define XCHAL_PS_INTLEVEL_MASK 0x0000000F 603 #define XCHAL_PS_EXCM_BITS 1 604 #define XCHAL_PS_EXCM_NUM 2 605 #define XCHAL_PS_EXCM_SHIFT 4 606 #define XCHAL_PS_EXCM_MASK 0x00000010 607 #define XCHAL_PS_UM_BITS 1 608 #define XCHAL_PS_UM_NUM 2 609 #define XCHAL_PS_UM_SHIFT 5 610 #define XCHAL_PS_UM_MASK 0x00000020 611 #define XCHAL_PS_RING_BITS 2 612 #define XCHAL_PS_RING_NUM 4 613 #define XCHAL_PS_RING_SHIFT 6 614 #define XCHAL_PS_RING_MASK 0x000000C0 615 #define XCHAL_PS_OWB_BITS 4 616 #define XCHAL_PS_OWB_NUM 16 617 #define XCHAL_PS_OWB_SHIFT 8 618 #define XCHAL_PS_OWB_MASK 0x00000F00 619 #define XCHAL_PS_CALLINC_BITS 2 620 #define XCHAL_PS_CALLINC_NUM 4 621 #define XCHAL_PS_CALLINC_SHIFT 16 622 #define XCHAL_PS_CALLINC_MASK 0x00030000 623 #define XCHAL_PS_WOE_BITS 1 624 #define XCHAL_PS_WOE_NUM 2 625 #define XCHAL_PS_WOE_SHIFT 18 626 #define XCHAL_PS_WOE_MASK 0x00040000 627 /* EXCCAUSE (special register number 232): */ 628 #define XCHAL_EXCCAUSE_VALIDMASK 0x0000003F 629 #define XCHAL_EXCCAUSE_BITS 6 630 #define XCHAL_EXCCAUSE_NUM 64 631 #define XCHAL_EXCCAUSE_SHIFT 0 632 #define XCHAL_EXCCAUSE_MASK 0x0000003F 633 /* DEBUGCAUSE (special register number 233): */ 634 #define XCHAL_DEBUGCAUSE_VALIDMASK 0x0000003F 635 #define XCHAL_DEBUGCAUSE_ICOUNT_BITS 1 636 #define XCHAL_DEBUGCAUSE_ICOUNT_NUM 2 637 #define XCHAL_DEBUGCAUSE_ICOUNT_SHIFT 0 638 #define XCHAL_DEBUGCAUSE_ICOUNT_MASK 0x00000001 639 #define XCHAL_DEBUGCAUSE_IBREAK_BITS 1 640 #define XCHAL_DEBUGCAUSE_IBREAK_NUM 2 641 #define XCHAL_DEBUGCAUSE_IBREAK_SHIFT 1 642 #define XCHAL_DEBUGCAUSE_IBREAK_MASK 0x00000002 643 #define XCHAL_DEBUGCAUSE_DBREAK_BITS 1 644 #define XCHAL_DEBUGCAUSE_DBREAK_NUM 2 645 #define XCHAL_DEBUGCAUSE_DBREAK_SHIFT 2 646 #define XCHAL_DEBUGCAUSE_DBREAK_MASK 0x00000004 647 #define XCHAL_DEBUGCAUSE_BREAK_BITS 1 648 #define XCHAL_DEBUGCAUSE_BREAK_NUM 2 649 #define XCHAL_DEBUGCAUSE_BREAK_SHIFT 3 650 #define XCHAL_DEBUGCAUSE_BREAK_MASK 0x00000008 651 #define XCHAL_DEBUGCAUSE_BREAKN_BITS 1 652 #define XCHAL_DEBUGCAUSE_BREAKN_NUM 2 653 #define XCHAL_DEBUGCAUSE_BREAKN_SHIFT 4 654 #define XCHAL_DEBUGCAUSE_BREAKN_MASK 0x00000010 655 #define XCHAL_DEBUGCAUSE_DEBUGINT_BITS 1 656 #define XCHAL_DEBUGCAUSE_DEBUGINT_NUM 2 657 #define XCHAL_DEBUGCAUSE_DEBUGINT_SHIFT 5 658 #define XCHAL_DEBUGCAUSE_DEBUGINT_MASK 0x00000020 659 660 661 662 663 /*---------------------------------------------------------------------- 664 TIMERS 665 ----------------------------------------------------------------------*/ 666 667 /*#define XCHAL_HAVE_TIMERS XCHAL_HAVE_CCOUNT*/ 668 669 670 671 /*---------------------------------------------------------------------- 672 INTERNAL I/D RAM/ROMs and XLMI 673 ----------------------------------------------------------------------*/ 674 675 #define XCHAL_NUM_IROM XCHAL_NUM_INSTROM /* (DEPRECATED) */ 676 #define XCHAL_NUM_IRAM XCHAL_NUM_INSTRAM /* (DEPRECATED) */ 677 #define XCHAL_NUM_DROM XCHAL_NUM_DATAROM /* (DEPRECATED) */ 678 #define XCHAL_NUM_DRAM XCHAL_NUM_DATARAM /* (DEPRECATED) */ 679 680 #define XCHAL_IROM0_VADDR XCHAL_INSTROM0_VADDR /* (DEPRECATED) */ 681 #define XCHAL_IROM0_PADDR XCHAL_INSTROM0_PADDR /* (DEPRECATED) */ 682 #define XCHAL_IROM0_SIZE XCHAL_INSTROM0_SIZE /* (DEPRECATED) */ 683 #define XCHAL_IROM1_VADDR XCHAL_INSTROM1_VADDR /* (DEPRECATED) */ 684 #define XCHAL_IROM1_PADDR XCHAL_INSTROM1_PADDR /* (DEPRECATED) */ 685 #define XCHAL_IROM1_SIZE XCHAL_INSTROM1_SIZE /* (DEPRECATED) */ 686 #define XCHAL_IRAM0_VADDR XCHAL_INSTRAM0_VADDR /* (DEPRECATED) */ 687 #define XCHAL_IRAM0_PADDR XCHAL_INSTRAM0_PADDR /* (DEPRECATED) */ 688 #define XCHAL_IRAM0_SIZE XCHAL_INSTRAM0_SIZE /* (DEPRECATED) */ 689 #define XCHAL_IRAM1_VADDR XCHAL_INSTRAM1_VADDR /* (DEPRECATED) */ 690 #define XCHAL_IRAM1_PADDR XCHAL_INSTRAM1_PADDR /* (DEPRECATED) */ 691 #define XCHAL_IRAM1_SIZE XCHAL_INSTRAM1_SIZE /* (DEPRECATED) */ 692 #define XCHAL_DROM0_VADDR XCHAL_DATAROM0_VADDR /* (DEPRECATED) */ 693 #define XCHAL_DROM0_PADDR XCHAL_DATAROM0_PADDR /* (DEPRECATED) */ 694 #define XCHAL_DROM0_SIZE XCHAL_DATAROM0_SIZE /* (DEPRECATED) */ 695 #define XCHAL_DROM1_VADDR XCHAL_DATAROM1_VADDR /* (DEPRECATED) */ 696 #define XCHAL_DROM1_PADDR XCHAL_DATAROM1_PADDR /* (DEPRECATED) */ 697 #define XCHAL_DROM1_SIZE XCHAL_DATAROM1_SIZE /* (DEPRECATED) */ 698 #define XCHAL_DRAM0_VADDR XCHAL_DATARAM0_VADDR /* (DEPRECATED) */ 699 #define XCHAL_DRAM0_PADDR XCHAL_DATARAM0_PADDR /* (DEPRECATED) */ 700 #define XCHAL_DRAM0_SIZE XCHAL_DATARAM0_SIZE /* (DEPRECATED) */ 701 #define XCHAL_DRAM1_VADDR XCHAL_DATARAM1_VADDR /* (DEPRECATED) */ 702 #define XCHAL_DRAM1_PADDR XCHAL_DATARAM1_PADDR /* (DEPRECATED) */ 703 #define XCHAL_DRAM1_SIZE XCHAL_DATARAM1_SIZE /* (DEPRECATED) */ 704 705 706 707 /*---------------------------------------------------------------------- 708 CACHE 709 ----------------------------------------------------------------------*/ 710 711 712 /* Default PREFCTL value to enable prefetch. */ 713 #if XCHAL_HW_MIN_VERSION < XTENSA_HWVERSION_RE_2012_0 714 #define XCHAL_CACHE_PREFCTL_DEFAULT 0x00044 /* enabled, not aggressive */ 715 #elif XCHAL_HW_MIN_VERSION < XTENSA_HWVERSION_RF_2014_0 716 #define XCHAL_CACHE_PREFCTL_DEFAULT 0x01044 /* + enable prefetch to L1 */ 717 #elif XCHAL_PREFETCH_ENTRIES >= 16 718 #define XCHAL_CACHE_PREFCTL_DEFAULT 0x81044 /* 12 entries for block ops */ 719 #elif XCHAL_PREFETCH_ENTRIES >= 8 720 #define XCHAL_CACHE_PREFCTL_DEFAULT 0x51044 /* 5 entries for block ops */ 721 #else 722 #define XCHAL_CACHE_PREFCTL_DEFAULT 0x01044 /* 0 entries for block ops */ 723 #endif 724 725 726 /* Max for both I-cache and D-cache (used for general alignment): */ 727 #if XCHAL_ICACHE_LINESIZE > XCHAL_DCACHE_LINESIZE 728 # define XCHAL_CACHE_LINEWIDTH_MAX XCHAL_ICACHE_LINEWIDTH 729 # define XCHAL_CACHE_LINESIZE_MAX XCHAL_ICACHE_LINESIZE 730 #else 731 # define XCHAL_CACHE_LINEWIDTH_MAX XCHAL_DCACHE_LINEWIDTH 732 # define XCHAL_CACHE_LINESIZE_MAX XCHAL_DCACHE_LINESIZE 733 #endif 734 735 #define XCHAL_ICACHE_SETSIZE (1<<XCHAL_ICACHE_SETWIDTH) 736 #define XCHAL_DCACHE_SETSIZE (1<<XCHAL_DCACHE_SETWIDTH) 737 /* Max for both I and D caches (used for cache-coherency page alignment): */ 738 #if XCHAL_ICACHE_SETWIDTH > XCHAL_DCACHE_SETWIDTH 739 # define XCHAL_CACHE_SETWIDTH_MAX XCHAL_ICACHE_SETWIDTH 740 # define XCHAL_CACHE_SETSIZE_MAX XCHAL_ICACHE_SETSIZE 741 #else 742 # define XCHAL_CACHE_SETWIDTH_MAX XCHAL_DCACHE_SETWIDTH 743 # define XCHAL_CACHE_SETSIZE_MAX XCHAL_DCACHE_SETSIZE 744 #endif 745 746 /* Instruction cache tag bits: */ 747 #define XCHAL_ICACHE_TAG_V_SHIFT 0 748 #define XCHAL_ICACHE_TAG_V 0x1 /* valid bit */ 749 #if XCHAL_ICACHE_WAYS > 1 750 # define XCHAL_ICACHE_TAG_F_SHIFT 1 751 # define XCHAL_ICACHE_TAG_F 0x2 /* fill (LRU) bit */ 752 #else 753 # define XCHAL_ICACHE_TAG_F_SHIFT 0 754 # define XCHAL_ICACHE_TAG_F 0 /* no fill (LRU) bit */ 755 #endif 756 #if XCHAL_ICACHE_LINE_LOCKABLE 757 # define XCHAL_ICACHE_TAG_L_SHIFT (XCHAL_ICACHE_TAG_F_SHIFT+1) 758 # define XCHAL_ICACHE_TAG_L (1 << XCHAL_ICACHE_TAG_L_SHIFT) /* lock bit */ 759 #else 760 # define XCHAL_ICACHE_TAG_L_SHIFT XCHAL_ICACHE_TAG_F_SHIFT 761 # define XCHAL_ICACHE_TAG_L 0 /* no lock bit */ 762 #endif 763 /* Data cache tag bits: */ 764 #define XCHAL_DCACHE_TAG_V_SHIFT 0 765 #define XCHAL_DCACHE_TAG_V 0x1 /* valid bit */ 766 #if XCHAL_DCACHE_WAYS > 1 767 # define XCHAL_DCACHE_TAG_F_SHIFT 1 768 # define XCHAL_DCACHE_TAG_F 0x2 /* fill (LRU) bit */ 769 #else 770 # define XCHAL_DCACHE_TAG_F_SHIFT 0 771 # define XCHAL_DCACHE_TAG_F 0 /* no fill (LRU) bit */ 772 #endif 773 #if XCHAL_DCACHE_IS_WRITEBACK 774 # define XCHAL_DCACHE_TAG_D_SHIFT (XCHAL_DCACHE_TAG_F_SHIFT+1) 775 # define XCHAL_DCACHE_TAG_D (1 << XCHAL_DCACHE_TAG_D_SHIFT) /* dirty bit */ 776 #else 777 # define XCHAL_DCACHE_TAG_D_SHIFT XCHAL_DCACHE_TAG_F_SHIFT 778 # define XCHAL_DCACHE_TAG_D 0 /* no dirty bit */ 779 #endif 780 #if XCHAL_DCACHE_LINE_LOCKABLE 781 # define XCHAL_DCACHE_TAG_L_SHIFT (XCHAL_DCACHE_TAG_D_SHIFT+1) 782 # define XCHAL_DCACHE_TAG_L (1 << XCHAL_DCACHE_TAG_L_SHIFT) /* lock bit */ 783 #else 784 # define XCHAL_DCACHE_TAG_L_SHIFT XCHAL_DCACHE_TAG_D_SHIFT 785 # define XCHAL_DCACHE_TAG_L 0 /* no lock bit */ 786 #endif 787 788 /* Whether MEMCTL register has anything useful */ 789 #define XCHAL_USE_MEMCTL (((XCHAL_LOOP_BUFFER_SIZE > 0) || \ 790 XCHAL_DCACHE_IS_COHERENT || \ 791 XCHAL_HAVE_ICACHE_DYN_WAYS || \ 792 XCHAL_HAVE_DCACHE_DYN_WAYS) && \ 793 (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0)) 794 795 /* Default MEMCTL values: */ 796 #if XCHAL_HAVE_ICACHE_DYN_WAYS || XCHAL_HAVE_DCACHE_DYN_WAYS 797 /* NOTE: constant defined this way to allow movi instead of l32r in reset code. */ 798 #define XCHAL_CACHE_MEMCTL_DEFAULT 0xFFFFFF00 /* Init all possible ways */ 799 #else 800 #define XCHAL_CACHE_MEMCTL_DEFAULT 0x00000000 /* Nothing to do */ 801 #endif 802 803 #if XCHAL_DCACHE_IS_COHERENT 804 #define _MEMCTL_SNOOP_EN 0x02 /* Enable snoop */ 805 #else 806 #define _MEMCTL_SNOOP_EN 0x00 /* Don't enable snoop */ 807 #endif 808 809 #if (XCHAL_LOOP_BUFFER_SIZE == 0) || XCHAL_ERRATUM_453 810 #define _MEMCTL_L0IBUF_EN 0x00 /* No loop buffer or don't enable */ 811 #else 812 #define _MEMCTL_L0IBUF_EN 0x01 /* Enable loop buffer */ 813 #endif 814 815 #define XCHAL_SNOOP_LB_MEMCTL_DEFAULT (_MEMCTL_SNOOP_EN | _MEMCTL_L0IBUF_EN) 816 817 818 /*---------------------------------------------------------------------- 819 MMU 820 ----------------------------------------------------------------------*/ 821 822 /* See <xtensa/config/core-matmap.h> for more details. */ 823 824 /* Has different semantic in open source headers (where it means HAVE_PTP_MMU), 825 so comment out starting with RB-2008.3 release; later, might get 826 get reintroduced as a synonym for XCHAL_HAVE_PTP_MMU instead: */ 827 /*#define XCHAL_HAVE_MMU XCHAL_HAVE_TLBS*/ /* (DEPRECATED; use XCHAL_HAVE_TLBS instead) */ 828 829 /* Indexing macros: */ 830 #define _XCHAL_ITLB_SET(n,_what) XCHAL_ITLB_SET ## n ## _what 831 #define XCHAL_ITLB_SET(n,what) _XCHAL_ITLB_SET(n, _ ## what ) 832 #define _XCHAL_ITLB_SET_E(n,i,_what) XCHAL_ITLB_SET ## n ## _E ## i ## _what 833 #define XCHAL_ITLB_SET_E(n,i,what) _XCHAL_ITLB_SET_E(n,i, _ ## what ) 834 #define _XCHAL_DTLB_SET(n,_what) XCHAL_DTLB_SET ## n ## _what 835 #define XCHAL_DTLB_SET(n,what) _XCHAL_DTLB_SET(n, _ ## what ) 836 #define _XCHAL_DTLB_SET_E(n,i,_what) XCHAL_DTLB_SET ## n ## _E ## i ## _what 837 #define XCHAL_DTLB_SET_E(n,i,what) _XCHAL_DTLB_SET_E(n,i, _ ## what ) 838 /* 839 * Example use: XCHAL_ITLB_SET(XCHAL_ITLB_ARF_SET0,ENTRIES) 840 * to get the value of XCHAL_ITLB_SET<n>_ENTRIES where <n> is the first auto-refill set. 841 */ 842 843 /* Number of entries per autorefill way: */ 844 #define XCHAL_ITLB_ARF_ENTRIES (1<<XCHAL_ITLB_ARF_ENTRIES_LOG2) 845 #define XCHAL_DTLB_ARF_ENTRIES (1<<XCHAL_DTLB_ARF_ENTRIES_LOG2) 846 847 /* 848 * Determine whether we have a full MMU (with Page Table and Protection) 849 * usable for an MMU-based OS: 850 */ 851 #if 0 852 #if XCHAL_HAVE_TLBS && !XCHAL_HAVE_SPANNING_WAY && XCHAL_ITLB_ARF_WAYS > 0 && XCHAL_DTLB_ARF_WAYS > 0 && XCHAL_MMU_RINGS >= 2 853 # define XCHAL_HAVE_PTP_MMU 1 /* have full MMU (with page table [autorefill] and protection) */ 854 #else 855 # define XCHAL_HAVE_PTP_MMU 0 /* don't have full MMU */ 856 #endif 857 #endif 858 859 /* 860 * For full MMUs, report kernel RAM segment and kernel I/O segment static page mappings: 861 */ 862 #if XCHAL_HAVE_PTP_MMU && !XCHAL_HAVE_SPANNING_WAY 863 #define XCHAL_KSEG_CACHED_VADDR 0xD0000000 /* virt.addr of kernel RAM cached static map */ 864 #define XCHAL_KSEG_CACHED_PADDR 0x00000000 /* phys.addr of kseg_cached */ 865 #define XCHAL_KSEG_CACHED_SIZE 0x08000000 /* size in bytes of kseg_cached (assumed power of 2!!!) */ 866 #define XCHAL_KSEG_BYPASS_VADDR 0xD8000000 /* virt.addr of kernel RAM bypass (uncached) static map */ 867 #define XCHAL_KSEG_BYPASS_PADDR 0x00000000 /* phys.addr of kseg_bypass */ 868 #define XCHAL_KSEG_BYPASS_SIZE 0x08000000 /* size in bytes of kseg_bypass (assumed power of 2!!!) */ 869 870 #define XCHAL_KIO_CACHED_VADDR 0xE0000000 /* virt.addr of kernel I/O cached static map */ 871 #define XCHAL_KIO_CACHED_PADDR 0xF0000000 /* phys.addr of kio_cached */ 872 #define XCHAL_KIO_CACHED_SIZE 0x10000000 /* size in bytes of kio_cached (assumed power of 2!!!) */ 873 #define XCHAL_KIO_BYPASS_VADDR 0xF0000000 /* virt.addr of kernel I/O bypass (uncached) static map */ 874 #define XCHAL_KIO_BYPASS_PADDR 0xF0000000 /* phys.addr of kio_bypass */ 875 #define XCHAL_KIO_BYPASS_SIZE 0x10000000 /* size in bytes of kio_bypass (assumed power of 2!!!) */ 876 877 #define XCHAL_SEG_MAPPABLE_VADDR 0x00000000 /* start of largest non-static-mapped virtual addr area */ 878 #define XCHAL_SEG_MAPPABLE_SIZE 0xD0000000 /* size in bytes of " */ 879 /* define XCHAL_SEG_MAPPABLE2_xxx if more areas present, sorted in order of descending size. */ 880 #endif 881 882 883 /*---------------------------------------------------------------------- 884 MISC 885 ----------------------------------------------------------------------*/ 886 887 /* Data alignment required if used for instructions: */ 888 #if XCHAL_INST_FETCH_WIDTH > XCHAL_DATA_WIDTH 889 # define XCHAL_ALIGN_MAX XCHAL_INST_FETCH_WIDTH 890 #else 891 # define XCHAL_ALIGN_MAX XCHAL_DATA_WIDTH 892 #endif 893 894 /* 895 * Names kept for backward compatibility. 896 * (Here "RELEASE" is now a misnomer; these are product *versions*, not the releases 897 * under which they are released. In the T10##.# era there was no distinction.) 898 */ 899 #define XCHAL_HW_RELEASE_MAJOR XCHAL_HW_VERSION_MAJOR 900 #define XCHAL_HW_RELEASE_MINOR XCHAL_HW_VERSION_MINOR 901 #define XCHAL_HW_RELEASE_NAME XCHAL_HW_VERSION_NAME 902 903 904 905 906 /*---------------------------------------------------------------------- 907 COPROCESSORS and EXTRA STATE 908 ----------------------------------------------------------------------*/ 909 910 #define XCHAL_EXTRA_SA_SIZE XCHAL_NCP_SA_SIZE 911 #define XCHAL_EXTRA_SA_ALIGN XCHAL_NCP_SA_ALIGN 912 #define XCHAL_CPEXTRA_SA_SIZE XCHAL_TOTAL_SA_SIZE 913 #define XCHAL_CPEXTRA_SA_ALIGN XCHAL_TOTAL_SA_ALIGN 914 915 #if defined (_ASMLANGUAGE) || defined (__ASSEMBLER__) 916 917 /* Invoked at start of save area load/store sequence macro to setup macro 918 * internal offsets. Not usually invoked directly. 919 * continue 0 for 1st sequence, 1 for subsequent consecutive ones. 920 * totofs offset from original ptr to next load/store location. 921 */ 922 .macro xchal_sa_start continue totofs 923 .ifeq \continue 924 .set .Lxchal_pofs_, 0 /* offset from original ptr to current \ptr */ 925 .set .Lxchal_ofs_, 0 /* offset from current \ptr to next load/store location */ 926 .endif 927 .if \totofs + 1 /* if totofs specified (not -1) */ 928 .set .Lxchal_ofs_, \totofs - .Lxchal_pofs_ /* specific offset from original ptr */ 929 .endif 930 .endm 931 932 /* Align portion of save area and bring ptr in range if necessary. 933 * Used by save area load/store sequences. Not usually invoked directly. 934 * Allows combining multiple (sub-)sequences arbitrarily. 935 * ptr pointer to save area (may be off, see .Lxchal_pofs_) 936 * minofs,maxofs range of offset from cur ptr to next load/store loc; 937 * minofs <= 0 <= maxofs (0 must always be valid offset) 938 * range must be within +/- 30kB or so. 939 * ofsalign alignment granularity of minofs .. maxofs (pow of 2) 940 * (restriction on offset from ptr to next load/store loc) 941 * totalign align from orig ptr to next load/store loc (pow of 2) 942 */ 943 .macro xchal_sa_align ptr minofs maxofs ofsalign totalign 944 /* First align where we start accessing the next register 945 * per \totalign relative to original ptr (i.e. start of the save area): 946 */ 947 .set .Lxchal_ofs_, ((.Lxchal_pofs_ + .Lxchal_ofs_ + \totalign - 1) & -\totalign) - .Lxchal_pofs_ 948 /* If necessary, adjust \ptr to bring .Lxchal_ofs_ in acceptable range: */ 949 .if (((\maxofs) - .Lxchal_ofs_) & 0xC0000000) | ((.Lxchal_ofs_ - (\minofs)) & 0xC0000000) | (.Lxchal_ofs_ & (\ofsalign-1)) 950 .set .Ligmask, 0xFFFFFFFF /* TODO: optimize to addmi, per aligns and .Lxchal_ofs_ */ 951 addi \ptr, \ptr, (.Lxchal_ofs_ & .Ligmask) 952 .set .Lxchal_pofs_, .Lxchal_pofs_ + (.Lxchal_ofs_ & .Ligmask) 953 .set .Lxchal_ofs_, (.Lxchal_ofs_ & ~.Ligmask) 954 .endif 955 .endm 956 /* 957 * We could optimize for addi to expand to only addmi instead of 958 * "addmi;addi", where possible. Here's a partial example how: 959 * .set .Lmaxmask, -(\ofsalign) & -(\totalign) 960 * .if (((\maxofs) + ~.Lmaxmask + 1) & 0xFFFFFF00) && ((.Lxchal_ofs_ & ~.Lmaxmask) == 0) 961 * .set .Ligmask, 0xFFFFFF00 962 * .elif ... ditto for negative ofs range ... 963 * .set .Ligmask, 0xFFFFFF00 964 * .set ... adjust per offset ... 965 * .else 966 * .set .Ligmask, 0xFFFFFFFF 967 * .endif 968 */ 969 970 /* Invoke this after xchal_XXX_{load,store} macros to restore \ptr. */ 971 .macro xchal_sa_ptr_restore ptr 972 .if .Lxchal_pofs_ 973 addi \ptr, \ptr, - .Lxchal_pofs_ 974 .set .Lxchal_ofs_, .Lxchal_ofs_ + .Lxchal_pofs_ 975 .set .Lxchal_pofs_, 0 976 .endif 977 .endm 978 979 /* 980 * Use as eg: 981 * xchal_atmps_store a1, SOMEOFS, XCHAL_SA_NUM_ATMPS, a4, a5 982 * xchal_ncp_load a2, a0,a3,a4,a5 983 * xchal_atmps_load a1, SOMEOFS, XCHAL_SA_NUM_ATMPS, a4, a5 984 * 985 * Specify only the ARs you *haven't* saved/restored already, up to 4. 986 * They *must* be the *last* ARs (in same order) specified to save area 987 * load/store sequences. In the example above, a0 and a3 were already 988 * saved/restored and unused (thus available) but a4 and a5 were not. 989 */ 990 #define xchal_atmps_store xchal_atmps_loadstore s32i, 991 #define xchal_atmps_load xchal_atmps_loadstore l32i, 992 .macro xchal_atmps_loadstore inst ptr offset nreq aa=0 ab=0 ac=0 ad=0 993 .set .Lnsaved_, 0 994 .irp reg,\aa,\ab,\ac,\ad 995 .ifeq 0x\reg ; .set .Lnsaved_,.Lnsaved_+1 ; .endif 996 .endr 997 .set .Laofs_, 0 998 .irp reg,\aa,\ab,\ac,\ad 999 .ifgt (\nreq)-.Lnsaved_ 1000 \inst \reg, \ptr, .Laofs_+\offset 1001 .set .Laofs_,.Laofs_+4 1002 .set .Lnsaved_,.Lnsaved_+1 1003 .endif 1004 .endr 1005 .endm 1006 1007 /*#define xchal_ncp_load_a2 xchal_ncp_load a2,a3,a4,a5,a6*/ 1008 /*#define xchal_ncp_store_a2 xchal_ncp_store a2,a3,a4,a5,a6*/ 1009 #define xchal_extratie_load xchal_ncptie_load 1010 #define xchal_extratie_store xchal_ncptie_store 1011 #define xchal_extratie_load_a2 xchal_ncptie_load a2,a3,a4,a5,a6 1012 #define xchal_extratie_store_a2 xchal_ncptie_store a2,a3,a4,a5,a6 1013 #define xchal_extra_load xchal_ncp_load 1014 #define xchal_extra_store xchal_ncp_store 1015 #define xchal_extra_load_a2 xchal_ncp_load a2,a3,a4,a5,a6 1016 #define xchal_extra_store_a2 xchal_ncp_store a2,a3,a4,a5,a6 1017 #define xchal_extra_load_funcbody xchal_ncp_load a2,a3,a4,a5,a6 1018 #define xchal_extra_store_funcbody xchal_ncp_store a2,a3,a4,a5,a6 1019 #define xchal_cp0_store_a2 xchal_cp0_store a2,a3,a4,a5,a6 1020 #define xchal_cp0_load_a2 xchal_cp0_load a2,a3,a4,a5,a6 1021 #define xchal_cp1_store_a2 xchal_cp1_store a2,a3,a4,a5,a6 1022 #define xchal_cp1_load_a2 xchal_cp1_load a2,a3,a4,a5,a6 1023 #define xchal_cp2_store_a2 xchal_cp2_store a2,a3,a4,a5,a6 1024 #define xchal_cp2_load_a2 xchal_cp2_load a2,a3,a4,a5,a6 1025 #define xchal_cp3_store_a2 xchal_cp3_store a2,a3,a4,a5,a6 1026 #define xchal_cp3_load_a2 xchal_cp3_load a2,a3,a4,a5,a6 1027 #define xchal_cp4_store_a2 xchal_cp4_store a2,a3,a4,a5,a6 1028 #define xchal_cp4_load_a2 xchal_cp4_load a2,a3,a4,a5,a6 1029 #define xchal_cp5_store_a2 xchal_cp5_store a2,a3,a4,a5,a6 1030 #define xchal_cp5_load_a2 xchal_cp5_load a2,a3,a4,a5,a6 1031 #define xchal_cp6_store_a2 xchal_cp6_store a2,a3,a4,a5,a6 1032 #define xchal_cp6_load_a2 xchal_cp6_load a2,a3,a4,a5,a6 1033 #define xchal_cp7_store_a2 xchal_cp7_store a2,a3,a4,a5,a6 1034 #define xchal_cp7_load_a2 xchal_cp7_load a2,a3,a4,a5,a6 1035 1036 /* Empty placeholder macros for undefined coprocessors: */ 1037 #if (XCHAL_CP_MASK & ~XCHAL_CP_PORT_MASK) == 0 1038 # if XCHAL_CP0_SA_SIZE == 0 1039 .macro xchal_cp0_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 1040 .macro xchal_cp0_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 1041 # endif 1042 # if XCHAL_CP1_SA_SIZE == 0 1043 .macro xchal_cp1_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 1044 .macro xchal_cp1_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 1045 # endif 1046 # if XCHAL_CP2_SA_SIZE == 0 1047 .macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 1048 .macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 1049 # endif 1050 # if XCHAL_CP3_SA_SIZE == 0 1051 .macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 1052 .macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 1053 # endif 1054 # if XCHAL_CP4_SA_SIZE == 0 1055 .macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 1056 .macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 1057 # endif 1058 # if XCHAL_CP5_SA_SIZE == 0 1059 .macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 1060 .macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 1061 # endif 1062 # if XCHAL_CP6_SA_SIZE == 0 1063 .macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 1064 .macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 1065 # endif 1066 # if XCHAL_CP7_SA_SIZE == 0 1067 .macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 1068 .macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 1069 # endif 1070 #endif 1071 1072 /******************** 1073 * Macros to create functions that save and restore the state of *any* TIE 1074 * coprocessor (by dynamic index). 1075 */ 1076 1077 /* 1078 * Macro that expands to the body of a function 1079 * that stores the selected coprocessor's state (registers etc). 1080 * Entry: a2 = ptr to save area in which to save cp state 1081 * a3 = coprocessor number 1082 * Exit: any register a2-a15 (?) may have been clobbered. 1083 */ 1084 .macro xchal_cpi_store_funcbody 1085 #if (XCHAL_CP_MASK & ~XCHAL_CP_PORT_MASK) 1086 # if XCHAL_CP0_SA_SIZE 1087 bnez a3, 99f 1088 xchal_cp0_store_a2 1089 j 90f 1090 99: 1091 # endif 1092 # if XCHAL_CP1_SA_SIZE 1093 bnei a3, 1, 99f 1094 xchal_cp1_store_a2 1095 j 90f 1096 99: 1097 # endif 1098 # if XCHAL_CP2_SA_SIZE 1099 bnei a3, 2, 99f 1100 xchal_cp2_store_a2 1101 j 90f 1102 99: 1103 # endif 1104 # if XCHAL_CP3_SA_SIZE 1105 bnei a3, 3, 99f 1106 xchal_cp3_store_a2 1107 j 90f 1108 99: 1109 # endif 1110 # if XCHAL_CP4_SA_SIZE 1111 bnei a3, 4, 99f 1112 xchal_cp4_store_a2 1113 j 90f 1114 99: 1115 # endif 1116 # if XCHAL_CP5_SA_SIZE 1117 bnei a3, 5, 99f 1118 xchal_cp5_store_a2 1119 j 90f 1120 99: 1121 # endif 1122 # if XCHAL_CP6_SA_SIZE 1123 bnei a3, 6, 99f 1124 xchal_cp6_store_a2 1125 j 90f 1126 99: 1127 # endif 1128 # if XCHAL_CP7_SA_SIZE 1129 bnei a3, 7, 99f 1130 xchal_cp7_store_a2 1131 j 90f 1132 99: 1133 # endif 1134 90: 1135 #endif 1136 .endm 1137 1138 /* 1139 * Macro that expands to the body of a function 1140 * that loads the selected coprocessor's state (registers etc). 1141 * Entry: a2 = ptr to save area from which to restore cp state 1142 * a3 = coprocessor number 1143 * Exit: any register a2-a15 (?) may have been clobbered. 1144 */ 1145 .macro xchal_cpi_load_funcbody 1146 #if (XCHAL_CP_MASK & ~XCHAL_CP_PORT_MASK) 1147 # if XCHAL_CP0_SA_SIZE 1148 bnez a3, 99f 1149 xchal_cp0_load_a2 1150 j 90f 1151 99: 1152 # endif 1153 # if XCHAL_CP1_SA_SIZE 1154 bnei a3, 1, 99f 1155 xchal_cp1_load_a2 1156 j 90f 1157 99: 1158 # endif 1159 # if XCHAL_CP2_SA_SIZE 1160 bnei a3, 2, 99f 1161 xchal_cp2_load_a2 1162 j 90f 1163 99: 1164 # endif 1165 # if XCHAL_CP3_SA_SIZE 1166 bnei a3, 3, 99f 1167 xchal_cp3_load_a2 1168 j 90f 1169 99: 1170 # endif 1171 # if XCHAL_CP4_SA_SIZE 1172 bnei a3, 4, 99f 1173 xchal_cp4_load_a2 1174 j 90f 1175 99: 1176 # endif 1177 # if XCHAL_CP5_SA_SIZE 1178 bnei a3, 5, 99f 1179 xchal_cp5_load_a2 1180 j 90f 1181 99: 1182 # endif 1183 # if XCHAL_CP6_SA_SIZE 1184 bnei a3, 6, 99f 1185 xchal_cp6_load_a2 1186 j 90f 1187 99: 1188 # endif 1189 # if XCHAL_CP7_SA_SIZE 1190 bnei a3, 7, 99f 1191 xchal_cp7_load_a2 1192 j 90f 1193 99: 1194 # endif 1195 90: 1196 #endif 1197 .endm 1198 1199 #endif /*_ASMLANGUAGE or __ASSEMBLER__*/ 1200 1201 1202 /* Other default macros for undefined coprocessors: */ 1203 #ifndef XCHAL_CP0_NAME 1204 # define XCHAL_CP0_NAME 0 1205 # define XCHAL_CP0_SA_CONTENTS_LIBDB_NUM 0 1206 # define XCHAL_CP0_SA_CONTENTS_LIBDB /* empty */ 1207 #endif 1208 #ifndef XCHAL_CP1_NAME 1209 # define XCHAL_CP1_NAME 0 1210 # define XCHAL_CP1_SA_CONTENTS_LIBDB_NUM 0 1211 # define XCHAL_CP1_SA_CONTENTS_LIBDB /* empty */ 1212 #endif 1213 #ifndef XCHAL_CP2_NAME 1214 # define XCHAL_CP2_NAME 0 1215 # define XCHAL_CP2_SA_CONTENTS_LIBDB_NUM 0 1216 # define XCHAL_CP2_SA_CONTENTS_LIBDB /* empty */ 1217 #endif 1218 #ifndef XCHAL_CP3_NAME 1219 # define XCHAL_CP3_NAME 0 1220 # define XCHAL_CP3_SA_CONTENTS_LIBDB_NUM 0 1221 # define XCHAL_CP3_SA_CONTENTS_LIBDB /* empty */ 1222 #endif 1223 #ifndef XCHAL_CP4_NAME 1224 # define XCHAL_CP4_NAME 0 1225 # define XCHAL_CP4_SA_CONTENTS_LIBDB_NUM 0 1226 # define XCHAL_CP4_SA_CONTENTS_LIBDB /* empty */ 1227 #endif 1228 #ifndef XCHAL_CP5_NAME 1229 # define XCHAL_CP5_NAME 0 1230 # define XCHAL_CP5_SA_CONTENTS_LIBDB_NUM 0 1231 # define XCHAL_CP5_SA_CONTENTS_LIBDB /* empty */ 1232 #endif 1233 #ifndef XCHAL_CP6_NAME 1234 # define XCHAL_CP6_NAME 0 1235 # define XCHAL_CP6_SA_CONTENTS_LIBDB_NUM 0 1236 # define XCHAL_CP6_SA_CONTENTS_LIBDB /* empty */ 1237 #endif 1238 #ifndef XCHAL_CP7_NAME 1239 # define XCHAL_CP7_NAME 0 1240 # define XCHAL_CP7_SA_CONTENTS_LIBDB_NUM 0 1241 # define XCHAL_CP7_SA_CONTENTS_LIBDB /* empty */ 1242 #endif 1243 1244 #if XCHAL_CP_MASK == 0 1245 /* Filler info for unassigned coprocessors, to simplify arrays etc: */ 1246 #define XCHAL_CP0_SA_SIZE 0 1247 #define XCHAL_CP0_SA_ALIGN 1 1248 #define XCHAL_CP1_SA_SIZE 0 1249 #define XCHAL_CP1_SA_ALIGN 1 1250 #define XCHAL_CP2_SA_SIZE 0 1251 #define XCHAL_CP2_SA_ALIGN 1 1252 #define XCHAL_CP3_SA_SIZE 0 1253 #define XCHAL_CP3_SA_ALIGN 1 1254 #define XCHAL_CP4_SA_SIZE 0 1255 #define XCHAL_CP4_SA_ALIGN 1 1256 #define XCHAL_CP5_SA_SIZE 0 1257 #define XCHAL_CP5_SA_ALIGN 1 1258 #define XCHAL_CP6_SA_SIZE 0 1259 #define XCHAL_CP6_SA_ALIGN 1 1260 #define XCHAL_CP7_SA_SIZE 0 1261 #define XCHAL_CP7_SA_ALIGN 1 1262 #endif 1263 1264 1265 /* Indexing macros: */ 1266 #define _XCHAL_CP_SA_SIZE(n) XCHAL_CP ## n ## _SA_SIZE 1267 #define XCHAL_CP_SA_SIZE(n) _XCHAL_CP_SA_SIZE(n) /* n = 0 .. 7 */ 1268 #define _XCHAL_CP_SA_ALIGN(n) XCHAL_CP ## n ## _SA_ALIGN 1269 #define XCHAL_CP_SA_ALIGN(n) _XCHAL_CP_SA_ALIGN(n) /* n = 0 .. 7 */ 1270 1271 #define XCHAL_CPEXTRA_SA_SIZE_TOR2 XCHAL_CPEXTRA_SA_SIZE /* Tor2Beta only - do not use */ 1272 1273 /* Link-time HAL global variables that report coprocessor numbers by name 1274 (names are case-preserved from the original TIE): */ 1275 #if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__) 1276 # define _XCJOIN(a,b) a ## b 1277 # define XCJOIN(a,b) _XCJOIN(a,b) 1278 # ifdef XCHAL_CP0_NAME 1279 extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP0_IDENT); 1280 extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP0_IDENT); 1281 # endif 1282 # ifdef XCHAL_CP1_NAME 1283 extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP1_IDENT); 1284 extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP1_IDENT); 1285 # endif 1286 # ifdef XCHAL_CP2_NAME 1287 extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP2_IDENT); 1288 extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP2_IDENT); 1289 # endif 1290 # ifdef XCHAL_CP3_NAME 1291 extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP3_IDENT); 1292 extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP3_IDENT); 1293 # endif 1294 # ifdef XCHAL_CP4_NAME 1295 extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP4_IDENT); 1296 extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP4_IDENT); 1297 # endif 1298 # ifdef XCHAL_CP5_NAME 1299 extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP5_IDENT); 1300 extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP5_IDENT); 1301 # endif 1302 # ifdef XCHAL_CP6_NAME 1303 extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP6_IDENT); 1304 extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP6_IDENT); 1305 # endif 1306 # ifdef XCHAL_CP7_NAME 1307 extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP7_IDENT); 1308 extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP7_IDENT); 1309 # endif 1310 #endif 1311 1312 1313 1314 1315 /*---------------------------------------------------------------------- 1316 DERIVED 1317 ----------------------------------------------------------------------*/ 1318 1319 #if XCHAL_HAVE_BE 1320 #define XCHAL_INST_ILLN 0xD60F /* 2-byte illegal instruction, msb-first */ 1321 #define XCHAL_INST_ILLN_BYTE0 0xD6 /* 2-byte illegal instruction, 1st byte */ 1322 #define XCHAL_INST_ILLN_BYTE1 0x0F /* 2-byte illegal instruction, 2nd byte */ 1323 #else 1324 #define XCHAL_INST_ILLN 0xF06D /* 2-byte illegal instruction, lsb-first */ 1325 #define XCHAL_INST_ILLN_BYTE0 0x6D /* 2-byte illegal instruction, 1st byte */ 1326 #define XCHAL_INST_ILLN_BYTE1 0xF0 /* 2-byte illegal instruction, 2nd byte */ 1327 #endif 1328 /* Belongs in xtensa/hal.h: */ 1329 #define XTHAL_INST_ILL 0x000000 /* 3-byte illegal instruction */ 1330 1331 1332 /* 1333 * Because information as to exactly which hardware version is targeted 1334 * by a given software build is not always available, compile-time HAL 1335 * Hardware-Release "_AT" macros are fuzzy (return 0, 1, or XCHAL_MAYBE): 1336 * (Here "RELEASE" is now a misnomer; these are product *versions*, not the releases 1337 * under which they are released. In the T10##.# era there was no distinction.) 1338 */ 1339 #if XCHAL_HW_CONFIGID_RELIABLE 1340 # define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor) (XTHAL_REL_LE( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0) 1341 # define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor) (XTHAL_REL_GE( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0) 1342 # define XCHAL_HW_RELEASE_AT(major,minor) (XTHAL_REL_EQ( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0) 1343 # define XCHAL_HW_RELEASE_MAJOR_AT(major) ((XCHAL_HW_VERSION_MAJOR == (major)) ? 1 : 0) 1344 #else 1345 # define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor) ( ((major) < 1040 && XCHAL_HAVE_XEA2) ? 0 \ 1346 : ((major) > 1050 && XCHAL_HAVE_XEA1) ? 1 \ 1347 : XTHAL_MAYBE ) 1348 # define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor) ( ((major) >= 2000 && XCHAL_HAVE_XEA1) ? 0 \ 1349 : (XTHAL_REL_LE(major,minor, 1040,0) && XCHAL_HAVE_XEA2) ? 1 \ 1350 : XTHAL_MAYBE ) 1351 # define XCHAL_HW_RELEASE_AT(major,minor) ( (((major) < 1040 && XCHAL_HAVE_XEA2) || \ 1352 ((major) >= 2000 && XCHAL_HAVE_XEA1)) ? 0 : XTHAL_MAYBE) 1353 # define XCHAL_HW_RELEASE_MAJOR_AT(major) XCHAL_HW_RELEASE_AT(major,0) 1354 #endif 1355 1356 /* 1357 * Specific errata: 1358 */ 1359 1360 /* 1361 * Erratum T1020.H13, T1030.H7, T1040.H10, T1050.H4 (fixed in T1040.3 and T1050.1; 1362 * relevant only in XEA1, kernel-vector mode, level-one interrupts and overflows enabled): 1363 */ 1364 #define XCHAL_MAYHAVE_ERRATUM_XEA1KWIN (XCHAL_HAVE_XEA1 && \ 1365 (XCHAL_HW_RELEASE_AT_OR_BELOW(1040,2) != 0 \ 1366 || XCHAL_HW_RELEASE_AT(1050,0))) 1367 /* 1368 * Erratum 453 present in RE-2013.2 up to RF-2014.0, fixed in RF-2014.1. 1369 * Applies to specific set of configuration options. 1370 * Part of the workaround is to add ISYNC at certain points in the code. 1371 * The workaround gated by this macro can be disabled if not needed, e.g. if 1372 * zero-overhead loop buffer will be disabled, by defining _NO_ERRATUM_453. 1373 */ 1374 #if ( XCHAL_HW_MAX_VERSION >= XTENSA_HWVERSION_RE_2013_2 && \ 1375 XCHAL_HW_MIN_VERSION <= XTENSA_HWVERSION_RF_2014_0 && \ 1376 XCHAL_ICACHE_SIZE != 0 && XCHAL_HAVE_PIF /*covers also AXI/AHB*/ && \ 1377 XCHAL_HAVE_LOOPS && XCHAL_LOOP_BUFFER_SIZE != 0 && \ 1378 XCHAL_CLOCK_GATING_GLOBAL && !defined(_NO_ERRATUM_453) ) 1379 #define XCHAL_ERRATUM_453 1 1380 #else 1381 #define XCHAL_ERRATUM_453 0 1382 #endif 1383 1384 /* 1385 * Erratum 497 present in RE-2012.2 up to RG/RF-2015.2 1386 * Applies to specific set of configuration options. 1387 * Workaround is to add MEMWs after at most 8 cache WB instructions 1388 */ 1389 #if ( ((XCHAL_HW_MAX_VERSION >= XTENSA_HWVERSION_RE_2012_0 && \ 1390 XCHAL_HW_MIN_VERSION <= XTENSA_HWVERSION_RF_2015_2) || \ 1391 (XCHAL_HW_MAX_VERSION >= XTENSA_HWVERSION_RG_2015_0 && \ 1392 XCHAL_HW_MIN_VERSION <= XTENSA_HWVERSION_RG_2015_2) \ 1393 ) && \ 1394 XCHAL_DCACHE_IS_WRITEBACK && \ 1395 XCHAL_HAVE_AXI && \ 1396 XCHAL_HAVE_PIF_WR_RESP && \ 1397 XCHAL_HAVE_PIF_REQ_ATTR && !defined(_NO_ERRATUM_497) \ 1398 ) 1399 #define XCHAL_ERRATUM_497 1 1400 #else 1401 #define XCHAL_ERRATUM_497 0 1402 #endif 1403 1404 /* 1405 * Erratum 572 (releases TBD, but present in ESP32) 1406 * Disable zero-overhead loop buffer to prevent rare illegal instruction 1407 * exceptions while executing zero-overhead loops. 1408 */ 1409 #if ( XCHAL_HAVE_LOOPS && XCHAL_LOOP_BUFFER_SIZE != 0 ) 1410 #define XCHAL_ERRATUM_572 1 1411 #else 1412 #define XCHAL_ERRATUM_572 0 1413 #endif 1414 1415 #endif /*XTENSA_CONFIG_CORE_H*/ 1416