1 // Copyright 2020 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #ifndef XTENSA_DEBUG_MODULE_H 16 #define XTENSA_DEBUG_MODULE_H 17 18 /* 19 ERI registers / OCD offsets and field definitions 20 */ 21 22 #define ERI_DEBUG_OFFSET 0x100000 23 24 #define ERI_TRAX_OFFSET (ERI_DEBUG_OFFSET+0) 25 #define ERI_PERFMON_OFFSET (ERI_DEBUG_OFFSET+0x1000) 26 #define ERI_OCDREG_OFFSET (ERI_DEBUG_OFFSET+0x2000) 27 #define ERI_MISCDBG_OFFSET (ERI_DEBUG_OFFSET+0x3000) 28 #define ERI_CORESIGHT_OFFSET (ERI_DEBUG_OFFSET+0x3F00) 29 30 #define ERI_TRAX_TRAXID (ERI_TRAX_OFFSET+0x00) 31 #define ERI_TRAX_TRAXCTRL (ERI_TRAX_OFFSET+0x04) 32 #define ERI_TRAX_TRAXSTAT (ERI_TRAX_OFFSET+0x08) 33 #define ERI_TRAX_TRAXDATA (ERI_TRAX_OFFSET+0x0C) 34 #define ERI_TRAX_TRAXADDR (ERI_TRAX_OFFSET+0x10) 35 #define ERI_TRAX_TRIGGERPC (ERI_TRAX_OFFSET+0x14) 36 #define ERI_TRAX_PCMATCHCTRL (ERI_TRAX_OFFSET+0x18) 37 #define ERI_TRAX_DELAYCNT (ERI_TRAX_OFFSET+0x1C) 38 #define ERI_TRAX_MEMADDRSTART (ERI_TRAX_OFFSET+0x20) 39 #define ERI_TRAX_MEMADDREND (ERI_TRAX_OFFSET+0x24) 40 41 #define TRAXCTRL_TREN (1<<0) //Trace enable. Tracing starts on 0->1 42 #define TRAXCTRL_TRSTP (1<<1) //Trace Stop. Make 1 to stop trace. 43 #define TRAXCTRL_PCMEN (1<<2) //PC match enable 44 #define TRAXCTRL_PTIEN (1<<4) //Processor-trigger enable 45 #define TRAXCTRL_CTIEN (1<<5) //Cross-trigger enable 46 #define TRAXCTRL_TMEN (1<<7) //Tracemem Enable. Always set. 47 #define TRAXCTRL_CNTU (1<<9) //Post-stop-trigger countdown units; selects when DelayCount-- happens. 48 //0 - every 32-bit word written to tracemem, 1 - every cpu instruction 49 #define TRAXCTRL_TSEN (1<<11) //Undocumented/deprecated? 50 #define TRAXCTRL_SMPER_SHIFT 12 //Send sync every 2^(9-smper) messages. 7=reserved, 0=no sync msg 51 #define TRAXCTRL_SMPER_MASK 0x7 //Synchronization message period 52 #define TRAXCTRL_PTOWT (1<<16) //Processor Trigger Out (OCD halt) enabled when stop triggered 53 #define TRAXCTRL_PTOWS (1<<17) //Processor Trigger Out (OCD halt) enabled when trace stop completes 54 #define TRAXCTRL_CTOWT (1<<20) //Cross-trigger Out enabled when stop triggered 55 #define TRAXCTRL_CTOWS (1<<21) //Cross-trigger Out enabled when trace stop completes 56 #define TRAXCTRL_ITCTO (1<<22) //Integration mode: cross-trigger output 57 #define TRAXCTRL_ITCTIA (1<<23) //Integration mode: cross-trigger ack 58 #define TRAXCTRL_ITATV (1<<24) //replaces ATID when in integration mode: ATVALID output 59 #define TRAXCTRL_ATID_MASK 0x7F //ARB source ID 60 #define TRAXCTRL_ATID_SHIFT 24 61 #define TRAXCTRL_ATEN (1<<31) //ATB interface enable 62 63 #define TRAXSTAT_TRACT (1<<0) //Trace active flag. 64 #define TRAXSTAT_TRIG (1<<1) //Trace stop trigger. Clears on TREN 1->0 65 #define TRAXSTAT_PCMTG (1<<2) //Stop trigger caused by PC match. Clears on TREN 1->0 66 #define TRAXSTAT_PJTR (1<<3) //JTAG transaction result. 1=err in preceding jtag transaction. 67 #define TRAXSTAT_PTITG (1<<4) //Stop trigger caused by Processor Trigger Input. Clears on TREN 1->0 68 #define TRAXSTAT_CTITG (1<<5) //Stop trigger caused by Cross-Trigger Input. Clears on TREN 1->0 69 #define TRAXSTAT_MEMSZ_SHIFT 8 //Traceram size inducator. Usable trace ram is 2^MEMSZ bytes. 70 #define TRAXSTAT_MEMSZ_MASK 0x1F 71 #define TRAXSTAT_PTO (1<<16) //Processor Trigger Output: current value 72 #define TRAXSTAT_CTO (1<<17) //Cross-Trigger Output: current value 73 #define TRAXSTAT_ITCTOA (1<<22) //Cross-Trigger Out Ack: current value 74 #define TRAXSTAT_ITCTI (1<<23) //Cross-Trigger Input: current value 75 #define TRAXSTAT_ITATR (1<<24) //ATREADY Input: current value 76 77 #define TRAXADDR_TADDR_SHIFT 0 //Trax memory address, in 32-bit words. 78 #define TRAXADDR_TADDR_MASK 0x1FFFFF //Actually is only as big as the trace buffer size max addr. 79 #define TRAXADDR_TWRAP_SHIFT 21 //Amount of times TADDR has overflown 80 #define TRAXADDR_TWRAP_MASK 0x3FF 81 #define TRAXADDR_TWSAT (1<<31) //1 if TWRAP has overflown, clear by disabling tren. 82 83 #define PCMATCHCTRL_PCML_SHIFT 0 //Amount of lower bits to ignore in pc trigger register 84 #define PCMATCHCTRL_PCML_MASK 0x1F 85 #define PCMATCHCTRL_PCMS (1<<31) //PC Match Sense, 0 - match when procs PC is in-range, 1 - match when 86 //out-of-range 87 88 // Global control/status for all performance counters 89 #define ERI_PERFMON_PGM (ERI_PERFMON_OFFSET+0x0000) 90 //PC at the cycle of the event that caused PerfMonInt assertion 91 #define ERI_PERFMON_INTPC (ERI_PERFMON_OFFSET+0x0010) 92 93 // Maximum amount of counter (depends on chip) 94 #define ERI_PERFMON_MAX XCHAL_NUM_PERF_COUNTERS 95 96 // Performance counter value 97 #define ERI_PERFMON_PM0 (ERI_PERFMON_OFFSET+0x0080) 98 // Performance counter control register 99 #define ERI_PERFMON_PMCTRL0 (ERI_PERFMON_OFFSET+0x0100) 100 // Performance counter status register 101 #define ERI_PERFMON_PMSTAT0 (ERI_PERFMON_OFFSET+0x0180) 102 103 104 #define PMCTRL_INTEN (1<<0) // Enables assertion of PerfMonInt output when overflow happens 105 #define PMCTRL_KRNLCNT (1<<3) // Enables counting when CINTLEVEL* > 106 // TRACELEVEL (i.e. If this bit is set, this counter 107 // counts only when CINTLEVEL >TRACELEVEL; 108 // if this bit is cleared, this counter counts only when 109 // CINTLEVEL ≤ TRACELEVEL) 110 #define PMCTRL_KRNLCNT_SHIFT 3 111 #define PMCTRL_TRACELEVEL_SHIFT 4 // Compares this value to CINTLEVEL* when deciding whether to count 112 #define PMCTRL_TRACELEVEL_MASK 0xf 113 #define PMCTRL_SELECT_SHIFT 8 // Selects input to be counted by the counter 114 #define PMCTRL_SELECT_MASK 0x1f 115 #define PMCTRL_MASK_SHIFT 16 // Selects input subsets to be counted (counter will 116 // increment only once even if more than one condition 117 // corresponding to a mask bit occurs) 118 #define PMCTRL_MASK_MASK 0xffff 119 120 121 #define PMSTAT_OVFL (1<<0) // Counter Overflow. Sticky bit set when a counter rolls over 122 // from 0xffffffff to 0x0. 123 #define PMSTAT_INTSTART (1<<4) // This counter’s overflow caused PerfMonInt to be asserted. 124 125 126 #define PGM_PMEN (1<<0) // Overall enable for all performance counting 127 128 129 #endif 130