1 /******************************************************************************* 2 // Copyright (c) 2003-2015 Cadence Design Systems, Inc. 3 // 4 // Permission is hereby granted, free of charge, to any person obtaining 5 // a copy of this software and associated documentation files (the 6 // "Software"), to deal in the Software without restriction, including 7 // without limitation the rights to use, copy, modify, merge, publish, 8 // distribute, sublicense, and/or sell copies of the Software, and to 9 // permit persons to whom the Software is furnished to do so, subject to 10 // the following conditions: 11 // 12 // The above copyright notice and this permission notice shall be included 13 // in all copies or substantial portions of the Software. 14 // 15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 16 // EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 17 // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 18 // IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 19 // CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 20 // TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 21 // SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 -------------------------------------------------------------------------------- 23 24 XTENSA INFORMATION FOR RTOS TICK TIMER AND CLOCK FREQUENCY 25 26 This header contains definitions and macros for use primarily by Xtensa 27 RTOS assembly coded source files. It includes and uses the Xtensa hardware 28 abstraction layer (HAL) to deal with config specifics. It may also be 29 included in C source files. 30 31 User may edit to modify timer selection and to specify clock frequency and 32 tick duration to match timer interrupt to the real-time tick duration. 33 34 If the RTOS has no timer interrupt, then there is no tick timer and the 35 clock frequency is irrelevant, so all of these macros are left undefined 36 and the Xtensa core configuration need not have a timer. 37 38 *******************************************************************************/ 39 40 #ifndef XTENSA_TIMER_H 41 #define XTENSA_TIMER_H 42 43 #ifdef __ASSEMBLER__ 44 #include <xtensa/coreasm.h> 45 #endif 46 47 #include <xtensa/corebits.h> 48 #include <xtensa/config/system.h> 49 50 #include "xtensa_rtos.h" /* in case this wasn't included directly */ 51 52 #include "esp_osal/osal_config.h" 53 54 /* 55 Select timer to use for periodic tick, and determine its interrupt number 56 and priority. User may specify a timer by defining XT_TIMER_INDEX with -D, 57 in which case its validity is checked (it must exist in this core and must 58 not be on a high priority interrupt - an error will be reported in invalid). 59 Otherwise select the first low or medium priority interrupt timer available. 60 */ 61 #if XCHAL_NUM_TIMERS == 0 62 63 #error "This Xtensa configuration is unsupported, it has no timers." 64 65 #else 66 67 #ifndef XT_TIMER_INDEX 68 #if XCHAL_TIMER3_INTERRUPT != XTHAL_TIMER_UNCONFIGURED 69 #if XCHAL_INT_LEVEL(XCHAL_TIMER3_INTERRUPT) <= XCHAL_EXCM_LEVEL 70 #undef XT_TIMER_INDEX 71 #define XT_TIMER_INDEX 3 72 #endif 73 #endif 74 #if XCHAL_TIMER2_INTERRUPT != XTHAL_TIMER_UNCONFIGURED 75 #if XCHAL_INT_LEVEL(XCHAL_TIMER2_INTERRUPT) <= XCHAL_EXCM_LEVEL 76 #undef XT_TIMER_INDEX 77 #define XT_TIMER_INDEX 2 78 #endif 79 #endif 80 #if XCHAL_TIMER1_INTERRUPT != XTHAL_TIMER_UNCONFIGURED 81 #if XCHAL_INT_LEVEL(XCHAL_TIMER1_INTERRUPT) <= XCHAL_EXCM_LEVEL 82 #undef XT_TIMER_INDEX 83 #define XT_TIMER_INDEX 1 84 #endif 85 #endif 86 #if XCHAL_TIMER0_INTERRUPT != XTHAL_TIMER_UNCONFIGURED 87 #if XCHAL_INT_LEVEL(XCHAL_TIMER0_INTERRUPT) <= XCHAL_EXCM_LEVEL 88 #undef XT_TIMER_INDEX 89 #define XT_TIMER_INDEX 0 90 #endif 91 #endif 92 #endif 93 #ifndef XT_TIMER_INDEX 94 #error "There is no suitable timer in this Xtensa configuration." 95 #endif 96 97 #define XT_CCOMPARE (CCOMPARE + XT_TIMER_INDEX) 98 #define XT_TIMER_INTNUM XCHAL_TIMER_INTERRUPT(XT_TIMER_INDEX) 99 #define XT_TIMER_INTPRI XCHAL_INT_LEVEL(XT_TIMER_INTNUM) 100 #define XT_TIMER_INTEN (1 << XT_TIMER_INTNUM) 101 102 #if XT_TIMER_INTNUM == XTHAL_TIMER_UNCONFIGURED 103 #error "The timer selected by XT_TIMER_INDEX does not exist in this core." 104 #elif XT_TIMER_INTPRI > XCHAL_EXCM_LEVEL 105 #error "The timer interrupt cannot be high priority (use medium or low)." 106 #endif 107 108 #endif /* XCHAL_NUM_TIMERS */ 109 110 /* 111 Set processor clock frequency, used to determine clock divisor for timer tick. 112 User should BE SURE TO ADJUST THIS for the Xtensa platform being used. 113 If using a supported board via the board-independent API defined in xtbsp.h, 114 this may be left undefined and frequency and tick divisor will be computed 115 and cached during run-time initialization. 116 117 NOTE ON SIMULATOR: 118 Under the Xtensa instruction set simulator, the frequency can only be estimated 119 because it depends on the speed of the host and the version of the simulator. 120 Also because it runs much slower than hardware, it is not possible to achieve 121 real-time performance for most applications under the simulator. A frequency 122 too low does not allow enough time between timer interrupts, starving threads. 123 To obtain a more convenient but non-real-time tick duration on the simulator, 124 compile with xt-xcc option "-DXT_SIMULATOR". 125 Adjust this frequency to taste (it's not real-time anyway!). 126 */ 127 #if defined(XT_SIMULATOR) && !defined(XT_CLOCK_FREQ) 128 #define XT_CLOCK_FREQ configCPU_CLOCK_HZ 129 #endif 130 131 #if !defined(XT_CLOCK_FREQ) && !defined(XT_BOARD) 132 #error "XT_CLOCK_FREQ must be defined for the target platform." 133 #endif 134 135 /* 136 Default number of timer "ticks" per second (default 100 for 10ms tick). 137 RTOS may define this in its own way (if applicable) in xtensa_rtos.h. 138 User may redefine this to an optimal value for the application, either by 139 editing this here or in xtensa_rtos.h, or compiling with xt-xcc option 140 "-DXT_TICK_PER_SEC=<value>" where <value> is a suitable number. 141 */ 142 #ifndef XT_TICK_PER_SEC 143 #define XT_TICK_PER_SEC configTICK_RATE_HZ /* 10 ms tick = 100 ticks per second */ 144 #endif 145 146 /* 147 Derivation of clock divisor for timer tick and interrupt (one per tick). 148 */ 149 #ifdef XT_CLOCK_FREQ 150 #define XT_TICK_DIVISOR (XT_CLOCK_FREQ / XT_TICK_PER_SEC) 151 #endif 152 153 #ifndef __ASSEMBLER__ 154 extern unsigned _xt_tick_divisor; 155 extern void _xt_tick_divisor_init(void); 156 #endif 157 158 #endif /* XTENSA_TIMER_H */ 159