1 /* 2 * Allwinner SoCs display driver. 3 * 4 * Copyright (C) 2017 Allwinner. 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 */ 10 11 #ifndef _DE_VSU_TYPE_H_ 12 #define _DE_VSU_TYPE_H_ 13 14 #include <linux/types.h> 15 16 union vsu8_ctl_reg { 17 u32 dwval; 18 struct { 19 u32 en:1; 20 u32 res0:29; 21 u32 reset:1; 22 u32 res1:1; 23 } bits; 24 }; 25 26 union vsu8_scale_mode_reg { 27 u32 dwval; 28 struct { 29 u32 mode:1; 30 u32 res0:31; 31 } bits; 32 }; 33 34 union vsu8_size_reg { 35 u32 dwval; 36 struct { 37 u32 width:13; 38 u32 res0:3; 39 u32 height:13; 40 u32 res1:3; 41 } bits; 42 }; 43 44 union vsu8_glb_alpha_reg { 45 u32 dwval; 46 struct { 47 u32 alpha:8; 48 u32 res0:24; 49 } bits; 50 }; 51 52 #define VSU8_STEP_VALID_START_BIT 1 53 #define VSU8_STEP_FRAC_BITWIDTH 19 54 #define VSU8_STEP_FIXED_BITWIDTH 4 55 union vsu8_step_reg { 56 u32 dwval; 57 struct { 58 u32 res0:VSU8_STEP_VALID_START_BIT; 59 u32 frac:VSU8_STEP_FRAC_BITWIDTH; 60 u32 fixed:VSU8_STEP_FIXED_BITWIDTH; 61 u32 res1:8; 62 } bits; 63 }; 64 65 #define VSU8_PHASE_VALID_START_BIT 1 66 #define VSU8_PHASE_RRAC_BITWIDTH 19 67 #define VSU8_PHASE_FIXED_BITWIDTH 4 68 union vsu8_phase_reg { 69 u32 dwval; 70 struct { 71 u32 res0:VSU8_PHASE_VALID_START_BIT; 72 u32 frac:VSU8_PHASE_RRAC_BITWIDTH; 73 u32 fixed:VSU8_PHASE_FIXED_BITWIDTH; 74 u32 res1:8; 75 } bits; 76 }; 77 78 union vsu8_filter_coeff_reg { 79 u32 dwval; 80 struct { 81 u32 coeff0:8; 82 u32 coeff1:8; 83 u32 coeff2:8; 84 u32 coeff3:8; 85 } bits; 86 }; 87 88 struct vsu8_reg { 89 union vsu8_ctl_reg ctl; 90 u32 res0[3]; 91 union vsu8_scale_mode_reg scale_mode; 92 u32 res1[11]; 93 union vsu8_size_reg out_size; 94 union vsu8_glb_alpha_reg glb_alpha; 95 u32 res2[14]; 96 union vsu8_size_reg y_in_size; 97 u32 res3; 98 union vsu8_step_reg y_hstep; 99 union vsu8_step_reg y_vstep; 100 union vsu8_phase_reg y_hphase; 101 u32 res4; 102 union vsu8_phase_reg y_vphase; 103 u32 res5[9]; 104 union vsu8_size_reg c_in_size; 105 u32 res6; 106 union vsu8_step_reg c_hstep; 107 union vsu8_step_reg c_vstep; 108 union vsu8_phase_reg c_hphase; 109 u32 res7; 110 union vsu8_phase_reg c_vphase; /* 0xD8 */ 111 u32 res8[73]; 112 113 union vsu8_filter_coeff_reg y_hori_coeff[32]; /* 0x200 */ 114 u32 res9[96]; 115 116 union vsu8_filter_coeff_reg y_vert_coeff[32]; /* 0x400 */ 117 u32 res10[96]; 118 119 union vsu8_filter_coeff_reg c_hori_coeff[32]; /* 0x600 */ 120 }; 121 122 /* ********************************************************** */ 123 124 union vsu10_ctl_reg { 125 u32 dwval; 126 struct { 127 u32 en:1; 128 u32 res0:29; 129 u32 reset:1; 130 u32 res1:1; 131 } bits; 132 }; 133 134 union vsu10_status_reg { 135 u32 dwval; 136 struct { 137 u32 res0:4; 138 u32 busy:1; 139 u32 res1:11; 140 u32 line_cnt:12; 141 u32 res2:4; 142 } bits; 143 }; 144 145 union vsu10_field_ctl_reg { 146 u32 dwval; 147 struct { 148 u32 vphase_en:1; 149 u32 res0:3; 150 u32 filed_reverse:1; 151 u32 sync_reverse:1; 152 u32 res1:26; 153 } bits; 154 }; 155 156 union vsu10_scale_mode_reg { 157 u32 dwval; 158 struct { 159 u32 mode:2; 160 u32 res0:30; 161 } bits; 162 }; 163 164 union vsu10_size_reg { 165 u32 dwval; 166 struct { 167 u32 width:13; 168 u32 res0:3; 169 u32 height:13; 170 u32 res1:3; 171 } bits; 172 }; 173 174 union vsu10_glb_alpha_reg { 175 u32 dwval; 176 struct { 177 u32 alpha:8; 178 u32 res0:24; 179 } bits; 180 }; 181 182 #define VSU10_STEP_VALID_START_BIT 1 183 #define VSU10_STEP_FRAC_BITWIDTH 19 184 #define VSU10_STEP_FIXED_BITWIDTH 4 185 union vsu10_step_reg { 186 u32 dwval; 187 struct { 188 u32 res0:1; 189 u32 frac:19; 190 u32 fixed:4; 191 u32 res1:8; 192 } bits; 193 }; 194 195 #define VSU10_PHASE_VALID_START_BIT 1 196 #define VSU10_PHASE_RRAC_BITWIDTH 19 197 #define VSU10_PHASE_FIXED_BITWIDTH 4 198 union vsu10_phase_reg { 199 u32 dwval; 200 struct { 201 u32 res0:VSU10_PHASE_VALID_START_BIT; 202 u32 frac:VSU10_PHASE_RRAC_BITWIDTH; 203 u32 fixed:VSU10_PHASE_FIXED_BITWIDTH; 204 u32 res1:8; 205 } bits; 206 }; 207 208 union vsu10_filter_coeff_reg { 209 u32 dwval; 210 struct { 211 u32 coeff0:8; 212 u32 coeff1:8; 213 u32 coeff2:8; 214 u32 coeff3:8; 215 } bits; 216 }; 217 218 struct vsu10_reg { 219 union vsu10_ctl_reg ctl; 220 u32 res0; 221 union vsu10_status_reg status; 222 union vsu10_field_ctl_reg field_ctl; 223 union vsu10_scale_mode_reg scale_mode; 224 u32 res1[11]; 225 union vsu10_size_reg out_size; 226 union vsu10_glb_alpha_reg glb_alpha; 227 u32 res2[14]; 228 union vsu10_size_reg y_in_size; 229 u32 res3; 230 union vsu10_step_reg y_hstep; 231 union vsu10_step_reg y_vstep; 232 union vsu10_phase_reg y_hphase; 233 u32 res4; 234 union vsu10_phase_reg y_vphase0; 235 union vsu10_phase_reg y_vphase1; 236 u32 res5[8]; 237 union vsu10_size_reg c_in_size; 238 u32 res6; 239 union vsu10_step_reg c_hstep; 240 union vsu10_step_reg c_vstep; 241 union vsu10_phase_reg c_hphase; 242 u32 res7; 243 union vsu10_phase_reg c_vphase0; 244 union vsu10_phase_reg c_vphase1; 245 u32 res8[72]; 246 union vsu10_filter_coeff_reg y_hori_coeff0[32]; 247 u32 res9[32]; 248 union vsu10_filter_coeff_reg y_hori_coeff1[32]; 249 u32 res10[32]; 250 union vsu10_filter_coeff_reg y_vert_coeff[32]; 251 u32 res11[96]; 252 union vsu10_filter_coeff_reg c_hori_coeff0[32]; 253 u32 res12[32]; 254 union vsu10_filter_coeff_reg c_hori_coeff1[32]; 255 u32 res13[32]; 256 union vsu10_filter_coeff_reg c_vert_coeff[32]; 257 }; 258 259 /* ********************************************************** */ 260 261 union vsu_ed_ctl_reg { 262 u32 dwval; 263 struct { 264 u32 en:1; 265 u32 res0:29; 266 u32 core_rest:1; 267 u32 res1:1; 268 } bits; 269 }; 270 271 union vsu_ed_status_reg { 272 u32 dwval; 273 struct { 274 u32 res0:4; 275 u32 busy:1; 276 u32 res1:11; 277 u32 line_cnt:12; 278 u32 res2:4; 279 } bits; 280 }; 281 282 union vsu_ed_field_ctl_reg { 283 u32 dwval; 284 struct { 285 u32 vphase_sel:1; 286 u32 res0:3; 287 u32 filed_reverse:1; 288 u32 sync_reverse:1; 289 u32 res1:26; 290 } bits; 291 }; 292 293 union vsu_ed_scale_mode_reg { 294 u32 dwval; 295 struct { 296 u32 mode:2; 297 u32 res0:30; 298 } bits; 299 }; 300 301 union vsu_ed_direction_thr_reg { 302 u32 dwval; 303 struct { 304 u32 vert_dir_thr:8; 305 u32 horz_dir_thr:8; 306 u32 zero_dir_thr:8; 307 u32 sub_zero_dir_thr:8; 308 } bits; 309 }; 310 311 union vsu_ed_edge_thr_reg { 312 u32 dwval; 313 struct { 314 u32 edge_offset:8; 315 u32 res0:8; 316 u32 edge_shift:4; 317 u32 res1:12; 318 } bits; 319 }; 320 321 union vsu_ed_direction_ctl_reg { 322 u32 dwval; 323 struct { 324 u32 clamp:1; 325 u32 res0:31; 326 } bits; 327 }; 328 329 union vsu_ed_angle_thr_reg { 330 u32 dwval; 331 struct { 332 u32 angle_offset:8; 333 u32 res0:8; 334 u32 angle_shift:4; 335 u32 res1:12; 336 } bits; 337 }; 338 339 union vsu_ed_sharp_en_reg { 340 u32 dwval; 341 struct { 342 u32 en:1; 343 u32 res0:31; 344 } bits; 345 }; 346 347 union vsu_ed_sharp_coring_reg { 348 u32 dwval; 349 struct { 350 u32 corth:10; 351 u32 res0:22; 352 } bits; 353 }; 354 355 union vsu_ed_sharp_gain0_reg { 356 u32 dwval; 357 struct { 358 u32 dipthr0:10; 359 u32 res0:6; 360 u32 dipthr1:10; 361 u32 res1:6; 362 } bits; 363 }; 364 365 union vsu_ed_sharp_gain1_reg { 366 u32 dwval; 367 struct { 368 u32 gain:8; 369 u32 res0:8; 370 u32 neggain:5; 371 u32 res1:3; 372 u32 beta:5; 373 u32 res2:3; 374 } bits; 375 }; 376 377 union vsu_ed_size_reg { 378 u32 dwval; 379 struct { 380 u32 width:13; 381 u32 res0:3; 382 u32 height:13; 383 u32 res1:3; 384 } bits; 385 }; 386 387 union vsu_ed_glb_alpha_reg { 388 u32 dwval; 389 struct { 390 u32 alpha:8; 391 u32 res0:24; 392 } bits; 393 }; 394 395 #define VSU_ED_STEP_VALID_START_BIT 1 396 #define VSU_ED_STEP_FRAC_BITWIDTH 19 397 #define VSU_ED_STEP_FIXED_BITWIDTH 4 398 union vsu_ed_step_reg { 399 u32 dwval; 400 struct { 401 u32 res0:VSU_ED_STEP_VALID_START_BIT; 402 u32 frac:VSU_ED_STEP_FRAC_BITWIDTH; 403 u32 fixed:VSU_ED_STEP_FIXED_BITWIDTH; 404 u32 res1:8; 405 } bits; 406 }; 407 408 #define VSU_ED_PHASE_VALID_START_BIT 1 409 #define VSU_ED_PHASE_RRAC_BITWIDTH 19 410 #define VSU_ED_PHASE_FIXED_BITWIDTH 4 411 union vsu_ed_phase_reg { 412 u32 dwval; 413 struct { 414 u32 res0:VSU_ED_PHASE_VALID_START_BIT; 415 u32 frac:VSU_ED_PHASE_RRAC_BITWIDTH; 416 u32 fixed:VSU_ED_PHASE_FIXED_BITWIDTH; 417 u32 res1:8; 418 } bits; 419 }; 420 421 union vsu_ed_filter_coeff_reg { 422 u32 dwval; 423 struct { 424 u32 coeff0:8; 425 u32 coeff1:8; 426 u32 coeff2:8; 427 u32 coeff3:8; 428 } bits; 429 }; 430 431 struct vsu_ed_reg { 432 union vsu_ed_ctl_reg ctl; 433 u32 res0; 434 union vsu_ed_status_reg status; 435 union vsu_ed_field_ctl_reg field_ctl; 436 union vsu_ed_scale_mode_reg scale_mode; 437 u32 res1[3]; 438 union vsu_ed_direction_thr_reg dir_thr; 439 union vsu_ed_edge_thr_reg edge_thr; 440 union vsu_ed_direction_ctl_reg dir_ctl; 441 union vsu_ed_angle_thr_reg angle_thr; 442 union vsu_ed_sharp_en_reg sharp_en; 443 union vsu_ed_sharp_coring_reg sharp_coring; 444 union vsu_ed_sharp_gain0_reg sharp_gain0; 445 union vsu_ed_sharp_gain1_reg sharp_gain1; 446 union vsu_ed_size_reg out_size; 447 union vsu_ed_glb_alpha_reg glb_alpha; 448 u32 res2[14]; 449 union vsu_ed_size_reg y_in_size; 450 u32 res3; 451 union vsu_ed_step_reg y_hstep; 452 union vsu_ed_step_reg y_vstep; 453 union vsu_ed_phase_reg y_hphase; 454 u32 res4; 455 union vsu_ed_phase_reg y_vphase0; 456 union vsu_ed_phase_reg y_vphase1; 457 u32 res5[8]; 458 union vsu_ed_size_reg c_in_size; 459 u32 res6; 460 union vsu_ed_step_reg c_hstep; 461 union vsu_ed_step_reg c_vstep; 462 union vsu_ed_phase_reg c_hphase; 463 u32 res7; 464 union vsu_ed_phase_reg c_vphase0; 465 union vsu_ed_phase_reg c_vphase1; 466 u32 res8[72]; 467 union vsu_ed_filter_coeff_reg y_hori_coeff0[32]; 468 u32 res9[32]; 469 union vsu_ed_filter_coeff_reg y_hori_coeff1[32]; 470 u32 res10[32]; 471 union vsu_ed_filter_coeff_reg y_vert_coeff[32]; 472 u32 res11[96]; 473 union vsu_ed_filter_coeff_reg c_hori_coeff0[32]; 474 u32 res12[32]; 475 union vsu_ed_filter_coeff_reg c_hori_coeff1[32]; 476 u32 res13[32]; 477 union vsu_ed_filter_coeff_reg c_vert_coeff[32]; 478 }; 479 480 #endif /* #ifndef _DE_VSU_TYPE_H_ */ 481