1 /*
2 * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 *
18 * Description:
19 */
20 /*
21 * AMLOGIC demux driver.
22 */
23
24 #include <linux/version.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/mutex.h>
28 #include <linux/wait.h>
29 #include <linux/string.h>
30 #include <linux/interrupt.h>
31 #include <linux/fs.h>
32 #include <linux/cdev.h>
33 #include <linux/device.h>
34 #include <linux/spinlock.h>
35 #include <linux/fcntl.h>
36 #include <asm/irq.h>
37 #include <linux/uaccess.h>
38 #include <linux/poll.h>
39 #include <linux/delay.h>
40 #include <linux/platform_device.h>
41 #include <linux/delay.h>
42 #include <asm/cacheflush.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/pinctrl/pinmux.h>
45 #include <linux/vmalloc.h>
46 #include <linux/amlogic/media/codec_mm/codec_mm.h>
47 #include <linux/amlogic/media/codec_mm/configs.h>
48 #include "../../amports/streambuf.h"
49 #include "c_stb_define.h"
50 #include "c_stb_regs_define.h"
51 #include "aml_dvb.h"
52 #include "aml_dvb_reg.h"
53
54
55 #define ENABLE_SEC_BUFF_WATCHDOG
56 #define USE_AHB_MODE
57 #define PR_ERROR_SPEED_LIMIT
58
59 #define pr_dbg_flag(_f, _args...)\
60 do {\
61 if (debug_dmx&(_f))\
62 printk(_args);\
63 } while (0)
64 #define pr_dbg_irq_flag(_f, _args...)\
65 do {\
66 if (debug_irq&(_f))\
67 printk(_args);\
68 } while (0)
69 #define pr_dbg(args...) pr_dbg_flag(0x1, args)
70 #define pr_dbg_irq(args...)pr_dbg_irq_flag(0x1, args)
71 #define pr_dbg_irq_dvr(args...)pr_dbg_irq_flag(0x2, args)
72 #define pr_dbg_sf(args...) pr_dbg_flag(0x4, args)
73 #define pr_dbg_irq_sf(args...) pr_dbg_irq_flag(0x4, args)
74 #define pr_dbg_ss(args...) pr_dbg_flag(0x8, args)
75 #define pr_dbg_irq_ss(args...) pr_dbg_irq_flag(0x8, args)
76 #define pr_dbg_irq_pes(args...) pr_dbg_irq_flag(0x10, args)
77 #define pr_dbg_irq_sub(args...) pr_dbg_irq_flag(0x20, args)
78
79 #ifdef PR_ERROR_SPEED_LIMIT
80 static u32 last_pr_error_time;
81 #define pr_error(fmt, _args...)\
82 do {\
83 u32 diff = jiffies_to_msecs(jiffies - last_pr_error_time);\
84 if (!last_pr_error_time || diff > 50) {\
85 pr_err("DVB:" fmt, ## _args);\
86 last_pr_error_time = jiffies;\
87 } \
88 } while (0)
89 #else
90 #define pr_error(fmt, args...) pr_err("DVB: " fmt, ## args)
91 #endif
92
93 #define pr_inf(fmt, args...) printk("DVB: " fmt, ## args)
94
95 #define dump(b, l) \
96 do { \
97 int i; \
98 printk("dump: "); \
99 for (i = 0; i < (l); i++) {\
100 if (!(i&0xf)) \
101 printk("\n\t"); \
102 printk("%02x ", *(((unsigned char *)(b))+i)); \
103 } \
104 printk("\n"); \
105 } while (0)
106
107 MODULE_PARM_DESC(debug_dmx, "\n\t\t Enable demux debug information");
108 static int debug_dmx;
109 module_param(debug_dmx, int, 0644);
110
111 MODULE_PARM_DESC(debug_irq, "\n\t\t Enable demux IRQ debug information");
112 static int debug_irq;
113 module_param(debug_irq, int, 0644);
114
115 MODULE_PARM_DESC(disable_dsc, "\n\t\t Disable discrambler");
116 static int disable_dsc;
117 module_param(disable_dsc, int, 0644);
118
119 MODULE_PARM_DESC(enable_sec_monitor, "\n\t\t Enable sec monitor default is enable");
120 static int enable_sec_monitor = 2;
121 module_param(enable_sec_monitor, int, 0644);
122 /*For old version kernel */
123 #ifndef MESON_CPU_MAJOR_ID_GXL
124 #define MESON_CPU_MAJOR_ID_GXL 0x21
125 #endif
126
127 static int npids = CHANNEL_COUNT;
128 #define MOD_PARAM_DECLARE_CHANPIDS(_dmx) \
129 MODULE_PARM_DESC(debug_dmx##_dmx##_chanpids, "\n\t\t pids of dmx channels"); \
130 static short debug_dmx##_dmx##_chanpids[CHANNEL_COUNT] = \
131 {[0 ... (CHANNEL_COUNT - 1)] = -1}; \
132 module_param_array(debug_dmx##_dmx##_chanpids, short, &npids, 0444)
133
134 #define CIPLUS_OUTPUT_AUTO 8
135 static int ciplus_out_sel = CIPLUS_OUTPUT_AUTO;
136 static int ciplus_out_auto_mode = 1;
137 static u32 ciplus = 0;
138 #define CIPLUS_OUT_SEL 28
139 #define CIPLUS_IN_SEL 26
140
141 MOD_PARAM_DECLARE_CHANPIDS(0);
142 MOD_PARAM_DECLARE_CHANPIDS(1);
143 MOD_PARAM_DECLARE_CHANPIDS(2);
144
145 #define set_debug_dmx_chanpids(_dmx, _idx, _pid)\
146 do { \
147 if ((_dmx) == 0) \
148 debug_dmx0_chanpids[(_idx)] = (_pid); \
149 else if ((_dmx) == 1) \
150 debug_dmx1_chanpids[(_idx)] = (_pid); \
151 else if ((_dmx) == 2) \
152 debug_dmx2_chanpids[(_idx)] = (_pid); \
153 } while (0)
154
155 MODULE_PARM_DESC(debug_sf_user, "\n\t\t only for sf mode check");
156 static int debug_sf_user;
157 module_param(debug_sf_user, int, 0444);
158
159 MODULE_PARM_DESC(force_sec_sf, "\n\t\t force sf mode for sec filter");
160 static int force_sec_sf;
161 module_param(force_sec_sf, int, 0644);
162
163 MODULE_PARM_DESC(force_pes_sf, "\n\t\t force sf mode for pes filter");
164 static int force_pes_sf;
165 module_param(force_pes_sf, int, 0644);
166
167 MODULE_PARM_DESC(use_of_sop, "\n\t\t Enable use of sop input");
168 static int use_of_sop;
169 module_param(use_of_sop, int, 0644);
170
171 /*#define CIPLUS_KEY0 0x16f8
172 #define CIPLUS_KEY1 0x16f9
173 #define CIPLUS_KEY2 0x16fa
174 #define CIPLUS_KEY3 0x16fb
175 #define CIPLUS_KEY_WR 0x16fc
176 #define CIPLUS_CONFIG 0x16fd
177 #define CIPLUS_ENDIAN 0x16fe*/
178
179
180 static u32 old_stb_top_config;
181 static u32 old_fec_input_control;
182 static int have_old_stb_top_config = 1;
183 static int have_old_fec_input_control = 1;
184
185 static long pes_off_pre[DMX_DEV_COUNT];
186
187 static void
dmx_write_reg(int r,u32 v)188 dmx_write_reg(int r, u32 v)
189 {
190 u32 oldv, mask;
191
192 if (disable_dsc) {
193 if (r == STB_TOP_CONFIG) {
194 if (have_old_stb_top_config) {
195 oldv = old_stb_top_config;
196 have_old_stb_top_config = 0;
197 } else {
198 oldv = READ_MPEG_REG(STB_TOP_CONFIG);
199 }
200
201 mask = (1<<7)|(1<<15)|(3<<26)|(7<<28);
202 v &= ~mask;
203 v |= (oldv & mask);
204 } else if (r == FEC_INPUT_CONTROL) {
205 if (have_old_fec_input_control) {
206 oldv = old_fec_input_control;
207 have_old_fec_input_control = 0;
208 } else {
209 oldv = READ_MPEG_REG(FEC_INPUT_CONTROL);
210 }
211
212 mask = (1<<15);
213 v &= ~mask;
214 v |= (oldv & mask);
215 } else if ((r == RESET1_REGISTER) || (r == RESET3_REGISTER)) {
216 if (!have_old_stb_top_config) {
217 have_old_stb_top_config = 1;
218 old_stb_top_config =
219 READ_MPEG_REG(STB_TOP_CONFIG);
220 }
221 if (!have_old_fec_input_control) {
222 have_old_fec_input_control = 1;
223 old_fec_input_control =
224 READ_MPEG_REG(FEC_INPUT_CONTROL);
225 }
226 } else if ((r == TS_PL_PID_INDEX) || (r == TS_PL_PID_DATA)
227 || (r == COMM_DESC_KEY0)
228 || (r == COMM_DESC_KEY1)
229 || (r == COMM_DESC_KEY_RW)
230 || (r == CIPLUS_KEY0)
231 || (r == CIPLUS_KEY1)
232 || (r == CIPLUS_KEY2)
233 || (r == CIPLUS_KEY3)
234 || (r == CIPLUS_KEY_WR)
235 || (r == CIPLUS_CONFIG)
236 || (r == CIPLUS_ENDIAN)) {
237 return;
238 }
239 }
240 WRITE_MPEG_REG(r, v);
241 }
242
243 #undef WRITE_MPEG_REG
244 #define WRITE_MPEG_REG(r, v) dmx_write_reg(r, v)
245
246 #define DMX_READ_REG(i, r)\
247 ((i)?((i == 1)?READ_MPEG_REG(r##_2) :\
248 READ_MPEG_REG(r##_3)) : READ_MPEG_REG(r))
249
250 #define DMX_WRITE_REG(i, r, d)\
251 do {\
252 if (i == 1) {\
253 WRITE_MPEG_REG(r##_2, d);\
254 } else if (i == 2) {\
255 WRITE_MPEG_REG(r##_3, d);\
256 } \
257 else {\
258 WRITE_MPEG_REG(r, d);\
259 } \
260 } while (0)
261
262 #define READ_PERI_REG READ_CBUS_REG
263 #define WRITE_PERI_REG WRITE_CBUS_REG
264
265 #define READ_ASYNC_FIFO_REG(i, r)\
266 ((i) ? ((i-1)?READ_PERI_REG(ASYNC_FIFO1_##r):\
267 READ_PERI_REG(ASYNC_FIFO2_##r)) : READ_PERI_REG(ASYNC_FIFO_##r))
268
269 #define WRITE_ASYNC_FIFO_REG(i, r, d)\
270 do {\
271 if (i == 2) {\
272 WRITE_PERI_REG(ASYNC_FIFO1_##r, d);\
273 } else if (i == 0) {\
274 WRITE_PERI_REG(ASYNC_FIFO_##r, d);\
275 } else {\
276 WRITE_PERI_REG(ASYNC_FIFO2_##r, d);\
277 } \
278 } while (0)
279
280 #define CLEAR_ASYNC_FIFO_REG_MASK(i, reg, mask) \
281 WRITE_ASYNC_FIFO_REG(i, reg, \
282 (READ_ASYNC_FIFO_REG(i, reg)&(~(mask))))
283
284 #define DVR_FEED(f) \
285 ((f) && ((f)->type == DMX_TYPE_TS) && \
286 (((f)->ts_type & (TS_PACKET | TS_DEMUX)) == TS_PACKET))
287
288 #define MOD_PARAM_DECLARE_CHANREC(_dmx) \
289 MODULE_PARM_DESC(dmx##_dmx##_chanrec_enable, \
290 "\n\t\t record by channel, one time use in the beginning"); \
291 static int dmx##_dmx##_chanrec_enable; \
292 module_param(dmx##_dmx##_chanrec_enable, int, 0644); \
293 MODULE_PARM_DESC(dmx##_dmx##_chanrec, "\n\t\t record channels bits"); \
294 static int dmx##_dmx##_chanrec; \
295 module_param(dmx##_dmx##_chanrec, int, 0644)
296
297 MOD_PARAM_DECLARE_CHANREC(0);
298 MOD_PARAM_DECLARE_CHANREC(1);
299 MOD_PARAM_DECLARE_CHANREC(2);
300
301 #define MOD_PARAM_DECLARE_CHANPROC(_dmx) \
302 MODULE_PARM_DESC(dmx##_dmx##_chanproc_enable, "channel further processing"); \
303 static int dmx##_dmx##_chanproc_enable; \
304 module_param(dmx##_dmx##_chanproc_enable, int, 0644); \
305 MODULE_PARM_DESC(dmx##_dmx##_chanproc, "further process channels bits"); \
306 static int dmx##_dmx##_chanproc; \
307 module_param(dmx##_dmx##_chanproc, int, 0644)
308
309 MOD_PARAM_DECLARE_CHANPROC(0);
310 MOD_PARAM_DECLARE_CHANPROC(1);
311 MOD_PARAM_DECLARE_CHANPROC(2);
312
313 #define DMX_CH_OP_CHANREC 0
314 #define DMX_CH_OP_CHANPROC 1
315
_setbit(int v,int b)316 static inline int _setbit(int v, int b) { return v|(1<<b); }
_clrbit(int v,int b)317 static inline int _clrbit(int v, int b) { return v&~(1<<b); }
_set(int v,int b)318 static inline int _set(int v, int b) { return b; }
319
320 static int dsc_set_csa_key(struct aml_dsc_channel *ch, int flags,
321 enum ca_cw_type type, u8 *key);
322 static int dsc_set_aes_des_sm4_key(struct aml_dsc_channel *ch, int flags,
323 enum ca_cw_type type, u8 *key);
324 static void aml_ci_plus_disable(void);
325 static void am_ci_plus_set_output(struct aml_dsc_channel *ch);
326 static int set_subtitle_pes_buffer(struct aml_dmx *dmx);
327
dmxn_op_chan(int dmx,int ch,int (* op)(int,int),int ch_op)328 static void dmxn_op_chan(int dmx, int ch, int(*op)(int, int), int ch_op)
329 {
330 int enable_0, enable_1, enable_2;
331 int *set_0, *set_1, *set_2;
332 int reg;
333
334 if (ch_op == DMX_CH_OP_CHANREC) {
335 enable_0 = dmx0_chanrec_enable;
336 enable_1 = dmx1_chanrec_enable;
337 enable_2 = dmx2_chanrec_enable;
338 set_0 = &dmx0_chanrec;
339 set_1 = &dmx1_chanrec;
340 set_2 = &dmx2_chanrec;
341 reg = DEMUX_CHAN_RECORD_EN;
342 } else if (ch_op == DMX_CH_OP_CHANPROC) {
343 enable_0 = dmx0_chanproc_enable;
344 enable_1 = dmx1_chanproc_enable;
345 enable_2 = dmx2_chanproc_enable;
346 set_0 = &dmx0_chanproc;
347 set_1 = &dmx1_chanproc;
348 set_2 = &dmx2_chanproc;
349 reg = DEMUX_CHAN_PROCESS_EN;
350 } else {
351 return;
352 }
353 if (dmx == 0) {
354 if (enable_0) {
355 *set_0 = op(*set_0, ch);
356 WRITE_MPEG_REG(reg+DEMUX_1_OFFSET, *set_0);
357 }
358 } else if (dmx == 1) {
359 if (enable_1) {
360 *set_1 = op(*set_1, ch);
361 WRITE_MPEG_REG(reg+DEMUX_2_OFFSET, *set_1);
362 }
363 } else if (dmx == 2) {
364 if (enable_2) {
365 *set_2 = op(*set_2, ch);
366 WRITE_MPEG_REG(reg+DEMUX_3_OFFSET, *set_2);
367 }
368 }
369 }
370 #define dmx_add_recchan(_dmx, _chid) \
371 do { \
372 pr_dbg("dmx[%d]_add_recchan[%d]\n", _dmx, _chid); \
373 dmxn_op_chan(_dmx, _chid, _setbit, DMX_CH_OP_CHANREC); \
374 } while (0)
375 #define dmx_rm_recchan(_dmx, _chid) \
376 do { \
377 pr_dbg("dmx[%d]_rm_recchan[%ld]\n", _dmx, _chid); \
378 dmxn_op_chan(_dmx, _chid, _clrbit, DMX_CH_OP_CHANREC); \
379 } while (0)
380 #define dmx_set_recchan(_dmx, _chs) \
381 do { \
382 pr_dbg("dmx[%d]_set_recchan[%d]\n", _dmx, _chs); \
383 dmxn_op_chan(_dmx, _chs, _set, DMX_CH_OP_CHANREC); \
384 } while (0)
385
386 #define dmx_add_procchan(_dmx, _chid) \
387 do { \
388 pr_dbg("dmx[%d]_add_procchan[%d]\n", _dmx, _chid); \
389 dmxn_op_chan(_dmx, _chid, _setbit, DMX_CH_OP_CHANPROC); \
390 } while (0)
391 #define dmx_rm_procchan(_dmx, _chid) \
392 do { \
393 pr_dbg("dmx[%d]_rm_procchan[%ld]\n", _dmx, _chid); \
394 dmxn_op_chan(_dmx, _chid, _clrbit, DMX_CH_OP_CHANPROC); \
395 } while (0)
396 #define dmx_set_procchan(_dmx, _chs) \
397 do { \
398 pr_dbg("dmx[%d]_set_procchan[%d]\n", _dmx, _chs); \
399 dmxn_op_chan(_dmx, _chs, _set, DMX_CH_OP_CHANPROC); \
400 } while (0)
401
402 #define NO_SUB
403 #define SUB_BUF_DMX
404 #define SUB_PARSER
405
406 #ifndef SUB_BUF_DMX
407 #undef SUB_PARSER
408 #endif
409
410 #define SUB_BUF_SHARED
411 #define PES_BUF_SHARED
412
413 #define SYS_CHAN_COUNT (4)
414 #define SEC_GRP_LEN_0 (0xc)
415 #define SEC_GRP_LEN_1 (0xc)
416 #define SEC_GRP_LEN_2 (0xc)
417 #define SEC_GRP_LEN_3 (0xc)
418 #define LARGE_SEC_BUFF_MASK 0xFFFFFFFF
419 #define LARGE_SEC_BUFF_COUNT 32
420 #define WATCHDOG_TIMER 250
421 #define ASYNCFIFO_BUFFER_SIZE_DEFAULT (512*1024)
422
423 #define DEMUX_INT_MASK\
424 ((0<<(AUDIO_SPLICING_POINT)) |\
425 (0<<(VIDEO_SPLICING_POINT)) |\
426 (1<<(OTHER_PES_READY)) |\
427 (1<<(PCR_READY)) |\
428 (1<<(SUB_PES_READY)) |\
429 (1<<(SECTION_BUFFER_READY)) |\
430 (0<<(OM_CMD_READ_PENDING)) |\
431 (1<<(TS_ERROR_PIN)) |\
432 (1<<(NEW_PDTS_READY)) |\
433 (0<<(DUPLICATED_PACKET)) |\
434 (0<<(DIS_CONTINUITY_PACKET)))
435
436 #define TS_SRC_MAX 3
437
438 /*Reset the demux device*/
439 #define RESET_DEMUX2 (1<<15)
440 #define RESET_DEMUX1 (1<<14)
441 #define RESET_DEMUX0 (1<<13)
442 #define RESET_S2P1 (1<<12)
443 #define RESET_S2P0 (1<<11)
444 #define RESET_DES (1<<10)
445 #define RESET_TOP (1<<9)
446
447 static int dmx_remove_feed(struct aml_dmx *dmx, struct dvb_demux_feed *feed);
448 static void reset_async_fifos(struct aml_dvb *dvb);
449 static int dmx_add_feed(struct aml_dmx *dmx, struct dvb_demux_feed *feed);
450 static int dmx_smallsec_set(struct aml_smallsec *ss, int enable, int bufsize,
451 int force);
452 static int dmx_timeout_set(struct aml_dmxtimeout *dto, int enable,
453 int timeout, int ch_dis, int nomatch,
454 int force);
455
456 /*Audio & Video PTS value*/
457 static u32 video_pts = 0;
458 static u32 audio_pts = 0;
459 static u32 video_pts_bit32 = 0;
460 static u32 audio_pts_bit32 = 0;
461 static u32 first_video_pts = 0;
462 static u32 first_audio_pts = 0;
463 static int demux_skipbyte;
464 static int tsfile_clkdiv = 5;
465 static int asyncfifo_buf_len = ASYNCFIFO_BUFFER_SIZE_DEFAULT;
466
467 #define SF_DMX_ID 2
468 #define SF_AFIFO_ID 1
469
470 #define sf_dmx_sf(_dmx) \
471 (((_dmx)->id == SF_DMX_ID) \
472 && ((struct aml_dvb *)(_dmx)->demux.priv)->swfilter.user)
473 #define sf_afifo_sf(_afifo) \
474 (((_afifo)->id == SF_AFIFO_ID) && (_afifo)->dvb->swfilter.user)
475 #define dmx_get_dev(dmx) (((struct aml_dvb *)((dmx)->demux.priv))->dev)
476 #define asyncfifo_get_dev(afifo) ((afifo)->dvb->dev)
477
478
479
480 /*Section buffer watchdog*/
section_buffer_watchdog_func(unsigned long arg)481 static void section_buffer_watchdog_func(unsigned long arg)
482 {
483 struct aml_dvb *dvb = (struct aml_dvb *)arg;
484 struct aml_dmx *dmx;
485 u32 section_busy32 = 0, om_cmd_status32 = 0,
486 demux_channel_activity32 = 0;
487 u16 demux_int_status1 = 0;
488 u32 device_no = 0;
489 u32 filter_number = 0;
490 u32 i = 0;
491 unsigned long flags;
492
493 spin_lock_irqsave(&dvb->slock, flags);
494
495 for (device_no = 0; device_no < DMX_DEV_COUNT; device_no++) {
496
497 dmx = &dvb->dmx[device_no];
498
499 if (dvb->dmx_watchdog_disable[device_no])
500 continue;
501
502 if (!dmx->init)
503 continue;
504
505 om_cmd_status32 =
506 DMX_READ_REG(device_no, OM_CMD_STATUS);
507 demux_channel_activity32 =
508 DMX_READ_REG(device_no, DEMUX_CHANNEL_ACTIVITY);
509 section_busy32 =
510 DMX_READ_REG(device_no, SEC_BUFF_BUSY);
511
512 if (om_cmd_status32 & 0x8fc2) {
513 /* bit 15:12 -- om_cmd_count (read only) */
514 /* bit 11:9 -- overflow_count */
515 /* bit 11:9 -- om_cmd_wr_ptr(read only) */
516 /* bit 8:6 -- om_overwrite_count */
517 /* bit 8:6 -- om_cmd_rd_ptr(read only) */
518 /* bit 5:3 -- type_stb_om_w_rd(read only) */
519 /* bit 2 -- unit_start_stb_om_w_rd(read only) */
520 /* bit 1 -- om_cmd_overflow(read only) */
521 /* bit 0 -- om_cmd_pending(read) */
522 /* bit 0 -- om_cmd_read_finished(write) */
523 /*BUG: If the recoder is running, return */
524 if (!dmx->record) {
525 /* OM status is wrong */
526 dmx->om_status_error_count++;
527 pr_dbg("demux om status \n"
528 "%04x\t%03x\t%03x\t%03x\t%01x\t%01x\t"
529 "%x\t%x\tdmx%d:status:0x%xerr_cnt:%d-%d\n",
530 (om_cmd_status32 >> 12) & 0xf,
531 (om_cmd_status32 >> 9) & 0x7,
532 (om_cmd_status32 >> 6) & 0x7,
533 (om_cmd_status32 >> 3) & 0x7,
534 (om_cmd_status32 >> 2) & 0x1,
535 (om_cmd_status32 >> 1) & 0x1,
536 demux_channel_activity32, section_busy32,
537 dmx->id, om_cmd_status32, dmx->om_status_error_count, enable_sec_monitor);
538 if (enable_sec_monitor &&
539 dmx->om_status_error_count > enable_sec_monitor) {
540 /*Reset the demux */
541 dmx_reset_dmx_hw_ex_unlock(dvb, dmx, 0);
542 /* Reset the error count */
543 dmx->om_status_error_count = 0;
544 goto end;
545 }
546 }
547 } else {
548 /* OM status is correct, reset the error count */
549 dmx->om_status_error_count = 0;
550 }
551 section_busy32 =
552 DMX_READ_REG(device_no, SEC_BUFF_BUSY);
553 if (LARGE_SEC_BUFF_MASK ==
554 (section_busy32 & LARGE_SEC_BUFF_MASK)) {
555 /*All the largest section buffers occupied,
556 * clear buffers
557 */
558 DMX_WRITE_REG(device_no,
559 SEC_BUFF_READY, section_busy32);
560 } else {
561 for (i = 0; i < SEC_BUF_COUNT; i++) {
562 if (!(section_busy32 & (1 << i)))
563 continue;
564 DMX_WRITE_REG(device_no, SEC_BUFF_NUMBER, i);
565 filter_number = DMX_READ_REG(device_no,
566 SEC_BUFF_NUMBER);
567 filter_number >>= 8;
568 if ((filter_number >= FILTER_COUNT)
569 /* >=31, do not handle this case */
570 || ((filter_number < FILTER_COUNT)
571 && dmx->filter[filter_number].used))
572 section_busy32 &= ~(1 << i);
573 }
574 if (section_busy32 & (dmx->smallsec.enable ?
575 0x7FFFFFFF :
576 LARGE_SEC_BUFF_MASK)) {
577 /*Clear invalid buffers */
578 DMX_WRITE_REG(device_no,
579 SEC_BUFF_READY,
580 section_busy32);
581 pr_error("clear invalid buffer 0x%x\n",
582 section_busy32);
583 }
584 #if 0
585 section_busy32 = 0x7fffffff;
586 for (i = 0; i < SEC_BUF_BUSY_SIZE; i++) {
587 dmx->section_busy[i] = (
588 (i == SEC_BUF_BUSY_SIZE - 1) ?
589 DMX_READ_REG(device_no, SEC_BUFF_BUSY) :
590 dmx->section_busy[i + 1]);
591 section_busy32 &= dmx->section_busy[i];
592 }
593
594 /*count the number of '1' bits */
595 i = section_busy32;
596 i = (i & 0x55555555) + ((i & 0xaaaaaaaa) >> 1);
597 i = (i & 0x33333333) + ((i & 0xcccccccc) >> 2);
598 i = (i & 0x0f0f0f0f) + ((i & 0xf0f0f0f0) >> 4);
599 i = (i & 0x00ff00ff) + ((i & 0xff00ff00) >> 8);
600 i = (i & 0x0000ffff) + ((i & 0xffff0000) >> 16);
601 if (i > LARGE_SEC_BUFF_COUNT) {
602 /*too long some of the section
603 * buffers are being processed
604 */
605 DMX_WRITE_REG(device_no, SEC_BUFF_READY,
606 section_busy32);
607 }
608 #endif
609 }
610 demux_int_status1 =
611 DMX_READ_REG(device_no, STB_INT_STATUS) & 0xfff7;
612 if (demux_int_status1 & (1 << TS_ERROR_PIN)) {
613 DMX_WRITE_REG(device_no,
614 STB_INT_STATUS,
615 (1 << TS_ERROR_PIN));
616 }
617 }
618
619 end:
620 spin_unlock_irqrestore(&dvb->slock, flags);
621 #ifdef ENABLE_SEC_BUFF_WATCHDOG
622 mod_timer(&dvb->watchdog_timer,
623 jiffies + msecs_to_jiffies(WATCHDOG_TIMER));
624 #endif
625 }
626
sec_filter_match(struct aml_dmx * dmx,struct aml_filter * f,u8 * p)627 static inline int sec_filter_match(struct aml_dmx *dmx, struct aml_filter *f,
628 u8 *p)
629 {
630 int b;
631 u8 neq = 0;
632
633 if (!f->used || !dmx->channel[f->chan_id].used)
634 return 0;
635
636 for (b = 0; b < FILTER_LEN; b++) {
637 u8 xor = p[b] ^ f->value[b];
638
639 if (xor & f->maskandmode[b])
640 return 0;
641
642 if (xor & f->maskandnotmode[b])
643 neq = 1;
644 }
645
646 if (f->neq && !neq)
647 return 0;
648
649 return 1;
650 }
651
trigger_crc_monitor(struct aml_dmx * dmx)652 static void trigger_crc_monitor(struct aml_dmx *dmx)
653 {
654 if (!dmx->crc_check_time) {
655 dmx->crc_check_time = jiffies;
656 dmx->crc_check_count = 0;
657 }
658
659 if (dmx->crc_check_count > 100) {
660 if (jiffies_to_msecs(jiffies - dmx->crc_check_time) <= 1000) {
661 struct aml_dvb *dvb = (struct aml_dvb *)dmx->demux.priv;
662
663 pr_error("Too many crc fail (%d crc fail in %d ms)!\n",
664 dmx->crc_check_count,
665 jiffies_to_msecs(jiffies - dmx->crc_check_time)
666 );
667 dmx_reset_dmx_hw_ex_unlock(dvb, dmx, 0);
668 }
669 dmx->crc_check_time = 0;
670 }
671
672 dmx->crc_check_count++;
673 }
section_crc(struct aml_dmx * dmx,struct aml_filter * f,u8 * p)674 static int section_crc(struct aml_dmx *dmx, struct aml_filter *f, u8 *p)
675 {
676 int sec_len = (((p[1] & 0xF) << 8) | p[2]) + 3;
677 struct dvb_demux_feed *feed = dmx->channel[f->chan_id].feed;
678
679 if (feed->feed.sec.check_crc) {
680 struct dvb_demux *demux = feed->demux;
681 struct dmx_section_feed *sec = &feed->feed.sec;
682 int section_syntax_indicator;
683
684 section_syntax_indicator = ((p[1] & 0x80) != 0);
685 sec->seclen = sec_len;
686 sec->crc_val = ~0;
687 if (demux->check_crc32(feed, p, sec_len)) {
688 pr_error("section CRC check failed! pid[%d]\n", feed->pid);
689
690 #if 0
691 {
692 int i;
693
694 pr_error("sec:[%#lx:%#lx:%#lx-%#lx:%#lx:%#lx-%#lx:%#lx:%#lx]\n",
695 dmx->sec_cnt[0], dmx->sec_cnt_match[0], dmx->sec_cnt_crc_fail[0],
696 dmx->sec_cnt[1], dmx->sec_cnt_match[1], dmx->sec_cnt_crc_fail[1],
697 dmx->sec_cnt[2], dmx->sec_cnt_match[2], dmx->sec_cnt_crc_fail[2]);
698 pr_error("bad sec[%d]:\n", sec_len);
699 /*
700 * if (sec_len > 256)
701 * sec_len = 256;
702 * for (i = 0; i < sec_len; i++) {
703 * pr_err("%02x ", p[i]);
704 * if (!((i + 1) % 16))
705 * pr_err("\n");
706 * }
707 */
708 }
709 #endif
710 trigger_crc_monitor(dmx);
711 return 0;
712 }
713 #if 0
714 int i;
715
716 for (i = 0; i < sec_len; i++) {
717 pr_dbg("%02x ", p[i]);
718 if (!((i + 1) % 16))
719 pr_dbg("\n");
720 }
721 pr_dbg("\nsection data\n");
722 #endif
723 }
724
725 return 1;
726 }
727
section_notify(struct aml_dmx * dmx,struct aml_filter * f,u8 * p)728 static void section_notify(struct aml_dmx *dmx, struct aml_filter *f, u8 *p)
729 {
730 int sec_len = (((p[1] & 0xF) << 8) | p[2]) + 3;
731 struct dvb_demux_feed *feed = dmx->channel[f->chan_id].feed;
732
733 if (feed && feed->cb.sec)
734 feed->cb.sec(p, sec_len, NULL, 0, f->filter);
735 }
736
hardware_match_section(struct aml_dmx * dmx,u16 sec_num,u16 buf_num)737 static void hardware_match_section(struct aml_dmx *dmx,
738 u16 sec_num, u16 buf_num)
739 {
740 u8 *p = (u8 *) dmx->sec_buf[buf_num].addr;
741 struct aml_filter *f;
742 int chid, i;
743 int need_crc = 1;
744
745 if (sec_num >= FILTER_COUNT) {
746 pr_dbg("sec_num invalid: %d\n", sec_num);
747 return;
748 }
749
750 dma_sync_single_for_cpu(dmx_get_dev(dmx),
751 dmx->sec_pages_map + (buf_num << 0x0c),
752 (1 << 0x0c), DMA_FROM_DEVICE);
753
754 f = &dmx->filter[sec_num];
755 chid = f->chan_id;
756
757 dmx->sec_cnt[SEC_CNT_HW]++;
758
759 for (i = 0; i < FILTER_COUNT; i++) {
760 f = &dmx->filter[i];
761 if (f->chan_id != chid)
762 continue;
763 if (sec_filter_match(dmx, f, p)) {
764 if (need_crc) {
765 dmx->sec_cnt_match[SEC_CNT_HW]++;
766 if (!section_crc(dmx, f, p)) {
767 dmx->sec_cnt_crc_fail[SEC_CNT_HW]++;
768 return;
769 }
770 need_crc = 0;
771 }
772 section_notify(dmx, f, p);
773 }
774 }
775 }
776
software_match_section(struct aml_dmx * dmx,u16 buf_num)777 static void software_match_section(struct aml_dmx *dmx, u16 buf_num)
778 {
779 u8 *p = (u8 *) dmx->sec_buf[buf_num].addr;
780 struct aml_filter *f, *fmatch = NULL;
781 int i, fid = -1;
782
783 dma_sync_single_for_cpu(dmx_get_dev(dmx),
784 dmx->sec_pages_map + (buf_num << 0x0c),
785 (1 << 0x0c), DMA_FROM_DEVICE);
786
787 dmx->sec_cnt[SEC_CNT_SW]++;
788
789 for (i = 0; i < FILTER_COUNT; i++) {
790 f = &dmx->filter[i];
791
792 if (sec_filter_match(dmx, f, p)) {
793 pr_dbg("[software match]filter %d match, pid %d\n",
794 i, dmx->channel[f->chan_id].pid);
795 if (!fmatch) {
796 fmatch = f;
797 fid = i;
798 } else {
799 pr_error("[sw match]Muli-filter match this\n"
800 "section, will skip this section\n");
801 return;
802 }
803 }
804 }
805
806 if (fmatch) {
807 pr_dbg("[software match]dispatch\n"
808 "section to filter %d pid %d\n",
809 fid, dmx->channel[fmatch->chan_id].pid);
810 dmx->sec_cnt_match[SEC_CNT_SW]++;
811 if (section_crc(dmx, fmatch, p))
812 section_notify(dmx, fmatch, p);
813 else
814 dmx->sec_cnt_crc_fail[SEC_CNT_SW]++;
815 } else {
816 pr_dbg("[software match]this section do not\n"
817 "match any filter!!!\n");
818 }
819 }
820
821
_rbuf_write(struct dvb_ringbuffer * buf,const u8 * src,size_t len)822 static int _rbuf_write(struct dvb_ringbuffer *buf, const u8 *src, size_t len)
823 {
824 ssize_t free;
825
826 if (!len)
827 return 0;
828 if (!buf->data)
829 return 0;
830
831 free = dvb_ringbuffer_free(buf);
832 if (len > free) {
833 pr_error("sf: buffer overflow\n");
834 return -EOVERFLOW;
835 }
836
837 return dvb_ringbuffer_write(buf, src, len);
838 }
839
_rbuf_filter_pkts(struct dvb_ringbuffer * rb,u8 * wrapbuf,void (* swfilter_packets)(struct dvb_demux * demux,const u8 * buf,size_t count),struct dvb_demux * demux)840 static int _rbuf_filter_pkts(struct dvb_ringbuffer *rb,
841 u8 *wrapbuf,
842 void (*swfilter_packets)(struct dvb_demux *demux,
843 const u8 *buf,
844 size_t count),
845 struct dvb_demux *demux)
846 {
847 ssize_t len1 = 0;
848 ssize_t len2 = 0;
849 size_t off;
850 size_t count;
851 size_t size;
852
853 if (debug_irq & 0x4)
854 dump(&rb->data[rb->pread], (debug_irq & 0xFFF00) >> 8);
855
856 /*
857 * rb|====--------===[0x47]====|
858 * ^ ^
859 * wr rd
860 */
861
862 len1 = rb->pwrite - rb->pread;
863 if (len1 < 0) {
864 len1 = rb->size - rb->pread;
865 len2 = rb->pwrite;
866 }
867
868 for (off = 0; off < len1; off++) {
869 if (rb->data[rb->pread + off] == 0x47)
870 break;
871 }
872
873 if (off)
874 pr_dbg_irq_sf("off ->|%zd\n", off);
875
876 len1 -= off;
877 rb->pread = (rb->pread + off) % rb->size;
878
879 count = len1 / 188;
880 if (count) {
881 pr_dbg_irq_sf("pkt >> 1[%zd<->%zd]\n", rb->pread, rb->pwrite);
882 swfilter_packets(demux, rb->data + rb->pread, count);
883
884 size = count * 188;
885 len1 -= size;
886 rb->pread += size;
887 }
888
889 if (len2 && len1 && ((len1 + len2) > 188)) {
890 pr_dbg_irq_sf("pkt >> 2[%zd<->%zd]\n", rb->pread, rb->pwrite);
891 size = 188 - len1;
892 memcpy(wrapbuf, rb->data + rb->pread, len1);
893 memcpy(wrapbuf + len1, rb->data, size);
894 swfilter_packets(demux, wrapbuf, 1);
895 rb->pread = size;
896 len2 -= size;
897 }
898
899 if (len2) {
900 pr_dbg_irq_sf("pkt >> 3[%zd<->%zd]\n", rb->pread, rb->pwrite);
901 count = len2 / 188;
902 if (count) {
903 swfilter_packets(demux, rb->data + rb->pread, count);
904 rb->pread += count * 188;
905 }
906 }
907 return 0;
908 }
909
smallsection_match_section(struct aml_dmx * dmx,u8 * p,u16 sec_num)910 static void smallsection_match_section(struct aml_dmx *dmx, u8 *p, u16 sec_num)
911 {
912 struct aml_filter *f;
913 int chid, i;
914 int need_crc = 1;
915
916 if (sec_num >= FILTER_COUNT) {
917 pr_dbg("sec_num invalid: %d\n", sec_num);
918 return;
919 }
920
921 f = &dmx->filter[sec_num];
922 chid = f->chan_id;
923
924 dmx->sec_cnt[SEC_CNT_SS]++;
925
926 for (i = 0; i < FILTER_COUNT; i++) {
927 f = &dmx->filter[i];
928 if (f->chan_id != chid)
929 continue;
930 if (sec_filter_match(dmx, f, p)) {
931 if (need_crc) {
932 dmx->sec_cnt_match[SEC_CNT_SS]++;
933 if (!section_crc(dmx, f, p)) {
934 dmx->sec_cnt_crc_fail[SEC_CNT_SS]++;
935 return;
936 }
937 need_crc = 0;
938 }
939 section_notify(dmx, f, p);
940 }
941 }
942
943 }
process_smallsection(struct aml_dmx * dmx)944 static void process_smallsection(struct aml_dmx *dmx)
945 {
946
947 u32 v, wr, rd;
948 u32 data32;
949 struct aml_smallsec *ss = &dmx->smallsec;
950
951 v = DMX_READ_REG(dmx->id, DEMUX_SMALL_SEC_CTL);
952 wr = (v >> 8) & 0xff;
953 rd = (v >> 16) & 0xff;
954
955 if (rd != wr) {
956 int n1 = wr - rd,
957 n2 = 0,
958 max = (ss->bufsize>>8);
959 int i;
960 u8 *p;
961 int sec_len;
962
963 pr_dbg_irq_ss("secbuf[31] ctrl:0x%x\n", v);
964
965 if (n1 < 0) {
966 n1 = max - rd;
967 n2 = wr;
968 }
969 if (n1) {
970 pr_dbg_irq_ss("n1:%d\n", n1);
971 dma_sync_single_for_cpu(dmx_get_dev(dmx),
972 ss->buf_map+(rd<<8),
973 n1<<8,
974 DMA_FROM_DEVICE);
975 for (i = 0; i < n1; i++) {
976 p = (u8 *)ss->buf+((rd+i)<<8);
977 sec_len = (((p[1] & 0xF) << 8) | p[2]) + 3;
978 smallsection_match_section(dmx, p,
979 *(p+sec_len+1));
980 }
981 }
982 if (n2) {
983 pr_dbg_irq_ss("n2:%d\n", n2);
984 dma_sync_single_for_cpu(dmx_get_dev(dmx),
985 ss->buf_map,
986 n2<<8,
987 DMA_FROM_DEVICE);
988 for (i = 0; i < n2; i++) {
989 p = (u8 *)ss->buf+(i<<8);
990 sec_len = (((p[1] & 0xF) << 8) | p[2]) + 3;
991 smallsection_match_section(dmx, p,
992 *(p+sec_len+1));
993 }
994 }
995
996 rd = wr;
997 data32 = (DMX_READ_REG(dmx->id, DEMUX_SMALL_SEC_CTL)
998 & 0xff00ffff)
999 | (rd << 16);
1000 DMX_WRITE_REG(dmx->id, DEMUX_SMALL_SEC_CTL, data32);
1001 }
1002 }
1003
1004
process_section(struct aml_dmx * dmx)1005 static void process_section(struct aml_dmx *dmx)
1006 {
1007 u32 ready, i, sec_busy;
1008 u16 sec_num;
1009
1010 /*pr_dbg("section\n"); */
1011 ready = DMX_READ_REG(dmx->id, SEC_BUFF_READY);
1012 if (ready) {
1013 #ifdef USE_AHB_MODE
1014 /* WRITE_ISA_REG(AHB_BRIDGE_CTRL1,
1015 * READ_ISA_REG (AHB_BRIDGE_CTRL1) | (1 << 31));
1016 */
1017 /* WRITE_ISA_REG(AHB_BRIDGE_CTRL1,
1018 * READ_ISA_REG (AHB_BRIDGE_CTRL1) & (~ (1 << 31)));
1019 */
1020 #endif
1021
1022 if ((ready & (1<<31)) && dmx->smallsec.enable) {
1023 u32 v, wr, rd;
1024
1025 v = DMX_READ_REG(dmx->id, DEMUX_SMALL_SEC_CTL);
1026 wr = (v >> 8) & 0xff;
1027 rd = (v >> 16) & 0xff;
1028 if ((wr < rd) && (5 > (rd - wr)))
1029 pr_error("warning: small ss buf [w%dr%d]\n",
1030 wr, rd);
1031 pr_dbg_irq_ss("ss>%x\n",
1032 DMX_READ_REG(dmx->id, DEMUX_SMALL_SEC_CTL));
1033 process_smallsection(dmx);
1034 /*tasklet_hi_schedule(&dmx->dmx_tasklet);*/
1035 /*tasklet_schedule(&dmx->dmx_tasklet);*/
1036 DMX_WRITE_REG(dmx->id, SEC_BUFF_READY, (1<<31));
1037 return;
1038 }
1039
1040 for (i = 0; i < SEC_BUF_COUNT; i++) {
1041
1042 if (!(ready & (1 << i)))
1043 continue;
1044
1045 /* get section busy */
1046 sec_busy = DMX_READ_REG(dmx->id, SEC_BUFF_BUSY);
1047 /* get filter number */
1048 DMX_WRITE_REG(dmx->id, SEC_BUFF_NUMBER, i);
1049 sec_num = (DMX_READ_REG(dmx->id, SEC_BUFF_NUMBER) >> 8);
1050
1051 /*
1052 * sec_buf_watchdog_count dispatch:
1053 * byte0 -- always busy=0 's watchdog count
1054 * byte1 -- always busy=1 & filter_num=31 's
1055 * watchdog count
1056 */
1057
1058 /* sec_busy is not set, check busy=0 watchdog count */
1059 if (!(sec_busy & (1 << i))) {
1060 /* clear other wd count of this buffer */
1061 dmx->sec_buf_watchdog_count[i] &= 0x000000ff;
1062 dmx->sec_buf_watchdog_count[i] += 0x1;
1063 pr_dbg("bit%d ready=1, busy=0,\n"
1064 "sec_num=%d for %d times\n",
1065 i, sec_num,
1066 dmx->sec_buf_watchdog_count[i]);
1067 if (dmx->sec_buf_watchdog_count[i] >= 5) {
1068 pr_dbg("busy=0 reach the max count,\n"
1069 "try software match.\n");
1070 software_match_section(dmx, i);
1071 dmx->sec_buf_watchdog_count[i] = 0;
1072 DMX_WRITE_REG(dmx->id, SEC_BUFF_READY,
1073 (1 << i));
1074 }
1075 continue;
1076 }
1077
1078 /* filter_num == 31 && busy == 1,check watchdog count */
1079 if (sec_num >= FILTER_COUNT) {
1080 /* clear other wd count of this buffer */
1081 dmx->sec_buf_watchdog_count[i] &= 0x0000ff00;
1082 dmx->sec_buf_watchdog_count[i] += 0x100;
1083 pr_dbg("bit%d ready=1,busy=1,\n"
1084 "sec_num=%d for %d times\n",
1085 i, sec_num,
1086 dmx->sec_buf_watchdog_count[i] >> 8);
1087 if (dmx->sec_buf_watchdog_count[i] >= 0x500) {
1088 pr_dbg("busy=1&filter_num=31\n"
1089 " reach the max count, clear\n"
1090 " the buf ready & busy!\n");
1091 software_match_section(dmx, i);
1092 dmx->sec_buf_watchdog_count[i] = 0;
1093 DMX_WRITE_REG(dmx->id,
1094 SEC_BUFF_READY,
1095 (1 << i));
1096 DMX_WRITE_REG(dmx->id,
1097 SEC_BUFF_BUSY,
1098 (1 << i));
1099 }
1100 continue;
1101 }
1102
1103 /* now, ready & busy are both set and
1104 * filter number is valid
1105 */
1106 if (dmx->sec_buf_watchdog_count[i] != 0)
1107 dmx->sec_buf_watchdog_count[i] = 0;
1108
1109 /* process this section */
1110 hardware_match_section(dmx, sec_num, i);
1111
1112 /* clear the ready & busy bit */
1113 DMX_WRITE_REG(dmx->id, SEC_BUFF_READY, (1 << i));
1114 DMX_WRITE_REG(dmx->id, SEC_BUFF_BUSY, (1 << i));
1115 }
1116 }
1117 }
1118
1119 #ifdef NO_SUB
process_sub(struct aml_dmx * dmx)1120 static void process_sub(struct aml_dmx *dmx)
1121 {
1122
1123 u32 rd_ptr = 0;
1124
1125 u32 wr_ptr = READ_MPEG_REG(PARSER_SUB_WP);
1126 u32 start_ptr = READ_MPEG_REG(PARSER_SUB_START_PTR);
1127 u32 end_ptr = READ_MPEG_REG(PARSER_SUB_END_PTR);
1128
1129 u32 buffer1 = 0, buffer2 = 0;
1130 u8 *buffer1_virt = 0, *buffer2_virt = 0;
1131 u32 len1 = 0, len2 = 0;
1132
1133 if (!dmx->sub_buf_base_virt)
1134 return;
1135
1136 rd_ptr = READ_MPEG_REG(PARSER_SUB_RP);
1137 if (!rd_ptr)
1138 return;
1139 if (rd_ptr > wr_ptr) {
1140 len1 = end_ptr - rd_ptr + 8;
1141 buffer1 = rd_ptr;
1142
1143 len2 = wr_ptr - start_ptr;
1144 buffer2 = start_ptr;
1145
1146 rd_ptr = start_ptr + len2;
1147 } else if (rd_ptr < wr_ptr) {
1148 len1 = wr_ptr - rd_ptr;
1149 buffer1 = rd_ptr;
1150 rd_ptr += len1;
1151 len2 = 0;
1152 } else if (rd_ptr == wr_ptr) {
1153 pr_dbg("sub no data\n");
1154 }
1155
1156 if (buffer1 && len1)
1157 #ifdef SUB_BUF_DMX
1158 buffer1_virt = (void *)dmx->sub_pages + (buffer1 - start_ptr);
1159 #else
1160 buffer1_virt = (void *)dmx->sub_buf_base_virt + (buffer1 - start_ptr);
1161 #endif
1162
1163 if (buffer2 && len2)
1164 #ifdef SUB_BUF_DMX
1165 buffer2_virt = (void *)dmx->sub_pages + (buffer2 - start_ptr);
1166 #else
1167 buffer2_virt = (void *)dmx->sub_buf_base_virt + (buffer2 - start_ptr);
1168 #endif
1169
1170 pr_dbg_irq_sub("sub: rd_ptr:%x buf1:%x len1:%d buf2:%x len2:%d\n",
1171 rd_ptr, buffer1, len1, buffer2, len2);
1172 pr_dbg_irq_sub("sub: buf1_virt:%p buf2_virt:%p\n",
1173 buffer1_virt, buffer2_virt);
1174
1175 if (len1)
1176 dma_sync_single_for_cpu(dmx_get_dev(dmx),
1177 (dma_addr_t) buffer1, len1,
1178 DMA_FROM_DEVICE);
1179 if (len2)
1180 dma_sync_single_for_cpu(dmx_get_dev(dmx),
1181 (dma_addr_t) buffer2, len2,
1182 DMA_FROM_DEVICE);
1183
1184 if (dmx->channel[2].used) {
1185 if (dmx->channel[2].feed && dmx->channel[2].feed->cb.ts &&
1186 ((buffer1_virt != NULL && len1 !=0 ) || (buffer2_virt != NULL && len2 != 0)))
1187 {
1188 dmx->channel[2].feed->cb.ts(buffer1_virt, len1,
1189 buffer2_virt, len2,
1190 &dmx->channel[2].feed->feed.ts);
1191 }
1192 }
1193 WRITE_MPEG_REG(PARSER_SUB_RP, rd_ptr);
1194 }
1195 #endif
1196
process_pes(struct aml_dmx * dmx)1197 static void process_pes(struct aml_dmx *dmx)
1198 {
1199 long off, off_pre = pes_off_pre[dmx->id];
1200 u8 *buffer1 = 0, *buffer2 = 0;
1201 u8 *buffer1_phys = 0, *buffer2_phys = 0;
1202 u32 len1 = 0, len2 = 0;
1203 int i = 1;
1204
1205 off = (DMX_READ_REG(dmx->id, OTHER_WR_PTR) << 3);
1206
1207 pr_dbg_irq_pes("[%d]WR:0x%x PES WR:0x%x\n", dmx->id,
1208 DMX_READ_REG(dmx->id, OTHER_WR_PTR),
1209 DMX_READ_REG(dmx->id, OB_PES_WR_PTR));
1210 buffer1 = (u8 *)(dmx->pes_pages + off_pre);
1211 pr_dbg_irq_pes("[%d]PES WR[%02x %02x %02x %02x %02x %02x %02x %02x",
1212 dmx->id,
1213 buffer1[0], buffer1[1], buffer1[2], buffer1[3],
1214 buffer1[4], buffer1[5], buffer1[6], buffer1[7]);
1215 pr_dbg_irq_pes(" %02x %02x %02x %02x %02x %02x %02x %02x]\n",
1216 buffer1[8], buffer1[9], buffer1[10], buffer1[11],
1217 buffer1[12], buffer1[13], buffer1[14], buffer1[15]);
1218
1219 if (off > off_pre) {
1220 len1 = off-off_pre;
1221 buffer1 = (unsigned char *)(dmx->pes_pages + off_pre);
1222 } else if (off < off_pre) {
1223 len1 = dmx->pes_buf_len-off_pre;
1224 buffer1 = (unsigned char *)(dmx->pes_pages + off_pre);
1225 len2 = off;
1226 buffer2 = (unsigned char *)dmx->pes_pages;
1227 } else if (off == off_pre) {
1228 pr_dbg("pes no data\n");
1229 }
1230 pes_off_pre[dmx->id] = off;
1231 if (len1) {
1232 buffer1_phys = (unsigned char *)virt_to_phys(buffer1);
1233 dma_sync_single_for_cpu(dmx_get_dev(dmx),
1234 (dma_addr_t)buffer1_phys, len1, DMA_FROM_DEVICE);
1235 }
1236 if (len2) {
1237 buffer2_phys = (unsigned char *)virt_to_phys(buffer2);
1238 dma_sync_single_for_cpu(dmx_get_dev(dmx),
1239 (dma_addr_t)buffer2_phys, len2, DMA_FROM_DEVICE);
1240 }
1241 if (len1 || len2) {
1242 struct aml_channel *ch;
1243
1244 for (i = 0; i < CHANNEL_COUNT; i++) {
1245 ch = &dmx->channel[i];
1246 if (ch->used && ch->feed
1247 && (ch->feed->type == DMX_TYPE_TS)) {
1248 if (ch->feed->ts_type & TS_PAYLOAD_ONLY) {
1249 ch->feed->cb.ts(buffer1,
1250 len1, buffer2, len2,
1251 &ch->feed->feed.ts);
1252 }
1253 }
1254 }
1255 }
1256 }
1257
process_om_read(struct aml_dmx * dmx)1258 static void process_om_read(struct aml_dmx *dmx)
1259 {
1260 unsigned int i;
1261 unsigned short om_cmd_status_data_0 = 0;
1262 unsigned short om_cmd_status_data_1 = 0;
1263 /* unsigned short om_cmd_status_data_2 = 0;*/
1264 unsigned short om_cmd_data_out = 0;
1265
1266 om_cmd_status_data_0 = DMX_READ_REG(dmx->id, OM_CMD_STATUS);
1267 om_cmd_status_data_1 = DMX_READ_REG(dmx->id, OM_CMD_DATA);
1268 /* om_cmd_status_data_2 = DMX_READ_REG(dmx->id, OM_CMD_DATA2);*/
1269
1270 if (om_cmd_status_data_0 & 1) {
1271 DMX_WRITE_REG(dmx->id, OM_DATA_RD_ADDR,
1272 (1 << 15) | ((om_cmd_status_data_1 & 0xff) << 2));
1273 for (i = 0; i < (((om_cmd_status_data_1 >> 7) & 0x1fc) >> 1);
1274 i++) {
1275 om_cmd_data_out = DMX_READ_REG(dmx->id, OM_DATA_RD);
1276 }
1277
1278 om_cmd_data_out = DMX_READ_REG(dmx->id, OM_DATA_RD_ADDR);
1279 DMX_WRITE_REG(dmx->id, OM_DATA_RD_ADDR, 0);
1280 DMX_WRITE_REG(dmx->id, OM_CMD_STATUS, 1);
1281 }
1282 }
1283
dmx_irq_bh_handler(unsigned long arg)1284 static void dmx_irq_bh_handler(unsigned long arg)
1285 {
1286 struct aml_dmx *dmx = (struct aml_dmx *)arg;
1287 #if 0
1288 u32 status;
1289
1290 status = DMX_READ_REG(dmx->id, STB_INT_STATUS);
1291
1292 if (status)
1293 DMX_WRITE_REG(dmx->id, STB_INT_STATUS, status);
1294 #endif
1295 process_smallsection(dmx);
1296 }
1297
dmx_irq_handler(int irq_number,void * para)1298 static irqreturn_t dmx_irq_handler(int irq_number, void *para)
1299 {
1300 struct aml_dmx *dmx = (struct aml_dmx *)para;
1301 struct aml_dvb *dvb = aml_get_dvb_device();
1302 u32 status;
1303 unsigned long flags;
1304
1305 spin_lock_irqsave(&dvb->slock, flags);
1306 status = DMX_READ_REG(dmx->id, STB_INT_STATUS);
1307 if (!status)
1308 goto irq_handled;
1309
1310 pr_dbg_irq("demux %d irq status: 0x%08x\n", dmx->id, status);
1311
1312 if (status & (1 << SECTION_BUFFER_READY))
1313 process_section(dmx);
1314 #ifdef NO_SUB
1315 if (status & (1 << SUB_PES_READY)) {
1316 /*If the subtitle is set by tsdemux,
1317 *do not parser in demux driver.
1318 */
1319 if (dmx->sub_chan == -1)
1320 process_sub(dmx);
1321 }
1322 #endif
1323 if (status & (1 << OTHER_PES_READY))
1324 process_pes(dmx);
1325 if (status & (1 << OM_CMD_READ_PENDING))
1326 process_om_read(dmx);
1327 /*
1328 *if (status & (1 << DUPLICATED_PACKET)) {
1329 *}
1330 *if (status & (1 << DIS_CONTINUITY_PACKET)) {
1331 *}
1332 *if (status & (1 << VIDEO_SPLICING_POINT)) {
1333 *}
1334 *if (status & (1 << AUDIO_SPLICING_POINT)) {
1335 *}
1336 */
1337 if (status & (1 << TS_ERROR_PIN))
1338 pr_error("TS_ERROR_PIN\n");
1339
1340 if (status & (1 << NEW_PDTS_READY)) {
1341 u32 pdts_status = DMX_READ_REG(dmx->id, STB_PTS_DTS_STATUS);
1342
1343 if (pdts_status & (1 << VIDEO_PTS_READY)) {
1344 video_pts = DMX_READ_REG(dmx->id, VIDEO_PTS_DEMUX);
1345 video_pts_bit32 =
1346 (pdts_status & (1 << VIDEO_PTS_BIT32)) ? 1 : 0;
1347 if (!first_video_pts
1348 || 0 > (int)(video_pts - first_video_pts))
1349 first_video_pts = video_pts;
1350 }
1351
1352 if (pdts_status & (1 << AUDIO_PTS_READY)) {
1353 audio_pts = DMX_READ_REG(dmx->id, AUDIO_PTS_DEMUX);
1354 audio_pts_bit32 =
1355 (pdts_status & (1 << AUDIO_PTS_BIT32)) ? 1 : 0;
1356 if (!first_audio_pts
1357 || 0 > (int)(audio_pts - first_audio_pts))
1358 first_audio_pts = audio_pts;
1359 }
1360 }
1361
1362 if (dmx->irq_handler)
1363 dmx->irq_handler(dmx->dmx_irq, (void *)(long)dmx->id);
1364
1365 DMX_WRITE_REG(dmx->id, STB_INT_STATUS, status);
1366
1367 /*tasklet_schedule(&dmx->dmx_tasklet);*/
1368
1369 {
1370 if (!dmx->int_check_time) {
1371 dmx->int_check_time = jiffies;
1372 dmx->int_check_count = 0;
1373 }
1374
1375 if (jiffies_to_msecs(jiffies - dmx->int_check_time) >= 100
1376 || dmx->int_check_count > 1000) {
1377 if (dmx->int_check_count > 1000) {
1378 struct aml_dvb *dvb =
1379 (struct aml_dvb *)dmx->demux.priv;
1380 pr_error("Too many irq (%d irq in %d ms)!\n",
1381 dmx->int_check_count,
1382 jiffies_to_msecs(jiffies -
1383 dmx->int_check_time));
1384 if (dmx->fe && !dmx->in_tune)
1385 DMX_WRITE_REG(dmx->id, STB_INT_MASK, 0);
1386 dmx_reset_hw_ex(dvb, 0);
1387 }
1388 dmx->int_check_time = 0;
1389 }
1390
1391 dmx->int_check_count++;
1392
1393 if (dmx->in_tune) {
1394 dmx->error_check++;
1395 if (dmx->error_check > 200)
1396 DMX_WRITE_REG(dmx->id, STB_INT_MASK, 0);
1397 }
1398 }
1399
1400 irq_handled:
1401 spin_unlock_irqrestore(&dvb->slock, flags);
1402 return IRQ_HANDLED;
1403 }
1404
dmx_get_order(unsigned long size)1405 static inline int dmx_get_order(unsigned long size)
1406 {
1407 int order;
1408
1409 order = -1;
1410 do {
1411 size >>= 1;
1412 order++;
1413 } while (size);
1414
1415 return order;
1416 }
1417
dmx_get_afifo_size(struct aml_asyncfifo * afifo)1418 static inline int dmx_get_afifo_size(struct aml_asyncfifo *afifo)
1419 {
1420 return afifo->secure_enable && afifo->blk.len ? afifo->blk.len : asyncfifo_buf_len;
1421 }
1422
dvr_process_channel(struct aml_asyncfifo * afifo,struct aml_channel * channel,u32 total,u32 size,struct aml_swfilter * sf)1423 static void dvr_process_channel(struct aml_asyncfifo *afifo,
1424 struct aml_channel *channel,
1425 u32 total, u32 size,
1426 struct aml_swfilter *sf)
1427 {
1428 int cnt;
1429 int ret = 0;
1430 struct aml_dvr_block blk;
1431
1432 if (afifo->buf_read > afifo->buf_toggle) {
1433 cnt = total - afifo->buf_read;
1434 if (!(afifo->secure_enable && afifo->blk.addr)) {
1435 dma_sync_single_for_cpu(asyncfifo_get_dev(afifo),
1436 afifo->pages_map+afifo->buf_read*size,
1437 cnt*size,
1438 DMA_FROM_DEVICE);
1439 if (sf)
1440 ret = _rbuf_write(&sf->rbuf,
1441 (u8 *)afifo->pages+afifo->buf_read*size,
1442 cnt*size);
1443 else
1444 channel->dvr_feed->cb.ts(
1445 (u8 *)afifo->pages+afifo->buf_read*size,
1446 cnt*size, NULL, 0,
1447 &channel->dvr_feed->feed.ts);
1448 } else {
1449 blk.addr = afifo->blk.addr+afifo->buf_read*size;
1450 blk.len = cnt*size;
1451 if (sf)
1452 ret = _rbuf_write(&sf->rbuf,
1453 (u8 *)afifo->pages+afifo->buf_read*size,
1454 cnt*size);
1455 else {
1456 channel->dvr_feed->cb.ts(
1457 (u8 *)&blk,
1458 sizeof(struct aml_dvr_block),
1459 NULL, 0,
1460 &channel->dvr_feed->feed.ts);
1461 }
1462 }
1463 afifo->buf_read = 0;
1464 }
1465
1466 if (afifo->buf_toggle > afifo->buf_read) {
1467 cnt = afifo->buf_toggle - afifo->buf_read;
1468 if (!(afifo->secure_enable && afifo->blk.addr)) {
1469 dma_sync_single_for_cpu(asyncfifo_get_dev(afifo),
1470 afifo->pages_map+afifo->buf_read*size,
1471 cnt*size,
1472 DMA_FROM_DEVICE);
1473 if (sf) {
1474 if (ret >= 0)
1475 ret = _rbuf_write(&sf->rbuf,
1476 (u8 *)afifo->pages+afifo->buf_read*size,
1477 cnt*size);
1478 } else {
1479 channel->dvr_feed->cb.ts(
1480 (u8 *)afifo->pages+afifo->buf_read*size,
1481 cnt*size, NULL, 0,
1482 &channel->dvr_feed->feed.ts);
1483 }
1484 } else {
1485 blk.addr = afifo->blk.addr+afifo->buf_read*size;
1486 blk.len = cnt*size;
1487 if (sf)
1488 ret = _rbuf_write(&sf->rbuf,
1489 (u8 *)afifo->pages+afifo->buf_read*size,
1490 cnt*size);
1491 else {
1492 channel->dvr_feed->cb.ts(
1493 (u8 *)&blk,
1494 sizeof(struct aml_dvr_block),
1495 NULL, 0,
1496 &channel->dvr_feed->feed.ts);
1497 }
1498 }
1499 afifo->buf_read = afifo->buf_toggle;
1500 }
1501
1502 if (sf && ret > 0) {
1503 _rbuf_filter_pkts(&sf->rbuf, sf->wrapbuf,
1504 dvb_dmx_swfilter_packets,
1505 channel->dvr_feed->demux);
1506 } else if (sf && ret <= 0)
1507 pr_error("sf rbuf write error[%d]\n", ret);
1508 else
1509 pr_dbg_irq_dvr("write data to dvr\n");
1510 }
1511
1512 static uint32_t last_afifo_time = 0;
dvr_irq_bh_handler(unsigned long arg)1513 static void dvr_irq_bh_handler(unsigned long arg)
1514 {
1515 struct aml_asyncfifo *afifo = (struct aml_asyncfifo *)arg;
1516 struct aml_dvb *dvb = afifo->dvb;
1517 struct aml_dmx *dmx;
1518 u32 size, total;
1519 int i, factor;
1520 unsigned long flags;
1521
1522 pr_dbg_irq_dvr("async fifo %d irq, interval:%d ms, %d data\n", afifo->id,
1523 jiffies_to_msecs(jiffies - last_afifo_time), afifo->flush_size);
1524
1525 spin_lock_irqsave(&dvb->slock, flags);
1526
1527 if (dvb && afifo->source >= AM_DMX_0 && afifo->source < AM_DMX_MAX) {
1528 dmx = &dvb->dmx[afifo->source];
1529 // pr_inf("async fifo %d irq, source:%d\n", afifo->id,afifo->source);
1530 if (dmx->init && dmx->record) {
1531 struct aml_swfilter *sf = &dvb->swfilter;
1532 int issf = 0;
1533
1534 total = afifo->buf_len / afifo->flush_size;
1535 factor = dmx_get_order(total);
1536 size = afifo->buf_len >> factor;
1537
1538 if (sf->user && (sf->afifo == afifo))
1539 issf = 1;
1540
1541 for (i = 0; i < CHANNEL_COUNT; i++) {
1542 if (dmx->channel[i].used
1543 && dmx->channel[i].dvr_feed) {
1544 dvr_process_channel(afifo,
1545 &dmx->channel[i],
1546 total,
1547 size,
1548 issf?sf:NULL);
1549 break;
1550 }
1551 }
1552
1553 }
1554 }
1555 spin_unlock_irqrestore(&dvb->slock, flags);
1556 last_afifo_time = jiffies;
1557 }
1558
dvr_irq_handler(int irq_number,void * para)1559 static irqreturn_t dvr_irq_handler(int irq_number, void *para)
1560 {
1561 struct aml_asyncfifo *afifo = (struct aml_asyncfifo *)para;
1562 int factor = dmx_get_order(afifo->buf_len / afifo->flush_size);
1563
1564 afifo->buf_toggle++;
1565 afifo->buf_toggle %= (1 << factor);
1566 tasklet_schedule(&afifo->asyncfifo_tasklet);
1567 return IRQ_HANDLED;
1568 }
1569
1570 /*Enable the STB*/
stb_enable(struct aml_dvb * dvb)1571 static void stb_enable(struct aml_dvb *dvb)
1572 {
1573 int out_src, des_in, en_des, fec_clk, hiu, dec_clk_en;
1574 int src, tso_src, i;
1575 u32 fec_s0, fec_s1,fec_s2;
1576 u32 invert0, invert1, invert2;
1577 u32 data;
1578
1579 switch (dvb->stb_source) {
1580 case AM_TS_SRC_DMX0:
1581 src = dvb->dmx[0].source;
1582 break;
1583 case AM_TS_SRC_DMX1:
1584 src = dvb->dmx[1].source;
1585 break;
1586 case AM_TS_SRC_DMX2:
1587 src = dvb->dmx[2].source;
1588 break;
1589 default:
1590 src = dvb->stb_source;
1591 break;
1592 }
1593
1594 switch (src) {
1595 case AM_TS_SRC_TS0:
1596 fec_clk = tsfile_clkdiv;
1597 hiu = 0;
1598 break;
1599 case AM_TS_SRC_TS1:
1600 fec_clk = tsfile_clkdiv;
1601 hiu = 0;
1602 break;
1603 case AM_TS_SRC_TS2:
1604 fec_clk = tsfile_clkdiv;
1605 hiu = 0;
1606 break;
1607 case AM_TS_SRC_TS3:
1608 fec_clk = tsfile_clkdiv;
1609 hiu = 0;
1610 break;
1611 case AM_TS_SRC_S_TS0:
1612 fec_clk = tsfile_clkdiv;
1613 hiu = 0;
1614 break;
1615 case AM_TS_SRC_S_TS1:
1616 fec_clk = tsfile_clkdiv;
1617 hiu = 0;
1618 break;
1619 case AM_TS_SRC_S_TS2:
1620 fec_clk = tsfile_clkdiv;
1621 hiu = 0;
1622 break;
1623 case AM_TS_SRC_HIU:
1624 fec_clk = tsfile_clkdiv;
1625 hiu = 1;
1626 break;
1627 case AM_TS_SRC_HIU1:
1628 fec_clk = tsfile_clkdiv;
1629 hiu = 1;
1630 break;
1631 default:
1632 fec_clk = 0;
1633 hiu = 0;
1634 break;
1635 }
1636
1637 switch (dvb->dsc[0].source) {
1638 case AM_TS_SRC_DMX0:
1639 des_in = 0;
1640 en_des = 1;
1641 dec_clk_en = 1;
1642 break;
1643 case AM_TS_SRC_DMX1:
1644 des_in = 1;
1645 en_des = 1;
1646 dec_clk_en = 1;
1647 break;
1648 case AM_TS_SRC_DMX2:
1649 des_in = 2;
1650 en_des = 1;
1651 dec_clk_en = 1;
1652 break;
1653 default:
1654 des_in = 0;
1655 en_des = 0;
1656 dec_clk_en = 0;
1657 break;
1658 }
1659 switch (dvb->tso_source) {
1660 case AM_TS_SRC_DMX0:
1661 tso_src = dvb->dmx[0].source;
1662 break;
1663 case AM_TS_SRC_DMX1:
1664 tso_src = dvb->dmx[1].source;
1665 break;
1666 case AM_TS_SRC_DMX2:
1667 tso_src = dvb->dmx[2].source;
1668 break;
1669 default:
1670 tso_src = dvb->tso_source;
1671 break;
1672 }
1673
1674 switch (tso_src) {
1675 case AM_TS_SRC_TS0:
1676 out_src = 0;
1677 break;
1678 case AM_TS_SRC_TS1:
1679 out_src = 1;
1680 break;
1681 case AM_TS_SRC_TS2:
1682 out_src = 2;
1683 break;
1684 case AM_TS_SRC_TS3:
1685 out_src = 3;
1686 break;
1687 case AM_TS_SRC_S_TS0:
1688 out_src = 6;
1689 break;
1690 case AM_TS_SRC_S_TS1:
1691 out_src = 5;
1692 break;
1693 case AM_TS_SRC_S_TS2:
1694 out_src = 4;
1695 break;
1696 case AM_TS_SRC_HIU:
1697 out_src = 7;
1698 break;
1699 default:
1700 out_src = 0;
1701 break;
1702 }
1703
1704 pr_dbg("[stb]src: %d, dsc1in: %d, tso: %d\n", src, des_in, out_src);
1705
1706 fec_s0 = 0;
1707 fec_s1 = 0;
1708 fec_s2 = 0;
1709 invert0 = 0;
1710 invert1 = 0;
1711 invert2 = 0;
1712
1713 for (i = 0; i < dvb->ts_in_total_count; i++) {
1714 if (dvb->ts[i].s2p_id == 0)
1715 fec_s0 = i;
1716 else if (dvb->ts[i].s2p_id == 1)
1717 fec_s1 = i;
1718 else if (dvb->ts[i].s2p_id == 2)
1719 fec_s2 = i;
1720 }
1721
1722 invert0 = dvb->s2p[0].invert;
1723 invert1 = dvb->s2p[1].invert;
1724
1725 WRITE_MPEG_REG(STB_TOP_CONFIG,
1726 (invert1 << INVERT_S2P1_FEC_CLK) |
1727 (fec_s1 << S2P1_FEC_SERIAL_SEL) |
1728 (out_src << TS_OUTPUT_SOURCE) |
1729 (des_in << DES_INPUT_SEL) |
1730 (en_des << ENABLE_DES_PL) |
1731 (dec_clk_en << ENABLE_DES_PL_CLK) |
1732 (invert0 << INVERT_S2P0_FEC_CLK) |
1733 (fec_s0 << S2P0_FEC_SERIAL_SEL)|
1734 (ciplus));
1735 ciplus = 0;
1736
1737 if (get_cpu_type() >= MESON_CPU_MAJOR_ID_TL1) {
1738 invert2 = dvb->s2p[2].invert;
1739
1740 WRITE_MPEG_REG(STB_S2P2_CONFIG,
1741 (invert2 << INVERT_S2P2_FEC_CLK) |
1742 (fec_s2 << S2P2_FEC_SERIAL_SEL));
1743 }
1744
1745 if (dvb->reset_flag)
1746 hiu = 0;
1747 /* invert ts out clk,add ci model need add this*/
1748 if (dvb->ts_out_invert) {
1749 printk("ts out invert ---\r\n");
1750 data = READ_MPEG_REG(TS_TOP_CONFIG);
1751 data |= 1 << TS_OUT_CLK_INVERT;
1752 WRITE_MPEG_REG(TS_TOP_CONFIG, data);
1753 }
1754
1755 if (src == AM_TS_SRC_HIU1) {
1756 WRITE_MPEG_REG(TS_HIU1_CONFIG,
1757 (demux_skipbyte << FILE_M2TS_SKIP_BYTES_HIU1) |
1758 (hiu << TS_HIU_ENABLE_HIU1) |
1759 (fec_clk << FEC_CLK_DIV_HIU1) |
1760 (0xBB << TS_PACKAGE_LENGTH_SUB_1_HIU1) |
1761 (0x47 << FEC_SYNC_BYTE_HIU1));
1762 } else {
1763 /* invert ts out clk end */
1764 WRITE_MPEG_REG(TS_FILE_CONFIG,
1765 (demux_skipbyte << 16) |
1766 (6 << DES_OUT_DLY) |
1767 (3 << TRANSPORT_SCRAMBLING_CONTROL_ODD) |
1768 (3 << TRANSPORT_SCRAMBLING_CONTROL_ODD_2) |
1769 (hiu << TS_HIU_ENABLE) | (fec_clk << FEC_FILE_CLK_DIV));
1770 }
1771 }
1772
dsc_set_pid(struct aml_dsc_channel * ch,int pid)1773 int dsc_set_pid(struct aml_dsc_channel *ch, int pid)
1774 {
1775 struct aml_dsc *dsc = ch->dsc;
1776 int is_dsc2 = (dsc->id == 1) ? 1 : 0;
1777 u32 data;
1778
1779 WRITE_MPEG_REG(TS_PL_PID_INDEX,
1780 ((ch->id & 0x0f) >> 1)+(is_dsc2 ? 4 : 0));
1781 data = READ_MPEG_REG(TS_PL_PID_DATA);
1782 if (ch->id & 1) {
1783 data &= 0xFFFF0000;
1784 data |= pid & 0x1fff;
1785 if (!ch->used)
1786 data |= 1 << PID_MATCH_DISABLE_LOW;
1787 } else {
1788 data &= 0xFFFF;
1789 data |= (pid & 0x1fff) << 16;
1790 if (!ch->used)
1791 data |= 1 << PID_MATCH_DISABLE_HIGH;
1792 }
1793 WRITE_MPEG_REG(TS_PL_PID_INDEX,
1794 ((ch->id & 0x0f) >> 1)+(is_dsc2 ? 4 : 0));
1795 WRITE_MPEG_REG(TS_PL_PID_DATA, data);
1796 WRITE_MPEG_REG(TS_PL_PID_INDEX, 0);
1797
1798 if (ch->used)
1799 pr_dbg("set DSC %d ch %d PID %d\n", dsc->id, ch->id, pid);
1800 else
1801 pr_dbg("disable DSC %d ch %d\n", dsc->id, ch->id);
1802 return 0;
1803 }
1804
dsc_get_pid(struct aml_dsc_channel * ch,int * pid)1805 int dsc_get_pid(struct aml_dsc_channel *ch, int *pid)
1806 {
1807 struct aml_dsc *dsc = ch->dsc;
1808 int is_dsc2 = (dsc->id == 1) ? 1 : 0;
1809 u32 data;
1810
1811 WRITE_MPEG_REG(TS_PL_PID_INDEX,
1812 ((ch->id & 0x0f) >> 1)+(is_dsc2 ? 4 : 0));
1813 data = READ_MPEG_REG(TS_PL_PID_DATA);
1814 if (ch->id & 1) {
1815 *pid = data & 0x1fff;
1816 } else {
1817 *pid = (data >> 16) & 0x1fff;
1818 }
1819
1820 /*pr_dbg("%s,get DSC %d ch %d PID %d\n", __FUNCTION__,dsc->id, ch->id, *pid);*/
1821 return 0;
1822 }
1823
dsc_set_key(struct aml_dsc_channel * ch,int flags,enum ca_cw_type type,u8 * key)1824 int dsc_set_key(struct aml_dsc_channel *ch, int flags, enum ca_cw_type type,
1825 u8 *key)
1826 {
1827 /*struct aml_dsc *dsc = ch->dsc;*/
1828 int ret = -1;
1829
1830 switch (type) {
1831 case CA_CW_DVB_CSA_EVEN:
1832 case CA_CW_DVB_CSA_ODD:
1833 aml_ci_plus_disable();
1834 ret = dsc_set_csa_key(ch, flags, type, key);
1835 if (ret != 0)
1836 goto END;
1837 /* Different with old mode, do change */
1838 if (ch->work_mode == CIPLUS_MODE || ch->work_mode == -1) {
1839 if (ch->work_mode == -1)
1840 pr_inf("dsc[%d:%d] enable\n",
1841 ch->dsc->id, ch->id);
1842 else
1843 pr_inf("dsc[%d:%d] enable (from ciplus)\n",
1844 ch->dsc->id, ch->id);
1845 ch->mode = ECB_MODE;
1846 ch->work_mode = DVBCSA_MODE;
1847 }
1848 break;
1849 case CA_CW_AES_EVEN:
1850 case CA_CW_AES_ODD:
1851 case CA_CW_AES_EVEN_IV:
1852 case CA_CW_AES_ODD_IV:
1853 case CA_CW_DES_EVEN:
1854 case CA_CW_DES_ODD:
1855 case CA_CW_SM4_EVEN:
1856 case CA_CW_SM4_ODD:
1857 case CA_CW_SM4_EVEN_IV:
1858 case CA_CW_SM4_ODD_IV:
1859 am_ci_plus_set_output(ch);
1860 ret = dsc_set_aes_des_sm4_key(ch, flags, type, key);
1861 if (ret != 0)
1862 goto END;
1863 /* Different with old mode, do change */
1864 if (ch->work_mode == DVBCSA_MODE || ch->work_mode == -1) {
1865 if (ch->work_mode == -1)
1866 pr_inf("dsc[%d:%d] ciplus enable\n",
1867 ch->dsc->id, ch->id);
1868 else
1869 pr_inf("dsc[%d:%d] ciplus enable (from dsc)\n",
1870 ch->dsc->id, ch->id);
1871 ch->work_mode = CIPLUS_MODE;
1872 }
1873 break;
1874 default:
1875 break;
1876 }
1877 END:
1878 return ret;
1879 }
1880
dsc_set_keys(struct aml_dsc_channel * ch)1881 int dsc_set_keys(struct aml_dsc_channel *ch)
1882 {
1883 int types = ch->set & 0xFFFFFF;
1884 int flag = (ch->set >> 24) & 0xFF;
1885 int i;
1886 u8 *k;
1887 int ret = 0;
1888
1889 for (i = 0; i < CA_CW_TYPE_MAX; i++) {
1890 if (types & (1 << i)) {
1891 k = NULL;
1892 switch (i) {
1893 case CA_CW_DVB_CSA_EVEN:
1894 case CA_CW_AES_EVEN:
1895 case CA_CW_DES_EVEN:
1896 case CA_CW_SM4_EVEN:
1897 k = ch->even;
1898 break;
1899 case CA_CW_DVB_CSA_ODD:
1900 case CA_CW_AES_ODD:
1901 case CA_CW_DES_ODD:
1902 case CA_CW_SM4_ODD:
1903 k = ch->odd;
1904 break;
1905 case CA_CW_AES_EVEN_IV:
1906 case CA_CW_SM4_EVEN_IV:
1907 k = ch->even_iv;
1908 break;
1909 case CA_CW_AES_ODD_IV:
1910 case CA_CW_SM4_ODD_IV:
1911 k = ch->odd_iv;
1912 break;
1913 default:
1914 break;
1915 }
1916 /*
1917 if (k)
1918 pr_inf("dsc ch:%d flag:%d type:%d\n", ch->id, flag, i);
1919 */
1920 if (k)
1921 ret = dsc_set_key(ch, flag,
1922 i,
1923 k);
1924 }
1925 }
1926 return 0;
1927 }
1928
dsc_set_csa_key(struct aml_dsc_channel * ch,int flags,enum ca_cw_type type,u8 * key)1929 static int dsc_set_csa_key(struct aml_dsc_channel *ch, int flags,
1930 enum ca_cw_type type, u8 *key)
1931 {
1932 struct aml_dsc *dsc = ch->dsc;
1933 int is_dsc2 = (dsc->id == 1) ? 1 : 0;
1934 u16 k0, k1, k2, k3;
1935 u32 key0, key1;
1936 int reg;
1937
1938 if (flags & DSC_FROM_KL) {
1939 k0 = k1 = k2 = k3 = 0;
1940 /*dummy write to check if kl not working*/
1941 key0 = key1 = 0;
1942 WRITE_MPEG_REG(COMM_DESC_KEY0, key0);
1943 WRITE_MPEG_REG(COMM_DESC_KEY1, key1);
1944
1945 /*tdes? :*/
1946 if (get_cpu_type() == MESON_CPU_MAJOR_ID_GXBB) {
1947 WRITE_MPEG_REG(COMM_DESC_KEY_RW,
1948 /* (type ? (1 << 6) : (1 << 5)) | */
1949 ((1 << 5)) |
1950 ((ch->id + type * DSC_COUNT)+
1951 (is_dsc2 ? 16 : 0)));
1952 }
1953 if (get_cpu_type() == MESON_CPU_MAJOR_ID_GXL ||
1954 get_cpu_type() == MESON_CPU_MAJOR_ID_GXM) {
1955 pr_info("do kl..\n");
1956 WRITE_MPEG_REG(COMM_DESC_KEY_RW,
1957 (type ? (1 << 6) : (1 << 5)) | (1<<7) |
1958 ((ch->id + type * DSC_COUNT)+
1959 (is_dsc2 ? 16 : 0)));
1960 }
1961 reg = (type ? (1 << 6) : (1 << 5)) |
1962 ((ch->id + type * DSC_COUNT)+
1963 (is_dsc2 ? 16 : 0));
1964 } else {
1965 k0 = (key[0] << 8) | key[1];
1966 k1 = (key[2] << 8) | key[3];
1967 k2 = (key[4] << 8) | key[5];
1968 k3 = (key[6] << 8) | key[7];
1969
1970 key0 = (k0 << 16) | k1;
1971 key1 = (k2 << 16) | k3;
1972 WRITE_MPEG_REG(COMM_DESC_KEY0, key0);
1973 WRITE_MPEG_REG(COMM_DESC_KEY1, key1);
1974
1975 reg = (ch->id + type * DSC_COUNT)+(is_dsc2 ? 16 : 0);
1976 WRITE_MPEG_REG(COMM_DESC_KEY_RW, reg);
1977 }
1978
1979 return 0;
1980 }
1981
1982 /************************* AES DESC************************************/
1983 /*#define STB_TOP_CONFIG 0x16f0
1984 #define CIPLUS_KEY0 0x16f8
1985 #define CIPLUS_KEY1 0x16f9
1986 #define CIPLUS_KEY2 0x16fa
1987 #define CIPLUS_KEY3 0x16fb
1988 #define CIPLUS_KEY_WR 0x16fc
1989 #define CIPLUS_CONFIG 0x16fd
1990 #define CIPLUS_ENDIAN 0x16fe*/
1991
1992 #define ENABLE_DEC_PL 7
1993 #define ENABLE_DES_PL_CLK 15
1994
1995 #define KEY_WR_AES_IV_B 5
1996 #define KEY_WR_AES_IV_A 4
1997 #define KEY_WR_AES_B 3
1998 #define KEY_WR_AES_A 2
1999 #define KEY_WR_DES_B 1
2000 #define KEY_WR_DES_A 0
2001
2002 #define IDSA_MODE_BIT 31
2003 #define SM4_MODE 30
2004 #define CNTL_ENABLE 3
2005 #define AES_CBC_DISABLE 2
2006 #define AES_EN 1
2007 #define DES_EN 0
2008
2009 #define AES_MSG_OUT_ENDIAN 24
2010 #define AES_MSG_IN_ENDIAN 20
2011 #define AES_KEY_ENDIAN 16
2012 #define DES_MSG_OUT_ENDIAN 8
2013 #define DES_MSG_IN_ENDIAN 4
2014 #define DES_KEY_ENDIAN 0
2015
2016 #define ALGO_AES 0
2017 #define ALGO_SM4 1
2018 #define ALGO_DES 2
2019
2020 #if 0
2021 static void aml_ci_plus_set_stb(void)
2022 {
2023 unsigned int data;
2024 /* data = READ_MPEG_REG(FEC_INPUT_CONTROL); */
2025 /* data |= (0<<FEC_SEL); */
2026 /* data |= (1<<FEC_CORE_SEL); */
2027 /* data |= (1<<FEC_INPUT_FEC_CLK);
2028 * local playback will not work if set this
2029 */
2030 /* WRITE_MPEG_REG(FEC_INPUT_CONTROL, data); */
2031
2032 data = READ_MPEG_REG(STB_TOP_CONFIG);
2033 WRITE_MPEG_REG(STB_TOP_CONFIG, data |
2034 (0 << CIPLUS_IN_SEL) | (0 << CIPLUS_OUT_SEL));
2035 data = READ_MPEG_REG(STB_TOP_CONFIG);
2036 /* data |= (1<<ENABLE_DEC_PL); bit 7 --
2037 * enable_des_pl, this step was set in dsc_enable
2038 */
2039 /*bit 15 -- enable_des_pl_clk*/
2040 /* data |= (1<<ENABLE_DES_PL_CLK); */
2041 data |= (1<<CIPLUS_OUT_SEL);/*bit 28 -- ciplus_out_sel from ciplus*/
2042 WRITE_MPEG_REG(STB_TOP_CONFIG, data);
2043 data = READ_MPEG_REG(STB_TOP_CONFIG);
2044 }
2045 #endif
2046
2047 /*
2048 * param:
2049 * key:
2050 * 16bytes IV key
2051 * type:
2052 * AM_DSC_KEY_TYPE_AES_ODD IV odd key
2053 * AM_DSC_KEY_TYPE_AES_EVEN IV even key
2054 */
aml_ci_plus_set_iv(struct aml_dsc_channel * ch,enum ca_cw_type type,u8 * key)2055 void aml_ci_plus_set_iv(struct aml_dsc_channel *ch, enum ca_cw_type type,
2056 u8 *key)
2057 {
2058 unsigned int k0, k1, k2, k3;
2059
2060 k3 = (key[0] << 24) | (key[1] << 16) | (key[2] << 8) | key[3];
2061 k2 = (key[4] << 24) | (key[5] << 16) | (key[6] << 8) | key[7];
2062 k1 = (key[8] << 24) | (key[9] << 16) | (key[10] << 8) | key[11];
2063 k0 = (key[12] << 24) | (key[13] << 16) | (key[14] << 8) | key[15];
2064
2065 if (type == CA_CW_AES_EVEN_IV ||
2066 type == CA_CW_SM4_EVEN_IV) {
2067 WRITE_MPEG_REG(CIPLUS_KEY0, k0);
2068 WRITE_MPEG_REG(CIPLUS_KEY1, k1);
2069 WRITE_MPEG_REG(CIPLUS_KEY2, k2);
2070 WRITE_MPEG_REG(CIPLUS_KEY3, k3);
2071 WRITE_MPEG_REG(CIPLUS_KEY_WR,
2072 (ch->id << 9) | (1<<KEY_WR_AES_IV_A));
2073 } else if (type == CA_CW_AES_ODD_IV ||
2074 type == CA_CW_SM4_ODD_IV) {
2075 WRITE_MPEG_REG(CIPLUS_KEY0, k0);
2076 WRITE_MPEG_REG(CIPLUS_KEY1, k1);
2077 WRITE_MPEG_REG(CIPLUS_KEY2, k2);
2078 WRITE_MPEG_REG(CIPLUS_KEY3, k3);
2079 WRITE_MPEG_REG(CIPLUS_KEY_WR,
2080 (ch->id << 9) | (1<<KEY_WR_AES_IV_B));
2081 }
2082 }
2083
2084 /*
2085 * Param:
2086 * key_endian
2087 * S905D 7 for kl 0 for set key directly
2088 * mode
2089 * 0 for ebc
2090 * 1 for cbc
2091 */
aml_ci_plus_config(int key_endian,int mode,int algo)2092 static void aml_ci_plus_config(int key_endian, int mode, int algo)
2093 {
2094 unsigned int data;
2095 unsigned int idsa_mode = 0;
2096 unsigned int sm4_mode = 0;
2097 unsigned int cbc_disable = 0;
2098 unsigned int des_enable = 0;
2099 unsigned int aes_enable = 1;
2100
2101 pr_dbg("%s mode:%d,alog:%d\n",__FUNCTION__,mode,algo);
2102
2103 if (get_cpu_type() < MESON_CPU_MAJOR_ID_SM1) {
2104 WRITE_MPEG_REG(CIPLUS_ENDIAN,
2105 (15 << AES_MSG_OUT_ENDIAN)
2106 | (15 << AES_MSG_IN_ENDIAN)
2107 | (key_endian << AES_KEY_ENDIAN)
2108 |
2109 (15 << DES_MSG_OUT_ENDIAN)
2110 | (15 << DES_MSG_IN_ENDIAN)
2111 | (key_endian << DES_KEY_ENDIAN)
2112 );
2113 } else {
2114 WRITE_MPEG_REG(CIPLUS_ENDIAN, 0);
2115 }
2116
2117 data = READ_MPEG_REG(CIPLUS_ENDIAN);
2118
2119 if (algo == ALGO_SM4) {
2120 sm4_mode = 1;
2121 } else if (algo == ALGO_AES){
2122 sm4_mode = 0;
2123 } else {
2124 sm4_mode = 0;
2125 des_enable = 1;
2126 }
2127
2128 if (mode == IDSA_MODE) {
2129 idsa_mode = 1;
2130 cbc_disable = 0;
2131 } else if (mode == CBC_MODE) {
2132 cbc_disable = 0;
2133 } else {
2134 cbc_disable = 1;
2135 }
2136 pr_dbg("idsa_mode:%d sm4_mode:%d cbc_disable:%d aes_enable:%d des_enable:%d\n", \
2137 idsa_mode,sm4_mode,cbc_disable,aes_enable,des_enable);
2138
2139 data = (idsa_mode << IDSA_MODE_BIT) |
2140 (sm4_mode << SM4_MODE ) |
2141 (cbc_disable << AES_CBC_DISABLE) |
2142 /*1 << AES_CBC_DISABLE : ECB
2143 *0 << AES_CBC_DISABLE : CBC
2144 */
2145 (1 << CNTL_ENABLE) |
2146 (aes_enable << AES_EN) |
2147 (des_enable << DES_EN);
2148
2149 WRITE_MPEG_REG(CIPLUS_CONFIG, data);
2150 data = READ_MPEG_REG(CIPLUS_CONFIG);
2151 pr_dbg("CIPLUS_CONFIG is 0x%x\n",data);
2152 }
2153
2154 /*
2155 * Set output to demux set.
2156 */
am_ci_plus_set_output(struct aml_dsc_channel * ch)2157 static void am_ci_plus_set_output(struct aml_dsc_channel *ch)
2158 {
2159 struct aml_dsc *dsc = ch->dsc;
2160 u32 data;
2161 u32 in = 0, out = 0;
2162 int set = 0;
2163
2164 if (dsc->id != 0) {
2165 pr_error("Ciplus set output can only work at dsc0 device\n");
2166 return;
2167 }
2168
2169 switch (dsc->source) {
2170 case AM_TS_SRC_DMX0:
2171 in = 0;
2172 break;
2173 case AM_TS_SRC_DMX1:
2174 in = 1;
2175 break;
2176 case AM_TS_SRC_DMX2:
2177 in = 2;
2178 break;
2179 default:
2180 break;
2181 }
2182
2183 if (ciplus_out_auto_mode == 1) {
2184 switch (dsc->dst) {
2185 case AM_TS_SRC_DMX0:
2186 out = 1;
2187 break;
2188 case AM_TS_SRC_DMX1:
2189 out = 2;
2190 break;
2191 case AM_TS_SRC_DMX2:
2192 out = 4;
2193 break;
2194 default:
2195 break;
2196 }
2197 set = 1;
2198 ciplus_out_sel = out;
2199 } else if (ciplus_out_sel >= 0 && ciplus_out_sel <= 7) {
2200 set = 1;
2201 out = ciplus_out_sel;
2202 } else {
2203 pr_error("dsc ciplus out config is invalid\n");
2204 }
2205
2206 if (set) {
2207 /* Set ciplus input source ,
2208 * output set 0 means no output. ---> need confirm.
2209 * if output set 0 still affects dsc output, we need to disable
2210 * ciplus module.
2211 */
2212 data = READ_MPEG_REG(STB_TOP_CONFIG);
2213 data &= ~(3<<CIPLUS_IN_SEL);
2214 data |= in << CIPLUS_IN_SEL;
2215 data &= ~(7<<CIPLUS_OUT_SEL);
2216 data |= out << CIPLUS_OUT_SEL;
2217 WRITE_MPEG_REG(STB_TOP_CONFIG, data);
2218 pr_inf("dsc ciplus in[%x] out[%x] %s\n", in, out,
2219 (ciplus_out_auto_mode) ? "" : "force");
2220 }
2221 }
2222
2223 #if 0
2224 /*
2225 * Ciplus output has high priority,
2226 * disable it's output will let dsc output go.
2227 */
2228 static void aml_ci_plus_disable_output(void)
2229 {
2230 u32 data = 0;
2231
2232 data = READ_MPEG_REG(STB_TOP_CONFIG);
2233 WRITE_MPEG_REG(STB_TOP_CONFIG, data &
2234 ~(7 << CIPLUS_OUT_SEL));
2235 }
2236
2237 static void aml_ci_plus_enable(void)
2238 {
2239 u32 data = 0;
2240
2241 data = READ_MPEG_REG(STB_TOP_CONFIG);
2242 WRITE_MPEG_REG(CIPLUS_CONFIG,
2243 (1 << CNTL_ENABLE)
2244 | (1 << AES_EN)
2245 | (1 << DES_EN));
2246 }
2247 #endif
2248
aml_ci_plus_disable(void)2249 static void aml_ci_plus_disable(void)
2250 {
2251 u32 data = 0;
2252
2253 WRITE_MPEG_REG(CIPLUS_CONFIG, 0);
2254
2255 data = READ_MPEG_REG(STB_TOP_CONFIG);
2256 WRITE_MPEG_REG(STB_TOP_CONFIG, data &
2257 ~((1 << CIPLUS_IN_SEL) | (7 << CIPLUS_OUT_SEL)));
2258 }
2259
dsc_set_aes_des_sm4_key(struct aml_dsc_channel * ch,int flags,enum ca_cw_type type,u8 * key)2260 static int dsc_set_aes_des_sm4_key(struct aml_dsc_channel *ch, int flags,
2261 enum ca_cw_type type, u8 *key)
2262 {
2263 unsigned int k0, k1, k2, k3;
2264 int iv = 0, aes = 0, des = 0;
2265 int ab_iv = 0, ab_aes = 0, ab_des = 0;
2266 int from_kl = flags & CA_CW_FROM_KL;
2267 int algo = 0;
2268
2269 if (!from_kl) {
2270 if (get_cpu_type() < MESON_CPU_MAJOR_ID_SM1) {
2271 k3 = (key[0] << 24) | (key[1] << 16) | (key[2] << 8) | key[3];
2272 k2 = (key[4] << 24) | (key[5] << 16) | (key[6] << 8) | key[7];
2273 k1 = (key[8] << 24) | (key[9] << 16) | (key[10] << 8) | key[11];
2274 k0 = (key[12] << 24) | (key[13] << 16)
2275 | (key[14] << 8) | key[15];
2276 } else {
2277 k0 = (key[0]) | (key[1] << 8) | (key[2] << 16) | (key[3] << 24);
2278 k1 = (key[4]) | (key[5] << 8) | (key[6] << 16) | (key[7] << 24);
2279 k2 = (key[8]) | (key[9] << 8) | (key[10] << 16)| (key[11] << 24);
2280 k3 = (key[12])| (key[13] << 8)| (key[14] << 16)| (key[15] << 24);
2281 }
2282 } else
2283 k0 = k1 = k2 = k3 = 0;
2284
2285 switch (type) {
2286 case CA_CW_AES_EVEN:
2287 case CA_CW_SM4_EVEN:
2288 ab_aes = (from_kl) ? 0x2 : 0x1;
2289 if (ch->mode == -1)
2290 ch->mode = ECB_MODE;
2291 aes = 1;
2292 if (type == CA_CW_AES_EVEN)
2293 algo = ALGO_AES;
2294 else
2295 algo = ALGO_SM4;
2296 break;
2297 case CA_CW_AES_ODD:
2298 case CA_CW_SM4_ODD:
2299 ab_aes = (from_kl) ? 0x1 : 0x2;
2300 if (ch->mode == -1)
2301 ch->mode = ECB_MODE;
2302 aes = 1;
2303 if (type == CA_CW_AES_ODD)
2304 algo = ALGO_AES;
2305 else
2306 algo = ALGO_SM4;
2307 break;
2308 case CA_CW_AES_EVEN_IV:
2309 case CA_CW_SM4_EVEN_IV:
2310 ab_iv = 0x1;
2311 if (ch->mode == -1)
2312 ch->mode = CBC_MODE;
2313 iv = 1;
2314 if (type == CA_CW_AES_EVEN_IV)
2315 algo = ALGO_AES;
2316 else
2317 algo = ALGO_SM4;
2318 break;
2319 case CA_CW_AES_ODD_IV:
2320 case CA_CW_SM4_ODD_IV:
2321 ab_iv = 0x2;
2322 if (ch->mode == -1)
2323 ch->mode = CBC_MODE;
2324 iv = 1;
2325 if (type == CA_CW_AES_ODD_IV)
2326 algo = ALGO_AES;
2327 else
2328 algo = ALGO_SM4;
2329 break;
2330 case CA_CW_DES_EVEN:
2331 ab_des = 0x1;
2332 ch->mode = ECB_MODE;
2333 des = 1;
2334 algo = ALGO_DES;
2335 break;
2336 case CA_CW_DES_ODD:
2337 ab_des = 0x2;
2338 ch->mode = ECB_MODE;
2339 algo = ALGO_DES;
2340 des = 1;
2341 break;
2342 default:
2343 break;
2344 }
2345
2346 /* Set endian and cbc/ecb mode */
2347 if (from_kl)
2348 aml_ci_plus_config(7, ch->mode, algo);
2349 else
2350 aml_ci_plus_config(0, ch->mode, algo);
2351
2352 /* Write keys to work */
2353 if (iv || aes) {
2354 WRITE_MPEG_REG(CIPLUS_KEY0, k0);
2355 WRITE_MPEG_REG(CIPLUS_KEY1, k1);
2356 WRITE_MPEG_REG(CIPLUS_KEY2, k2);
2357 WRITE_MPEG_REG(CIPLUS_KEY3, k3);
2358 } else {/*des*/
2359 WRITE_MPEG_REG(CIPLUS_KEY0, k2);
2360 WRITE_MPEG_REG(CIPLUS_KEY1, k3);
2361 WRITE_MPEG_REG(CIPLUS_KEY2, 0);
2362 WRITE_MPEG_REG(CIPLUS_KEY3, 0);
2363 }
2364 WRITE_MPEG_REG(CIPLUS_KEY_WR,
2365 (ch->id << 9) |
2366 /* bit[11:9] the key of index,
2367 need match PID index*/
2368 ((from_kl && des) ? (1 << 8) : 0) |
2369 /* bit[8] des key use cw[127:64]*/
2370 (0 << 7) | /* bit[7] aes iv use cw*/
2371 ((from_kl && (aes || des)) ? (1 << 6) : 0) |
2372 /* bit[6] aes/des key use cw*/
2373 /* bit[5] write AES IV B value*/
2374 (ab_iv << 4) | /* bit[4] write AES IV A value*/
2375 /* bit[3] write AES B key*/
2376 (ab_aes << 2) | /* bit[2] write AES A key*/
2377 /* bit[1] write DES B key*/
2378 (ab_des)); /* bit[0] write DES A key*/
2379
2380 /*
2381 pr_inf("k:%08x:%08x:%08x:%08x kl:%d aes:%d des:%d ab_iv:%d ab_aes:%d ab_des:%d id:%d mod:%d\n",
2382 k0, k1, k2, k3,
2383 from_kl, aes, des, ab_iv, ab_aes, ab_des, ch->id, ch->aes_mode);
2384 */
2385 return 0;
2386 }
2387
dsc_release(void)2388 void dsc_release(void)
2389 {
2390 aml_ci_plus_disable();
2391 }
2392 /************************* AES DESC************************************/
set_ciplus_input_source(struct aml_dsc * dsc)2393 void set_ciplus_input_source(struct aml_dsc *dsc)
2394 {
2395 u32 data;
2396 u32 in = 0;
2397
2398 if (dsc->id != 0) {
2399 pr_error("Ciplus set output can only work at dsc0 device\n");
2400 return;
2401 }
2402
2403 switch (dsc->source) {
2404 case AM_TS_SRC_DMX0:
2405 in = 0;
2406 break;
2407 case AM_TS_SRC_DMX1:
2408 in = 1;
2409 break;
2410 case AM_TS_SRC_DMX2:
2411 in = 2;
2412 break;
2413 default:
2414 break;
2415 }
2416
2417 if (ciplus_out_auto_mode == 1) {
2418 /* Set ciplus input source */
2419 data = READ_MPEG_REG(STB_TOP_CONFIG);
2420 data &= ~(3<<CIPLUS_IN_SEL);
2421 data |= in << CIPLUS_IN_SEL;
2422 WRITE_MPEG_REG(STB_TOP_CONFIG, data);
2423 pr_inf("dsc ciplus in[%x]\n", in);
2424 }
2425 }
2426
dsc_enable(struct aml_dsc * dsc,int enable)2427 int dsc_enable(struct aml_dsc *dsc, int enable)
2428 {
2429 if (dsc->id == 0) {
2430 WRITE_MPEG_REG(STB_TOP_CONFIG,
2431 READ_MPEG_REG(STB_TOP_CONFIG) &
2432 ~((0x11 << DES_INPUT_SEL)|
2433 (1 << ENABLE_DES_PL)|
2434 (1 << ENABLE_DES_PL_CLK)));
2435 } else if (dsc->id == 1) {
2436 WRITE_MPEG_REG(COMM_DESC_2_CTL, 0);
2437 }
2438 return 0;
2439 }
2440
2441 /*Set section buffer*/
dmx_alloc_sec_buffer(struct aml_dmx * dmx)2442 static int dmx_alloc_sec_buffer(struct aml_dmx *dmx)
2443 {
2444 unsigned long base;
2445 unsigned long grp_addr[SEC_BUF_GRP_COUNT];
2446 int grp_len[SEC_BUF_GRP_COUNT];
2447 int i;
2448
2449 if (dmx->sec_pages)
2450 return 0;
2451
2452 grp_len[0] = (1 << SEC_GRP_LEN_0) * 8;
2453 grp_len[1] = (1 << SEC_GRP_LEN_1) * 8;
2454 grp_len[2] = (1 << SEC_GRP_LEN_2) * 8;
2455 grp_len[3] = (1 << SEC_GRP_LEN_3) * 8;
2456
2457 dmx->sec_total_len = grp_len[0] + grp_len[1] + grp_len[2] + grp_len[3];
2458 dmx->sec_pages =
2459 __get_free_pages(GFP_KERNEL, get_order(dmx->sec_total_len));
2460 if (!dmx->sec_pages) {
2461 pr_error("cannot allocate section buffer %d bytes %d order\n",
2462 dmx->sec_total_len, get_order(dmx->sec_total_len));
2463 return -1;
2464 }
2465 dmx->sec_pages_map =
2466 dma_map_single(dmx_get_dev(dmx), (void *)dmx->sec_pages,
2467 dmx->sec_total_len, DMA_FROM_DEVICE);
2468
2469 grp_addr[0] = dmx->sec_pages_map;
2470
2471 grp_addr[1] = grp_addr[0] + grp_len[0];
2472 grp_addr[2] = grp_addr[1] + grp_len[1];
2473 grp_addr[3] = grp_addr[2] + grp_len[2];
2474
2475 dmx->sec_buf[0].addr = dmx->sec_pages;
2476 dmx->sec_buf[0].len = grp_len[0] / 8;
2477
2478 for (i = 1; i < SEC_BUF_COUNT; i++) {
2479 dmx->sec_buf[i].addr =
2480 dmx->sec_buf[i - 1].addr + dmx->sec_buf[i - 1].len;
2481 dmx->sec_buf[i].len = grp_len[i / 8] / 8;
2482 }
2483
2484 base = grp_addr[0] & 0xFFFF0000;
2485 DMX_WRITE_REG(dmx->id, SEC_BUFF_BASE, base >> 16);
2486 DMX_WRITE_REG(dmx->id, SEC_BUFF_01_START,
2487 (((grp_addr[0] - base) >> 8) << 16) |
2488 ((grp_addr[1] - base) >> 8));
2489 DMX_WRITE_REG(dmx->id, SEC_BUFF_23_START,
2490 (((grp_addr[2] - base) >> 8) << 16) |
2491 ((grp_addr[3] - base) >> 8));
2492 DMX_WRITE_REG(dmx->id, SEC_BUFF_SIZE,
2493 SEC_GRP_LEN_0 |
2494 (SEC_GRP_LEN_1 << 4) |
2495 (SEC_GRP_LEN_2 << 8) |
2496 (SEC_GRP_LEN_3 << 12));
2497
2498 return 0;
2499 }
2500
2501 #ifdef NO_SUB
2502 /*Set subtitle buffer*/
dmx_alloc_sub_buffer(struct aml_dvb * dvb,struct aml_dmx * dmx)2503 static int dmx_alloc_sub_buffer(struct aml_dvb *dvb, struct aml_dmx *dmx)
2504 {
2505 #ifdef SUB_BUF_DMX
2506 unsigned long addr;
2507
2508 if (dmx->sub_pages)
2509 return 0;
2510
2511 /*check if use shared buf*/
2512 if (dvb->sub_pages) {
2513 dmx->sub_pages = dvb->sub_pages;
2514 dmx->sub_buf_len = dvb->sub_buf_len;
2515 dmx->sub_pages_map = dvb->sub_pages_map;
2516 goto end_alloc;
2517 }
2518
2519 dmx->sub_buf_len = 64 * 1024;
2520 dmx->sub_pages =
2521 __get_free_pages(GFP_KERNEL, get_order(dmx->sub_buf_len));
2522 if (!dmx->sub_pages) {
2523 pr_error("cannot allocate subtitle buffer\n");
2524 return -1;
2525 }
2526 dmx->sub_pages_map =
2527 dma_map_single(dmx_get_dev(dmx), (void *)dmx->sub_pages,
2528 dmx->sub_buf_len, DMA_FROM_DEVICE);
2529
2530 end_alloc:
2531 addr = virt_to_phys((void *)dmx->sub_pages);
2532 #ifndef SUB_PARSER
2533 DMX_WRITE_REG(dmx->id, SB_START, addr >> 12);
2534 DMX_WRITE_REG(dmx->id, SB_LAST_ADDR, (dmx->sub_buf_len >> 3) - 1);
2535 #endif
2536 pr_inf("sub buff: (%d) %lx %x\n", dmx->id, addr, dmx->sub_buf_len);
2537 #endif
2538 return 0;
2539 }
2540 #ifdef SUB_BUF_SHARED
dmx_alloc_sub_buffer_shared(struct aml_dvb * dvb)2541 static int dmx_alloc_sub_buffer_shared(struct aml_dvb *dvb)
2542 {
2543 #ifdef SUB_BUF_DMX
2544 if (dvb->sub_pages)
2545 return 0;
2546
2547 dvb->sub_buf_len = 64 * 1024;
2548 dvb->sub_pages =
2549 __get_free_pages(GFP_KERNEL, get_order(dvb->sub_buf_len));
2550 if (!dvb->sub_pages) {
2551 pr_error("cannot allocate subtitle buffer\n");
2552 return -1;
2553 }
2554 dvb->sub_pages_map =
2555 dma_map_single(dvb->dev, (void *)dvb->sub_pages,
2556 dvb->sub_buf_len, DMA_FROM_DEVICE);
2557
2558 pr_inf("sub buff shared: %lx %x\n",
2559 (unsigned long)virt_to_phys((void *)dvb->sub_pages),
2560 dvb->sub_buf_len);
2561 #endif
2562 return 0;
2563 }
2564 #endif
2565 #endif /*NO_SUB */
2566
2567 /*Set PES buffer*/
dmx_alloc_pes_buffer(struct aml_dvb * dvb,struct aml_dmx * dmx)2568 static int dmx_alloc_pes_buffer(struct aml_dvb *dvb, struct aml_dmx *dmx)
2569 {
2570 unsigned long addr;
2571
2572 if (dmx->pes_pages)
2573 return 0;
2574
2575 /*check if use shared buf*/
2576 if (dvb->pes_pages) {
2577 dmx->pes_pages = dvb->pes_pages;
2578 dmx->pes_buf_len = dvb->pes_buf_len;
2579 dmx->pes_pages_map = dvb->pes_pages_map;
2580 goto end_alloc;
2581 }
2582
2583 dmx->pes_buf_len = 64 * 1024;
2584 dmx->pes_pages =
2585 __get_free_pages(GFP_KERNEL, get_order(dmx->pes_buf_len));
2586 if (!dmx->pes_pages) {
2587 pr_error("cannot allocate pes buffer\n");
2588 return -1;
2589 }
2590 dmx->pes_pages_map =
2591 dma_map_single(dmx_get_dev(dmx), (void *)dmx->pes_pages,
2592 dmx->pes_buf_len, DMA_FROM_DEVICE);
2593 end_alloc:
2594 addr = virt_to_phys((void *)dmx->pes_pages);
2595 DMX_WRITE_REG(dmx->id, OB_START, addr >> 12);
2596 DMX_WRITE_REG(dmx->id, OB_LAST_ADDR, (dmx->pes_buf_len >> 3) - 1);
2597
2598 pr_inf("pes buff: (%d) %lx %x\n", dmx->id, addr, dmx->pes_buf_len);
2599 return 0;
2600 }
2601 #ifdef PES_BUF_SHARED
dmx_alloc_pes_buffer_shared(struct aml_dvb * dvb)2602 static int dmx_alloc_pes_buffer_shared(struct aml_dvb *dvb)
2603 {
2604 if (dvb->pes_pages)
2605 return 0;
2606
2607 dvb->pes_buf_len = 64 * 1024;
2608 dvb->pes_pages =
2609 __get_free_pages(GFP_KERNEL, get_order(dvb->pes_buf_len));
2610 if (!dvb->pes_pages) {
2611 pr_error("cannot allocate pes buffer\n");
2612 return -1;
2613 }
2614 dvb->pes_pages_map =
2615 dma_map_single(dvb->dev, (void *)dvb->pes_pages,
2616 dvb->pes_buf_len, DMA_FROM_DEVICE);
2617
2618 pr_inf("pes buff shared: %lx %x\n",
2619 (unsigned long)virt_to_phys((void *)dvb->pes_pages),
2620 dvb->pes_buf_len);
2621 return 0;
2622 }
2623 #endif
2624
2625 /*Allocate ASYNC FIFO Buffer*/
asyncfifo_alloc_buffer(struct aml_asyncfifo * afifo,int len)2626 static unsigned long asyncfifo_alloc_buffer(struct aml_asyncfifo *afifo, int len)
2627 {
2628 if (!afifo->stored_pages) {
2629 afifo->stored_pages = __get_free_pages(GFP_KERNEL, get_order(len));
2630 }
2631
2632 if (!afifo->stored_pages) {
2633 pr_error("cannot allocate async fifo buffer\n");
2634 return 0;
2635 }
2636 return afifo->stored_pages;
2637 }
asyncfifo_free_buffer(unsigned long buf,int len)2638 static void asyncfifo_free_buffer(unsigned long buf, int len)
2639 {
2640 //free_pages(buf, get_order(len));
2641 }
2642
asyncfifo_set_buffer(struct aml_asyncfifo * afifo,int len,unsigned long buf)2643 static int asyncfifo_set_buffer(struct aml_asyncfifo *afifo,
2644 int len, unsigned long buf)
2645 {
2646 if (afifo->pages)
2647 return -1;
2648
2649 afifo->buf_toggle = 0;
2650 afifo->buf_read = 0;
2651 afifo->buf_len = dmx_get_afifo_size(afifo);
2652 pr_error("++++async fifo %d buf %lu buf size %d, flush size %d, secure_enable %d, blk.addr %u\n",
2653 afifo->id, buf, afifo->buf_len, afifo->flush_size, afifo->secure_enable, afifo->blk.addr);
2654
2655 if ((afifo->flush_size <= 0)
2656 || (afifo->flush_size > (len>>1))) {
2657 afifo->flush_size = len>>1;
2658 } else if (afifo->flush_size < 128) {
2659 afifo->flush_size = 128;
2660 } else {
2661 int fsize;
2662
2663 for (fsize = 128; fsize < (len>>1); fsize <<= 1) {
2664 if (fsize >= afifo->flush_size)
2665 break;
2666 }
2667
2668 afifo->flush_size = fsize;
2669 }
2670
2671 afifo->pages = buf;
2672 if (!afifo->pages)
2673 return -1;
2674
2675 afifo->pages_map = dma_map_single(asyncfifo_get_dev(afifo),
2676 (void *)afifo->pages, len, DMA_FROM_DEVICE);
2677
2678 return 0;
2679 }
asyncfifo_put_buffer(struct aml_asyncfifo * afifo)2680 static void asyncfifo_put_buffer(struct aml_asyncfifo *afifo)
2681 {
2682 if (afifo->pages) {
2683 dma_unmap_single(asyncfifo_get_dev(afifo),
2684 afifo->pages_map, asyncfifo_buf_len, DMA_FROM_DEVICE);
2685 asyncfifo_free_buffer(afifo->pages, asyncfifo_buf_len);
2686 afifo->pages_map = 0;
2687 afifo->pages = 0;
2688 }
2689 }
2690
async_fifo_init(struct aml_asyncfifo * afifo,int initirq,int buf_len,unsigned long buf)2691 int async_fifo_init(struct aml_asyncfifo *afifo, int initirq,
2692 int buf_len, unsigned long buf)
2693 {
2694 int ret = 0;
2695 int irq;
2696
2697 if (afifo->init)
2698 return -1;
2699
2700 afifo->source = AM_DMX_MAX;
2701 afifo->pages = 0;
2702 afifo->buf_toggle = 0;
2703 afifo->buf_read = 0;
2704 afifo->buf_len = 0;
2705
2706 if (afifo->asyncfifo_irq == -1) {
2707 pr_error("no irq for ASYNC_FIFO%d\n", afifo->id);
2708 /*Do not return error*/
2709 return -1;
2710 }
2711
2712 tasklet_init(&afifo->asyncfifo_tasklet,
2713 dvr_irq_bh_handler, (unsigned long)afifo);
2714 if (initirq)
2715 irq = request_irq(afifo->asyncfifo_irq, dvr_irq_handler,
2716 IRQF_SHARED|IRQF_TRIGGER_RISING,
2717 "dvr irq", afifo);
2718 else
2719 enable_irq(afifo->asyncfifo_irq);
2720
2721 /*alloc buffer*/
2722 ret = asyncfifo_set_buffer(afifo, buf_len, buf);
2723
2724 afifo->init = 1;
2725
2726 return ret;
2727 }
2728
async_fifo_deinit(struct aml_asyncfifo * afifo,int freeirq)2729 int async_fifo_deinit(struct aml_asyncfifo *afifo, int freeirq)
2730 {
2731 struct aml_dvb *dvb = afifo->dvb;
2732 unsigned long flags;
2733
2734 if (!afifo->init)
2735 return 0;
2736
2737 spin_lock_irqsave(&dvb->slock, flags);
2738 CLEAR_ASYNC_FIFO_REG_MASK(afifo->id, REG1, 1 << ASYNC_FIFO_FLUSH_EN);
2739 CLEAR_ASYNC_FIFO_REG_MASK(afifo->id, REG2, 1 << ASYNC_FIFO_FILL_EN);
2740 spin_unlock_irqrestore(&dvb->slock, flags);
2741
2742 asyncfifo_put_buffer(afifo);
2743
2744 afifo->source = AM_DMX_MAX;
2745 afifo->buf_toggle = 0;
2746 afifo->buf_read = 0;
2747 afifo->buf_len = 0;
2748
2749 if (afifo->asyncfifo_irq != -1) {
2750 if (freeirq)
2751 free_irq(afifo->asyncfifo_irq, afifo);
2752 else
2753 disable_irq(afifo->asyncfifo_irq);
2754 }
2755 tasklet_kill(&afifo->asyncfifo_tasklet);
2756
2757 afifo->init = 0;
2758
2759 return 0;
2760 }
2761
_dmx_smallsec_enable(struct aml_smallsec * ss,int bufsize)2762 static int _dmx_smallsec_enable(struct aml_smallsec *ss, int bufsize)
2763 {
2764 if (!ss->buf) {
2765
2766 ss->buf = __get_free_pages(GFP_KERNEL,
2767 get_order(bufsize));
2768 if (!ss->buf) {
2769 pr_error("cannot allocate smallsec buffer\n"
2770 "%d bytes %d order\n",
2771 bufsize, get_order(bufsize));
2772 return -1;
2773 }
2774 ss->buf_map = dma_map_single(dmx_get_dev(ss->dmx),
2775 (void *)ss->buf,
2776 bufsize, DMA_FROM_DEVICE);
2777 }
2778
2779 DMX_WRITE_REG(ss->dmx->id, DEMUX_SMALL_SEC_ADDR,
2780 ss->buf_map);
2781 DMX_WRITE_REG(ss->dmx->id, DEMUX_SMALL_SEC_CTL,
2782 ((((bufsize>>8)-1)&0xff)<<24) |
2783 (1<<1) |/*enable reset the wr ptr*/
2784 (1<<0));
2785
2786 ss->bufsize = bufsize;
2787 ss->enable = 1;
2788
2789 pr_inf("demux%d smallsec buf start: %lx, size: %d\n",
2790 ss->dmx->id, ss->buf, ss->bufsize);
2791 return 0;
2792 }
2793
_dmx_smallsec_disable(struct aml_smallsec * ss)2794 static int _dmx_smallsec_disable(struct aml_smallsec *ss)
2795 {
2796 DMX_WRITE_REG(ss->dmx->id, DEMUX_SMALL_SEC_CTL, 0);
2797 if (ss->buf) {
2798 dma_unmap_single(dmx_get_dev(ss->dmx), ss->buf_map,
2799 ss->bufsize, DMA_FROM_DEVICE);
2800 free_pages(ss->buf, get_order(ss->bufsize));
2801 ss->buf = 0;
2802 ss->buf_map = 0;
2803 }
2804 ss->enable = 0;
2805 pr_inf("demux%d smallsec buf disable\n", ss->dmx->id);
2806 return 0;
2807 }
2808
dmx_smallsec_set(struct aml_smallsec * ss,int enable,int bufsize,int force)2809 static int dmx_smallsec_set(struct aml_smallsec *ss, int enable, int bufsize,
2810 int force)
2811 {
2812 if (!enable) {/*disable*/
2813
2814 if (ss->enable || force)
2815 _dmx_smallsec_disable(ss);
2816
2817 } else {/*enable*/
2818
2819 if (bufsize < 0)
2820 bufsize = SS_BUFSIZE_DEF;
2821 else if (!bufsize)
2822 bufsize = ss->bufsize;
2823 else {
2824 /*unit:FF max:FF00*/
2825 bufsize &= ~0xFF;
2826 bufsize &= 0x1FF00;
2827 }
2828
2829 if ((ss->enable && (bufsize != ss->bufsize)) || force)
2830 _dmx_smallsec_disable(ss);
2831
2832 if (!ss->enable)
2833 _dmx_smallsec_enable(ss, bufsize);
2834 }
2835
2836 return 0;
2837 }
2838
_dmx_timeout_enable(struct aml_dmxtimeout * dto,int timeout,int ch_dis,int match)2839 static int _dmx_timeout_enable(struct aml_dmxtimeout *dto, int timeout,
2840 int ch_dis, int match)
2841 {
2842
2843 DMX_WRITE_REG(dto->dmx->id, DEMUX_INPUT_TIMEOUT_C, ch_dis);
2844 DMX_WRITE_REG(dto->dmx->id, DEMUX_INPUT_TIMEOUT,
2845 ((!!match)<<31) |
2846 (timeout&0x7fffffff));
2847
2848 dto->ch_disable = ch_dis;
2849 dto->match = match;
2850 dto->timeout = timeout;
2851 dto->trigger = 0;
2852 dto->enable = 1;
2853
2854 pr_inf("demux%d timeout enable:timeout(%d),ch(0x%x),match(%d)\n",
2855 dto->dmx->id, dto->timeout, dto->ch_disable, dto->match);
2856
2857 return 0;
2858 }
_dmx_timeout_disable(struct aml_dmxtimeout * dto)2859 static int _dmx_timeout_disable(struct aml_dmxtimeout *dto)
2860 {
2861
2862 DMX_WRITE_REG(dto->dmx->id, DEMUX_INPUT_TIMEOUT, 0);
2863 dto->enable = 0;
2864 dto->trigger = 0;
2865 pr_inf("demux%d timeout disable\n", dto->dmx->id);
2866
2867 return 0;
2868 }
2869
dmx_timeout_set(struct aml_dmxtimeout * dto,int enable,int timeout,int ch_dis,int match,int force)2870 static int dmx_timeout_set(struct aml_dmxtimeout *dto, int enable,
2871 int timeout, int ch_dis, int match,
2872 int force)
2873 {
2874
2875 if (!enable) {/*disable*/
2876
2877 if (dto->enable || force)
2878 _dmx_timeout_disable(dto);
2879
2880 } else {/*enable*/
2881
2882 if (timeout < 0) {
2883 timeout = DTO_TIMEOUT_DEF;
2884 ch_dis = DTO_CHDIS_VAS;
2885 match = dto->match;
2886 } else if (!timeout) {
2887 timeout = dto->timeout;
2888 ch_dis = dto->ch_disable;
2889 match = dto->match;
2890 }
2891
2892 if ((dto->enable && (timeout != dto->timeout))
2893 || force)
2894 _dmx_timeout_disable(dto);
2895
2896 if (!dto->enable)
2897 _dmx_timeout_enable(dto, timeout, ch_dis, match);
2898 }
2899
2900 return 0;
2901 }
2902
2903 /*Initialize the registers*/
dmx_init(struct aml_dmx * dmx)2904 static int dmx_init(struct aml_dmx *dmx)
2905 {
2906 struct aml_dvb *dvb = (struct aml_dvb *)dmx->demux.priv;
2907 int irq;
2908 int ret = 0;
2909 char buf[32];
2910 u32 value = 0;
2911
2912 if (dmx->init)
2913 return 0;
2914
2915 pr_dbg("[dmx_kpi] %s Enter\n", __func__);
2916
2917 memset(buf, 0, 32);
2918 snprintf(buf, sizeof(buf), "asyncfifo_buf_len");
2919 ret = of_property_read_u32(dvb->pdev->dev.of_node, buf, &value);
2920 if (!ret) {
2921 pr_inf("%s: 0x%x\n", buf, value);
2922 asyncfifo_buf_len = value;
2923 }
2924 /*Register irq handlers */
2925 if (dmx->dmx_irq != -1) {
2926 pr_dbg("request irq\n");
2927 tasklet_init(&dmx->dmx_tasklet,
2928 dmx_irq_bh_handler,
2929 (unsigned long)dmx);
2930 irq = request_irq(dmx->dmx_irq, dmx_irq_handler,
2931 IRQF_SHARED|IRQF_TRIGGER_RISING,
2932 "dmx irq", dmx);
2933 }
2934
2935 /*Allocate buffer */
2936 if (dmx_alloc_sec_buffer(dmx) < 0)
2937 return -1;
2938 #ifdef NO_SUB
2939 #ifdef SUB_BUF_SHARED
2940 if (dmx_alloc_sub_buffer_shared(dvb) < 0)
2941 return -1;
2942 #endif
2943 if (dmx_alloc_sub_buffer(dvb, dmx) < 0)
2944 return -1;
2945 #endif
2946 #ifdef PES_BUF_SHARED
2947 if (dmx_alloc_pes_buffer_shared(dvb) < 0)
2948 return -1;
2949 #endif
2950 if (dmx_alloc_pes_buffer(dvb, dmx) < 0)
2951 return -1;
2952 /*Reset the hardware */
2953 if (!dvb->dmx_init) {
2954 init_timer(&dvb->watchdog_timer);
2955 dvb->watchdog_timer.function = section_buffer_watchdog_func;
2956 dvb->watchdog_timer.expires =
2957 jiffies + msecs_to_jiffies(WATCHDOG_TIMER);
2958 dvb->watchdog_timer.data = (unsigned long)dvb;
2959 #ifdef ENABLE_SEC_BUFF_WATCHDOG
2960 add_timer(&dvb->watchdog_timer);
2961 #endif
2962 dmx_reset_hw(dvb);
2963 }
2964
2965 dvb->dmx_init++;
2966
2967 memset(dmx->sec_buf_watchdog_count, 0,
2968 sizeof(dmx->sec_buf_watchdog_count));
2969
2970 dmx->om_status_error_count = 0;
2971 dmx->init = 1;
2972 pr_dbg("[dmx_kpi] %s Exit\n", __func__);
2973 return 0;
2974 }
2975
2976 /*Release the resource*/
dmx_deinit(struct aml_dmx * dmx)2977 static int dmx_deinit(struct aml_dmx *dmx)
2978 {
2979 struct aml_dvb *dvb = (struct aml_dvb *)dmx->demux.priv;
2980 pr_dbg("[dmx_kpi] %s Enter\n", __func__);
2981 if (!dmx->init)
2982 return 0;
2983
2984 DMX_WRITE_REG(dmx->id, DEMUX_CONTROL, 0);
2985
2986 dvb->dmx_init--;
2987
2988 /*Reset the hardware */
2989 if (!dvb->dmx_init) {
2990 dmx_reset_hw(dvb);
2991 #ifdef ENABLE_SEC_BUFF_WATCHDOG
2992 del_timer_sync(&dvb->watchdog_timer);
2993 #endif
2994 }
2995
2996 if (dmx->sec_pages) {
2997 dma_unmap_single(dmx_get_dev(dmx), dmx->sec_pages_map,
2998 dmx->sec_total_len, DMA_FROM_DEVICE);
2999 free_pages(dmx->sec_pages, get_order(dmx->sec_total_len));
3000 dmx->sec_pages = 0;
3001 dmx->sec_pages_map = 0;
3002 }
3003 #ifdef NO_SUB
3004 #ifdef SUB_BUF_DMX
3005 #ifdef SUB_BUF_SHARED
3006 if (dvb->sub_pages) {
3007 dma_unmap_single(dvb->dev, dvb->sub_pages_map,
3008 dvb->sub_buf_len, DMA_FROM_DEVICE);
3009 free_pages(dvb->sub_pages, get_order(dvb->sub_buf_len));
3010 dvb->sub_pages = 0;
3011 }
3012 dmx->sub_pages = 0;
3013 #else
3014 if (dmx->sub_pages) {
3015 dma_unmap_single(dmx_get_dev(dmx), dmx->sub_pages_map,
3016 dmx->sub_buf_len, DMA_FROM_DEVICE);
3017 free_pages(dmx->sub_pages, get_order(dmx->sub_buf_len));
3018 dmx->sub_pages = 0;
3019 }
3020 #endif
3021 #endif
3022 #endif
3023 #ifdef PES_BUF_SHARED
3024 if (dvb->pes_pages) {
3025 dma_unmap_single(dvb->dev, dvb->pes_pages_map,
3026 dvb->pes_buf_len, DMA_FROM_DEVICE);
3027 free_pages(dvb->pes_pages, get_order(dvb->pes_buf_len));
3028 dvb->pes_pages = 0;
3029 }
3030 dmx->pes_pages = 0;
3031 #else
3032 if (dmx->pes_pages) {
3033 dma_unmap_single(dmx_get_dev(dmx), dmx->pes_pages_map,
3034 dmx->pes_buf_len, DMA_FROM_DEVICE);
3035 free_pages(dmx->pes_pages, get_order(dmx->pes_buf_len));
3036 dmx->pes_pages = 0;
3037 }
3038 #endif
3039 if (dmx->dmx_irq != -1) {
3040 free_irq(dmx->dmx_irq, dmx);
3041 tasklet_kill(&dmx->dmx_tasklet);
3042 }
3043
3044 dmx->init = 0;
3045 pr_dbg("[dmx_kpi] %s Exit\n", __func__);
3046 return 0;
3047 }
3048
3049 /*Check the record flag*/
dmx_get_record_flag(struct aml_dmx * dmx)3050 static int dmx_get_record_flag(struct aml_dmx *dmx)
3051 {
3052 int i, linked = 0, record_flag = 0;
3053 struct aml_dvb *dvb = (struct aml_dvb *)dmx->demux.priv;
3054
3055 /*Check whether a async fifo connected to this dmx */
3056 for (i = 0; i < dvb->async_fifo_total_count; i++) {
3057 if (!dvb->asyncfifo[i].init)
3058 continue;
3059 if ((dvb->asyncfifo[i].source == dmx->id)
3060 /*&& !(dvb->swfilter.user && (i==SF_AFIFO_ID)) */
3061 /*sf mode reserved */
3062 ) {
3063 linked = 1;
3064 break;
3065 }
3066 }
3067
3068 for (i = 0; i < CHANNEL_COUNT; i++) {
3069 if (dmx->channel[i].used && dmx->channel[i].dvr_feed) {
3070 if (!dmx->record) {
3071 pr_error("dmx_get_record_flag set record dmx->id: %d\n", dmx->id);
3072 dmx->record = 1;
3073
3074 if (linked) {
3075 /*A new record will start,
3076 * must reset the async fifos for
3077 * linking the right demux
3078 */
3079 reset_async_fifos(dvb);
3080 }
3081 }
3082 if (linked)
3083 record_flag = 1;
3084 goto find_done;
3085 }
3086 }
3087
3088 if (dmx->record) {
3089 pr_error("dmx_get_record_flag clear record dmx->id: %d\n", dmx->id);
3090 dmx->record = 0;
3091 if (linked) {
3092 /*A record will stop, reset the async fifos
3093 *for linking the right demux
3094 */
3095 reset_async_fifos(dvb);
3096 }
3097 }
3098
3099 find_done:
3100 return record_flag;
3101 }
3102
dmx_cascade_set(int cur_dmx,int source)3103 static void dmx_cascade_set(int cur_dmx, int source) {
3104 int fec_sel_demux = 0;
3105 int data;
3106
3107 switch (source) {
3108 case AM_TS_SRC_DMX0:
3109 case AM_TS_SRC_DMX1:
3110 case AM_TS_SRC_DMX2:
3111 fec_sel_demux = source -AM_TS_SRC_DMX0;
3112 break;
3113 default:
3114 fec_sel_demux = cur_dmx;
3115 break;
3116 }
3117
3118 data = READ_MPEG_REG(TS_TOP_CONFIG1);
3119 data &= ~(0x3 << (cur_dmx*2));
3120 data |= (fec_sel_demux << (cur_dmx*2));
3121 WRITE_MPEG_REG(TS_TOP_CONFIG1,data);
3122
3123 pr_dbg("%s id:%d, source:%d data:0x%0x\n",__FUNCTION__,cur_dmx,fec_sel_demux,data);
3124 }
3125
3126 /*Enable the demux device*/
dmx_enable(struct aml_dmx * dmx)3127 static int dmx_enable(struct aml_dmx *dmx)
3128 {
3129 struct aml_dvb *dvb = (struct aml_dvb *)dmx->demux.priv;
3130 int fec_sel, hi_bsf, fec_ctrl, record;
3131 int fec_core_sel = 0;
3132 int set_stb = 0, fec_s = 0;
3133 int s2p_id;
3134 u32 invert0 = 0, invert1 = 0, invert2 = 0, fec_s0 = 0, fec_s1 = 0, fec_s2 = 0;
3135 u32 use_sop = 0;
3136 int i = 0;
3137
3138 record = dmx_get_record_flag(dmx);
3139 if (use_of_sop == 1) {
3140 use_sop = 1;
3141 pr_inf("dmx use of sop input\r\n");
3142 }
3143 switch (dmx->source) {
3144 case AM_TS_SRC_TS0:
3145 fec_sel = 0;
3146 fec_ctrl = dvb->ts[0].control;
3147 record = record ? 1 : 0;
3148 break;
3149 case AM_TS_SRC_TS1:
3150 fec_sel = 1;
3151 fec_ctrl = dvb->ts[1].control;
3152 record = record ? 1 : 0;
3153 break;
3154 case AM_TS_SRC_TS2:
3155 fec_sel = 2;
3156 fec_ctrl = dvb->ts[2].control;
3157 record = record ? 1 : 0;
3158 break;
3159 case AM_TS_SRC_TS3:
3160 fec_sel = 3;
3161 fec_ctrl = dvb->ts[3].control;
3162 record = record ? 1 : 0;
3163 break;
3164 case AM_TS_SRC_S_TS0:
3165 case AM_TS_SRC_S_TS1:
3166 case AM_TS_SRC_S_TS2:
3167 s2p_id = 0;
3168 fec_ctrl = 0;
3169 if (dmx->source == AM_TS_SRC_S_TS0) {
3170 s2p_id = 0;
3171 } else if (dmx->source == AM_TS_SRC_S_TS1) {
3172 s2p_id = 1;
3173 } else if (dmx->source == AM_TS_SRC_S_TS2) {
3174 s2p_id = 2;
3175 }
3176 for (i = 0; i < dvb->s2p_total_count; i++) {
3177 if (dvb->ts[i].s2p_id == s2p_id) {
3178 fec_ctrl = dvb->ts[i].control;
3179 }
3180 }
3181 //fec_sel = (s2p_id == 1) ? 5 : 6;
3182 fec_sel = 6 - s2p_id;
3183 record = record ? 1 : 0;
3184 set_stb = 1;
3185 fec_s = dmx->source - AM_TS_SRC_S_TS0;
3186 break;
3187 case AM_TS_SRC_HIU:
3188 fec_sel = 7;
3189 fec_ctrl = 0;
3190 /*
3191 support record in HIU mode
3192 record = 0;
3193 */
3194 break;
3195 case AM_TS_SRC_HIU1:
3196 fec_sel = 8;
3197 fec_ctrl = 0;
3198 /*
3199 support record in HIU mode
3200 record = 0;
3201 */
3202 break;
3203 case AM_TS_SRC_DMX0:
3204 case AM_TS_SRC_DMX1:
3205 case AM_TS_SRC_DMX2:
3206 fec_sel = -1;
3207 fec_ctrl = 0;
3208 record = record ? 1 : 0;
3209 break;
3210 default:
3211 fec_sel = 0;
3212 fec_ctrl = 0;
3213 record = 0;
3214 break;
3215 }
3216
3217 if (dmx->channel[0].used || dmx->channel[1].used) {
3218 hi_bsf = 1;
3219 if (fec_sel == 8) {
3220 hi_bsf = 2; /*hi_bsf select hiu1*/
3221 }
3222 }else {
3223 hi_bsf = 0;
3224 }
3225 if ((dvb->dsc[0].dst != -1)
3226 && ((dvb->dsc[0].dst - AM_TS_SRC_DMX0) == dmx->id))
3227 fec_core_sel = 1;
3228
3229 if ((dvb->dsc[1].dst != -1)
3230 && ((dvb->dsc[1].dst - AM_TS_SRC_DMX0) == dmx->id)) {
3231 int des_in, des_out, en_des = 0;
3232
3233 switch (dvb->dsc[1].source) {
3234 case AM_TS_SRC_DMX0:
3235 des_in = 0;
3236 en_des = 1;
3237 break;
3238 case AM_TS_SRC_DMX1:
3239 des_in = 1;
3240 en_des = 1;
3241 break;
3242 case AM_TS_SRC_DMX2:
3243 des_in = 2;
3244 en_des = 1;
3245 break;
3246 default:
3247 des_in = 0;
3248 en_des = 0;
3249 break;
3250 }
3251
3252 switch (dvb->dsc[1].dst) {
3253 case AM_TS_SRC_DMX0:
3254 des_out = 1;
3255 break;
3256 case AM_TS_SRC_DMX1:
3257 des_out = 2;
3258 break;
3259 case AM_TS_SRC_DMX2:
3260 des_out = 4;
3261 break;
3262 default:
3263 des_out = 0;
3264 break;
3265 }
3266
3267 if (!des_out)
3268 en_des = 0;
3269
3270 WRITE_MPEG_REG(COMM_DESC_2_CTL,
3271 (6 << 8) |/*des_out_dly_2*/
3272 ((!!en_des) << 6) |/* des_pl_clk_2*/
3273 ((!!en_des) << 5) |/* des_pl_2*/
3274 (des_out << 2) |/*use_des_2*/
3275 (des_in)/*des_i_sel_2*/
3276 );
3277 fec_core_sel = 1;
3278 pr_dbg("dsc2 ctrl: 0x%x\n", READ_MPEG_REG(COMM_DESC_2_CTL));
3279 }
3280
3281 pr_dbg("[dmx-%d]src: %d, rec: %d, hi_bsf: %d, dsc: %d\n",
3282 dmx->id, dmx->source, record, hi_bsf, fec_core_sel);
3283
3284 if (dmx->chan_count) {
3285 if (set_stb) {
3286 u32 v = READ_MPEG_REG(STB_TOP_CONFIG);
3287 int i;
3288
3289 for (i = 0; i < dvb->ts_in_total_count; i++) {
3290 if (dvb->ts[i].s2p_id == 0)
3291 fec_s0 = i;
3292 else if (dvb->ts[i].s2p_id == 1)
3293 fec_s1 = i;
3294 else if (dvb->ts[i].s2p_id == 2)
3295 fec_s2 = i;
3296 }
3297
3298 invert0 = dvb->s2p[0].invert;
3299 invert1 = dvb->s2p[1].invert;
3300
3301 v &= ~((0x3 << S2P0_FEC_SERIAL_SEL) |
3302 (0x1f << INVERT_S2P0_FEC_CLK) |
3303 (0x3 << S2P1_FEC_SERIAL_SEL) |
3304 (0x1f << INVERT_S2P1_FEC_CLK));
3305
3306 v |= (fec_s0 << S2P0_FEC_SERIAL_SEL) |
3307 (invert0 << INVERT_S2P0_FEC_CLK) |
3308 (fec_s1 << S2P1_FEC_SERIAL_SEL) |
3309 (invert1 << INVERT_S2P1_FEC_CLK);
3310 WRITE_MPEG_REG(STB_TOP_CONFIG, v);
3311
3312 if (get_cpu_type() >= MESON_CPU_MAJOR_ID_TL1) {
3313 invert2 = dvb->s2p[2].invert;
3314
3315 //add s2p2 config
3316 v = READ_MPEG_REG(STB_S2P2_CONFIG);
3317 v &= ~((0x3 << S2P2_FEC_SERIAL_SEL) |
3318 (0x1f << INVERT_S2P2_FEC_CLK));
3319 v |= (fec_s2 << S2P2_FEC_SERIAL_SEL) |
3320 (invert2 << INVERT_S2P2_FEC_CLK);
3321 WRITE_MPEG_REG(STB_S2P2_CONFIG, v);
3322 }
3323 }
3324
3325 /*Initialize the registers */
3326 DMX_WRITE_REG(dmx->id, STB_INT_MASK, DEMUX_INT_MASK);
3327 DMX_WRITE_REG(dmx->id, DEMUX_MEM_REQ_EN,
3328 #ifdef USE_AHB_MODE
3329 (1 << SECTION_AHB_DMA_EN) |
3330 (0 << SUB_AHB_DMA_EN) |
3331 (1 << OTHER_PES_AHB_DMA_EN) |
3332 #endif
3333 (1 << SECTION_PACKET) |
3334 (1 << VIDEO_PACKET) |
3335 (1 << AUDIO_PACKET) |
3336 (1 << SUB_PACKET) |
3337 (1 << SCR_ONLY_PACKET) |
3338 (1 << OTHER_PES_PACKET));
3339 DMX_WRITE_REG(dmx->id, PES_STRONG_SYNC, 0x1234);
3340 DMX_WRITE_REG(dmx->id, DEMUX_ENDIAN,
3341 (1<<SEPERATE_ENDIAN) |
3342 (0<<OTHER_PES_ENDIAN) |
3343 (7<<SCR_ENDIAN) |
3344 (7<<SUB_ENDIAN) |
3345 (7<<AUDIO_ENDIAN) |
3346 (7<<VIDEO_ENDIAN) |
3347 (7 << OTHER_ENDIAN) |
3348 (7 << BYPASS_ENDIAN) | (0 << SECTION_ENDIAN));
3349 if (fec_sel != 8) {
3350 DMX_WRITE_REG(dmx->id, TS_HIU_CTL,
3351 // (0 << LAST_BURST_THRESHOLD) |
3352 (hi_bsf << USE_HI_BSF_INTERFACE));
3353 } else {
3354 DMX_WRITE_REG(dmx->id, TS_HIU_CTL,
3355 (1 << PDTS_WR_SEL) |
3356 (hi_bsf << USE_HI_BSF_INTERFACE));
3357 }
3358
3359 if (fec_sel == -1) {
3360 dmx_cascade_set(dmx->id,dmx->source);
3361 DMX_WRITE_REG(dmx->id, FEC_INPUT_CONTROL,
3362 (fec_core_sel << FEC_CORE_SEL) |
3363 (0 << FEC_SEL) | (fec_ctrl << 0));
3364 } else {
3365 dmx_cascade_set(dmx->id,dmx->source);
3366 if (fec_sel != 8) {
3367 DMX_WRITE_REG(dmx->id, FEC_INPUT_CONTROL,
3368 (fec_core_sel << FEC_CORE_SEL) |
3369 (fec_sel << FEC_SEL) | (fec_ctrl << 0));
3370 } else {
3371 DMX_WRITE_REG(dmx->id, FEC_INPUT_CONTROL,
3372 (fec_core_sel << FEC_CORE_SEL) |
3373 (1 << FEC_SEL_3BIT) | (fec_ctrl << 0));
3374 }
3375 }
3376 DMX_WRITE_REG(dmx->id, STB_OM_CTL,
3377 (0x40 << MAX_OM_DMA_COUNT) |
3378 (0x7f << LAST_OM_ADDR));
3379 DMX_WRITE_REG(dmx->id, DEMUX_CONTROL,
3380 (0 << BYPASS_USE_RECODER_PATH) |
3381 (0 << INSERT_AUDIO_PES_STRONG_SYNC) |
3382 (0 << INSERT_VIDEO_PES_STRONG_SYNC) |
3383 (0 << OTHER_INT_AT_PES_BEGINING) |
3384 (0 << DISCARD_AV_PACKAGE) |
3385 ((!!dmx->dump_ts_select) << TS_RECORDER_SELECT) |
3386 (record << TS_RECORDER_ENABLE) |
3387 (1 << KEEP_DUPLICATE_PACKAGE) |
3388 (1 << SECTION_END_WITH_TABLE_ID) |
3389 (1 << ENABLE_FREE_CLK_FEC_DATA_VALID) |
3390 (1 << ENABLE_FREE_CLK_STB_REG) |
3391 (1 << STB_DEMUX_ENABLE) |
3392 (use_sop << NOT_USE_OF_SOP_INPUT));
3393 } else {
3394 DMX_WRITE_REG(dmx->id, STB_INT_MASK, 0);
3395 DMX_WRITE_REG(dmx->id, FEC_INPUT_CONTROL, 0);
3396 DMX_WRITE_REG(dmx->id, DEMUX_CONTROL, 0);
3397 //dmx not used, but it can cascade for other dmx
3398 if ((dmx->source == AM_TS_SRC_DMX0 ||
3399 dmx->source == AM_TS_SRC_DMX1 ||
3400 dmx->source == AM_TS_SRC_DMX2 ) &&
3401 (dmx->id != dmx->source-AM_TS_SRC_DMX0))
3402 dmx_cascade_set(dmx->id,dmx->source);
3403 }
3404 return 0;
3405 }
3406
dmx_set_misc(struct aml_dmx * dmx,int hi_bsf,int en_dsc)3407 static int dmx_set_misc(struct aml_dmx *dmx, int hi_bsf, int en_dsc)
3408 {
3409 if (hi_bsf >= 0) {
3410 DMX_WRITE_REG(dmx->id, TS_HIU_CTL,
3411 hi_bsf ?
3412 (DMX_READ_REG(dmx->id, TS_HIU_CTL) |
3413 (1 << USE_HI_BSF_INTERFACE))
3414 :
3415 (DMX_READ_REG(dmx->id, TS_HIU_CTL) &
3416 (~(1 << USE_HI_BSF_INTERFACE))));
3417 }
3418
3419 if (en_dsc >= 0) {
3420 DMX_WRITE_REG(dmx->id, FEC_INPUT_CONTROL,
3421 en_dsc ?
3422 (DMX_READ_REG(dmx->id, FEC_INPUT_CONTROL) |
3423 (1 << FEC_CORE_SEL))
3424 :
3425 (DMX_READ_REG(dmx->id, FEC_INPUT_CONTROL) &
3426 (~(1 << FEC_CORE_SEL))));
3427 }
3428
3429 return 0;
3430 }
3431
dmx_set_misc_id(struct aml_dvb * dvb,int id,int hi_bsf,int en_dsc)3432 static int dmx_set_misc_id(struct aml_dvb *dvb, int id, int hi_bsf, int en_dsc)
3433 {
3434 return dmx_set_misc(&dvb->dmx[id], hi_bsf, en_dsc);
3435 }
3436
3437 /*Get the channel's ID by its PID*/
dmx_get_chan(struct aml_dmx * dmx,int pid)3438 static int dmx_get_chan(struct aml_dmx *dmx, int pid)
3439 {
3440 int id;
3441
3442 for (id = 0; id < CHANNEL_COUNT; id++) {
3443 if (dmx->channel[id].used && dmx->channel[id].pid == pid)
3444 return id;
3445 }
3446
3447 return -1;
3448 }
3449
3450 /*Get the channel's target*/
dmx_get_chan_target(struct aml_dmx * dmx,int cid)3451 static u32 dmx_get_chan_target(struct aml_dmx *dmx, int cid)
3452 {
3453 u32 type;
3454
3455 if (!dmx->channel[cid].used)
3456 return 0xFFFF;
3457
3458 if (dmx->channel[cid].type == DMX_TYPE_SEC) {
3459 type = SECTION_PACKET;
3460 } else {
3461 switch (dmx->channel[cid].pes_type) {
3462 case DMX_PES_AUDIO:
3463 type = AUDIO_PACKET;
3464 break;
3465 case DMX_PES_VIDEO:
3466 type = VIDEO_PACKET;
3467 break;
3468 case DMX_PES_SUBTITLE:
3469 case DMX_PES_TELETEXT:
3470 type = SUB_PACKET;
3471 break;
3472 case DMX_PES_PCR:
3473 type = SCR_ONLY_PACKET;
3474 break;
3475 case DMX_PES_AUDIO3:
3476 type = OTHER_PES_PACKET;
3477 break;
3478 default:
3479 type = BYPASS_PACKET;
3480 break;
3481 }
3482 }
3483
3484 pr_dbg("chan target: %x %x\n", type, dmx->channel[cid].pid);
3485 return (type << PID_TYPE) | dmx->channel[cid].pid;
3486 }
3487
3488 /*Get the advance value of the channel*/
dmx_get_chan_advance(struct aml_dmx * dmx,int cid)3489 static inline u32 dmx_get_chan_advance(struct aml_dmx *dmx, int cid)
3490 {
3491 return 0;
3492 }
3493
3494 /*Set the channel registers*/
dmx_set_chan_regs(struct aml_dmx * dmx,int cid)3495 static int dmx_set_chan_regs(struct aml_dmx *dmx, int cid)
3496 {
3497 u32 data, addr, advance, max;
3498
3499 pr_dbg("set channel (id:%d PID:0x%x) registers\n", cid,
3500 dmx->channel[cid].pid);
3501
3502 while (DMX_READ_REG(dmx->id, FM_WR_ADDR) & 0x8000)
3503 udelay(1);
3504
3505 if (cid & 1) {
3506 data =
3507 (dmx_get_chan_target(dmx, cid - 1) << 16) |
3508 dmx_get_chan_target(dmx, cid);
3509 advance =
3510 (dmx_get_chan_advance(dmx, cid) << 8) |
3511 dmx_get_chan_advance(dmx, cid - 1);
3512 } else {
3513 data =
3514 (dmx_get_chan_target(dmx, cid) << 16) |
3515 dmx_get_chan_target(dmx, cid + 1);
3516 advance =
3517 (dmx_get_chan_advance(dmx, cid + 1) << 8) |
3518 dmx_get_chan_advance(dmx, cid);
3519 }
3520 addr = cid >> 1;
3521 DMX_WRITE_REG(dmx->id, FM_WR_DATA, data);
3522 DMX_WRITE_REG(dmx->id, FM_WR_ADDR, (advance << 16) | 0x8000 | addr);
3523
3524 pr_dbg("write fm %x:%x\n", (advance << 16) | 0x8000 | addr, data);
3525
3526 for (max = CHANNEL_COUNT - 1; max > 0; max--) {
3527 if (dmx->channel[max].used)
3528 break;
3529 }
3530
3531 data = DMX_READ_REG(dmx->id, MAX_FM_COMP_ADDR) & 0xF0;
3532 DMX_WRITE_REG(dmx->id, MAX_FM_COMP_ADDR, data | (max >> 1));
3533
3534 pr_dbg("write fm comp %x\n", data | (max >> 1));
3535
3536 if (DMX_READ_REG(dmx->id, OM_CMD_STATUS) & 0x8e00) {
3537 pr_error("error send cmd %x\n",
3538 DMX_READ_REG(dmx->id, OM_CMD_STATUS));
3539 }
3540
3541 if (cid == 0) {
3542 video_pts = 0;
3543 first_video_pts = 0;
3544 }
3545 else if (cid == 1) {
3546 audio_pts = 0;
3547 first_audio_pts = 0;
3548 }
3549
3550 return 0;
3551 }
3552
3553 /*Get the filter target*/
dmx_get_filter_target(struct aml_dmx * dmx,int fid,u32 * target,u8 * advance)3554 static int dmx_get_filter_target(struct aml_dmx *dmx, int fid, u32 *target,
3555 u8 *advance)
3556 {
3557 struct dmx_section_filter *filter;
3558 struct aml_filter *f;
3559 int i, cid, neq_bytes;
3560
3561 fid = fid & 0xFFFF;
3562 f = &dmx->filter[fid];
3563
3564 if (!f->used) {
3565 target[0] = 0x1fff;
3566 advance[0] = 0;
3567 for (i = 1; i < FILTER_LEN; i++) {
3568 target[i] = 0x9fff;
3569 advance[i] = 0;
3570 }
3571 return 0;
3572 }
3573
3574 cid = f->chan_id;
3575 filter = f->filter;
3576
3577 neq_bytes = 0;
3578 if (filter->filter_mode[0] != 0xFF) {
3579 neq_bytes = 2;
3580 } else {
3581 for (i = 3; i < FILTER_LEN; i++) {
3582 if (filter->filter_mode[i] != 0xFF)
3583 neq_bytes++;
3584 }
3585 }
3586
3587 f->neq = 0;
3588
3589 for (i = 0; i < FILTER_LEN; i++) {
3590 u8 value = filter->filter_value[i];
3591 u8 mask = filter->filter_mask[i];
3592 u8 mode = filter->filter_mode[i];
3593 u8 mb, mb1, nb, v, t, adv = 0;
3594
3595 if (!i) {
3596 mb = 1;
3597 mb1 = 1;
3598 v = 0;
3599 if ((mode == 0xFF) && mask) {
3600 t = mask & 0xF0;
3601 if (t) {
3602 mb1 = 0;
3603 adv |= t^0xF0;
3604 }
3605 v |= (value & 0xF0) | adv;
3606
3607 t = mask & 0x0F;
3608 if (t) {
3609 mb = 0;
3610 adv |= t^0x0F;
3611 }
3612 v |= (value & 0x0F) | adv;
3613 }
3614
3615 target[i] = (mb << SECTION_FIRSTBYTE_MASKLOW) |
3616 (mb1 << SECTION_FIRSTBYTE_MASKHIGH) |
3617 (0 << SECTION_FIRSTBYTE_DISABLE_PID_CHECK) |
3618 (cid << SECTION_FIRSTBYTE_PID_INDEX) | v;
3619 advance[i] = adv;
3620 } else {
3621 if (i < 3) {
3622 value = 0;
3623 mask = 0;
3624 mode = 0xff;
3625 }
3626 mb = 1;
3627 nb = 0;
3628 v = 0;
3629
3630 if ((i >= 3) && mask) {
3631 if (mode == 0xFF) {
3632 mb = 0;
3633 nb = 0;
3634 adv = mask ^ 0xFF;
3635 v = value | adv;
3636 } else {
3637 if (neq_bytes == 1) {
3638 mb = 0;
3639 nb = 1;
3640 adv = mask ^ 0xFF;
3641 v = value & ~adv;
3642 }
3643 }
3644 }
3645 target[i] = (mb << SECTION_RESTBYTE_MASK) |
3646 (nb << SECTION_RESTBYTE_MASK_EQ) |
3647 (0 << SECTION_RESTBYTE_DISABLE_PID_CHECK) |
3648 (cid << SECTION_RESTBYTE_PID_INDEX) | v;
3649 advance[i] = adv;
3650 }
3651
3652 f->value[i] = value;
3653 f->maskandmode[i] = mask & mode;
3654 f->maskandnotmode[i] = mask & ~mode;
3655
3656 if (f->maskandnotmode[i])
3657 f->neq = 1;
3658 }
3659
3660 return 0;
3661 }
3662
3663 /*Set the filter registers*/
dmx_set_filter_regs(struct aml_dmx * dmx,int fid)3664 static int dmx_set_filter_regs(struct aml_dmx *dmx, int fid)
3665 {
3666 u32 t1[FILTER_LEN], t2[FILTER_LEN];
3667 u8 advance1[FILTER_LEN], advance2[FILTER_LEN];
3668 u32 addr, data, max, adv;
3669 int i;
3670
3671 pr_dbg("set filter (id:%d) registers\n", fid);
3672
3673 if (fid & 1) {
3674 dmx_get_filter_target(dmx, fid - 1, t1, advance1);
3675 dmx_get_filter_target(dmx, fid, t2, advance2);
3676 } else {
3677 dmx_get_filter_target(dmx, fid, t1, advance1);
3678 dmx_get_filter_target(dmx, fid + 1, t2, advance2);
3679 }
3680
3681 for (i = 0; i < FILTER_LEN; i++) {
3682 while (DMX_READ_REG(dmx->id, FM_WR_ADDR) & 0x8000)
3683 udelay(1);
3684
3685 data = (t1[i] << 16) | t2[i];
3686 addr = (fid >> 1) | ((i + 1) << 4);
3687 adv = (advance1[i] << 8) | advance2[i];
3688
3689 DMX_WRITE_REG(dmx->id, FM_WR_DATA, data);
3690 DMX_WRITE_REG(dmx->id, FM_WR_ADDR, (adv << 16) | 0x8000 | addr);
3691
3692 pr_dbg("write fm %x:%x\n", (adv << 16) | 0x8000 | addr, data);
3693 }
3694
3695 for (max = FILTER_COUNT - 1; max > 0; max--) {
3696 if (dmx->filter[max].used)
3697 break;
3698 }
3699
3700 data = DMX_READ_REG(dmx->id, MAX_FM_COMP_ADDR) & 0xF;
3701 DMX_WRITE_REG(dmx->id, MAX_FM_COMP_ADDR, data | ((max >> 1) << 4));
3702
3703 pr_dbg("write fm comp %x\n", data | ((max >> 1) << 4));
3704
3705 if (DMX_READ_REG(dmx->id, OM_CMD_STATUS) & 0x8e00) {
3706 pr_error("error send cmd %x\n",
3707 DMX_READ_REG(dmx->id, OM_CMD_STATUS));
3708 }
3709
3710 return 0;
3711 }
3712
3713 /*Clear the filter's buffer*/
dmx_clear_filter_buffer(struct aml_dmx * dmx,int fid)3714 static void dmx_clear_filter_buffer(struct aml_dmx *dmx, int fid)
3715 {
3716 u32 section_busy32 = DMX_READ_REG(dmx->id, SEC_BUFF_READY);
3717 u32 filter_number;
3718 int i;
3719
3720 if (!section_busy32)
3721 return;
3722
3723 for (i = 0; i < SEC_BUF_COUNT; i++) {
3724 if (section_busy32 & (1 << i)) {
3725 DMX_WRITE_REG(dmx->id, SEC_BUFF_NUMBER, i);
3726 filter_number =
3727 (DMX_READ_REG(dmx->id, SEC_BUFF_NUMBER) >> 8);
3728 if (filter_number != fid)
3729 section_busy32 &= ~(1 << i);
3730 }
3731 }
3732
3733 if (section_busy32)
3734 DMX_WRITE_REG(dmx->id, SEC_BUFF_READY, section_busy32);
3735 }
3736
async_fifo_set_regs(struct aml_asyncfifo * afifo,int source_val)3737 static void async_fifo_set_regs(struct aml_asyncfifo *afifo, int source_val)
3738 {
3739 u32 start_addr = (afifo->secure_enable && afifo->blk.addr) ? afifo->blk.addr :
3740 virt_to_phys((void *)afifo->pages);
3741 u32 size = afifo->buf_len;
3742 u32 flush_size = afifo->flush_size;
3743 int factor = dmx_get_order(size / flush_size);
3744 u32 old_start_addr, old_size, new_size, old_factor, new_factor;
3745
3746 int old_src, old_en;
3747
3748 old_en = READ_ASYNC_FIFO_REG(afifo->id, REG2) & (1 << ASYNC_FIFO_FILL_EN);
3749 old_src = (READ_ASYNC_FIFO_REG(afifo->id, REG2) >> ASYNC_FIFO_SOURCE_LSB) & 3;
3750
3751 old_start_addr = READ_ASYNC_FIFO_REG(afifo->id, REG0);
3752
3753 new_size = (size >> 7) & 0x7fff;
3754 old_size = (READ_ASYNC_FIFO_REG(afifo->id, REG1) >> ASYNC_FIFO_FLUSH_CNT_LSB) & 0x7fff;
3755
3756 old_factor = (READ_ASYNC_FIFO_REG(afifo->id, REG3) >> ASYNC_FLUSH_SIZE_IRQ_LSB) & 0x7fff;
3757 new_factor = ((size >> (factor + 7)) - 1) & 0x7fff;
3758
3759 pr_error("async_fifo_set_regs old_src=0x%x source_val=0x%x new_size=0x%x old_size=0x%x old_factor=0x%x new_factor=0x%x old_start_addr=0x%x start_addr=0x%x\n", old_src, source_val, new_size, old_size, old_factor , new_factor,old_start_addr, start_addr);
3760 if (old_en && (old_src == source_val) && (new_size == old_size) && (old_factor == new_factor) && (old_start_addr == start_addr))
3761 return;
3762
3763 pr_error("ASYNC FIFO id=%d, link to DMX%d, start_addr %x, buf_size %d,"
3764 "source value 0x%x, factor %d\n",
3765 afifo->id, afifo->source, start_addr, size, source_val, factor);
3766 /* Destination address */
3767 WRITE_ASYNC_FIFO_REG(afifo->id, REG0, start_addr);
3768
3769 /* Setup flush parameters */
3770 WRITE_ASYNC_FIFO_REG(afifo->id, REG1,
3771 (0 << ASYNC_FIFO_TO_HIU) |
3772 (0 << ASYNC_FIFO_FLUSH) |
3773 /* don't flush the path */
3774 (1 << ASYNC_FIFO_RESET) |
3775 /* reset the path */
3776 (1 << ASYNC_FIFO_WRAP_EN) |
3777 /* wrap enable */
3778 (0 << ASYNC_FIFO_FLUSH_EN) |
3779 /* disable the flush path */
3780 /*(0x3 << ASYNC_FIFO_FLUSH_CNT_LSB);
3781 * flush 3 x 32 32-bit words
3782 */
3783 /*(0x7fff << ASYNC_FIFO_FLUSH_CNT_LSB);
3784 * flush 4MBytes of data
3785 */
3786 (((size >> 7) & 0x7fff) << ASYNC_FIFO_FLUSH_CNT_LSB));
3787 /* number of 128-byte blocks to flush */
3788
3789 /* clear the reset signal */
3790 WRITE_ASYNC_FIFO_REG(afifo->id, REG1,
3791 READ_ASYNC_FIFO_REG(afifo->id,
3792 REG1) & ~(1 << ASYNC_FIFO_RESET));
3793 /* Enable flush */
3794 WRITE_ASYNC_FIFO_REG(afifo->id, REG1,
3795 READ_ASYNC_FIFO_REG(afifo->id,
3796 REG1) | (1 << ASYNC_FIFO_FLUSH_EN));
3797
3798 /*Setup Fill parameters */
3799 WRITE_ASYNC_FIFO_REG(afifo->id, REG2,
3800 (1 << ASYNC_FIFO_ENDIAN_LSB) |
3801 (0 << ASYNC_FIFO_FILL_EN) |
3802 /* disable fill path to reset fill path */
3803 /*(96 << ASYNC_FIFO_FILL_CNT_LSB);
3804 *3 x 32 32-bit words
3805 */
3806 (0 << ASYNC_FIFO_FILL_CNT_LSB));
3807 /* forever FILL; */
3808 WRITE_ASYNC_FIFO_REG(afifo->id, REG2,
3809 READ_ASYNC_FIFO_REG(afifo->id, REG2) |
3810 (1 << ASYNC_FIFO_FILL_EN));/*Enable fill path*/
3811
3812 /* generate flush interrupt */
3813 WRITE_ASYNC_FIFO_REG(afifo->id, REG3,
3814 (READ_ASYNC_FIFO_REG(afifo->id, REG3) & 0xffff0000) |
3815 ((((size >> (factor + 7)) - 1) & 0x7fff) <<
3816 ASYNC_FLUSH_SIZE_IRQ_LSB));
3817
3818 /* Connect the STB DEMUX to ASYNC_FIFO */
3819 WRITE_ASYNC_FIFO_REG(afifo->id, REG2,
3820 READ_ASYNC_FIFO_REG(afifo->id, REG2) |
3821 (source_val << ASYNC_FIFO_SOURCE_LSB));
3822 }
3823
3824 /*Reset the ASYNC FIFOS when a ASYNC FIFO connect to a different DMX*/
reset_async_fifos(struct aml_dvb * dvb)3825 static void reset_async_fifos(struct aml_dvb *dvb)
3826 {
3827 struct aml_asyncfifo *low_dmx_fifo = NULL;
3828 struct aml_asyncfifo *high_dmx_fifo = NULL;
3829 struct aml_asyncfifo *highest_dmx_fifo = NULL;
3830 int i, j;
3831 int record_enable;
3832
3833
3834 for (j = 0; j < DMX_DEV_COUNT; j++) {
3835 if (!dvb->dmx[j].init)
3836 continue;
3837 record_enable = 0;
3838 for (i = 0; i < dvb->async_fifo_total_count; i++) {
3839 if (!dvb->asyncfifo[i].init)
3840 continue;
3841
3842 if (dvb->dmx[j].record
3843 && dvb->dmx[j].id == dvb->asyncfifo[i].source) {
3844 /*This dmx is linked to the async fifo,
3845 *Enable the TS_RECORDER_ENABLE
3846 */
3847 record_enable = 1;
3848 if (!low_dmx_fifo) {
3849 low_dmx_fifo = &dvb->asyncfifo[i];
3850 } else if (low_dmx_fifo->source >
3851 dvb->asyncfifo[i].source) {
3852 if (!high_dmx_fifo)
3853 high_dmx_fifo = low_dmx_fifo;
3854 else {
3855 highest_dmx_fifo = high_dmx_fifo;
3856 high_dmx_fifo = low_dmx_fifo;
3857 }
3858 low_dmx_fifo = &dvb->asyncfifo[i];
3859 } else if (low_dmx_fifo->source <
3860 dvb->asyncfifo[i].source) {
3861 if (!high_dmx_fifo)
3862 high_dmx_fifo = &dvb->asyncfifo[i];
3863 else {
3864 if (high_dmx_fifo->source > dvb->asyncfifo[i].source) {
3865 highest_dmx_fifo = high_dmx_fifo;
3866 high_dmx_fifo = &dvb->asyncfifo[i];
3867 } else {
3868 highest_dmx_fifo = &dvb->asyncfifo[i];
3869 }
3870 }
3871 }
3872
3873 break;
3874 }
3875 }
3876 pr_error("Set DMX%d TS_RECORDER_ENABLE to %d\n", dvb->dmx[j].id,
3877 record_enable ? 1 : 0);
3878 if (record_enable) {
3879 int old_en = DMX_READ_REG(dvb->dmx[j].id, DEMUX_CONTROL) & (1 << TS_RECORDER_ENABLE);
3880
3881 if (!old_en) {
3882 DMX_WRITE_REG(dvb->dmx[j].id, DEMUX_CONTROL,
3883 DMX_READ_REG(dvb->dmx[j].id, DEMUX_CONTROL) |
3884 (1 << TS_RECORDER_ENABLE));
3885 }
3886 } else {
3887 int old_en = DMX_READ_REG(dvb->dmx[j].id, DEMUX_CONTROL) & (1 << TS_RECORDER_ENABLE);
3888
3889 if (old_en) {
3890 DMX_WRITE_REG(dvb->dmx[j].id, DEMUX_CONTROL,
3891 DMX_READ_REG(dvb->dmx[j].id, DEMUX_CONTROL) &
3892 (~(1 << TS_RECORDER_ENABLE)));
3893 }
3894 }
3895 }
3896 pr_error("reset ASYNC FIFOs\n");
3897 for (i = 0; i < dvb->async_fifo_total_count; i++) {
3898 struct aml_asyncfifo *afifo = &dvb->asyncfifo[i];
3899 int old;
3900
3901 if (!dvb->asyncfifo[i].init)
3902 continue;
3903
3904 old = READ_ASYNC_FIFO_REG(afifo->id, REG2) & (1 << ASYNC_FIFO_FILL_EN);
3905
3906 if (old && (afifo != low_dmx_fifo) && (afifo != high_dmx_fifo) && (afifo != highest_dmx_fifo)) {
3907 pr_error("Disable ASYNC FIFO id=%d\n", dvb->asyncfifo[i].id);
3908 CLEAR_ASYNC_FIFO_REG_MASK(dvb->asyncfifo[i].id, REG1,
3909 1 << ASYNC_FIFO_FLUSH_EN);
3910 CLEAR_ASYNC_FIFO_REG_MASK(dvb->asyncfifo[i].id, REG2,
3911 1 << ASYNC_FIFO_FILL_EN);
3912 if (READ_ASYNC_FIFO_REG(dvb->asyncfifo[i].id, REG2) &
3913 (1 << ASYNC_FIFO_FILL_EN) ||
3914 READ_ASYNC_FIFO_REG(dvb->asyncfifo[i].id, REG1) &
3915 (1 << ASYNC_FIFO_FLUSH_EN)) {
3916 pr_error("Set reg failed\n");
3917 } else
3918 pr_error("Set reg ok\n");
3919 dvb->asyncfifo[i].buf_toggle = 0;
3920 dvb->asyncfifo[i].buf_read = 0;
3921 }
3922 }
3923
3924 /*Set the async fifo regs */
3925 if (low_dmx_fifo) {
3926 async_fifo_set_regs(low_dmx_fifo, 0x3);
3927
3928 if (high_dmx_fifo) {
3929 async_fifo_set_regs(high_dmx_fifo, 0x2);
3930
3931 if (highest_dmx_fifo)
3932 async_fifo_set_regs(highest_dmx_fifo, 0x0);
3933 }
3934 }
3935 }
3936
3937 /*Reset the demux device*/
dmx_reset_hw(struct aml_dvb * dvb)3938 void dmx_reset_hw(struct aml_dvb *dvb)
3939 {
3940 dmx_reset_hw_ex(dvb, 1);
3941 }
3942
3943 /*Reset the demux device*/
dmx_reset_hw_ex(struct aml_dvb * dvb,int reset_irq)3944 void dmx_reset_hw_ex(struct aml_dvb *dvb, int reset_irq)
3945 {
3946 int id, times;
3947 u32 pcr_num[DMX_DEV_COUNT];
3948 u32 pcr_reg[DMX_DEV_COUNT];
3949
3950 pr_dbg("[dmx_kpi] demux reset begin\n");
3951
3952 for (id = 0; id < DMX_DEV_COUNT; id++) {
3953 if (!dvb->dmx[id].init)
3954 continue;
3955 pcr_reg[id] = DMX_READ_REG(id, PCR90K_CTL);
3956 pcr_num[id] = DMX_READ_REG(id, ASSIGN_PID_NUMBER);
3957 pr_dbg("reset demux, pcr_regs[%d]:0x%x, pcr_num[%d]:0x%x\n", id, pcr_reg[id], id, pcr_num[id]);
3958 if (reset_irq) {
3959 if (dvb->dmx[id].dmx_irq != -1)
3960 disable_irq(dvb->dmx[id].dmx_irq);
3961 if (dvb->dmx[id].dvr_irq != -1)
3962 disable_irq(dvb->dmx[id].dvr_irq);
3963 }
3964 }
3965 #ifdef ENABLE_SEC_BUFF_WATCHDOG
3966 if (reset_irq)
3967 del_timer_sync(&dvb->watchdog_timer);
3968 #endif
3969 /*RESET_TOP will clear the dsc pid , save all dsc pid that setting in TA*/
3970 for (id = 0; id < DSC_DEV_COUNT; id++) {
3971 struct aml_dsc *dsc = &dvb->dsc[id];
3972 int n;
3973
3974 for (n = 0; n < DSC_COUNT; n++) {
3975 struct aml_dsc_channel *ch = &dsc->channel[n];
3976 /*if(ch->used)*/
3977 {
3978 ch->id = n;
3979 dsc_get_pid(ch,&ch->pid);
3980 }
3981 }
3982 }
3983 /*WRITE_MPEG_REG(RESET1_REGISTER, RESET_DEMUXSTB);*/
3984 WRITE_MPEG_REG(RESET3_REGISTER, RESET_DEMUX2|RESET_DEMUX1|RESET_DEMUX0|RESET_S2P1|RESET_S2P0|RESET_TOP);
3985
3986 for (id = 0; id < DMX_DEV_COUNT; id++) {
3987 times = 0;
3988 while (times++ < 1000000) {
3989 if (!(DMX_READ_REG(id, OM_CMD_STATUS) & 0x01))
3990 break;
3991 }
3992 }
3993 {
3994 u32 data;
3995 data = READ_MPEG_REG(STB_TOP_CONFIG);
3996 ciplus = 0x7C000000 & data;
3997 }
3998
3999 WRITE_MPEG_REG(STB_TOP_CONFIG, 0);
4000 WRITE_MPEG_REG(STB_S2P2_CONFIG, 0);
4001
4002 for (id = 0; id < DMX_DEV_COUNT; id++) {
4003 u32 version, data;
4004
4005 if (!dvb->dmx[id].init)
4006 continue;
4007
4008 if (reset_irq) {
4009 if (dvb->dmx[id].dmx_irq != -1)
4010 enable_irq(dvb->dmx[id].dmx_irq);
4011 if (dvb->dmx[id].dvr_irq != -1)
4012 enable_irq(dvb->dmx[id].dvr_irq);
4013 }
4014 DMX_WRITE_REG(id, DEMUX_CONTROL, 0x0000);
4015 version = DMX_READ_REG(id, STB_VERSION);
4016 DMX_WRITE_REG(id, STB_TEST_REG, version);
4017 pr_dbg("STB %d hardware version : %d\n", id, version);
4018 DMX_WRITE_REG(id, STB_TEST_REG, 0x5550);
4019 data = DMX_READ_REG(id, STB_TEST_REG);
4020 if (data != 0x5550)
4021 pr_error("STB %d register access failed\n", id);
4022 DMX_WRITE_REG(id, STB_TEST_REG, 0xaaa0);
4023 data = DMX_READ_REG(id, STB_TEST_REG);
4024 if (data != 0xaaa0)
4025 pr_error("STB %d register access failed\n", id);
4026 DMX_WRITE_REG(id, MAX_FM_COMP_ADDR, 0x0000);
4027 DMX_WRITE_REG(id, STB_INT_MASK, 0);
4028 DMX_WRITE_REG(id, STB_INT_STATUS, 0xffff);
4029 DMX_WRITE_REG(id, FEC_INPUT_CONTROL, 0);
4030 }
4031
4032 stb_enable(dvb);
4033
4034 for (id = 0; id < DMX_DEV_COUNT; id++) {
4035 struct aml_dmx *dmx = &dvb->dmx[id];
4036 int n;
4037 unsigned long addr;
4038 unsigned long base;
4039 unsigned long grp_addr[SEC_BUF_GRP_COUNT];
4040 int grp_len[SEC_BUF_GRP_COUNT];
4041
4042 if (!dvb->dmx[id].init)
4043 continue;
4044
4045 if (dmx->sec_pages) {
4046 grp_len[0] = (1 << SEC_GRP_LEN_0) * 8;
4047 grp_len[1] = (1 << SEC_GRP_LEN_1) * 8;
4048 grp_len[2] = (1 << SEC_GRP_LEN_2) * 8;
4049 grp_len[3] = (1 << SEC_GRP_LEN_3) * 8;
4050
4051 grp_addr[0] = virt_to_phys((void *)dmx->sec_pages);
4052 grp_addr[1] = grp_addr[0] + grp_len[0];
4053 grp_addr[2] = grp_addr[1] + grp_len[1];
4054 grp_addr[3] = grp_addr[2] + grp_len[2];
4055
4056 base = grp_addr[0] & 0xFFFF0000;
4057 DMX_WRITE_REG(dmx->id, SEC_BUFF_BASE, base >> 16);
4058 DMX_WRITE_REG(dmx->id, SEC_BUFF_01_START,
4059 (((grp_addr[0] - base) >> 8) << 16) |
4060 ((grp_addr[1] - base) >> 8));
4061 DMX_WRITE_REG(dmx->id, SEC_BUFF_23_START,
4062 (((grp_addr[2] - base) >> 8) << 16) |
4063 ((grp_addr[3] - base) >> 8));
4064 DMX_WRITE_REG(dmx->id, SEC_BUFF_SIZE,
4065 SEC_GRP_LEN_0 |
4066 (SEC_GRP_LEN_1 << 4) |
4067 (SEC_GRP_LEN_2 << 8) |
4068 (SEC_GRP_LEN_3 << 12));
4069 }
4070 #ifdef NO_SUB
4071 #ifndef SUB_PARSER
4072 if (dmx->sub_pages) {
4073 addr = virt_to_phys((void *)dmx->sub_pages);
4074 DMX_WRITE_REG(dmx->id, SB_START, addr >> 12);
4075 DMX_WRITE_REG(dmx->id, SB_LAST_ADDR,
4076 (dmx->sub_buf_len >> 3) - 1);
4077 }
4078 #endif
4079 #endif
4080 if (dmx->pes_pages) {
4081 addr = virt_to_phys((void *)dmx->pes_pages);
4082 DMX_WRITE_REG(dmx->id, OB_START, addr >> 12);
4083 DMX_WRITE_REG(dmx->id, OB_LAST_ADDR,
4084 (dmx->pes_buf_len >> 3) - 1);
4085 }
4086
4087 for (n = 0; n < CHANNEL_COUNT; n++) {
4088 /*struct aml_channel *chan = &dmx->channel[n];*/
4089
4090 /*if (chan->used)*/
4091 {
4092 #ifdef NO_SUB
4093 #ifdef SUB_PARSER
4094 /*
4095 check if subtitle channel was running,
4096 the parser will be used in amstream also,
4097 take care of the buff ptr.
4098 */
4099 u32 v = dmx_get_chan_target(dmx, n);
4100 if (v != 0xFFFF &&
4101 (v & (0x7 << PID_TYPE))
4102 == (SUB_PACKET << PID_TYPE))
4103 set_subtitle_pes_buffer(dmx);
4104 #endif
4105 #endif
4106 {
4107 u32 v = dmx_get_chan_target(dmx, n);
4108 if (v != 0xFFFF &&
4109 (v & (0x7 << PID_TYPE))
4110 ==
4111 (OTHER_PES_PACKET << PID_TYPE))
4112 pes_off_pre[dmx->id] = 0;
4113 }
4114 dmx_set_chan_regs(dmx, n);
4115 }
4116 }
4117
4118 for (n = 0; n < FILTER_COUNT; n++) {
4119 struct aml_filter *filter = &dmx->filter[n];
4120
4121 if (filter->used)
4122 dmx_set_filter_regs(dmx, n);
4123 }
4124 dmx_enable(&dvb->dmx[id]);
4125 dmx_smallsec_set(&dmx->smallsec,
4126 dmx->smallsec.enable,
4127 dmx->smallsec.bufsize,
4128 1);
4129
4130 dmx_timeout_set(&dmx->timeout,
4131 dmx->timeout.enable,
4132 dmx->timeout.timeout,
4133 dmx->timeout.ch_disable,
4134 dmx->timeout.match,
4135 1);
4136 DMX_WRITE_REG(id, ASSIGN_PID_NUMBER, pcr_num[id]);
4137 DMX_WRITE_REG(id, PCR90K_CTL, pcr_reg[id]);
4138 }
4139
4140 for (id = 0; id < DSC_DEV_COUNT; id++) {
4141 struct aml_dsc *dsc = &dvb->dsc[id];
4142 int n;
4143
4144 for (n = 0; n < DSC_COUNT; n++) {
4145 int flag = 0;
4146 struct aml_dsc_channel *ch = &dsc->channel[n];
4147 /*if(ch->used)*/
4148 {
4149 ch->work_mode = -1;
4150 //if ta setting pid, used will 0
4151 if (ch->pid != 0x1fff && !ch->used) {
4152 flag = 1;
4153 ch->used = 1;
4154 }
4155 dsc_set_pid(ch, ch->pid);
4156 if (flag)
4157 ch->used = 0;
4158 //dsc_set_keys(ch);
4159 }
4160 }
4161 }
4162 #ifdef ENABLE_SEC_BUFF_WATCHDOG
4163 if (reset_irq) {
4164 mod_timer(&dvb->watchdog_timer,
4165 jiffies + msecs_to_jiffies(WATCHDOG_TIMER));
4166 }
4167 #endif
4168
4169 pr_dbg("[dmx_kpi] demux reset end\n");
4170 }
4171
4172 /*Reset the individual demux*/
dmx_reset_dmx_hw_ex_unlock(struct aml_dvb * dvb,struct aml_dmx * dmx,int reset_irq)4173 void dmx_reset_dmx_hw_ex_unlock(struct aml_dvb *dvb, struct aml_dmx *dmx,
4174 int reset_irq)
4175 {
4176 u32 pcr_num = 0;
4177 u32 pcr_regs = 0;
4178 {
4179 if (!dmx->init)
4180 return;
4181 pcr_regs = DMX_READ_REG(dmx->id, PCR90K_CTL);
4182 pcr_num = DMX_READ_REG(dmx->id, ASSIGN_PID_NUMBER);
4183 pr_dbg("reset demux, pcr_regs:0x%x, pcr_num:0x%x\n", pcr_regs, pcr_num);
4184 }
4185 {
4186 if (!dmx->init)
4187 return;
4188 if (reset_irq) {
4189 if (dmx->dmx_irq != -1)
4190 disable_irq(dmx->dmx_irq);
4191 if (dmx->dvr_irq != -1)
4192 disable_irq(dmx->dvr_irq);
4193 }
4194 }
4195 #ifdef ENABLE_SEC_BUFF_WATCHDOG
4196 if (reset_irq) {
4197 /*del_timer_sync(&dvb->watchdog_timer); */
4198 dvb->dmx_watchdog_disable[dmx->id] = 1;
4199 }
4200 #endif
4201 pr_error("dmx_reset_dmx_hw_ex_unlock into\n");
4202 WRITE_MPEG_REG(RESET3_REGISTER,
4203 (dmx->id) ? ((dmx->id ==
4204 1) ? RESET_DEMUX1 : RESET_DEMUX2) :
4205 RESET_DEMUX0);
4206 WRITE_MPEG_REG(RESET3_REGISTER, RESET_DES);
4207
4208 {
4209 int times;
4210
4211 times = 0;
4212 while (times++ < 1000000) {
4213 if (!(DMX_READ_REG(dmx->id, OM_CMD_STATUS) & 0x01))
4214 break;
4215 }
4216 }
4217
4218 /*WRITE_MPEG_REG(STB_TOP_CONFIG, 0); */
4219 {
4220 u32 data;
4221 data = READ_MPEG_REG(STB_TOP_CONFIG);
4222 ciplus = 0x7C000000 & data;
4223 }
4224
4225 {
4226 u32 version, data;
4227
4228 if (!dmx->init)
4229 return;
4230
4231 if (reset_irq) {
4232 if (dmx->dmx_irq != -1)
4233 enable_irq(dmx->dmx_irq);
4234 if (dmx->dvr_irq != -1)
4235 enable_irq(dmx->dvr_irq);
4236 }
4237 DMX_WRITE_REG(dmx->id, DEMUX_CONTROL, 0x0000);
4238 version = DMX_READ_REG(dmx->id, STB_VERSION);
4239 DMX_WRITE_REG(dmx->id, STB_TEST_REG, version);
4240 pr_dbg("STB %d hardware version : %d\n", dmx->id, version);
4241 DMX_WRITE_REG(dmx->id, STB_TEST_REG, 0x5550);
4242 data = DMX_READ_REG(dmx->id, STB_TEST_REG);
4243 if (data != 0x5550)
4244 pr_error("STB %d register access failed\n", dmx->id);
4245 DMX_WRITE_REG(dmx->id, STB_TEST_REG, 0xaaa0);
4246 data = DMX_READ_REG(dmx->id, STB_TEST_REG);
4247 if (data != 0xaaa0)
4248 pr_error("STB %d register access failed\n", dmx->id);
4249 DMX_WRITE_REG(dmx->id, MAX_FM_COMP_ADDR, 0x0000);
4250 DMX_WRITE_REG(dmx->id, STB_INT_MASK, 0);
4251 DMX_WRITE_REG(dmx->id, STB_INT_STATUS, 0xffff);
4252 DMX_WRITE_REG(dmx->id, FEC_INPUT_CONTROL, 0);
4253 }
4254
4255 stb_enable(dvb);
4256
4257 {
4258 int n;
4259 unsigned long addr;
4260 unsigned long base;
4261 unsigned long grp_addr[SEC_BUF_GRP_COUNT];
4262 int grp_len[SEC_BUF_GRP_COUNT];
4263
4264 if (!dmx->init)
4265 return;
4266
4267 if (dmx->sec_pages) {
4268 grp_len[0] = (1 << SEC_GRP_LEN_0) * 8;
4269 grp_len[1] = (1 << SEC_GRP_LEN_1) * 8;
4270 grp_len[2] = (1 << SEC_GRP_LEN_2) * 8;
4271 grp_len[3] = (1 << SEC_GRP_LEN_3) * 8;
4272
4273 grp_addr[0] = virt_to_phys((void *)dmx->sec_pages);
4274 grp_addr[1] = grp_addr[0] + grp_len[0];
4275 grp_addr[2] = grp_addr[1] + grp_len[1];
4276 grp_addr[3] = grp_addr[2] + grp_len[2];
4277
4278 base = grp_addr[0] & 0xFFFF0000;
4279 DMX_WRITE_REG(dmx->id, SEC_BUFF_BASE, base >> 16);
4280 DMX_WRITE_REG(dmx->id, SEC_BUFF_01_START,
4281 (((grp_addr[0] - base) >> 8) << 16) |
4282 ((grp_addr[1] - base) >> 8));
4283 DMX_WRITE_REG(dmx->id, SEC_BUFF_23_START,
4284 (((grp_addr[2] - base) >> 8) << 16) |
4285 ((grp_addr[3] - base) >> 8));
4286 DMX_WRITE_REG(dmx->id, SEC_BUFF_SIZE,
4287 SEC_GRP_LEN_0 |
4288 (SEC_GRP_LEN_1 << 4) |
4289 (SEC_GRP_LEN_2 << 8) |
4290 (SEC_GRP_LEN_3 << 12));
4291 }
4292 #ifdef NO_SUB
4293 #ifndef SUB_PARSER
4294 if (dmx->sub_pages) {
4295 addr = virt_to_phys((void *)dmx->sub_pages);
4296 DMX_WRITE_REG(dmx->id, SB_START, addr >> 12);
4297 DMX_WRITE_REG(dmx->id, SB_LAST_ADDR,
4298 (dmx->sub_buf_len >> 3) - 1);
4299 }
4300 #endif
4301 #endif
4302 if (dmx->pes_pages) {
4303 addr = virt_to_phys((void *)dmx->pes_pages);
4304 DMX_WRITE_REG(dmx->id, OB_START, addr >> 12);
4305 DMX_WRITE_REG(dmx->id, OB_LAST_ADDR,
4306 (dmx->pes_buf_len >> 3) - 1);
4307 }
4308
4309 for (n = 0; n < CHANNEL_COUNT; n++) {
4310 /*struct aml_channel *chan = &dmx->channel[n];*/
4311
4312 /*if (chan->used)*/
4313 {
4314 #ifdef NO_SUB
4315 #ifdef SUB_PARSER
4316 /*
4317 check if subtitle channel was running,
4318 the parser will be used in amstream also,
4319 take care of the buff ptr.
4320 */
4321 u32 v = dmx_get_chan_target(dmx, n);
4322 if (v != 0xFFFF &&
4323 (v & (0x7 << PID_TYPE))
4324 == (SUB_PACKET << PID_TYPE))
4325 set_subtitle_pes_buffer(dmx);
4326 #endif
4327 #endif
4328 {
4329 u32 v = dmx_get_chan_target(dmx, n);
4330 if (v != 0xFFFF &&
4331 (v & (0x7 << PID_TYPE))
4332 ==
4333 (OTHER_PES_PACKET << PID_TYPE))
4334 pes_off_pre[dmx->id] = 0;
4335 }
4336 dmx_set_chan_regs(dmx, n);
4337 }
4338 }
4339
4340 for (n = 0; n < FILTER_COUNT; n++) {
4341 struct aml_filter *filter = &dmx->filter[n];
4342
4343 if (filter->used)
4344 dmx_set_filter_regs(dmx, n);
4345 }
4346
4347 for (n = 0; n < SEC_CNT_MAX; n++) {
4348 dmx->sec_cnt[n] = 0;
4349 dmx->sec_cnt_match[n] = 0;
4350 dmx->sec_cnt_crc_fail[n] = 0;
4351 }
4352 dmx_enable(dmx);
4353 dmx_smallsec_set(&dmx->smallsec,
4354 dmx->smallsec.enable,
4355 dmx->smallsec.bufsize,
4356 1);
4357
4358 dmx_timeout_set(&dmx->timeout,
4359 dmx->timeout.enable,
4360 dmx->timeout.timeout,
4361 dmx->timeout.ch_disable,
4362 dmx->timeout.match,
4363 1);
4364 }
4365
4366 {
4367 int id;
4368
4369 for (id = 0; id < DSC_DEV_COUNT; id++) {
4370 struct aml_dsc *dsc = &dvb->dsc[id];
4371 int n;
4372
4373 for (n = 0; n < DSC_COUNT; n++) {
4374 int flag = 0;
4375 struct aml_dsc_channel *ch = &dsc->channel[n];
4376 /*if(ch->used)*/ {
4377 ch->id = n;
4378 ch->work_mode = -1;
4379 dsc_get_pid(ch,&ch->pid);
4380 if (ch->pid != 0x1fff && !ch->used) {
4381 flag = 1;
4382 ch->used = 1;
4383 }
4384 dsc_set_pid(ch, ch->pid);
4385 if (flag)
4386 ch->used = 0;
4387 //dsc_set_keys(ch);
4388 }
4389 }
4390 }
4391 }
4392 #ifdef ENABLE_SEC_BUFF_WATCHDOG
4393 if (reset_irq) {
4394 /*mod_timer(&dvb->watchdog_timer,
4395 *jiffies+msecs_to_jiffies(WATCHDOG_TIMER));
4396 */
4397 dvb->dmx_watchdog_disable[dmx->id] = 0;
4398 }
4399 #endif
4400 {
4401 DMX_WRITE_REG(dmx->id, ASSIGN_PID_NUMBER, pcr_num);
4402 DMX_WRITE_REG(dmx->id, PCR90K_CTL, pcr_regs);
4403 }
4404 }
4405
dmx_reset_dmx_id_hw_ex_unlock(struct aml_dvb * dvb,int id,int reset_irq)4406 void dmx_reset_dmx_id_hw_ex_unlock(struct aml_dvb *dvb, int id, int reset_irq)
4407 {
4408 dmx_reset_dmx_hw_ex_unlock(dvb, &dvb->dmx[id], reset_irq);
4409 }
4410
dmx_reset_dmx_hw_ex(struct aml_dvb * dvb,struct aml_dmx * dmx,int reset_irq)4411 void dmx_reset_dmx_hw_ex(struct aml_dvb *dvb, struct aml_dmx *dmx,
4412 int reset_irq)
4413 {
4414 unsigned long flags;
4415 spin_lock_irqsave(&dvb->slock, flags);
4416 dmx_reset_dmx_hw_ex_unlock(dvb, dmx, reset_irq);
4417 spin_unlock_irqrestore(&dvb->slock, flags);
4418 }
4419
dmx_reset_dmx_id_hw_ex(struct aml_dvb * dvb,int id,int reset_irq)4420 void dmx_reset_dmx_id_hw_ex(struct aml_dvb *dvb, int id, int reset_irq)
4421 {
4422 unsigned long flags;
4423
4424 spin_lock_irqsave(&dvb->slock, flags);
4425 dmx_reset_dmx_id_hw_ex_unlock(dvb, id, reset_irq);
4426 spin_unlock_irqrestore(&dvb->slock, flags);
4427 }
4428
dmx_reset_dmx_hw(struct aml_dvb * dvb,int id)4429 void dmx_reset_dmx_hw(struct aml_dvb *dvb, int id)
4430 {
4431 dmx_reset_dmx_id_hw_ex(dvb, id, 1);
4432 }
4433
4434 /*Allocate subtitle pes buffer*/
4435 #if 0
4436 static int alloc_subtitle_pes_buffer(struct aml_dmx *dmx)
4437 {
4438 int start_ptr = 0;
4439 struct stream_buf_s *sbuff = 0;
4440 u32 phy_addr;
4441
4442 start_ptr = READ_MPEG_REG(PARSER_SUB_START_PTR);
4443 if (start_ptr) {
4444 WRITE_MPEG_REG(PARSER_SUB_RP, start_ptr);
4445 goto exit;
4446 }
4447 sbuff = get_stream_buffer(BUF_TYPE_SUBTITLE);
4448 if (sbuff) {
4449 if (sbuff->flag & BUF_FLAG_IOMEM)
4450 phy_addr = sbuff->buf_start;
4451 else
4452 phy_addr = virt_to_phys((void *)sbuff->buf_start);
4453
4454 WRITE_MPEG_REG(PARSER_SUB_RP, phy_addr);
4455 WRITE_MPEG_REG(PARSER_SUB_START_PTR, phy_addr);
4456 WRITE_MPEG_REG(PARSER_SUB_END_PTR,
4457 phy_addr + sbuff->buf_size - 8);
4458
4459 pr_dbg("pes buff=:%x %x\n", phy_addr, sbuff->buf_size);
4460 } else
4461 pr_dbg("Error stream buffer\n");
4462 exit:
4463 return 0;
4464 }
4465 #endif
4466
set_subtitle_pes_buffer(struct aml_dmx * dmx)4467 static int set_subtitle_pes_buffer(struct aml_dmx *dmx)
4468 {
4469 #ifdef SUB_PARSER
4470 if (dmx->sub_chan == -1) {
4471 unsigned long addr = virt_to_phys((void *)dmx->sub_pages);
4472 WRITE_MPEG_REG(PARSER_SUB_RP, addr);
4473 WRITE_MPEG_REG(PARSER_SUB_START_PTR, addr);
4474 WRITE_MPEG_REG(PARSER_SUB_END_PTR, addr + dmx->sub_buf_len - 8);
4475 pr_inf("set sub buff: (%d) %lx %x\n", dmx->id, addr, dmx->sub_buf_len);
4476 }
4477 #endif
4478 return 0;
4479 }
4480
dmx_get_sub_buffer(unsigned long * base,unsigned long * virt)4481 int dmx_get_sub_buffer(unsigned long *base, unsigned long *virt)
4482 {
4483 #ifndef SUB_BUF_DMX
4484 unsigned long s = READ_MPEG_REG(PARSER_SUB_START_PTR);
4485 if (base)
4486 *base = s;
4487 if (virt)
4488 *virt = (unsigned long)codec_mm_phys_to_virt(s);
4489 #endif
4490 return 0;
4491 }
4492
dmx_init_sub_buffer(struct aml_dmx * dmx,unsigned long base,unsigned long virt)4493 int dmx_init_sub_buffer(struct aml_dmx *dmx, unsigned long base, unsigned long virt)
4494 {
4495 #ifndef SUB_BUF_DMX
4496 dmx->sub_buf_base = base;
4497 pr_inf("sub buf base: 0x%lx\n", dmx->sub_buf_base);
4498
4499 dmx->sub_buf_base_virt = (u8 *)virt;
4500 pr_inf("sub buf base virt: 0x%p\n", dmx->sub_buf_base_virt);
4501 #endif
4502 return 0;
4503 }
4504
4505 /*Allocate a new channel*/
dmx_alloc_chan(struct aml_dmx * dmx,int type,int pes_type,int pid)4506 int dmx_alloc_chan(struct aml_dmx *dmx, int type, int pes_type, int pid)
4507 {
4508 int id = -1;
4509 int ret;
4510
4511 if (type == DMX_TYPE_TS) {
4512 switch (pes_type) {
4513 case DMX_PES_VIDEO:
4514 if (!dmx->channel[0].used)
4515 id = 0;
4516 break;
4517 case DMX_PES_AUDIO:
4518 if (!dmx->channel[1].used)
4519 id = 1;
4520 break;
4521 case DMX_PES_SUBTITLE:
4522 case DMX_PES_TELETEXT:
4523 if (!dmx->channel[2].used)
4524 id = 2;
4525 //alloc_subtitle_pes_buffer(dmx);
4526 set_subtitle_pes_buffer(dmx);
4527 break;
4528 case DMX_PES_PCR:
4529 if (!dmx->channel[3].used)
4530 id = 3;
4531 break;
4532 case DMX_PES_AUDIO3:
4533 pes_off_pre[dmx->id] = 0;
4534 case DMX_PES_OTHER:
4535 {
4536 int i;
4537
4538 for (i = SYS_CHAN_COUNT;
4539 i < CHANNEL_COUNT; i++) {
4540 if (!dmx->channel[i].used) {
4541 id = i;
4542 break;
4543 }
4544 }
4545 }
4546 break;
4547 default:
4548 break;
4549 }
4550 } else {
4551 int i;
4552
4553 for (i = SYS_CHAN_COUNT; i < CHANNEL_COUNT; i++) {
4554 if (!dmx->channel[i].used) {
4555 id = i;
4556 break;
4557 }
4558 }
4559 }
4560
4561 if (id == -1) {
4562 pr_error("too many channels\n");
4563 return -1;
4564 }
4565
4566 pr_dbg("allocate channel(id:%d PID:0x%x)\n", id, pid);
4567
4568 if (id <= 3) {
4569 ret = dmx_get_chan(dmx, pid);
4570 if (ret >= 0 && DVR_FEED(dmx->channel[ret].feed)) {
4571 dmx_remove_feed(dmx, dmx->channel[ret].feed);
4572 dmx->channel[id].dvr_feed = dmx->channel[ret].feed;
4573 dmx->channel[id].dvr_feed->priv = (void *)(long)id;
4574 } else {
4575 dmx->channel[id].dvr_feed = NULL;
4576 }
4577 }
4578
4579 dmx->channel[id].type = type;
4580 dmx->channel[id].pes_type = pes_type;
4581 dmx->channel[id].pid = pid;
4582 dmx->channel[id].used = 1;
4583 dmx->channel[id].filter_count = 0;
4584
4585 dmx_set_chan_regs(dmx, id);
4586
4587 set_debug_dmx_chanpids(dmx->id, id, pid);
4588
4589 dmx->chan_count++;
4590 dmx_enable(dmx);
4591
4592 return id;
4593 }
4594
4595 /*Free a channel*/
dmx_free_chan(struct aml_dmx * dmx,int cid)4596 void dmx_free_chan(struct aml_dmx *dmx, int cid)
4597 {
4598 pr_dbg("free channel(id:%d PID:0x%x)\n", cid, dmx->channel[cid].pid);
4599
4600 dmx->channel[cid].used = 0;
4601 dmx->channel[cid].pid = 0x1fff;
4602 dmx_set_chan_regs(dmx, cid);
4603
4604 if (cid == 2) {
4605 u32 parser_sub_start_ptr;
4606
4607 parser_sub_start_ptr = READ_MPEG_REG(PARSER_SUB_START_PTR);
4608 WRITE_MPEG_REG(PARSER_SUB_RP, parser_sub_start_ptr);
4609 WRITE_MPEG_REG(PARSER_SUB_WP, parser_sub_start_ptr);
4610 }
4611
4612 set_debug_dmx_chanpids(dmx->id, cid, -1);
4613 dmx->chan_count--;
4614 dmx_enable(dmx);
4615
4616 /*Special pes type channel, check its dvr feed */
4617 if (cid <= 3 && dmx->channel[cid].dvr_feed) {
4618 /*start the dvr feed */
4619 dmx_add_feed(dmx, dmx->channel[cid].dvr_feed);
4620 }
4621 }
4622
4623 /*Add a section*/
dmx_chan_add_filter(struct aml_dmx * dmx,int cid,struct dvb_demux_filter * filter)4624 static int dmx_chan_add_filter(struct aml_dmx *dmx, int cid,
4625 struct dvb_demux_filter *filter)
4626 {
4627 int id = -1;
4628 int i;
4629
4630 for (i = 0; i < FILTER_COUNT; i++) {
4631 if (!dmx->filter[i].used) {
4632 id = i;
4633 break;
4634 }
4635 }
4636
4637 if (id == -1) {
4638 pr_error("too many filters\n");
4639 return -1;
4640 }
4641
4642 pr_dbg("channel(id:%d PID:0x%x) add filter(id:%d)\n", cid,
4643 filter->feed->pid, id);
4644
4645 dmx->filter[id].chan_id = cid;
4646 dmx->filter[id].used = 1;
4647 dmx->filter[id].filter = (struct dmx_section_filter *)filter;
4648 dmx->channel[cid].filter_count++;
4649
4650 dmx_set_filter_regs(dmx, id);
4651
4652 return id;
4653 }
4654
dmx_remove_filter(struct aml_dmx * dmx,int cid,int fid)4655 static void dmx_remove_filter(struct aml_dmx *dmx, int cid, int fid)
4656 {
4657 pr_dbg("channel(id:%d PID:0x%x) remove filter(id:%d)\n", cid,
4658 dmx->channel[cid].pid, fid);
4659
4660 dmx->filter[fid].used = 0;
4661 dmx->channel[cid].filter_count--;
4662
4663 dmx_set_filter_regs(dmx, fid);
4664 dmx_clear_filter_buffer(dmx, fid);
4665 }
4666
sf_add_feed(struct aml_dmx * src_dmx,struct dvb_demux_feed * feed)4667 static int sf_add_feed(struct aml_dmx *src_dmx, struct dvb_demux_feed *feed)
4668 {
4669 int ret = 0;
4670
4671 struct aml_dvb *dvb = (struct aml_dvb *)src_dmx->demux.priv;
4672 struct aml_swfilter *sf = &dvb->swfilter;
4673
4674 pr_dbg_sf("sf add pid[%d]\n", feed->pid);
4675
4676 /*init sf */
4677 if (!sf->user) {
4678 void *mem;
4679
4680 mem = vmalloc(SF_BUFFER_SIZE);
4681 if (!mem) {
4682 ret = -ENOMEM;
4683 goto fail;
4684 }
4685 dvb_ringbuffer_init(&sf->rbuf, mem, SF_BUFFER_SIZE);
4686
4687 sf->dmx = &dvb->dmx[SF_DMX_ID];
4688 sf->afifo = &dvb->asyncfifo[SF_AFIFO_ID];
4689
4690 sf->dmx->source = src_dmx->source;
4691 sf->afifo->source = sf->dmx->id;
4692 sf->track_dmx = src_dmx->id;
4693 /*sf->afifo->flush_size = 188*10; */
4694
4695 pr_dbg_sf("init sf mode.\n");
4696
4697 } else if (sf->dmx->source != src_dmx->source) {
4698 pr_error(" pid=%d[src:%d] already used with sfdmx%d[src:%d]\n",
4699 feed->pid, src_dmx->source, sf->dmx->id,
4700 sf->dmx->source);
4701 ret = -EBUSY;
4702 goto fail;
4703 }
4704
4705 /*setup feed */
4706 ret = dmx_get_chan(sf->dmx, feed->pid);
4707 if (ret >= 0) {
4708 pr_error(" pid=%d[dmx:%d] already used [dmx:%d].\n",
4709 feed->pid, src_dmx->id,
4710 ((struct aml_dmx *)sf->dmx->channel[ret].feed->
4711 demux)->id);
4712 ret = -EBUSY;
4713 goto fail;
4714 }
4715 ret =
4716 dmx_alloc_chan(sf->dmx, DMX_TYPE_TS, DMX_PES_OTHER,
4717 feed->pid);
4718 if (ret < 0) {
4719 pr_error(" %s: alloc chan error, ret=%d\n", __func__, ret);
4720 ret = -EBUSY;
4721 goto fail;
4722 }
4723 sf->dmx->channel[ret].feed = feed;
4724 feed->priv = (void *)(long)ret;
4725
4726 sf->dmx->channel[ret].dvr_feed = feed;
4727
4728 sf->user++;
4729 debug_sf_user = sf->user;
4730 dmx_enable(sf->dmx);
4731
4732 return 0;
4733
4734 fail:
4735 feed->priv = (void *)-1;
4736 return ret;
4737 }
4738
sf_remove_feed(struct aml_dmx * src_dmx,struct dvb_demux_feed * feed)4739 static int sf_remove_feed(struct aml_dmx *src_dmx, struct dvb_demux_feed *feed)
4740 {
4741 int ret;
4742
4743 struct aml_dvb *dvb = (struct aml_dvb *)src_dmx->demux.priv;
4744 struct aml_swfilter *sf = &dvb->swfilter;
4745
4746 if (!sf->user || (sf->dmx->source != src_dmx->source))
4747 return 0;
4748
4749 /*add fail, no need to remove*/
4750 if (((long)feed->priv) < 0)
4751 return 0;
4752
4753 ret = dmx_get_chan(sf->dmx, feed->pid);
4754 if (ret < 0)
4755 return 0;
4756
4757 pr_dbg_sf("sf remove pid[%d]\n", feed->pid);
4758
4759 dmx_free_chan(sf->dmx, (long)feed->priv);
4760
4761 sf->dmx->channel[ret].feed = NULL;
4762 sf->dmx->channel[ret].dvr_feed = NULL;
4763
4764 sf->user--;
4765 debug_sf_user = sf->user;
4766
4767 if (!sf->user) {
4768 sf->dmx->source = -1;
4769 sf->afifo->source = AM_DMX_MAX;
4770 sf->track_dmx = -1;
4771 /*sf->afifo->flush_size = sf->afifo->buf_len>>1; */
4772
4773 if (sf->rbuf.data) {
4774 void *mem = sf->rbuf.data;
4775
4776 sf->rbuf.data = NULL;
4777 vfree(mem);
4778 }
4779 pr_dbg_sf("exit sf mode.\n");
4780 }
4781
4782 return 0;
4783 }
4784
sf_feed_sf(struct aml_dmx * dmx,struct dvb_demux_feed * feed,int add_not_remove)4785 static int sf_feed_sf(struct aml_dmx *dmx, struct dvb_demux_feed *feed,
4786 int add_not_remove)
4787 {
4788 int sf = 0;
4789
4790 if (sf_dmx_sf(dmx)) {
4791 pr_error("%s: demux %d is in sf mode\n", __func__, dmx->id);
4792 return -EINVAL;
4793 }
4794
4795 switch (feed->type) {
4796 case DMX_TYPE_TS:{
4797 struct dmxdev_filter *dmxdevfilter =
4798 feed->feed.ts.priv;
4799 if (!DVR_FEED(feed)) {
4800 if (dmxdevfilter->params.pes.
4801 flags & DMX_USE_SWFILTER)
4802 sf = 1;
4803 if (force_pes_sf)
4804 sf = 1;
4805 }
4806 }
4807 break;
4808
4809 case DMX_TYPE_SEC:{
4810 struct dvb_demux_filter *filter;
4811
4812 for (filter = feed->filter; filter;
4813 filter = filter->next) {
4814 struct dmxdev_filter *dmxdevfilter =
4815 filter->filter.priv;
4816 if (dmxdevfilter->params.sec.
4817 flags & DMX_USE_SWFILTER)
4818 sf = 1;
4819 if (add_not_remove)
4820 filter->hw_handle = (u16)-1;
4821 }
4822 if (force_sec_sf)
4823 sf = 1;
4824 }
4825 break;
4826 }
4827
4828 return sf ? 0 : 1;
4829 }
4830
sf_check_feed(struct aml_dmx * dmx,struct dvb_demux_feed * feed,int add_not_remove)4831 static int sf_check_feed(struct aml_dmx *dmx, struct dvb_demux_feed *feed,
4832 int add_not_remove)
4833 {
4834 int ret = 0;
4835
4836 ret = sf_feed_sf(dmx, feed, add_not_remove);
4837 if (ret)
4838 return ret;
4839
4840 pr_dbg_sf("%s [pid:%d] %s\n",
4841 (feed->type == DMX_TYPE_TS) ? "DMX_TYPE_TS" : "DMX_TYPE_SEC",
4842 feed->pid, add_not_remove ? "-> sf mode" : "sf mode ->");
4843
4844 if (add_not_remove)
4845 ret = sf_add_feed(dmx, feed);
4846 else
4847 ret = sf_remove_feed(dmx, feed);
4848
4849 if (ret < 0) {
4850 pr_error("sf %s feed fail[%d]\n",
4851 add_not_remove ? "add" : "remove", ret);
4852 }
4853 return ret;
4854 }
4855
dmx_add_feed(struct aml_dmx * dmx,struct dvb_demux_feed * feed)4856 static int dmx_add_feed(struct aml_dmx *dmx, struct dvb_demux_feed *feed)
4857 {
4858 int id, ret = 0;
4859 struct dvb_demux_filter *filter;
4860 struct dvb_demux_feed *dfeed = NULL;
4861 int sf_ret = 0; /*<0:error, =0:sf_on, >0:sf_off */
4862
4863 sf_ret = sf_check_feed(dmx, feed, 1/*SF_FEED_OP_ADD */);
4864 if (sf_ret < 0)
4865 return sf_ret;
4866
4867 switch (feed->type) {
4868 case DMX_TYPE_TS:
4869 pr_dbg("%s: DMX_TYPE_TS\n", __func__);
4870 ret = dmx_get_chan(dmx, feed->pid);
4871 if (ret >= 0) {
4872 if (DVR_FEED(dmx->channel[ret].feed)) {
4873 if (DVR_FEED(feed)) {
4874 /*dvr feed already work */
4875 pr_error("PID %d already used(DVR)\n",
4876 feed->pid);
4877 ret = -EBUSY;
4878 goto fail;
4879 }
4880 if (sf_ret) {
4881 /*if sf_on, we do not reset the
4882 *previous dvr feed, just load the pes
4883 *feed on the sf, a diffrent data path.
4884 */
4885 dfeed = dmx->channel[ret].feed;
4886 dmx_remove_feed(dmx, dfeed);
4887 }
4888 } else {
4889 if (DVR_FEED(feed)
4890 && (!dmx->channel[ret].dvr_feed)) {
4891 /*just store the dvr_feed */
4892 dmx->channel[ret].dvr_feed = feed;
4893 feed->priv = (void *)(long)ret;
4894 if (!dmx->record)
4895 dmx_enable(dmx);
4896 dmx_add_recchan(dmx->id, ret);
4897 return 0;
4898 }
4899 {
4900 pr_error("PID %d already used\n",
4901 feed->pid);
4902 ret = -EBUSY;
4903 goto fail;
4904 }
4905 }
4906 }
4907
4908 if (sf_ret) { /*not sf feed. */
4909 ret =
4910 dmx_alloc_chan(dmx, feed->type,
4911 feed->pes_type, feed->pid);
4912 if (ret < 0) {
4913 pr_dbg("%s: alloc chan error, ret=%d\n",
4914 __func__, ret);
4915 ret = -EBUSY;
4916 goto fail;
4917 }
4918 dmx->channel[ret].feed = feed;
4919 feed->priv = (void *)(long)ret;
4920 dmx->channel[ret].dvr_feed = NULL;
4921 }
4922 /*dvr */
4923 if (DVR_FEED(feed)) {
4924 dmx->channel[ret].dvr_feed = feed;
4925 feed->priv = (void *)(long)ret;
4926 if (!dmx->record)
4927 dmx_enable(dmx);
4928 dmx_add_recchan(dmx->id, ret);
4929 } else if (dfeed && sf_ret) {
4930 dmx->channel[ret].dvr_feed = dfeed;
4931 dfeed->priv = (void *)(long)ret;
4932 if (!dmx->record)
4933 dmx_enable(dmx);
4934 dmx_add_recchan(dmx->id, ret);
4935 }
4936
4937 break;
4938 case DMX_TYPE_SEC:
4939 pr_dbg("%s: DMX_TYPE_SEC\n", __func__);
4940 ret = dmx_get_chan(dmx, feed->pid);
4941 if (ret >= 0) {
4942 if (DVR_FEED(dmx->channel[ret].feed)) {
4943 if (sf_ret) {
4944 /*if sf_on, we do not reset the
4945 *previous dvr feed, just load the pes
4946 *feed on the sf,a diffrent data path.
4947 */
4948 dfeed = dmx->channel[ret].feed;
4949 dmx_remove_feed(dmx, dfeed);
4950 }
4951 } else {
4952 pr_error("PID %d already used\n", feed->pid);
4953 ret = -EBUSY;
4954 goto fail;
4955 }
4956 }
4957 if (sf_ret) { /*not sf feed. */
4958 id = dmx_alloc_chan(dmx, feed->type,
4959 feed->pes_type, feed->pid);
4960 if (id < 0) {
4961 pr_dbg("%s: alloc chan error, ret=%d\n",
4962 __func__, id);
4963 ret = -EBUSY;
4964 goto fail;
4965 }
4966 for (filter = feed->filter; filter;
4967 filter = filter->next) {
4968 ret = dmx_chan_add_filter(dmx, id, filter);
4969 if (ret >= 0)
4970 filter->hw_handle = ret;
4971 else
4972 filter->hw_handle = (u16)-1;
4973 }
4974 dmx->channel[id].feed = feed;
4975 feed->priv = (void *)(long)id;
4976 dmx->channel[id].dvr_feed = NULL;
4977
4978 if (dfeed) {
4979 dmx->channel[id].dvr_feed = dfeed;
4980 dfeed->priv = (void *)(long)id;
4981 if (!dmx->record)
4982 dmx_enable(dmx);
4983 dmx_add_recchan(dmx->id, id);
4984 }
4985 }
4986 break;
4987 default:
4988 return -EINVAL;
4989 }
4990
4991 dmx->feed_count++;
4992
4993 return 0;
4994
4995 fail:
4996 feed->priv = (void *)-1;
4997 return ret;
4998 }
4999
dmx_remove_feed(struct aml_dmx * dmx,struct dvb_demux_feed * feed)5000 static int dmx_remove_feed(struct aml_dmx *dmx, struct dvb_demux_feed *feed)
5001 {
5002 struct dvb_demux_filter *filter;
5003 struct dvb_demux_feed *dfeed = NULL;
5004
5005 int sf_ret = 0; /*<0:error, =0:sf_on, >0:sf_off */
5006
5007 /*add fail, no need to remove*/
5008 if (((long)feed->priv) < 0)
5009 return 0;
5010
5011 sf_ret = sf_check_feed(dmx, feed, 0/*SF_FEED_OP_RM */);
5012 if (sf_ret <= 0)
5013 return sf_ret;
5014
5015 switch (feed->type) {
5016 case DMX_TYPE_TS:
5017 if (dmx->channel[(long)feed->priv].feed ==
5018 dmx->channel[(long)feed->priv].dvr_feed) {
5019 dmx_rm_recchan(dmx->id, (long)feed->priv);
5020 dmx_free_chan(dmx, (long)feed->priv);
5021 } else {
5022 if (feed == dmx->channel[(long)feed->priv].feed) {
5023 dfeed = dmx->channel[(long)feed->priv].dvr_feed;
5024 dmx_rm_recchan(dmx->id, (long)feed->priv);
5025 dmx_free_chan(dmx, (long)feed->priv);
5026 if (dfeed) {
5027 /*start the dvr feed */
5028 dmx_add_feed(dmx, dfeed);
5029 }
5030 } else if (feed ==
5031 dmx->channel[(long)feed->priv].dvr_feed) {
5032 /*just remove the dvr_feed */
5033 dmx->channel[(long)feed->priv].dvr_feed = NULL;
5034 dmx_rm_recchan(dmx->id, (long)feed->priv);
5035 if (dmx->record)
5036 dmx_enable(dmx);
5037 } else {
5038 /*This must never happen */
5039 pr_error("%s: unknown feed\n", __func__);
5040 return -EINVAL;
5041 }
5042 }
5043
5044 break;
5045 case DMX_TYPE_SEC:
5046 for (filter = feed->filter; filter; filter = filter->next) {
5047 if (filter->hw_handle != (u16)-1)
5048 dmx_remove_filter(dmx, (long)feed->priv,
5049 (int)filter->hw_handle);
5050 }
5051
5052 dfeed = dmx->channel[(long)feed->priv].dvr_feed;
5053 dmx_rm_recchan(dmx->id, (long)feed->priv);
5054 dmx_free_chan(dmx, (long)feed->priv);
5055 if (dfeed) {
5056 /*start the dvr feed */
5057 dmx_add_feed(dmx, dfeed);
5058 }
5059 break;
5060 default:
5061 return -EINVAL;
5062 }
5063
5064 dmx->feed_count--;
5065 return 0;
5066 }
5067
aml_dmx_hw_init(struct aml_dmx * dmx)5068 int aml_dmx_hw_init(struct aml_dmx *dmx)
5069 {
5070 /*
5071 *struct aml_dvb *dvb = (struct aml_dvb *)dmx->demux.priv;
5072 *unsigned long flags;
5073 */
5074 int ret;
5075
5076 /*Demux initialize */
5077 /*spin_lock_irqsave(&dvb->slock, flags);*/
5078 ret = dmx_init(dmx);
5079 /*spin_unlock_irqrestore(&dvb->slock, flags);*/
5080
5081 return ret;
5082 }
5083
aml_dmx_hw_deinit(struct aml_dmx * dmx)5084 int aml_dmx_hw_deinit(struct aml_dmx *dmx)
5085 {
5086 struct aml_dvb *dvb = (struct aml_dvb *)dmx->demux.priv;
5087 unsigned long flags;
5088 int ret;
5089
5090 spin_lock_irqsave(&dvb->slock, flags);
5091 ret = dmx_deinit(dmx);
5092 spin_unlock_irqrestore(&dvb->slock, flags);
5093
5094 return ret;
5095 }
5096
5097 /*extern void afifo_reset(int v);*/
5098
aml_asyncfifo_hw_init(struct aml_asyncfifo * afifo)5099 int aml_asyncfifo_hw_init(struct aml_asyncfifo *afifo)
5100 {
5101
5102 /*
5103 * struct aml_dvb *dvb = afifo->dvb;
5104 * unsigned long flags;
5105 */
5106 int ret;
5107
5108 int len = asyncfifo_buf_len;
5109 unsigned long buf = asyncfifo_alloc_buffer(afifo, len);
5110
5111 if (!buf)
5112 return -1;
5113
5114 /*Async FIFO initialize*/
5115 /*
5116 * spin_lock_irqsave(&dvb->slock, flags);
5117 */
5118 /*
5119 *#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
5120 * CLK_GATE_ON(ASYNC_FIFO);
5121 *#endif
5122 */
5123 /*afifo_reset(0);*/
5124
5125 WRITE_MPEG_REG(RESET6_REGISTER, (1<<11)|(1<<12));
5126
5127 ret = async_fifo_init(afifo, 1, len, buf);
5128 /*
5129 * spin_unlock_irqrestore(&dvb->slock, flags);
5130 */
5131 if (ret < 0)
5132 asyncfifo_free_buffer(buf, len);
5133
5134 return ret;
5135 }
5136
aml_asyncfifo_hw_deinit(struct aml_asyncfifo * afifo)5137 int aml_asyncfifo_hw_deinit(struct aml_asyncfifo *afifo)
5138 {
5139 int ret;
5140
5141 ret = async_fifo_deinit(afifo, 1);
5142 /*
5143 *#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
5144 * CLK_GATE_OFF(ASYNC_FIFO);
5145 *#endif
5146 */
5147 /*afifo_reset(1);*/
5148
5149 return ret;
5150 }
5151
aml_asyncfifo_hw_reset(struct aml_asyncfifo * afifo)5152 int aml_asyncfifo_hw_reset(struct aml_asyncfifo *afifo)
5153 {
5154 struct aml_dvb *dvb = afifo->dvb;
5155 unsigned long flags;
5156 int ret, src = -1;
5157
5158 unsigned long buf = 0;
5159 int len = asyncfifo_buf_len;
5160 buf = asyncfifo_alloc_buffer(afifo, len);
5161 if (!buf)
5162 return -1;
5163
5164 if (afifo->init) {
5165 src = afifo->source;
5166 async_fifo_deinit(afifo, 0);
5167 }
5168
5169 spin_lock_irqsave(&dvb->slock, flags);
5170 ret = async_fifo_init(afifo, 0, len, buf);
5171 /* restore the source */
5172 if (src != -1)
5173 afifo->source = src;
5174
5175 if ((ret == 0) && afifo->dvb)
5176 reset_async_fifos(afifo->dvb);
5177
5178 spin_unlock_irqrestore(&dvb->slock, flags);
5179
5180 if (ret < 0)
5181 asyncfifo_free_buffer(buf, len);
5182
5183 return ret;
5184 }
5185
aml_dmx_hw_start_feed(struct dvb_demux_feed * dvbdmxfeed)5186 int aml_dmx_hw_start_feed(struct dvb_demux_feed *dvbdmxfeed)
5187 {
5188 struct aml_dmx *dmx = (struct aml_dmx *)dvbdmxfeed->demux;
5189 struct aml_dvb *dvb = (struct aml_dvb *)dmx->demux.priv;
5190 unsigned long flags;
5191 int ret = 0;
5192
5193 spin_lock_irqsave(&dvb->slock, flags);
5194 ret = dmx_add_feed(dmx, dvbdmxfeed);
5195 spin_unlock_irqrestore(&dvb->slock, flags);
5196
5197 /*handle errors silently*/
5198 if (ret != 0)
5199 ret = 0;
5200
5201 return ret;
5202 }
5203
aml_dmx_hw_stop_feed(struct dvb_demux_feed * dvbdmxfeed)5204 int aml_dmx_hw_stop_feed(struct dvb_demux_feed *dvbdmxfeed)
5205 {
5206 struct aml_dmx *dmx = (struct aml_dmx *)dvbdmxfeed->demux;
5207 struct aml_dvb *dvb = (struct aml_dvb *)dmx->demux.priv;
5208 unsigned long flags;
5209
5210 spin_lock_irqsave(&dvb->slock, flags);
5211 dmx_remove_feed(dmx, dvbdmxfeed);
5212 spin_unlock_irqrestore(&dvb->slock, flags);
5213
5214 return 0;
5215 }
5216
sf_dmx_track_source(struct aml_dmx * dmx)5217 int sf_dmx_track_source(struct aml_dmx *dmx)
5218 {
5219 struct aml_dvb *dvb = (struct aml_dvb *)dmx->demux.priv;
5220 struct aml_swfilter *sf = &dvb->swfilter;
5221
5222 if (sf->user && (dmx->id == sf->track_dmx)) {
5223 pr_dbg_sf("tracking dmx src [%d -> %d]\n",
5224 sf->dmx->source, dmx->source);
5225 sf->dmx->source = dmx->source;
5226 dmx_reset_dmx_hw_ex_unlock(dvb, sf->dmx, 0);
5227 }
5228 return 0;
5229 }
5230
aml_dmx_hw_set_source(struct dmx_demux * demux,dmx_source_t src)5231 int aml_dmx_hw_set_source(struct dmx_demux *demux, dmx_source_t src)
5232 {
5233 struct aml_dmx *dmx = (struct aml_dmx *)demux;
5234 struct aml_dvb *dvb = (struct aml_dvb *)dmx->demux.priv;
5235 int ret = 0;
5236 int hw_src;
5237 unsigned long flags;
5238
5239 if (sf_dmx_sf(dmx)) {
5240 pr_error("%s: demux %d is in sf mode\n", __func__, dmx->id);
5241 return -EINVAL;
5242 }
5243
5244 spin_lock_irqsave(&dvb->slock, flags);
5245
5246 hw_src = dmx->source;
5247
5248 switch (src) {
5249 case DMX_SOURCE_FRONT0:
5250 hw_src =
5251 (dvb->ts[0].mode ==
5252 AM_TS_SERIAL) ? (dvb->ts[0].s2p_id+AM_TS_SRC_S_TS0) : AM_TS_SRC_TS0;
5253 break;
5254 case DMX_SOURCE_FRONT1:
5255 hw_src =
5256 (dvb->ts[1].mode ==
5257 AM_TS_SERIAL) ? (dvb->ts[1].s2p_id+AM_TS_SRC_S_TS0) : AM_TS_SRC_TS1;
5258 break;
5259 case DMX_SOURCE_FRONT2:
5260 hw_src =
5261 (dvb->ts[2].mode ==
5262 AM_TS_SERIAL) ? (dvb->ts[2].s2p_id+AM_TS_SRC_S_TS0) : AM_TS_SRC_TS2;
5263 break;
5264 case DMX_SOURCE_FRONT3:
5265 hw_src =
5266 (dvb->ts[3].mode ==
5267 AM_TS_SERIAL) ? (dvb->ts[3].s2p_id+AM_TS_SRC_S_TS0) : AM_TS_SRC_TS3;
5268 break;
5269 case DMX_SOURCE_DVR0:
5270 hw_src = AM_TS_SRC_HIU;
5271 break;
5272 case DMX_SOURCE_DVR1:
5273 hw_src = AM_TS_SRC_HIU1;
5274 break;
5275 case DMX_SOURCE_FRONT0_OFFSET:
5276 hw_src = AM_TS_SRC_DMX0;
5277 break;
5278 case DMX_SOURCE_FRONT1_OFFSET:
5279 hw_src = AM_TS_SRC_DMX1;
5280 break;
5281 case DMX_SOURCE_FRONT2_OFFSET:
5282 hw_src = AM_TS_SRC_DMX2;
5283 break;
5284 default:
5285 pr_error("illegal demux source %d\n", src);
5286 ret = -EINVAL;
5287 break;
5288 }
5289
5290 if (hw_src != dmx->source) {
5291 dmx->source = hw_src;
5292 dmx_reset_dmx_hw_ex_unlock(dvb, dmx, 0);
5293 sf_dmx_track_source(dmx);
5294 }
5295
5296 spin_unlock_irqrestore(&dvb->slock, flags);
5297
5298 return ret;
5299 }
5300
5301 #define IS_SRC_DMX(_src) ((_src) >= AM_TS_SRC_DMX0 && (_src) <= AM_TS_SRC_DMX2)
5302
aml_stb_hw_set_source(struct aml_dvb * dvb,dmx_source_t src)5303 int aml_stb_hw_set_source(struct aml_dvb *dvb, dmx_source_t src)
5304 {
5305 unsigned long flags;
5306 int hw_src;
5307 int ret;
5308
5309 ret = 0;
5310 spin_lock_irqsave(&dvb->slock, flags);
5311
5312 hw_src = dvb->stb_source;
5313
5314 switch (src) {
5315 case DMX_SOURCE_FRONT0:
5316 hw_src =
5317 (dvb->ts[0].mode ==
5318 AM_TS_SERIAL) ? (dvb->ts[0].s2p_id+AM_TS_SRC_S_TS0) : AM_TS_SRC_TS0;
5319 break;
5320 case DMX_SOURCE_FRONT1:
5321 hw_src =
5322 (dvb->ts[1].mode ==
5323 AM_TS_SERIAL) ? (dvb->ts[1].s2p_id+AM_TS_SRC_S_TS0) : AM_TS_SRC_TS1;
5324 break;
5325 case DMX_SOURCE_FRONT2:
5326 hw_src =
5327 (dvb->ts[2].mode ==
5328 AM_TS_SERIAL) ? (dvb->ts[2].s2p_id+AM_TS_SRC_S_TS0) : AM_TS_SRC_TS2;
5329 break;
5330 case DMX_SOURCE_FRONT3:
5331 hw_src =
5332 (dvb->ts[3].mode ==
5333 AM_TS_SERIAL) ? (dvb->ts[3].s2p_id+AM_TS_SRC_S_TS0) : AM_TS_SRC_TS3;
5334 break;
5335 case DMX_SOURCE_DVR0:
5336 hw_src = AM_TS_SRC_HIU;
5337 break;
5338 case DMX_SOURCE_DVR1:
5339 hw_src = AM_TS_SRC_HIU1;
5340 break;
5341 case DMX_SOURCE_FRONT0_OFFSET:
5342 hw_src = AM_TS_SRC_DMX0;
5343 break;
5344 case DMX_SOURCE_FRONT1_OFFSET:
5345 hw_src = AM_TS_SRC_DMX1;
5346 break;
5347 case DMX_SOURCE_FRONT2_OFFSET:
5348 hw_src = AM_TS_SRC_DMX2;
5349 break;
5350 default:
5351 pr_error("illegal demux source %d\n", src);
5352 ret = -EINVAL;
5353 break;
5354 }
5355
5356 if (dvb->stb_source != hw_src) {
5357 int old_source = dvb->stb_source;
5358
5359 dvb->stb_source = hw_src;
5360
5361 if (IS_SRC_DMX(old_source)) {
5362 dmx_set_misc_id(dvb,
5363 (old_source - AM_TS_SRC_DMX0), 0, -1);
5364 } else {
5365 /*which dmx for av-play is unknown,
5366 *can't avoid reset-all
5367 */
5368 dmx_reset_hw_ex(dvb, 0);
5369 }
5370
5371 if (IS_SRC_DMX(dvb->stb_source)) {
5372 dmx_set_misc_id(dvb,
5373 (dvb->stb_source - AM_TS_SRC_DMX0), 1, -1);
5374 /*dmx_reset_dmx_id_hw_ex_unlock
5375 * (dvb, (dvb->stb_source-AM_TS_SRC_DMX0), 0);
5376 */
5377 } else {
5378 /*which dmx for av-play is unknown,
5379 *can't avoid reset-all
5380 */
5381 dmx_reset_hw_ex(dvb, 0);
5382 }
5383 }
5384
5385 spin_unlock_irqrestore(&dvb->slock, flags);
5386
5387 return ret;
5388 }
5389
5390
5391
aml_dsc_hw_set_source(struct aml_dsc * dsc,dmx_source_t src,dmx_source_t dst)5392 int aml_dsc_hw_set_source(struct aml_dsc *dsc,
5393 dmx_source_t src, dmx_source_t dst)
5394 {
5395 struct aml_dvb *dvb = dsc->dvb;
5396 int ret = 0;
5397 unsigned long flags;
5398 int hw_src = -1, hw_dst = -1, org_src = -1, org_dst = -1;
5399 int src_reset = 0, dst_reset = 0;
5400
5401 spin_lock_irqsave(&dvb->slock, flags);
5402
5403 hw_src = dsc->source;
5404 hw_dst = dsc->dst;
5405
5406 switch (src) {
5407 case DMX_SOURCE_FRONT0_OFFSET:
5408 hw_src = AM_TS_SRC_DMX0;
5409 break;
5410 case DMX_SOURCE_FRONT1_OFFSET:
5411 hw_src = AM_TS_SRC_DMX1;
5412 break;
5413 case DMX_SOURCE_FRONT2_OFFSET:
5414 hw_src = AM_TS_SRC_DMX2;
5415 break;
5416 default:
5417 hw_src = -1;
5418 break;
5419 }
5420 switch (dst) {
5421 case DMX_SOURCE_FRONT0_OFFSET:
5422 hw_dst = AM_TS_SRC_DMX0;
5423 break;
5424 case DMX_SOURCE_FRONT1_OFFSET:
5425 hw_dst = AM_TS_SRC_DMX1;
5426 break;
5427 case DMX_SOURCE_FRONT2_OFFSET:
5428 hw_dst = AM_TS_SRC_DMX2;
5429 break;
5430 default:
5431 hw_dst = -1;
5432 break;
5433 }
5434
5435 if (hw_src != dsc->source) {
5436 org_src = dsc->source;
5437 dsc->source = hw_src;
5438 src_reset = 1;
5439 }
5440 if (hw_dst != dsc->dst) {
5441 org_dst = dsc->dst;
5442 dsc->dst = hw_dst;
5443 dst_reset = 1;
5444 }
5445
5446 if (src_reset) {
5447 pr_inf("dsc%d source changed: %d -> %d\n",
5448 dsc->id, org_src, hw_src);
5449 if (org_src != -1) {
5450 pr_inf("reset dmx%d\n", (org_src - AM_TS_SRC_DMX0));
5451 dmx_reset_dmx_id_hw_ex_unlock(dvb,
5452 (org_src - AM_TS_SRC_DMX0), 0);
5453 }
5454 if (hw_src != -1) {
5455 pr_inf("reset dmx%d\n", (hw_src - AM_TS_SRC_DMX0));
5456 dmx_reset_dmx_id_hw_ex_unlock(dvb,
5457 (hw_src - AM_TS_SRC_DMX0), 0);
5458 } else
5459 dsc_enable(dsc, 0);
5460 }
5461 if (dst_reset) {
5462 pr_inf("dsc%d dest changed: %d -> %d\n",
5463 dsc->id, org_dst, hw_dst);
5464 if (((!src_reset) && (org_dst != -1)) ||
5465 (src_reset && (org_dst != -1) &&
5466 (org_dst != org_src) && (org_dst != hw_src))) {
5467 pr_inf("reset dmx%d\n", (org_dst - AM_TS_SRC_DMX0));
5468 dmx_reset_dmx_id_hw_ex_unlock(dvb,
5469 (org_dst - AM_TS_SRC_DMX0), 0);
5470 }
5471 if (((!src_reset) && (hw_dst != -1)) ||
5472 (src_reset && (hw_dst != -1)
5473 && (hw_dst != org_src) && (hw_dst != hw_src))) {
5474 pr_inf("reset dmx%d\n", (hw_dst - AM_TS_SRC_DMX0));
5475 dmx_reset_dmx_id_hw_ex_unlock(dvb,
5476 (hw_dst - AM_TS_SRC_DMX0), 0);
5477 }
5478 if (hw_dst == -1)
5479 dsc_enable(dsc, 0);
5480 }
5481 if (src_reset && dst_reset) {
5482 set_ciplus_input_source(dsc);
5483 }
5484
5485 spin_unlock_irqrestore(&dvb->slock, flags);
5486
5487 return ret;
5488 }
5489
aml_tso_hw_set_source(struct aml_dvb * dvb,dmx_source_t src)5490 int aml_tso_hw_set_source(struct aml_dvb *dvb, dmx_source_t src)
5491 {
5492 int ret = 0;
5493 unsigned long flags;
5494 int hw_src;
5495
5496 spin_lock_irqsave(&dvb->slock, flags);
5497
5498 hw_src = dvb->tso_source;
5499
5500 switch (src) {
5501 case DMX_SOURCE_FRONT0:
5502 hw_src = (dvb->ts[0].mode == AM_TS_SERIAL)
5503 ? (dvb->ts[0].s2p_id+AM_TS_SRC_S_TS0) : AM_TS_SRC_TS0;
5504 break;
5505 case DMX_SOURCE_FRONT1:
5506 hw_src = (dvb->ts[1].mode == AM_TS_SERIAL)
5507 ? (dvb->ts[1].s2p_id+AM_TS_SRC_S_TS0) : AM_TS_SRC_TS1;
5508 break;
5509 case DMX_SOURCE_FRONT2:
5510 hw_src = (dvb->ts[2].mode == AM_TS_SERIAL)
5511 ? (dvb->ts[2].s2p_id+AM_TS_SRC_S_TS0) : AM_TS_SRC_TS2;
5512 break;
5513 case DMX_SOURCE_FRONT3:
5514 hw_src = (dvb->ts[3].mode == AM_TS_SERIAL)
5515 ? (dvb->ts[3].s2p_id+AM_TS_SRC_S_TS0) : AM_TS_SRC_TS3;
5516 break;
5517 case DMX_SOURCE_DVR0:
5518 hw_src = AM_TS_SRC_HIU;
5519 break;
5520 case DMX_SOURCE_FRONT0 + 100:
5521 hw_src = AM_TS_SRC_DMX0;
5522 break;
5523 case DMX_SOURCE_FRONT1 + 100:
5524 hw_src = AM_TS_SRC_DMX1;
5525 break;
5526 case DMX_SOURCE_FRONT2 + 100:
5527 hw_src = AM_TS_SRC_DMX2;
5528 break;
5529 default:
5530 hw_src = -1;
5531 ret = -EINVAL;
5532 break;
5533 }
5534
5535 if (hw_src != dvb->tso_source) {
5536 dvb->tso_source = hw_src;
5537 stb_enable(dvb);
5538 }
5539
5540 spin_unlock_irqrestore(&dvb->slock, flags);
5541
5542 return ret;
5543 }
5544
aml_asyncfifo_hw_set_source(struct aml_asyncfifo * afifo,enum aml_dmx_id_t src)5545 int aml_asyncfifo_hw_set_source(struct aml_asyncfifo *afifo,
5546 enum aml_dmx_id_t src)
5547 {
5548 struct aml_dvb *dvb = afifo->dvb;
5549 int ret = -1;
5550 unsigned long flags;
5551
5552 if (sf_afifo_sf(afifo)) {
5553 pr_error("%s: afifo %d is in sf mode\n", __func__, afifo->id);
5554 return -EINVAL;
5555 }
5556
5557 spin_lock_irqsave(&dvb->slock, flags);
5558
5559 pr_dbg("asyncfifo %d set source %d->%d",
5560 afifo->id, afifo->source, src);
5561 switch (src) {
5562 case AM_DMX_0:
5563 case AM_DMX_1:
5564 case AM_DMX_2:
5565 if (afifo->source != src) {
5566 afifo->source = src;
5567 ret = 0;
5568 }
5569 break;
5570 default:
5571 pr_error("illegal async fifo source %d\n", src);
5572 ret = -EINVAL;
5573 break;
5574 }
5575
5576 if (ret == 0 && afifo->dvb)
5577 reset_async_fifos(afifo->dvb);
5578
5579 spin_unlock_irqrestore(&dvb->slock, flags);
5580
5581 return ret;
5582 }
5583
aml_dmx_hw_set_dump_ts_select(struct dmx_demux * demux,int dump_ts_select)5584 int aml_dmx_hw_set_dump_ts_select(struct dmx_demux *demux, int dump_ts_select)
5585 {
5586 struct aml_dmx *dmx = (struct aml_dmx *)demux;
5587 struct aml_dvb *dvb = (struct aml_dvb *)dmx->demux.priv;
5588 int ret = 0;
5589 unsigned long flags;
5590
5591 spin_lock_irqsave(&dvb->slock, flags);
5592 dump_ts_select = !!dump_ts_select;
5593 if (dmx->dump_ts_select != dump_ts_select) {
5594 dmx->dump_ts_select = dump_ts_select;
5595 dmx_reset_dmx_hw_ex_unlock(dvb, dmx, 0);
5596 }
5597 spin_unlock_irqrestore(&dvb->slock, flags);
5598
5599 return ret;
5600 }
5601
aml_dmx_get_video_pts(struct aml_dvb * dvb)5602 u32 aml_dmx_get_video_pts(struct aml_dvb *dvb)
5603 {
5604 unsigned long flags;
5605 u32 pts;
5606
5607 spin_lock_irqsave(&dvb->slock, flags);
5608 pts = video_pts;
5609 spin_unlock_irqrestore(&dvb->slock, flags);
5610
5611 return pts;
5612 }
5613
aml_dmx_get_audio_pts(struct aml_dvb * dvb)5614 u32 aml_dmx_get_audio_pts(struct aml_dvb *dvb)
5615 {
5616 unsigned long flags;
5617 u32 pts;
5618
5619 spin_lock_irqsave(&dvb->slock, flags);
5620 pts = audio_pts;
5621 spin_unlock_irqrestore(&dvb->slock, flags);
5622
5623 return pts;
5624 }
5625
aml_dmx_get_video_pts_bit32(struct aml_dvb * dvb)5626 u32 aml_dmx_get_video_pts_bit32(struct aml_dvb *dvb)
5627 {
5628 unsigned long flags;
5629 u32 bit32;
5630
5631 spin_lock_irqsave(&dvb->slock, flags);
5632 bit32 = video_pts_bit32;
5633 spin_unlock_irqrestore(&dvb->slock, flags);
5634
5635 return bit32;
5636 }
5637
aml_dmx_get_audio_pts_bit32(struct aml_dvb * dvb)5638 u32 aml_dmx_get_audio_pts_bit32(struct aml_dvb *dvb)
5639 {
5640 unsigned long flags;
5641 u32 bit32;
5642
5643 spin_lock_irqsave(&dvb->slock, flags);
5644 bit32 = audio_pts_bit32;
5645 spin_unlock_irqrestore(&dvb->slock, flags);
5646
5647 return bit32;
5648 }
aml_dmx_get_first_video_pts(struct aml_dvb * dvb)5649 u32 aml_dmx_get_first_video_pts(struct aml_dvb *dvb)
5650 {
5651 unsigned long flags;
5652 u32 pts;
5653
5654 spin_lock_irqsave(&dvb->slock, flags);
5655 pts = first_video_pts;
5656 spin_unlock_irqrestore(&dvb->slock, flags);
5657
5658 return pts;
5659 }
5660
aml_dmx_get_first_audio_pts(struct aml_dvb * dvb)5661 u32 aml_dmx_get_first_audio_pts(struct aml_dvb *dvb)
5662 {
5663 unsigned long flags;
5664 u32 pts;
5665
5666 spin_lock_irqsave(&dvb->slock, flags);
5667 pts = first_audio_pts;
5668 spin_unlock_irqrestore(&dvb->slock, flags);
5669
5670 return pts;
5671 }
5672
aml_dmx_set_skipbyte(struct aml_dvb * dvb,int skipbyte)5673 int aml_dmx_set_skipbyte(struct aml_dvb *dvb, int skipbyte)
5674 {
5675 if (demux_skipbyte != skipbyte) {
5676 pr_dbg("set skip byte %d\n", skipbyte);
5677 demux_skipbyte = skipbyte;
5678 dmx_reset_hw_ex(dvb, 0);
5679 }
5680
5681 return 0;
5682 }
5683
aml_dmx_set_demux(struct aml_dvb * dvb,int id)5684 int aml_dmx_set_demux(struct aml_dvb *dvb, int id)
5685 {
5686 aml_stb_hw_set_source(dvb, DMX_SOURCE_DVR0);
5687 if (id < DMX_DEV_COUNT) {
5688 struct aml_dmx *dmx = &dvb->dmx[id];
5689
5690 aml_dmx_hw_set_source((struct dmx_demux *)dmx,
5691 DMX_SOURCE_DVR0);
5692 }
5693
5694 return 0;
5695 }
5696
_set_tsfile_clkdiv(struct aml_dvb * dvb,int clkdiv)5697 int _set_tsfile_clkdiv(struct aml_dvb *dvb, int clkdiv)
5698 {
5699 if (tsfile_clkdiv != clkdiv) {
5700 pr_dbg("set ts file clock div %d\n", clkdiv);
5701 tsfile_clkdiv = clkdiv;
5702 dmx_reset_hw(dvb);
5703 }
5704
5705 return 0;
5706 }
5707
stb_set_tsfile_clkdiv(struct class * class,struct class_attribute * attr,const char * buf,size_t size)5708 static ssize_t stb_set_tsfile_clkdiv(struct class *class,
5709 struct class_attribute *attr,
5710 const char *buf, size_t size)
5711 {
5712 /*int div = (int)simple_strtol(buf, NULL, 10);*/
5713 long div;
5714
5715 if (kstrtol(buf, 0, &div) == 0)
5716 _set_tsfile_clkdiv(aml_get_dvb_device(), (int)div);
5717 return size;
5718 }
5719
stb_get_tsfile_clkdiv(struct class * class,struct class_attribute * attr,char * buf)5720 static ssize_t stb_get_tsfile_clkdiv(struct class *class,
5721 struct class_attribute *attr, char *buf)
5722 {
5723 ssize_t ret;
5724
5725 ret = sprintf(buf, "%d\n", tsfile_clkdiv);
5726 return ret;
5727 }
5728
5729
5730 static int dmx_id;
5731
dmx_smallsec_show(struct class * class,struct class_attribute * attr,char * buf)5732 static ssize_t dmx_smallsec_show(struct class *class,
5733 struct class_attribute *attr, char *buf)
5734 {
5735 ssize_t ret;
5736 struct aml_dvb *dvb = aml_get_dvb_device();
5737
5738 ret = sprintf(buf, "%d:%d\n", dvb->dmx[dmx_id].smallsec.enable,
5739 dvb->dmx[dmx_id].smallsec.bufsize);
5740 return ret;
5741 }
dmx_smallsec_store(struct class * class,struct class_attribute * attr,const char * buf,size_t size)5742 static ssize_t dmx_smallsec_store(struct class *class,
5743 struct class_attribute *attr,
5744 const char *buf, size_t size)
5745 {
5746 int i, e, s = 0, f = 0;
5747 struct aml_dvb *dvb = aml_get_dvb_device();
5748
5749 i = sscanf(buf, "%d:%i:%d", &e, &s, &f);
5750 if (i <= 0)
5751 return size;
5752
5753 dmx_smallsec_set(&dvb->dmx[dmx_id].smallsec, e, s, f);
5754 return size;
5755 }
5756
dmx_timeout_show(struct class * class,struct class_attribute * attr,char * buf)5757 static ssize_t dmx_timeout_show(struct class *class,
5758 struct class_attribute *attr, char *buf)
5759 {
5760 ssize_t ret;
5761 struct aml_dvb *dvb = aml_get_dvb_device();
5762
5763 ret = sprintf(buf, "%d:%d:0x%x:%d:%d\n",
5764 dvb->dmx[dmx_id].timeout.enable,
5765 dvb->dmx[dmx_id].timeout.timeout,
5766 dvb->dmx[dmx_id].timeout.ch_disable,
5767 dvb->dmx[dmx_id].timeout.match,
5768 (DMX_READ_REG(dmx_id, STB_INT_STATUS)&(1<<INPUT_TIME_OUT)) ?
5769 1 : 0);
5770 DMX_WRITE_REG(dmx_id, STB_INT_STATUS, (1<<INPUT_TIME_OUT));
5771 return ret;
5772 }
dmx_timeout_store(struct class * class,struct class_attribute * attr,const char * buf,size_t size)5773 static ssize_t dmx_timeout_store(struct class *class,
5774 struct class_attribute *attr,
5775 const char *buf, size_t size)
5776 {
5777 int i, e, t = 0, c = 0, m = 0, f = 0;
5778 struct aml_dvb *dvb = aml_get_dvb_device();
5779
5780 i = sscanf(buf, "%d:%i:%i:%d:%d", &e, &t, &c, &m, &f);
5781 if (i <= 0)
5782 return size;
5783
5784 dmx_timeout_set(&dvb->dmx[dmx_id].timeout, e, t, c, m, f);
5785 return size;
5786 }
5787
5788
5789 #define DEMUX_SCAMBLE_FUNC_DECL(i) \
5790 static ssize_t dmx_reg_value_show_demux##i##_scramble(struct class *class, \
5791 struct class_attribute *attr, char *buf)\
5792 {\
5793 int data = 0;\
5794 int aflag = 0;\
5795 int vflag = 0;\
5796 ssize_t ret = 0;\
5797 data = DMX_READ_REG(i, DEMUX_SCRAMBLING_STATE);\
5798 if ((data & 0x01) == 0x01) \
5799 vflag = 1;\
5800 if ((data & 0x02) == 0x02) \
5801 aflag = 1;\
5802 ret = sprintf(buf, "%d %d\n", vflag, aflag);\
5803 return ret;\
5804 }
5805
5806 #if DMX_DEV_COUNT > 0
5807 DEMUX_SCAMBLE_FUNC_DECL(0)
5808 #endif
5809 #if DMX_DEV_COUNT > 1
5810 DEMUX_SCAMBLE_FUNC_DECL(1)
5811 #endif
5812 #if DMX_DEV_COUNT > 2
5813 DEMUX_SCAMBLE_FUNC_DECL(2)
5814 #endif
ciplus_output_ctrl_show(struct class * class,struct class_attribute * attr,char * buf)5815 static ssize_t ciplus_output_ctrl_show(struct class *class,
5816 struct class_attribute *attr,
5817 char *buf)
5818 {
5819 int ret;
5820 char *out = "none";
5821
5822 pr_inf("output demux use 3 bit to indicate.\n");
5823 pr_inf("1bit:demux0 2bit:demux1 3bit:demux2\n");
5824
5825 switch (ciplus_out_sel) {
5826 case 1:
5827 out = "dmx0";
5828 break;
5829 case 2:
5830 out = "dmx1";
5831 break;
5832 case 4:
5833 out = "dmx2";
5834 break;
5835 default:
5836 break;
5837 }
5838
5839 ret = sprintf(buf, "%s 0x%x %s\n",
5840 out,
5841 ciplus_out_sel,
5842 (ciplus_out_auto_mode) ? "" : "(force)");
5843 return ret;
5844 }
5845
ciplus_output_ctrl_store(struct class * class,struct class_attribute * attr,const char * buf,size_t size)5846 static ssize_t ciplus_output_ctrl_store(struct class *class,
5847 struct class_attribute *attr,
5848 const char *buf, size_t size)
5849 {
5850 int i, tmp;
5851
5852 i = kstrtoint(buf, -1, &tmp);
5853 if (tmp > 8 || tmp < 0)
5854 pr_error("Invalid output set\n");
5855 else if (tmp == 8) {
5856 ciplus_out_auto_mode = 1;
5857 ciplus_out_sel = -1;
5858 pr_error("Auto set output mode enable\n");
5859 } else {
5860 ciplus_out_auto_mode = 0;
5861 ciplus_out_sel = tmp;
5862 pr_error("Auto set output mode disable\n");
5863 }
5864 return size;
5865 }
reset_fec_input_ctrl_show(struct class * class,struct class_attribute * attr,char * buf)5866 static ssize_t reset_fec_input_ctrl_show(struct class *class,
5867 struct class_attribute *attr,
5868 char *buf)
5869 {
5870 return 0;
5871 }
5872
reset_fec_input_ctrl_store(struct class * class,struct class_attribute * attr,const char * buf,size_t size)5873 static ssize_t reset_fec_input_ctrl_store(struct class *class,
5874 struct class_attribute *attr,
5875 const char *buf, size_t size)
5876 {
5877 u32 v;
5878
5879 v = READ_MPEG_REG(FEC_INPUT_CONTROL);
5880 v &= ~(1<<11);
5881 WRITE_MPEG_REG(FEC_INPUT_CONTROL, v);
5882
5883 pr_dbg("reset FEC_INPUT_CONTROL to %x\n", v);
5884
5885 return size;
5886 }
5887 static ssize_t dmx_reg_addr_show_source(struct class *class,
5888 struct class_attribute *attr,
5889 char *buf);
5890 static ssize_t dmx_reg_addr_store_source(struct class *class,
5891 struct class_attribute *attr,
5892 const char *buf, size_t size);
5893 static ssize_t dmx_id_show_source(struct class *class,
5894 struct class_attribute *attr, char *buf);
5895 static ssize_t dmx_id_store_source(struct class *class,
5896 struct class_attribute *attr,
5897 const char *buf, size_t size);
5898 static ssize_t dmx_reg_value_show_source(struct class *class,
5899 struct class_attribute *attr,
5900 char *buf);
5901 static ssize_t dmx_reg_value_store_source(struct class *class,
5902 struct class_attribute *attr,
5903 const char *buf, size_t size);
5904 static ssize_t dmx_sec_statistics_show(struct class *class,
5905 struct class_attribute *attr,
5906 char *buf);
5907 static int reg_addr;
5908
5909 static struct class_attribute aml_dmx_class_attrs[] = {
5910 __ATTR(dmx_id, 0644, dmx_id_show_source,
5911 dmx_id_store_source),
5912 __ATTR(register_addr, 0644, dmx_reg_addr_show_source,
5913 dmx_reg_addr_store_source),
5914 __ATTR(register_value, 0644, dmx_reg_value_show_source,
5915 dmx_reg_value_store_source),
5916 __ATTR(tsfile_clkdiv, 0644, stb_get_tsfile_clkdiv,
5917 stb_set_tsfile_clkdiv),
5918
5919 #define DEMUX_SCAMBLE_ATTR_DECL(i)\
5920 __ATTR(demux##i##_scramble, 0644, \
5921 dmx_reg_value_show_demux##i##_scramble, NULL)
5922 #if DMX_DEV_COUNT > 0
5923 DEMUX_SCAMBLE_ATTR_DECL(0),
5924 #endif
5925 #if DMX_DEV_COUNT > 1
5926 DEMUX_SCAMBLE_ATTR_DECL(1),
5927 #endif
5928 #if DMX_DEV_COUNT > 2
5929 DEMUX_SCAMBLE_ATTR_DECL(2),
5930 #endif
5931
5932 __ATTR(dmx_smallsec, 0644,
5933 dmx_smallsec_show,
5934 dmx_smallsec_store),
5935 __ATTR(dmx_timeout, 0644,
5936 dmx_timeout_show,
5937 dmx_timeout_store),
5938 __ATTR(reset_fec_input_ctrl, 0644,
5939 reset_fec_input_ctrl_show,
5940 reset_fec_input_ctrl_store),
5941 __ATTR(ciplus_output_ctrl, 0644,
5942 ciplus_output_ctrl_show,
5943 ciplus_output_ctrl_store),
5944 __ATTR_RO(dmx_sec_statistics),
5945 __ATTR_NULL
5946 };
5947
5948 static struct class aml_dmx_class = {
5949 .name = "dmx",
5950 .class_attrs = aml_dmx_class_attrs,
5951 };
5952
dmx_id_show_source(struct class * class,struct class_attribute * attr,char * buf)5953 static ssize_t dmx_id_show_source(struct class *class,
5954 struct class_attribute *attr, char *buf)
5955 {
5956 int ret;
5957
5958 ret = sprintf(buf, "%d\n", dmx_id);
5959 return ret;
5960 }
5961
dmx_id_store_source(struct class * class,struct class_attribute * attr,const char * buf,size_t size)5962 static ssize_t dmx_id_store_source(struct class *class,
5963 struct class_attribute *attr,
5964 const char *buf, size_t size)
5965 {
5966 int id = 0;
5967 long value = 0;
5968
5969 if (kstrtol(buf, 0, &value) == 0)
5970 id = (int)value;
5971 /*id = simple_strtol(buf, 0, 16);*/
5972
5973 if (id < 0 || id > 2)
5974 pr_dbg("dmx id must 0 ~2\n");
5975 else
5976 dmx_id = id;
5977
5978 return size;
5979 }
5980
dmx_reg_addr_show_source(struct class * class,struct class_attribute * attr,char * buf)5981 static ssize_t dmx_reg_addr_show_source(struct class *class,
5982 struct class_attribute *attr,
5983 char *buf)
5984 {
5985 int ret;
5986
5987 ret = sprintf(buf, "%x\n", reg_addr);
5988 return ret;
5989 }
5990
dmx_reg_addr_store_source(struct class * class,struct class_attribute * attr,const char * buf,size_t size)5991 static ssize_t dmx_reg_addr_store_source(struct class *class,
5992 struct class_attribute *attr,
5993 const char *buf, size_t size)
5994 {
5995 int addr = 0;
5996 /*addr = simple_strtol(buf, 0, 16);*/
5997 long value = 0;
5998
5999 if (kstrtol(buf, 0, &value) == 0)
6000 addr = (int)value;
6001 reg_addr = addr;
6002 return size;
6003 }
6004
dmx_reg_value_show_source(struct class * class,struct class_attribute * attr,char * buf)6005 static ssize_t dmx_reg_value_show_source(struct class *class,
6006 struct class_attribute *attr,
6007 char *buf)
6008 {
6009 int ret, value;
6010
6011 value = READ_MPEG_REG(reg_addr);
6012 ret = sprintf(buf, "%x\n", value);
6013 return ret;
6014 }
6015
dmx_reg_value_store_source(struct class * class,struct class_attribute * attr,const char * buf,size_t size)6016 static ssize_t dmx_reg_value_store_source(struct class *class,
6017 struct class_attribute *attr,
6018 const char *buf, size_t size)
6019 {
6020 int value = 0;
6021 /*value = simple_strtol(buf, 0, 16);*/
6022 long val = 0;
6023
6024 if (kstrtol(buf, 0, &val) == 0)
6025 value = (int)val;
6026 WRITE_MPEG_REG(reg_addr, value);
6027 return size;
6028 }
6029
dmx_sec_statistics_show(struct class * class,struct class_attribute * attr,char * buf)6030 static ssize_t dmx_sec_statistics_show(struct class *class,
6031 struct class_attribute *attr,
6032 char *buf)
6033 {
6034 ssize_t ret;
6035 char tmp[128];
6036 struct aml_dvb *dvb = aml_get_dvb_device();
6037
6038 ret = sprintf(tmp, "[hw]%#lx:%#lx:%#lx\n[sw]%#lx:%#lx:%#lx\n",
6039 dvb->dmx[dmx_id].sec_cnt[SEC_CNT_HW],
6040 dvb->dmx[dmx_id].sec_cnt_match[SEC_CNT_HW],
6041 dvb->dmx[dmx_id].sec_cnt_crc_fail[SEC_CNT_HW],
6042 dvb->dmx[dmx_id].sec_cnt[SEC_CNT_SW],
6043 dvb->dmx[dmx_id].sec_cnt_match[SEC_CNT_SW],
6044 dvb->dmx[dmx_id].sec_cnt_crc_fail[SEC_CNT_SW]);
6045 ret = sprintf(buf, "%s[ss]%#lx:%#lx:%#lx\n",
6046 tmp,
6047 dvb->dmx[dmx_id].sec_cnt[SEC_CNT_SS],
6048 dvb->dmx[dmx_id].sec_cnt_match[SEC_CNT_SS],
6049 dvb->dmx[dmx_id].sec_cnt_crc_fail[SEC_CNT_SS]);
6050 return ret;
6051 }
6052
aml_regist_dmx_class(void)6053 int aml_regist_dmx_class(void)
6054 {
6055
6056 if (class_register(&aml_dmx_class) < 0)
6057 pr_error("register class error\n");
6058
6059 return 0;
6060 }
6061
aml_unregist_dmx_class(void)6062 int aml_unregist_dmx_class(void)
6063 {
6064
6065 class_unregister(&aml_dmx_class);
6066 return 0;
6067 }
6068
6069 static struct mconfig parser_configs[] = {
6070 MC_PU32("video_pts", &video_pts),
6071 MC_PU32("audio_pts", &audio_pts),
6072 MC_PU32("video_pts_bit32", &video_pts_bit32),
6073 MC_PU32("audio_pts_bit32", &audio_pts_bit32),
6074 MC_PU32("first_video_pts", &first_video_pts),
6075 MC_PU32("first_audio_pts", &first_audio_pts),
6076 };
6077
aml_register_parser_mconfig(void)6078 void aml_register_parser_mconfig(void)
6079 {
6080 REG_PATH_CONFIGS("media.parser", parser_configs);
6081 }
6082
6083