1 // Copyright (C) 2022 Beken Corporation 2 // Licensed under the Apache License, Version 2.0 (the "License"); 3 // you may not use this file except in compliance with the License. 4 // You may obtain a copy of the License at 5 // 6 // http://www.apache.org/licenses/LICENSE-2.0 7 // 8 // Unless required by applicable law or agreed to in writing, software 9 // distributed under the License is distributed on an "AS IS" BASIS, 10 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 11 // See the License for the specific language governing permissions and 12 // limitations under the License. 13 14 15 #pragma once 16 17 18 #ifdef __cplusplus 19 extern "C" { 20 #endif 21 22 typedef volatile struct { 23 24 /* REG_0x00 */ 25 union 26 { 27 struct 28 { 29 volatile uint32_t tran_start : 1; //0x0[ 0],dma2d transfer start.,0,RW 30 volatile uint32_t tran_suspend : 1; //0x0[ 1],dma2d transfer start.,0,RW 31 volatile uint32_t tran_abort : 1; //0x0[ 2],dma2d transfer start.,0,RW 32 volatile uint32_t reserved0 : 3; //0x0[ 5: 3],NC,0,RW 33 volatile uint32_t line_offset_mode : 1; //0x0[ 6],line's offset mode sel: 0:in pixel express; 1: in bytes express.,0,RW 34 volatile uint32_t reserved1 : 1; //0x0[ 7],NC,0,RW 35 volatile uint32_t error_int_en : 1; //0x0[ 8],trabsfer error int ena.,0,RW 36 volatile uint32_t complete_int_en : 1; //0x0[ 9],transfer complete int ena.,0,RW 37 volatile uint32_t waterm_int_en : 1; //0x0[ 10],transfer watermark int ena.,0,RW 38 volatile uint32_t clut_error_int_en : 1; //0x0[ 11],clut transfer error int ena.,0,RW 39 volatile uint32_t clut_cmplt_int_en : 1; //0x0[ 12],clut transfer complete int ena.,0,RW 40 volatile uint32_t config_error_int_en : 1; //0x0[ 13],config error int ena,,0,RW 41 volatile uint32_t reserved2 : 2; //0x0[15:14],NC,0,R 42 volatile uint32_t mode : 3; //0x0[18:16],DMA2D mode sel: 000:m2m; 001:m2m pixel convert with fg; 010:m2m blend; 011:r2m.only with output; 100: m2m blend fix fg; 101:m2m blend fix bg;,0,RW 43 volatile uint32_t master_tran_length :2; //0x0[20:19],RW max transfer length:00:256bytes; 01:192 bytes; 10:128bytes; 11:64bytes; 44 volatile uint32_t out_byte_revese :1; //0x0[21],RW output rgb888 formart, reverse data byte by byte. 45 volatile uint32_t reserved :13; //0x0[31:21],NC,0,R 46 }; 47 uint32_t v; 48 }dma2d_control_reg; 49 50 /* REG_0x01 */ 51 union 52 { 53 struct 54 { 55 volatile uint32_t error_int : 1; //0x1[ 0],transfer error int flag.,0,R 56 volatile uint32_t complete_int : 1; //0x1[ 1],transfer complete int flag.,0,R 57 volatile uint32_t waterm_int : 1; //0x1[ 2],transfer watermark intt flag.,0,R 58 volatile uint32_t clut_error_int : 1; //0x1[ 3],clut transfer error intt flag.,0,R 59 volatile uint32_t clut_cmplt_int : 1; //0x1[ 4],clut transfer complete intt flag.,0,R 60 volatile uint32_t config_error_int : 1; //0x1[ 5],config error int t flag.,0,R 61 volatile uint32_t reserved :26; //0x1[31: 6],NC,0,R 62 }; 63 uint32_t v; 64 }dma2d_int_status; 65 66 /* REG_0x02 */ 67 union 68 { 69 struct 70 { 71 volatile uint32_t clr_error_int : 1; //0x2[ 0],clear transfer error int flag.,0,W 72 volatile uint32_t clr_complete_int : 1; //0x2[ 1],clear transfer complete int flag.,0,W 73 volatile uint32_t clr_waterm_int : 1; //0x2[ 2],clear transfer watermark intt flag.,0,W 74 volatile uint32_t clr_clut_error_int : 1; //0x2[ 3],clear clut transfer error intt flag.,0,W 75 volatile uint32_t clr_clut_cmplt_int : 1; //0x2[ 4],clear clut transfer complete intt flag.,0,W 76 volatile uint32_t clr_config_error_int : 1; //0x2[ 5],clear config error int t flag.,0,W 77 volatile uint32_t reserved :26; //0x2[31: 6],NC,0,W 78 }; 79 uint32_t v; 80 }dma2d_int_clear; 81 82 /* REG_0x03 */ 83 union 84 { 85 struct 86 { 87 volatile uint32_t fg_address :32; //0x3[31: 0],foreground mem address, written when transfer disable.,0,RW 88 }; 89 uint32_t v; 90 }dma2d_fg_address; 91 92 /* REG_0x04 */ 93 union 94 { 95 struct 96 { 97 volatile uint32_t fg_line_offset :16; //0x4[15: 0],line offset for fg, offset In pixel or bytes.,0,RW 98 volatile uint32_t reserved :16; //0x4[31:16],NC,0,RW 99 }; 100 uint32_t v; 101 }dma2d_fg_offset; 102 103 /* REG_0x05 */ 104 union 105 { 106 struct 107 { 108 volatile uint32_t bg_address :32; //0x5[31: 0],background mem address, written when transfer disable.,0,RW 109 }; 110 uint32_t v; 111 }dma2d_bg_address; 112 113 /* REG_0x06 */ 114 union 115 { 116 struct 117 { 118 volatile uint32_t bg_line_offset :16; //0x6[15: 0],line offset for bg, offset In pixel or bytes.,0,RW 119 volatile uint32_t reserved :16; //0x6[31:16],NC,0,RW 120 }; 121 uint32_t v; 122 }dma2d_bg_offset; 123 124 /* REG_0x07 */ 125 union 126 { 127 struct 128 { 129 volatile uint32_t fg_color_mode : 4; //0x7[ 3: 0],foreground image color mode.; 0000:ARGB888;0001:RGB888;0010:RGB565;0011:ARGB1555;0100:ARGB4444; 0101:L8;0110:AL44; 0111:AL88; 1000:L4; 1001:A8;1010:A4;,0,RW 130 volatile uint32_t fg_clut_color_mode : 1; //0x7[ 4],color mode for clut. 0:argb8888; 1:rgb888.,0,RW 131 volatile uint32_t fg_start_clut : 1; //0x7[ 5],automatic load the clut. Automatic reset.,0,RW 132 volatile uint32_t reserved0 : 2; //0x7[ 7: 6],NC,0,RW 133 volatile uint32_t fg_clut_size : 8; //0x7[15: 8],the size of clut used for foreground image. Size = fg_clut_size + 1;,0,RW 134 volatile uint32_t fg_alpha_mode : 2; //0x7[17:16],alpha value use for fg image. 00: nochange; 01:replace orginal, 10: alpha[7:0] multipied with orginal value.,0,RW 135 volatile uint32_t reserved1 : 2; //0x7[19:18],NC,0,RW 136 volatile uint32_t alpha_invert : 1; //0x7[ 20],invert alpha value.,0,RW 137 volatile uint32_t fg_rb_swap : 1; //0x7[ 21],red blue swap to support rgb or argb. 0: regular mode.1:swap_mode.,0,RW 138 volatile uint32_t reserved : 2; //0x7[23:22],NC,0,RW 139 volatile uint32_t fg_alpha : 8; //0x7[31:24],fg alpha value set. Use with fg_alpha_mode.,0,RW 140 }; 141 uint32_t v; 142 }dma2d_fg_pfc_ctrl; 143 144 /* REG_0x08 */ 145 union 146 { 147 struct 148 { 149 volatile uint32_t blue_value : 8; //0x8[ 7: 0],blue_value in a4 or a8 mode of fg,,0,RW 150 volatile uint32_t green_value : 8; //0x8[15: 8],green_value in a4 or a8 mode of fg,,0,RW 151 volatile uint32_t red_value : 8; //0x8[23:16],red_value in a4 or a8 mode of fg,,0,RW 152 volatile uint32_t reserved : 8; //0x8[31:24],NC,0,RW 153 }; 154 uint32_t v; 155 }dma2d_fg_color_reg; 156 157 /* REG_0x09 */ 158 union 159 { 160 struct 161 { 162 volatile uint32_t bg_color_mode : 4; //0x9[ 3: 0],background image color mode.; 0000:ARGB888;0001:RGB888;0010:RGB565;0011:ARGB1555;0100:ARGB4444; 0101:L8;0110:AL44; 0111:AL88; 1000:L4; 1001:A8;1010:A4;,0,RW 163 volatile uint32_t bg_clut_color_mode : 1; //0x9[ 4],color mode for clut. 0:argb8888; 1:rgb888.,0,RW 164 volatile uint32_t bg_start_clut : 1; //0x9[ 5],automatic load the clut. Automatic reset.,0,RW 165 volatile uint32_t reserved0 : 2; //0x9[ 7: 6],NC,0,RW 166 volatile uint32_t bg_clut_size : 8; //0x9[15: 8],the size of clut used for background image. Size = fg_clut_size + 1;,0,RW 167 volatile uint32_t bg_alpha_mode : 2; //0x9[17:16],alpha value use for fg image. 00: nochange; 01:replace orginal, 10: alpha[7:0] multipied with orginal value.,0,RW 168 volatile uint32_t reserved1 : 2; //0x9[19:18],NC,0,RW 169 volatile uint32_t alpha_invert : 1; //0x9[ 20],invert alpha value.,0,RW 170 volatile uint32_t bg_rb_swap : 1; //0x9[ 21],red blue swap to support rgb or argb. 0: regular mode.1:swap_mode.,0,RW 171 volatile uint32_t reserved : 2; //0x9[23:22],NC,0,RW 172 volatile uint32_t bg_alpha : 8; //0x9[31:24],bg alpha value set. Use withbg_alpha_mode.,0,RW 173 }; 174 uint32_t v; 175 }dma2d_bg_pfc_ctrl; 176 177 /* REG_0x0a */ 178 union 179 { 180 struct 181 { 182 volatile uint32_t blue_value : 8; //0xa[ 7: 0],blue_value in a4 or a8 mode of bg,,0,RW 183 volatile uint32_t green_value : 8; //0xa[15: 8],green_value in a4 or a8 mode of bg,,0,RW 184 volatile uint32_t red_value : 8; //0xa[23:16],red_value in a4 or a8 mode of bg,,0,RW 185 volatile uint32_t reserved : 8; //0xa[31:24],NC,0,RW 186 }; 187 uint32_t v; 188 }dma2d_bg_color_reg; 189 190 /* REG_0x0b */ 191 union 192 { 193 struct 194 { 195 volatile uint32_t fg_clut_address :32; //0xb[31: 0],clut data dedicated to the fg image.,0,RW 196 }; 197 uint32_t v; 198 }fg_clut_mem_address; 199 200 /* REG_0x0c */ 201 union 202 { 203 struct 204 { 205 volatile uint32_t bg_clut_address :32; //0xc[31: 0],clut data dedicated to the bg image.,0,RW 206 }; 207 uint32_t v; 208 }bg_clut_mem_address; 209 210 /* REG_0x0d */ 211 union 212 { 213 struct 214 { 215 volatile uint32_t out_color_mode : 3; //0xd[ 2: 0],format of output image.0:argb888; 1:rgb888; 010:rgb565; 011:argb1555; 100:argb444,0,RW 216 volatile uint32_t reserved0 : 6; //0xd[ 8: 3],NC,0,RW 217 volatile uint32_t out_swap_bytes : 1; //0xd[ 9],0:bytes in regular order. 1:bytes swaped two by two in output fifo.,0,RW 218 volatile uint32_t reserved1 :10; //0xd[19:10],NC,0,RW 219 volatile uint32_t out_alpha_invert :1; //0xd[ 20],invert alpha value.,0,RW 220 volatile uint32_t out_rb_swap : 1; //0xd[ 21],ed blue swap to support rgb or argb. 0: regular mode.1:swap_mode.,0,RW 221 volatile uint32_t reserved :10; //0xd[31:22],NC,0,RW 222 }; 223 uint32_t v; 224 }out_pfc_contrl; 225 226 /* REG_0x0e */ 227 union 228 { 229 struct 230 { 231 volatile uint32_t output_clor_reg :32; //0xe[31: 0],output reg, in different color mode. Output is different.; Argb888 or rgb888: alpha[31:24];red[23:16]; green[15:8];blue[7:0].; Rgb565:red[15:11]; green[12:5]; blue[4:0];; argb1555:a[15];red[14:10]; green[4:0]; blue[4:0];; argb4444:alpha[15:12];red[11:8];green[7:4];blue[3;0].,0,RW 232 }; 233 uint32_t v; 234 }out_color_reg; 235 236 /* REG_0x0f */ 237 union 238 { 239 struct 240 { 241 volatile uint32_t out_mem_address :32; //0xf[31: 0],address of data output fifo.,0,RW 242 }; 243 uint32_t v; 244 }dma2d_out_mem_address; 245 246 /* REG_0x10 */ 247 union 248 { 249 struct 250 { 251 volatile uint32_t out_line_offset :16; //0x10[15: 0],output line offset. Offfset with bytes or pixel.in pixel[15:14] ignored.,0,RW 252 volatile uint32_t reserved :16; //0x10[31:16],NC,0,R 253 }; 254 uint32_t v; 255 }output_offset; 256 257 /* REG_0x11 */ 258 union 259 { 260 struct 261 { 262 volatile uint32_t number_line :16; //0x11[15: 0],X PIXEL.,0,RW 263 volatile uint32_t pixel_line :14; //0x11[29:16],Y_PIXEL.,None,RW 264 volatile uint32_t reserved : 2; //0x11[31:30],NC,0,RW 265 }; 266 uint32_t v; 267 }dma2d_number_of_line; 268 269 /* REG_0x12 */ 270 union 271 { 272 struct 273 { 274 volatile uint32_t line_watermark :16; //0x12[15: 0],config the line watermark int generation, transfer reach the watermark, int hold on.,0,RW 275 volatile uint32_t reserved :16; //0x12[31:16],NC,0,RW 276 }; 277 uint32_t v; 278 }dma2d_line_watermark; 279 280 /* REG_0x13 */ 281 union 282 { 283 struct 284 { 285 volatile uint32_t master_time_en : 1; //0x18[ 0],enable dead time function.,0,RW 286 volatile uint32_t reserved0 : 7; //0x18[ 7: 1],NC,0,RW 287 volatile uint32_t dead_time : 8; //0x18[15: 8],dead time value in ahb clock cycle inserted between two consecutive accesses on ahb master.,0,RW 288 volatile uint32_t reserved :16; //0x18[31:16],NC,0,RW 289 }; 290 uint32_t v; 291 }dma2d_master_time_config; 292 293 /* REG_0x14 ~0xff offset 0x50 ~0x3fc reserved*/ 294 union 295 { 296 struct 297 { 298 volatile uint32_t reserved:32; 299 }; 300 uint32_t v; 301 }reg_0x14_reserved; 302 303 union 304 { 305 struct 306 { 307 volatile uint32_t reserved:32; 308 }; 309 uint32_t v; 310 }reg_0x15_reserved; 311 312 union 313 { 314 struct 315 { 316 volatile uint32_t reserved:32; 317 }; 318 uint32_t v; 319 }reg_0x16_reserved; 320 321 union 322 { 323 struct 324 { 325 volatile uint32_t reserved:32; 326 }; 327 uint32_t v; 328 }reg_0x17_reserved; 329 330 union 331 { 332 struct 333 { 334 volatile uint32_t reserved:32; 335 }; 336 uint32_t v; 337 }reg_0x18_reserved; 338 339 340 /* REG_0x19*/ 341 union 342 { 343 struct 344 { 345 volatile uint32_t reserved:32; 346 }; 347 uint32_t v; 348 }reg_0x19_reserved; 349 350 /* REG_0x1a */ 351 union 352 { 353 struct 354 { 355 volatile uint32_t reserved:32; 356 }; 357 uint32_t v; 358 }reg_0x1a_reserved; 359 360 /* REG_0x1b */ 361 union 362 { 363 struct 364 { 365 volatile uint32_t reserved:32; 366 }; 367 uint32_t v; 368 }reg_0x1b_reserved; 369 370 /* REG_0x1c */ 371 union 372 { 373 struct 374 { 375 volatile uint32_t reserved:32; 376 }; 377 uint32_t v; 378 }reg_0x1c_reserved; 379 380 /* REG_0x1d */ 381 union 382 { 383 struct 384 { 385 volatile uint32_t reserved:32; 386 }; 387 uint32_t v; 388 }reg_0x1d_reserved; 389 390 /* REG_0x1e */ 391 union 392 { 393 struct 394 { 395 volatile uint32_t reserved:32; 396 }; 397 uint32_t v; 398 }reg_0x1e_reserved; 399 400 /* REG_0x1f */ 401 union 402 { 403 struct 404 { 405 volatile uint32_t reserved:32; 406 }; 407 uint32_t v; 408 }reg_0x1f_reserved; 409 410 /* REG_0x20 */ 411 union 412 { 413 struct 414 { 415 volatile uint32_t reserved:32; 416 }; 417 uint32_t v; 418 }reg_0x20_reserved; 419 420 /* REG_0x21 */ 421 union 422 { 423 struct 424 { 425 volatile uint32_t reserved:32; 426 }; 427 uint32_t v; 428 }reg_0x21_reserved; 429 430 /* REG_0x22 */ 431 union 432 { 433 struct 434 { 435 volatile uint32_t reserved:32; 436 }; 437 uint32_t v; 438 }reg_0x22_reserved; 439 440 /* REG_0x23 */ 441 union 442 { 443 struct 444 { 445 volatile uint32_t reserved:32; 446 }; 447 uint32_t v; 448 }reg_0x23_reserved; 449 450 /* REG_0x24 */ 451 union 452 { 453 struct 454 { 455 volatile uint32_t reserved:32; 456 }; 457 uint32_t v; 458 }reg_0x24_reserved; 459 460 /* REG_0x25 */ 461 union 462 { 463 struct 464 { 465 volatile uint32_t reserved:32; 466 }; 467 uint32_t v; 468 }reg_0x25_reserved; 469 470 /* REG_0x26 */ 471 union 472 { 473 struct 474 { 475 volatile uint32_t reserved:32; 476 }; 477 uint32_t v; 478 }reg_0x26_reserved; 479 480 /* REG_0x27 */ 481 union 482 { 483 struct 484 { 485 volatile uint32_t reserved:32; 486 }; 487 uint32_t v; 488 }reg_0x27_reserved; 489 490 /* REG_0x28 */ 491 union 492 { 493 struct 494 { 495 volatile uint32_t reserved:32; 496 }; 497 uint32_t v; 498 }reg_0x28_reserved; 499 500 /* REG_0x29 */ 501 union 502 { 503 struct 504 { 505 volatile uint32_t reserved:32; 506 }; 507 uint32_t v; 508 }reg_0x29_reserved; 509 510 /* REG_0x2a */ 511 union 512 { 513 struct 514 { 515 volatile uint32_t reserved:32; 516 }; 517 uint32_t v; 518 }reg_0x2a_reserved; 519 520 /* REG_0x2b */ 521 union 522 { 523 struct 524 { 525 volatile uint32_t reserved:32; 526 }; 527 uint32_t v; 528 }reg_0x2b_reserved; 529 530 /* REG_0x2c */ 531 union 532 { 533 struct 534 { 535 volatile uint32_t reserved:32; 536 }; 537 uint32_t v; 538 }reg_0x2c_reserved; 539 540 /* REG_0x2d */ 541 union 542 { 543 struct 544 { 545 volatile uint32_t reserved:32; 546 }; 547 uint32_t v; 548 }reg_0x2d_reserved; 549 550 /* REG_0x2e */ 551 union 552 { 553 struct 554 { 555 volatile uint32_t reserved:32; 556 }; 557 uint32_t v; 558 }reg_0x2e_reserved; 559 560 /* REG_0x2f */ 561 union 562 { 563 struct 564 { 565 volatile uint32_t reserved:32; 566 }; 567 uint32_t v; 568 }reg_0x2f_reserved; 569 570 /* REG_0x30 */ 571 union 572 { 573 struct 574 { 575 volatile uint32_t reserved:32; 576 }; 577 uint32_t v; 578 }reg_0x30_reserved; 579 580 /* REG_0x31 */ 581 union 582 { 583 struct 584 { 585 volatile uint32_t reserved:32; 586 }; 587 uint32_t v; 588 }reg_0x31_reserved; 589 590 /* REG_0x32 */ 591 union 592 { 593 struct 594 { 595 volatile uint32_t reserved:32; 596 }; 597 uint32_t v; 598 }reg_0x32_reserved; 599 600 /* REG_0x33 */ 601 union 602 { 603 struct 604 { 605 volatile uint32_t reserved:32; 606 }; 607 uint32_t v; 608 }reg_0x33_reserved; 609 610 /* REG_0x34 */ 611 union 612 { 613 struct 614 { 615 volatile uint32_t reserved:32; 616 }; 617 uint32_t v; 618 }reg_0x34_reserved; 619 620 /* REG_0x35 */ 621 union 622 { 623 struct 624 { 625 volatile uint32_t reserved:32; 626 }; 627 uint32_t v; 628 }reg_0x35_reserved; 629 630 /* REG_0x36 */ 631 union 632 { 633 struct 634 { 635 volatile uint32_t reserved:32; 636 }; 637 uint32_t v; 638 }reg_0x36_reserved; 639 640 /* REG_0x37 */ 641 union 642 { 643 struct 644 { 645 volatile uint32_t reserved:32; 646 }; 647 uint32_t v; 648 }reg_0x37_reserved; 649 650 /* REG_0x38 */ 651 union 652 { 653 struct 654 { 655 volatile uint32_t reserved:32; 656 }; 657 uint32_t v; 658 }reg_0x38_reserved; 659 660 /* REG_0x39 */ 661 union 662 { 663 struct 664 { 665 volatile uint32_t reserved:32; 666 }; 667 uint32_t v; 668 }reg_0x39_reserved; 669 670 /* REG_0x3a */ 671 union 672 { 673 struct 674 { 675 volatile uint32_t reserved:32; 676 }; 677 uint32_t v; 678 }reg_0x3a_reserved; 679 680 /* REG_0x3b */ 681 union 682 { 683 struct 684 { 685 volatile uint32_t reserved:32; 686 }; 687 uint32_t v; 688 }reg_0x3b_reserved; 689 690 /* REG_0x3c */ 691 union 692 { 693 struct 694 { 695 volatile uint32_t reserved:32; 696 }; 697 uint32_t v; 698 }reg_0x3c_reserved; 699 700 /* REG_0x3d */ 701 union 702 { 703 struct 704 { 705 volatile uint32_t reserved:32; 706 }; 707 uint32_t v; 708 }reg_0x3d_reserved; 709 710 /* REG_0x3e */ 711 union 712 { 713 struct 714 { 715 volatile uint32_t reserved:32; 716 }; 717 uint32_t v; 718 }reg_0x3e_reserved; 719 720 /* REG_0x3f */ 721 union 722 { 723 struct 724 { 725 volatile uint32_t reserved:32; 726 }; 727 uint32_t v; 728 }reg_0x3f_reserved; 729 730 /* REG_0x40 */ 731 union 732 { 733 struct 734 { 735 volatile uint32_t reserved:32; 736 }; 737 uint32_t v; 738 }reg_0x40_reserved; 739 740 /* REG_0x41 */ 741 union 742 { 743 struct 744 { 745 volatile uint32_t reserved:32; 746 }; 747 uint32_t v; 748 }reg_0x41_reserved; 749 750 /* REG_0x42 */ 751 union 752 { 753 struct 754 { 755 volatile uint32_t reserved:32; 756 }; 757 uint32_t v; 758 }reg_0x42_reserved; 759 760 /* REG_0x43 */ 761 union 762 { 763 struct 764 { 765 volatile uint32_t reserved:32; 766 }; 767 uint32_t v; 768 }reg_0x43_reserved; 769 770 /* REG_0x44 */ 771 union 772 { 773 struct 774 { 775 volatile uint32_t reserved:32; 776 }; 777 uint32_t v; 778 }reg_0x44_reserved; 779 780 /* REG_0x45 */ 781 union 782 { 783 struct 784 { 785 volatile uint32_t reserved:32; 786 }; 787 uint32_t v; 788 }reg_0x45_reserved; 789 790 /* REG_0x46 */ 791 union 792 { 793 struct 794 { 795 volatile uint32_t reserved:32; 796 }; 797 uint32_t v; 798 }reg_0x46_reserved; 799 800 /* REG_0x47 */ 801 union 802 { 803 struct 804 { 805 volatile uint32_t reserved:32; 806 }; 807 uint32_t v; 808 }reg_0x47_reserved; 809 810 /* REG_0x48 */ 811 union 812 { 813 struct 814 { 815 volatile uint32_t reserved:32; 816 }; 817 uint32_t v; 818 }reg_0x48_reserved; 819 820 /* REG_0x49 */ 821 union 822 { 823 struct 824 { 825 volatile uint32_t reserved:32; 826 }; 827 uint32_t v; 828 }reg_0x49_reserved; 829 830 /* REG_0x4a */ 831 union 832 { 833 struct 834 { 835 volatile uint32_t reserved:32; 836 }; 837 uint32_t v; 838 }reg_0x4a_reserved; 839 840 /* REG_0x4b */ 841 union 842 { 843 struct 844 { 845 volatile uint32_t reserved:32; 846 }; 847 uint32_t v; 848 }reg_0x4b_reserved; 849 850 /* REG_0x4c */ 851 union 852 { 853 struct 854 { 855 volatile uint32_t reserved:32; 856 }; 857 uint32_t v; 858 }reg_0x4c_reserved; 859 860 /* REG_0x4d */ 861 union 862 { 863 struct 864 { 865 volatile uint32_t reserved:32; 866 }; 867 uint32_t v; 868 }reg_0x4d_reserved; 869 870 /* REG_0x4e */ 871 union 872 { 873 struct 874 { 875 volatile uint32_t reserved:32; 876 }; 877 uint32_t v; 878 }reg_0x4e_reserved; 879 880 /* REG_0x4f */ 881 union 882 { 883 struct 884 { 885 volatile uint32_t reserved:32; 886 }; 887 uint32_t v; 888 }reg_0x4f_reserved; 889 890 /* REG_0x50 */ 891 union 892 { 893 struct 894 { 895 volatile uint32_t reserved:32; 896 }; 897 uint32_t v; 898 }reg_0x50_reserved; 899 900 /* REG_0x51 */ 901 union 902 { 903 struct 904 { 905 volatile uint32_t reserved:32; 906 }; 907 uint32_t v; 908 }reg_0x51_reserved; 909 910 /* REG_0x52 */ 911 union 912 { 913 struct 914 { 915 volatile uint32_t reserved:32; 916 }; 917 uint32_t v; 918 }reg_0x52_reserved; 919 920 /* REG_0x53 */ 921 union 922 { 923 struct 924 { 925 volatile uint32_t reserved:32; 926 }; 927 uint32_t v; 928 }reg_0x53_reserved; 929 930 /* REG_0x54 */ 931 union 932 { 933 struct 934 { 935 volatile uint32_t reserved:32; 936 }; 937 uint32_t v; 938 }reg_0x54_reserved; 939 940 /* REG_0x55 */ 941 union 942 { 943 struct 944 { 945 volatile uint32_t reserved:32; 946 }; 947 uint32_t v; 948 }reg_0x55_reserved; 949 950 /* REG_0x56 */ 951 union 952 { 953 struct 954 { 955 volatile uint32_t reserved:32; 956 }; 957 uint32_t v; 958 }reg_0x56_reserved; 959 960 /* REG_0x57 */ 961 union 962 { 963 struct 964 { 965 volatile uint32_t reserved:32; 966 }; 967 uint32_t v; 968 }reg_0x57_reserved; 969 970 /* REG_0x58 */ 971 union 972 { 973 struct 974 { 975 volatile uint32_t reserved:32; 976 }; 977 uint32_t v; 978 }reg_0x58_reserved; 979 980 /* REG_0x59 */ 981 union 982 { 983 struct 984 { 985 volatile uint32_t reserved:32; 986 }; 987 uint32_t v; 988 }reg_0x59_reserved; 989 990 /* REG_0x5a */ 991 union 992 { 993 struct 994 { 995 volatile uint32_t reserved:32; 996 }; 997 uint32_t v; 998 }reg_0x5a_reserved; 999 1000 /* REG_0x5b */ 1001 union 1002 { 1003 struct 1004 { 1005 volatile uint32_t reserved:32; 1006 }; 1007 uint32_t v; 1008 }reg_0x5b_reserved; 1009 1010 /* REG_0x5c */ 1011 union 1012 { 1013 struct 1014 { 1015 volatile uint32_t reserved:32; 1016 }; 1017 uint32_t v; 1018 }reg_0x5c_reserved; 1019 1020 /* REG_0x5d */ 1021 union 1022 { 1023 struct 1024 { 1025 volatile uint32_t reserved:32; 1026 }; 1027 uint32_t v; 1028 }reg_0x5d_reserved; 1029 1030 /* REG_0x5e */ 1031 union 1032 { 1033 struct 1034 { 1035 volatile uint32_t reserved:32; 1036 }; 1037 uint32_t v; 1038 }reg_0x5e_reserved; 1039 1040 /* REG_0x5f */ 1041 union 1042 { 1043 struct 1044 { 1045 volatile uint32_t reserved:32; 1046 }; 1047 uint32_t v; 1048 }reg_0x5f_reserved; 1049 1050 /* REG_0x60 */ 1051 union 1052 { 1053 struct 1054 { 1055 volatile uint32_t reserved:32; 1056 }; 1057 uint32_t v; 1058 }reg_0x60_reserved; 1059 1060 /* REG_0x61 */ 1061 union 1062 { 1063 struct 1064 { 1065 volatile uint32_t reserved:32; 1066 }; 1067 uint32_t v; 1068 }reg_0x61_reserved; 1069 1070 /* REG_0x62 */ 1071 union 1072 { 1073 struct 1074 { 1075 volatile uint32_t reserved:32; 1076 }; 1077 uint32_t v; 1078 }reg_0x62_reserved; 1079 1080 /* REG_0x63 */ 1081 union 1082 { 1083 struct 1084 { 1085 volatile uint32_t reserved:32; 1086 }; 1087 uint32_t v; 1088 }reg_0x63_reserved; 1089 1090 /* REG_0x64 */ 1091 union 1092 { 1093 struct 1094 { 1095 volatile uint32_t reserved:32; 1096 }; 1097 uint32_t v; 1098 }reg_0x64_reserved; 1099 1100 /* REG_0x65 */ 1101 union 1102 { 1103 struct 1104 { 1105 volatile uint32_t reserved:32; 1106 }; 1107 uint32_t v; 1108 }reg_0x65_reserved; 1109 1110 /* REG_0x66 */ 1111 union 1112 { 1113 struct 1114 { 1115 volatile uint32_t reserved:32; 1116 }; 1117 uint32_t v; 1118 }reg_0x66_reserved; 1119 1120 /* REG_0x67 */ 1121 union 1122 { 1123 struct 1124 { 1125 volatile uint32_t reserved:32; 1126 }; 1127 uint32_t v; 1128 }reg_0x67_reserved; 1129 1130 /* REG_0x68 */ 1131 union 1132 { 1133 struct 1134 { 1135 volatile uint32_t reserved:32; 1136 }; 1137 uint32_t v; 1138 }reg_0x68_reserved; 1139 1140 /* REG_0x69 */ 1141 union 1142 { 1143 struct 1144 { 1145 volatile uint32_t reserved:32; 1146 }; 1147 uint32_t v; 1148 }reg_0x69_reserved; 1149 1150 /* REG_0x6a */ 1151 union 1152 { 1153 struct 1154 { 1155 volatile uint32_t reserved:32; 1156 }; 1157 uint32_t v; 1158 }reg_0x6a_reserved; 1159 1160 /* REG_0x6b */ 1161 union 1162 { 1163 struct 1164 { 1165 volatile uint32_t reserved:32; 1166 }; 1167 uint32_t v; 1168 }reg_0x6b_reserved; 1169 1170 /* REG_0x6c */ 1171 union 1172 { 1173 struct 1174 { 1175 volatile uint32_t reserved:32; 1176 }; 1177 uint32_t v; 1178 }reg_0x6c_reserved; 1179 1180 /* REG_0x6d */ 1181 union 1182 { 1183 struct 1184 { 1185 volatile uint32_t reserved:32; 1186 }; 1187 uint32_t v; 1188 }reg_0x6d_reserved; 1189 1190 /* REG_0x6e */ 1191 union 1192 { 1193 struct 1194 { 1195 volatile uint32_t reserved:32; 1196 }; 1197 uint32_t v; 1198 }reg_0x6e_reserved; 1199 1200 /* REG_0x6f */ 1201 union 1202 { 1203 struct 1204 { 1205 volatile uint32_t reserved:32; 1206 }; 1207 uint32_t v; 1208 }reg_0x6f_reserved; 1209 1210 /* REG_0x70 */ 1211 union 1212 { 1213 struct 1214 { 1215 volatile uint32_t reserved:32; 1216 }; 1217 uint32_t v; 1218 }reg_0x70_reserved; 1219 1220 /* REG_0x71 */ 1221 union 1222 { 1223 struct 1224 { 1225 volatile uint32_t reserved:32; 1226 }; 1227 uint32_t v; 1228 }reg_0x71_reserved; 1229 1230 /* REG_0x72 */ 1231 union 1232 { 1233 struct 1234 { 1235 volatile uint32_t reserved:32; 1236 }; 1237 uint32_t v; 1238 }reg_0x72_reserved; 1239 1240 /* REG_0x73 */ 1241 union 1242 { 1243 struct 1244 { 1245 volatile uint32_t reserved:32; 1246 }; 1247 uint32_t v; 1248 }reg_0x73_reserved; 1249 1250 /* REG_0x74 */ 1251 union 1252 { 1253 struct 1254 { 1255 volatile uint32_t reserved:32; 1256 }; 1257 uint32_t v; 1258 }reg_0x74_reserved; 1259 1260 /* REG_0x75 */ 1261 union 1262 { 1263 struct 1264 { 1265 volatile uint32_t reserved:32; 1266 }; 1267 uint32_t v; 1268 }reg_0x75_reserved; 1269 1270 /* REG_0x76 */ 1271 union 1272 { 1273 struct 1274 { 1275 volatile uint32_t reserved:32; 1276 }; 1277 uint32_t v; 1278 }reg_0x76_reserved; 1279 1280 /* REG_0x77 */ 1281 union 1282 { 1283 struct 1284 { 1285 volatile uint32_t reserved:32; 1286 }; 1287 uint32_t v; 1288 }reg_0x77_reserved; 1289 1290 /* REG_0x78 */ 1291 union 1292 { 1293 struct 1294 { 1295 volatile uint32_t reserved:32; 1296 }; 1297 uint32_t v; 1298 }reg_0x78_reserved; 1299 1300 /* REG_0x79 */ 1301 union 1302 { 1303 struct 1304 { 1305 volatile uint32_t reserved:32; 1306 }; 1307 uint32_t v; 1308 }reg_0x79_reserved; 1309 1310 /* REG_0x7a */ 1311 union 1312 { 1313 struct 1314 { 1315 volatile uint32_t reserved:32; 1316 }; 1317 uint32_t v; 1318 }reg_0x7a_reserved; 1319 1320 /* REG_0x7b */ 1321 union 1322 { 1323 struct 1324 { 1325 volatile uint32_t reserved:32; 1326 }; 1327 uint32_t v; 1328 }reg_0x7b_reserved; 1329 1330 /* REG_0x7c */ 1331 union 1332 { 1333 struct 1334 { 1335 volatile uint32_t reserved:32; 1336 }; 1337 uint32_t v; 1338 }reg_0x7c_reserved; 1339 1340 /* REG_0x7d */ 1341 union 1342 { 1343 struct 1344 { 1345 volatile uint32_t reserved:32; 1346 }; 1347 uint32_t v; 1348 }reg_0x7d_reserved; 1349 1350 /* REG_0x7e */ 1351 union 1352 { 1353 struct 1354 { 1355 volatile uint32_t reserved:32; 1356 }; 1357 uint32_t v; 1358 }reg_0x7e_reserved; 1359 1360 /* REG_0x7f */ 1361 union 1362 { 1363 struct 1364 { 1365 volatile uint32_t reserved:32; 1366 }; 1367 uint32_t v; 1368 }reg_0x7f_reserved; 1369 1370 /* REG_0x80 */ 1371 union 1372 { 1373 struct 1374 { 1375 volatile uint32_t reserved:32; 1376 }; 1377 uint32_t v; 1378 }reg_0x80_reserved; 1379 1380 /* REG_0x81 */ 1381 union 1382 { 1383 struct 1384 { 1385 volatile uint32_t reserved:32; 1386 }; 1387 uint32_t v; 1388 }reg_0x81_reserved; 1389 1390 /* REG_0x82 */ 1391 union 1392 { 1393 struct 1394 { 1395 volatile uint32_t reserved:32; 1396 }; 1397 uint32_t v; 1398 }reg_0x82_reserved; 1399 1400 /* REG_0x83 */ 1401 union 1402 { 1403 struct 1404 { 1405 volatile uint32_t reserved:32; 1406 }; 1407 uint32_t v; 1408 }reg_0x83_reserved; 1409 1410 /* REG_0x84 */ 1411 union 1412 { 1413 struct 1414 { 1415 volatile uint32_t reserved:32; 1416 }; 1417 uint32_t v; 1418 }reg_0x84_reserved; 1419 1420 /* REG_0x85 */ 1421 union 1422 { 1423 struct 1424 { 1425 volatile uint32_t reserved:32; 1426 }; 1427 uint32_t v; 1428 }reg_0x85_reserved; 1429 1430 /* REG_0x86 */ 1431 union 1432 { 1433 struct 1434 { 1435 volatile uint32_t reserved:32; 1436 }; 1437 uint32_t v; 1438 }reg_0x86_reserved; 1439 1440 /* REG_0x87 */ 1441 union 1442 { 1443 struct 1444 { 1445 volatile uint32_t reserved:32; 1446 }; 1447 uint32_t v; 1448 }reg_0x87_reserved; 1449 1450 /* REG_0x88 */ 1451 union 1452 { 1453 struct 1454 { 1455 volatile uint32_t reserved:32; 1456 }; 1457 uint32_t v; 1458 }reg_0x88_reserved; 1459 1460 /* REG_0x89 */ 1461 union 1462 { 1463 struct 1464 { 1465 volatile uint32_t reserved:32; 1466 }; 1467 uint32_t v; 1468 }reg_0x89_reserved; 1469 1470 /* REG_0x8a */ 1471 union 1472 { 1473 struct 1474 { 1475 volatile uint32_t reserved:32; 1476 }; 1477 uint32_t v; 1478 }reg_0x8a_reserved; 1479 1480 /* REG_0x8b */ 1481 union 1482 { 1483 struct 1484 { 1485 volatile uint32_t reserved:32; 1486 }; 1487 uint32_t v; 1488 }reg_0x8b_reserved; 1489 1490 /* REG_0x8c */ 1491 union 1492 { 1493 struct 1494 { 1495 volatile uint32_t reserved:32; 1496 }; 1497 uint32_t v; 1498 }reg_0x8c_reserved; 1499 1500 /* REG_0x8d */ 1501 union 1502 { 1503 struct 1504 { 1505 volatile uint32_t reserved:32; 1506 }; 1507 uint32_t v; 1508 }reg_0x8d_reserved; 1509 1510 /* REG_0x8e */ 1511 union 1512 { 1513 struct 1514 { 1515 volatile uint32_t reserved:32; 1516 }; 1517 uint32_t v; 1518 }reg_0x8e_reserved; 1519 1520 /* REG_0x8f */ 1521 union 1522 { 1523 struct 1524 { 1525 volatile uint32_t reserved:32; 1526 }; 1527 uint32_t v; 1528 }reg_0x8f_reserved; 1529 1530 /* REG_0x90 */ 1531 union 1532 { 1533 struct 1534 { 1535 volatile uint32_t reserved:32; 1536 }; 1537 uint32_t v; 1538 }reg_0x90_reserved; 1539 1540 /* REG_0x91 */ 1541 union 1542 { 1543 struct 1544 { 1545 volatile uint32_t reserved:32; 1546 }; 1547 uint32_t v; 1548 }reg_0x91_reserved; 1549 1550 /* REG_0x92 */ 1551 union 1552 { 1553 struct 1554 { 1555 volatile uint32_t reserved:32; 1556 }; 1557 uint32_t v; 1558 }reg_0x92_reserved; 1559 1560 /* REG_0x93 */ 1561 union 1562 { 1563 struct 1564 { 1565 volatile uint32_t reserved:32; 1566 }; 1567 uint32_t v; 1568 }reg_0x93_reserved; 1569 1570 /* REG_0x94 */ 1571 union 1572 { 1573 struct 1574 { 1575 volatile uint32_t reserved:32; 1576 }; 1577 uint32_t v; 1578 }reg_0x94_reserved; 1579 1580 /* REG_0x95 */ 1581 union 1582 { 1583 struct 1584 { 1585 volatile uint32_t reserved:32; 1586 }; 1587 uint32_t v; 1588 }reg_0x95_reserved; 1589 1590 /* REG_0x96 */ 1591 union 1592 { 1593 struct 1594 { 1595 volatile uint32_t reserved:32; 1596 }; 1597 uint32_t v; 1598 }reg_0x96_reserved; 1599 1600 /* REG_0x97 */ 1601 union 1602 { 1603 struct 1604 { 1605 volatile uint32_t reserved:32; 1606 }; 1607 uint32_t v; 1608 }reg_0x97_reserved; 1609 1610 /* REG_0x98 */ 1611 union 1612 { 1613 struct 1614 { 1615 volatile uint32_t reserved:32; 1616 }; 1617 uint32_t v; 1618 }reg_0x98_reserved; 1619 1620 /* REG_0x99 */ 1621 union 1622 { 1623 struct 1624 { 1625 volatile uint32_t reserved:32; 1626 }; 1627 uint32_t v; 1628 }reg_0x99_reserved; 1629 1630 /* REG_0x9a */ 1631 union 1632 { 1633 struct 1634 { 1635 volatile uint32_t reserved:32; 1636 }; 1637 uint32_t v; 1638 }reg_0x9a_reserved; 1639 1640 /* REG_0x9b */ 1641 union 1642 { 1643 struct 1644 { 1645 volatile uint32_t reserved:32; 1646 }; 1647 uint32_t v; 1648 }reg_0x9b_reserved; 1649 1650 /* REG_0x9c */ 1651 union 1652 { 1653 struct 1654 { 1655 volatile uint32_t reserved:32; 1656 }; 1657 uint32_t v; 1658 }reg_0x9c_reserved; 1659 1660 /* REG_0x9d */ 1661 union 1662 { 1663 struct 1664 { 1665 volatile uint32_t reserved:32; 1666 }; 1667 uint32_t v; 1668 }reg_0x9d_reserved; 1669 1670 /* REG_0x9e */ 1671 union 1672 { 1673 struct 1674 { 1675 volatile uint32_t reserved:32; 1676 }; 1677 uint32_t v; 1678 }reg_0x9e_reserved; 1679 1680 /* REG_0x9f */ 1681 union 1682 { 1683 struct 1684 { 1685 volatile uint32_t reserved:32; 1686 }; 1687 uint32_t v; 1688 }reg_0x9f_reserved; 1689 1690 /* REG_0xa0 */ 1691 union 1692 { 1693 struct 1694 { 1695 volatile uint32_t reserved:32; 1696 }; 1697 uint32_t v; 1698 }reg_0xa0_reserved; 1699 1700 /* REG_0xa1 */ 1701 union 1702 { 1703 struct 1704 { 1705 volatile uint32_t reserved:32; 1706 }; 1707 uint32_t v; 1708 }reg_0xa1_reserved; 1709 1710 /* REG_0xa2 */ 1711 union 1712 { 1713 struct 1714 { 1715 volatile uint32_t reserved:32; 1716 }; 1717 uint32_t v; 1718 }reg_0xa2_reserved; 1719 1720 /* REG_0xa3 */ 1721 union 1722 { 1723 struct 1724 { 1725 volatile uint32_t reserved:32; 1726 }; 1727 uint32_t v; 1728 }reg_0xa3_reserved; 1729 1730 /* REG_0xa4 */ 1731 union 1732 { 1733 struct 1734 { 1735 volatile uint32_t reserved:32; 1736 }; 1737 uint32_t v; 1738 }reg_0xa4_reserved; 1739 1740 /* REG_0xa5 */ 1741 union 1742 { 1743 struct 1744 { 1745 volatile uint32_t reserved:32; 1746 }; 1747 uint32_t v; 1748 }reg_0xa5_reserved; 1749 1750 /* REG_0xa6 */ 1751 union 1752 { 1753 struct 1754 { 1755 volatile uint32_t reserved:32; 1756 }; 1757 uint32_t v; 1758 }reg_0xa6_reserved; 1759 1760 /* REG_0xa7 */ 1761 union 1762 { 1763 struct 1764 { 1765 volatile uint32_t reserved:32; 1766 }; 1767 uint32_t v; 1768 }reg_0xa7_reserved; 1769 1770 /* REG_0xa8 */ 1771 union 1772 { 1773 struct 1774 { 1775 volatile uint32_t reserved:32; 1776 }; 1777 uint32_t v; 1778 }reg_0xa8_reserved; 1779 1780 /* REG_0xa9 */ 1781 union 1782 { 1783 struct 1784 { 1785 volatile uint32_t reserved:32; 1786 }; 1787 uint32_t v; 1788 }reg_0xa9_reserved; 1789 1790 /* REG_0xaa */ 1791 union 1792 { 1793 struct 1794 { 1795 volatile uint32_t reserved:32; 1796 }; 1797 uint32_t v; 1798 }reg_0xaa_reserved; 1799 1800 /* REG_0xab */ 1801 union 1802 { 1803 struct 1804 { 1805 volatile uint32_t reserved:32; 1806 }; 1807 uint32_t v; 1808 }reg_0xab_reserved; 1809 1810 /* REG_0xac */ 1811 union 1812 { 1813 struct 1814 { 1815 volatile uint32_t reserved:32; 1816 }; 1817 uint32_t v; 1818 }reg_0xac_reserved; 1819 1820 /* REG_0xad */ 1821 union 1822 { 1823 struct 1824 { 1825 volatile uint32_t reserved:32; 1826 }; 1827 uint32_t v; 1828 }reg_0xad_reserved; 1829 1830 /* REG_0xae */ 1831 union 1832 { 1833 struct 1834 { 1835 volatile uint32_t reserved:32; 1836 }; 1837 uint32_t v; 1838 }reg_0xae_reserved; 1839 1840 /* REG_0xaf */ 1841 union 1842 { 1843 struct 1844 { 1845 volatile uint32_t reserved:32; 1846 }; 1847 uint32_t v; 1848 }reg_0xaf_reserved; 1849 1850 /* REG_0xb0 */ 1851 union 1852 { 1853 struct 1854 { 1855 volatile uint32_t reserved:32; 1856 }; 1857 uint32_t v; 1858 }reg_0xb0_reserved; 1859 1860 /* REG_0xb1 */ 1861 union 1862 { 1863 struct 1864 { 1865 volatile uint32_t reserved:32; 1866 }; 1867 uint32_t v; 1868 }reg_0xb1_reserved; 1869 1870 /* REG_0xb2 */ 1871 union 1872 { 1873 struct 1874 { 1875 volatile uint32_t reserved:32; 1876 }; 1877 uint32_t v; 1878 }reg_0xb2_reserved; 1879 1880 /* REG_0xb3 */ 1881 union 1882 { 1883 struct 1884 { 1885 volatile uint32_t reserved:32; 1886 }; 1887 uint32_t v; 1888 }reg_0xb3_reserved; 1889 1890 /* REG_0xb4 */ 1891 union 1892 { 1893 struct 1894 { 1895 volatile uint32_t reserved:32; 1896 }; 1897 uint32_t v; 1898 }reg_0xb4_reserved; 1899 1900 /* REG_0xb5 */ 1901 union 1902 { 1903 struct 1904 { 1905 volatile uint32_t reserved:32; 1906 }; 1907 uint32_t v; 1908 }reg_0xb5_reserved; 1909 1910 /* REG_0xb6 */ 1911 union 1912 { 1913 struct 1914 { 1915 volatile uint32_t reserved:32; 1916 }; 1917 uint32_t v; 1918 }reg_0xb6_reserved; 1919 1920 /* REG_0xb7 */ 1921 union 1922 { 1923 struct 1924 { 1925 volatile uint32_t reserved:32; 1926 }; 1927 uint32_t v; 1928 }reg_0xb7_reserved; 1929 1930 /* REG_0xb8 */ 1931 union 1932 { 1933 struct 1934 { 1935 volatile uint32_t reserved:32; 1936 }; 1937 uint32_t v; 1938 }reg_0xb8_reserved; 1939 1940 /* REG_0xb9 */ 1941 union 1942 { 1943 struct 1944 { 1945 volatile uint32_t reserved:32; 1946 }; 1947 uint32_t v; 1948 }reg_0xb9_reserved; 1949 1950 /* REG_0xba */ 1951 union 1952 { 1953 struct 1954 { 1955 volatile uint32_t reserved:32; 1956 }; 1957 uint32_t v; 1958 }reg_0xba_reserved; 1959 1960 /* REG_0xbb */ 1961 union 1962 { 1963 struct 1964 { 1965 volatile uint32_t reserved:32; 1966 }; 1967 uint32_t v; 1968 }reg_0xbb_reserved; 1969 1970 /* REG_0xbc */ 1971 union 1972 { 1973 struct 1974 { 1975 volatile uint32_t reserved:32; 1976 }; 1977 uint32_t v; 1978 }reg_0xbc_reserved; 1979 1980 /* REG_0xbd */ 1981 union 1982 { 1983 struct 1984 { 1985 volatile uint32_t reserved:32; 1986 }; 1987 uint32_t v; 1988 }reg_0xbd_reserved; 1989 1990 /* REG_0xbe */ 1991 union 1992 { 1993 struct 1994 { 1995 volatile uint32_t reserved:32; 1996 }; 1997 uint32_t v; 1998 }reg_0xbe_reserved; 1999 2000 /* REG_0xbf */ 2001 union 2002 { 2003 struct 2004 { 2005 volatile uint32_t reserved:32; 2006 }; 2007 uint32_t v; 2008 }reg_0xbf_reserved; 2009 2010 /* REG_0xc0 */ 2011 union 2012 { 2013 struct 2014 { 2015 volatile uint32_t reserved:32; 2016 }; 2017 uint32_t v; 2018 }reg_0xc0_reserved; 2019 2020 /* REG_0xc1 */ 2021 union 2022 { 2023 struct 2024 { 2025 volatile uint32_t reserved:32; 2026 }; 2027 uint32_t v; 2028 }reg_0xc1_reserved; 2029 2030 /* REG_0xc2 */ 2031 union 2032 { 2033 struct 2034 { 2035 volatile uint32_t reserved:32; 2036 }; 2037 uint32_t v; 2038 }reg_0xc2_reserved; 2039 2040 /* REG_0xc3 */ 2041 union 2042 { 2043 struct 2044 { 2045 volatile uint32_t reserved:32; 2046 }; 2047 uint32_t v; 2048 }reg_0xc3_reserved; 2049 2050 /* REG_0xc4 */ 2051 union 2052 { 2053 struct 2054 { 2055 volatile uint32_t reserved:32; 2056 }; 2057 uint32_t v; 2058 }reg_0xc4_reserved; 2059 2060 /* REG_0xc5 */ 2061 union 2062 { 2063 struct 2064 { 2065 volatile uint32_t reserved:32; 2066 }; 2067 uint32_t v; 2068 }reg_0xc5_reserved; 2069 2070 /* REG_0xc6 */ 2071 union 2072 { 2073 struct 2074 { 2075 volatile uint32_t reserved:32; 2076 }; 2077 uint32_t v; 2078 }reg_0xc6_reserved; 2079 2080 /* REG_0xc7 */ 2081 union 2082 { 2083 struct 2084 { 2085 volatile uint32_t reserved:32; 2086 }; 2087 uint32_t v; 2088 }reg_0xc7_reserved; 2089 2090 /* REG_0xc8 */ 2091 union 2092 { 2093 struct 2094 { 2095 volatile uint32_t reserved:32; 2096 }; 2097 uint32_t v; 2098 }reg_0xc8_reserved; 2099 2100 /* REG_0xc9 */ 2101 union 2102 { 2103 struct 2104 { 2105 volatile uint32_t reserved:32; 2106 }; 2107 uint32_t v; 2108 }reg_0xc9_reserved; 2109 2110 /* REG_0xca */ 2111 union 2112 { 2113 struct 2114 { 2115 volatile uint32_t reserved:32; 2116 }; 2117 uint32_t v; 2118 }reg_0xca_reserved; 2119 2120 /* REG_0xcb */ 2121 union 2122 { 2123 struct 2124 { 2125 volatile uint32_t reserved:32; 2126 }; 2127 uint32_t v; 2128 }reg_0xcb_reserved; 2129 2130 /* REG_0xcc */ 2131 union 2132 { 2133 struct 2134 { 2135 volatile uint32_t reserved:32; 2136 }; 2137 uint32_t v; 2138 }reg_0xcc_reserved; 2139 2140 /* REG_0xcd */ 2141 union 2142 { 2143 struct 2144 { 2145 volatile uint32_t reserved:32; 2146 }; 2147 uint32_t v; 2148 }reg_0xcd_reserved; 2149 2150 /* REG_0xce */ 2151 union 2152 { 2153 struct 2154 { 2155 volatile uint32_t reserved:32; 2156 }; 2157 uint32_t v; 2158 }reg_0xce_reserved; 2159 2160 /* REG_0xcf */ 2161 union 2162 { 2163 struct 2164 { 2165 volatile uint32_t reserved:32; 2166 }; 2167 uint32_t v; 2168 }reg_0xcf_reserved; 2169 2170 /* REG_0xd0 */ 2171 union 2172 { 2173 struct 2174 { 2175 volatile uint32_t reserved:32; 2176 }; 2177 uint32_t v; 2178 }reg_0xd0_reserved; 2179 2180 /* REG_0xd1 */ 2181 union 2182 { 2183 struct 2184 { 2185 volatile uint32_t reserved:32; 2186 }; 2187 uint32_t v; 2188 }reg_0xd1_reserved; 2189 2190 /* REG_0xd2 */ 2191 union 2192 { 2193 struct 2194 { 2195 volatile uint32_t reserved:32; 2196 }; 2197 uint32_t v; 2198 }reg_0xd2_reserved; 2199 2200 /* REG_0xd3 */ 2201 union 2202 { 2203 struct 2204 { 2205 volatile uint32_t reserved:32; 2206 }; 2207 uint32_t v; 2208 }reg_0xd3_reserved; 2209 2210 /* REG_0xd4 */ 2211 union 2212 { 2213 struct 2214 { 2215 volatile uint32_t reserved:32; 2216 }; 2217 uint32_t v; 2218 }reg_0xd4_reserved; 2219 2220 /* REG_0xd5 */ 2221 union 2222 { 2223 struct 2224 { 2225 volatile uint32_t reserved:32; 2226 }; 2227 uint32_t v; 2228 }reg_0xd5_reserved; 2229 2230 /* REG_0xd6 */ 2231 union 2232 { 2233 struct 2234 { 2235 volatile uint32_t reserved:32; 2236 }; 2237 uint32_t v; 2238 }reg_0xd6_reserved; 2239 2240 /* REG_0xd7 */ 2241 union 2242 { 2243 struct 2244 { 2245 volatile uint32_t reserved:32; 2246 }; 2247 uint32_t v; 2248 }reg_0xd7_reserved; 2249 2250 /* REG_0xd8 */ 2251 union 2252 { 2253 struct 2254 { 2255 volatile uint32_t reserved:32; 2256 }; 2257 uint32_t v; 2258 }reg_0xd8_reserved; 2259 2260 /* REG_0xd9 */ 2261 union 2262 { 2263 struct 2264 { 2265 volatile uint32_t reserved:32; 2266 }; 2267 uint32_t v; 2268 }reg_0xd9_reserved; 2269 2270 /* REG_0xda */ 2271 union 2272 { 2273 struct 2274 { 2275 volatile uint32_t reserved:32; 2276 }; 2277 uint32_t v; 2278 }reg_0xda_reserved; 2279 2280 /* REG_0xdb */ 2281 union 2282 { 2283 struct 2284 { 2285 volatile uint32_t reserved:32; 2286 }; 2287 uint32_t v; 2288 }reg_0xdb_reserved; 2289 2290 /* REG_0xdc */ 2291 union 2292 { 2293 struct 2294 { 2295 volatile uint32_t reserved:32; 2296 }; 2297 uint32_t v; 2298 }reg_0xdc_reserved; 2299 2300 /* REG_0xdd */ 2301 union 2302 { 2303 struct 2304 { 2305 volatile uint32_t reserved:32; 2306 }; 2307 uint32_t v; 2308 }reg_0xdd_reserved; 2309 2310 /* REG_0xde */ 2311 union 2312 { 2313 struct 2314 { 2315 volatile uint32_t reserved:32; 2316 }; 2317 uint32_t v; 2318 }reg_0xde_reserved; 2319 2320 /* REG_0xdf */ 2321 union 2322 { 2323 struct 2324 { 2325 volatile uint32_t reserved:32; 2326 }; 2327 uint32_t v; 2328 }reg_0xdf_reserved; 2329 2330 /* REG_0xe0 */ 2331 union 2332 { 2333 struct 2334 { 2335 volatile uint32_t reserved:32; 2336 }; 2337 uint32_t v; 2338 }reg_0xe0_reserved; 2339 2340 /* REG_0xe1 */ 2341 union 2342 { 2343 struct 2344 { 2345 volatile uint32_t reserved:32; 2346 }; 2347 uint32_t v; 2348 }reg_0xe1_reserved; 2349 2350 /* REG_0xe2 */ 2351 union 2352 { 2353 struct 2354 { 2355 volatile uint32_t reserved:32; 2356 }; 2357 uint32_t v; 2358 }reg_0xe2_reserved; 2359 2360 /* REG_0xe3 */ 2361 union 2362 { 2363 struct 2364 { 2365 volatile uint32_t reserved:32; 2366 }; 2367 uint32_t v; 2368 }reg_0xe3_reserved; 2369 2370 /* REG_0xe4 */ 2371 union 2372 { 2373 struct 2374 { 2375 volatile uint32_t reserved:32; 2376 }; 2377 uint32_t v; 2378 }reg_0xe4_reserved; 2379 2380 /* REG_0xe5 */ 2381 union 2382 { 2383 struct 2384 { 2385 volatile uint32_t reserved:32; 2386 }; 2387 uint32_t v; 2388 }reg_0xe5_reserved; 2389 2390 /* REG_0xe6 */ 2391 union 2392 { 2393 struct 2394 { 2395 volatile uint32_t reserved:32; 2396 }; 2397 uint32_t v; 2398 }reg_0xe6_reserved; 2399 2400 /* REG_0xe7 */ 2401 union 2402 { 2403 struct 2404 { 2405 volatile uint32_t reserved:32; 2406 }; 2407 uint32_t v; 2408 }reg_0xe7_reserved; 2409 2410 /* REG_0xe8 */ 2411 union 2412 { 2413 struct 2414 { 2415 volatile uint32_t reserved:32; 2416 }; 2417 uint32_t v; 2418 }reg_0xe8_reserved; 2419 2420 /* REG_0xe9 */ 2421 union 2422 { 2423 struct 2424 { 2425 volatile uint32_t reserved:32; 2426 }; 2427 uint32_t v; 2428 }reg_0xe9_reserved; 2429 2430 /* REG_0xea */ 2431 union 2432 { 2433 struct 2434 { 2435 volatile uint32_t reserved:32; 2436 }; 2437 uint32_t v; 2438 }reg_0xea_reserved; 2439 2440 /* REG_0xeb */ 2441 union 2442 { 2443 struct 2444 { 2445 volatile uint32_t reserved:32; 2446 }; 2447 uint32_t v; 2448 }reg_0xeb_reserved; 2449 2450 /* REG_0xec */ 2451 union 2452 { 2453 struct 2454 { 2455 volatile uint32_t reserved:32; 2456 }; 2457 uint32_t v; 2458 }reg_0xec_reserved; 2459 2460 /* REG_0xed */ 2461 union 2462 { 2463 struct 2464 { 2465 volatile uint32_t reserved:32; 2466 }; 2467 uint32_t v; 2468 }reg_0xed_reserved; 2469 2470 /* REG_0xee */ 2471 union 2472 { 2473 struct 2474 { 2475 volatile uint32_t reserved:32; 2476 }; 2477 uint32_t v; 2478 }reg_0xee_reserved; 2479 2480 /* REG_0xef */ 2481 union 2482 { 2483 struct 2484 { 2485 volatile uint32_t reserved:32; 2486 }; 2487 uint32_t v; 2488 }reg_0xef_reserved; 2489 2490 /* REG_0xf0 */ 2491 union 2492 { 2493 struct 2494 { 2495 volatile uint32_t reserved:32; 2496 }; 2497 uint32_t v; 2498 }reg_0xf0_reserved; 2499 2500 /* REG_0xf1 */ 2501 union 2502 { 2503 struct 2504 { 2505 volatile uint32_t reserved:32; 2506 }; 2507 uint32_t v; 2508 }reg_0xf1_reserved; 2509 2510 /* REG_0xf2 */ 2511 union 2512 { 2513 struct 2514 { 2515 volatile uint32_t reserved:32; 2516 }; 2517 uint32_t v; 2518 }reg_0xf2_reserved; 2519 2520 /* REG_0xf3 */ 2521 union 2522 { 2523 struct 2524 { 2525 volatile uint32_t reserved:32; 2526 }; 2527 uint32_t v; 2528 }reg_0xf3_reserved; 2529 2530 /* REG_0xf4 */ 2531 union 2532 { 2533 struct 2534 { 2535 volatile uint32_t reserved:32; 2536 }; 2537 uint32_t v; 2538 }reg_0xf4_reserved; 2539 2540 /* REG_0xf5 */ 2541 union 2542 { 2543 struct 2544 { 2545 volatile uint32_t reserved:32; 2546 }; 2547 uint32_t v; 2548 }reg_0xf5_reserved; 2549 2550 /* REG_0xf6 */ 2551 union 2552 { 2553 struct 2554 { 2555 volatile uint32_t reserved:32; 2556 }; 2557 uint32_t v; 2558 }reg_0xf6_reserved; 2559 2560 /* REG_0xf7 */ 2561 union 2562 { 2563 struct 2564 { 2565 volatile uint32_t reserved:32; 2566 }; 2567 uint32_t v; 2568 }reg_0xf7_reserved; 2569 2570 /* REG_0xf8 */ 2571 union 2572 { 2573 struct 2574 { 2575 volatile uint32_t reserved:32; 2576 }; 2577 uint32_t v; 2578 }reg_0xf8_reserved; 2579 2580 /* REG_0xf9 */ 2581 union 2582 { 2583 struct 2584 { 2585 volatile uint32_t reserved:32; 2586 }; 2587 uint32_t v; 2588 }reg_0xf9_reserved; 2589 2590 /* REG_0xfa */ 2591 union 2592 { 2593 struct 2594 { 2595 volatile uint32_t reserved:32; 2596 }; 2597 uint32_t v; 2598 }reg_0xfa_reserved; 2599 2600 /* REG_0xfb */ 2601 union 2602 { 2603 struct 2604 { 2605 volatile uint32_t reserved:32; 2606 }; 2607 uint32_t v; 2608 }reg_0xfb_reserved; 2609 2610 /* REG_0xfc */ 2611 union 2612 { 2613 struct 2614 { 2615 volatile uint32_t reserved:32; 2616 }; 2617 uint32_t v; 2618 }reg_0xfc_reserved; 2619 2620 /* REG_0xfd */ 2621 union 2622 { 2623 struct 2624 { 2625 volatile uint32_t reserved:32; 2626 }; 2627 uint32_t v; 2628 }reg_0xfd_reserved; 2629 2630 /* REG_0xfe */ 2631 union 2632 { 2633 struct 2634 { 2635 volatile uint32_t reserved:32; 2636 }; 2637 uint32_t v; 2638 }reg_0xfe_reserved; 2639 2640 /* REG_0xff */ 2641 union 2642 { 2643 struct 2644 { 2645 volatile uint32_t reserved:32; 2646 }; 2647 uint32_t v; 2648 }reg_0xff_reserved; 2649 2650 /* REG_0x100 */ 2651 union 2652 { 2653 struct 2654 { 2655 volatile uint32_t blue : 1; //0x100[ 7: 0],blue value foe index<y>for the fg.,0,RW 2656 volatile uint32_t green : 1; //0x100[15: 8],green value foe index<y>for the fg.,0,RW 2657 volatile uint32_t red : 1; //0x100[23:16],red value foe index<y>for the fg.,0,RW 2658 volatile uint32_t alpha : 1; //0x100[31:24],alpha value foe index<y>for the fg.,0,RW 2659 }; 2660 uint32_t v; 2661 }dma2d_fg_clut0; 2662 2663 /* REG_0x101 */ 2664 union 2665 { 2666 struct 2667 { 2668 volatile uint32_t reserved:32; 2669 }; 2670 uint32_t v; 2671 }reg_0x101_reserved; 2672 2673 /* REG_0x102 */ 2674 union 2675 { 2676 struct 2677 { 2678 volatile uint32_t reserved:32; 2679 }; 2680 uint32_t v; 2681 }reg_0x102_reserved; 2682 2683 /* REG_0x103 */ 2684 union 2685 { 2686 struct 2687 { 2688 volatile uint32_t reserved:32; 2689 }; 2690 uint32_t v; 2691 }reg_0x103_reserved; 2692 2693 /* REG_0x104 */ 2694 union 2695 { 2696 struct 2697 { 2698 volatile uint32_t reserved:32; 2699 }; 2700 uint32_t v; 2701 }reg_0x104_reserved; 2702 2703 /* REG_0x105 */ 2704 union 2705 { 2706 struct 2707 { 2708 volatile uint32_t reserved:32; 2709 }; 2710 uint32_t v; 2711 }reg_0x105_reserved; 2712 2713 /* REG_0x106 */ 2714 union 2715 { 2716 struct 2717 { 2718 volatile uint32_t reserved:32; 2719 }; 2720 uint32_t v; 2721 }reg_0x106_reserved; 2722 2723 /* REG_0x107 */ 2724 union 2725 { 2726 struct 2727 { 2728 volatile uint32_t reserved:32; 2729 }; 2730 uint32_t v; 2731 }reg_0x107_reserved; 2732 2733 /* REG_0x108 */ 2734 union 2735 { 2736 struct 2737 { 2738 volatile uint32_t reserved:32; 2739 }; 2740 uint32_t v; 2741 }reg_0x108_reserved; 2742 2743 /* REG_0x109 */ 2744 union 2745 { 2746 struct 2747 { 2748 volatile uint32_t reserved:32; 2749 }; 2750 uint32_t v; 2751 }reg_0x109_reserved; 2752 2753 /* REG_0x10a */ 2754 union 2755 { 2756 struct 2757 { 2758 volatile uint32_t reserved:32; 2759 }; 2760 uint32_t v; 2761 }reg_0x10a_reserved; 2762 2763 /* REG_0x10b */ 2764 union 2765 { 2766 struct 2767 { 2768 volatile uint32_t reserved:32; 2769 }; 2770 uint32_t v; 2771 }reg_0x10b_reserved; 2772 2773 /* REG_0x10c */ 2774 union 2775 { 2776 struct 2777 { 2778 volatile uint32_t reserved:32; 2779 }; 2780 uint32_t v; 2781 }reg_0x10c_reserved; 2782 2783 /* REG_0x10d */ 2784 union 2785 { 2786 struct 2787 { 2788 volatile uint32_t reserved:32; 2789 }; 2790 uint32_t v; 2791 }reg_0x10d_reserved; 2792 2793 /* REG_0x10e */ 2794 union 2795 { 2796 struct 2797 { 2798 volatile uint32_t reserved:32; 2799 }; 2800 uint32_t v; 2801 }reg_0x10e_reserved; 2802 2803 /* REG_0x10f */ 2804 union 2805 { 2806 struct 2807 { 2808 volatile uint32_t reserved:32; 2809 }; 2810 uint32_t v; 2811 }reg_0x10f_reserved; 2812 2813 /* REG_0x110 */ 2814 union 2815 { 2816 struct 2817 { 2818 volatile uint32_t reserved:32; 2819 }; 2820 uint32_t v; 2821 }reg_0x110_reserved; 2822 2823 /* REG_0x111 */ 2824 union 2825 { 2826 struct 2827 { 2828 volatile uint32_t reserved:32; 2829 }; 2830 uint32_t v; 2831 }reg_0x111_reserved; 2832 2833 /* REG_0x112 */ 2834 union 2835 { 2836 struct 2837 { 2838 volatile uint32_t reserved:32; 2839 }; 2840 uint32_t v; 2841 }reg_0x112_reserved; 2842 2843 /* REG_0x113 */ 2844 union 2845 { 2846 struct 2847 { 2848 volatile uint32_t reserved:32; 2849 }; 2850 uint32_t v; 2851 }reg_0x113_reserved; 2852 2853 /* REG_0x114 */ 2854 union 2855 { 2856 struct 2857 { 2858 volatile uint32_t reserved:32; 2859 }; 2860 uint32_t v; 2861 }reg_0x114_reserved; 2862 2863 /* REG_0x115 */ 2864 union 2865 { 2866 struct 2867 { 2868 volatile uint32_t reserved:32; 2869 }; 2870 uint32_t v; 2871 }reg_0x115_reserved; 2872 2873 /* REG_0x116 */ 2874 union 2875 { 2876 struct 2877 { 2878 volatile uint32_t reserved:32; 2879 }; 2880 uint32_t v; 2881 }reg_0x116_reserved; 2882 2883 /* REG_0x117 */ 2884 union 2885 { 2886 struct 2887 { 2888 volatile uint32_t reserved:32; 2889 }; 2890 uint32_t v; 2891 }reg_0x117_reserved; 2892 2893 /* REG_0x118 */ 2894 union 2895 { 2896 struct 2897 { 2898 volatile uint32_t reserved:32; 2899 }; 2900 uint32_t v; 2901 }reg_0x118_reserved; 2902 2903 /* REG_0x119 */ 2904 union 2905 { 2906 struct 2907 { 2908 volatile uint32_t reserved:32; 2909 }; 2910 uint32_t v; 2911 }reg_0x119_reserved; 2912 2913 /* REG_0x11a */ 2914 union 2915 { 2916 struct 2917 { 2918 volatile uint32_t reserved:32; 2919 }; 2920 uint32_t v; 2921 }reg_0x11a_reserved; 2922 2923 /* REG_0x11b */ 2924 union 2925 { 2926 struct 2927 { 2928 volatile uint32_t reserved:32; 2929 }; 2930 uint32_t v; 2931 }reg_0x11b_reserved; 2932 2933 /* REG_0x11c */ 2934 union 2935 { 2936 struct 2937 { 2938 volatile uint32_t reserved:32; 2939 }; 2940 uint32_t v; 2941 }reg_0x11c_reserved; 2942 2943 /* REG_0x11d */ 2944 union 2945 { 2946 struct 2947 { 2948 volatile uint32_t reserved:32; 2949 }; 2950 uint32_t v; 2951 }reg_0x11d_reserved; 2952 2953 /* REG_0x11e */ 2954 union 2955 { 2956 struct 2957 { 2958 volatile uint32_t reserved:32; 2959 }; 2960 uint32_t v; 2961 }reg_0x11e_reserved; 2962 2963 /* REG_0x11f */ 2964 union 2965 { 2966 struct 2967 { 2968 volatile uint32_t reserved:32; 2969 }; 2970 uint32_t v; 2971 }reg_0x11f_reserved; 2972 2973 /* REG_0x120 */ 2974 union 2975 { 2976 struct 2977 { 2978 volatile uint32_t reserved:32; 2979 }; 2980 uint32_t v; 2981 }reg_0x120_reserved; 2982 2983 /* REG_0x121 */ 2984 union 2985 { 2986 struct 2987 { 2988 volatile uint32_t reserved:32; 2989 }; 2990 uint32_t v; 2991 }reg_0x121_reserved; 2992 2993 /* REG_0x122 */ 2994 union 2995 { 2996 struct 2997 { 2998 volatile uint32_t reserved:32; 2999 }; 3000 uint32_t v; 3001 }reg_0x122_reserved; 3002 3003 /* REG_0x123 */ 3004 union 3005 { 3006 struct 3007 { 3008 volatile uint32_t reserved:32; 3009 }; 3010 uint32_t v; 3011 }reg_0x123_reserved; 3012 3013 /* REG_0x124 */ 3014 union 3015 { 3016 struct 3017 { 3018 volatile uint32_t reserved:32; 3019 }; 3020 uint32_t v; 3021 }reg_0x124_reserved; 3022 3023 /* REG_0x125 */ 3024 union 3025 { 3026 struct 3027 { 3028 volatile uint32_t reserved:32; 3029 }; 3030 uint32_t v; 3031 }reg_0x125_reserved; 3032 3033 /* REG_0x126 */ 3034 union 3035 { 3036 struct 3037 { 3038 volatile uint32_t reserved:32; 3039 }; 3040 uint32_t v; 3041 }reg_0x126_reserved; 3042 3043 /* REG_0x127 */ 3044 union 3045 { 3046 struct 3047 { 3048 volatile uint32_t reserved:32; 3049 }; 3050 uint32_t v; 3051 }reg_0x127_reserved; 3052 3053 /* REG_0x128 */ 3054 union 3055 { 3056 struct 3057 { 3058 volatile uint32_t reserved:32; 3059 }; 3060 uint32_t v; 3061 }reg_0x128_reserved; 3062 3063 /* REG_0x129 */ 3064 union 3065 { 3066 struct 3067 { 3068 volatile uint32_t reserved:32; 3069 }; 3070 uint32_t v; 3071 }reg_0x129_reserved; 3072 3073 /* REG_0x12a */ 3074 union 3075 { 3076 struct 3077 { 3078 volatile uint32_t reserved:32; 3079 }; 3080 uint32_t v; 3081 }reg_0x12a_reserved; 3082 3083 /* REG_0x12b */ 3084 union 3085 { 3086 struct 3087 { 3088 volatile uint32_t reserved:32; 3089 }; 3090 uint32_t v; 3091 }reg_0x12b_reserved; 3092 3093 /* REG_0x12c */ 3094 union 3095 { 3096 struct 3097 { 3098 volatile uint32_t reserved:32; 3099 }; 3100 uint32_t v; 3101 }reg_0x12c_reserved; 3102 3103 /* REG_0x12d */ 3104 union 3105 { 3106 struct 3107 { 3108 volatile uint32_t reserved:32; 3109 }; 3110 uint32_t v; 3111 }reg_0x12d_reserved; 3112 3113 /* REG_0x12e */ 3114 union 3115 { 3116 struct 3117 { 3118 volatile uint32_t reserved:32; 3119 }; 3120 uint32_t v; 3121 }reg_0x12e_reserved; 3122 3123 /* REG_0x12f */ 3124 union 3125 { 3126 struct 3127 { 3128 volatile uint32_t reserved:32; 3129 }; 3130 uint32_t v; 3131 }reg_0x12f_reserved; 3132 3133 /* REG_0x130 */ 3134 union 3135 { 3136 struct 3137 { 3138 volatile uint32_t reserved:32; 3139 }; 3140 uint32_t v; 3141 }reg_0x130_reserved; 3142 3143 /* REG_0x131 */ 3144 union 3145 { 3146 struct 3147 { 3148 volatile uint32_t reserved:32; 3149 }; 3150 uint32_t v; 3151 }reg_0x131_reserved; 3152 3153 /* REG_0x132 */ 3154 union 3155 { 3156 struct 3157 { 3158 volatile uint32_t reserved:32; 3159 }; 3160 uint32_t v; 3161 }reg_0x132_reserved; 3162 3163 /* REG_0x133 */ 3164 union 3165 { 3166 struct 3167 { 3168 volatile uint32_t reserved:32; 3169 }; 3170 uint32_t v; 3171 }reg_0x133_reserved; 3172 3173 /* REG_0x134 */ 3174 union 3175 { 3176 struct 3177 { 3178 volatile uint32_t reserved:32; 3179 }; 3180 uint32_t v; 3181 }reg_0x134_reserved; 3182 3183 /* REG_0x135 */ 3184 union 3185 { 3186 struct 3187 { 3188 volatile uint32_t reserved:32; 3189 }; 3190 uint32_t v; 3191 }reg_0x135_reserved; 3192 3193 /* REG_0x136 */ 3194 union 3195 { 3196 struct 3197 { 3198 volatile uint32_t reserved:32; 3199 }; 3200 uint32_t v; 3201 }reg_0x136_reserved; 3202 3203 /* REG_0x137 */ 3204 union 3205 { 3206 struct 3207 { 3208 volatile uint32_t reserved:32; 3209 }; 3210 uint32_t v; 3211 }reg_0x137_reserved; 3212 3213 /* REG_0x138 */ 3214 union 3215 { 3216 struct 3217 { 3218 volatile uint32_t reserved:32; 3219 }; 3220 uint32_t v; 3221 }reg_0x138_reserved; 3222 3223 /* REG_0x139 */ 3224 union 3225 { 3226 struct 3227 { 3228 volatile uint32_t reserved:32; 3229 }; 3230 uint32_t v; 3231 }reg_0x139_reserved; 3232 3233 /* REG_0x13a */ 3234 union 3235 { 3236 struct 3237 { 3238 volatile uint32_t reserved:32; 3239 }; 3240 uint32_t v; 3241 }reg_0x13a_reserved; 3242 3243 /* REG_0x13b */ 3244 union 3245 { 3246 struct 3247 { 3248 volatile uint32_t reserved:32; 3249 }; 3250 uint32_t v; 3251 }reg_0x13b_reserved; 3252 3253 /* REG_0x13c */ 3254 union 3255 { 3256 struct 3257 { 3258 volatile uint32_t reserved:32; 3259 }; 3260 uint32_t v; 3261 }reg_0x13c_reserved; 3262 3263 /* REG_0x13d */ 3264 union 3265 { 3266 struct 3267 { 3268 volatile uint32_t reserved:32; 3269 }; 3270 uint32_t v; 3271 }reg_0x13d_reserved; 3272 3273 /* REG_0x13e */ 3274 union 3275 { 3276 struct 3277 { 3278 volatile uint32_t reserved:32; 3279 }; 3280 uint32_t v; 3281 }reg_0x13e_reserved; 3282 3283 /* REG_0x13f */ 3284 union 3285 { 3286 struct 3287 { 3288 volatile uint32_t reserved:32; 3289 }; 3290 uint32_t v; 3291 }reg_0x13f_reserved; 3292 3293 /* REG_0x140 */ 3294 union 3295 { 3296 struct 3297 { 3298 volatile uint32_t reserved:32; 3299 }; 3300 uint32_t v; 3301 }reg_0x140_reserved; 3302 3303 /* REG_0x141 */ 3304 union 3305 { 3306 struct 3307 { 3308 volatile uint32_t reserved:32; 3309 }; 3310 uint32_t v; 3311 }reg_0x141_reserved; 3312 3313 /* REG_0x142 */ 3314 union 3315 { 3316 struct 3317 { 3318 volatile uint32_t reserved:32; 3319 }; 3320 uint32_t v; 3321 }reg_0x142_reserved; 3322 3323 /* REG_0x143 */ 3324 union 3325 { 3326 struct 3327 { 3328 volatile uint32_t reserved:32; 3329 }; 3330 uint32_t v; 3331 }reg_0x143_reserved; 3332 3333 /* REG_0x144 */ 3334 union 3335 { 3336 struct 3337 { 3338 volatile uint32_t reserved:32; 3339 }; 3340 uint32_t v; 3341 }reg_0x144_reserved; 3342 3343 /* REG_0x145 */ 3344 union 3345 { 3346 struct 3347 { 3348 volatile uint32_t reserved:32; 3349 }; 3350 uint32_t v; 3351 }reg_0x145_reserved; 3352 3353 /* REG_0x146 */ 3354 union 3355 { 3356 struct 3357 { 3358 volatile uint32_t reserved:32; 3359 }; 3360 uint32_t v; 3361 }reg_0x146_reserved; 3362 3363 /* REG_0x147 */ 3364 union 3365 { 3366 struct 3367 { 3368 volatile uint32_t reserved:32; 3369 }; 3370 uint32_t v; 3371 }reg_0x147_reserved; 3372 3373 /* REG_0x148 */ 3374 union 3375 { 3376 struct 3377 { 3378 volatile uint32_t reserved:32; 3379 }; 3380 uint32_t v; 3381 }reg_0x148_reserved; 3382 3383 /* REG_0x149 */ 3384 union 3385 { 3386 struct 3387 { 3388 volatile uint32_t reserved:32; 3389 }; 3390 uint32_t v; 3391 }reg_0x149_reserved; 3392 3393 /* REG_0x14a */ 3394 union 3395 { 3396 struct 3397 { 3398 volatile uint32_t reserved:32; 3399 }; 3400 uint32_t v; 3401 }reg_0x14a_reserved; 3402 3403 /* REG_0x14b */ 3404 union 3405 { 3406 struct 3407 { 3408 volatile uint32_t reserved:32; 3409 }; 3410 uint32_t v; 3411 }reg_0x14b_reserved; 3412 3413 /* REG_0x14c */ 3414 union 3415 { 3416 struct 3417 { 3418 volatile uint32_t reserved:32; 3419 }; 3420 uint32_t v; 3421 }reg_0x14c_reserved; 3422 3423 /* REG_0x14d */ 3424 union 3425 { 3426 struct 3427 { 3428 volatile uint32_t reserved:32; 3429 }; 3430 uint32_t v; 3431 }reg_0x14d_reserved; 3432 3433 /* REG_0x14e */ 3434 union 3435 { 3436 struct 3437 { 3438 volatile uint32_t reserved:32; 3439 }; 3440 uint32_t v; 3441 }reg_0x14e_reserved; 3442 3443 /* REG_0x14f */ 3444 union 3445 { 3446 struct 3447 { 3448 volatile uint32_t reserved:32; 3449 }; 3450 uint32_t v; 3451 }reg_0x14f_reserved; 3452 3453 /* REG_0x150 */ 3454 union 3455 { 3456 struct 3457 { 3458 volatile uint32_t reserved:32; 3459 }; 3460 uint32_t v; 3461 }reg_0x150_reserved; 3462 3463 /* REG_0x151 */ 3464 union 3465 { 3466 struct 3467 { 3468 volatile uint32_t reserved:32; 3469 }; 3470 uint32_t v; 3471 }reg_0x151_reserved; 3472 3473 /* REG_0x152 */ 3474 union 3475 { 3476 struct 3477 { 3478 volatile uint32_t reserved:32; 3479 }; 3480 uint32_t v; 3481 }reg_0x152_reserved; 3482 3483 /* REG_0x153 */ 3484 union 3485 { 3486 struct 3487 { 3488 volatile uint32_t reserved:32; 3489 }; 3490 uint32_t v; 3491 }reg_0x153_reserved; 3492 3493 /* REG_0x154 */ 3494 union 3495 { 3496 struct 3497 { 3498 volatile uint32_t reserved:32; 3499 }; 3500 uint32_t v; 3501 }reg_0x154_reserved; 3502 3503 /* REG_0x155 */ 3504 union 3505 { 3506 struct 3507 { 3508 volatile uint32_t reserved:32; 3509 }; 3510 uint32_t v; 3511 }reg_0x155_reserved; 3512 3513 /* REG_0x156 */ 3514 union 3515 { 3516 struct 3517 { 3518 volatile uint32_t reserved:32; 3519 }; 3520 uint32_t v; 3521 }reg_0x156_reserved; 3522 3523 /* REG_0x157 */ 3524 union 3525 { 3526 struct 3527 { 3528 volatile uint32_t reserved:32; 3529 }; 3530 uint32_t v; 3531 }reg_0x157_reserved; 3532 3533 /* REG_0x158 */ 3534 union 3535 { 3536 struct 3537 { 3538 volatile uint32_t reserved:32; 3539 }; 3540 uint32_t v; 3541 }reg_0x158_reserved; 3542 3543 /* REG_0x159 */ 3544 union 3545 { 3546 struct 3547 { 3548 volatile uint32_t reserved:32; 3549 }; 3550 uint32_t v; 3551 }reg_0x159_reserved; 3552 3553 /* REG_0x15a */ 3554 union 3555 { 3556 struct 3557 { 3558 volatile uint32_t reserved:32; 3559 }; 3560 uint32_t v; 3561 }reg_0x15a_reserved; 3562 3563 /* REG_0x15b */ 3564 union 3565 { 3566 struct 3567 { 3568 volatile uint32_t reserved:32; 3569 }; 3570 uint32_t v; 3571 }reg_0x15b_reserved; 3572 3573 /* REG_0x15c */ 3574 union 3575 { 3576 struct 3577 { 3578 volatile uint32_t reserved:32; 3579 }; 3580 uint32_t v; 3581 }reg_0x15c_reserved; 3582 3583 /* REG_0x15d */ 3584 union 3585 { 3586 struct 3587 { 3588 volatile uint32_t reserved:32; 3589 }; 3590 uint32_t v; 3591 }reg_0x15d_reserved; 3592 3593 /* REG_0x15e */ 3594 union 3595 { 3596 struct 3597 { 3598 volatile uint32_t reserved:32; 3599 }; 3600 uint32_t v; 3601 }reg_0x15e_reserved; 3602 3603 /* REG_0x15f */ 3604 union 3605 { 3606 struct 3607 { 3608 volatile uint32_t reserved:32; 3609 }; 3610 uint32_t v; 3611 }reg_0x15f_reserved; 3612 3613 /* REG_0x160 */ 3614 union 3615 { 3616 struct 3617 { 3618 volatile uint32_t reserved:32; 3619 }; 3620 uint32_t v; 3621 }reg_0x160_reserved; 3622 3623 /* REG_0x161 */ 3624 union 3625 { 3626 struct 3627 { 3628 volatile uint32_t reserved:32; 3629 }; 3630 uint32_t v; 3631 }reg_0x161_reserved; 3632 3633 /* REG_0x162 */ 3634 union 3635 { 3636 struct 3637 { 3638 volatile uint32_t reserved:32; 3639 }; 3640 uint32_t v; 3641 }reg_0x162_reserved; 3642 3643 /* REG_0x163 */ 3644 union 3645 { 3646 struct 3647 { 3648 volatile uint32_t reserved:32; 3649 }; 3650 uint32_t v; 3651 }reg_0x163_reserved; 3652 3653 /* REG_0x164 */ 3654 union 3655 { 3656 struct 3657 { 3658 volatile uint32_t reserved:32; 3659 }; 3660 uint32_t v; 3661 }reg_0x164_reserved; 3662 3663 /* REG_0x165 */ 3664 union 3665 { 3666 struct 3667 { 3668 volatile uint32_t reserved:32; 3669 }; 3670 uint32_t v; 3671 }reg_0x165_reserved; 3672 3673 /* REG_0x166 */ 3674 union 3675 { 3676 struct 3677 { 3678 volatile uint32_t reserved:32; 3679 }; 3680 uint32_t v; 3681 }reg_0x166_reserved; 3682 3683 /* REG_0x167 */ 3684 union 3685 { 3686 struct 3687 { 3688 volatile uint32_t reserved:32; 3689 }; 3690 uint32_t v; 3691 }reg_0x167_reserved; 3692 3693 /* REG_0x168 */ 3694 union 3695 { 3696 struct 3697 { 3698 volatile uint32_t reserved:32; 3699 }; 3700 uint32_t v; 3701 }reg_0x168_reserved; 3702 3703 /* REG_0x169 */ 3704 union 3705 { 3706 struct 3707 { 3708 volatile uint32_t reserved:32; 3709 }; 3710 uint32_t v; 3711 }reg_0x169_reserved; 3712 3713 /* REG_0x16a */ 3714 union 3715 { 3716 struct 3717 { 3718 volatile uint32_t reserved:32; 3719 }; 3720 uint32_t v; 3721 }reg_0x16a_reserved; 3722 3723 /* REG_0x16b */ 3724 union 3725 { 3726 struct 3727 { 3728 volatile uint32_t reserved:32; 3729 }; 3730 uint32_t v; 3731 }reg_0x16b_reserved; 3732 3733 /* REG_0x16c */ 3734 union 3735 { 3736 struct 3737 { 3738 volatile uint32_t reserved:32; 3739 }; 3740 uint32_t v; 3741 }reg_0x16c_reserved; 3742 3743 /* REG_0x16d */ 3744 union 3745 { 3746 struct 3747 { 3748 volatile uint32_t reserved:32; 3749 }; 3750 uint32_t v; 3751 }reg_0x16d_reserved; 3752 3753 /* REG_0x16e */ 3754 union 3755 { 3756 struct 3757 { 3758 volatile uint32_t reserved:32; 3759 }; 3760 uint32_t v; 3761 }reg_0x16e_reserved; 3762 3763 /* REG_0x16f */ 3764 union 3765 { 3766 struct 3767 { 3768 volatile uint32_t reserved:32; 3769 }; 3770 uint32_t v; 3771 }reg_0x16f_reserved; 3772 3773 /* REG_0x170 */ 3774 union 3775 { 3776 struct 3777 { 3778 volatile uint32_t reserved:32; 3779 }; 3780 uint32_t v; 3781 }reg_0x170_reserved; 3782 3783 /* REG_0x171 */ 3784 union 3785 { 3786 struct 3787 { 3788 volatile uint32_t reserved:32; 3789 }; 3790 uint32_t v; 3791 }reg_0x171_reserved; 3792 3793 /* REG_0x172 */ 3794 union 3795 { 3796 struct 3797 { 3798 volatile uint32_t reserved:32; 3799 }; 3800 uint32_t v; 3801 }reg_0x172_reserved; 3802 3803 /* REG_0x173 */ 3804 union 3805 { 3806 struct 3807 { 3808 volatile uint32_t reserved:32; 3809 }; 3810 uint32_t v; 3811 }reg_0x173_reserved; 3812 3813 /* REG_0x174 */ 3814 union 3815 { 3816 struct 3817 { 3818 volatile uint32_t reserved:32; 3819 }; 3820 uint32_t v; 3821 }reg_0x174_reserved; 3822 3823 /* REG_0x175 */ 3824 union 3825 { 3826 struct 3827 { 3828 volatile uint32_t reserved:32; 3829 }; 3830 uint32_t v; 3831 }reg_0x175_reserved; 3832 3833 /* REG_0x176 */ 3834 union 3835 { 3836 struct 3837 { 3838 volatile uint32_t reserved:32; 3839 }; 3840 uint32_t v; 3841 }reg_0x176_reserved; 3842 3843 /* REG_0x177 */ 3844 union 3845 { 3846 struct 3847 { 3848 volatile uint32_t reserved:32; 3849 }; 3850 uint32_t v; 3851 }reg_0x177_reserved; 3852 3853 /* REG_0x178 */ 3854 union 3855 { 3856 struct 3857 { 3858 volatile uint32_t reserved:32; 3859 }; 3860 uint32_t v; 3861 }reg_0x178_reserved; 3862 3863 /* REG_0x179 */ 3864 union 3865 { 3866 struct 3867 { 3868 volatile uint32_t reserved:32; 3869 }; 3870 uint32_t v; 3871 }reg_0x179_reserved; 3872 3873 /* REG_0x17a */ 3874 union 3875 { 3876 struct 3877 { 3878 volatile uint32_t reserved:32; 3879 }; 3880 uint32_t v; 3881 }reg_0x17a_reserved; 3882 3883 /* REG_0x17b */ 3884 union 3885 { 3886 struct 3887 { 3888 volatile uint32_t reserved:32; 3889 }; 3890 uint32_t v; 3891 }reg_0x17b_reserved; 3892 3893 /* REG_0x17c */ 3894 union 3895 { 3896 struct 3897 { 3898 volatile uint32_t reserved:32; 3899 }; 3900 uint32_t v; 3901 }reg_0x17c_reserved; 3902 3903 /* REG_0x17d */ 3904 union 3905 { 3906 struct 3907 { 3908 volatile uint32_t reserved:32; 3909 }; 3910 uint32_t v; 3911 }reg_0x17d_reserved; 3912 3913 /* REG_0x17e */ 3914 union 3915 { 3916 struct 3917 { 3918 volatile uint32_t reserved:32; 3919 }; 3920 uint32_t v; 3921 }reg_0x17e_reserved; 3922 3923 /* REG_0x17f */ 3924 union 3925 { 3926 struct 3927 { 3928 volatile uint32_t reserved:32; 3929 }; 3930 uint32_t v; 3931 }reg_0x17f_reserved; 3932 3933 /* REG_0x180 */ 3934 union 3935 { 3936 struct 3937 { 3938 volatile uint32_t reserved:32; 3939 }; 3940 uint32_t v; 3941 }reg_0x180_reserved; 3942 3943 /* REG_0x181 */ 3944 union 3945 { 3946 struct 3947 { 3948 volatile uint32_t reserved:32; 3949 }; 3950 uint32_t v; 3951 }reg_0x181_reserved; 3952 3953 /* REG_0x182 */ 3954 union 3955 { 3956 struct 3957 { 3958 volatile uint32_t reserved:32; 3959 }; 3960 uint32_t v; 3961 }reg_0x182_reserved; 3962 3963 /* REG_0x183 */ 3964 union 3965 { 3966 struct 3967 { 3968 volatile uint32_t reserved:32; 3969 }; 3970 uint32_t v; 3971 }reg_0x183_reserved; 3972 3973 /* REG_0x184 */ 3974 union 3975 { 3976 struct 3977 { 3978 volatile uint32_t reserved:32; 3979 }; 3980 uint32_t v; 3981 }reg_0x184_reserved; 3982 3983 /* REG_0x185 */ 3984 union 3985 { 3986 struct 3987 { 3988 volatile uint32_t reserved:32; 3989 }; 3990 uint32_t v; 3991 }reg_0x185_reserved; 3992 3993 /* REG_0x186 */ 3994 union 3995 { 3996 struct 3997 { 3998 volatile uint32_t reserved:32; 3999 }; 4000 uint32_t v; 4001 }reg_0x186_reserved; 4002 4003 /* REG_0x187 */ 4004 union 4005 { 4006 struct 4007 { 4008 volatile uint32_t reserved:32; 4009 }; 4010 uint32_t v; 4011 }reg_0x187_reserved; 4012 4013 /* REG_0x188 */ 4014 union 4015 { 4016 struct 4017 { 4018 volatile uint32_t reserved:32; 4019 }; 4020 uint32_t v; 4021 }reg_0x188_reserved; 4022 4023 /* REG_0x189 */ 4024 union 4025 { 4026 struct 4027 { 4028 volatile uint32_t reserved:32; 4029 }; 4030 uint32_t v; 4031 }reg_0x189_reserved; 4032 4033 /* REG_0x18a */ 4034 union 4035 { 4036 struct 4037 { 4038 volatile uint32_t reserved:32; 4039 }; 4040 uint32_t v; 4041 }reg_0x18a_reserved; 4042 4043 /* REG_0x18b */ 4044 union 4045 { 4046 struct 4047 { 4048 volatile uint32_t reserved:32; 4049 }; 4050 uint32_t v; 4051 }reg_0x18b_reserved; 4052 4053 /* REG_0x18c */ 4054 union 4055 { 4056 struct 4057 { 4058 volatile uint32_t reserved:32; 4059 }; 4060 uint32_t v; 4061 }reg_0x18c_reserved; 4062 4063 /* REG_0x18d */ 4064 union 4065 { 4066 struct 4067 { 4068 volatile uint32_t reserved:32; 4069 }; 4070 uint32_t v; 4071 }reg_0x18d_reserved; 4072 4073 /* REG_0x18e */ 4074 union 4075 { 4076 struct 4077 { 4078 volatile uint32_t reserved:32; 4079 }; 4080 uint32_t v; 4081 }reg_0x18e_reserved; 4082 4083 /* REG_0x18f */ 4084 union 4085 { 4086 struct 4087 { 4088 volatile uint32_t reserved:32; 4089 }; 4090 uint32_t v; 4091 }reg_0x18f_reserved; 4092 4093 /* REG_0x190 */ 4094 union 4095 { 4096 struct 4097 { 4098 volatile uint32_t reserved:32; 4099 }; 4100 uint32_t v; 4101 }reg_0x190_reserved; 4102 4103 /* REG_0x191 */ 4104 union 4105 { 4106 struct 4107 { 4108 volatile uint32_t reserved:32; 4109 }; 4110 uint32_t v; 4111 }reg_0x191_reserved; 4112 4113 /* REG_0x192 */ 4114 union 4115 { 4116 struct 4117 { 4118 volatile uint32_t reserved:32; 4119 }; 4120 uint32_t v; 4121 }reg_0x192_reserved; 4122 4123 /* REG_0x193 */ 4124 union 4125 { 4126 struct 4127 { 4128 volatile uint32_t reserved:32; 4129 }; 4130 uint32_t v; 4131 }reg_0x193_reserved; 4132 4133 /* REG_0x194 */ 4134 union 4135 { 4136 struct 4137 { 4138 volatile uint32_t reserved:32; 4139 }; 4140 uint32_t v; 4141 }reg_0x194_reserved; 4142 4143 /* REG_0x195 */ 4144 union 4145 { 4146 struct 4147 { 4148 volatile uint32_t reserved:32; 4149 }; 4150 uint32_t v; 4151 }reg_0x195_reserved; 4152 4153 /* REG_0x196 */ 4154 union 4155 { 4156 struct 4157 { 4158 volatile uint32_t reserved:32; 4159 }; 4160 uint32_t v; 4161 }reg_0x196_reserved; 4162 4163 /* REG_0x197 */ 4164 union 4165 { 4166 struct 4167 { 4168 volatile uint32_t reserved:32; 4169 }; 4170 uint32_t v; 4171 }reg_0x197_reserved; 4172 4173 /* REG_0x198 */ 4174 union 4175 { 4176 struct 4177 { 4178 volatile uint32_t reserved:32; 4179 }; 4180 uint32_t v; 4181 }reg_0x198_reserved; 4182 4183 /* REG_0x199 */ 4184 union 4185 { 4186 struct 4187 { 4188 volatile uint32_t reserved:32; 4189 }; 4190 uint32_t v; 4191 }reg_0x199_reserved; 4192 4193 /* REG_0x19a */ 4194 union 4195 { 4196 struct 4197 { 4198 volatile uint32_t reserved:32; 4199 }; 4200 uint32_t v; 4201 }reg_0x19a_reserved; 4202 4203 /* REG_0x19b */ 4204 union 4205 { 4206 struct 4207 { 4208 volatile uint32_t reserved:32; 4209 }; 4210 uint32_t v; 4211 }reg_0x19b_reserved; 4212 4213 /* REG_0x19c */ 4214 union 4215 { 4216 struct 4217 { 4218 volatile uint32_t reserved:32; 4219 }; 4220 uint32_t v; 4221 }reg_0x19c_reserved; 4222 4223 /* REG_0x19d */ 4224 union 4225 { 4226 struct 4227 { 4228 volatile uint32_t reserved:32; 4229 }; 4230 uint32_t v; 4231 }reg_0x19d_reserved; 4232 4233 /* REG_0x19e */ 4234 union 4235 { 4236 struct 4237 { 4238 volatile uint32_t reserved:32; 4239 }; 4240 uint32_t v; 4241 }reg_0x19e_reserved; 4242 4243 /* REG_0x19f */ 4244 union 4245 { 4246 struct 4247 { 4248 volatile uint32_t reserved:32; 4249 }; 4250 uint32_t v; 4251 }reg_0x19f_reserved; 4252 4253 /* REG_0x1a0 */ 4254 union 4255 { 4256 struct 4257 { 4258 volatile uint32_t reserved:32; 4259 }; 4260 uint32_t v; 4261 }reg_0x1a0_reserved; 4262 4263 /* REG_0x1a1 */ 4264 union 4265 { 4266 struct 4267 { 4268 volatile uint32_t reserved:32; 4269 }; 4270 uint32_t v; 4271 }reg_0x1a1_reserved; 4272 4273 /* REG_0x1a2 */ 4274 union 4275 { 4276 struct 4277 { 4278 volatile uint32_t reserved:32; 4279 }; 4280 uint32_t v; 4281 }reg_0x1a2_reserved; 4282 4283 /* REG_0x1a3 */ 4284 union 4285 { 4286 struct 4287 { 4288 volatile uint32_t reserved:32; 4289 }; 4290 uint32_t v; 4291 }reg_0x1a3_reserved; 4292 4293 /* REG_0x1a4 */ 4294 union 4295 { 4296 struct 4297 { 4298 volatile uint32_t reserved:32; 4299 }; 4300 uint32_t v; 4301 }reg_0x1a4_reserved; 4302 4303 /* REG_0x1a5 */ 4304 union 4305 { 4306 struct 4307 { 4308 volatile uint32_t reserved:32; 4309 }; 4310 uint32_t v; 4311 }reg_0x1a5_reserved; 4312 4313 /* REG_0x1a6 */ 4314 union 4315 { 4316 struct 4317 { 4318 volatile uint32_t reserved:32; 4319 }; 4320 uint32_t v; 4321 }reg_0x1a6_reserved; 4322 4323 /* REG_0x1a7 */ 4324 union 4325 { 4326 struct 4327 { 4328 volatile uint32_t reserved:32; 4329 }; 4330 uint32_t v; 4331 }reg_0x1a7_reserved; 4332 4333 /* REG_0x1a8 */ 4334 union 4335 { 4336 struct 4337 { 4338 volatile uint32_t reserved:32; 4339 }; 4340 uint32_t v; 4341 }reg_0x1a8_reserved; 4342 4343 /* REG_0x1a9 */ 4344 union 4345 { 4346 struct 4347 { 4348 volatile uint32_t reserved:32; 4349 }; 4350 uint32_t v; 4351 }reg_0x1a9_reserved; 4352 4353 /* REG_0x1aa */ 4354 union 4355 { 4356 struct 4357 { 4358 volatile uint32_t reserved:32; 4359 }; 4360 uint32_t v; 4361 }reg_0x1aa_reserved; 4362 4363 /* REG_0x1ab */ 4364 union 4365 { 4366 struct 4367 { 4368 volatile uint32_t reserved:32; 4369 }; 4370 uint32_t v; 4371 }reg_0x1ab_reserved; 4372 4373 /* REG_0x1ac */ 4374 union 4375 { 4376 struct 4377 { 4378 volatile uint32_t reserved:32; 4379 }; 4380 uint32_t v; 4381 }reg_0x1ac_reserved; 4382 4383 /* REG_0x1ad */ 4384 union 4385 { 4386 struct 4387 { 4388 volatile uint32_t reserved:32; 4389 }; 4390 uint32_t v; 4391 }reg_0x1ad_reserved; 4392 4393 /* REG_0x1ae */ 4394 union 4395 { 4396 struct 4397 { 4398 volatile uint32_t reserved:32; 4399 }; 4400 uint32_t v; 4401 }reg_0x1ae_reserved; 4402 4403 /* REG_0x1af */ 4404 union 4405 { 4406 struct 4407 { 4408 volatile uint32_t reserved:32; 4409 }; 4410 uint32_t v; 4411 }reg_0x1af_reserved; 4412 4413 /* REG_0x1b0 */ 4414 union 4415 { 4416 struct 4417 { 4418 volatile uint32_t reserved:32; 4419 }; 4420 uint32_t v; 4421 }reg_0x1b0_reserved; 4422 4423 /* REG_0x1b1 */ 4424 union 4425 { 4426 struct 4427 { 4428 volatile uint32_t reserved:32; 4429 }; 4430 uint32_t v; 4431 }reg_0x1b1_reserved; 4432 4433 /* REG_0x1b2 */ 4434 union 4435 { 4436 struct 4437 { 4438 volatile uint32_t reserved:32; 4439 }; 4440 uint32_t v; 4441 }reg_0x1b2_reserved; 4442 4443 /* REG_0x1b3 */ 4444 union 4445 { 4446 struct 4447 { 4448 volatile uint32_t reserved:32; 4449 }; 4450 uint32_t v; 4451 }reg_0x1b3_reserved; 4452 4453 /* REG_0x1b4 */ 4454 union 4455 { 4456 struct 4457 { 4458 volatile uint32_t reserved:32; 4459 }; 4460 uint32_t v; 4461 }reg_0x1b4_reserved; 4462 4463 /* REG_0x1b5 */ 4464 union 4465 { 4466 struct 4467 { 4468 volatile uint32_t reserved:32; 4469 }; 4470 uint32_t v; 4471 }reg_0x1b5_reserved; 4472 4473 /* REG_0x1b6 */ 4474 union 4475 { 4476 struct 4477 { 4478 volatile uint32_t reserved:32; 4479 }; 4480 uint32_t v; 4481 }reg_0x1b6_reserved; 4482 4483 /* REG_0x1b7 */ 4484 union 4485 { 4486 struct 4487 { 4488 volatile uint32_t reserved:32; 4489 }; 4490 uint32_t v; 4491 }reg_0x1b7_reserved; 4492 4493 /* REG_0x1b8 */ 4494 union 4495 { 4496 struct 4497 { 4498 volatile uint32_t reserved:32; 4499 }; 4500 uint32_t v; 4501 }reg_0x1b8_reserved; 4502 4503 /* REG_0x1b9 */ 4504 union 4505 { 4506 struct 4507 { 4508 volatile uint32_t reserved:32; 4509 }; 4510 uint32_t v; 4511 }reg_0x1b9_reserved; 4512 4513 /* REG_0x1ba */ 4514 union 4515 { 4516 struct 4517 { 4518 volatile uint32_t reserved:32; 4519 }; 4520 uint32_t v; 4521 }reg_0x1ba_reserved; 4522 4523 /* REG_0x1bb */ 4524 union 4525 { 4526 struct 4527 { 4528 volatile uint32_t reserved:32; 4529 }; 4530 uint32_t v; 4531 }reg_0x1bb_reserved; 4532 4533 /* REG_0x1bc */ 4534 union 4535 { 4536 struct 4537 { 4538 volatile uint32_t reserved:32; 4539 }; 4540 uint32_t v; 4541 }reg_0x1bc_reserved; 4542 4543 /* REG_0x1bd */ 4544 union 4545 { 4546 struct 4547 { 4548 volatile uint32_t reserved:32; 4549 }; 4550 uint32_t v; 4551 }reg_0x1bd_reserved; 4552 4553 /* REG_0x1be */ 4554 union 4555 { 4556 struct 4557 { 4558 volatile uint32_t reserved:32; 4559 }; 4560 uint32_t v; 4561 }reg_0x1be_reserved; 4562 4563 /* REG_0x1bf */ 4564 union 4565 { 4566 struct 4567 { 4568 volatile uint32_t reserved:32; 4569 }; 4570 uint32_t v; 4571 }reg_0x1bf_reserved; 4572 4573 /* REG_0x1c0 */ 4574 union 4575 { 4576 struct 4577 { 4578 volatile uint32_t reserved:32; 4579 }; 4580 uint32_t v; 4581 }reg_0x1c0_reserved; 4582 4583 /* REG_0x1c1 */ 4584 union 4585 { 4586 struct 4587 { 4588 volatile uint32_t reserved:32; 4589 }; 4590 uint32_t v; 4591 }reg_0x1c1_reserved; 4592 4593 /* REG_0x1c2 */ 4594 union 4595 { 4596 struct 4597 { 4598 volatile uint32_t reserved:32; 4599 }; 4600 uint32_t v; 4601 }reg_0x1c2_reserved; 4602 4603 /* REG_0x1c3 */ 4604 union 4605 { 4606 struct 4607 { 4608 volatile uint32_t reserved:32; 4609 }; 4610 uint32_t v; 4611 }reg_0x1c3_reserved; 4612 4613 /* REG_0x1c4 */ 4614 union 4615 { 4616 struct 4617 { 4618 volatile uint32_t reserved:32; 4619 }; 4620 uint32_t v; 4621 }reg_0x1c4_reserved; 4622 4623 /* REG_0x1c5 */ 4624 union 4625 { 4626 struct 4627 { 4628 volatile uint32_t reserved:32; 4629 }; 4630 uint32_t v; 4631 }reg_0x1c5_reserved; 4632 4633 /* REG_0x1c6 */ 4634 union 4635 { 4636 struct 4637 { 4638 volatile uint32_t reserved:32; 4639 }; 4640 uint32_t v; 4641 }reg_0x1c6_reserved; 4642 4643 /* REG_0x1c7 */ 4644 union 4645 { 4646 struct 4647 { 4648 volatile uint32_t reserved:32; 4649 }; 4650 uint32_t v; 4651 }reg_0x1c7_reserved; 4652 4653 /* REG_0x1c8 */ 4654 union 4655 { 4656 struct 4657 { 4658 volatile uint32_t reserved:32; 4659 }; 4660 uint32_t v; 4661 }reg_0x1c8_reserved; 4662 4663 /* REG_0x1c9 */ 4664 union 4665 { 4666 struct 4667 { 4668 volatile uint32_t reserved:32; 4669 }; 4670 uint32_t v; 4671 }reg_0x1c9_reserved; 4672 4673 /* REG_0x1ca */ 4674 union 4675 { 4676 struct 4677 { 4678 volatile uint32_t reserved:32; 4679 }; 4680 uint32_t v; 4681 }reg_0x1ca_reserved; 4682 4683 /* REG_0x1cb */ 4684 union 4685 { 4686 struct 4687 { 4688 volatile uint32_t reserved:32; 4689 }; 4690 uint32_t v; 4691 }reg_0x1cb_reserved; 4692 4693 /* REG_0x1cc */ 4694 union 4695 { 4696 struct 4697 { 4698 volatile uint32_t reserved:32; 4699 }; 4700 uint32_t v; 4701 }reg_0x1cc_reserved; 4702 4703 /* REG_0x1cd */ 4704 union 4705 { 4706 struct 4707 { 4708 volatile uint32_t reserved:32; 4709 }; 4710 uint32_t v; 4711 }reg_0x1cd_reserved; 4712 4713 /* REG_0x1ce */ 4714 union 4715 { 4716 struct 4717 { 4718 volatile uint32_t reserved:32; 4719 }; 4720 uint32_t v; 4721 }reg_0x1ce_reserved; 4722 4723 /* REG_0x1cf */ 4724 union 4725 { 4726 struct 4727 { 4728 volatile uint32_t reserved:32; 4729 }; 4730 uint32_t v; 4731 }reg_0x1cf_reserved; 4732 4733 /* REG_0x1d0 */ 4734 union 4735 { 4736 struct 4737 { 4738 volatile uint32_t reserved:32; 4739 }; 4740 uint32_t v; 4741 }reg_0x1d0_reserved; 4742 4743 /* REG_0x1d1 */ 4744 union 4745 { 4746 struct 4747 { 4748 volatile uint32_t reserved:32; 4749 }; 4750 uint32_t v; 4751 }reg_0x1d1_reserved; 4752 4753 /* REG_0x1d2 */ 4754 union 4755 { 4756 struct 4757 { 4758 volatile uint32_t reserved:32; 4759 }; 4760 uint32_t v; 4761 }reg_0x1d2_reserved; 4762 4763 /* REG_0x1d3 */ 4764 union 4765 { 4766 struct 4767 { 4768 volatile uint32_t reserved:32; 4769 }; 4770 uint32_t v; 4771 }reg_0x1d3_reserved; 4772 4773 /* REG_0x1d4 */ 4774 union 4775 { 4776 struct 4777 { 4778 volatile uint32_t reserved:32; 4779 }; 4780 uint32_t v; 4781 }reg_0x1d4_reserved; 4782 4783 /* REG_0x1d5 */ 4784 union 4785 { 4786 struct 4787 { 4788 volatile uint32_t reserved:32; 4789 }; 4790 uint32_t v; 4791 }reg_0x1d5_reserved; 4792 4793 /* REG_0x1d6 */ 4794 union 4795 { 4796 struct 4797 { 4798 volatile uint32_t reserved:32; 4799 }; 4800 uint32_t v; 4801 }reg_0x1d6_reserved; 4802 4803 /* REG_0x1d7 */ 4804 union 4805 { 4806 struct 4807 { 4808 volatile uint32_t reserved:32; 4809 }; 4810 uint32_t v; 4811 }reg_0x1d7_reserved; 4812 4813 /* REG_0x1d8 */ 4814 union 4815 { 4816 struct 4817 { 4818 volatile uint32_t reserved:32; 4819 }; 4820 uint32_t v; 4821 }reg_0x1d8_reserved; 4822 4823 /* REG_0x1d9 */ 4824 union 4825 { 4826 struct 4827 { 4828 volatile uint32_t reserved:32; 4829 }; 4830 uint32_t v; 4831 }reg_0x1d9_reserved; 4832 4833 /* REG_0x1da */ 4834 union 4835 { 4836 struct 4837 { 4838 volatile uint32_t reserved:32; 4839 }; 4840 uint32_t v; 4841 }reg_0x1da_reserved; 4842 4843 /* REG_0x1db */ 4844 union 4845 { 4846 struct 4847 { 4848 volatile uint32_t reserved:32; 4849 }; 4850 uint32_t v; 4851 }reg_0x1db_reserved; 4852 4853 /* REG_0x1dc */ 4854 union 4855 { 4856 struct 4857 { 4858 volatile uint32_t reserved:32; 4859 }; 4860 uint32_t v; 4861 }reg_0x1dc_reserved; 4862 4863 /* REG_0x1dd */ 4864 union 4865 { 4866 struct 4867 { 4868 volatile uint32_t reserved:32; 4869 }; 4870 uint32_t v; 4871 }reg_0x1dd_reserved; 4872 4873 /* REG_0x1de */ 4874 union 4875 { 4876 struct 4877 { 4878 volatile uint32_t reserved:32; 4879 }; 4880 uint32_t v; 4881 }reg_0x1de_reserved; 4882 4883 /* REG_0x1df */ 4884 union 4885 { 4886 struct 4887 { 4888 volatile uint32_t reserved:32; 4889 }; 4890 uint32_t v; 4891 }reg_0x1df_reserved; 4892 4893 /* REG_0x1e0 */ 4894 union 4895 { 4896 struct 4897 { 4898 volatile uint32_t reserved:32; 4899 }; 4900 uint32_t v; 4901 }reg_0x1e0_reserved; 4902 4903 /* REG_0x1e1 */ 4904 union 4905 { 4906 struct 4907 { 4908 volatile uint32_t reserved:32; 4909 }; 4910 uint32_t v; 4911 }reg_0x1e1_reserved; 4912 4913 /* REG_0x1e2 */ 4914 union 4915 { 4916 struct 4917 { 4918 volatile uint32_t reserved:32; 4919 }; 4920 uint32_t v; 4921 }reg_0x1e2_reserved; 4922 4923 /* REG_0x1e3 */ 4924 union 4925 { 4926 struct 4927 { 4928 volatile uint32_t reserved:32; 4929 }; 4930 uint32_t v; 4931 }reg_0x1e3_reserved; 4932 4933 /* REG_0x1e4 */ 4934 union 4935 { 4936 struct 4937 { 4938 volatile uint32_t reserved:32; 4939 }; 4940 uint32_t v; 4941 }reg_0x1e4_reserved; 4942 4943 /* REG_0x1e5 */ 4944 union 4945 { 4946 struct 4947 { 4948 volatile uint32_t reserved:32; 4949 }; 4950 uint32_t v; 4951 }reg_0x1e5_reserved; 4952 4953 /* REG_0x1e6 */ 4954 union 4955 { 4956 struct 4957 { 4958 volatile uint32_t reserved:32; 4959 }; 4960 uint32_t v; 4961 }reg_0x1e6_reserved; 4962 4963 /* REG_0x1e7 */ 4964 union 4965 { 4966 struct 4967 { 4968 volatile uint32_t reserved:32; 4969 }; 4970 uint32_t v; 4971 }reg_0x1e7_reserved; 4972 4973 /* REG_0x1e8 */ 4974 union 4975 { 4976 struct 4977 { 4978 volatile uint32_t reserved:32; 4979 }; 4980 uint32_t v; 4981 }reg_0x1e8_reserved; 4982 4983 /* REG_0x1e9 */ 4984 union 4985 { 4986 struct 4987 { 4988 volatile uint32_t reserved:32; 4989 }; 4990 uint32_t v; 4991 }reg_0x1e9_reserved; 4992 4993 /* REG_0x1ea */ 4994 union 4995 { 4996 struct 4997 { 4998 volatile uint32_t reserved:32; 4999 }; 5000 uint32_t v; 5001 }reg_0x1ea_reserved; 5002 5003 /* REG_0x1eb */ 5004 union 5005 { 5006 struct 5007 { 5008 volatile uint32_t reserved:32; 5009 }; 5010 uint32_t v; 5011 }reg_0x1eb_reserved; 5012 5013 /* REG_0x1ec */ 5014 union 5015 { 5016 struct 5017 { 5018 volatile uint32_t reserved:32; 5019 }; 5020 uint32_t v; 5021 }reg_0x1ec_reserved; 5022 5023 /* REG_0x1ed */ 5024 union 5025 { 5026 struct 5027 { 5028 volatile uint32_t reserved:32; 5029 }; 5030 uint32_t v; 5031 }reg_0x1ed_reserved; 5032 5033 /* REG_0x1ee */ 5034 union 5035 { 5036 struct 5037 { 5038 volatile uint32_t reserved:32; 5039 }; 5040 uint32_t v; 5041 }reg_0x1ee_reserved; 5042 5043 /* REG_0x1ef */ 5044 union 5045 { 5046 struct 5047 { 5048 volatile uint32_t reserved:32; 5049 }; 5050 uint32_t v; 5051 }reg_0x1ef_reserved; 5052 5053 /* REG_0x1f0 */ 5054 union 5055 { 5056 struct 5057 { 5058 volatile uint32_t reserved:32; 5059 }; 5060 uint32_t v; 5061 }reg_0x1f0_reserved; 5062 5063 /* REG_0x1f1 */ 5064 union 5065 { 5066 struct 5067 { 5068 volatile uint32_t reserved:32; 5069 }; 5070 uint32_t v; 5071 }reg_0x1f1_reserved; 5072 5073 /* REG_0x1f2 */ 5074 union 5075 { 5076 struct 5077 { 5078 volatile uint32_t reserved:32; 5079 }; 5080 uint32_t v; 5081 }reg_0x1f2_reserved; 5082 5083 /* REG_0x1f3 */ 5084 union 5085 { 5086 struct 5087 { 5088 volatile uint32_t reserved:32; 5089 }; 5090 uint32_t v; 5091 }reg_0x1f3_reserved; 5092 5093 /* REG_0x1f4 */ 5094 union 5095 { 5096 struct 5097 { 5098 volatile uint32_t reserved:32; 5099 }; 5100 uint32_t v; 5101 }reg_0x1f4_reserved; 5102 5103 /* REG_0x1f5 */ 5104 union 5105 { 5106 struct 5107 { 5108 volatile uint32_t reserved:32; 5109 }; 5110 uint32_t v; 5111 }reg_0x1f5_reserved; 5112 5113 /* REG_0x1f6 */ 5114 union 5115 { 5116 struct 5117 { 5118 volatile uint32_t reserved:32; 5119 }; 5120 uint32_t v; 5121 }reg_0x1f6_reserved; 5122 5123 /* REG_0x1f7 */ 5124 union 5125 { 5126 struct 5127 { 5128 volatile uint32_t reserved:32; 5129 }; 5130 uint32_t v; 5131 }reg_0x1f7_reserved; 5132 5133 /* REG_0x1f8 */ 5134 union 5135 { 5136 struct 5137 { 5138 volatile uint32_t reserved:32; 5139 }; 5140 uint32_t v; 5141 }reg_0x1f8_reserved; 5142 5143 /* REG_0x1f9 */ 5144 union 5145 { 5146 struct 5147 { 5148 volatile uint32_t reserved:32; 5149 }; 5150 uint32_t v; 5151 }reg_0x1f9_reserved; 5152 5153 /* REG_0x1fa */ 5154 union 5155 { 5156 struct 5157 { 5158 volatile uint32_t reserved:32; 5159 }; 5160 uint32_t v; 5161 }reg_0x1fa_reserved; 5162 5163 /* REG_0x1fb */ 5164 union 5165 { 5166 struct 5167 { 5168 volatile uint32_t reserved:32; 5169 }; 5170 uint32_t v; 5171 }reg_0x1fb_reserved; 5172 5173 /* REG_0x1fc */ 5174 union 5175 { 5176 struct 5177 { 5178 volatile uint32_t reserved:32; 5179 }; 5180 uint32_t v; 5181 }reg_0x1fc_reserved; 5182 5183 /* REG_0x1fd */ 5184 union 5185 { 5186 struct 5187 { 5188 volatile uint32_t reserved:32; 5189 }; 5190 uint32_t v; 5191 }reg_0x1fd_reserved; 5192 5193 /* REG_0x1fe */ 5194 union 5195 { 5196 struct 5197 { 5198 volatile uint32_t reserved:32; 5199 }; 5200 uint32_t v; 5201 }reg_0x1fe_reserved; 5202 5203 /* REG_0x1ff */ 5204 union 5205 { 5206 struct 5207 { 5208 volatile uint32_t reserved:32; 5209 }; 5210 uint32_t v; 5211 }reg_0x1ff_reserved; 5212 5213 /* REG_0x200 */ 5214 union 5215 { 5216 struct 5217 { 5218 volatile uint32_t blue : 1; //0x200[ 7: 0],blue value foe index<y>for the bg.,0,RW 5219 volatile uint32_t green : 1; //0x200[15: 8],green value foe index<y>for the bg.,0,RW 5220 volatile uint32_t red : 1; //0x200[23:16],red value foe index<y>for the bg.,0,RW 5221 volatile uint32_t alpha : 1; //0x200[31:24],alpha value foe index<y>for the bg.,0,RW 5222 }; 5223 uint32_t v; 5224 }dma2d_bg_clut0; 5225 } dma2d_hw_t; 5226 5227 #ifdef __cplusplus 5228 } 5229 #endif 5230 5231