1 // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _SOC_UHCI_STRUCT_H_ 15 #define _SOC_UHCI_STRUCT_H_ 16 17 #include <stdint.h> 18 19 #ifdef __cplusplus 20 extern "C" { 21 #endif 22 23 typedef volatile struct uhci_dev_s { 24 union { 25 struct { 26 uint32_t in_rst: 1; /*Set this bit to reset in link operations.*/ 27 uint32_t out_rst: 1; /*Set this bit to reset out link operations.*/ 28 uint32_t ahbm_fifo_rst: 1; /*Set this bit to reset dma ahb fifo.*/ 29 uint32_t ahbm_rst: 1; /*Set this bit to reset dma ahb interface.*/ 30 uint32_t in_loop_test: 1; /*Set this bit to enable loop test for in links.*/ 31 uint32_t out_loop_test: 1; /*Set this bit to enable loop test for out links.*/ 32 uint32_t out_auto_wrback: 1; /*when in link's length is 0 go on to use the next in link automatically.*/ 33 uint32_t out_no_restart_clr: 1; /*don't use*/ 34 uint32_t out_eof_mode: 1; /*Set this bit to produce eof after DMA pops all data clear this bit to produce eof after DMA pushes all data*/ 35 uint32_t uart0_ce: 1; /*Set this bit to use UART to transmit or receive data.*/ 36 uint32_t uart1_ce: 1; /*Set this bit to use UART1 to transmit or receive data.*/ 37 uint32_t uart2_ce: 1; /*Set this bit to use UART2 to transmit or receive data.*/ 38 uint32_t outdscr_burst_en: 1; /*Set this bit to enable DMA in links to use burst mode.*/ 39 uint32_t indscr_burst_en: 1; /*Set this bit to enable DMA out links to use burst mode.*/ 40 uint32_t out_data_burst_en: 1; /*Set this bit to enable DMA burst MODE*/ 41 uint32_t mem_trans_en: 1; 42 uint32_t seper_en: 1; /*Set this bit to use special char to separate the data frame.*/ 43 uint32_t head_en: 1; /*Set this bit to enable to use head packet before the data frame.*/ 44 uint32_t crc_rec_en: 1; /*Set this bit to enable receiver''s ability of crc calculation when crc_en bit in head packet is 1 then there will be crc bytes after data_frame*/ 45 uint32_t uart_idle_eof_en: 1; /*Set this bit to enable to use idle time when the idle time after data frame is satisfied this means the end of a data frame.*/ 46 uint32_t len_eof_en: 1; /*Set this bit to enable to use packet_len in packet head when the received data is equal to packet_len this means the end of a data frame.*/ 47 uint32_t encode_crc_en: 1; /*Set this bit to enable crc calculation for data frame when bit6 in the head packet is 1.*/ 48 uint32_t clk_en: 1; /*Set this bit to enable clock-gating for read or write registers.*/ 49 uint32_t uart_rx_brk_eof_en: 1; /*Set this bit to enable to use brk char as the end of a data frame.*/ 50 uint32_t reserved24: 8; 51 }; 52 uint32_t val; 53 } conf0; 54 union { 55 struct { 56 uint32_t rx_start: 1; /*when a separator char has been send it will produce uhci_rx_start_int interrupt.*/ 57 uint32_t tx_start: 1; /*when DMA detects a separator char it will produce uhci_tx_start_int interrupt.*/ 58 uint32_t rx_hung: 1; /*when DMA takes a lot of time to receive a data it will produce uhci_rx_hung_int interrupt.*/ 59 uint32_t tx_hung: 1; /*when DMA takes a lot of time to read a data from RAM it will produce uhci_tx_hung_int interrupt.*/ 60 uint32_t in_done: 1; /*when a in link descriptor has been completed it will produce uhci_in_done_int interrupt.*/ 61 uint32_t in_suc_eof: 1; /*when a data packet has been received it will produce uhci_in_suc_eof_int interrupt.*/ 62 uint32_t in_err_eof: 1; /*when there are some errors about eof in in link descriptor it will produce uhci_in_err_eof_int interrupt.*/ 63 uint32_t out_done: 1; /*when a out link descriptor is completed it will produce uhci_out_done_int interrupt.*/ 64 uint32_t out_eof: 1; /*when the current descriptor's eof bit is 1 it will produce uhci_out_eof_int interrupt.*/ 65 uint32_t in_dscr_err: 1; /*when there are some errors about the out link descriptor it will produce uhci_in_dscr_err_int interrupt.*/ 66 uint32_t out_dscr_err: 1; /*when there are some errors about the in link descriptor it will produce uhci_out_dscr_err_int interrupt.*/ 67 uint32_t in_dscr_empty: 1; /*when there are not enough in links for DMA it will produce uhci_in_dscr_err_int interrupt.*/ 68 uint32_t outlink_eof_err: 1; /*when there are some errors about eof in outlink descriptor it will produce uhci_outlink_eof_err_int interrupt.*/ 69 uint32_t out_total_eof: 1; /*When all data have been send it will produce uhci_out_total_eof_int interrupt.*/ 70 uint32_t send_s_q: 1; /*When use single send registers to send a short packets it will produce this interrupt when dma has send the short packet.*/ 71 uint32_t send_a_q: 1; /*When use always_send registers to send a series of short packets it will produce this interrupt when dma has send the short packet.*/ 72 uint32_t dma_in_fifo_full_wm: 1; 73 uint32_t reserved17: 15; 74 }; 75 uint32_t val; 76 } int_raw; 77 union { 78 struct { 79 uint32_t rx_start: 1; 80 uint32_t tx_start: 1; 81 uint32_t rx_hung: 1; 82 uint32_t tx_hung: 1; 83 uint32_t in_done: 1; 84 uint32_t in_suc_eof: 1; 85 uint32_t in_err_eof: 1; 86 uint32_t out_done: 1; 87 uint32_t out_eof: 1; 88 uint32_t in_dscr_err: 1; 89 uint32_t out_dscr_err: 1; 90 uint32_t in_dscr_empty: 1; 91 uint32_t outlink_eof_err: 1; 92 uint32_t out_total_eof: 1; 93 uint32_t send_s_q: 1; 94 uint32_t send_a_q: 1; 95 uint32_t dma_in_fifo_full_wm: 1; 96 uint32_t reserved17: 15; 97 }; 98 uint32_t val; 99 } int_st; 100 union { 101 struct { 102 uint32_t rx_start: 1; 103 uint32_t tx_start: 1; 104 uint32_t rx_hung: 1; 105 uint32_t tx_hung: 1; 106 uint32_t in_done: 1; 107 uint32_t in_suc_eof: 1; 108 uint32_t in_err_eof: 1; 109 uint32_t out_done: 1; 110 uint32_t out_eof: 1; 111 uint32_t in_dscr_err: 1; 112 uint32_t out_dscr_err: 1; 113 uint32_t in_dscr_empty: 1; 114 uint32_t outlink_eof_err: 1; 115 uint32_t out_total_eof: 1; 116 uint32_t send_s_q: 1; 117 uint32_t send_a_q: 1; 118 uint32_t dma_in_fifo_full_wm: 1; 119 uint32_t reserved17: 15; 120 }; 121 uint32_t val; 122 } int_ena; 123 union { 124 struct { 125 uint32_t rx_start: 1; 126 uint32_t tx_start: 1; 127 uint32_t rx_hung: 1; 128 uint32_t tx_hung: 1; 129 uint32_t in_done: 1; 130 uint32_t in_suc_eof: 1; 131 uint32_t in_err_eof: 1; 132 uint32_t out_done: 1; 133 uint32_t out_eof: 1; 134 uint32_t in_dscr_err: 1; 135 uint32_t out_dscr_err: 1; 136 uint32_t in_dscr_empty: 1; 137 uint32_t outlink_eof_err: 1; 138 uint32_t out_total_eof: 1; 139 uint32_t send_s_q: 1; 140 uint32_t send_a_q: 1; 141 uint32_t dma_in_fifo_full_wm: 1; 142 uint32_t reserved17: 15; 143 }; 144 uint32_t val; 145 } int_clr; 146 union { 147 struct { 148 uint32_t full: 1; /*1:DMA out link descriptor's fifo is full.*/ 149 uint32_t empty: 1; /*1:DMA in link descriptor's fifo is empty.*/ 150 uint32_t reserved2: 30; 151 }; 152 uint32_t val; 153 } dma_out_status; 154 union { 155 struct { 156 uint32_t fifo_wdata: 9; /*This is the data need to be pushed into out link descriptor's fifo.*/ 157 uint32_t reserved9: 7; 158 uint32_t fifo_push: 1; /*Set this bit to push data in out link descriptor's fifo.*/ 159 uint32_t reserved17:15; 160 }; 161 uint32_t val; 162 } dma_out_push; 163 union { 164 struct { 165 uint32_t full: 1; 166 uint32_t empty: 1; 167 uint32_t reserved2: 2; 168 uint32_t rx_err_cause: 3; /*This register stores the errors caused in out link descriptor's data packet.*/ 169 uint32_t reserved7: 25; 170 }; 171 uint32_t val; 172 } dma_in_status; 173 union { 174 struct { 175 uint32_t fifo_rdata: 12; /*This register stores the data pop from in link descriptor's fifo.*/ 176 uint32_t reserved12: 4; 177 uint32_t fifo_pop: 1; /*Set this bit to pop data in in link descriptor's fifo.*/ 178 uint32_t reserved17: 15; 179 }; 180 uint32_t val; 181 } dma_in_pop; 182 union { 183 struct { 184 uint32_t addr: 20; /*This register stores the least 20 bits of the first out link descriptor's address.*/ 185 uint32_t reserved20: 8; 186 uint32_t stop: 1; /*Set this bit to stop dealing with the out link descriptors.*/ 187 uint32_t start: 1; /*Set this bit to start dealing with the out link descriptors.*/ 188 uint32_t restart: 1; /*Set this bit to mount on new out link descriptors*/ 189 uint32_t park: 1; /*1： the out link descriptor's fsm is in idle state. 0:the out link descriptor's fsm is working.*/ 190 }; 191 uint32_t val; 192 } dma_out_link; 193 union { 194 struct { 195 uint32_t addr: 20; /*This register stores the least 20 bits of the first in link descriptor's address.*/ 196 uint32_t auto_ret: 1; /*1:when a packet is wrong in link descriptor returns to the descriptor which is lately used.*/ 197 uint32_t reserved21: 7; 198 uint32_t stop: 1; /*Set this bit to stop dealing with the in link descriptors.*/ 199 uint32_t start: 1; /*Set this bit to start dealing with the in link descriptors.*/ 200 uint32_t restart: 1; /*Set this bit to mount on new in link descriptors*/ 201 uint32_t park: 1; /*1:the in link descriptor's fsm is in idle state. 0:the in link descriptor's fsm is working*/ 202 }; 203 uint32_t val; 204 } dma_in_link; 205 union { 206 struct { 207 uint32_t check_sum_en: 1; /*Set this bit to enable decoder to check check_sum in packet header.*/ 208 uint32_t check_seq_en: 1; /*Set this bit to enable decoder to check seq num in packet header.*/ 209 uint32_t crc_disable: 1; /*Set this bit to disable crc calculation.*/ 210 uint32_t save_head: 1; /*Set this bit to save packet header .*/ 211 uint32_t tx_check_sum_re: 1; /*Set this bit to enable hardware replace check_sum in packet header automatically.*/ 212 uint32_t tx_ack_num_re: 1; /*Set this bit to enable hardware replace ack num in packet header automatically.*/ 213 uint32_t check_owner: 1; /*Set this bit to check the owner bit in link descriptor.*/ 214 uint32_t wait_sw_start: 1; /*Set this bit to enable software way to add packet header.*/ 215 uint32_t sw_start: 1; /*Set this bit to start inserting the packet header.*/ 216 uint32_t dma_in_fifo_full_thrs:12; /*when data amount in link descriptor's fifo is more than this register value it will produce uhci_dma_in_fifo_full_wm_int interrupt.*/ 217 uint32_t reserved21: 11; 218 }; 219 uint32_t val; 220 } conf1; 221 uint32_t state0; /**/ 222 uint32_t state1; /**/ 223 uint32_t dma_out_eof_des_addr; /*This register stores the address of out link description when eof bit in this descriptor is 1.*/ 224 uint32_t dma_in_suc_eof_des_addr; /*This register stores the address of in link descriptor when eof bit in this descriptor is 1.*/ 225 uint32_t dma_in_err_eof_des_addr; /*This register stores the address of in link descriptor when there are some errors in this descriptor.*/ 226 uint32_t dma_out_eof_bfr_des_addr; /*This register stores the address of out link descriptor when there are some errors in this descriptor.*/ 227 union { 228 struct { 229 uint32_t test_mode: 3; /*bit2 is ahb bus test enable ，bit1 is used to choose write(1) or read(0) mode. bit0 is used to choose test only once(1) or continue(0)*/ 230 uint32_t reserved3: 1; 231 uint32_t test_addr: 2; /*The two bits represent ahb bus address bit[20:19]*/ 232 uint32_t reserved6: 26; 233 }; 234 uint32_t val; 235 } ahb_test; 236 uint32_t dma_in_dscr; /*The content of current in link descriptor's third dword*/ 237 uint32_t dma_in_dscr_bf0; /*The content of current in link descriptor's first dword*/ 238 uint32_t dma_in_dscr_bf1; /*The content of current in link descriptor's second dword*/ 239 uint32_t dma_out_dscr; /*The content of current out link descriptor's third dword*/ 240 uint32_t dma_out_dscr_bf0; /*The content of current out link descriptor's first dword*/ 241 uint32_t dma_out_dscr_bf1; /*The content of current out link descriptor's second dword*/ 242 union { 243 struct { 244 uint32_t tx_c0_esc_en: 1; /*Set this bit to enable 0xc0 char decode when DMA receives data.*/ 245 uint32_t tx_db_esc_en: 1; /*Set this bit to enable 0xdb char decode when DMA receives data.*/ 246 uint32_t tx_11_esc_en: 1; /*Set this bit to enable flow control char 0x11 decode when DMA receives data.*/ 247 uint32_t tx_13_esc_en: 1; /*Set this bit to enable flow control char 0x13 decode when DMA receives data.*/ 248 uint32_t rx_c0_esc_en: 1; /*Set this bit to enable 0xc0 char replace when DMA sends data.*/ 249 uint32_t rx_db_esc_en: 1; /*Set this bit to enable 0xdb char replace when DMA sends data.*/ 250 uint32_t rx_11_esc_en: 1; /*Set this bit to enable flow control char 0x11 replace when DMA sends data.*/ 251 uint32_t rx_13_esc_en: 1; /*Set this bit to enable flow control char 0x13 replace when DMA sends data.*/ 252 uint32_t reserved8: 24; 253 }; 254 uint32_t val; 255 } escape_conf; 256 union { 257 struct { 258 uint32_t txfifo_timeout: 8; /*This register stores the timeout value.when DMA takes more time than this register value to receive a data it will produce uhci_tx_hung_int interrupt.*/ 259 uint32_t txfifo_timeout_shift: 3; /*The tick count is cleared when its value >=(17'd8000>>reg_txfifo_timeout_shift)*/ 260 uint32_t txfifo_timeout_ena: 1; /*The enable bit for tx fifo receive data timeout*/ 261 uint32_t rxfifo_timeout: 8; /*This register stores the timeout value.when DMA takes more time than this register value to read a data from RAM it will produce uhci_rx_hung_int interrupt.*/ 262 uint32_t rxfifo_timeout_shift: 3; /*The tick count is cleared when its value >=(17'd8000>>reg_rxfifo_timeout_shift)*/ 263 uint32_t rxfifo_timeout_ena: 1; /*This is the enable bit for DMA send data timeout*/ 264 uint32_t reserved24: 8; 265 }; 266 uint32_t val; 267 } hung_conf; 268 uint32_t ack_num; /**/ 269 uint32_t rx_head; /*This register stores the packet header received by DMA*/ 270 union { 271 struct { 272 uint32_t single_send_num: 3; /*The bits are used to choose which short packet*/ 273 uint32_t single_send_en: 1; /*Set this bit to enable send a short packet*/ 274 uint32_t always_send_num: 3; /*The bits are used to choose which short packet*/ 275 uint32_t always_send_en: 1; /*Set this bit to enable continuously send the same short packet*/ 276 uint32_t reserved8: 24; 277 }; 278 uint32_t val; 279 } quick_sent; 280 struct{ 281 uint32_t w_data[2]; /*This register stores the content of short packet's dword*/ 282 } q_data[7]; 283 union { 284 struct { 285 uint32_t seper_char: 8; /*This register stores the separator char separator char is used to separate the data frame.*/ 286 uint32_t seper_esc_char0: 8; /*This register stores the first char used to replace separator char in data.*/ 287 uint32_t seper_esc_char1: 8; /*This register stores the second char used to replace separator char in data . 0xdc 0xdb replace 0xc0 by default.*/ 288 uint32_t reserved24: 8; 289 }; 290 uint32_t val; 291 } esc_conf0; 292 union { 293 struct { 294 uint32_t seq0: 8; /*This register stores the first substitute char used to replace the separate char.*/ 295 uint32_t seq0_char0: 8; /*This register stores the first char used to replace reg_esc_seq0 in data.*/ 296 uint32_t seq0_char1: 8; /*This register stores the second char used to replace the reg_esc_seq0 in data*/ 297 uint32_t reserved24: 8; 298 }; 299 uint32_t val; 300 } esc_conf1; 301 union { 302 struct { 303 uint32_t seq1: 8; /*This register stores the flow control char to turn on the flow_control*/ 304 uint32_t seq1_char0: 8; /*This register stores the first char used to replace the reg_esc_seq1 in data.*/ 305 uint32_t seq1_char1: 8; /*This register stores the second char used to replace the reg_esc_seq1 in data.*/ 306 uint32_t reserved24: 8; 307 }; 308 uint32_t val; 309 } esc_conf2; 310 union { 311 struct { 312 uint32_t seq2: 8; /*This register stores the flow_control char to turn off the flow_control*/ 313 uint32_t seq2_char0: 8; /*This register stores the first char used to replace the reg_esc_seq2 in data.*/ 314 uint32_t seq2_char1: 8; /*This register stores the second char used to replace the reg_esc_seq2 in data.*/ 315 uint32_t reserved24: 8; 316 }; 317 uint32_t val; 318 } esc_conf3; 319 union { 320 struct { 321 uint32_t thrs: 13; /*when the amount of packet payload is larger than this value the process of receiving data is done.*/ 322 uint32_t reserved13:19; 323 }; 324 uint32_t val; 325 } pkt_thres; 326 uint32_t reserved_c4; 327 uint32_t reserved_c8; 328 uint32_t reserved_cc; 329 uint32_t reserved_d0; 330 uint32_t reserved_d4; 331 uint32_t reserved_d8; 332 uint32_t reserved_dc; 333 uint32_t reserved_e0; 334 uint32_t reserved_e4; 335 uint32_t reserved_e8; 336 uint32_t reserved_ec; 337 uint32_t reserved_f0; 338 uint32_t reserved_f4; 339 uint32_t reserved_f8; 340 uint32_t date; /*version information*/ 341 } uhci_dev_t; 342 extern uhci_dev_t UHCI0; 343 extern uhci_dev_t UHCI1; 344 345 #ifdef __cplusplus 346 } 347 #endif 348 349 #endif /* _SOC_UHCI_STRUCT_H_ */ 350