1root { 2 platform { 3 template iwdg_controller { 4 5 num = 0; // iwdg num 6 7 reg_base = 0x5C003000; 8 reg_step = 0x400; 9 10 timeout_sec = 32; // default iwdg timeout(s) 11 12 start = false; 13 14 clock_rate = 32000; // default clock source rate 15 } 16 controller_0x5C003000 :: iwdg_controller { 17 match_attr = "stm32mp1_iwdg_0"; 18 } 19 controller_0x5A002000 :: iwdg_controller { 20 match_attr = "stm32mp1_iwdg_1"; 21 num = 1; 22 reg_base = 0x5A002000; 23 start = true; 24 } 25 } 26} 27