1 /* 2 * Copyright (C) 2023 Huawei Device Co., Ltd. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #ifndef API_RENDER_DEVICE_PIPELINE_STATE_DESC_H 17 #define API_RENDER_DEVICE_PIPELINE_STATE_DESC_H 18 19 #include <cstdint> 20 21 #include <base/containers/array_view.h> 22 #include <base/util/formats.h> 23 #include <render/namespace.h> 24 #include <render/resource_handle.h> 25 26 RENDER_BEGIN_NAMESPACE() 27 /** \addtogroup group_render_pipelinestatedesc 28 * @{ 29 */ 30 /** Index type */ 31 enum IndexType { 32 /** UINT16 */ 33 CORE_INDEX_TYPE_UINT16 = 0, 34 /** UINT32 */ 35 CORE_INDEX_TYPE_UINT32 = 1, 36 /** Max enumeration */ 37 CORE_INDEX_TYPE_MAX_ENUM = 0x7FFFFFFF 38 }; 39 40 /** Memory property flag bits */ 41 enum MemoryPropertyFlagBits { 42 /** Device local bit */ 43 CORE_MEMORY_PROPERTY_DEVICE_LOCAL_BIT = 0x00000001, 44 /** Host visible bit */ 45 CORE_MEMORY_PROPERTY_HOST_VISIBLE_BIT = 0x00000002, 46 /** Host visible bit */ 47 CORE_MEMORY_PROPERTY_HOST_COHERENT_BIT = 0x00000004, 48 /** Host cached bit, always preferred not required for allocation */ 49 CORE_MEMORY_PROPERTY_HOST_CACHED_BIT = 0x00000008, 50 /** Lazily allocated bit, always preferred not required for allocation */ 51 CORE_MEMORY_PROPERTY_LAZILY_ALLOCATED_BIT = 0x00000010, 52 /** Protected bit, always preferred not required for allocation */ 53 CORE_MEMORY_PROPERTY_PROTECTED_BIT = 0x00000020, 54 /** Max enumeration */ 55 CORE_MEMORY_PROPERTY_FLAG_BITS_MAX_ENUM = 0x7FFFFFFF 56 }; 57 /** Container for memory property flag bits */ 58 using MemoryPropertyFlags = uint32_t; 59 60 enum FormatFeatureFlagBits { 61 /** Sampled image bit */ 62 CORE_FORMAT_FEATURE_SAMPLED_IMAGE_BIT = 0x00000001, 63 /** Storage image bit */ 64 CORE_FORMAT_FEATURE_STORAGE_IMAGE_BIT = 0x00000002, 65 /** Image atomic bit */ 66 CORE_FORMAT_FEATURE_STORAGE_IMAGE_ATOMIC_BIT = 0x00000004, 67 /** Uniform texel buffer bit */ 68 CORE_FORMAT_FEATURE_UNIFORM_TEXEL_BUFFER_BIT = 0x00000008, 69 /** Storage texel buffer bit */ 70 CORE_FORMAT_FEATURE_STORAGE_TEXEL_BUFFER_BIT = 0x00000010, 71 /** Storage texel buffer atomic bit */ 72 CORE_FORMAT_FEATURE_STORAGE_TEXEL_BUFFER_ATOMIC_BIT = 0x00000020, 73 /** Vertex buffer bit */ 74 CORE_FORMAT_FEATURE_VERTEX_BUFFER_BIT = 0x00000040, 75 /** Color attachment bit */ 76 CORE_FORMAT_FEATURE_COLOR_ATTACHMENT_BIT = 0x00000080, 77 /** Color attachment blend bit */ 78 CORE_FORMAT_FEATURE_COLOR_ATTACHMENT_BLEND_BIT = 0x00000100, 79 /** Depth stencil attachment bit */ 80 CORE_FORMAT_FEATURE_DEPTH_STENCIL_ATTACHMENT_BIT = 0x00000200, 81 /** Blit src bit */ 82 CORE_FORMAT_FEATURE_BLIT_SRC_BIT = 0x00000400, 83 /** Blit dst bit */ 84 CORE_FORMAT_FEATURE_BLIT_DST_BIT = 0x00000800, 85 /** Sampled image filter linear bit */ 86 CORE_FORMAT_FEATURE_SAMPLED_IMAGE_FILTER_LINEAR_BIT = 0x00001000, 87 /** Transfer src bit */ 88 CORE_FORMAT_FEATURE_TRANSFER_SRC_BIT = 0x00004000, 89 /** Transfer dst bit */ 90 CORE_FORMAT_FEATURE_TRANSFER_DST_BIT = 0x00008000, 91 }; 92 /** Format feature flags */ 93 using FormatFeatureFlags = uint32_t; 94 95 /** Format properties */ 96 struct FormatProperties { 97 /** Linear tiling feature flags */ 98 FormatFeatureFlags linearTilingFeatures { 0u }; 99 /** Optimal tiling feature flags */ 100 FormatFeatureFlags optimalTilingFeatures { 0u }; 101 /** Buffer feature flags */ 102 FormatFeatureFlags bufferFeatures { 0u }; 103 /** Bytes per pixel */ 104 uint32_t bytesPerPixel { 0u }; 105 }; 106 107 /** Image layout */ 108 enum ImageLayout { 109 /** Undefined */ 110 CORE_IMAGE_LAYOUT_UNDEFINED = 0, 111 /** General */ 112 CORE_IMAGE_LAYOUT_GENERAL = 1, 113 /** Color attachment optimal */ 114 CORE_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL = 2, 115 /** Depth stencil attachment optimal */ 116 CORE_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL = 3, 117 /** Depth stencil read only optimal */ 118 CORE_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL = 4, 119 /** Shader read only optimal */ 120 CORE_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL = 5, 121 /** Transfer source optimal */ 122 CORE_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL = 6, 123 /** Transfer destination optimal */ 124 CORE_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL = 7, 125 /** Preinitialized */ 126 CORE_IMAGE_LAYOUT_PREINITIALIZED = 8, 127 /** Depth read only stencil attachment optimal */ 128 CORE_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL = 1000117000, 129 /** Depth attachment stencil read only optimal */ 130 CORE_IMAGE_LAYOUT_DEPTH_ATTACHMENT_STENCIL_READ_ONLY_OPTIMAL = 1000117001, 131 /** Present source KHR */ 132 CORE_IMAGE_LAYOUT_PRESENT_SRC_KHR = 1000001002, 133 /** Shared present source KHR */ 134 CORE_IMAGE_LAYOUT_SHARED_PRESENT_KHR = 1000111000, 135 /** Max enumeration */ 136 CORE_IMAGE_LAYOUT_MAX_ENUM = 0x7FFFFFFF 137 }; 138 139 /** Image aspect flag bits */ 140 enum ImageAspectFlagBits { 141 /** Color bit */ 142 CORE_IMAGE_ASPECT_COLOR_BIT = 0x00000001, 143 /** Depth bit */ 144 CORE_IMAGE_ASPECT_DEPTH_BIT = 0x00000002, 145 /** Stencil bit */ 146 CORE_IMAGE_ASPECT_STENCIL_BIT = 0x00000004, 147 /** Metadata bit */ 148 CORE_IMAGE_ASPECT_METADATA_BIT = 0x00000008, 149 /** Aspect plane 0 */ 150 CORE_IMAGE_ASPECT_PLANE_0_BIT = 0x00000010, 151 /** Aspect plane 1 */ 152 CORE_IMAGE_ASPECT_PLANE_1_BIT = 0x00000020, 153 /** Aspect plane 2 */ 154 CORE_IMAGE_ASPECT_PLANE_2_BIT = 0x00000040, 155 /** Max enumeration */ 156 CORE_IMAGE_ASPECT_FLAG_BITS_MAX_ENUM = 0x7FFFFFFF 157 }; 158 /** Container for image aspect flag bits */ 159 using ImageAspectFlags = uint32_t; 160 161 /** Access flag bits */ 162 enum AccessFlagBits { 163 /** Indirect command read bit */ 164 CORE_ACCESS_INDIRECT_COMMAND_READ_BIT = 0x00000001, 165 /** Index read bit */ 166 CORE_ACCESS_INDEX_READ_BIT = 0x00000002, 167 /** Vertex attribute read bit */ 168 CORE_ACCESS_VERTEX_ATTRIBUTE_READ_BIT = 0x00000004, 169 /** Uniform read bit */ 170 CORE_ACCESS_UNIFORM_READ_BIT = 0x00000008, 171 /** Input attachment read bit */ 172 CORE_ACCESS_INPUT_ATTACHMENT_READ_BIT = 0x00000010, 173 /** Shader read bit */ 174 CORE_ACCESS_SHADER_READ_BIT = 0x00000020, 175 /** Shader write bit */ 176 CORE_ACCESS_SHADER_WRITE_BIT = 0x00000040, 177 /** Color attachment read bit */ 178 CORE_ACCESS_COLOR_ATTACHMENT_READ_BIT = 0x00000080, 179 /** Color attachment write bit */ 180 CORE_ACCESS_COLOR_ATTACHMENT_WRITE_BIT = 0x00000100, 181 /** Depth stencil attachment read bit */ 182 CORE_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT = 0x00000200, 183 /** Depth stencil attachment write bit */ 184 CORE_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT = 0x00000400, 185 /** Transfer read bit */ 186 CORE_ACCESS_TRANSFER_READ_BIT = 0x00000800, 187 /** Transfer write bit */ 188 CORE_ACCESS_TRANSFER_WRITE_BIT = 0x00001000, 189 /** Host read bit */ 190 CORE_ACCESS_HOST_READ_BIT = 0x00002000, 191 /** Host write bit */ 192 CORE_ACCESS_HOST_WRITE_BIT = 0x00004000, 193 /** Memory read bit */ 194 CORE_ACCESS_MEMORY_READ_BIT = 0x00008000, 195 /** Memory write bit */ 196 CORE_ACCESS_MEMORY_WRITE_BIT = 0x00010000, 197 }; 198 /** Container for access flag bits */ 199 using AccessFlags = uint32_t; 200 201 /** Pipeline stage flag bits */ 202 enum PipelineStageFlagBits { 203 /** Top of pipe bit */ 204 CORE_PIPELINE_STAGE_TOP_OF_PIPE_BIT = 0x00000001, 205 /** Draw indirect bit */ 206 CORE_PIPELINE_STAGE_DRAW_INDIRECT_BIT = 0x00000002, 207 /** Vertex input bit */ 208 CORE_PIPELINE_STAGE_VERTEX_INPUT_BIT = 0x00000004, 209 /** Vertex shader bit */ 210 CORE_PIPELINE_STAGE_VERTEX_SHADER_BIT = 0x00000008, 211 /** Fragment shader bit */ 212 CORE_PIPELINE_STAGE_FRAGMENT_SHADER_BIT = 0x00000080, 213 /** Early fragment tests bit */ 214 CORE_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT = 0x00000100, 215 /** Late fragment tests bit */ 216 CORE_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT = 0x00000200, 217 /** Color attachment output bit */ 218 CORE_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT = 0x00000400, 219 /** Compute shader bit */ 220 CORE_PIPELINE_STAGE_COMPUTE_SHADER_BIT = 0x00000800, 221 /** Transfer bit */ 222 CORE_PIPELINE_STAGE_TRANSFER_BIT = 0x00001000, 223 /** Bottom of pipe bit */ 224 CORE_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT = 0x00002000, 225 /** Host bit */ 226 CORE_PIPELINE_STAGE_HOST_BIT = 0x00004000, 227 /** All graphics bit */ 228 CORE_PIPELINE_STAGE_ALL_GRAPHICS_BIT = 0x00008000, 229 /** All commands bit */ 230 CORE_PIPELINE_STAGE_ALL_COMMANDS_BIT = 0x00010000, 231 }; 232 /** Container for pipeline stage flag bits */ 233 using PipelineStageFlags = uint32_t; 234 235 /** GPU queue */ 236 struct GpuQueue { 237 /** Queue type */ 238 enum class QueueType { 239 /** Undefined queue type */ 240 UNDEFINED = 0x0, 241 /** Graphics */ 242 GRAPHICS = 0x1, 243 /** Compute */ 244 COMPUTE = 0x2, 245 /** Transfer */ 246 TRANSFER = 0x4, 247 }; 248 249 /** Type of queue */ 250 QueueType type { QueueType::UNDEFINED }; 251 /** Index of queue */ 252 uint32_t index { 0 }; 253 }; 254 255 /** Descriptor type */ 256 enum DescriptorType { 257 /** Sampler */ 258 CORE_DESCRIPTOR_TYPE_SAMPLER = 0, 259 /** Combined image sampler */ 260 CORE_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER = 1, 261 /** Sampled image */ 262 CORE_DESCRIPTOR_TYPE_SAMPLED_IMAGE = 2, 263 /** Storage image */ 264 CORE_DESCRIPTOR_TYPE_STORAGE_IMAGE = 3, 265 /** Uniform texel buffer */ 266 CORE_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER = 4, 267 /** Storage texel buffer */ 268 CORE_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER = 5, 269 /** Uniform buffer */ 270 CORE_DESCRIPTOR_TYPE_UNIFORM_BUFFER = 6, 271 /** Storage buffer */ 272 CORE_DESCRIPTOR_TYPE_STORAGE_BUFFER = 7, 273 /** Dynamic uniform buffer */ 274 CORE_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC = 8, 275 /** Dynamic storage buffer */ 276 CORE_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC = 9, 277 /** Input attachment */ 278 CORE_DESCRIPTOR_TYPE_INPUT_ATTACHMENT = 10, 279 /** Acceleration structure */ 280 CORE_DESCRIPTOR_TYPE_ACCELERATION_STRUCTURE = 1000150000, 281 /** Max enumeration */ 282 CORE_DESCRIPTOR_TYPE_MAX_ENUM = 0x7FFFFFFF 283 }; 284 285 /** Shader stage flag bits */ 286 enum ShaderStageFlagBits { 287 /** Vertex bit */ 288 CORE_SHADER_STAGE_VERTEX_BIT = 0x00000001, 289 /** Fragment bit */ 290 CORE_SHADER_STAGE_FRAGMENT_BIT = 0x00000010, 291 /** Compute bit */ 292 CORE_SHADER_STAGE_COMPUTE_BIT = 0x00000020, 293 /** All graphics */ 294 CORE_SHADER_STAGE_ALL_GRAPHICS = 0x0000001F, 295 /** All */ 296 CORE_SHADER_STAGE_ALL = 0x7FFFFFFF, 297 /** Max enumeration */ 298 CORE_SHADER_STAGE_FLAG_BITS_MAX_ENUM = 0x7FFFFFFF 299 }; 300 /** Shader stage flags */ 301 using ShaderStageFlags = uint32_t; 302 303 /** Pipeline bind point */ 304 enum PipelineBindPoint { 305 /** Bind point graphics */ 306 CORE_PIPELINE_BIND_POINT_GRAPHICS = 0, 307 /** Bind point compute */ 308 CORE_PIPELINE_BIND_POINT_COMPUTE = 1, 309 /** Max enumeration */ 310 CORE_PIPELINE_BIND_POINT_MAX_ENUM = 0x7FFFFFFF 311 }; 312 313 /** Query pipeline statistic flag bits */ 314 enum QueryPipelineStatisticFlagBits { 315 /** Input assembly vertices bit */ 316 CORE_QUERY_PIPELINE_STATISTIC_INPUT_ASSEMBLY_VERTICES_BIT = 0x00000001, 317 /** Input assembly primitives bit */ 318 CORE_QUERY_PIPELINE_STATISTIC_INPUT_ASSEMBLY_PRIMITIVES_BIT = 0x00000002, 319 /** Vertex shader invocations bit */ 320 CORE_QUERY_PIPELINE_STATISTIC_VERTEX_SHADER_INVOCATIONS_BIT = 0x00000004, 321 /* Geometry shader invocations bit */ 322 CORE_QUERY_PIPELINE_STATISTIC_GEOMETRY_SHADER_INVOCATIONS_BIT = 0x00000008, 323 /* Geometry shader primitives bit */ 324 CORE_QUERY_PIPELINE_STATISTIC_GEOMETRY_SHADER_PRIMITIVES_BIT = 0x00000010, 325 /** Clipping invocations bit */ 326 CORE_QUERY_PIPELINE_STATISTIC_CLIPPING_INVOCATIONS_BIT = 0x00000020, 327 /** Clipping primitives bit */ 328 CORE_QUERY_PIPELINE_STATISTIC_CLIPPING_PRIMITIVES_BIT = 0x00000040, 329 /** Fragment shader invocations bit */ 330 CORE_QUERY_PIPELINE_STATISTIC_FRAGMENT_SHADER_INVOCATIONS_BIT = 0x00000080, 331 /* Tesselation control shader patches bit */ 332 CORE_QUERY_PIPELINE_STATISTIC_TESSELLATION_CONTROL_SHADER_PATCHES_BIT = 0x00000100, 333 /* Tesselation evaluation shader invocations bit */ 334 CORE_QUERY_PIPELINE_STATISTIC_TESSELLATION_EVALUATION_SHADER_INVOCATIONS_BIT = 0x00000200, 335 /** Compute shader invocations bit */ 336 CORE_QUERY_PIPELINE_STATISTIC_COMPUTE_SHADER_INVOCATIONS_BIT = 0x00000400, 337 /** Max enumeration */ 338 CORE_QUERY_PIPELINE_STATISTIC_FLAG_BITS_MAX_ENUM = 0x7FFFFFFF 339 }; 340 /** Query pipeline statistic flags */ 341 using QueryPipelineStatisticFlags = uint32_t; 342 343 /** Query type */ 344 enum QueryType { 345 /** Timestamp */ 346 CORE_QUERY_TYPE_TIMESTAMP = 2, 347 /** Max enumeration */ 348 CORE_QUERY_TYPE_MAX_ENUM = 0x7FFFFFFF 349 }; 350 351 /** Vertex input rate */ 352 enum VertexInputRate { 353 /** Vertex */ 354 CORE_VERTEX_INPUT_RATE_VERTEX = 0, 355 /** Instance */ 356 CORE_VERTEX_INPUT_RATE_INSTANCE = 1, 357 /** Max enumeration */ 358 CORE_VERTEX_INPUT_RATE_MAX_ENUM = 0x7FFFFFFF 359 }; 360 361 /** Polygon mode */ 362 enum PolygonMode { 363 /** Fill */ 364 CORE_POLYGON_MODE_FILL = 0, 365 /** Line */ 366 CORE_POLYGON_MODE_LINE = 1, 367 /** Point */ 368 CORE_POLYGON_MODE_POINT = 2, 369 /** Max enumeration */ 370 CORE_POLYGON_MODE_MAX_ENUM = 0x7FFFFFFF 371 }; 372 373 /** Cull mode flag bits */ 374 enum CullModeFlagBits { 375 /** None */ 376 CORE_CULL_MODE_NONE = 0, 377 /** Front bit */ 378 CORE_CULL_MODE_FRONT_BIT = 0x00000001, 379 /** Back bit */ 380 CORE_CULL_MODE_BACK_BIT = 0x00000002, 381 /** Front and back bit */ 382 CORE_CULL_MODE_FRONT_AND_BACK = 0x00000003, 383 /** Max enumeration */ 384 CORE_CULL_MODE_FLAG_BITS_MAX_ENUM = 0x7FFFFFFF 385 }; 386 /** Cull mode flags */ 387 using CullModeFlags = uint32_t; 388 389 /** Front face */ 390 enum FrontFace { 391 /** Counter clockwise */ 392 CORE_FRONT_FACE_COUNTER_CLOCKWISE = 0, 393 /** Clockwise */ 394 CORE_FRONT_FACE_CLOCKWISE = 1, 395 /** Max enumeration */ 396 CORE_FRONT_FACE_MAX_ENUM = 0x7FFFFFFF 397 }; 398 399 /** Stencil face flag bits */ 400 enum StencilFaceFlagBits { 401 /** Face front bit */ 402 CORE_STENCIL_FACE_FRONT_BIT = 0x00000001, 403 /** Face back bit */ 404 CORE_STENCIL_FACE_BACK_BIT = 0x00000002, 405 /** Front and back */ 406 CORE_STENCIL_FRONT_AND_BACK = 0x00000003, 407 }; 408 /** Lume stencil face flags */ 409 using StencilFaceFlags = uint32_t; 410 411 /** Compare op */ 412 enum CompareOp { 413 /** Never */ 414 CORE_COMPARE_OP_NEVER = 0, 415 /** Less */ 416 CORE_COMPARE_OP_LESS = 1, 417 /** Equal */ 418 CORE_COMPARE_OP_EQUAL = 2, 419 /** Less or equal */ 420 CORE_COMPARE_OP_LESS_OR_EQUAL = 3, 421 /** Greater */ 422 CORE_COMPARE_OP_GREATER = 4, 423 /** Not equal */ 424 CORE_COMPARE_OP_NOT_EQUAL = 5, 425 /** Greater or equal */ 426 CORE_COMPARE_OP_GREATER_OR_EQUAL = 6, 427 /** Always */ 428 CORE_COMPARE_OP_ALWAYS = 7, 429 /** Max enumeration */ 430 CORE_COMPARE_OP_MAX_ENUM = 0x7FFFFFFF 431 }; 432 433 /** Stencil op */ 434 enum StencilOp { 435 /** Keep */ 436 CORE_STENCIL_OP_KEEP = 0, 437 /** Zero */ 438 CORE_STENCIL_OP_ZERO = 1, 439 /** Replace */ 440 CORE_STENCIL_OP_REPLACE = 2, 441 /** Increment and clamp */ 442 CORE_STENCIL_OP_INCREMENT_AND_CLAMP = 3, 443 /** Decrement and clamp */ 444 CORE_STENCIL_OP_DECREMENT_AND_CLAMP = 4, 445 /** Invert */ 446 CORE_STENCIL_OP_INVERT = 5, 447 /** Increment and wrap */ 448 CORE_STENCIL_OP_INCREMENT_AND_WRAP = 6, 449 /** Decrement and wrap */ 450 CORE_STENCIL_OP_DECREMENT_AND_WRAP = 7, 451 /** Max enumeration */ 452 CORE_STENCIL_OP_MAX_ENUM = 0x7FFFFFFF 453 }; 454 455 /** Primitive topology */ 456 enum PrimitiveTopology { 457 /** Point list */ 458 CORE_PRIMITIVE_TOPOLOGY_POINT_LIST = 0, 459 /** Line list */ 460 CORE_PRIMITIVE_TOPOLOGY_LINE_LIST = 1, 461 /** Line strip */ 462 CORE_PRIMITIVE_TOPOLOGY_LINE_STRIP = 2, 463 /** Triangle list */ 464 CORE_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST = 3, 465 /** Triangle strip */ 466 CORE_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP = 4, 467 /** Triangle fan */ 468 CORE_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN = 5, 469 /** Line list with adjacency */ 470 CORE_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY = 6, 471 /** Line strip with adjacency */ 472 CORE_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY = 7, 473 /** Triangle list with adjacency */ 474 CORE_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY = 8, 475 /** Triangle strip with adjacency */ 476 CORE_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY = 9, 477 /** Patch list */ 478 CORE_PRIMITIVE_TOPOLOGY_PATCH_LIST = 10, 479 /** Max enumeration */ 480 CORE_PRIMITIVE_TOPOLOGY_MAX_ENUM = 0x7FFFFFFF 481 }; 482 483 /** Blend factor */ 484 enum BlendFactor { 485 /** Zero */ 486 CORE_BLEND_FACTOR_ZERO = 0, 487 /** One */ 488 CORE_BLEND_FACTOR_ONE = 1, 489 /** Source color */ 490 CORE_BLEND_FACTOR_SRC_COLOR = 2, 491 /** One minus source color */ 492 CORE_BLEND_FACTOR_ONE_MINUS_SRC_COLOR = 3, 493 /** Destination color */ 494 CORE_BLEND_FACTOR_DST_COLOR = 4, 495 /** One minus destination color */ 496 CORE_BLEND_FACTOR_ONE_MINUS_DST_COLOR = 5, 497 /** Source alpha */ 498 CORE_BLEND_FACTOR_SRC_ALPHA = 6, 499 /** One minus source alpha */ 500 CORE_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA = 7, 501 /** Destination alpha */ 502 CORE_BLEND_FACTOR_DST_ALPHA = 8, 503 /** One minus destination alpha */ 504 CORE_BLEND_FACTOR_ONE_MINUS_DST_ALPHA = 9, 505 /** Constant color */ 506 CORE_BLEND_FACTOR_CONSTANT_COLOR = 10, 507 /** One minus constant color */ 508 CORE_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR = 11, 509 /** Constant alpha */ 510 CORE_BLEND_FACTOR_CONSTANT_ALPHA = 12, 511 /** One minus constant alpha */ 512 CORE_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA = 13, 513 /** Source alpha saturate */ 514 CORE_BLEND_FACTOR_SRC_ALPHA_SATURATE = 14, 515 /** Source one color */ 516 CORE_BLEND_FACTOR_SRC1_COLOR = 15, 517 /** One minus source one color */ 518 CORE_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR = 16, 519 /** Source one alpha */ 520 CORE_BLEND_FACTOR_SRC1_ALPHA = 17, 521 /** One minus source one alpha */ 522 CORE_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA = 18, 523 /** Max enumeration */ 524 CORE_BLEND_FACTOR_MAX_ENUM = 0x7FFFFFFF 525 }; 526 527 /** Blend op */ 528 enum BlendOp { 529 /** Add */ 530 CORE_BLEND_OP_ADD = 0, 531 /** Subtract */ 532 CORE_BLEND_OP_SUBTRACT = 1, 533 /** Reverse subtract */ 534 CORE_BLEND_OP_REVERSE_SUBTRACT = 2, 535 /** Min */ 536 CORE_BLEND_OP_MIN = 3, 537 /** Max */ 538 CORE_BLEND_OP_MAX = 4, 539 /** Max enumeration */ 540 CORE_BLEND_OP_MAX_ENUM = 0x7FFFFFFF 541 }; 542 543 /** Color component flag bits */ 544 enum ColorComponentFlagBits { 545 /** Red bit */ 546 CORE_COLOR_COMPONENT_R_BIT = 0x00000001, 547 /** Green bit */ 548 CORE_COLOR_COMPONENT_G_BIT = 0x00000002, 549 /** Blue bit */ 550 CORE_COLOR_COMPONENT_B_BIT = 0x00000004, 551 /** Alpha bit */ 552 CORE_COLOR_COMPONENT_A_BIT = 0x00000008, 553 /** Max enumeration */ 554 CORE_COLOR_COMPONENT_FLAG_BITS_MAX_ENUM = 0x7FFFFFFF 555 }; 556 /** Color component flags */ 557 using ColorComponentFlags = uint32_t; 558 559 /** Logic op */ 560 enum LogicOp { 561 /** Clear */ 562 CORE_LOGIC_OP_CLEAR = 0, 563 /** And */ 564 CORE_LOGIC_OP_AND = 1, 565 /** And reverse */ 566 CORE_LOGIC_OP_AND_REVERSE = 2, 567 /** Copy */ 568 CORE_LOGIC_OP_COPY = 3, 569 /** And inverted */ 570 CORE_LOGIC_OP_AND_INVERTED = 4, 571 /** No op */ 572 CORE_LOGIC_OP_NO_OP = 5, 573 /** Xor */ 574 CORE_LOGIC_OP_XOR = 6, 575 /** Or */ 576 CORE_LOGIC_OP_OR = 7, 577 /** Nor */ 578 CORE_LOGIC_OP_NOR = 8, 579 /** Equivalent */ 580 CORE_LOGIC_OP_EQUIVALENT = 9, 581 /** Invert */ 582 CORE_LOGIC_OP_INVERT = 10, 583 /** Or reverse */ 584 CORE_LOGIC_OP_OR_REVERSE = 11, 585 /** Copy inverted */ 586 CORE_LOGIC_OP_COPY_INVERTED = 12, 587 /** Or inverted */ 588 CORE_LOGIC_OP_OR_INVERTED = 13, 589 /** Nand */ 590 CORE_LOGIC_OP_NAND = 14, 591 /** Set */ 592 CORE_LOGIC_OP_SET = 15, 593 /** Max enumeration */ 594 CORE_LOGIC_OP_MAX_ENUM = 0x7FFFFFFF 595 }; 596 597 /** Attachment load op */ 598 enum AttachmentLoadOp { 599 /** Load */ 600 CORE_ATTACHMENT_LOAD_OP_LOAD = 0, 601 /** Clear */ 602 CORE_ATTACHMENT_LOAD_OP_CLEAR = 1, 603 /** Dont care */ 604 CORE_ATTACHMENT_LOAD_OP_DONT_CARE = 2, 605 }; 606 607 /** Attachment store op */ 608 enum AttachmentStoreOp { 609 /** Store */ 610 CORE_ATTACHMENT_STORE_OP_STORE = 0, 611 /** Dont care */ 612 CORE_ATTACHMENT_STORE_OP_DONT_CARE = 1, 613 }; 614 615 /** Clear color value */ 616 union ClearColorValue { 617 ClearColorValue() = default; 618 ~ClearColorValue() = default; ClearColorValue(float r,float g,float b,float a)619 constexpr ClearColorValue(float r, float g, float b, float a) : float32 { r, g, b, a } {}; ClearColorValue(int32_t r,int32_t g,int32_t b,int32_t a)620 constexpr ClearColorValue(int32_t r, int32_t g, int32_t b, int32_t a) : int32 { r, g, b, a } {}; ClearColorValue(uint32_t r,uint32_t g,uint32_t b,uint32_t a)621 constexpr ClearColorValue(uint32_t r, uint32_t g, uint32_t b, uint32_t a) : uint32 { r, g, b, a } {}; 622 /** Float32 array of 4 */ 623 float float32[4]; 624 /** int32 array of 4 */ 625 int32_t int32[4]; 626 /** uint32 array of 4 */ 627 uint32_t uint32[4]; 628 }; 629 630 /** Clear depth stencil value */ 631 struct ClearDepthStencilValue { 632 /** Depth, default value 1.0f */ 633 float depth; 634 /** Stencil */ 635 uint32_t stencil; 636 }; 637 638 /** Clear value */ 639 union ClearValue { 640 ClearValue() = default; 641 ~ClearValue() = default; ClearValue(const ClearColorValue & color)642 constexpr explicit ClearValue(const ClearColorValue& color) : color { color } {}; ClearValue(const ClearDepthStencilValue & depthStencil)643 constexpr explicit ClearValue(const ClearDepthStencilValue& depthStencil) : depthStencil { depthStencil } {}; ClearValue(float r,float g,float b,float a)644 constexpr ClearValue(float r, float g, float b, float a) : color { r, g, b, a } {}; ClearValue(int32_t r,int32_t g,int32_t b,int32_t a)645 constexpr ClearValue(int32_t r, int32_t g, int32_t b, int32_t a) : color { r, g, b, a } {}; ClearValue(uint32_t r,uint32_t g,uint32_t b,uint32_t a)646 constexpr ClearValue(uint32_t r, uint32_t g, uint32_t b, uint32_t a) : color { r, g, b, a } {}; ClearValue(float depth,uint32_t stencil)647 constexpr ClearValue(float depth, uint32_t stencil) : depthStencil { depth, stencil } {}; 648 649 /** Color */ 650 ClearColorValue color; 651 /** Depth stencil */ 652 ClearDepthStencilValue depthStencil; 653 }; 654 655 /** Dynamic state flag bits */ 656 enum DynamicStateFlagBits { 657 /** Undefined */ 658 CORE_DYNAMIC_STATE_UNDEFINED = 0, 659 /** Viewport */ 660 CORE_DYNAMIC_STATE_VIEWPORT = (1 << 0), 661 /** Scissor */ 662 CORE_DYNAMIC_STATE_SCISSOR = (1 << 1), 663 /** Line width */ 664 CORE_DYNAMIC_STATE_LINE_WIDTH = (1 << 2), 665 /** Depth bias */ 666 CORE_DYNAMIC_STATE_DEPTH_BIAS = (1 << 3), 667 /** Blend constants */ 668 CORE_DYNAMIC_STATE_BLEND_CONSTANTS = (1 << 4), 669 /** Depth bounds */ 670 CORE_DYNAMIC_STATE_DEPTH_BOUNDS = (1 << 5), 671 /** Stencil compare mask */ 672 CORE_DYNAMIC_STATE_STENCIL_COMPARE_MASK = (1 << 6), 673 /** Stencil write mask */ 674 CORE_DYNAMIC_STATE_STENCIL_WRITE_MASK = (1 << 7), 675 /** Stencil reference */ 676 CORE_DYNAMIC_STATE_STENCIL_REFERENCE = (1 << 8), 677 }; 678 /** Dynamic state flags */ 679 using DynamicStateFlags = uint32_t; 680 681 /** Resolve mode flag bits */ 682 enum ResolveModeFlagBits { 683 /** None. No resolve mode done */ 684 CORE_RESOLVE_MODE_NONE = 0, 685 /** Resolve value is same as sample zero */ 686 CORE_RESOLVE_MODE_SAMPLE_ZERO_BIT = 0x00000001, 687 /** Resolve value is same as average of all samples */ 688 CORE_RESOLVE_MODE_AVERAGE_BIT = 0x00000002, 689 /** Resolve value is same as min of all samples */ 690 CORE_RESOLVE_MODE_MIN_BIT = 0x00000004, 691 /** Resolve value is same as max of all samples */ 692 CORE_RESOLVE_MODE_MAX_BIT = 0x00000008, 693 }; 694 /** Resolve mode flags */ 695 using ResolveModeFlags = uint32_t; 696 697 /** SubpassContents Specifies how commands in the first subpass are provided 698 * CORE_SUBPASS_CONTENTS_INLINE == subpasses are recorded to the same render command list 699 * CORE_SUBPASS_CONTENTS_SECONDARY_COMMAND_LISTS == subpasses are recorded to secondary command lists 700 */ 701 enum SubpassContents { 702 /** Inline */ 703 CORE_SUBPASS_CONTENTS_INLINE = 0, 704 /* Secondary command lists (Not yet supported) */ 705 // CORE_SUBPASS_CONTENTS_SECONDARY_COMMAND_LISTS = 1, 706 }; 707 708 /** Pipeline state constants */ 709 struct PipelineStateConstants { 710 /** GPU buffer whole size */ 711 static constexpr uint32_t GPU_BUFFER_WHOLE_SIZE { ~0u }; 712 /** GPU image all mip levels */ 713 static constexpr uint32_t GPU_IMAGE_ALL_MIP_LEVELS { ~0u }; 714 /** GPU image all layers */ 715 static constexpr uint32_t GPU_IMAGE_ALL_LAYERS { ~0u }; 716 /** Max vertex buffer count */ 717 static constexpr uint32_t MAX_VERTEX_BUFFER_COUNT { 8 }; 718 719 /** Max input attachment count */ 720 static constexpr uint32_t MAX_INPUT_ATTACHMENT_COUNT { 8 }; 721 /** Max color attachment count */ 722 static constexpr uint32_t MAX_COLOR_ATTACHMENT_COUNT { 8 }; 723 /** Max resolve attachment count */ 724 static constexpr uint32_t MAX_RESOLVE_ATTACHMENT_COUNT { 4 }; 725 /** Max render pass attachment count */ 726 static constexpr uint32_t MAX_RENDER_PASS_ATTACHMENT_COUNT { 8 }; 727 /** Max render node gpu wait signals */ 728 static constexpr uint32_t MAX_RENDER_NODE_GPU_WAIT_SIGNALS { 4 }; 729 }; 730 731 /** Viewport descriptor 732 * x and y are upper left corner (x,y) */ 733 struct ViewportDesc { 734 /** X point */ 735 float x { 0.0f }; 736 /** Y point */ 737 float y { 0.0f }; 738 /** Width */ 739 float width { 0.0f }; 740 /** Height */ 741 float height { 0.0f }; 742 743 /** Min depth (0.0f - 1.0f) */ 744 float minDepth { 0.0f }; 745 /** Max depth (0.0f - 1.0f) */ 746 float maxDepth { 1.0f }; 747 }; 748 749 /** Scissor descriptor */ 750 struct ScissorDesc { 751 /** X offset */ 752 int32_t offsetX { 0 }; 753 /** Y offset */ 754 int32_t offsetY { 0 }; 755 /** Extent width */ 756 uint32_t extentWidth { 0 }; 757 /** Extent height */ 758 uint32_t extentHeight { 0 }; 759 }; 760 761 /** Size 3D */ 762 struct Size3D { 763 /** Width */ 764 uint32_t width { 0 }; 765 /** Height */ 766 uint32_t height { 0 }; 767 /** Depth */ 768 uint32_t depth { 0 }; 769 }; 770 771 /** Offset 3D */ 772 struct Offset3D { 773 /** X offset */ 774 int32_t x { 0 }; 775 /** Y offset */ 776 int32_t y { 0 }; 777 /** Z offset */ 778 int32_t z { 0 }; 779 }; 780 781 /** Image subresource layers */ 782 struct ImageSubresourceLayers { 783 /** Image aspect flags */ 784 ImageAspectFlags imageAspectFlags { 0 }; 785 /** Mip level */ 786 uint32_t mipLevel { 0 }; 787 /** Base array layer */ 788 uint32_t baseArrayLayer { 0 }; 789 /** Layer count */ 790 uint32_t layerCount { PipelineStateConstants::GPU_IMAGE_ALL_LAYERS }; 791 }; 792 793 /** Image subresource range */ 794 struct ImageSubresourceRange { 795 /** Image aspect flags */ 796 ImageAspectFlags imageAspectFlags { 0 }; 797 /** Base mip level */ 798 uint32_t baseMipLevel { 0 }; 799 /** Level count */ 800 uint32_t levelCount { PipelineStateConstants::GPU_IMAGE_ALL_MIP_LEVELS }; 801 /** Base array layer */ 802 uint32_t baseArrayLayer { 0 }; 803 /** Layer count */ 804 uint32_t layerCount { PipelineStateConstants::GPU_IMAGE_ALL_LAYERS }; 805 }; 806 807 /** Image blit */ 808 struct ImageBlit { 809 /** Source subresource */ 810 ImageSubresourceLayers srcSubresource; 811 /** Source offsets (top left and bottom right coordinates) */ 812 Size3D srcOffsets[2u]; 813 /** Destination subresource */ 814 ImageSubresourceLayers dstSubresource; 815 /** Destination offsets (top left and bottom right coordinates) */ 816 Size3D dstOffsets[2u]; 817 }; 818 819 /** Memory barrier with pipeline stages */ 820 struct GeneralBarrier { 821 /** Access flags */ 822 AccessFlags accessFlags { 0 }; 823 /** Pipeline stage flags */ 824 PipelineStageFlags pipelineStageFlags { 0 }; 825 }; 826 827 /** Buffer resource barrier */ 828 struct BufferResourceBarrier { 829 /** Access flags */ 830 AccessFlags accessFlags { 0 }; 831 /** Pipeline stage flags */ 832 PipelineStageFlags pipelineStageFlags { 0 }; 833 }; 834 835 /** Image resource barrier */ 836 struct ImageResourceBarrier { 837 /** Access flags */ 838 AccessFlags accessFlags { 0 }; 839 /** Pipeline stage flags */ 840 PipelineStageFlags pipelineStageFlags { 0 }; 841 /** Image layout */ 842 ImageLayout imageLayout { ImageLayout::CORE_IMAGE_LAYOUT_UNDEFINED }; 843 }; 844 845 /** Buffer copy */ 846 struct BufferCopy { 847 /** Offset to source buffer */ 848 uint32_t srcOffset { 0 }; 849 /** Offset to destination buffer */ 850 uint32_t dstOffset { 0 }; 851 /** Size of copy */ 852 uint32_t size { 0 }; 853 }; 854 855 /** Buffer image copy */ 856 struct BufferImageCopy { 857 /** Buffer offset */ 858 uint32_t bufferOffset { 0 }; 859 /** Buffer row length */ 860 uint32_t bufferRowLength { 0 }; 861 /** Buffer image height */ 862 uint32_t bufferImageHeight { 0 }; 863 /** Image subresource */ 864 ImageSubresourceLayers imageSubresource; 865 /** Image offset */ 866 Size3D imageOffset; 867 /** Image extent */ 868 Size3D imageExtent; 869 }; 870 871 /** Image copy */ 872 struct ImageCopy { 873 /** Src image subresource */ 874 ImageSubresourceLayers srcSubresource; 875 /** Src offset */ 876 Offset3D srcOffset; 877 /** Dst image subresource */ 878 ImageSubresourceLayers dstSubresource; 879 /** Dst offset */ 880 Offset3D dstOffset; 881 /** Texel size of copy */ 882 Size3D extent; 883 }; 884 885 /** GPU resource state in pipeline */ 886 struct GpuResourceState { 887 /** Shader stage flags */ 888 ShaderStageFlags shaderStageFlags { 0 }; 889 890 /** Access flags */ 891 AccessFlags accessFlags { 0 }; 892 /** Pipeline stage flags */ 893 PipelineStageFlags pipelineStageFlags { 0 }; 894 895 /** GPU queue */ 896 GpuQueue gpuQueue {}; 897 }; 898 899 /** Render pass descriptor */ 900 struct RenderPassDesc { 901 /** Render area */ 902 struct RenderArea { 903 /** X offset */ 904 int32_t offsetX { 0 }; 905 /** Y offset */ 906 int32_t offsetY { 0 }; 907 /** Extent width */ 908 uint32_t extentWidth { 0 }; 909 /** Extent height */ 910 uint32_t extentHeight { 0 }; 911 }; 912 913 /** Attachment descriptor */ 914 struct AttachmentDesc { 915 /** Layer for layered image */ 916 uint32_t layer { 0u }; 917 /** Mip level to target on mipped image */ 918 uint32_t mipLevel { 0u }; 919 920 // following values are not needed in render pass compatibility 921 /** Load operation */ 922 AttachmentLoadOp loadOp { AttachmentLoadOp::CORE_ATTACHMENT_LOAD_OP_DONT_CARE }; 923 /** Store operation */ 924 AttachmentStoreOp storeOp { AttachmentStoreOp::CORE_ATTACHMENT_STORE_OP_DONT_CARE }; 925 926 /** Stencil load operation */ 927 AttachmentLoadOp stencilLoadOp { AttachmentLoadOp::CORE_ATTACHMENT_LOAD_OP_DONT_CARE }; 928 /** Stencil store operation */ 929 AttachmentStoreOp stencilStoreOp { AttachmentStoreOp::CORE_ATTACHMENT_STORE_OP_DONT_CARE }; 930 931 /** Clear value (union ClearColorValue or ClearDepthStencilValue) */ 932 ClearValue clearValue {}; 933 }; 934 935 /** Attachment count */ 936 uint32_t attachmentCount { 0 }; 937 938 /** Attachment handles */ 939 RenderHandle attachmentHandles[PipelineStateConstants::MAX_RENDER_PASS_ATTACHMENT_COUNT]; 940 /** Attachments */ 941 AttachmentDesc attachments[PipelineStateConstants::MAX_RENDER_PASS_ATTACHMENT_COUNT]; 942 943 /** Render area */ 944 RenderArea renderArea; 945 946 /** Subpass count */ 947 uint32_t subpassCount { 0 }; 948 /** Subpass contents */ 949 SubpassContents subpassContents { SubpassContents::CORE_SUBPASS_CONTENTS_INLINE }; 950 }; 951 952 /** Render pass subpass descriptor */ 953 struct RenderPassSubpassDesc { 954 // indices to render pass attachments 955 /** Depth attachment index */ 956 uint32_t depthAttachmentIndex { ~0u }; 957 /** Depth resolve attachment index */ 958 uint32_t depthResolveAttachmentIndex { ~0u }; 959 /** Input attachment indices */ 960 uint32_t inputAttachmentIndices[PipelineStateConstants::MAX_INPUT_ATTACHMENT_COUNT] {}; 961 /** Color attachment indices */ 962 uint32_t colorAttachmentIndices[PipelineStateConstants::MAX_COLOR_ATTACHMENT_COUNT] {}; 963 /** Resolve attachment indices */ 964 uint32_t resolveAttachmentIndices[PipelineStateConstants::MAX_RESOLVE_ATTACHMENT_COUNT] {}; 965 966 // attachment counts in this subpass 967 /** Depth attachment count in this subpass */ 968 uint32_t depthAttachmentCount { 0 }; 969 /** Depth resolve attachment count in this subpass */ 970 uint32_t depthResolveAttachmentCount { 0 }; 971 /** Input attachment count in this subpass */ 972 uint32_t inputAttachmentCount { 0 }; 973 /** Color attachment count in this subpass */ 974 uint32_t colorAttachmentCount { 0 }; 975 /** Resolve attachment count in this subpass */ 976 uint32_t resolveAttachmentCount { 0 }; 977 978 /** Depth resolve mode flag bit */ 979 ResolveModeFlagBits depthResolveModeFlagBit { ResolveModeFlagBits::CORE_RESOLVE_MODE_NONE }; 980 /** Stencil resolve mode flag bit */ 981 ResolveModeFlagBits stencilResolveModeFlagBit { ResolveModeFlagBits::CORE_RESOLVE_MODE_NONE }; 982 }; 983 984 /** Render pass */ 985 struct RenderPass { 986 /** Render pass descriptor */ 987 RenderPassDesc renderPassDesc; 988 /** Subpass start index */ 989 uint32_t subpassStartIndex { 0 }; 990 /** Subpass descriptor */ 991 RenderPassSubpassDesc subpassDesc; 992 }; 993 994 /** Graphics state */ 995 struct GraphicsState { 996 /** Stencil operation state */ 997 struct StencilOpState { 998 /** Fail operation */ 999 StencilOp failOp { StencilOp::CORE_STENCIL_OP_KEEP }; 1000 /** Pass operation */ 1001 StencilOp passOp { StencilOp::CORE_STENCIL_OP_KEEP }; 1002 /** Depth fail operation */ 1003 StencilOp depthFailOp { StencilOp::CORE_STENCIL_OP_KEEP }; 1004 /** Compare operation */ 1005 CompareOp compareOp { CompareOp::CORE_COMPARE_OP_NEVER }; 1006 /** Compare mask */ 1007 uint32_t compareMask { 0 }; 1008 /** Write mask */ 1009 uint32_t writeMask { 0 }; 1010 /** Reference */ 1011 uint32_t reference { 0 }; 1012 }; 1013 1014 /** Rasterization state */ 1015 struct RasterizationState { 1016 /** Enable depth clamp */ 1017 bool enableDepthClamp { false }; 1018 /** Enable depth bias */ 1019 bool enableDepthBias { false }; 1020 /** Enable rasterizer discard */ 1021 bool enableRasterizerDiscard { false }; 1022 1023 /** Polygon mode */ 1024 PolygonMode polygonMode { PolygonMode::CORE_POLYGON_MODE_FILL }; 1025 /** Cull mode flags */ 1026 CullModeFlags cullModeFlags { CullModeFlagBits::CORE_CULL_MODE_NONE }; 1027 /** Front face */ 1028 FrontFace frontFace { FrontFace::CORE_FRONT_FACE_COUNTER_CLOCKWISE }; 1029 1030 /** Depth bias constant factor */ 1031 float depthBiasConstantFactor { 0.0f }; 1032 /** Depth bias clamp */ 1033 float depthBiasClamp { 0.0f }; 1034 /** Depth bias slope factor */ 1035 float depthBiasSlopeFactor { 0.0f }; 1036 1037 /** Line width */ 1038 float lineWidth { 1.0f }; 1039 }; 1040 1041 /** Depth stencil state */ 1042 struct DepthStencilState { 1043 /** Enable depth test */ 1044 bool enableDepthTest { false }; 1045 /** Enable depth write */ 1046 bool enableDepthWrite { false }; 1047 /** Enable depth bounds test */ 1048 bool enableDepthBoundsTest { false }; 1049 /** Enable stencil test */ 1050 bool enableStencilTest { false }; 1051 1052 /** Min depth bounds */ 1053 float minDepthBounds { 0.0f }; 1054 /** Max depth bounds */ 1055 float maxDepthBounds { 1.0f }; 1056 1057 /** Depth compare operation */ 1058 CompareOp depthCompareOp { CompareOp::CORE_COMPARE_OP_NEVER }; 1059 /** Front stencil operation state */ 1060 StencilOpState frontStencilOpState {}; 1061 /** Back stencil operation state */ 1062 StencilOpState backStencilOpState {}; 1063 }; 1064 1065 /** Color blend state */ 1066 struct ColorBlendState { 1067 /** Attachment */ 1068 struct Attachment { 1069 /** Enable blend */ 1070 bool enableBlend { false }; 1071 /** Color write mask */ 1072 ColorComponentFlags colorWriteMask { ColorComponentFlagBits::CORE_COLOR_COMPONENT_R_BIT | 1073 ColorComponentFlagBits::CORE_COLOR_COMPONENT_G_BIT | 1074 ColorComponentFlagBits::CORE_COLOR_COMPONENT_B_BIT | 1075 ColorComponentFlagBits::CORE_COLOR_COMPONENT_A_BIT }; 1076 1077 /** Source color blend factor */ 1078 BlendFactor srcColorBlendFactor { BlendFactor::CORE_BLEND_FACTOR_ONE }; 1079 /** Destination color blend factor */ 1080 BlendFactor dstColorBlendFactor { BlendFactor::CORE_BLEND_FACTOR_ONE }; 1081 /** Color blend operation */ 1082 BlendOp colorBlendOp { BlendOp::CORE_BLEND_OP_ADD }; 1083 1084 /** Source alpha blend factor */ 1085 BlendFactor srcAlphaBlendFactor { BlendFactor::CORE_BLEND_FACTOR_ONE }; 1086 /** Destination alpha blend factor */ 1087 BlendFactor dstAlphaBlendFactor { BlendFactor::CORE_BLEND_FACTOR_ONE }; 1088 /** Alpha blend operation */ 1089 BlendOp alphaBlendOp { BlendOp::CORE_BLEND_OP_ADD }; 1090 }; 1091 1092 /** Enable logic operation */ 1093 bool enableLogicOp { false }; 1094 /** Logic operation */ 1095 LogicOp logicOp { LogicOp::CORE_LOGIC_OP_NO_OP }; 1096 1097 /** Color blend constants (R, G, B, A) */ 1098 float colorBlendConstants[4u] { 0.0f, 0.0f, 0.0f, 0.0f }; 1099 /** Color attachment count */ 1100 uint32_t colorAttachmentCount { 0 }; 1101 /** Color attachments */ 1102 Attachment colorAttachments[PipelineStateConstants::MAX_COLOR_ATTACHMENT_COUNT]; 1103 }; 1104 1105 /** Input assembly */ 1106 struct InputAssembly { 1107 /** Enable primitive restart */ 1108 bool enablePrimitiveRestart { false }; 1109 /** Primitive topology */ 1110 PrimitiveTopology primitiveTopology { PrimitiveTopology::CORE_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST }; 1111 }; 1112 1113 /** Input assembly */ 1114 InputAssembly inputAssembly; 1115 /** Rasterization state */ 1116 RasterizationState rasterizationState; 1117 /** Depth stencil state */ 1118 DepthStencilState depthStencilState; 1119 /** Color blend state */ 1120 ColorBlendState colorBlendState; 1121 /** Dynamic state flags. Prefer using dynamic viewport and dynamic scissor for less graphics pipelines. */ 1122 DynamicStateFlags dynamicStateFlags { DynamicStateFlagBits::CORE_DYNAMIC_STATE_UNDEFINED }; 1123 }; 1124 1125 /** Vertex input declaration */ 1126 struct VertexInputDeclaration { 1127 /** Vertex input binding description */ 1128 struct VertexInputBindingDescription { 1129 /** Binding */ 1130 uint32_t binding { ~0u }; 1131 /** Stride */ 1132 uint32_t stride { 0u }; 1133 /** Vertex input rate */ 1134 VertexInputRate vertexInputRate { VertexInputRate::CORE_VERTEX_INPUT_RATE_MAX_ENUM }; 1135 }; 1136 1137 /** Vertex input attribute description */ 1138 struct VertexInputAttributeDescription { 1139 /** Location */ 1140 uint32_t location { ~0u }; 1141 /** Binding */ 1142 uint32_t binding { ~0u }; 1143 /** Format */ 1144 BASE_NS::Format format { BASE_NS::Format::BASE_FORMAT_UNDEFINED }; 1145 /** Offset */ 1146 uint32_t offset { 0u }; 1147 }; 1148 }; 1149 1150 /** Vertex input declaration data */ 1151 struct VertexInputDeclarationData { 1152 /** Binding description count */ 1153 uint32_t bindingDescriptionCount { 0 }; 1154 /** Attribute description count */ 1155 uint32_t attributeDescriptionCount { 0 }; 1156 1157 /** Array of binding descriptions */ 1158 VertexInputDeclaration::VertexInputBindingDescription 1159 bindingDescriptions[PipelineStateConstants::MAX_VERTEX_BUFFER_COUNT]; 1160 /** Array of attribute descriptions */ 1161 VertexInputDeclaration::VertexInputAttributeDescription 1162 attributeDescriptions[PipelineStateConstants::MAX_VERTEX_BUFFER_COUNT]; 1163 }; 1164 1165 /** Vertex input declaration view */ 1166 struct VertexInputDeclarationView { 1167 /** Array of binding descriptions */ 1168 BASE_NS::array_view<const VertexInputDeclaration::VertexInputBindingDescription> bindingDescriptions; 1169 /** Array of attribute descriptions */ 1170 BASE_NS::array_view<const VertexInputDeclaration::VertexInputAttributeDescription> attributeDescriptions; 1171 }; 1172 1173 /** Shader specialization */ 1174 struct ShaderSpecialization { 1175 /** Constant */ 1176 struct Constant { 1177 enum class Type : uint32_t { 1178 INVALID = 0, 1179 /** 32 bit boolean value */ 1180 BOOL = 1, 1181 /** 32 bit unsigned integer value */ 1182 UINT32 = 2, 1183 /** 32 bit signed integer value */ 1184 INT32 = 3, 1185 /** 32 bit floating-point value */ 1186 FLOAT = 4, 1187 }; 1188 /** Shader stage */ 1189 ShaderStageFlags shaderStage; 1190 /** ID */ 1191 uint32_t id; 1192 /** Type */ 1193 Type type; 1194 /** Offset */ 1195 uint32_t offset; 1196 }; 1197 }; 1198 1199 /** Shader specialization constant view */ 1200 struct ShaderSpecilizationConstantView { 1201 /** Array of shader specialization constants */ 1202 BASE_NS::array_view<const ShaderSpecialization::Constant> constants; 1203 }; 1204 1205 /** Shader specialization constant data view */ 1206 struct ShaderSpecializationConstantDataView { 1207 /** Array of shader specialization constants */ 1208 BASE_NS::array_view<const ShaderSpecialization::Constant> constants; 1209 /** Data */ 1210 BASE_NS::array_view<const uint32_t> data; 1211 }; 1212 1213 /** Buffer offset */ 1214 struct BufferOffset { 1215 /** Buffer handle */ 1216 RenderHandle handle; 1217 /** Buffer offset in bytes */ 1218 uint32_t offset { 0 }; 1219 }; 1220 1221 /** Accleration structure types */ 1222 enum AccelerationStructureType : uint32_t { 1223 /** Acceleration structure type top level */ 1224 CORE_ACCELERATION_STRUCTURE_TYPE_TOP_LEVEL = 0, 1225 /** Acceleration structure type bottom level */ 1226 CORE_ACCELERATION_STRUCTURE_TYPE_BOTTOM_LEVEL = 1, 1227 /** Acceleration structure type generic */ 1228 CORE_ACCELERATION_STRUCTURE_TYPE_GENERIC = 2, 1229 }; 1230 1231 struct AccelerationStructureBuildRangeInfo { 1232 uint32_t primitiveCount { 0u }; 1233 uint32_t primitiveOffset { 0u }; 1234 uint32_t firstVertex { 0u }; 1235 uint32_t transformOffset { 0u }; 1236 }; 1237 1238 /** Additional parameters for geometry */ 1239 enum GeometryFlagBits : uint32_t { 1240 /** The geometry does not invoke the any-hit shaders even if present in a hit group */ 1241 GEOMETRY_OPAQUE_BIT = 0x00000001, 1242 /** Indicates that the implementation must only call the any-hit shader a single time for each primitive 1243 * in this geometry. 1244 */ 1245 GEOMETRY_NO_DUPLICATE_ANY_HIT_INVOCATION_BIT = 0x00000002, 1246 }; 1247 /** Geometry flags */ 1248 using GeometryFlags = uint32_t; 1249 1250 /** Acceleratoin structure geometry triangles data */ 1251 struct AccelerationStructureGeometryTrianglesInfo { 1252 /** Vertex format */ 1253 BASE_NS::Format vertexFormat { BASE_NS::Format::BASE_FORMAT_UNDEFINED }; 1254 /** Vertex stride, bytes between each vertex */ 1255 uint32_t vertexStride { 0u }; 1256 /** Highest index of a vertex for building geom */ 1257 uint32_t maxVertex { 0u }; 1258 /** Index type */ 1259 IndexType indexType { IndexType::CORE_INDEX_TYPE_MAX_ENUM }; 1260 /** Index count */ 1261 uint32_t indexCount { 0u }; 1262 1263 /** Geometry flags */ 1264 GeometryFlags geometryFlags { 0u }; 1265 }; 1266 1267 /** Acceleratoin structure geometry triangles data */ 1268 struct AccelerationStructureGeometryTrianglesData { 1269 /** Triangles info */ 1270 AccelerationStructureGeometryTrianglesInfo info; 1271 1272 /** Vertex buffer with offset */ 1273 BufferOffset vertexData; 1274 /** Index buffer with offset */ 1275 BufferOffset indexData; 1276 /** Transform buffer (4x3 matrices), additional */ 1277 BufferOffset transformData; 1278 }; 1279 1280 /** Acceleration structure geometry AABBs info */ 1281 struct AccelerationStructureGeometryAabbsInfo { 1282 /** Stride, bytes between each AABB (must be a multiple of 8) */ 1283 uint32_t stride { 0u }; 1284 }; 1285 1286 /** Acceleration structure geometry AABBs data */ 1287 struct AccelerationStructureGeometryAabbsData { 1288 /** AABBs info */ 1289 AccelerationStructureGeometryAabbsInfo info; 1290 /** Buffer resource and offset for AabbPositions */ 1291 BufferOffset data; 1292 }; 1293 1294 /** Acceleration structure geometry instances info */ 1295 struct AccelerationStructureGeometryInstancesInfo { 1296 /** Specifies whether data is used as an array of addresses or just an array */ 1297 bool arrayOfPointers { false }; 1298 }; 1299 1300 /** Acceleration structure geometry instances data */ 1301 struct AccelerationStructureGeometryInstancesData { 1302 /** Instances info */ 1303 AccelerationStructureGeometryInstancesInfo info; 1304 /** Buffer resource and offset for structures */ 1305 BufferOffset data; 1306 }; 1307 1308 /** Build acceleration structure flag bits */ 1309 enum BuildAccelerationStructureFlagBits : uint32_t { 1310 /** Can be updated */ 1311 CORE_BUILD_ACCELERATION_STRUCTURE_ALLOW_UPDATE_BIT = 0x00000001, 1312 /** Alloc compaction bit. Can be used as a source for compaction. */ 1313 CORE_BUILD_ACCELERATION_STRUCTURE_ALLOW_COMPACTION_BIT = 0x00000002, 1314 /** Prefer fast trace. Prioritizes trace performance for build time. */ 1315 CORE_BUILD_ACCELERATION_STRUCTURE_PREFER_FAST_TRACE_BIT = 0x00000004, 1316 /** Prefer fast build. Prioritizes fast build for trace performance. */ 1317 CORE_BUILD_ACCELERATION_STRUCTURE_PREFER_FAST_BUILD_BIT = 0x00000008, 1318 /** Prefer low memory. Prioritizes the size of the scratch memory and the final acceleration structure, 1319 * potentially at the expense of build time or trace performance */ 1320 CORE_BUILD_ACCELERATION_STRUCTURE_LOW_MEMORY_BIT = 0x00000010, 1321 }; 1322 /** Build acceleration structure flags */ 1323 using BuildAccelerationStructureFlags = uint32_t; 1324 1325 /** Build acceleration structure mode */ 1326 enum BuildAccelerationStructureMode : uint32_t { 1327 /** The destination acceleration structure will be built using the specified geometries */ 1328 CORE_BUILD_ACCELERATION_STRUCTURE_MODE_BUILD = 0, 1329 /** The destination acceleration structure will be built using data in a source acceleration structure, 1330 * updated by the specified geometries. */ 1331 CORE_BUILD_ACCELERATION_STRUCTURE_MODE_UPDATE = 1, 1332 }; 1333 1334 /** Acceleration structure build geometry info */ 1335 struct AccelerationStructureBuildGeometryInfo { 1336 /** Acceleration structure type */ 1337 AccelerationStructureType type { AccelerationStructureType::CORE_ACCELERATION_STRUCTURE_TYPE_TOP_LEVEL }; 1338 /** Additional flags */ 1339 BuildAccelerationStructureFlags flags { 0 }; 1340 /** Build mode */ 1341 BuildAccelerationStructureMode mode { 1342 BuildAccelerationStructureMode::CORE_BUILD_ACCELERATION_STRUCTURE_MODE_BUILD 1343 }; 1344 }; 1345 1346 /** Acceleration structure build geometry data */ 1347 struct AccelerationStructureBuildGeometryData { 1348 /** Geometry info */ 1349 AccelerationStructureBuildGeometryInfo info; 1350 1351 /** Handle to existing acceleration structure which is used a src for dst update. */ 1352 RenderHandle srcAccelerationStructure; 1353 /** Handle to dst acceleration structure which is to be build. */ 1354 RenderHandle dstAccelerationStructure; 1355 /** Handle and offset to build scratch data. */ 1356 BufferOffset scratchBuffer; 1357 }; 1358 1359 /** Acceleration structure build sizes. 1360 * The build sizes can be queried from device with AccelerationStructureBuildGeometryInfo. 1361 */ 1362 struct AccelerationStructureBuildSizes { 1363 /** Acceleration structure size */ 1364 uint32_t accelerationStructureSize { 0u }; 1365 /** Update scratch size */ 1366 uint32_t updateScratchSize { 0u }; 1367 /** Build scratch size */ 1368 uint32_t buildScratchSize { 0u }; 1369 }; 1370 1371 /** Geometry type. 1372 */ 1373 enum GeometryType : uint32_t { 1374 /** Triangles */ 1375 CORE_GEOMETRY_TYPE_TRIANGLES = 0, 1376 /** AABBs */ 1377 CORE_GEOMETRY_TYPE_AABBS = 1, 1378 /** Instances */ 1379 CORE_GEOMETRY_TYPE_INSTANCES = 2, 1380 }; 1381 1382 /** Geometry instance flags. 1383 */ 1384 enum GeometryInstanceFlagBits : uint32_t { 1385 /** Disable face culling */ 1386 CORE_GEOMETRY_INSTANCE_TRIANGLE_FACING_CULL_DISABLE_BIT = 0x00000001, 1387 /** Invert the facing */ 1388 CORE_GEOMETRY_INSTANCE_TRIANGLE_FLIP_FACING_BIT = 0x00000002, 1389 /** Force geometry to be treated as opaque */ 1390 CORE_GEOMETRY_INSTANCE_FORCE_OPAQUE_BIT = 0x00000004, 1391 /** Removes opaque bit from geometry. Can be overriden with SPIR-v OpaqueKHR flag */ 1392 CORE_GEOMETRY_INSTANCE_FORCE_NO_OPAQUE_BIT = 0x00000008, 1393 }; 1394 using GeometryInstanceFlags = uint32_t; 1395 1396 /** Acceleration structure instance info. 1397 */ 1398 struct AccelerationStructureInstanceInfo { 1399 /** Affine transform matrix (4x3 used) */ 1400 // BASE_NS::Math::Mat4X4 transform{}; 1401 float transform[4][4]; 1402 /** User specified index accessable in ray shaders with InstanceCustomIndexKHR (24 bits) */ 1403 uint32_t instanceCustomIndex { 0u }; 1404 /** Mask, a visibility mask for geometry (8 bits). Instance may only be hit if cull mask & instance.mask != 0. */ 1405 uint8_t mask { 0u }; 1406 /** GeometryInstanceFlags for this instance */ 1407 GeometryInstanceFlags flags { 0u }; 1408 }; 1409 1410 /** Acceleration structure instance data. 1411 */ 1412 struct AccelerationStructureInstanceData { 1413 /** Instance info */ 1414 AccelerationStructureInstanceInfo info; 1415 1416 /** Acceleration structure handle */ 1417 RenderHandle accelerationStructureReference; 1418 }; 1419 /** @} */ 1420 RENDER_END_NAMESPACE() 1421 1422 #endif // API_RENDER_DEVICE_PIPELINE_STATE_DESC_H 1423