1 /* 2 * linux-5.4/drivers/media/platform/sunxi-vin/vin-cci/csi_cci_reg_i.h 3 * 4 * Copyright (c) 2007-2017 Allwinnertech Co., Ltd. 5 * 6 * This software is licensed under the terms of the GNU General Public 7 * License version 2, as published by the Free Software Foundation, and 8 * may be copied, distributed, and modified under those terms. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 */ 16 17 18 /* 19 ****************************************************************************** 20 * 21 * csi_cci_reg_i.h 22 * 23 * Hawkview ISP - csi_cci_reg_i.h module 24 * 25 * Copyright (c) 2014 by Allwinnertech Co., Ltd. http://www.allwinnertech.com 26 * 27 * Version Author Date Description 28 * 29 * 2.0 Yang Feng 2014/07/15 Second Version 30 * 31 ****************************************************************************** 32 */ 33 34 #ifndef _CSI_CCI_REG_I_H_ 35 #define _CSI_CCI_REG_I_H_ 36 /* 37 * Detail information of registers 38 */ 39 #define CCI_CTRL_OFF 0x0000 40 41 #define CCI_CTRL_CCI_EN 0 42 #define CCI_CTRL_SOFT_RESET 1 43 #define CCI_CTRL_CCI_STA 16 44 #define CCI_CTRL_TRAN_RESULT 24 45 #define CCI_CTRL_READ_TRAN_MODE 28 46 #define CCI_CTRL_RESTART_MODE 29 47 #define CCI_CTRL_REPEAT_TRAN 30 48 #define CCI_CTRL_SINGLE_TRAN 31 49 50 #define CCI_CFG_OFF 0x0004 51 #define CCI_CFG_CSI_TRIG 0 52 #define CCI_CFG_CSI_TRIG_MASK (0xf << CCI_CFG_CSI_TRIG) 53 #define CCI_CFG_TRIG_MODE 4 54 #define CCI_CFG_TRIG_MODE_MASK (0x7 << CCI_CFG_TRIG_MODE) 55 #define CCI_CFG_SRC_SEL 7 56 #define CCI_CFG_SRC_SEL_MASK (0x1 << CCI_CFG_SRC_SEL) 57 #define CCI_CFG_PACKET_MODE 15 58 #define CCI_CFG_PACKET_MODE_MASK (0x1 << CCI_CFG_PACKET_MODE) 59 #define CCI_CFG_INTERVAL 16 60 #define CCI_CFG_INTERVAL_MASK (0xff << CCI_CFG_INTERVAL) 61 #define CCI_CFG_TIMEOUT_N 24 62 #define CCI_CFG_TIMEOUT_N_MASK (0xff << CCI_CFG_TIMEOUT_N) 63 64 #define CCI_FMT_OFF 0x0008 65 #define CCI_FMT_PACKET_CNT 0 66 #define CCI_FMT_PACKET_CNT_MASK (0xffff << CCI_FMT_PACKET_CNT) 67 #define CCI_FMT_DATA_BYTE 16 68 #define CCI_FMT_DATA_BYTE_MASK (0xf << CCI_FMT_DATA_BYTE) 69 #define CCI_FMT_ADDR_BYTE 20 70 #define CCI_FMT_ADDR_BYTE_MASK (0xf << CCI_FMT_ADDR_BYTE) 71 #define CCI_FMT_CMD 24 72 #define CCI_FMT_CMD_MASK (0x1 << CCI_FMT_CMD) 73 #define CCI_FMT_SLV_ID 25 74 #define CCI_FMT_SLV_ID_MASK (0x7f << CCI_FMT_SLV_ID) 75 76 #define CCI_BUS_CTRL_OFF 0x000C 77 #define CCI_BUS_CTRL_SDA_MOE 0 78 #define CCI_BUS_CTRL_SCL_MOE 1 79 #define CCI_BUS_CTRL_SDA_MOV 2 80 #define CCI_BUS_CTRL_SCL_MOV 3 81 #define CCI_BUS_CTRL_SDA_PEN 4 82 #define CCI_BUS_CTRL_SCL_PEN 5 83 #define CCI_BUS_CTRL_SDA_STA 6 84 #define CCI_BUS_CTRL_SCL_STA 7 85 #define CCI_BUS_CTRL_CLK_M 8 86 #define CCI_BUS_CTRL_CLK_M_MASK (0xF << CCI_BUS_CTRL_CLK_M) 87 #define CCI_BUS_CTRL_CLK_N 12 88 #define CCI_BUS_CTRL_CLK_N_MASK (0x7 << CCI_BUS_CTRL_CLK_N) 89 #define CCI_BUS_CTRL_DLY_TRIG 15 90 #define CCI_BUS_CTRL_DLY_CYC 16 91 #define CCI_BUS_CTRL_DLY_CYC_MASK (0xffff << CCI_BUS_CTRL_DLY_CYC) 92 93 #define CCI_INT_CTRL_OFF 0x0014 94 #define CCI_INT_CTRL_S_TRAN_COM_PD 0 95 #define CCI_INT_CTRL_S_TRAN_ERR_PD 1 96 #define CCI_INT_CTRL_RES0 2 97 #define CCI_INT_CTRL_S_TRAN_COM_INT_EN 16 98 #define CCI_INT_CTRL_S_TRAN_ERR_INT_EN 17 99 #define CCI_INT_CTRL_RES1 18 100 101 #define CCI_LC_TRIG_OFF 0x0018 102 #define CCI_LC_TRIG_LN_CNT 0 103 #define CCI_LC_TRIG_LN_CNT_MASK (0x1fff << CCI_LC_TRIG_LN_CNT) 104 #define CCI_LC_TRIG_RES0 13 105 106 #define CCI_FIFO_ACC_OFF 0x0100 107 #define CCI_FIFO_ACC_DATA_FIFO 0 108 109 #define CCI_RSV_REG_OFF 0x0200 110 111 #endif /*_CSI_CCI_REG_I_H_*/ 112