1 /* 2 * Copyright (c) 2021-2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_MIPI_DSI_H 10 #define HPM_MIPI_DSI_H 11 12 typedef struct { 13 __R uint32_t VERSION; /* 0x0: version */ 14 __RW uint32_t PWR_UP; /* 0x4: power up */ 15 __RW uint32_t CLKMGR_CFG; /* 0x8: divide lanebyteclk for timeout */ 16 __RW uint32_t DPI_VCID; /* 0xC: virtual channel ID for DPI traffic */ 17 __RW uint32_t DPI_COLOR_CODING; /* 0x10: dpi color coding */ 18 __RW uint32_t DPI_CFG_POL; /* 0x14: the polarity of DPI signals */ 19 __RW uint32_t DPI_LP_CMD_TIM; /* 0x18: the timing for low-power commands sent while in video mode */ 20 __R uint8_t RESERVED0[16]; /* 0x1C - 0x2B: Reserved */ 21 __RW uint32_t PCKHDL_CFG; /* 0x2C: configures how EoTp, BTA, CRC and ECC to be used */ 22 __RW uint32_t GEN_VCID; /* 0x30: configures the virtual channel ID of read response to store and return to generic interface */ 23 __RW uint32_t MODE_CFG; /* 0x34: configures the mode of operation between video or command mode */ 24 __RW uint32_t VID_MODE_CFG; /* 0x38: several aspect of video mode operation */ 25 __RW uint32_t VID_PKT_SIZE; /* 0x3C: configures the video packet size */ 26 __RW uint32_t VID_NUM_CHUNKS; /* 0x40: configures the number of chunks to use */ 27 __RW uint32_t VID_NULL_SIZE; /* 0x44: configures the size of null packets */ 28 __RW uint32_t VID_HSA_TIME; /* 0x48: configures the video HAS time */ 29 __RW uint32_t VID_HBP_TIME; /* 0x4C: configure the video HBP time */ 30 __RW uint32_t VID_HLINE_TIME; /* 0x50: configures the overall time for each video line */ 31 __RW uint32_t VID_VSA_LINES; /* 0x54: configures the vsa period */ 32 __RW uint32_t VID_VBP_LINES; /* 0x58: configures the vbp period */ 33 __RW uint32_t VID_VFP_LINES; /* 0x5C: configures the vfp period */ 34 __RW uint32_t VID_VACTIVE_LINES; /* 0x60: configures the vertical resolution of video */ 35 __R uint8_t RESERVED1[4]; /* 0x64 - 0x67: Reserved */ 36 __RW uint32_t CMD_MODE_CFG; /* 0x68: This register configures several aspect of command mode operation, tearing effect, acknowledge for each packet and the speed mode to transmit each Data Type related to commands. */ 37 __RW uint32_t GEN_HDR; /* 0x6C: sets the header for new packets sent using the generic interface */ 38 __RW uint32_t GEN_PLD_DATA; /* 0x70: sets the payload for packets sent using the generic interface */ 39 __R uint32_t CMD_PKT_STATUS; /* 0x74: information about the status of FIFOs related to DBI and Generic interface */ 40 __RW uint32_t TO_CNT_CFG; /* 0x78: configures the trigger timeout errors */ 41 __RW uint32_t HS_RD_TO_CNT; /* 0x7C: configures the peripheral response timeout after high speed read operations */ 42 __RW uint32_t LP_RD_TO_CNT; /* 0x80: configures the peripheral response timeout after low-power read operation */ 43 __RW uint32_t HS_WR_TO_CNT; /* 0x84: configures the peripheral response timeout after high speed write operations */ 44 __RW uint32_t LP_WR_TO_CNT; /* 0x88: configures the peripheral response timeout after low power write operations */ 45 __RW uint32_t BTA_TO_CNT; /* 0x8C: configures the periphera response timeout after bus turnaround */ 46 __RW uint32_t SDF_3D; /* 0x90: sotres 3d control information for vss packets in video mode */ 47 __RW uint32_t LPCLK_CTRL; /* 0x94: configures the possibility for using non continous clock in the clock lane */ 48 __RW uint32_t PHY_TMR_LPCLK_CFG; /* 0x98: sets the time that dsi host assumes in calculations for the clock lane to switch between high-speed and low-power */ 49 __RW uint32_t PHY_TMR_CFG; /* 0x9C: sets the time that dsi host assumes in calculations for data lanes to switch between hs to lp */ 50 __RW uint32_t PHY_RSTZ; /* 0xA0: controls resets and the pll of d-phy */ 51 __RW uint32_t PHY_IF_CFG; /* 0xA4: configures the number of active lanes */ 52 __RW uint32_t PHY_ULPS_CTRL; /* 0xA8: configures entering and leaving ulps */ 53 __RW uint32_t PHY_TX_TRIGGERS; /* 0xAC: configures the pins that activate triggers in the d-phy */ 54 __R uint32_t PHY_STATUS; /* 0xB0: contains information about the status of the d-phy */ 55 __RW uint32_t PHY_TST_CTRL0; /* 0xB4: controls clock and clear pins of the d-phy vendor specific interface */ 56 __RW uint32_t PHY_TST_CTRL1; /* 0xB8: controls data and enable pins of the d-phy */ 57 __R uint32_t INT_ST0; /* 0xBC: controls the status of interrupt */ 58 __R uint32_t INT_ST1; /* 0xC0: the interrupt source related to timeout etc */ 59 __RW uint32_t INT_MSK0; /* 0xC4: configures masks for the sources of interrupt that affec int_st0 */ 60 __RW uint32_t INT_MSK1; /* 0xC8: configures masks for int_st1 */ 61 __RW uint32_t PHY_CAL; /* 0xCC: controls the skew calibration of D-phy */ 62 __R uint8_t RESERVED2[8]; /* 0xD0 - 0xD7: Reserved */ 63 __RW uint32_t INT_FORCE0; /* 0xD8: forces that affect the int_st0 register */ 64 __RW uint32_t INT_FORCE1; /* 0xDC: forces interrupts that affect the int_st1 register */ 65 __R uint8_t RESERVED3[20]; /* 0xE0 - 0xF3: Reserved */ 66 __RW uint32_t PHY_TMR_RD; /* 0xF4: configures times related to PHY to perform some operations in lane byte clock cycle */ 67 __RW uint32_t AUTO_ULPS_MIN_TIME; /* 0xF8: configures the minimum time required by phy between ulpsactivenot and ulpsexitreq for clock and data lane */ 68 __RW uint32_t PHY_MODE; /* 0xFC: select phy mode */ 69 __RW uint32_t VID_SHADOW_CTRL; /* 0x100: controls dpi shadow feature */ 70 __R uint8_t RESERVED4[8]; /* 0x104 - 0x10B: Reserved */ 71 __R uint32_t DPI_VCID_ACT; /* 0x10C: holds the value that controller is using for DPI_VCID */ 72 __R uint32_t DPI_COLOR_CODING_ACT; /* 0x110: holds the value that controller is using for DPI_COLOR_CODING */ 73 __R uint8_t RESERVED5[4]; /* 0x114 - 0x117: Reserved */ 74 __R uint32_t DPI_LP_CMD_TIM_ACT; /* 0x118: holds value that controller is using for dpi_lp_cmd_time */ 75 __R uint8_t RESERVED6[28]; /* 0x11C - 0x137: Reserved */ 76 __R uint32_t VID_MODE_CFG_ACT; /* 0x138: holds value that controller is using for vid_mode_cfg */ 77 __R uint32_t VID_PKT_SIZE_ACT; /* 0x13C: holds value that controller is using for vid_pkt_size */ 78 __R uint32_t VID_NUM_CHUNKS_ACT; /* 0x140: holds value that controller is using for vid_num_chunks */ 79 __R uint32_t VID_NULL_SIZE_ACT; /* 0x144: holds the value that controller is using for vid_null_size */ 80 __R uint32_t VID_HSA_TIME_ACT; /* 0x148: the value of vid_hsa_time */ 81 __R uint32_t VID_HBP_TIME_ACT; /* 0x14C: the value that controller is using for vid_hbp_time */ 82 __R uint32_t VID_HLINE_TIME_ACT; /* 0x150: the value for vid_hline_time */ 83 __R uint32_t VID_VSA_LINES_ACT; /* 0x154: value for vid_vsa_lines */ 84 __R uint32_t VID_VBP_LINES_ACT; /* 0x158: value for vid_vbp_lines */ 85 __R uint32_t VID_VFP_LINES_ACT; /* 0x15C: value for vid_vfp_lines */ 86 __R uint32_t VID_VACTIVE_LINES_ACT; /* 0x160: value for vid_vactive_lines */ 87 __R uint8_t RESERVED7[4]; /* 0x164 - 0x167: Reserved */ 88 __R uint32_t VID_PKT_STATUS; /* 0x168: status of fifo related to dpi */ 89 __R uint8_t RESERVED8[36]; /* 0x16C - 0x18F: Reserved */ 90 __R uint32_t SDF_3D_ACT; /* 0x190: value for sdf_3d */ 91 } MIPI_DSI_Type; 92 93 94 /* Bitfield definition for register: VERSION */ 95 /* 96 * VERSION (RO) 97 * 98 * version of DSI 99 */ 100 #define MIPI_DSI_VERSION_VERSION_MASK (0xFFFFFFFFUL) 101 #define MIPI_DSI_VERSION_VERSION_SHIFT (0U) 102 #define MIPI_DSI_VERSION_VERSION_GET(x) (((uint32_t)(x) & MIPI_DSI_VERSION_VERSION_MASK) >> MIPI_DSI_VERSION_VERSION_SHIFT) 103 104 /* Bitfield definition for register: PWR_UP */ 105 /* 106 * SHUTDOWNZ (RW) 107 * 108 * 0x0: reset the core 109 * 0x1: power up the core 110 */ 111 #define MIPI_DSI_PWR_UP_SHUTDOWNZ_MASK (0x1U) 112 #define MIPI_DSI_PWR_UP_SHUTDOWNZ_SHIFT (0U) 113 #define MIPI_DSI_PWR_UP_SHUTDOWNZ_SET(x) (((uint32_t)(x) << MIPI_DSI_PWR_UP_SHUTDOWNZ_SHIFT) & MIPI_DSI_PWR_UP_SHUTDOWNZ_MASK) 114 #define MIPI_DSI_PWR_UP_SHUTDOWNZ_GET(x) (((uint32_t)(x) & MIPI_DSI_PWR_UP_SHUTDOWNZ_MASK) >> MIPI_DSI_PWR_UP_SHUTDOWNZ_SHIFT) 115 116 /* Bitfield definition for register: CLKMGR_CFG */ 117 /* 118 * TO_CLK_DIVISION (RW) 119 * 120 * the timeout clock division factor for HS to LP and LP to HS transition error 121 */ 122 #define MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_MASK (0xFF00U) 123 #define MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_SHIFT (8U) 124 #define MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_SET(x) (((uint32_t)(x) << MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_SHIFT) & MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_MASK) 125 #define MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_GET(x) (((uint32_t)(x) & MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_MASK) >> MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_SHIFT) 126 127 /* 128 * TX_ESC_CLK_DIVISION (RW) 129 * 130 * the division factor for the TX Escape clock source lanebyteclk 131 */ 132 #define MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_MASK (0xFFU) 133 #define MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_SHIFT (0U) 134 #define MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_SET(x) (((uint32_t)(x) << MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_SHIFT) & MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_MASK) 135 #define MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_GET(x) (((uint32_t)(x) & MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_MASK) >> MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_SHIFT) 136 137 /* Bitfield definition for register: DPI_VCID */ 138 /* 139 * DPI_VCID (RW) 140 * 141 * the DPI virtual channel id to the video mode packets 142 */ 143 #define MIPI_DSI_DPI_VCID_DPI_VCID_MASK (0x3U) 144 #define MIPI_DSI_DPI_VCID_DPI_VCID_SHIFT (0U) 145 #define MIPI_DSI_DPI_VCID_DPI_VCID_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_VCID_DPI_VCID_SHIFT) & MIPI_DSI_DPI_VCID_DPI_VCID_MASK) 146 #define MIPI_DSI_DPI_VCID_DPI_VCID_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_VCID_DPI_VCID_MASK) >> MIPI_DSI_DPI_VCID_DPI_VCID_SHIFT) 147 148 /* Bitfield definition for register: DPI_COLOR_CODING */ 149 /* 150 * LOOSELY18_EN (RW) 151 * 152 * when set to 1, this bit activates loosely packed variant to 18-bit configurations 153 */ 154 #define MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_MASK (0x100U) 155 #define MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_SHIFT (8U) 156 #define MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_SHIFT) & MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_MASK) 157 #define MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_MASK) >> MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_SHIFT) 158 159 /* 160 * DPI_COLOR_CODING (RW) 161 * 162 * configures the DPI color for video mode 163 */ 164 #define MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_MASK (0xFU) 165 #define MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_SHIFT (0U) 166 #define MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_SHIFT) & MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_MASK) 167 #define MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_MASK) >> MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_SHIFT) 168 169 /* Bitfield definition for register: DPI_CFG_POL */ 170 /* 171 * COLORM_ACTIVE_LOW (RW) 172 * 173 * configures the color mode pin as active low 174 */ 175 #define MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_MASK (0x10U) 176 #define MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_SHIFT (4U) 177 #define MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_SHIFT) & MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_MASK) 178 #define MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_MASK) >> MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_SHIFT) 179 180 /* 181 * SHUTD_ACTIVE_LOW (RW) 182 * 183 * configures the shutdown pin as active low 184 */ 185 #define MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_MASK (0x8U) 186 #define MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_SHIFT (3U) 187 #define MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_SHIFT) & MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_MASK) 188 #define MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_MASK) >> MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_SHIFT) 189 190 /* 191 * HSYNC_ACTIVE_LOW (RW) 192 * 193 * configures the horizontal synchronism pin as active low 194 */ 195 #define MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_MASK (0x4U) 196 #define MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_SHIFT (2U) 197 #define MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_SHIFT) & MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_MASK) 198 #define MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_MASK) >> MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_SHIFT) 199 200 /* 201 * VSYNC_ACTIVE_LOW (RW) 202 * 203 * configures the vertical synchronism pin as active low 204 */ 205 #define MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_MASK (0x2U) 206 #define MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_SHIFT (1U) 207 #define MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_SHIFT) & MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_MASK) 208 #define MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_MASK) >> MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_SHIFT) 209 210 /* 211 * DATAEN_ACTIVE_LOW (RW) 212 * 213 * configures the data enable pin active low 214 */ 215 #define MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_MASK (0x1U) 216 #define MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_SHIFT (0U) 217 #define MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_SHIFT) & MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_MASK) 218 #define MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_MASK) >> MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_SHIFT) 219 220 /* Bitfield definition for register: DPI_LP_CMD_TIM */ 221 /* 222 * OUTVACT_LPCMD_TIME (RW) 223 * 224 * transmission of commands in low-power mode, defines the size in bytes of the largest pachet that can fit in a line during the VSA VBP and VFP; 225 */ 226 #define MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_MASK (0xFF0000UL) 227 #define MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_SHIFT (16U) 228 #define MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_SHIFT) & MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_MASK) 229 #define MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_MASK) >> MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_SHIFT) 230 231 /* 232 * INVACT_LPCMD_TIME (RW) 233 * 234 * transmission of commands in low-power mode, defines the size in bytes of the largest packet that can fit in a line during the VACT region. 235 */ 236 #define MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_MASK (0xFFU) 237 #define MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_SHIFT (0U) 238 #define MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_SHIFT) & MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_MASK) 239 #define MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_MASK) >> MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_SHIFT) 240 241 /* Bitfield definition for register: PCKHDL_CFG */ 242 /* 243 * EOTP_TX_LP_EN (RW) 244 * 245 * enable the EoTp transmission in low-power 246 */ 247 #define MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_MASK (0x20U) 248 #define MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_SHIFT (5U) 249 #define MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_SHIFT) & MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_MASK) 250 #define MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_MASK) >> MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_SHIFT) 251 252 /* 253 * CRC_RX_EN (RW) 254 * 255 * enable the crc reception and error reporting 256 */ 257 #define MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_MASK (0x10U) 258 #define MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_SHIFT (4U) 259 #define MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_SHIFT) & MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_MASK) 260 #define MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_MASK) >> MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_SHIFT) 261 262 /* 263 * ECC_RX_EN (RW) 264 * 265 * enable the ecc reception error correction and reporting 266 */ 267 #define MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_MASK (0x8U) 268 #define MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_SHIFT (3U) 269 #define MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_SHIFT) & MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_MASK) 270 #define MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_MASK) >> MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_SHIFT) 271 272 /* 273 * BTA_EN (RW) 274 * 275 * enable the bus turn-around request 276 */ 277 #define MIPI_DSI_PCKHDL_CFG_BTA_EN_MASK (0x4U) 278 #define MIPI_DSI_PCKHDL_CFG_BTA_EN_SHIFT (2U) 279 #define MIPI_DSI_PCKHDL_CFG_BTA_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_PCKHDL_CFG_BTA_EN_SHIFT) & MIPI_DSI_PCKHDL_CFG_BTA_EN_MASK) 280 #define MIPI_DSI_PCKHDL_CFG_BTA_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_PCKHDL_CFG_BTA_EN_MASK) >> MIPI_DSI_PCKHDL_CFG_BTA_EN_SHIFT) 281 282 /* 283 * EOTP_RX_EN (RW) 284 * 285 * enable the EoTp reception 286 */ 287 #define MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_MASK (0x2U) 288 #define MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_SHIFT (1U) 289 #define MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_SHIFT) & MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_MASK) 290 #define MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_MASK) >> MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_SHIFT) 291 292 /* 293 * EOTP_TX_EN (RW) 294 * 295 * enable the EoTp transmission in high-speed 296 */ 297 #define MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_MASK (0x1U) 298 #define MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_SHIFT (0U) 299 #define MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_SHIFT) & MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_MASK) 300 #define MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_MASK) >> MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_SHIFT) 301 302 /* Bitfield definition for register: GEN_VCID */ 303 /* 304 * GEN_VCID_TX_AUTO (RW) 305 * 306 * indicates the generic interface virtual channel identification where generic packet is automatically generated and transmitted 307 */ 308 #define MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_MASK (0x30000UL) 309 #define MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_SHIFT (16U) 310 #define MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_SHIFT) & MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_MASK) 311 #define MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_MASK) >> MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_SHIFT) 312 313 /* 314 * GEN_VCID_TEAR_AUTO (RW) 315 * 316 * indicates the virtual channel identification for tear effect by hardware 317 */ 318 #define MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_MASK (0x300U) 319 #define MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_SHIFT (8U) 320 #define MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_SHIFT) & MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_MASK) 321 #define MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_MASK) >> MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_SHIFT) 322 323 /* 324 * GEN_VCID_RX (RW) 325 * 326 * indicates the generic interface read-back virtual channel identication 327 */ 328 #define MIPI_DSI_GEN_VCID_GEN_VCID_RX_MASK (0x3U) 329 #define MIPI_DSI_GEN_VCID_GEN_VCID_RX_SHIFT (0U) 330 #define MIPI_DSI_GEN_VCID_GEN_VCID_RX_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_VCID_GEN_VCID_RX_SHIFT) & MIPI_DSI_GEN_VCID_GEN_VCID_RX_MASK) 331 #define MIPI_DSI_GEN_VCID_GEN_VCID_RX_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_VCID_GEN_VCID_RX_MASK) >> MIPI_DSI_GEN_VCID_GEN_VCID_RX_SHIFT) 332 333 /* Bitfield definition for register: MODE_CFG */ 334 /* 335 * CMD_VIDEO_MODE (RW) 336 * 337 * 0x0: video mode 338 * 0x1: command mode 339 */ 340 #define MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_MASK (0x1U) 341 #define MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_SHIFT (0U) 342 #define MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_SET(x) (((uint32_t)(x) << MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_SHIFT) & MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_MASK) 343 #define MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_GET(x) (((uint32_t)(x) & MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_MASK) >> MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_SHIFT) 344 345 /* Bitfield definition for register: VID_MODE_CFG */ 346 /* 347 * VPG_ORIENTATION (RW) 348 * 349 * indicates the color bar orientation : 350 * 0x0: vertical mode 351 * 0x1: horizontal mode 352 */ 353 #define MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_MASK (0x1000000UL) 354 #define MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_SHIFT (24U) 355 #define MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_SHIFT) & MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_MASK) 356 #define MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_MASK) >> MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_SHIFT) 357 358 /* 359 * VPG_MODE (RW) 360 * 361 * 0x0: colorbar 362 * 0x1: berpattern, vertical only 363 */ 364 #define MIPI_DSI_VID_MODE_CFG_VPG_MODE_MASK (0x100000UL) 365 #define MIPI_DSI_VID_MODE_CFG_VPG_MODE_SHIFT (20U) 366 #define MIPI_DSI_VID_MODE_CFG_VPG_MODE_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_VPG_MODE_SHIFT) & MIPI_DSI_VID_MODE_CFG_VPG_MODE_MASK) 367 #define MIPI_DSI_VID_MODE_CFG_VPG_MODE_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_VPG_MODE_MASK) >> MIPI_DSI_VID_MODE_CFG_VPG_MODE_SHIFT) 368 369 /* 370 * VPG_EN (RW) 371 * 372 * enable video mode pattern generator 373 */ 374 #define MIPI_DSI_VID_MODE_CFG_VPG_EN_MASK (0x10000UL) 375 #define MIPI_DSI_VID_MODE_CFG_VPG_EN_SHIFT (16U) 376 #define MIPI_DSI_VID_MODE_CFG_VPG_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_VPG_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_VPG_EN_MASK) 377 #define MIPI_DSI_VID_MODE_CFG_VPG_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_VPG_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_VPG_EN_SHIFT) 378 379 /* 380 * LP_CMD_EN (RW) 381 * 382 * enable command transmission only in low-power mode 383 */ 384 #define MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_MASK (0x8000U) 385 #define MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_SHIFT (15U) 386 #define MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_MASK) 387 #define MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_SHIFT) 388 389 /* 390 * FRAME_BTA_ACK_EN (RW) 391 * 392 * enable the request for an acknowledge response at the end of a frame 393 */ 394 #define MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_MASK (0x4000U) 395 #define MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_SHIFT (14U) 396 #define MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_MASK) 397 #define MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_SHIFT) 398 399 /* 400 * LP_HFP_EN (RW) 401 * 402 * enable the return to low-power inside the HFP period when timing allows 403 */ 404 #define MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_MASK (0x2000U) 405 #define MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_SHIFT (13U) 406 #define MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_MASK) 407 #define MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_SHIFT) 408 409 /* 410 * LP_HBP_EN (RW) 411 * 412 * enable the return to low-power inside the HBP period when timing allows 413 */ 414 #define MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_MASK (0x1000U) 415 #define MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_SHIFT (12U) 416 #define MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_MASK) 417 #define MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_SHIFT) 418 419 /* 420 * LP_VACT_EN (RW) 421 * 422 * enable the return to low-power inside the VACT period when timing allows 423 */ 424 #define MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_MASK (0x800U) 425 #define MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_SHIFT (11U) 426 #define MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_MASK) 427 #define MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_SHIFT) 428 429 /* 430 * LP_VFP_EN (RW) 431 * 432 * enable the return to low-power inside the VFP period when timing allows 433 */ 434 #define MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_MASK (0x400U) 435 #define MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_SHIFT (10U) 436 #define MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_MASK) 437 #define MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_SHIFT) 438 439 /* 440 * LP_VBP_EN (RW) 441 * 442 * enable the return to low-power inside the VBP period when timing allows 443 */ 444 #define MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_MASK (0x200U) 445 #define MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_SHIFT (9U) 446 #define MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_MASK) 447 #define MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_SHIFT) 448 449 /* 450 * LP_VSA_EN (RW) 451 * 452 * enable the return to low-power inside the VSA period when timing allows 453 */ 454 #define MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_MASK (0x100U) 455 #define MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_SHIFT (8U) 456 #define MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_MASK) 457 #define MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_SHIFT) 458 459 /* 460 * VID_MODE_TYPE (RW) 461 * 462 * indicates the video mode transmission type 463 */ 464 #define MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_MASK (0x3U) 465 #define MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_SHIFT (0U) 466 #define MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_SHIFT) & MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_MASK) 467 #define MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_MASK) >> MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_SHIFT) 468 469 /* Bitfield definition for register: VID_PKT_SIZE */ 470 /* 471 * VID_PKT_SIZE (RW) 472 * 473 * configures the number of pixels in a single video packet 474 */ 475 #define MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_MASK (0x3FFFU) 476 #define MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_SHIFT (0U) 477 #define MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_SHIFT) & MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_MASK) 478 #define MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_MASK) >> MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_SHIFT) 479 480 /* Bitfield definition for register: VID_NUM_CHUNKS */ 481 /* 482 * VID_NUM_CHUNKS (RW) 483 * 484 * configures the number of chunks to be transmitted a line period 485 */ 486 #define MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_MASK (0x1FFFU) 487 #define MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_SHIFT (0U) 488 #define MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_SHIFT) & MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_MASK) 489 #define MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_MASK) >> MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_SHIFT) 490 491 /* Bitfield definition for register: VID_NULL_SIZE */ 492 /* 493 * VID_NULL_SIZE (RW) 494 * 495 * configures the number of bytes inside a null packet 496 */ 497 #define MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_MASK (0x1FFFU) 498 #define MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_SHIFT (0U) 499 #define MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_SHIFT) & MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_MASK) 500 #define MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_MASK) >> MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_SHIFT) 501 502 /* Bitfield definition for register: VID_HSA_TIME */ 503 /* 504 * VID_HSA_TIME (RW) 505 * 506 * configure the Horizontal synchronism active period in lane byte clock cycles 507 */ 508 #define MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_MASK (0xFFFU) 509 #define MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_SHIFT (0U) 510 #define MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_SHIFT) & MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_MASK) 511 #define MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_MASK) >> MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_SHIFT) 512 513 /* Bitfield definition for register: VID_HBP_TIME */ 514 /* 515 * VID_HPB_TIME (RW) 516 * 517 * configures the Horizontal back porch period in lane byte clock cycles 518 */ 519 #define MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_MASK (0xFFFU) 520 #define MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_SHIFT (0U) 521 #define MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_SHIFT) & MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_MASK) 522 #define MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_MASK) >> MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_SHIFT) 523 524 /* Bitfield definition for register: VID_HLINE_TIME */ 525 /* 526 * VID_HLINE_TIME (RW) 527 * 528 * configures the size of the total line time in lane byte clock cycles 529 */ 530 #define MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_MASK (0x7FFFU) 531 #define MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_SHIFT (0U) 532 #define MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_SHIFT) & MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_MASK) 533 #define MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_MASK) >> MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_SHIFT) 534 535 /* Bitfield definition for register: VID_VSA_LINES */ 536 /* 537 * VSA_LINES (RW) 538 * 539 * configures the verical synchronism active period measured in number of horizontal lines 540 */ 541 #define MIPI_DSI_VID_VSA_LINES_VSA_LINES_MASK (0x3FFU) 542 #define MIPI_DSI_VID_VSA_LINES_VSA_LINES_SHIFT (0U) 543 #define MIPI_DSI_VID_VSA_LINES_VSA_LINES_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_VSA_LINES_VSA_LINES_SHIFT) & MIPI_DSI_VID_VSA_LINES_VSA_LINES_MASK) 544 #define MIPI_DSI_VID_VSA_LINES_VSA_LINES_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_VSA_LINES_VSA_LINES_MASK) >> MIPI_DSI_VID_VSA_LINES_VSA_LINES_SHIFT) 545 546 /* Bitfield definition for register: VID_VBP_LINES */ 547 /* 548 * VBP_LINES (RW) 549 * 550 * configures the vertical back porch period measured in number of horizontal lines 551 */ 552 #define MIPI_DSI_VID_VBP_LINES_VBP_LINES_MASK (0x3FFU) 553 #define MIPI_DSI_VID_VBP_LINES_VBP_LINES_SHIFT (0U) 554 #define MIPI_DSI_VID_VBP_LINES_VBP_LINES_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_VBP_LINES_VBP_LINES_SHIFT) & MIPI_DSI_VID_VBP_LINES_VBP_LINES_MASK) 555 #define MIPI_DSI_VID_VBP_LINES_VBP_LINES_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_VBP_LINES_VBP_LINES_MASK) >> MIPI_DSI_VID_VBP_LINES_VBP_LINES_SHIFT) 556 557 /* Bitfield definition for register: VID_VFP_LINES */ 558 /* 559 * VFP_LINIES (RW) 560 * 561 * configures the vertical front porch period measured in number of horizontal lines 562 */ 563 #define MIPI_DSI_VID_VFP_LINES_VFP_LINIES_MASK (0x3FFU) 564 #define MIPI_DSI_VID_VFP_LINES_VFP_LINIES_SHIFT (0U) 565 #define MIPI_DSI_VID_VFP_LINES_VFP_LINIES_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_VFP_LINES_VFP_LINIES_SHIFT) & MIPI_DSI_VID_VFP_LINES_VFP_LINIES_MASK) 566 #define MIPI_DSI_VID_VFP_LINES_VFP_LINIES_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_VFP_LINES_VFP_LINIES_MASK) >> MIPI_DSI_VID_VFP_LINES_VFP_LINIES_SHIFT) 567 568 /* Bitfield definition for register: VID_VACTIVE_LINES */ 569 /* 570 * V_ACTIVE_LINES (RW) 571 * 572 * configures the vertical active period measured in number of horizontal lines 573 */ 574 #define MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_MASK (0x3FFFU) 575 #define MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_SHIFT (0U) 576 #define MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_SHIFT) & MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_MASK) 577 #define MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_MASK) >> MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_SHIFT) 578 579 /* Bitfield definition for register: CMD_MODE_CFG */ 580 /* 581 * MAX_RD_PKT_SIZE (RW) 582 * 583 * This bit configures the maximum read packet size command transmission type: 584 * 0x0 (HIGHSPEED): Transition type is High Speed 585 * 0x1 (LOWPOWER): Transition type is Low Power 586 */ 587 #define MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_MASK (0x1000000UL) 588 #define MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_SHIFT (24U) 589 #define MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_SHIFT) & MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_MASK) 590 #define MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_MASK) >> MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_SHIFT) 591 592 /* 593 * DCS_LW_TX (RW) 594 * 595 * This bit configures the DCS long write packet command transmission type: 596 * 0x0 (HIGHSPEED): Transition type is High Speed 597 * 0x1 (LOWPOWER): Transition type is Low Power 598 */ 599 #define MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_MASK (0x80000UL) 600 #define MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_SHIFT (19U) 601 #define MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_MASK) 602 #define MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_SHIFT) 603 604 /* 605 * DCS_SR_0P_TX (RW) 606 * 607 * This bit configures the DCS short read packet with zero parameter command transmission type: 608 * 0x0 (HIGHSPEED): Transition type is High Speed 609 * 0x1 (LOWPOWER): Transition type is Low Power 610 */ 611 #define MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_MASK (0x40000UL) 612 #define MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_SHIFT (18U) 613 #define MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_MASK) 614 #define MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_SHIFT) 615 616 /* 617 * DCS_SW_1P_TX (RW) 618 * 619 * This bit configures the DCS short write packet with one parameter command transmission type: 620 * 0x0 (HIGHSPEED): Transition type is High Speed 621 * 0x1 (LOWPOWER): Transition type is Low Power 622 */ 623 #define MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_MASK (0x20000UL) 624 #define MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_SHIFT (17U) 625 #define MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_MASK) 626 #define MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_SHIFT) 627 628 /* 629 * DCS_SW_0P_TX (RW) 630 * 631 * This bit configures the DCS short write packet with zero parameter command transmission type: 632 * 0x0 (HIGHSPEED): Transition type is High Speed 633 * 0x1 (LOWPOWER): Transition type is Low Power 634 */ 635 #define MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_MASK (0x10000UL) 636 #define MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_SHIFT (16U) 637 #define MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_MASK) 638 #define MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_SHIFT) 639 640 /* 641 * GEN_LW_TX (RW) 642 * 643 * This bit configures the Generic long write packet command transmission type: 644 * 0x0 (HIGHSPEED): Transition type is High Speed 645 * 0x1 (LOWPOWER): Transition type is Low Power 646 */ 647 #define MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_MASK (0x4000U) 648 #define MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_SHIFT (14U) 649 #define MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_MASK) 650 #define MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_SHIFT) 651 652 /* 653 * GEN_SR_2P_TX (RW) 654 * 655 * This bit configures the Generic short read packet with two parameters command transmission type: 656 * 0x0 (HIGHSPEED): Transition type is High Speed 657 * 0x1 (LOWPOWER): Transition type is Low Power 658 */ 659 #define MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_MASK (0x2000U) 660 #define MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_SHIFT (13U) 661 #define MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_MASK) 662 #define MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_SHIFT) 663 664 /* 665 * GEN_SR_1P_TX (RW) 666 * 667 * This bit configures the Generic short read packet with two parameters command transmission type: 668 * 0x0 (HIGHSPEED): Transition type is High Speed 669 * 0x1 (LOWPOWER): Transition type is Low Power 670 */ 671 #define MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_MASK (0x1000U) 672 #define MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_SHIFT (12U) 673 #define MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_MASK) 674 #define MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_SHIFT) 675 676 /* 677 * GEN_SR_0P_TX (RW) 678 * 679 * This bit configures the Generic short read packet with two parameters command transmission type: 680 * 0x0 (HIGHSPEED): Transition type is High Speed 681 * 0x1 (LOWPOWER): Transition type is Low Power 682 */ 683 #define MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_MASK (0x800U) 684 #define MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_SHIFT (11U) 685 #define MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_MASK) 686 #define MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_SHIFT) 687 688 /* 689 * GEN_SW_2P_TX (RW) 690 * 691 * This bit configures the Generic short read packet with two parameters command transmission type: 692 * 0x0 (HIGHSPEED): Transition type is High Speed 693 * 0x1 (LOWPOWER): Transition type is Low Power 694 */ 695 #define MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_MASK (0x400U) 696 #define MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_SHIFT (10U) 697 #define MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_MASK) 698 #define MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_SHIFT) 699 700 /* 701 * GEN_SW_1P_TX (RW) 702 * 703 * This bit configures the Generic short read packet with two parameters command transmission type: 704 * 0x0 (HIGHSPEED): Transition type is High Speed 705 * 0x1 (LOWPOWER): Transition type is Low Power 706 */ 707 #define MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_MASK (0x200U) 708 #define MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_SHIFT (9U) 709 #define MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_MASK) 710 #define MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_SHIFT) 711 712 /* 713 * GEN_SW_0P_TX (RW) 714 * 715 * This bit configures the Generic short read packet with two parameters command transmission type: 716 * 0x0 (HIGHSPEED): Transition type is High Speed 717 * 0x1 (LOWPOWER): Transition type is Low Power 718 */ 719 #define MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_MASK (0x100U) 720 #define MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_SHIFT (8U) 721 #define MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_MASK) 722 #define MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_SHIFT) 723 724 /* 725 * ACK_RQST_EN (RW) 726 * 727 * When set to 1, this bit enables the acknowledge request after each packet transmission. 728 */ 729 #define MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_MASK (0x2U) 730 #define MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_SHIFT (1U) 731 #define MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_SHIFT) & MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_MASK) 732 #define MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_MASK) >> MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_SHIFT) 733 734 /* 735 * TEAR_FX_EN (RW) 736 * 737 * When set to 1, this bit enables the tearing effect acknowledge request. 738 */ 739 #define MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_MASK (0x1U) 740 #define MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_SHIFT (0U) 741 #define MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_SHIFT) & MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_MASK) 742 #define MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_MASK) >> MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_SHIFT) 743 744 /* Bitfield definition for register: GEN_HDR */ 745 /* 746 * GEN_WC_MSBYTE (RW) 747 * 748 * configures the most significant byte of the header packet's word count for long packets or data 1 for shout packets 749 */ 750 #define MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_MASK (0xFF0000UL) 751 #define MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_SHIFT (16U) 752 #define MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_SHIFT) & MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_MASK) 753 #define MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_MASK) >> MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_SHIFT) 754 755 /* 756 * GEN_WC_LSBYTE (RW) 757 * 758 * configures the least significant byte of the header packet's word count for long packets or data0 for short packets 759 */ 760 #define MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_MASK (0xFF00U) 761 #define MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_SHIFT (8U) 762 #define MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_SHIFT) & MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_MASK) 763 #define MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_MASK) >> MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_SHIFT) 764 765 /* 766 * GEN_VC (RW) 767 * 768 * configures the virtual channel ID of the header packet 769 */ 770 #define MIPI_DSI_GEN_HDR_GEN_VC_MASK (0xC0U) 771 #define MIPI_DSI_GEN_HDR_GEN_VC_SHIFT (6U) 772 #define MIPI_DSI_GEN_HDR_GEN_VC_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_HDR_GEN_VC_SHIFT) & MIPI_DSI_GEN_HDR_GEN_VC_MASK) 773 #define MIPI_DSI_GEN_HDR_GEN_VC_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_HDR_GEN_VC_MASK) >> MIPI_DSI_GEN_HDR_GEN_VC_SHIFT) 774 775 /* 776 * GEN_DT (RW) 777 * 778 * configures the packet data type of the header packet 779 */ 780 #define MIPI_DSI_GEN_HDR_GEN_DT_MASK (0x3FU) 781 #define MIPI_DSI_GEN_HDR_GEN_DT_SHIFT (0U) 782 #define MIPI_DSI_GEN_HDR_GEN_DT_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_HDR_GEN_DT_SHIFT) & MIPI_DSI_GEN_HDR_GEN_DT_MASK) 783 #define MIPI_DSI_GEN_HDR_GEN_DT_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_HDR_GEN_DT_MASK) >> MIPI_DSI_GEN_HDR_GEN_DT_SHIFT) 784 785 /* Bitfield definition for register: GEN_PLD_DATA */ 786 /* 787 * GEN_PLD_B4 (RW) 788 * 789 * indicates byte4 of the packet payload 790 */ 791 #define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_MASK (0xFF000000UL) 792 #define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_SHIFT (24U) 793 #define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_SHIFT) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_MASK) 794 #define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_MASK) >> MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_SHIFT) 795 796 /* 797 * GEN_PLD_B3 (RW) 798 * 799 * indicates byte3 of the packet payload 800 */ 801 #define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_MASK (0xFF0000UL) 802 #define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_SHIFT (16U) 803 #define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_SHIFT) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_MASK) 804 #define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_MASK) >> MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_SHIFT) 805 806 /* 807 * GEN_PLD_B2 (RW) 808 * 809 * indicates byte2 of the packet payload 810 */ 811 #define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_MASK (0xFF00U) 812 #define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_SHIFT (8U) 813 #define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_SHIFT) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_MASK) 814 #define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_MASK) >> MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_SHIFT) 815 816 /* 817 * GEN_PLD_B1 (RW) 818 * 819 * indicates byte1 of the packet payload 820 */ 821 #define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_MASK (0xFFU) 822 #define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_SHIFT (0U) 823 #define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_SHIFT) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_MASK) 824 #define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_MASK) >> MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_SHIFT) 825 826 /* Bitfield definition for register: CMD_PKT_STATUS */ 827 /* 828 * GEN_BUFF_PLD_FULL (R) 829 * 830 * the full status of the generic payload internal buffer 831 */ 832 #define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_FULL_MASK (0x80000UL) 833 #define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_FULL_SHIFT (19U) 834 #define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_FULL_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_FULL_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_FULL_SHIFT) 835 836 /* 837 * GEN_BUFF_PLD_EMPTY (R) 838 * 839 * the empty status of the generic payload internal buffer 840 */ 841 #define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_EMPTY_MASK (0x40000UL) 842 #define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_EMPTY_SHIFT (18U) 843 #define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_EMPTY_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_EMPTY_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_EMPTY_SHIFT) 844 845 /* 846 * GEN_BUFF_CMD_FULL (R) 847 * 848 * the full status of the generic command internal buffer 849 */ 850 #define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_FULL_MASK (0x20000UL) 851 #define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_FULL_SHIFT (17U) 852 #define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_FULL_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_FULL_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_FULL_SHIFT) 853 854 /* 855 * GEN_BUFF_CMD_EMPTY (R) 856 * 857 * the empty status of the generic command internal buffer 858 */ 859 #define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_EMPTY_MASK (0x10000UL) 860 #define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_EMPTY_SHIFT (16U) 861 #define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_EMPTY_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_EMPTY_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_EMPTY_SHIFT) 862 863 /* 864 * GEN_RD_CMD_BUSY (R) 865 * 866 * indicates a read command is issued and the entire response is not sotred in the FIFO 867 */ 868 #define MIPI_DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY_MASK (0x40U) 869 #define MIPI_DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY_SHIFT (6U) 870 #define MIPI_DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY_SHIFT) 871 872 /* 873 * GEN_PLD_R_FULL (R) 874 * 875 * indicates the full status of the generic read payoad FIFO 876 */ 877 #define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_FULL_MASK (0x20U) 878 #define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_FULL_SHIFT (5U) 879 #define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_FULL_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_FULL_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_FULL_SHIFT) 880 881 /* 882 * GEN_PLD_R_EMPTY (R) 883 * 884 * indicates the empty status of the generic read payload FIFO 885 */ 886 #define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY_MASK (0x10U) 887 #define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY_SHIFT (4U) 888 #define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY_SHIFT) 889 890 /* 891 * GEN_PLD_W_FULL (R) 892 * 893 * indicates the full status of the generic write payload FIFO 894 */ 895 #define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL_MASK (0x8U) 896 #define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL_SHIFT (3U) 897 #define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL_SHIFT) 898 899 /* 900 * GEN_PLD_W_EMPTY (R) 901 * 902 * indicates the empty status of the generic write payload FIFO 903 */ 904 #define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY_MASK (0x4U) 905 #define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY_SHIFT (2U) 906 #define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY_SHIFT) 907 908 /* 909 * GEN_CMD_FULL (R) 910 * 911 * indicates the full status of the generic command FIFO 912 */ 913 #define MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_FULL_MASK (0x2U) 914 #define MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_FULL_SHIFT (1U) 915 #define MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_FULL_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_FULL_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_FULL_SHIFT) 916 917 /* 918 * GEN_CMD_EMPTY (R) 919 * 920 * indicates the empty status of the generic command FIFO 921 */ 922 #define MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY_MASK (0x1U) 923 #define MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY_SHIFT (0U) 924 #define MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY_SHIFT) 925 926 /* Bitfield definition for register: TO_CNT_CFG */ 927 /* 928 * HSTX_TO_CNT (RW) 929 * 930 * configures the timeout counter that triggers a high speed transmission timeout contention detection 931 */ 932 #define MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_MASK (0xFFFF0000UL) 933 #define MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_SHIFT (16U) 934 #define MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_SET(x) (((uint32_t)(x) << MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_SHIFT) & MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_MASK) 935 #define MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_GET(x) (((uint32_t)(x) & MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_MASK) >> MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_SHIFT) 936 937 /* 938 * LPRX_TO_CNT (RW) 939 * 940 * configures the timeout counter that triggers a low power reception timeout contention detection 941 */ 942 #define MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_MASK (0xFFFFU) 943 #define MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_SHIFT (0U) 944 #define MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_SET(x) (((uint32_t)(x) << MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_SHIFT) & MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_MASK) 945 #define MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_GET(x) (((uint32_t)(x) & MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_MASK) >> MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_SHIFT) 946 947 /* Bitfield definition for register: HS_RD_TO_CNT */ 948 /* 949 * HS_RD_TO_CNT (RW) 950 * 951 * sets a period for which DWC_mipi_dsi_host keeps the link still after sending a high speed read operation; 952 */ 953 #define MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_MASK (0xFFFFU) 954 #define MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_SHIFT (0U) 955 #define MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_SET(x) (((uint32_t)(x) << MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_SHIFT) & MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_MASK) 956 #define MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_GET(x) (((uint32_t)(x) & MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_MASK) >> MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_SHIFT) 957 958 /* Bitfield definition for register: LP_RD_TO_CNT */ 959 /* 960 * LP_RD_TO_CNT (RW) 961 * 962 * sets a period for which dwc_mipi_dsi_host keeps the link still after sending a low power read operation 963 */ 964 #define MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_MASK (0xFFFFU) 965 #define MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_SHIFT (0U) 966 #define MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_SET(x) (((uint32_t)(x) << MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_SHIFT) & MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_MASK) 967 #define MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_GET(x) (((uint32_t)(x) & MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_MASK) >> MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_SHIFT) 968 969 /* Bitfield definition for register: HS_WR_TO_CNT */ 970 /* 971 * HS_WR_TO_CNT (RW) 972 * 973 * sets the period for which dwc_mipi_dsi_host keeps the link still after sending a high speed wirte operation 974 */ 975 #define MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_MASK (0xFFFFU) 976 #define MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_SHIFT (0U) 977 #define MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_SET(x) (((uint32_t)(x) << MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_SHIFT) & MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_MASK) 978 #define MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_GET(x) (((uint32_t)(x) & MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_MASK) >> MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_SHIFT) 979 980 /* Bitfield definition for register: LP_WR_TO_CNT */ 981 /* 982 * LP_WR_TO_CNT (RW) 983 * 984 * sets the period for which dsi host keeps the link still after sending a low power write operation 985 */ 986 #define MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_MASK (0xFFFFU) 987 #define MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_SHIFT (0U) 988 #define MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_SET(x) (((uint32_t)(x) << MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_SHIFT) & MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_MASK) 989 #define MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_GET(x) (((uint32_t)(x) & MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_MASK) >> MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_SHIFT) 990 991 /* Bitfield definition for register: BTA_TO_CNT */ 992 /* 993 * BTA_TO_CNT (RW) 994 * 995 * sets the period for which dsi host keeps the link still after completing a bus turnaround. 996 */ 997 #define MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_MASK (0xFFFFU) 998 #define MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_SHIFT (0U) 999 #define MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_SET(x) (((uint32_t)(x) << MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_SHIFT) & MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_MASK) 1000 #define MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_GET(x) (((uint32_t)(x) & MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_MASK) >> MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_SHIFT) 1001 1002 /* Bitfield definition for register: SDF_3D */ 1003 /* 1004 * SEND_3D_CFG (RW) 1005 * 1006 * set the next vss packet to include 3d control payload in every vss packet 1007 */ 1008 #define MIPI_DSI_SDF_3D_SEND_3D_CFG_MASK (0x10000UL) 1009 #define MIPI_DSI_SDF_3D_SEND_3D_CFG_SHIFT (16U) 1010 #define MIPI_DSI_SDF_3D_SEND_3D_CFG_SET(x) (((uint32_t)(x) << MIPI_DSI_SDF_3D_SEND_3D_CFG_SHIFT) & MIPI_DSI_SDF_3D_SEND_3D_CFG_MASK) 1011 #define MIPI_DSI_SDF_3D_SEND_3D_CFG_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_SEND_3D_CFG_MASK) >> MIPI_DSI_SDF_3D_SEND_3D_CFG_SHIFT) 1012 1013 /* 1014 * RIGHT_FIRST (RW) 1015 * 1016 * 0x0: left eye is sent first 1017 * 0x1:right eye is sent first 1018 */ 1019 #define MIPI_DSI_SDF_3D_RIGHT_FIRST_MASK (0x20U) 1020 #define MIPI_DSI_SDF_3D_RIGHT_FIRST_SHIFT (5U) 1021 #define MIPI_DSI_SDF_3D_RIGHT_FIRST_SET(x) (((uint32_t)(x) << MIPI_DSI_SDF_3D_RIGHT_FIRST_SHIFT) & MIPI_DSI_SDF_3D_RIGHT_FIRST_MASK) 1022 #define MIPI_DSI_SDF_3D_RIGHT_FIRST_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_RIGHT_FIRST_MASK) >> MIPI_DSI_SDF_3D_RIGHT_FIRST_SHIFT) 1023 1024 /* 1025 * SECOND_VSYNC (RW) 1026 * 1027 * defines whether there is a second VSYNC pulse 1028 */ 1029 #define MIPI_DSI_SDF_3D_SECOND_VSYNC_MASK (0x10U) 1030 #define MIPI_DSI_SDF_3D_SECOND_VSYNC_SHIFT (4U) 1031 #define MIPI_DSI_SDF_3D_SECOND_VSYNC_SET(x) (((uint32_t)(x) << MIPI_DSI_SDF_3D_SECOND_VSYNC_SHIFT) & MIPI_DSI_SDF_3D_SECOND_VSYNC_MASK) 1032 #define MIPI_DSI_SDF_3D_SECOND_VSYNC_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_SECOND_VSYNC_MASK) >> MIPI_DSI_SDF_3D_SECOND_VSYNC_SHIFT) 1033 1034 /* 1035 * FORMAT_3D (RW) 1036 * 1037 * defines 3D image format 1038 */ 1039 #define MIPI_DSI_SDF_3D_FORMAT_3D_MASK (0xCU) 1040 #define MIPI_DSI_SDF_3D_FORMAT_3D_SHIFT (2U) 1041 #define MIPI_DSI_SDF_3D_FORMAT_3D_SET(x) (((uint32_t)(x) << MIPI_DSI_SDF_3D_FORMAT_3D_SHIFT) & MIPI_DSI_SDF_3D_FORMAT_3D_MASK) 1042 #define MIPI_DSI_SDF_3D_FORMAT_3D_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_FORMAT_3D_MASK) >> MIPI_DSI_SDF_3D_FORMAT_3D_SHIFT) 1043 1044 /* 1045 * MODE_3D (RW) 1046 * 1047 * defines 3D mode on/off 1048 */ 1049 #define MIPI_DSI_SDF_3D_MODE_3D_MASK (0x3U) 1050 #define MIPI_DSI_SDF_3D_MODE_3D_SHIFT (0U) 1051 #define MIPI_DSI_SDF_3D_MODE_3D_SET(x) (((uint32_t)(x) << MIPI_DSI_SDF_3D_MODE_3D_SHIFT) & MIPI_DSI_SDF_3D_MODE_3D_MASK) 1052 #define MIPI_DSI_SDF_3D_MODE_3D_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_MODE_3D_MASK) >> MIPI_DSI_SDF_3D_MODE_3D_SHIFT) 1053 1054 /* Bitfield definition for register: LPCLK_CTRL */ 1055 /* 1056 * AUTO_CLKLANE_CTRL (RW) 1057 * 1058 * enables the automatic mechanism to stop providing clock in the clock lane 1059 */ 1060 #define MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_MASK (0x2U) 1061 #define MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_SHIFT (1U) 1062 #define MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_SET(x) (((uint32_t)(x) << MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_SHIFT) & MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_MASK) 1063 #define MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_GET(x) (((uint32_t)(x) & MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_MASK) >> MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_SHIFT) 1064 1065 /* 1066 * PHY_TXREQUESTCLKHS (RW) 1067 * 1068 * controls the D-PHY PPI txrequestclkhs signal 1069 */ 1070 #define MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_MASK (0x1U) 1071 #define MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_SHIFT (0U) 1072 #define MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_SET(x) (((uint32_t)(x) << MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_SHIFT) & MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_MASK) 1073 #define MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_GET(x) (((uint32_t)(x) & MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_MASK) >> MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_SHIFT) 1074 1075 /* Bitfield definition for register: PHY_TMR_LPCLK_CFG */ 1076 /* 1077 * PHY_CLKHS2LP_TIME (RW) 1078 * 1079 * configures the maximum time that the d-phy clock lane takes to go from high-speed to low-power transmission 1080 */ 1081 #define MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_MASK (0x3FF0000UL) 1082 #define MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_SHIFT (16U) 1083 #define MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_SHIFT) & MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_MASK) 1084 #define MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_MASK) >> MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_SHIFT) 1085 1086 /* 1087 * PHY_CLKLP2HS_TIME (RW) 1088 * 1089 * configures the maximum time that the d-phy clock lane takes to go from low-power to high-speed transmission 1090 */ 1091 #define MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_MASK (0x3FFU) 1092 #define MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_SHIFT (0U) 1093 #define MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_SHIFT) & MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_MASK) 1094 #define MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_MASK) >> MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_SHIFT) 1095 1096 /* Bitfield definition for register: PHY_TMR_CFG */ 1097 /* 1098 * PHY_HS2LP_TIME (RW) 1099 * 1100 * This field configures the maximum time that the D-PHY data 1101 * lanes take to go from high-speed to low-power transmission 1102 * measured in lane byte clock cycles 1103 */ 1104 #define MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_MASK (0x3FF0000UL) 1105 #define MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_SHIFT (16U) 1106 #define MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_SHIFT) & MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_MASK) 1107 #define MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_MASK) >> MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_SHIFT) 1108 1109 /* 1110 * PHY_LP2HS_TIME (RW) 1111 * 1112 * This field configures the maximum time that the D-PHY data 1113 * lanes take to go from low-power to high-speed transmission 1114 * measured in lane byte clock cycles. 1115 */ 1116 #define MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_MASK (0x3FFU) 1117 #define MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_SHIFT (0U) 1118 #define MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_SHIFT) & MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_MASK) 1119 #define MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_MASK) >> MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_SHIFT) 1120 1121 /* Bitfield definition for register: PHY_RSTZ */ 1122 /* 1123 * PHY_FORCEPLL (RW) 1124 * 1125 * when the d-phy is in ulps, enable the d-phy pll 1126 */ 1127 #define MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_MASK (0x8U) 1128 #define MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_SHIFT (3U) 1129 #define MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_SHIFT) & MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_MASK) 1130 #define MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_MASK) >> MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_SHIFT) 1131 1132 /* 1133 * PHY_ENABLECLK (RW) 1134 * 1135 * enable dphy clock lane 1136 */ 1137 #define MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_MASK (0x4U) 1138 #define MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_SHIFT (2U) 1139 #define MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_SHIFT) & MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_MASK) 1140 #define MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_MASK) >> MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_SHIFT) 1141 1142 /* 1143 * PHY_RSTZ (RW) 1144 * 1145 * make the dphy in reset state when set to 0 1146 */ 1147 #define MIPI_DSI_PHY_RSTZ_PHY_RSTZ_MASK (0x2U) 1148 #define MIPI_DSI_PHY_RSTZ_PHY_RSTZ_SHIFT (1U) 1149 #define MIPI_DSI_PHY_RSTZ_PHY_RSTZ_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_RSTZ_PHY_RSTZ_SHIFT) & MIPI_DSI_PHY_RSTZ_PHY_RSTZ_MASK) 1150 #define MIPI_DSI_PHY_RSTZ_PHY_RSTZ_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_RSTZ_PHY_RSTZ_MASK) >> MIPI_DSI_PHY_RSTZ_PHY_RSTZ_SHIFT) 1151 1152 /* 1153 * PHY_SHUTDOWNZ (RW) 1154 * 1155 * places the dphy macro in power down mode when set to 0 1156 */ 1157 #define MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_MASK (0x1U) 1158 #define MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_SHIFT (0U) 1159 #define MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_SHIFT) & MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_MASK) 1160 #define MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_MASK) >> MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_SHIFT) 1161 1162 /* Bitfield definition for register: PHY_IF_CFG */ 1163 /* 1164 * PHY_STOP_WAIT_TIME (RW) 1165 * 1166 * configures the minimum time phy needs to stay in stopstate before requesting an highspeed transmission 1167 */ 1168 #define MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_MASK (0xFF00U) 1169 #define MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_SHIFT (8U) 1170 #define MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_SHIFT) & MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_MASK) 1171 #define MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_MASK) >> MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_SHIFT) 1172 1173 /* 1174 * N_LANES (RW) 1175 * 1176 * configures the number of active data lanes 1177 */ 1178 #define MIPI_DSI_PHY_IF_CFG_N_LANES_MASK (0x3U) 1179 #define MIPI_DSI_PHY_IF_CFG_N_LANES_SHIFT (0U) 1180 #define MIPI_DSI_PHY_IF_CFG_N_LANES_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_IF_CFG_N_LANES_SHIFT) & MIPI_DSI_PHY_IF_CFG_N_LANES_MASK) 1181 #define MIPI_DSI_PHY_IF_CFG_N_LANES_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_IF_CFG_N_LANES_MASK) >> MIPI_DSI_PHY_IF_CFG_N_LANES_SHIFT) 1182 1183 /* Bitfield definition for register: PHY_ULPS_CTRL */ 1184 /* 1185 * PHY_TXEXITULPSLAN (RW) 1186 * 1187 * ulps mode exit on all active data lanes 1188 */ 1189 #define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_MASK (0x8U) 1190 #define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_SHIFT (3U) 1191 #define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_SHIFT) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_MASK) 1192 #define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_MASK) >> MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_SHIFT) 1193 1194 /* 1195 * PHY_TXREQULPSLAN (RW) 1196 * 1197 * ulps mode request on all active data lanes 1198 */ 1199 #define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_MASK (0x4U) 1200 #define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_SHIFT (2U) 1201 #define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_SHIFT) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_MASK) 1202 #define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_MASK) >> MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_SHIFT) 1203 1204 /* 1205 * PHY_TXEXITULPSCLK (RW) 1206 * 1207 * ulps mode exit on clock lane 1208 */ 1209 #define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_MASK (0x2U) 1210 #define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_SHIFT (1U) 1211 #define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_SHIFT) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_MASK) 1212 #define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_MASK) >> MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_SHIFT) 1213 1214 /* 1215 * PHY_TXREQULPSCLK (RW) 1216 * 1217 * ulps mode request on clock lane 1218 */ 1219 #define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_MASK (0x1U) 1220 #define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_SHIFT (0U) 1221 #define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_SHIFT) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_MASK) 1222 #define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_MASK) >> MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_SHIFT) 1223 1224 /* Bitfield definition for register: PHY_TX_TRIGGERS */ 1225 /* 1226 * PHY_TX_TRIGGERS (RW) 1227 * 1228 * controls the trigger transmissions 1229 */ 1230 #define MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_MASK (0xFU) 1231 #define MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_SHIFT (0U) 1232 #define MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_SHIFT) & MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_MASK) 1233 #define MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_MASK) >> MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_SHIFT) 1234 1235 /* Bitfield definition for register: PHY_STATUS */ 1236 /* 1237 * PHY_ULPSACTIVENOT3LANE (R) 1238 * 1239 * indicates the status of ulpsactivenot3lane d-phy signal 1240 */ 1241 #define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT3LANE_MASK (0x1000U) 1242 #define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT3LANE_SHIFT (12U) 1243 #define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT3LANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT3LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT3LANE_SHIFT) 1244 1245 /* 1246 * PHY_STOPSTATE3LANE (R) 1247 * 1248 * This bit indicates the status of phystopstate3lane D-PHY 1249 * signal. 1250 */ 1251 #define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE3LANE_MASK (0x800U) 1252 #define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE3LANE_SHIFT (11U) 1253 #define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE3LANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_STOPSTATE3LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_STOPSTATE3LANE_SHIFT) 1254 1255 /* 1256 * PHY_ULPSACTIVENOT2LANE (R) 1257 * 1258 * This bit indicates the status of ulpsactivenot2lane D-PHY 1259 * signa 1260 */ 1261 #define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT2LANE_MASK (0x400U) 1262 #define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT2LANE_SHIFT (10U) 1263 #define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT2LANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT2LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT2LANE_SHIFT) 1264 1265 /* 1266 * PHY_STOPSTATE2LANE (R) 1267 * 1268 * This bit indicates the status of phystopstate2lane D-PHY 1269 * signal 1270 */ 1271 #define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE2LANE_MASK (0x200U) 1272 #define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE2LANE_SHIFT (9U) 1273 #define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE2LANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_STOPSTATE2LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_STOPSTATE2LANE_SHIFT) 1274 1275 /* 1276 * PHY_ULPSACTIVENOT1LANE (R) 1277 * 1278 * This bit indicates the status of ulpsactivenot1lane D-PHY 1279 * signal 1280 */ 1281 #define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT1LANE_MASK (0x100U) 1282 #define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT1LANE_SHIFT (8U) 1283 #define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT1LANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT1LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT1LANE_SHIFT) 1284 1285 /* 1286 * PHY_STOPSTATE1LANE (R) 1287 * 1288 * This bit indicates the status of phystopstate1lane D-PHY 1289 * signal 1290 */ 1291 #define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE1LANE_MASK (0x80U) 1292 #define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE1LANE_SHIFT (7U) 1293 #define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE1LANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_STOPSTATE1LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_STOPSTATE1LANE_SHIFT) 1294 1295 /* 1296 * PHY_RXULPSESC0LANE (R) 1297 * 1298 * This bit indicates the status of rxulpsesc0lane D-PHY signa 1299 */ 1300 #define MIPI_DSI_PHY_STATUS_PHY_RXULPSESC0LANE_MASK (0x40U) 1301 #define MIPI_DSI_PHY_STATUS_PHY_RXULPSESC0LANE_SHIFT (6U) 1302 #define MIPI_DSI_PHY_STATUS_PHY_RXULPSESC0LANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_RXULPSESC0LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_RXULPSESC0LANE_SHIFT) 1303 1304 /* 1305 * PHY_ULPSACTIVENOT0LANE (R) 1306 * 1307 * This bit indicates the status of ulpsactivenot0lane D-PHY 1308 * signal 1309 */ 1310 #define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT0LANE_MASK (0x20U) 1311 #define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT0LANE_SHIFT (5U) 1312 #define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT0LANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT0LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT0LANE_SHIFT) 1313 1314 /* 1315 * PHY_STOPSTATE0LANE (R) 1316 * 1317 * This bit indicates the status of phystopstate0lane D-PHY 1318 * signal 1319 */ 1320 #define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE0LANE_MASK (0x10U) 1321 #define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE0LANE_SHIFT (4U) 1322 #define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE0LANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_STOPSTATE0LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_STOPSTATE0LANE_SHIFT) 1323 1324 /* 1325 * PHY_ULPSACTIVENOTCLK (R) 1326 * 1327 * This bit indicates the status of phyulpsactivenotclk D-PHY 1328 * signal 1329 */ 1330 #define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOTCLK_MASK (0x8U) 1331 #define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOTCLK_SHIFT (3U) 1332 #define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOTCLK_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOTCLK_MASK) >> MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOTCLK_SHIFT) 1333 1334 /* 1335 * PHY_STOPSTATECLKLANE (R) 1336 * 1337 * This bit indicates the status of phystopstateclklane D-PHY 1338 * signal 1339 */ 1340 #define MIPI_DSI_PHY_STATUS_PHY_STOPSTATECLKLANE_MASK (0x4U) 1341 #define MIPI_DSI_PHY_STATUS_PHY_STOPSTATECLKLANE_SHIFT (2U) 1342 #define MIPI_DSI_PHY_STATUS_PHY_STOPSTATECLKLANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_STOPSTATECLKLANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_STOPSTATECLKLANE_SHIFT) 1343 1344 /* 1345 * PHY_DIRECTION (R) 1346 * 1347 * This bit indicates the status of phydirection D-PHY signal 1348 */ 1349 #define MIPI_DSI_PHY_STATUS_PHY_DIRECTION_MASK (0x2U) 1350 #define MIPI_DSI_PHY_STATUS_PHY_DIRECTION_SHIFT (1U) 1351 #define MIPI_DSI_PHY_STATUS_PHY_DIRECTION_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_DIRECTION_MASK) >> MIPI_DSI_PHY_STATUS_PHY_DIRECTION_SHIFT) 1352 1353 /* 1354 * PHY_LOCK (R) 1355 * 1356 * This bit indicates the status of phylock D-PHY signal 1357 */ 1358 #define MIPI_DSI_PHY_STATUS_PHY_LOCK_MASK (0x1U) 1359 #define MIPI_DSI_PHY_STATUS_PHY_LOCK_SHIFT (0U) 1360 #define MIPI_DSI_PHY_STATUS_PHY_LOCK_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_LOCK_MASK) >> MIPI_DSI_PHY_STATUS_PHY_LOCK_SHIFT) 1361 1362 /* Bitfield definition for register: PHY_TST_CTRL0 */ 1363 /* 1364 * PHY_TESTCLK (RW) 1365 * 1366 * reserve 1367 */ 1368 #define MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_MASK (0x2U) 1369 #define MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_SHIFT (1U) 1370 #define MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_SHIFT) & MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_MASK) 1371 #define MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_MASK) >> MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_SHIFT) 1372 1373 /* 1374 * PHY_TESTCLR (RW) 1375 * 1376 * reserve 1377 */ 1378 #define MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_MASK (0x1U) 1379 #define MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_SHIFT (0U) 1380 #define MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_SHIFT) & MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_MASK) 1381 #define MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_MASK) >> MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_SHIFT) 1382 1383 /* Bitfield definition for register: PHY_TST_CTRL1 */ 1384 /* 1385 * PHY_TESTEN (RW) 1386 * 1387 * reserve 1388 */ 1389 #define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_MASK (0x10000UL) 1390 #define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_SHIFT (16U) 1391 #define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_SHIFT) & MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_MASK) 1392 #define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_MASK) >> MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_SHIFT) 1393 1394 /* 1395 * PHY_TESTDOUT (R) 1396 * 1397 * reserve 1398 */ 1399 #define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDOUT_MASK (0xFF00U) 1400 #define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDOUT_SHIFT (8U) 1401 #define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDOUT_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDOUT_MASK) >> MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDOUT_SHIFT) 1402 1403 /* 1404 * PHY_TESTDIN (RW) 1405 * 1406 * reserve 1407 */ 1408 #define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_MASK (0xFFU) 1409 #define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_SHIFT (0U) 1410 #define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_SHIFT) & MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_MASK) 1411 #define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_MASK) >> MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_SHIFT) 1412 1413 /* Bitfield definition for register: INT_ST0 */ 1414 /* 1415 * DPHY_ERRORS_4 (R) 1416 * 1417 * indicates LP1 contention error ErrContentionLP1 from lane0 1418 */ 1419 #define MIPI_DSI_INT_ST0_DPHY_ERRORS_4_MASK (0x100000UL) 1420 #define MIPI_DSI_INT_ST0_DPHY_ERRORS_4_SHIFT (20U) 1421 #define MIPI_DSI_INT_ST0_DPHY_ERRORS_4_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_DPHY_ERRORS_4_MASK) >> MIPI_DSI_INT_ST0_DPHY_ERRORS_4_SHIFT) 1422 1423 /* 1424 * DPHY_ERRORS_3 (R) 1425 * 1426 * indicates LP0 contention error ErrContentionLP0 from lane0 1427 */ 1428 #define MIPI_DSI_INT_ST0_DPHY_ERRORS_3_MASK (0x80000UL) 1429 #define MIPI_DSI_INT_ST0_DPHY_ERRORS_3_SHIFT (19U) 1430 #define MIPI_DSI_INT_ST0_DPHY_ERRORS_3_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_DPHY_ERRORS_3_MASK) >> MIPI_DSI_INT_ST0_DPHY_ERRORS_3_SHIFT) 1431 1432 /* 1433 * DPHY_ERRORS_2 (R) 1434 * 1435 * indicates control error ErrControl from lane0 1436 */ 1437 #define MIPI_DSI_INT_ST0_DPHY_ERRORS_2_MASK (0x40000UL) 1438 #define MIPI_DSI_INT_ST0_DPHY_ERRORS_2_SHIFT (18U) 1439 #define MIPI_DSI_INT_ST0_DPHY_ERRORS_2_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_DPHY_ERRORS_2_MASK) >> MIPI_DSI_INT_ST0_DPHY_ERRORS_2_SHIFT) 1440 1441 /* 1442 * DPHY_ERRORS_1 (R) 1443 * 1444 * indicates ErrSyncEsc low-power data transmission synchronization error from lane 0 1445 */ 1446 #define MIPI_DSI_INT_ST0_DPHY_ERRORS_1_MASK (0x20000UL) 1447 #define MIPI_DSI_INT_ST0_DPHY_ERRORS_1_SHIFT (17U) 1448 #define MIPI_DSI_INT_ST0_DPHY_ERRORS_1_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_DPHY_ERRORS_1_MASK) >> MIPI_DSI_INT_ST0_DPHY_ERRORS_1_SHIFT) 1449 1450 /* 1451 * DPHY_ERRORS_0 (R) 1452 * 1453 * indicates ErrEsc escape entry error from lane0 1454 */ 1455 #define MIPI_DSI_INT_ST0_DPHY_ERRORS_0_MASK (0x10000UL) 1456 #define MIPI_DSI_INT_ST0_DPHY_ERRORS_0_SHIFT (16U) 1457 #define MIPI_DSI_INT_ST0_DPHY_ERRORS_0_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_DPHY_ERRORS_0_MASK) >> MIPI_DSI_INT_ST0_DPHY_ERRORS_0_SHIFT) 1458 1459 /* 1460 * ACK_WITH_ERR_15 (R) 1461 * 1462 * retrives the DSI protocal violation from the acknowledge error report 1463 */ 1464 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR_15_MASK (0x8000U) 1465 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR_15_SHIFT (15U) 1466 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR_15_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR_15_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR_15_SHIFT) 1467 1468 /* 1469 * ACK_WITH_ERR_14 (R) 1470 * 1471 * retrives the reserved from the acknowledge error report 1472 */ 1473 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR_14_MASK (0x4000U) 1474 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR_14_SHIFT (14U) 1475 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR_14_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR_14_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR_14_SHIFT) 1476 1477 /* 1478 * ACK_WITH_ERR_13 (R) 1479 * 1480 * retrives the invalid transmission length from the acknowledge error report 1481 */ 1482 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR_13_MASK (0x2000U) 1483 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR_13_SHIFT (13U) 1484 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR_13_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR_13_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR_13_SHIFT) 1485 1486 /* 1487 * ACK_WITH_ERR_12 (R) 1488 * 1489 * retrieves the dsi vc id invalid from the acknowledge error report 1490 */ 1491 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR_12_MASK (0x1000U) 1492 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR_12_SHIFT (12U) 1493 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR_12_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR_12_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR_12_SHIFT) 1494 1495 /* 1496 * ACK_WITH_ERR_11 (R) 1497 * 1498 * retrives the not recongnized dsi data type from the acknowledge error report 1499 */ 1500 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR_11_MASK (0x800U) 1501 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR_11_SHIFT (11U) 1502 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR_11_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR_11_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR_11_SHIFT) 1503 1504 /* 1505 * ACK_WITH_ERR_10 (R) 1506 * 1507 * retrives the checksum error from the acknowledge error report 1508 */ 1509 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR_10_MASK (0x400U) 1510 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR_10_SHIFT (10U) 1511 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR_10_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR_10_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR_10_SHIFT) 1512 1513 /* 1514 * ACK_WITH_ERR_9 (R) 1515 * 1516 * retrives the ECC error multi-bit from the acknowledge error report 1517 */ 1518 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR_9_MASK (0x200U) 1519 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR_9_SHIFT (9U) 1520 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR_9_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR_9_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR_9_SHIFT) 1521 1522 /* 1523 * ACK_WITH_ERR8 (R) 1524 * 1525 * retrives the ecc error sigle-bit from the acknowledge error report 1526 */ 1527 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR8_MASK (0x100U) 1528 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR8_SHIFT (8U) 1529 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR8_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR8_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR8_SHIFT) 1530 1531 /* 1532 * ACK_WITH_ERR7 (R) 1533 * 1534 * retrieves the reserved from the acknowledge error report 1535 */ 1536 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR7_MASK (0x80U) 1537 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR7_SHIFT (7U) 1538 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR7_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR7_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR7_SHIFT) 1539 1540 /* 1541 * ACK_WITH_ERR6 (R) 1542 * 1543 * retrieves the false control error fro the acknowledge error report 1544 */ 1545 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR6_MASK (0x40U) 1546 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR6_SHIFT (6U) 1547 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR6_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR6_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR6_SHIFT) 1548 1549 /* 1550 * ACK_WITH_ERR5 (R) 1551 * 1552 * retrives the peripheral timeout error from the acknowledge error report 1553 */ 1554 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR5_MASK (0x20U) 1555 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR5_SHIFT (5U) 1556 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR5_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR5_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR5_SHIFT) 1557 1558 /* 1559 * ACK_WITH_ERR4 (R) 1560 * 1561 * retrives the LP transmit sync error from the acknowledge error report 1562 */ 1563 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR4_MASK (0x10U) 1564 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR4_SHIFT (4U) 1565 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR4_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR4_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR4_SHIFT) 1566 1567 /* 1568 * ACK_WITH_ERR3 (R) 1569 * 1570 * retrives the Escap mode entry command error from the acknowledge error report 1571 */ 1572 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR3_MASK (0x8U) 1573 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR3_SHIFT (3U) 1574 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR3_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR3_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR3_SHIFT) 1575 1576 /* 1577 * ACK_WITH_ERR2 (R) 1578 * 1579 * retrives the EoT sync error from the acknowledge error report 1580 */ 1581 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR2_MASK (0x4U) 1582 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR2_SHIFT (2U) 1583 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR2_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR2_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR2_SHIFT) 1584 1585 /* 1586 * ACK_WITH_ERR1 (R) 1587 * 1588 * retrives the SoT sync error from the acknowledge error report 1589 */ 1590 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR1_MASK (0x2U) 1591 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR1_SHIFT (1U) 1592 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR1_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR1_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR1_SHIFT) 1593 1594 /* 1595 * ACK_WITH_ERR0 (R) 1596 * 1597 * retrives the SoT serror from the acknowledge error report 1598 */ 1599 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR0_MASK (0x1U) 1600 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR0_SHIFT (0U) 1601 #define MIPI_DSI_INT_ST0_ACK_WITH_ERR0_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR0_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR0_SHIFT) 1602 1603 /* Bitfield definition for register: INT_ST1 */ 1604 /* 1605 * TEAR_REQUEST_ERR (R) 1606 * 1607 * indicates tear_request has occurred but tear effect is not active in dsi host and device 1608 */ 1609 #define MIPI_DSI_INT_ST1_TEAR_REQUEST_ERR_MASK (0x100000UL) 1610 #define MIPI_DSI_INT_ST1_TEAR_REQUEST_ERR_SHIFT (20U) 1611 #define MIPI_DSI_INT_ST1_TEAR_REQUEST_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_TEAR_REQUEST_ERR_MASK) >> MIPI_DSI_INT_ST1_TEAR_REQUEST_ERR_SHIFT) 1612 1613 /* 1614 * DPI_BUFF_PLD_UNDER (R) 1615 * 1616 * indicates an underflow when reading payload to build dsi packet for video mode 1617 */ 1618 #define MIPI_DSI_INT_ST1_DPI_BUFF_PLD_UNDER_MASK (0x80000UL) 1619 #define MIPI_DSI_INT_ST1_DPI_BUFF_PLD_UNDER_SHIFT (19U) 1620 #define MIPI_DSI_INT_ST1_DPI_BUFF_PLD_UNDER_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_DPI_BUFF_PLD_UNDER_MASK) >> MIPI_DSI_INT_ST1_DPI_BUFF_PLD_UNDER_SHIFT) 1621 1622 /* 1623 * GEN_PLD_RECEV_ERR (R) 1624 * 1625 * indicates that during a generic interface packet read back, the payload FIFO full 1626 */ 1627 #define MIPI_DSI_INT_ST1_GEN_PLD_RECEV_ERR_MASK (0x1000U) 1628 #define MIPI_DSI_INT_ST1_GEN_PLD_RECEV_ERR_SHIFT (12U) 1629 #define MIPI_DSI_INT_ST1_GEN_PLD_RECEV_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_GEN_PLD_RECEV_ERR_MASK) >> MIPI_DSI_INT_ST1_GEN_PLD_RECEV_ERR_SHIFT) 1630 1631 /* 1632 * GEN_PLD_RD_ERR (R) 1633 * 1634 * indicates that during a DCS read data, the payload FIFO becomes empty 1635 */ 1636 #define MIPI_DSI_INT_ST1_GEN_PLD_RD_ERR_MASK (0x800U) 1637 #define MIPI_DSI_INT_ST1_GEN_PLD_RD_ERR_SHIFT (11U) 1638 #define MIPI_DSI_INT_ST1_GEN_PLD_RD_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_GEN_PLD_RD_ERR_MASK) >> MIPI_DSI_INT_ST1_GEN_PLD_RD_ERR_SHIFT) 1639 1640 /* 1641 * GEN_PLD_SEND_ERR (R) 1642 * 1643 * indicates the payload FIFO become empty when packet build 1644 */ 1645 #define MIPI_DSI_INT_ST1_GEN_PLD_SEND_ERR_MASK (0x400U) 1646 #define MIPI_DSI_INT_ST1_GEN_PLD_SEND_ERR_SHIFT (10U) 1647 #define MIPI_DSI_INT_ST1_GEN_PLD_SEND_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_GEN_PLD_SEND_ERR_MASK) >> MIPI_DSI_INT_ST1_GEN_PLD_SEND_ERR_SHIFT) 1648 1649 /* 1650 * GEN_PLD_WR_ERR (R) 1651 * 1652 * indicates the system tried to write a payload and FIFO is full 1653 */ 1654 #define MIPI_DSI_INT_ST1_GEN_PLD_WR_ERR_MASK (0x200U) 1655 #define MIPI_DSI_INT_ST1_GEN_PLD_WR_ERR_SHIFT (9U) 1656 #define MIPI_DSI_INT_ST1_GEN_PLD_WR_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_GEN_PLD_WR_ERR_MASK) >> MIPI_DSI_INT_ST1_GEN_PLD_WR_ERR_SHIFT) 1657 1658 /* 1659 * GEN_CMD_WR_ERR (R) 1660 * 1661 * indicates the system tried to write a command and FIFO is full 1662 */ 1663 #define MIPI_DSI_INT_ST1_GEN_CMD_WR_ERR_MASK (0x100U) 1664 #define MIPI_DSI_INT_ST1_GEN_CMD_WR_ERR_SHIFT (8U) 1665 #define MIPI_DSI_INT_ST1_GEN_CMD_WR_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_GEN_CMD_WR_ERR_MASK) >> MIPI_DSI_INT_ST1_GEN_CMD_WR_ERR_SHIFT) 1666 1667 /* 1668 * DPI_BPLD_WR_ERR (R) 1669 * 1670 * indicates the payload FIFO is full during a DPI pixel line storage 1671 */ 1672 #define MIPI_DSI_INT_ST1_DPI_BPLD_WR_ERR_MASK (0x80U) 1673 #define MIPI_DSI_INT_ST1_DPI_BPLD_WR_ERR_SHIFT (7U) 1674 #define MIPI_DSI_INT_ST1_DPI_BPLD_WR_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_DPI_BPLD_WR_ERR_MASK) >> MIPI_DSI_INT_ST1_DPI_BPLD_WR_ERR_SHIFT) 1675 1676 /* 1677 * EOPT_ERR (R) 1678 * 1679 * indicates that the EoTp packet has not been received at the end of the incoming peripheral transmission 1680 */ 1681 #define MIPI_DSI_INT_ST1_EOPT_ERR_MASK (0x40U) 1682 #define MIPI_DSI_INT_ST1_EOPT_ERR_SHIFT (6U) 1683 #define MIPI_DSI_INT_ST1_EOPT_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_EOPT_ERR_MASK) >> MIPI_DSI_INT_ST1_EOPT_ERR_SHIFT) 1684 1685 /* 1686 * PKT_SIZE_ERR (R) 1687 * 1688 * indicates that the packet size error has been detected during the packet reception 1689 */ 1690 #define MIPI_DSI_INT_ST1_PKT_SIZE_ERR_MASK (0x20U) 1691 #define MIPI_DSI_INT_ST1_PKT_SIZE_ERR_SHIFT (5U) 1692 #define MIPI_DSI_INT_ST1_PKT_SIZE_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_PKT_SIZE_ERR_MASK) >> MIPI_DSI_INT_ST1_PKT_SIZE_ERR_SHIFT) 1693 1694 /* 1695 * CRC_ERR (R) 1696 * 1697 * indicates that the CRC error has been detected in the reveived packet payload 1698 */ 1699 #define MIPI_DSI_INT_ST1_CRC_ERR_MASK (0x10U) 1700 #define MIPI_DSI_INT_ST1_CRC_ERR_SHIFT (4U) 1701 #define MIPI_DSI_INT_ST1_CRC_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_CRC_ERR_MASK) >> MIPI_DSI_INT_ST1_CRC_ERR_SHIFT) 1702 1703 /* 1704 * ECC_MULTI_ERR (R) 1705 * 1706 * indicates that the ECC multiple error has been detected in a revieved packet 1707 */ 1708 #define MIPI_DSI_INT_ST1_ECC_MULTI_ERR_MASK (0x8U) 1709 #define MIPI_DSI_INT_ST1_ECC_MULTI_ERR_SHIFT (3U) 1710 #define MIPI_DSI_INT_ST1_ECC_MULTI_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_ECC_MULTI_ERR_MASK) >> MIPI_DSI_INT_ST1_ECC_MULTI_ERR_SHIFT) 1711 1712 /* 1713 * ECC_SIGLE_ERR (R) 1714 * 1715 * indicates that the ECC single error has been detected and corrected in a reveived packet 1716 */ 1717 #define MIPI_DSI_INT_ST1_ECC_SIGLE_ERR_MASK (0x4U) 1718 #define MIPI_DSI_INT_ST1_ECC_SIGLE_ERR_SHIFT (2U) 1719 #define MIPI_DSI_INT_ST1_ECC_SIGLE_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_ECC_SIGLE_ERR_MASK) >> MIPI_DSI_INT_ST1_ECC_SIGLE_ERR_SHIFT) 1720 1721 /* 1722 * TO_LP_TX (R) 1723 * 1724 * indicates that the low-power reception timeout counter reached the end and contention has been detected 1725 */ 1726 #define MIPI_DSI_INT_ST1_TO_LP_TX_MASK (0x2U) 1727 #define MIPI_DSI_INT_ST1_TO_LP_TX_SHIFT (1U) 1728 #define MIPI_DSI_INT_ST1_TO_LP_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_TO_LP_TX_MASK) >> MIPI_DSI_INT_ST1_TO_LP_TX_SHIFT) 1729 1730 /* 1731 * TO_HS_TX (R) 1732 * 1733 * indicates that the high-speed transmission timeout counter reached the end and contention has been detected 1734 */ 1735 #define MIPI_DSI_INT_ST1_TO_HS_TX_MASK (0x1U) 1736 #define MIPI_DSI_INT_ST1_TO_HS_TX_SHIFT (0U) 1737 #define MIPI_DSI_INT_ST1_TO_HS_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_TO_HS_TX_MASK) >> MIPI_DSI_INT_ST1_TO_HS_TX_SHIFT) 1738 1739 /* Bitfield definition for register: INT_MSK0 */ 1740 /* 1741 * MASK_DPHY_ERRORS_4 (RW) 1742 * 1743 * disable LP1 contention error ErrContentionLP1 from lane0 1744 */ 1745 #define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_MASK (0x100000UL) 1746 #define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_SHIFT (20U) 1747 #define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_SHIFT) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_MASK) 1748 #define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_MASK) >> MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_SHIFT) 1749 1750 /* 1751 * MASK_DPHY_ERRORS_3 (RW) 1752 * 1753 * disable LP0 contention error ErrContentionLP0 from lane0 1754 */ 1755 #define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_MASK (0x80000UL) 1756 #define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_SHIFT (19U) 1757 #define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_SHIFT) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_MASK) 1758 #define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_MASK) >> MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_SHIFT) 1759 1760 /* 1761 * MASK_DPHY_ERRORS_2 (RW) 1762 * 1763 * disable control error ErrControl from lane0 1764 */ 1765 #define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_MASK (0x40000UL) 1766 #define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_SHIFT (18U) 1767 #define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_SHIFT) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_MASK) 1768 #define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_MASK) >> MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_SHIFT) 1769 1770 /* 1771 * MASK_DPHY_ERRORS_1 (RW) 1772 * 1773 * disable ErrSyncEsc low-power data transmission synchronization error from lane 0 1774 */ 1775 #define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_MASK (0x20000UL) 1776 #define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_SHIFT (17U) 1777 #define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_SHIFT) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_MASK) 1778 #define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_MASK) >> MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_SHIFT) 1779 1780 /* 1781 * MASK_DPHY_ERRORS_0 (RW) 1782 * 1783 * disable ErrEsc escape entry error from lane0 1784 */ 1785 #define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_MASK (0x10000UL) 1786 #define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_SHIFT (16U) 1787 #define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_SHIFT) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_MASK) 1788 #define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_MASK) >> MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_SHIFT) 1789 1790 /* 1791 * MASK_ACK_WITH_ERR_15 (RW) 1792 * 1793 * disable the DSI protocal violation from the acknowledge error report 1794 */ 1795 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_MASK (0x8000U) 1796 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_SHIFT (15U) 1797 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_MASK) 1798 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_SHIFT) 1799 1800 /* 1801 * MASK_ACK_WITH_ERR_14 (RW) 1802 * 1803 * disable the reserved from the acknowledge error report 1804 */ 1805 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_MASK (0x4000U) 1806 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_SHIFT (14U) 1807 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_MASK) 1808 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_SHIFT) 1809 1810 /* 1811 * MASK_ACK_WITH_ERR_13 (RW) 1812 * 1813 * disable the invalid transmission length from the acknowledge error report 1814 */ 1815 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_MASK (0x2000U) 1816 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_SHIFT (13U) 1817 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_MASK) 1818 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_SHIFT) 1819 1820 /* 1821 * MASK_ACK_WITH_ERR_12 (RW) 1822 * 1823 * disable the dsi vc id invalid from the acknowledge error report 1824 */ 1825 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_MASK (0x1000U) 1826 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_SHIFT (12U) 1827 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_MASK) 1828 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_SHIFT) 1829 1830 /* 1831 * MASK_ACK_WITH_ERR_11 (RW) 1832 * 1833 * disable the not recongnized dsi data type from the acknowledge error report 1834 */ 1835 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_MASK (0x800U) 1836 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_SHIFT (11U) 1837 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_MASK) 1838 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_SHIFT) 1839 1840 /* 1841 * MASK_ACK_WITH_ERR_10 (RW) 1842 * 1843 * disable the checksum error from the acknowledge error report 1844 */ 1845 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_MASK (0x400U) 1846 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_SHIFT (10U) 1847 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_MASK) 1848 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_SHIFT) 1849 1850 /* 1851 * MASK_ACK_WITH_ERR_9 (RW) 1852 * 1853 * disable the ECC error multi-bit from the acknowledge error report 1854 */ 1855 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_MASK (0x200U) 1856 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_SHIFT (9U) 1857 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_MASK) 1858 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_SHIFT) 1859 1860 /* 1861 * MASK_ACK_WITH_ERR8 (RW) 1862 * 1863 * disable the ecc error sigle-bit from the acknowledge error report 1864 */ 1865 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_MASK (0x100U) 1866 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_SHIFT (8U) 1867 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_MASK) 1868 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_SHIFT) 1869 1870 /* 1871 * MASK_ACK_WITH_ERR7 (RW) 1872 * 1873 * disable the reserved from the acknowledge error report 1874 */ 1875 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_MASK (0x80U) 1876 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_SHIFT (7U) 1877 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_MASK) 1878 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_SHIFT) 1879 1880 /* 1881 * MASK_ACK_WITH_ERR6 (RW) 1882 * 1883 * disable the false control error fro the acknowledge error report 1884 */ 1885 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_MASK (0x40U) 1886 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_SHIFT (6U) 1887 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_MASK) 1888 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_SHIFT) 1889 1890 /* 1891 * MASK_ACK_WITH_ERR5 (RW) 1892 * 1893 * disable the peripheral timeout error from the acknowledge error report 1894 */ 1895 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_MASK (0x20U) 1896 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_SHIFT (5U) 1897 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_MASK) 1898 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_SHIFT) 1899 1900 /* 1901 * MASK_ACK_WITH_ERR4 (RW) 1902 * 1903 * disable the LP transmit sync error from the acknowledge error report 1904 */ 1905 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_MASK (0x10U) 1906 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_SHIFT (4U) 1907 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_MASK) 1908 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_SHIFT) 1909 1910 /* 1911 * MASK_ACK_WITH_ERR3 (RW) 1912 * 1913 * disable the Escap mode entry command error from the acknowledge error report 1914 */ 1915 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_MASK (0x8U) 1916 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_SHIFT (3U) 1917 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_MASK) 1918 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_SHIFT) 1919 1920 /* 1921 * MASK_ACK_WITH_ERR2 (RW) 1922 * 1923 * disable the EoT sync error from the acknowledge error report 1924 */ 1925 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_MASK (0x4U) 1926 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_SHIFT (2U) 1927 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_MASK) 1928 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_SHIFT) 1929 1930 /* 1931 * MASK_ACK_WITH_ERR1 (RW) 1932 * 1933 * disable the SoT sync error from the acknowledge error report 1934 */ 1935 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_MASK (0x2U) 1936 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_SHIFT (1U) 1937 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_MASK) 1938 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_SHIFT) 1939 1940 /* 1941 * MASK_ACK_WITH_ERR0 (RW) 1942 * 1943 * disable the SoT serror from the acknowledge error report 1944 */ 1945 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_MASK (0x1U) 1946 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_SHIFT (0U) 1947 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_MASK) 1948 #define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_SHIFT) 1949 1950 /* Bitfield definition for register: INT_MSK1 */ 1951 /* 1952 * MASK_TEAR_REQUEST_ERR (RW) 1953 * 1954 * disable tear_request has occurred but tear effect is not active in dsi host and device 1955 */ 1956 #define MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_MASK (0x100000UL) 1957 #define MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_SHIFT (20U) 1958 #define MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_MASK) 1959 #define MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_SHIFT) 1960 1961 /* 1962 * MASK_DPI_BUFF_PLD_UNDER (RW) 1963 * 1964 * disable an underflow when reading payload to build dsi packet for video mode 1965 */ 1966 #define MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_MASK (0x80000UL) 1967 #define MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_SHIFT (19U) 1968 #define MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_SHIFT) & MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_MASK) 1969 #define MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_MASK) >> MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_SHIFT) 1970 1971 /* 1972 * MASK_GEN_PLD_RECEV_ERR (RW) 1973 * 1974 * disable that during a generic interface packet read back, the payload FIFO full 1975 */ 1976 #define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_MASK (0x1000U) 1977 #define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_SHIFT (12U) 1978 #define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_MASK) 1979 #define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_SHIFT) 1980 1981 /* 1982 * MASK_GEN_PLD_RD_ERR (RW) 1983 * 1984 * disable that during a DCS read data, the payload FIFO becomes empty 1985 */ 1986 #define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_MASK (0x800U) 1987 #define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_SHIFT (11U) 1988 #define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_MASK) 1989 #define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_SHIFT) 1990 1991 /* 1992 * MASK_GEN_PLD_SEND_ERR (RW) 1993 * 1994 * disable the payload FIFO become empty when packet build 1995 */ 1996 #define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_MASK (0x400U) 1997 #define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_SHIFT (10U) 1998 #define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_MASK) 1999 #define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_SHIFT) 2000 2001 /* 2002 * MASK_GEN_PLD_WR_ERR (RW) 2003 * 2004 * disable the system tried to write a payload and FIFO is full 2005 */ 2006 #define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_MASK (0x200U) 2007 #define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_SHIFT (9U) 2008 #define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_MASK) 2009 #define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_SHIFT) 2010 2011 /* 2012 * MASK_GEN_CMD_WR_ERR (RW) 2013 * 2014 * disable the system tried to write a command and FIFO is full 2015 */ 2016 #define MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_MASK (0x100U) 2017 #define MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_SHIFT (8U) 2018 #define MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_MASK) 2019 #define MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_SHIFT) 2020 2021 /* 2022 * MASK_DPI_BPLD_WR_ERR (RW) 2023 * 2024 * disable the payload FIFO is full during a DPI pixel line storage 2025 */ 2026 #define MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_MASK (0x80U) 2027 #define MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_SHIFT (7U) 2028 #define MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_MASK) 2029 #define MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_SHIFT) 2030 2031 /* 2032 * MASK_EOPT_ERR (RW) 2033 * 2034 * disable that the EoTp packet has not been received at the end of the incoming peripheral transmission 2035 */ 2036 #define MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_MASK (0x40U) 2037 #define MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_SHIFT (6U) 2038 #define MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_MASK) 2039 #define MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_SHIFT) 2040 2041 /* 2042 * MASK_PKT_SIZE_ERR (RW) 2043 * 2044 * disable that the packet size error has been detected during the packet reception 2045 */ 2046 #define MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_MASK (0x20U) 2047 #define MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_SHIFT (5U) 2048 #define MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_MASK) 2049 #define MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_SHIFT) 2050 2051 /* 2052 * MASK_CRC_ERR (RW) 2053 * 2054 * disable that the CRC error has been detected in the reveived packet payload 2055 */ 2056 #define MIPI_DSI_INT_MSK1_MASK_CRC_ERR_MASK (0x10U) 2057 #define MIPI_DSI_INT_MSK1_MASK_CRC_ERR_SHIFT (4U) 2058 #define MIPI_DSI_INT_MSK1_MASK_CRC_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_CRC_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_CRC_ERR_MASK) 2059 #define MIPI_DSI_INT_MSK1_MASK_CRC_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_CRC_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_CRC_ERR_SHIFT) 2060 2061 /* 2062 * MASK_ECC_MULTI_ERR (RW) 2063 * 2064 * disable that the ECC multiple error has been detected in a revieved packet 2065 */ 2066 #define MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_MASK (0x8U) 2067 #define MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_SHIFT (3U) 2068 #define MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_MASK) 2069 #define MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_SHIFT) 2070 2071 /* 2072 * MASK_ECC_SIGLE_ERR (RW) 2073 * 2074 * disable that the ECC single error has been detected and corrected in a reveived packet 2075 */ 2076 #define MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_MASK (0x4U) 2077 #define MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_SHIFT (2U) 2078 #define MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_MASK) 2079 #define MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_SHIFT) 2080 2081 /* 2082 * MASK_TO_LP_TX (RW) 2083 * 2084 * disable that the low-power reception timeout counter reached the end and contention has been detected 2085 */ 2086 #define MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_MASK (0x2U) 2087 #define MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_SHIFT (1U) 2088 #define MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_SHIFT) & MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_MASK) 2089 #define MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_MASK) >> MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_SHIFT) 2090 2091 /* 2092 * MASK_TO_HS_TX (RW) 2093 * 2094 * disable that the high-speed transmission timeout counter reached the end and contention has been detected 2095 */ 2096 #define MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_MASK (0x1U) 2097 #define MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_SHIFT (0U) 2098 #define MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_SHIFT) & MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_MASK) 2099 #define MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_MASK) >> MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_SHIFT) 2100 2101 /* Bitfield definition for register: PHY_CAL */ 2102 /* 2103 * TXSKEWCALHS (RW) 2104 * 2105 * High-speed skew calibration is started when txskewcalhs is 2106 * set high (assuming that PHY is in Stop state) 2107 */ 2108 #define MIPI_DSI_PHY_CAL_TXSKEWCALHS_MASK (0x1U) 2109 #define MIPI_DSI_PHY_CAL_TXSKEWCALHS_SHIFT (0U) 2110 #define MIPI_DSI_PHY_CAL_TXSKEWCALHS_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CAL_TXSKEWCALHS_SHIFT) & MIPI_DSI_PHY_CAL_TXSKEWCALHS_MASK) 2111 #define MIPI_DSI_PHY_CAL_TXSKEWCALHS_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CAL_TXSKEWCALHS_MASK) >> MIPI_DSI_PHY_CAL_TXSKEWCALHS_SHIFT) 2112 2113 /* Bitfield definition for register: INT_FORCE0 */ 2114 /* 2115 * FORCE_DPHY_ERRORS_4 (RW) 2116 * 2117 * force LP1 contention error ErrContentionLP1 from lane0 2118 */ 2119 #define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_MASK (0x100000UL) 2120 #define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_SHIFT (20U) 2121 #define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_MASK) 2122 #define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_SHIFT) 2123 2124 /* 2125 * FORCE_DPHY_ERRORS_3 (RW) 2126 * 2127 * force LP0 contention error ErrContentionLP0 from lane0 2128 */ 2129 #define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_MASK (0x80000UL) 2130 #define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_SHIFT (19U) 2131 #define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_MASK) 2132 #define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_SHIFT) 2133 2134 /* 2135 * FORCE_DPHY_ERRORS_2 (RW) 2136 * 2137 * force control error ErrControl from lane0 2138 */ 2139 #define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_MASK (0x40000UL) 2140 #define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_SHIFT (18U) 2141 #define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_MASK) 2142 #define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_SHIFT) 2143 2144 /* 2145 * FORCE_DPHY_ERRORS_1 (RW) 2146 * 2147 * force ErrSyncEsc low-power data transmission synchronization error from lane 0 2148 */ 2149 #define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_MASK (0x20000UL) 2150 #define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_SHIFT (17U) 2151 #define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_MASK) 2152 #define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_SHIFT) 2153 2154 /* 2155 * FORCE_DPHY_ERRORS_0 (RW) 2156 * 2157 * force ErrEsc escape entry error from lane0 2158 */ 2159 #define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_MASK (0x10000UL) 2160 #define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_SHIFT (16U) 2161 #define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_MASK) 2162 #define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_SHIFT) 2163 2164 /* 2165 * FORCE_ACK_WITH_ERR_15 (RW) 2166 * 2167 * force the DSI protocal violation from the acknowledge error report 2168 */ 2169 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_MASK (0x8000U) 2170 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_SHIFT (15U) 2171 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_MASK) 2172 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_SHIFT) 2173 2174 /* 2175 * FORCE_ACK_WITH_ERR_14 (RW) 2176 * 2177 * force the reserved from the acknowledge error report 2178 */ 2179 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_MASK (0x4000U) 2180 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_SHIFT (14U) 2181 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_MASK) 2182 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_SHIFT) 2183 2184 /* 2185 * FORCE_ACK_WITH_ERR_13 (RW) 2186 * 2187 * force the invalid transmission length from the acknowledge error report 2188 */ 2189 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_MASK (0x2000U) 2190 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_SHIFT (13U) 2191 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_MASK) 2192 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_SHIFT) 2193 2194 /* 2195 * FORCE_ACK_WITH_ERR_12 (RW) 2196 * 2197 * force the dsi vc id invalid from the acknowledge error report 2198 */ 2199 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_MASK (0x1000U) 2200 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_SHIFT (12U) 2201 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_MASK) 2202 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_SHIFT) 2203 2204 /* 2205 * FORCE_ACK_WITH_ERR_11 (RW) 2206 * 2207 * force the not recongnized dsi data type from the acknowledge error report 2208 */ 2209 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_MASK (0x800U) 2210 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_SHIFT (11U) 2211 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_MASK) 2212 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_SHIFT) 2213 2214 /* 2215 * FORCE_ACK_WITH_ERR_10 (RW) 2216 * 2217 * force the checksum error from the acknowledge error report 2218 */ 2219 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_MASK (0x400U) 2220 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_SHIFT (10U) 2221 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_MASK) 2222 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_SHIFT) 2223 2224 /* 2225 * FORCE_ACK_WITH_ERR_9 (RW) 2226 * 2227 * force the ECC error multi-bit from the acknowledge error report 2228 */ 2229 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_MASK (0x200U) 2230 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_SHIFT (9U) 2231 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_MASK) 2232 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_SHIFT) 2233 2234 /* 2235 * FORCE_ACK_WITH_ERR8 (RW) 2236 * 2237 * force the ecc error sigle-bit from the acknowledge error report 2238 */ 2239 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_MASK (0x100U) 2240 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_SHIFT (8U) 2241 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_MASK) 2242 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_SHIFT) 2243 2244 /* 2245 * FORCE_ACK_WITH_ERR7 (RW) 2246 * 2247 * force the reserved from the acknowledge error report 2248 */ 2249 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_MASK (0x80U) 2250 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_SHIFT (7U) 2251 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_MASK) 2252 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_SHIFT) 2253 2254 /* 2255 * FORCE_ACK_WITH_ERR6 (RW) 2256 * 2257 * force the false control error fro the acknowledge error report 2258 */ 2259 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_MASK (0x40U) 2260 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_SHIFT (6U) 2261 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_MASK) 2262 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_SHIFT) 2263 2264 /* 2265 * FORCE_ACK_WITH_ERR5 (RW) 2266 * 2267 * force the peripheral timeout error from the acknowledge error report 2268 */ 2269 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_MASK (0x20U) 2270 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_SHIFT (5U) 2271 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_MASK) 2272 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_SHIFT) 2273 2274 /* 2275 * FORCE_ACK_WITH_ERR4 (RW) 2276 * 2277 * force the LP transmit sync error from the acknowledge error report 2278 */ 2279 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_MASK (0x10U) 2280 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_SHIFT (4U) 2281 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_MASK) 2282 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_SHIFT) 2283 2284 /* 2285 * FORCE_ACK_WITH_ERR3 (RW) 2286 * 2287 * force the Escap mode entry command error from the acknowledge error report 2288 */ 2289 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_MASK (0x8U) 2290 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_SHIFT (3U) 2291 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_MASK) 2292 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_SHIFT) 2293 2294 /* 2295 * FORCE_ACK_WITH_ERR2 (RW) 2296 * 2297 * force the EoT sync error from the acknowledge error report 2298 */ 2299 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_MASK (0x4U) 2300 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_SHIFT (2U) 2301 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_MASK) 2302 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_SHIFT) 2303 2304 /* 2305 * FORCE_ACK_WITH_ERR1 (RW) 2306 * 2307 * force the SoT sync error from the acknowledge error report 2308 */ 2309 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_MASK (0x2U) 2310 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_SHIFT (1U) 2311 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_MASK) 2312 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_SHIFT) 2313 2314 /* 2315 * FORCE_ACK_WITH_ERR0 (RW) 2316 * 2317 * force the SoT serror from the acknowledge error report 2318 */ 2319 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_MASK (0x1U) 2320 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_SHIFT (0U) 2321 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_MASK) 2322 #define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_SHIFT) 2323 2324 /* Bitfield definition for register: INT_FORCE1 */ 2325 /* 2326 * FORCE_TEAR_REQUEST_ERR (RW) 2327 * 2328 * force tear_request has occurred but tear effect is not active in dsi host and device 2329 */ 2330 #define MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_MASK (0x100000UL) 2331 #define MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_SHIFT (20U) 2332 #define MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_MASK) 2333 #define MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_SHIFT) 2334 2335 /* 2336 * FORCE_DPI_BUFF_PLD_UNDER (RW) 2337 * 2338 * force an underflow when reading payload to build dsi packet for video mode 2339 */ 2340 #define MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_MASK (0x80000UL) 2341 #define MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_SHIFT (19U) 2342 #define MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_MASK) 2343 #define MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_SHIFT) 2344 2345 /* 2346 * FORCE_GEN_PLD_RECEV_ERR (RW) 2347 * 2348 * force that during a generic interface packet read back, the payload FIFO full 2349 */ 2350 #define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_MASK (0x1000U) 2351 #define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_SHIFT (12U) 2352 #define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_MASK) 2353 #define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_SHIFT) 2354 2355 /* 2356 * FORCE_GEN_PLD_RD_ERR (RW) 2357 * 2358 * force that during a DCS read data, the payload FIFO becomes empty 2359 */ 2360 #define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_MASK (0x800U) 2361 #define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_SHIFT (11U) 2362 #define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_MASK) 2363 #define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_SHIFT) 2364 2365 /* 2366 * FORCE_GEN_PLD_SEND_ERR (RW) 2367 * 2368 * force the payload FIFO become empty when packet build 2369 */ 2370 #define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_MASK (0x400U) 2371 #define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_SHIFT (10U) 2372 #define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_MASK) 2373 #define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_SHIFT) 2374 2375 /* 2376 * FORCE_GEN_PLD_WR_ERR (RW) 2377 * 2378 * force the system tried to write a payload and FIFO is full 2379 */ 2380 #define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_MASK (0x200U) 2381 #define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_SHIFT (9U) 2382 #define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_MASK) 2383 #define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_SHIFT) 2384 2385 /* 2386 * FORCE_GEN_CMD_WR_ERR (RW) 2387 * 2388 * force the system tried to write a command and FIFO is full 2389 */ 2390 #define MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_MASK (0x100U) 2391 #define MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_SHIFT (8U) 2392 #define MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_MASK) 2393 #define MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_SHIFT) 2394 2395 /* 2396 * FORCE_DPI_BPLD_WR_ERR (RW) 2397 * 2398 * force the payload FIFO is full during a DPI pixel line storage 2399 */ 2400 #define MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_MASK (0x80U) 2401 #define MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_SHIFT (7U) 2402 #define MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_MASK) 2403 #define MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_SHIFT) 2404 2405 /* 2406 * FORCE_EOPT_ERR (RW) 2407 * 2408 * force that the EoTp packet has not been received at the end of the incoming peripheral transmission 2409 */ 2410 #define MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_MASK (0x40U) 2411 #define MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_SHIFT (6U) 2412 #define MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_MASK) 2413 #define MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_SHIFT) 2414 2415 /* 2416 * FORCE_PKT_SIZE_ERR (RW) 2417 * 2418 * force that the packet size error has been detected during the packet reception 2419 */ 2420 #define MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_MASK (0x20U) 2421 #define MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_SHIFT (5U) 2422 #define MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_MASK) 2423 #define MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_SHIFT) 2424 2425 /* 2426 * FORCE_CRC_ERR (RW) 2427 * 2428 * force that the CRC error has been detected in the reveived packet payload 2429 */ 2430 #define MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_MASK (0x10U) 2431 #define MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_SHIFT (4U) 2432 #define MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_MASK) 2433 #define MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_SHIFT) 2434 2435 /* 2436 * FORCE_ECC_MULTI_ERR (RW) 2437 * 2438 * force that the ECC multiple error has been detected in a revieved packet 2439 */ 2440 #define MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_MASK (0x8U) 2441 #define MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_SHIFT (3U) 2442 #define MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_MASK) 2443 #define MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_SHIFT) 2444 2445 /* 2446 * FORCE_ECC_SIGLE_ERR (RW) 2447 * 2448 * force that the ECC single error has been detected and corrected in a reveived packet 2449 */ 2450 #define MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_MASK (0x4U) 2451 #define MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_SHIFT (2U) 2452 #define MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_MASK) 2453 #define MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_SHIFT) 2454 2455 /* 2456 * FORCE_TO_LP_TX (RW) 2457 * 2458 * force that the low-power reception timeout counter reached the end and contention has been detected 2459 */ 2460 #define MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_MASK (0x2U) 2461 #define MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_SHIFT (1U) 2462 #define MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_MASK) 2463 #define MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_SHIFT) 2464 2465 /* 2466 * FORCE_TO_HS_TX (RW) 2467 * 2468 * force that the high-speed transmission timeout counter reached the end and contention has been detected 2469 */ 2470 #define MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_MASK (0x1U) 2471 #define MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_SHIFT (0U) 2472 #define MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_MASK) 2473 #define MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_SHIFT) 2474 2475 /* Bitfield definition for register: PHY_TMR_RD */ 2476 /* 2477 * MAX_RD_TIME (RW) 2478 * 2479 * the maximum time required to perform a read command in lane byte clock cycles. 2480 */ 2481 #define MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_MASK (0x7FFFU) 2482 #define MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_SHIFT (0U) 2483 #define MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_SHIFT) & MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_MASK) 2484 #define MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_MASK) >> MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_SHIFT) 2485 2486 /* Bitfield definition for register: AUTO_ULPS_MIN_TIME */ 2487 /* 2488 * ULPS_MIN_TIME (RW) 2489 * 2490 * configures the minimum time required by phy between ulpsactivenot and ulpsexitreq for clock and data lane 2491 */ 2492 #define MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_MASK (0xFFFU) 2493 #define MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_SHIFT (0U) 2494 #define MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_SHIFT) & MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_MASK) 2495 #define MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_MASK) >> MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_SHIFT) 2496 2497 /* Bitfield definition for register: PHY_MODE */ 2498 /* 2499 * PHY_MODE (RW) 2500 * 2501 * sel DPHY or CPHY 2502 */ 2503 #define MIPI_DSI_PHY_MODE_PHY_MODE_MASK (0x1U) 2504 #define MIPI_DSI_PHY_MODE_PHY_MODE_SHIFT (0U) 2505 #define MIPI_DSI_PHY_MODE_PHY_MODE_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_MODE_PHY_MODE_SHIFT) & MIPI_DSI_PHY_MODE_PHY_MODE_MASK) 2506 #define MIPI_DSI_PHY_MODE_PHY_MODE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_MODE_PHY_MODE_MASK) >> MIPI_DSI_PHY_MODE_PHY_MODE_SHIFT) 2507 2508 /* Bitfield definition for register: VID_SHADOW_CTRL */ 2509 /* 2510 * VID_SHADOW_PIN_REQ (RW) 2511 * 2512 * when set to 1, the video request is done by external pin 2513 */ 2514 #define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_MASK (0x10000UL) 2515 #define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_SHIFT (16U) 2516 #define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_SHIFT) & MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_MASK) 2517 #define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_MASK) >> MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_SHIFT) 2518 2519 /* 2520 * VID_SHADOW_REQ (RW) 2521 * 2522 * when set to 1, request that the dpi register from regbank are copied to the auxiliary registers 2523 */ 2524 #define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_MASK (0x100U) 2525 #define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_SHIFT (8U) 2526 #define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_SHIFT) & MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_MASK) 2527 #define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_MASK) >> MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_SHIFT) 2528 2529 /* 2530 * VID_SHADOW_EN (RW) 2531 * 2532 * when set to 1, DPI receives the active configuration from the auxiliary register 2533 */ 2534 #define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_MASK (0x1U) 2535 #define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_SHIFT (0U) 2536 #define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_SHIFT) & MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_MASK) 2537 #define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_MASK) >> MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_SHIFT) 2538 2539 /* Bitfield definition for register: DPI_VCID_ACT */ 2540 /* 2541 * DPI_VCID (R) 2542 * 2543 * specifies the DPI virtual channel id that is indexed to the video mode packets 2544 */ 2545 #define MIPI_DSI_DPI_VCID_ACT_DPI_VCID_MASK (0x3U) 2546 #define MIPI_DSI_DPI_VCID_ACT_DPI_VCID_SHIFT (0U) 2547 #define MIPI_DSI_DPI_VCID_ACT_DPI_VCID_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_VCID_ACT_DPI_VCID_MASK) >> MIPI_DSI_DPI_VCID_ACT_DPI_VCID_SHIFT) 2548 2549 /* Bitfield definition for register: DPI_COLOR_CODING_ACT */ 2550 /* 2551 * LOOSELY18_EN (R) 2552 * 2553 * avtivates loosely packed variant to 18-bit configuration 2554 */ 2555 #define MIPI_DSI_DPI_COLOR_CODING_ACT_LOOSELY18_EN_MASK (0x100U) 2556 #define MIPI_DSI_DPI_COLOR_CODING_ACT_LOOSELY18_EN_SHIFT (8U) 2557 #define MIPI_DSI_DPI_COLOR_CODING_ACT_LOOSELY18_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_COLOR_CODING_ACT_LOOSELY18_EN_MASK) >> MIPI_DSI_DPI_COLOR_CODING_ACT_LOOSELY18_EN_SHIFT) 2558 2559 /* 2560 * DIP_COLOR_CODING (R) 2561 * 2562 * configures the DPI color for video mode 2563 */ 2564 #define MIPI_DSI_DPI_COLOR_CODING_ACT_DIP_COLOR_CODING_MASK (0xFU) 2565 #define MIPI_DSI_DPI_COLOR_CODING_ACT_DIP_COLOR_CODING_SHIFT (0U) 2566 #define MIPI_DSI_DPI_COLOR_CODING_ACT_DIP_COLOR_CODING_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_COLOR_CODING_ACT_DIP_COLOR_CODING_MASK) >> MIPI_DSI_DPI_COLOR_CODING_ACT_DIP_COLOR_CODING_SHIFT) 2567 2568 /* Bitfield definition for register: DPI_LP_CMD_TIM_ACT */ 2569 /* 2570 * OUTVACT_LPCMD_TIME (R) 2571 * 2572 * transmission of commands in low-power mode, it specifies the size in bytes of the lagest packet that can fit in a line during the VSA VBP and VFP regions. 2573 */ 2574 #define MIPI_DSI_DPI_LP_CMD_TIM_ACT_OUTVACT_LPCMD_TIME_MASK (0xFF0000UL) 2575 #define MIPI_DSI_DPI_LP_CMD_TIM_ACT_OUTVACT_LPCMD_TIME_SHIFT (16U) 2576 #define MIPI_DSI_DPI_LP_CMD_TIM_ACT_OUTVACT_LPCMD_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_LP_CMD_TIM_ACT_OUTVACT_LPCMD_TIME_MASK) >> MIPI_DSI_DPI_LP_CMD_TIM_ACT_OUTVACT_LPCMD_TIME_SHIFT) 2577 2578 /* 2579 * INVACT_LPCMD_TIME (R) 2580 * 2581 * transmission of commands in low-power mode, it specifies the size in bytes of the lagest packet that can fit in a line during the vact regions. 2582 */ 2583 #define MIPI_DSI_DPI_LP_CMD_TIM_ACT_INVACT_LPCMD_TIME_MASK (0xFFU) 2584 #define MIPI_DSI_DPI_LP_CMD_TIM_ACT_INVACT_LPCMD_TIME_SHIFT (0U) 2585 #define MIPI_DSI_DPI_LP_CMD_TIM_ACT_INVACT_LPCMD_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_LP_CMD_TIM_ACT_INVACT_LPCMD_TIME_MASK) >> MIPI_DSI_DPI_LP_CMD_TIM_ACT_INVACT_LPCMD_TIME_SHIFT) 2586 2587 /* Bitfield definition for register: VID_MODE_CFG_ACT */ 2588 /* 2589 * LP_CMD_EN (R) 2590 * 2591 * enable the command transmission only in low-power mode 2592 */ 2593 #define MIPI_DSI_VID_MODE_CFG_ACT_LP_CMD_EN_MASK (0x200U) 2594 #define MIPI_DSI_VID_MODE_CFG_ACT_LP_CMD_EN_SHIFT (9U) 2595 #define MIPI_DSI_VID_MODE_CFG_ACT_LP_CMD_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_LP_CMD_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_LP_CMD_EN_SHIFT) 2596 2597 /* 2598 * FRAME_BTA_ACK_EN (R) 2599 * 2600 * enable the request for an acknowledge response at the end of a frame 2601 */ 2602 #define MIPI_DSI_VID_MODE_CFG_ACT_FRAME_BTA_ACK_EN_MASK (0x100U) 2603 #define MIPI_DSI_VID_MODE_CFG_ACT_FRAME_BTA_ACK_EN_SHIFT (8U) 2604 #define MIPI_DSI_VID_MODE_CFG_ACT_FRAME_BTA_ACK_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_FRAME_BTA_ACK_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_FRAME_BTA_ACK_EN_SHIFT) 2605 2606 /* 2607 * LP_HFP_EN (R) 2608 * 2609 * enable the returne to low-power inside the HFP period when timing allows 2610 */ 2611 #define MIPI_DSI_VID_MODE_CFG_ACT_LP_HFP_EN_MASK (0x80U) 2612 #define MIPI_DSI_VID_MODE_CFG_ACT_LP_HFP_EN_SHIFT (7U) 2613 #define MIPI_DSI_VID_MODE_CFG_ACT_LP_HFP_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_LP_HFP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_LP_HFP_EN_SHIFT) 2614 2615 /* 2616 * LP_HBP_EN (R) 2617 * 2618 * enable the returne to low-power inside the HBP period when timing allows 2619 */ 2620 #define MIPI_DSI_VID_MODE_CFG_ACT_LP_HBP_EN_MASK (0x40U) 2621 #define MIPI_DSI_VID_MODE_CFG_ACT_LP_HBP_EN_SHIFT (6U) 2622 #define MIPI_DSI_VID_MODE_CFG_ACT_LP_HBP_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_LP_HBP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_LP_HBP_EN_SHIFT) 2623 2624 /* 2625 * LP_VACT_EN (R) 2626 * 2627 * enable the returne to low-power inside the VACT period when timing allows 2628 */ 2629 #define MIPI_DSI_VID_MODE_CFG_ACT_LP_VACT_EN_MASK (0x20U) 2630 #define MIPI_DSI_VID_MODE_CFG_ACT_LP_VACT_EN_SHIFT (5U) 2631 #define MIPI_DSI_VID_MODE_CFG_ACT_LP_VACT_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_LP_VACT_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_LP_VACT_EN_SHIFT) 2632 2633 /* 2634 * LP_VFP_EN (R) 2635 * 2636 * enable the returne to low-power inside the VFP period when timing allows 2637 */ 2638 #define MIPI_DSI_VID_MODE_CFG_ACT_LP_VFP_EN_MASK (0x10U) 2639 #define MIPI_DSI_VID_MODE_CFG_ACT_LP_VFP_EN_SHIFT (4U) 2640 #define MIPI_DSI_VID_MODE_CFG_ACT_LP_VFP_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_LP_VFP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_LP_VFP_EN_SHIFT) 2641 2642 /* 2643 * LP_VBP_EN (R) 2644 * 2645 * enable the returne to low-power inside the VBP period when timing allows 2646 */ 2647 #define MIPI_DSI_VID_MODE_CFG_ACT_LP_VBP_EN_MASK (0x8U) 2648 #define MIPI_DSI_VID_MODE_CFG_ACT_LP_VBP_EN_SHIFT (3U) 2649 #define MIPI_DSI_VID_MODE_CFG_ACT_LP_VBP_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_LP_VBP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_LP_VBP_EN_SHIFT) 2650 2651 /* 2652 * LP_VSA_EN (R) 2653 * 2654 * enable the returne to low-power inside the VSA period when timing allows 2655 */ 2656 #define MIPI_DSI_VID_MODE_CFG_ACT_LP_VSA_EN_MASK (0x4U) 2657 #define MIPI_DSI_VID_MODE_CFG_ACT_LP_VSA_EN_SHIFT (2U) 2658 #define MIPI_DSI_VID_MODE_CFG_ACT_LP_VSA_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_LP_VSA_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_LP_VSA_EN_SHIFT) 2659 2660 /* 2661 * VID_MODE_TYPE (R) 2662 * 2663 * specifies the video mode transmission type 2664 */ 2665 #define MIPI_DSI_VID_MODE_CFG_ACT_VID_MODE_TYPE_MASK (0x3U) 2666 #define MIPI_DSI_VID_MODE_CFG_ACT_VID_MODE_TYPE_SHIFT (0U) 2667 #define MIPI_DSI_VID_MODE_CFG_ACT_VID_MODE_TYPE_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_VID_MODE_TYPE_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_VID_MODE_TYPE_SHIFT) 2668 2669 /* Bitfield definition for register: VID_PKT_SIZE_ACT */ 2670 /* 2671 * VID_PKT_SIZE (R) 2672 * 2673 * the number of pixels in a single video packet 2674 */ 2675 #define MIPI_DSI_VID_PKT_SIZE_ACT_VID_PKT_SIZE_MASK (0x3FFFU) 2676 #define MIPI_DSI_VID_PKT_SIZE_ACT_VID_PKT_SIZE_SHIFT (0U) 2677 #define MIPI_DSI_VID_PKT_SIZE_ACT_VID_PKT_SIZE_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_PKT_SIZE_ACT_VID_PKT_SIZE_MASK) >> MIPI_DSI_VID_PKT_SIZE_ACT_VID_PKT_SIZE_SHIFT) 2678 2679 /* Bitfield definition for register: VID_NUM_CHUNKS_ACT */ 2680 /* 2681 * VID_NUM_CHUNKS (R) 2682 * 2683 * the number of chunks to be transmitted during a line period 2684 */ 2685 #define MIPI_DSI_VID_NUM_CHUNKS_ACT_VID_NUM_CHUNKS_MASK (0x1FFFU) 2686 #define MIPI_DSI_VID_NUM_CHUNKS_ACT_VID_NUM_CHUNKS_SHIFT (0U) 2687 #define MIPI_DSI_VID_NUM_CHUNKS_ACT_VID_NUM_CHUNKS_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_NUM_CHUNKS_ACT_VID_NUM_CHUNKS_MASK) >> MIPI_DSI_VID_NUM_CHUNKS_ACT_VID_NUM_CHUNKS_SHIFT) 2688 2689 /* Bitfield definition for register: VID_NULL_SIZE_ACT */ 2690 /* 2691 * VID_NULL_SIZE (R) 2692 * 2693 * the number of bytes in side a null packet 2694 */ 2695 #define MIPI_DSI_VID_NULL_SIZE_ACT_VID_NULL_SIZE_MASK (0x1FFFU) 2696 #define MIPI_DSI_VID_NULL_SIZE_ACT_VID_NULL_SIZE_SHIFT (0U) 2697 #define MIPI_DSI_VID_NULL_SIZE_ACT_VID_NULL_SIZE_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_NULL_SIZE_ACT_VID_NULL_SIZE_MASK) >> MIPI_DSI_VID_NULL_SIZE_ACT_VID_NULL_SIZE_SHIFT) 2698 2699 /* Bitfield definition for register: VID_HSA_TIME_ACT */ 2700 /* 2701 * VID_HSA_TIME (R) 2702 * 2703 * the horizontal synchronism active period in lane byte clock cycles 2704 */ 2705 #define MIPI_DSI_VID_HSA_TIME_ACT_VID_HSA_TIME_MASK (0xFFFU) 2706 #define MIPI_DSI_VID_HSA_TIME_ACT_VID_HSA_TIME_SHIFT (0U) 2707 #define MIPI_DSI_VID_HSA_TIME_ACT_VID_HSA_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_HSA_TIME_ACT_VID_HSA_TIME_MASK) >> MIPI_DSI_VID_HSA_TIME_ACT_VID_HSA_TIME_SHIFT) 2708 2709 /* Bitfield definition for register: VID_HBP_TIME_ACT */ 2710 /* 2711 * VID_HBP_TIME (R) 2712 * 2713 * the horizontal back porch period in lane byte clock cycles 2714 */ 2715 #define MIPI_DSI_VID_HBP_TIME_ACT_VID_HBP_TIME_MASK (0xFFFU) 2716 #define MIPI_DSI_VID_HBP_TIME_ACT_VID_HBP_TIME_SHIFT (0U) 2717 #define MIPI_DSI_VID_HBP_TIME_ACT_VID_HBP_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_HBP_TIME_ACT_VID_HBP_TIME_MASK) >> MIPI_DSI_VID_HBP_TIME_ACT_VID_HBP_TIME_SHIFT) 2718 2719 /* Bitfield definition for register: VID_HLINE_TIME_ACT */ 2720 /* 2721 * VID_HLINE_TIME (R) 2722 * 2723 * the size of total line: hsa+hbp+hact+hfp 2724 */ 2725 #define MIPI_DSI_VID_HLINE_TIME_ACT_VID_HLINE_TIME_MASK (0x7FFFU) 2726 #define MIPI_DSI_VID_HLINE_TIME_ACT_VID_HLINE_TIME_SHIFT (0U) 2727 #define MIPI_DSI_VID_HLINE_TIME_ACT_VID_HLINE_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_HLINE_TIME_ACT_VID_HLINE_TIME_MASK) >> MIPI_DSI_VID_HLINE_TIME_ACT_VID_HLINE_TIME_SHIFT) 2728 2729 /* Bitfield definition for register: VID_VSA_LINES_ACT */ 2730 /* 2731 * VSA_LINES (R) 2732 * 2733 * vertical synchronism active period 2734 */ 2735 #define MIPI_DSI_VID_VSA_LINES_ACT_VSA_LINES_MASK (0x3FFU) 2736 #define MIPI_DSI_VID_VSA_LINES_ACT_VSA_LINES_SHIFT (0U) 2737 #define MIPI_DSI_VID_VSA_LINES_ACT_VSA_LINES_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_VSA_LINES_ACT_VSA_LINES_MASK) >> MIPI_DSI_VID_VSA_LINES_ACT_VSA_LINES_SHIFT) 2738 2739 /* Bitfield definition for register: VID_VBP_LINES_ACT */ 2740 /* 2741 * VBP_LINES (R) 2742 * 2743 * vertical back porch period 2744 */ 2745 #define MIPI_DSI_VID_VBP_LINES_ACT_VBP_LINES_MASK (0x3FFU) 2746 #define MIPI_DSI_VID_VBP_LINES_ACT_VBP_LINES_SHIFT (0U) 2747 #define MIPI_DSI_VID_VBP_LINES_ACT_VBP_LINES_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_VBP_LINES_ACT_VBP_LINES_MASK) >> MIPI_DSI_VID_VBP_LINES_ACT_VBP_LINES_SHIFT) 2748 2749 /* Bitfield definition for register: VID_VFP_LINES_ACT */ 2750 /* 2751 * VFP_LINES (R) 2752 * 2753 * vertical porch period 2754 */ 2755 #define MIPI_DSI_VID_VFP_LINES_ACT_VFP_LINES_MASK (0x3FFU) 2756 #define MIPI_DSI_VID_VFP_LINES_ACT_VFP_LINES_SHIFT (0U) 2757 #define MIPI_DSI_VID_VFP_LINES_ACT_VFP_LINES_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_VFP_LINES_ACT_VFP_LINES_MASK) >> MIPI_DSI_VID_VFP_LINES_ACT_VFP_LINES_SHIFT) 2758 2759 /* Bitfield definition for register: VID_VACTIVE_LINES_ACT */ 2760 /* 2761 * V_ACTIVE_LINES (R) 2762 * 2763 * vertical active period 2764 */ 2765 #define MIPI_DSI_VID_VACTIVE_LINES_ACT_V_ACTIVE_LINES_MASK (0x3FFFU) 2766 #define MIPI_DSI_VID_VACTIVE_LINES_ACT_V_ACTIVE_LINES_SHIFT (0U) 2767 #define MIPI_DSI_VID_VACTIVE_LINES_ACT_V_ACTIVE_LINES_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_VACTIVE_LINES_ACT_V_ACTIVE_LINES_MASK) >> MIPI_DSI_VID_VACTIVE_LINES_ACT_V_ACTIVE_LINES_SHIFT) 2768 2769 /* Bitfield definition for register: VID_PKT_STATUS */ 2770 /* 2771 * DPI_BUFF_PLD_FULL (R) 2772 * 2773 * This bit indicates the full status of the payload internal buffer 2774 * for video Mode. This bit is set to 0 for command Mode 2775 */ 2776 #define MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_FULL_MASK (0x20000UL) 2777 #define MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_FULL_SHIFT (17U) 2778 #define MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_FULL_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_FULL_MASK) >> MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_FULL_SHIFT) 2779 2780 /* 2781 * DPI_BUFF_PLD_EMPTY (R) 2782 * 2783 * This bit indicates the empty status of the payload internal 2784 * buffer for video Mode. This bit is set to 0 for command Mod 2785 */ 2786 #define MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_EMPTY_MASK (0x10000UL) 2787 #define MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_EMPTY_SHIFT (16U) 2788 #define MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_EMPTY_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_EMPTY_MASK) >> MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_EMPTY_SHIFT) 2789 2790 /* 2791 * DPI_PLD_W_FULL (R) 2792 * 2793 * This bit indicates the full status of write payload FIFO for 2794 * video Mode. This bit is set to 0 for command Mode 2795 */ 2796 #define MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_FULL_MASK (0x8U) 2797 #define MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_FULL_SHIFT (3U) 2798 #define MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_FULL_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_FULL_MASK) >> MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_FULL_SHIFT) 2799 2800 /* 2801 * DPI_PLD_W_EMPTY (R) 2802 * 2803 * This bit indicates the empty status of write payload FIFO for 2804 * video Mode. This bit is set to 0 for command Mode 2805 */ 2806 #define MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_EMPTY_MASK (0x4U) 2807 #define MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_EMPTY_SHIFT (2U) 2808 #define MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_EMPTY_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_EMPTY_MASK) >> MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_EMPTY_SHIFT) 2809 2810 /* 2811 * DPI_CMD_W_FULL (R) 2812 * 2813 * This bit indicates the full status of write command FIFO for 2814 * video Mode. This bit is set to 0 for command Mode 2815 */ 2816 #define MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_FULL_MASK (0x2U) 2817 #define MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_FULL_SHIFT (1U) 2818 #define MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_FULL_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_FULL_MASK) >> MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_FULL_SHIFT) 2819 2820 /* 2821 * DPI_CMD_W_EMPTY (R) 2822 * 2823 * This bit indicates the empty status of write command FIFO 2824 * for video Mode. This bit is set to 0 for command Mode 2825 */ 2826 #define MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_EMPTY_MASK (0x1U) 2827 #define MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_EMPTY_SHIFT (0U) 2828 #define MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_EMPTY_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_EMPTY_MASK) >> MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_EMPTY_SHIFT) 2829 2830 /* Bitfield definition for register: SDF_3D_ACT */ 2831 /* 2832 * SEND_3D_CFG (R) 2833 * 2834 * When set, causes the next VSS packet to include 3D control 2835 * payload in every VSS packet. 2836 */ 2837 #define MIPI_DSI_SDF_3D_ACT_SEND_3D_CFG_MASK (0x10000UL) 2838 #define MIPI_DSI_SDF_3D_ACT_SEND_3D_CFG_SHIFT (16U) 2839 #define MIPI_DSI_SDF_3D_ACT_SEND_3D_CFG_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_ACT_SEND_3D_CFG_MASK) >> MIPI_DSI_SDF_3D_ACT_SEND_3D_CFG_SHIFT) 2840 2841 /* 2842 * RIGHT_FIRST (R) 2843 * 2844 * This bit specifies the left/right order 2845 */ 2846 #define MIPI_DSI_SDF_3D_ACT_RIGHT_FIRST_MASK (0x20U) 2847 #define MIPI_DSI_SDF_3D_ACT_RIGHT_FIRST_SHIFT (5U) 2848 #define MIPI_DSI_SDF_3D_ACT_RIGHT_FIRST_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_ACT_RIGHT_FIRST_MASK) >> MIPI_DSI_SDF_3D_ACT_RIGHT_FIRST_SHIFT) 2849 2850 /* 2851 * SECOND_VSYNC (R) 2852 * 2853 * This field specifies whether there is a second VSYNC pulse 2854 * between Left and Right Images, when 3D Image Format is 2855 * Frame-based 2856 */ 2857 #define MIPI_DSI_SDF_3D_ACT_SECOND_VSYNC_MASK (0x10U) 2858 #define MIPI_DSI_SDF_3D_ACT_SECOND_VSYNC_SHIFT (4U) 2859 #define MIPI_DSI_SDF_3D_ACT_SECOND_VSYNC_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_ACT_SECOND_VSYNC_MASK) >> MIPI_DSI_SDF_3D_ACT_SECOND_VSYNC_SHIFT) 2860 2861 /* 2862 * FORMAT_3D (R) 2863 * 2864 * This field specifies 3D Image Format 2865 */ 2866 #define MIPI_DSI_SDF_3D_ACT_FORMAT_3D_MASK (0xCU) 2867 #define MIPI_DSI_SDF_3D_ACT_FORMAT_3D_SHIFT (2U) 2868 #define MIPI_DSI_SDF_3D_ACT_FORMAT_3D_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_ACT_FORMAT_3D_MASK) >> MIPI_DSI_SDF_3D_ACT_FORMAT_3D_SHIFT) 2869 2870 /* 2871 * MODE_3D (R) 2872 * 2873 * This field specifies 3D Mode On/Off and Display Orientation 2874 */ 2875 #define MIPI_DSI_SDF_3D_ACT_MODE_3D_MASK (0x3U) 2876 #define MIPI_DSI_SDF_3D_ACT_MODE_3D_SHIFT (0U) 2877 #define MIPI_DSI_SDF_3D_ACT_MODE_3D_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_ACT_MODE_3D_MASK) >> MIPI_DSI_SDF_3D_ACT_MODE_3D_SHIFT) 2878 2879 2880 2881 2882 #endif /* HPM_MIPI_DSI_H */ 2883