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Searched defs:ICSR (Results 1 – 23 of 23) sorted by relevance

/device/soc/bestechnic/bes2600/liteos_m/sdk/bsp/platform/cmsis/inc/
Dcore_cm0.h344 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
Dcore_cm1.h344 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
Dcore_cm0plus.h358 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
Dcore_sc000.h355 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
Dcore_cm3.h382 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
Dcore_armv8mbl.h386 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
Dcore_sc300.h382 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
Dcore_cm23.h386 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
Dcore_cm4.h452 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
Dcore_cm7.h463 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
Dcore_armv8mml.h507 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
Dcore_cm33.h513 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
Dcore_cm35p.h507 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
Dcore_cm55.h519 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
Dcore_armv81mml.h514 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
/device/soc/chipsea/cst85/liteos_m/sdk/bsp/driver/dma/
Dreg_dma.h34 __IO uint32_t ICSR; /* 0x00C (R/W) : Int Ctrl & St Reg */ member
/device/qemu/SmartL_E802/liteos_m/board/hals/csky_driver/include/
Dcore_802.h421 …__IOM uint32_t ICSR[4U]; /*!< Offset: 0x1c0 (R/W) Security interrupt clear register… member
/device/soc/winnermicro/wm800/board/include/arch/xt804/csi_core/
Dcore_804.h430 …__IOM uint32_t ICSR[4U]; /* !< Offset: 0x1c0 (R/W) Security interrupt clear registe… member
/device/soc/bestechnic/bes2600/liteos_m/sdk/bsp/platform/hal/
Dhal_trace.c194 uint32_t ICSR; member
/device/soc/st/stm32f4xx/sdk/Drivers/CMSIS/Include/
Dcore_cm4.h443 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
/device/soc/chipsea/cst85/liteos_m/sdk/bsp/arch/cmsis/
Dcore_cm4.h443 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
/device/soc/asrmicro/asr582x/liteos_m/sdk/drivers/platform/CMSIS/Include/
Dcore_cm4.h439 …__IOM uint32_t ICSR; /* !< Offset: 0x004 (R/W) Interrupt Control and State Regi… member
/device/soc/st/common/platform/stm32mp1xx_hal/STM32MP1xx_HAL_Driver/Inc/
Dstm32mp157axx_ca7.h1971 …__IO uint32_t ICSR; /*!< RTC initialization control and status register, Addr… member