1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_dma.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of DMA LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_DMA DMA
47 * @brief DMA LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_LL_DMA_H__
53 #define __GR55xx_LL_DMA_H__
54
55 /* Includes ------------------------------------------------------------------*/
56 #include "gr55xx.h"
57
58 #ifdef __cplusplus
59 extern "C" {
60 #endif
61
62 #if defined (DMA)
63
64 /** @defgroup DMA_LL_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup DMA_LL_ES_INIT DMA Exported init structures
70 * @{
71 */
72
73 /**
74 * @brief LL DMA init Structure definition
75 */
76 typedef struct _ll_dma_init {
77 uint32_t src_address; /**< Specifies the Source base address for DMA transfer.
78 This parameter must be a value between Min_Data = 0
79 and Max_Data = 0xFFFFFFFF. */
80
81 uint32_t dst_address; /**< Specifies the Destination base address for DMA transfer.
82 This parameter must be a value between Min_Data = 0
83 and Max_Data = 0xFFFFFFFF. */
84
85 uint32_t direction; /**< Specifies if the data will be transferred from memory to peripheral,
86 from memory to memory or from peripheral to memory or
87 form peripheral to peripheral.
88 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
89 This feature can be modified afterwards using unitary function
90 @ref ll_dma_set_data_transfer_direction(). */
91
92 uint32_t mode; /**< Specifies the Single block or Multi-block operation mode.
93 This parameter can be a value of @ref DMA_LL_EC_MODE
94 @note: The circular buffer mode cannot be used if the memory to memory
95 data transfer direction is configured on the selected Channel
96 This feature can be modified afterwards using unitary function
97 @ref ll_dma_set_mode(). */
98
99 uint32_t src_increment_mode; /**< Specifies whether the Source address is incremented or decrement or not.
100 This parameter can be a value of @ref DMA_LL_EC_SOURCE
101 This feature can be modified afterwards using unitary function
102 @ref ll_dma_set_source_increment_mode(). */
103
104 uint32_t dst_increment_mode; /**< Specifies whether the Destination address is incremented or decrement or not.
105 This parameter can be a value of @ref DMA_LL_EC_DESTINATION
106 This feature can be modified afterwards using unitary function
107 @ref ll_dma_set_destination_increment_mode(). */
108
109 uint32_t src_data_width; /**< Specifies the Souce transfer width alignment(byte, half word, word).
110 This parameter can be a value of @ref DMA_LL_EC_SDATAALIGN
111 This feature can be modified afterwards using unitary function
112 @ref ll_dma_set_source_width(). */
113
114 uint32_t dst_data_width; /**< Specifies the Destination transfer width alignment(byte, half word, word).
115 This parameter can be a value of @ref DMA_LL_EC_DDATAALIGN
116 This feature can be modified afterwards using unitary function
117 @ref ll_dma_set_destination_width(). */
118
119 uint32_t block_size; /**< Specifies the number of data to transfer, in data unit.
120 The data unit is equal to the source buffer configuration set
121 in src_data_width parameters.
122 This parameter must be a value between Min_Data = 0 and Max_Data = 0x1FF
123 This feature can be modified afterwards using unitary function
124 @ref ll_dma_set_block_size(). */
125
126 uint32_t src_peripheral; /**< Specifies the Source peripheral type.
127 This parameter can be a value of @ref DMA_LL_EC_PERIPH
128 This feature can be modified afterwards using unitary function
129 @ref ll_dma_set_source_peripheral(). */
130
131 uint32_t dst_peripheral; /**< Specifies the Destination peripheral type.
132 This parameter can be a value of @ref DMA_LL_EC_PERIPH
133 This feature can be modified afterwards using unitary function
134 @ref ll_dma_set_destination_peripheral(). */
135
136 uint32_t priority; /**< Specifies the channel priority level.
137 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
138 This feature can be modified afterwards using unitary function
139 @ref ll_dma_set_channel_priority_level(). */
140 } ll_dma_init_t;
141
142 /** @} */
143
144 /** @} */
145
146 /**
147 * @defgroup DMA_LL_MACRO Defines
148 * @{
149 */
150
151 /* Exported constants --------------------------------------------------------*/
152 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
153 * @{
154 */
155
156 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
157 * @{
158 */
159 #define LL_DMA_CHANNEL_0 ((uint32_t)0x00000000U) /**< DMA Channel 0 */
160 #define LL_DMA_CHANNEL_1 ((uint32_t)0x00000001U) /**< DMA Channel 1 */
161 #define LL_DMA_CHANNEL_2 ((uint32_t)0x00000002U) /**< DMA Channel 2 */
162 #define LL_DMA_CHANNEL_3 ((uint32_t)0x00000003U) /**< DMA Channel 3 */
163 #define LL_DMA_CHANNEL_4 ((uint32_t)0x00000004U) /**< DMA Channel 4 */
164 #define LL_DMA_CHANNEL_5 ((uint32_t)0x00000005U) /**< DMA Channel 5 */
165 #define LL_DMA_CHANNEL_6 ((uint32_t)0x00000006U) /**< DMA Channel 6 */
166 #define LL_DMA_CHANNEL_7 ((uint32_t)0x00000007U) /**< DMA Channel 7 */
167 #define LL_DMA_CHANNEL_ALL ((uint32_t)0xFFFF0000U) /**< DMA Channel all
168 (used only for function
169 @ref ll_dma_deinit()) */
170 /** @} */
171
172 /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
173 * @{
174 */
175 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CTLL_TT_FC_M2M /**< Memory to memory direction */
176 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CTLL_TT_FC_M2P /**< Memory to peripheral direction */
177 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY DMA_CTLL_TT_FC_P2M /**< Peripheral to memory direction */
178 #define LL_DMA_DIRECTION_PERIPH_TO_PERIPH DMA_CTLL_TT_FC_P2P /**< Peripheral to Peripheral direction */
179 /** @} */
180
181
182 /** @defgroup DMA_LL_EC_MODE Transfer mode
183 * @{
184 */
185 #define LL_DMA_MODE_SINGLE_BLOCK ((uint32_t)0x00000000U) /**< Single block */
186 #define LL_DMA_MODE_MULTI_BLOCK_SRC_RELOAD DMA_CFGL_RELOAD_SRC /**< Multi-block:
187 src addr reload,
188 dst addr contiguous */
189 #define LL_DMA_MODE_MULTI_BLOCK_DST_RELOAD DMA_CFGL_RELOAD_DST /**< Multi-block:
190 src addr contiguous,
191 dst addr reload */
192 #define LL_DMA_MODE_MULTI_BLOCK_ALL_RELOAD (DMA_CFGL_RELOAD_SRC | DMA_CFGL_RELOAD_DST) /**< Multi-block:
193 src addr reload,
194 dst addr reload */
195 /** @} */
196
197 /** @defgroup DMA_LL_EC_SOURCE Source increment mode
198 * @{
199 */
200 #define LL_DMA_SRC_INCREMENT DMA_CTLL_SINC_INC /**< Source Address increment */
201 #define LL_DMA_SRC_DECREMENT DMA_CTLL_SINC_DEC /**< Source Address decrement */
202 #define LL_DMA_SRC_NO_CHANGE DMA_CTLL_SINC_NO /**< Source Address no change */
203 /** @} */
204
205 /** @defgroup DMA_LL_EC_DESTINATION Destination increment mode
206 * @{
207 */
208 #define LL_DMA_DST_INCREMENT DMA_CTLL_DINC_INC /**< Destination Address increment */
209 #define LL_DMA_DST_DECREMENT DMA_CTLL_DINC_DEC /**< Destination Address decrement */
210 #define LL_DMA_DST_NO_CHANGE DMA_CTLL_DINC_NO /**< Destination Address no change */
211 /** @} */
212
213 /** @defgroup DMA_LL_EC_SRC_BURST Source burst transaction length
214 * @{
215 */
216 #define LL_DMA_SRC_BURST_LENGTH_1 DMA_CTLL_SRC_MSIZE_1 /**< Source Burst length: 1 word */
217 #define LL_DMA_SRC_BURST_LENGTH_4 DMA_CTLL_SRC_MSIZE_4 /**< Source Burst length: 4 words */
218 #define LL_DMA_SRC_BURST_LENGTH_8 DMA_CTLL_SRC_MSIZE_8 /**< Source Burst length: 8 words */
219 #define LL_DMA_SRC_BURST_LENGTH_16 DMA_CTLL_SRC_MSIZE_16 /**< Source Burst length: 16 words */
220 #define LL_DMA_SRC_BURST_LENGTH_32 DMA_CTLL_SRC_MSIZE_32 /**< Source Burst length: 32 words */
221 #define LL_DMA_SRC_BURST_LENGTH_64 DMA_CTLL_SRC_MSIZE_64 /**< Source Burst length: 64 words */
222 /** @} */
223
224 /** @defgroup DMA_LL_EC_DST_BURST Destination burst transaction length
225 * @{
226 */
227 #define LL_DMA_DST_BURST_LENGTH_1 DMA_CTLL_DST_MSIZE_1 /**< Destination Burst length: 1 word */
228 #define LL_DMA_DST_BURST_LENGTH_4 DMA_CTLL_DST_MSIZE_4 /**< Destination Burst length: 4 words */
229 #define LL_DMA_DST_BURST_LENGTH_8 DMA_CTLL_DST_MSIZE_8 /**< Destination Burst length: 8 words */
230 #define LL_DMA_DST_BURST_LENGTH_16 DMA_CTLL_DST_MSIZE_16 /**< Destination Burst length: 16 words */
231 #define LL_DMA_DST_BURST_LENGTH_32 DMA_CTLL_DST_MSIZE_32 /**< Destination Burst length: 32 words */
232 #define LL_DMA_DST_BURST_LENGTH_64 DMA_CTLL_DST_MSIZE_64 /**< Destination Burst length: 64 words */
233 /** @} */
234
235 /** @defgroup DMA_LL_EC_SDATAALIGN Source data alignment
236 * @{
237 */
238 #define LL_DMA_SDATAALIGN_BYTE DMA_CTLL_SRC_TR_WIDTH_8 /**< Source data alignment : Byte */
239 #define LL_DMA_SDATAALIGN_HALFWORD DMA_CTLL_SRC_TR_WIDTH_16 /**< Source data alignment : HalfWord */
240 #define LL_DMA_SDATAALIGN_WORD DMA_CTLL_SRC_TR_WIDTH_32 /**< Source data alignment : Word */
241 /** @} */
242
243 /** @defgroup DMA_LL_EC_DDATAALIGN Destination data alignment
244 * @{
245 */
246 #define LL_DMA_DDATAALIGN_BYTE DMA_CTLL_DST_TR_WIDTH_8 /**< Destination data alignment : Byte */
247 #define LL_DMA_DDATAALIGN_HALFWORD DMA_CTLL_DST_TR_WIDTH_16 /**< Destination data alignment : HalfWord */
248 #define LL_DMA_DDATAALIGN_WORD DMA_CTLL_DST_TR_WIDTH_32 /**< Destination data alignment : Word */
249 /** @} */
250
251 /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
252 * @{
253 */
254 #define LL_DMA_PRIORITY_0 DMA_CFGL_CH_PRIOR_0 /**< Priority level : 0 */
255 #define LL_DMA_PRIORITY_1 DMA_CFGL_CH_PRIOR_1 /**< Priority level : 1 */
256 #define LL_DMA_PRIORITY_2 DMA_CFGL_CH_PRIOR_2 /**< Priority level : 2 */
257 #define LL_DMA_PRIORITY_3 DMA_CFGL_CH_PRIOR_3 /**< Priority level : 3 */
258 #define LL_DMA_PRIORITY_4 DMA_CFGL_CH_PRIOR_4 /**< Priority level : 4 */
259 #define LL_DMA_PRIORITY_5 DMA_CFGL_CH_PRIOR_5 /**< Priority level : 5 */
260 #define LL_DMA_PRIORITY_6 DMA_CFGL_CH_PRIOR_6 /**< Priority level : 6 */
261 #define LL_DMA_PRIORITY_7 DMA_CFGL_CH_PRIOR_7 /**< Priority level : 7 */
262 /** @} */
263
264 /** @defgroup DMA_LL_EC_SHANDSHAKING Source handshake interface
265 * @{
266 */
267 #define LL_DMA_SHANDSHAKING_HW ((uint32_t)0x00000000U) /**< Source: hardware handshake */
268 #define LL_DMA_SHANDSHAKING_SW DMA_CFGL_HS_SEL_SRC /**< Source: software handshake */
269 /** @} */
270
271 /** @defgroup DMA_LL_EC_DHANDSHAKING Destination handshake interface
272 * @{
273 */
274 #define LL_DMA_DHANDSHAKING_HW ((uint32_t)0x00000000U) /**< Destination: hardware handshake */
275 #define LL_DMA_DHANDSHAKING_SW DMA_CFGL_HS_SEL_DST /**< Destination: software handshake */
276 /** @} */
277
278 /** @defgroup DMA_LL_EC_PERIPH DMA Peripheral type
279 * @{
280 */
281 #define LL_DMA_PERIPH_SPIM_TX ((uint32_t)0x00000000U) /**< DMA Peripheral type is SPIM TX */
282 #define LL_DMA_PERIPH_SPIM_RX ((uint32_t)0x00000001U) /**< DMA Peripheral type is SPIM RX */
283 #define LL_DMA_PERIPH_SPIS_TX ((uint32_t)0x00000002U) /**< DMA Peripheral type is SPIS TX */
284 #define LL_DMA_PERIPH_SPIS_RX ((uint32_t)0x00000003U) /**< DMA Peripheral type is SPIS RX */
285 #define LL_DMA_PERIPH_QSPI0_TX ((uint32_t)0x00000004U) /**< DMA Peripheral type is QSPI0 TX */
286 #define LL_DMA_PERIPH_QSPI0_RX ((uint32_t)0x00000005U) /**< DMA Peripheral type is QSPI0 RX */
287 #define LL_DMA_PERIPH_I2C0_TX ((uint32_t)0x00000006U) /**< DMA Peripheral type is I2C0 TX */
288 #define LL_DMA_PERIPH_I2C0_RX ((uint32_t)0x00000007U) /**< DMA Peripheral type is I2C0 RX */
289 #define LL_DMA_PERIPH_I2C1_TX ((uint32_t)0x00000008U) /**< DMA Peripheral type is I2C1 TX */
290 #define LL_DMA_PERIPH_I2C1_RX ((uint32_t)0x00000009U) /**< DMA Peripheral type is I2C1 RX */
291 #define LL_DMA_PERIPH_I2S_S_TX ((uint32_t)0x00000008U) /**< DMA Peripheral type is I2S_S TX */
292 #define LL_DMA_PERIPH_I2S_S_RX ((uint32_t)0x00000009U) /**< DMA Peripheral type is I2S_S RX */
293 #define LL_DMA_PERIPH_UART0_TX ((uint32_t)0x0000000AU) /**< DMA Peripheral type is UART0 TX */
294 #define LL_DMA_PERIPH_UART0_RX ((uint32_t)0x0000000BU) /**< DMA Peripheral type is UART0 RX */
295 #define LL_DMA_PERIPH_QSPI1_TX ((uint32_t)0x0000000CU) /**< DMA peripheral type is QSPI1 TX */
296 #define LL_DMA_PERIPH_QSPI1_RX ((uint32_t)0x0000000DU) /**< DMA peripheral type is QSPI1 RX */
297 #define LL_DMA_PERIPH_I2S_M_TX ((uint32_t)0x0000000CU) /**< DMA Peripheral type is I2S_M TX */
298 #define LL_DMA_PERIPH_I2S_M_RX ((uint32_t)0x0000000DU) /**< DMA Peripheral type is I2S_M RX */
299 #define LL_DMA_PERIPH_SNSADC ((uint32_t)0x0000000EU) /**< DMA peripheral type is SNSADC */
300 #define LL_DMA_PERIPH_MEM ((uint32_t)0x0000000FU) /**< DMA peripheral type is Memory */
301 /** @} */
302
303 /** @} */
304
305 /* Exported macro ------------------------------------------------------------*/
306 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
307 * @{
308 */
309
310 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers Macros
311 * @{
312 */
313
314 /**
315 * @brief Write a value in DMA register
316 * @param __instance__ DMA instance
317 * @param __REG__ Register to be written
318 * @param __VALUE__ Value to be written in the register
319 * @retval None
320 */
321 #define LL_DMA_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__.__REG__, (__VALUE__))
322
323 /**
324 * @brief Read a value in DMA register
325 * @param __instance__ DMA instance
326 * @param __REG__ Register to be read
327 * @retval Register value
328 */
329 #define LL_DMA_ReadReg(__instance__, __REG__) READ_REG(__instance__.__REG__)
330
331 /** @} */
332
333 /** @} */
334
335 /** @} */
336
337 /* Exported functions --------------------------------------------------------*/
338 /** @defgroup DMA_LL_DRIVER_FUNCTIONS Functions
339 * @{
340 */
341
342 /** @defgroup DMA_LL_EF_Configuration Configuration functions
343 * @{
344 */
345
346 /**
347 * @brief Enable DMA Module.
348 * @note This function is used to enable the DMA Module, which must be done before any
349 * channel is enabled.
350 *
351 * Register|BitsName
352 * --------|--------
353 * CFG_REG | CFG_EN
354 *
355 * @param DMAx DMA instance.
356 * @retval None
357 */
ll_dma_enable(dma_regs_t * DMAx)358 __STATIC_INLINE void ll_dma_enable(dma_regs_t *DMAx)
359 {
360 WRITE_REG(DMAx->MISCELLANEOU.CFG, DMA_MODULE_CFG_EN);
361 }
362
363 /**
364 * @brief Disable DMA Module.
365 * @note If the ll_dma_disable() function is called while any dma channel is still active,
366 * the ll_dma_is_enable() function still return 1 to indicate that there are channels
367 * still active until hardware has terminated all cativity on all channels, at which
368 * point the ll_dma_is_enable() function returns 0.
369 *
370 * Register|BitsName
371 * --------|--------
372 * CFG_REG | CFG_EN
373 *
374 * @param DMAx DMA instance.
375 * @retval None
376 */
ll_dma_disable(dma_regs_t * DMAx)377 __STATIC_INLINE void ll_dma_disable(dma_regs_t *DMAx)
378 {
379 WRITE_REG(DMAx->MISCELLANEOU.CFG, 0);
380 }
381
382 /**
383 * @brief Check if DMA Module is enabled or disabled.
384 *
385 * Register|BitsName
386 * --------|--------
387 * CFG_REG | CFG_EN
388 *
389 * @param DMAx DMA instance.
390 * @retval State of bit (1 or 0).
391 */
ll_dma_is_enable(dma_regs_t * DMAx)392 __STATIC_INLINE uint32_t ll_dma_is_enable(dma_regs_t *DMAx)
393 {
394 return (READ_BITS(DMAx->MISCELLANEOU.CFG, DMA_MODULE_CFG_EN) == DMA_MODULE_CFG_EN);
395 }
396
397 /**
398 * @brief Enable DMA channel.
399 * @note When the DMA Module is disabled, then call this function to DMA_CFG_REG register
400 * is ignored and call ll_dma_disable_channel() function will always returns 0.
401 *
402 * Register|BitsName
403 * --------|--------
404 * CH_EN_REG | CH_EN_WE&CH_EN
405 *
406 * @param DMAx DMA instance.
407 * @param channel This parameter can be one of the following values:
408 * @arg @ref LL_DMA_CHANNEL_0
409 * @arg @ref LL_DMA_CHANNEL_1
410 * @arg @ref LL_DMA_CHANNEL_2
411 * @arg @ref LL_DMA_CHANNEL_3
412 * @arg @ref LL_DMA_CHANNEL_4
413 * @arg @ref LL_DMA_CHANNEL_5
414 * @arg @ref LL_DMA_CHANNEL_6
415 * @arg @ref LL_DMA_CHANNEL_7
416 * @retval None
417 */
ll_dma_enable_channel(dma_regs_t * DMAx,uint32_t channel)418 __STATIC_INLINE void ll_dma_enable_channel(dma_regs_t *DMAx, uint32_t channel)
419 {
420 WRITE_REG(DMAx->MISCELLANEOU.CH_EN, (1 << (channel + DMA_CH_WE_EN_Pos)) + (1 << channel));
421 }
422
423 /**
424 * @brief Disable DMA channel.
425 *
426 * Register|BitsName
427 * --------|--------
428 * CH_EN_REG | CH_EN_WE&CH_EN
429 *
430 * @param DMAx DMA instance.
431 * @param channel This parameter can be one of the following values:
432 * @arg @ref LL_DMA_CHANNEL_0
433 * @arg @ref LL_DMA_CHANNEL_1
434 * @arg @ref LL_DMA_CHANNEL_2
435 * @arg @ref LL_DMA_CHANNEL_3
436 * @arg @ref LL_DMA_CHANNEL_4
437 * @arg @ref LL_DMA_CHANNEL_5
438 * @arg @ref LL_DMA_CHANNEL_6
439 * @arg @ref LL_DMA_CHANNEL_7
440 * @retval None
441 */
ll_dma_disable_channel(dma_regs_t * DMAx,uint32_t channel)442 __STATIC_INLINE void ll_dma_disable_channel(dma_regs_t *DMAx, uint32_t channel)
443 {
444 WRITE_REG(DMAx->MISCELLANEOU.CH_EN, (1 << (channel + DMA_CH_WE_EN_Pos)));
445 }
446
447 /**
448 * @brief Check if DMA channel is enabled or disabled.
449 * @note Software can therefore poll this function to determine when channel is free
450 * for a new DMA transfer.
451 *
452 * Register|BitsName
453 * --------|--------
454 * CH_EN_REG | CH_EN_WE&CH_EN
455 *
456 * @param DMAx DMA instance.
457 * @param channel This parameter can be one of the following values:
458 * @arg @ref LL_DMA_CHANNEL_0
459 * @arg @ref LL_DMA_CHANNEL_1
460 * @arg @ref LL_DMA_CHANNEL_2
461 * @arg @ref LL_DMA_CHANNEL_3
462 * @arg @ref LL_DMA_CHANNEL_4
463 * @arg @ref LL_DMA_CHANNEL_5
464 * @arg @ref LL_DMA_CHANNEL_6
465 * @arg @ref LL_DMA_CHANNEL_7
466 * @retval State of bit (1 or 0).
467 */
ll_dma_is_enabled_channel(dma_regs_t * DMAx,uint32_t channel)468 __STATIC_INLINE uint32_t ll_dma_is_enabled_channel(dma_regs_t *DMAx, uint32_t channel)
469 {
470 return READ_BITS(DMAx->MISCELLANEOU.CH_EN, (1 << channel)) ? 1 : 0;
471 }
472
473 /**
474 * @brief Suspend a DMA channel transfer.
475 * @note Suspends all DMA data transfers from the source until the ll_dma_resume_channel()
476 * function is called. The function may be called after enabling the DMA channel.
477 *
478 * Register|BitsName
479 * --------|--------
480 * CFGL | CH_SUSP
481 *
482 * @param DMAx DMA instance.
483 * @param channel This parameter can be one of the following values:
484 * @arg @ref LL_DMA_CHANNEL_0
485 * @arg @ref LL_DMA_CHANNEL_1
486 * @arg @ref LL_DMA_CHANNEL_2
487 * @arg @ref LL_DMA_CHANNEL_3
488 * @arg @ref LL_DMA_CHANNEL_4
489 * @arg @ref LL_DMA_CHANNEL_5
490 * @arg @ref LL_DMA_CHANNEL_6
491 * @arg @ref LL_DMA_CHANNEL_7
492 * @retval None
493 */
ll_dma_suspend_channel(dma_regs_t * DMAx,uint32_t channel)494 __STATIC_INLINE void ll_dma_suspend_channel(dma_regs_t *DMAx, uint32_t channel)
495 {
496 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_SUSP, DMA_CFGL_CH_SUSP);
497 }
498
499 /**
500 * @brief Resume a DMA channel.
501 * @note The function may be called after enabling the DMA channel.
502 *
503 * Register|BitsName
504 * --------|--------
505 * CFGL | CH_SUSP
506 *
507 * @param DMAx DMA instance.
508 * @param channel This parameter can be one of the following values:
509 * @arg @ref LL_DMA_CHANNEL_0
510 * @arg @ref LL_DMA_CHANNEL_1
511 * @arg @ref LL_DMA_CHANNEL_2
512 * @arg @ref LL_DMA_CHANNEL_3
513 * @arg @ref LL_DMA_CHANNEL_4
514 * @arg @ref LL_DMA_CHANNEL_5
515 * @arg @ref LL_DMA_CHANNEL_6
516 * @arg @ref LL_DMA_CHANNEL_7
517 * @retval None
518 */
ll_dma_resume_channel(dma_regs_t * DMAx,uint32_t channel)519 __STATIC_INLINE void ll_dma_resume_channel(dma_regs_t *DMAx, uint32_t channel)
520 {
521 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_SUSP, 0);
522 }
523
524 /**
525 * @brief Check if DMA channel is suspended or resumed.
526 *
527 * Register|BitsName
528 * --------|--------
529 * CFGL | CH_SUSP
530 *
531 * @param DMAx DMA instance.
532 * @param channel This parameter can be one of the following values:
533 * @arg @ref LL_DMA_CHANNEL_0
534 * @arg @ref LL_DMA_CHANNEL_1
535 * @arg @ref LL_DMA_CHANNEL_2
536 * @arg @ref LL_DMA_CHANNEL_3
537 * @arg @ref LL_DMA_CHANNEL_4
538 * @arg @ref LL_DMA_CHANNEL_5
539 * @arg @ref LL_DMA_CHANNEL_6
540 * @arg @ref LL_DMA_CHANNEL_7
541 * @retval State of bit (1 or 0).
542 */
ll_dma_is_suspended(dma_regs_t * DMAx,uint32_t channel)543 __STATIC_INLINE uint32_t ll_dma_is_suspended(dma_regs_t *DMAx, uint32_t channel)
544 {
545 return (READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_SUSP) == DMA_CFGL_CH_SUSP);
546 }
547
548 /**
549 * @brief Check if DMA channel FIFO is empty.
550 *
551 * Register|BitsName
552 * --------|--------
553 * CFGL | FIFO_EMPTY
554 *
555 * @param DMAx DMA instance.
556 * @param channel This parameter can be one of the following values:
557 * @arg @ref LL_DMA_CHANNEL_0
558 * @arg @ref LL_DMA_CHANNEL_1
559 * @arg @ref LL_DMA_CHANNEL_2
560 * @arg @ref LL_DMA_CHANNEL_3
561 * @arg @ref LL_DMA_CHANNEL_4
562 * @arg @ref LL_DMA_CHANNEL_5
563 * @arg @ref LL_DMA_CHANNEL_6
564 * @arg @ref LL_DMA_CHANNEL_7
565 * @retval State of bit (1 or 0).
566 */
ll_dma_is_empty_fifo(dma_regs_t * DMAx,uint32_t channel)567 __STATIC_INLINE uint32_t ll_dma_is_empty_fifo(dma_regs_t *DMAx, uint32_t channel)
568 {
569 return (READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_FIFO_EMPTY) == DMA_CFGL_FIFO_EMPTY);
570 }
571
572 /**
573 * @brief Configure all parameters link to DMA transfer.
574 *
575 * Register|BitsName
576 * --------|--------
577 * CCR | DIR
578 * CCR | MEM2MEM
579 * CCR | CIRC
580 * CCR | PINC
581 * CCR | MINC
582 * CCR | PSIZE
583 * CCR | MSIZE
584 * CCR | PL
585 *
586 * @param DMAx DMAx instance
587 * @param channel This parameter can be one of the following values:
588 * @arg @ref LL_DMA_CHANNEL_0
589 * @arg @ref LL_DMA_CHANNEL_1
590 * @arg @ref LL_DMA_CHANNEL_2
591 * @arg @ref LL_DMA_CHANNEL_3
592 * @arg @ref LL_DMA_CHANNEL_4
593 * @arg @ref LL_DMA_CHANNEL_5
594 * @arg @ref LL_DMA_CHANNEL_6
595 * @arg @ref LL_DMA_CHANNEL_7
596 * @param configuration This parameter must be a combination of all the following values:
597 * @arg @ref LL_DMA_MODE_SINGLE_BLOCK or @ref LL_DMA_MODE_MULTI_BLOCK_SRC_RELOAD
598 * or @ref LL_DMA_MODE_MULTI_BLOCK_DST_RELOAD or @ref LL_DMA_MODE_MULTI_BLOCK_ALL_RELOAD
599 * @arg @ref LL_DMA_SRC_INCREMENT or @ref LL_DMA_SRC_DECREMENT or @ref LL_DMA_SRC_NO_CHANGE
600 * @arg @ref LL_DMA_DST_INCREMENT or @ref LL_DMA_DST_DECREMENT or @ref LL_DMA_DST_NO_CHANGE
601 * @arg @ref LL_DMA_SDATAALIGN_BYTE or @ref LL_DMA_SDATAALIGN_HALFWORD or @ref LL_DMA_SDATAALIGN_WORD
602 * @arg @ref LL_DMA_DDATAALIGN_BYTE or @ref LL_DMA_DDATAALIGN_HALFWORD or @ref LL_DMA_DDATAALIGN_WORD
603 * @arg @ref LL_DMA_SRC_BURST_LENGTH_1 or @ref LL_DMA_SRC_BURST_LENGTH_4 or @ref LL_DMA_SRC_BURST_LENGTH_8
604 * @arg @ref LL_DMA_DST_BURST_LENGTH_1 or @ref LL_DMA_DST_BURST_LENGTH_4 or @ref LL_DMA_DST_BURST_LENGTH_8
605 * @retval None
606 */
ll_dma_config_transfer(dma_regs_t * DMAx,uint32_t channel,uint32_t configuration)607 __STATIC_INLINE void ll_dma_config_transfer(dma_regs_t *DMAx, uint32_t channel, uint32_t configuration)
608 {
609 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_TR_WIDTH | DMA_CTLL_SRC_TR_WIDTH | \
610 DMA_CTLL_DINC | DMA_CTLL_SINC | DMA_CTLL_DST_MSIZE | DMA_CTLL_SRC_MSIZE | DMA_CTLL_TT_FC,
611 configuration);
612 }
613
614 /**
615 * @brief Set Data transfer direction (read from peripheral or from memory).
616 *
617 * Register|BitsName
618 * --------|--------
619 * CTL_LO | TT_FC
620 *
621 * @param DMAx DMAx instance
622 * @param channel This parameter can be one of the following values:
623 * @arg @ref LL_DMA_CHANNEL_0
624 * @arg @ref LL_DMA_CHANNEL_1
625 * @arg @ref LL_DMA_CHANNEL_2
626 * @arg @ref LL_DMA_CHANNEL_3
627 * @arg @ref LL_DMA_CHANNEL_4
628 * @arg @ref LL_DMA_CHANNEL_5
629 * @arg @ref LL_DMA_CHANNEL_6
630 * @arg @ref LL_DMA_CHANNEL_7
631 * @param direction This parameter can be one of the following values:
632 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
633 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
634 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
635 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_PERIPH
636 * @retval None
637 */
ll_dma_set_data_transfer_direction(dma_regs_t * DMAx,uint32_t channel,uint32_t direction)638 __STATIC_INLINE void ll_dma_set_data_transfer_direction(dma_regs_t *DMAx, uint32_t channel, uint32_t direction)
639 {
640 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, direction);
641 }
642
643 /**
644 * @brief Get Data transfer direction (read from peripheral or from memory).
645 *
646 * Register|BitsName
647 * --------|--------
648 * CTL_LO | TT_FC
649 *
650 * @param DMAx DMAx instance
651 * @param channel This parameter can be one of the following values:
652 * @arg @ref LL_DMA_CHANNEL_0
653 * @arg @ref LL_DMA_CHANNEL_1
654 * @arg @ref LL_DMA_CHANNEL_2
655 * @arg @ref LL_DMA_CHANNEL_3
656 * @arg @ref LL_DMA_CHANNEL_4
657 * @arg @ref LL_DMA_CHANNEL_5
658 * @arg @ref LL_DMA_CHANNEL_6
659 * @arg @ref LL_DMA_CHANNEL_7
660 * @retval Returned value can be one of the following values:
661 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
662 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
663 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
664 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_PERIPH
665 */
ll_dma_get_data_transfer_direction(dma_regs_t * DMAx,uint32_t channel)666 __STATIC_INLINE uint32_t ll_dma_get_data_transfer_direction(dma_regs_t *DMAx, uint32_t channel)
667 {
668 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC);
669 }
670
671 /**
672 * @brief Set DMA mode Single block or Multi block.
673 * @note The circular buffer mode cannot be used if the memory-to-memory
674 * data transfer is configured on the selected Channel.
675 *
676 * Register|BitsName
677 * --------|--------
678 * CFG_LO | RELOAD_DST
679 *
680 * @param DMAx DMAx instance
681 * @param channel This parameter can be one of the following values:
682 * @arg @ref LL_DMA_CHANNEL_0
683 * @arg @ref LL_DMA_CHANNEL_1
684 * @arg @ref LL_DMA_CHANNEL_2
685 * @arg @ref LL_DMA_CHANNEL_3
686 * @arg @ref LL_DMA_CHANNEL_4
687 * @arg @ref LL_DMA_CHANNEL_5
688 * @arg @ref LL_DMA_CHANNEL_6
689 * @arg @ref LL_DMA_CHANNEL_7
690 * @param mode This parameter can be one of the following values:
691 * @arg @ref LL_DMA_MODE_SINGLE_BLOCK
692 * @arg @ref LL_DMA_MODE_MULTI_BLOCK_SRC_RELOAD
693 * @arg @ref LL_DMA_MODE_MULTI_BLOCK_DST_RELOAD
694 * @arg @ref LL_DMA_MODE_MULTI_BLOCK_ALL_RELOAD
695 * @retval None
696 */
ll_dma_set_mode(dma_regs_t * DMAx,uint32_t channel,uint32_t mode)697 __STATIC_INLINE void ll_dma_set_mode(dma_regs_t *DMAx, uint32_t channel, uint32_t mode)
698 {
699 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_RELOAD_DST | DMA_CFGL_RELOAD_SRC, mode);
700 }
701
702
703 /**
704 * @brief Get DMA mode circular or normal.
705 *
706 * Register|BitsName
707 * --------|--------
708 * CFG_LO | RELOAD_DST
709 *
710 * @param DMAx DMAx instance
711 * @param channel This parameter can be one of the following values:
712 * @arg @ref LL_DMA_CHANNEL_0
713 * @arg @ref LL_DMA_CHANNEL_1
714 * @arg @ref LL_DMA_CHANNEL_2
715 * @arg @ref LL_DMA_CHANNEL_3
716 * @arg @ref LL_DMA_CHANNEL_4
717 * @arg @ref LL_DMA_CHANNEL_5
718 * @arg @ref LL_DMA_CHANNEL_6
719 * @arg @ref LL_DMA_CHANNEL_7
720 * @retval Returned value can be one of the following values:
721 * @arg @ref LL_DMA_MODE_SINGLE_BLOCK
722 * @arg @ref LL_DMA_MODE_MULTI_BLOCK_SRC_RELOAD
723 * @arg @ref LL_DMA_MODE_MULTI_BLOCK_DST_RELOAD
724 * @arg @ref LL_DMA_MODE_MULTI_BLOCK_ALL_RELOAD
725 */
ll_dma_get_mode(dma_regs_t * DMAx,uint32_t channel)726 __STATIC_INLINE uint32_t ll_dma_get_mode(dma_regs_t *DMAx, uint32_t channel)
727 {
728 return READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_RELOAD_DST | DMA_CFGL_RELOAD_SRC);
729 }
730
731 /**
732 * @brief Set Source increment mode.
733 *
734 * Register|BitsName
735 * --------|--------
736 * CTL_LO | SINC
737 *
738 * @param DMAx DMAx instance
739 * @param channel This parameter can be one of the following values:
740 * @arg @ref LL_DMA_CHANNEL_0
741 * @arg @ref LL_DMA_CHANNEL_1
742 * @arg @ref LL_DMA_CHANNEL_2
743 * @arg @ref LL_DMA_CHANNEL_3
744 * @arg @ref LL_DMA_CHANNEL_4
745 * @arg @ref LL_DMA_CHANNEL_5
746 * @arg @ref LL_DMA_CHANNEL_6
747 * @arg @ref LL_DMA_CHANNEL_7
748 * @param src_increment_mode This parameter can be one of the following values:
749 * @arg @ref LL_DMA_SRC_INCREMENT
750 * @arg @ref LL_DMA_SRC_DECREMENT
751 * @arg @ref LL_DMA_SRC_NO_CHANGE
752 * @retval None
753 */
ll_dma_set_source_increment_mode(dma_regs_t * DMAx,uint32_t channel,uint32_t src_increment_mode)754 __STATIC_INLINE void ll_dma_set_source_increment_mode(dma_regs_t *DMAx, uint32_t channel, uint32_t src_increment_mode)
755 {
756 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SINC, src_increment_mode);
757 }
758
759 /**
760 * @brief Get Source increment mode.
761 *
762 * Register|BitsName
763 * --------|--------
764 * CTL_LO | SINC
765 *
766 * @param DMAx DMAx instance
767 * @param channel This parameter can be one of the following values:
768 * @arg @ref LL_DMA_CHANNEL_0
769 * @arg @ref LL_DMA_CHANNEL_1
770 * @arg @ref LL_DMA_CHANNEL_2
771 * @arg @ref LL_DMA_CHANNEL_3
772 * @arg @ref LL_DMA_CHANNEL_4
773 * @arg @ref LL_DMA_CHANNEL_5
774 * @arg @ref LL_DMA_CHANNEL_6
775 * @arg @ref LL_DMA_CHANNEL_7
776 * @retval Returned value can be one of the following values:
777 * @arg @ref LL_DMA_SRC_INCREMENT
778 * @arg @ref LL_DMA_SRC_DECREMENT
779 * @arg @ref LL_DMA_SRC_NO_CHANGE
780 */
ll_dma_get_source_increment_mode(dma_regs_t * DMAx,uint32_t channel)781 __STATIC_INLINE uint32_t ll_dma_get_source_increment_mode(dma_regs_t *DMAx, uint32_t channel)
782 {
783 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SINC);
784 }
785
786 /**
787 * @brief Set Destination increment mode.
788 *
789 * Register|BitsName
790 * --------|--------
791 * CTL_LO | DINC
792 *
793 * @param DMAx DMAx instance
794 * @param channel This parameter can be one of the following values:
795 * @arg @ref LL_DMA_CHANNEL_0
796 * @arg @ref LL_DMA_CHANNEL_1
797 * @arg @ref LL_DMA_CHANNEL_2
798 * @arg @ref LL_DMA_CHANNEL_3
799 * @arg @ref LL_DMA_CHANNEL_4
800 * @arg @ref LL_DMA_CHANNEL_5
801 * @arg @ref LL_DMA_CHANNEL_6
802 * @arg @ref LL_DMA_CHANNEL_7
803 * @param dst_increment_mode This parameter can be one of the following values:
804 * @arg @ref LL_DMA_DST_INCREMENT
805 * @arg @ref LL_DMA_DST_DECREMENT
806 * @arg @ref LL_DMA_DST_NO_CHANGE
807 * @retval None
808 */
ll_dma_set_destination_increment_mode(dma_regs_t * DMAx,uint32_t channel,uint32_t dst_increment_mode)809 __STATIC_INLINE void ll_dma_set_destination_increment_mode(dma_regs_t *DMAx, uint32_t channel,
810 uint32_t dst_increment_mode)
811 {
812 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DINC, dst_increment_mode);
813 }
814
815 /**
816 * @brief Get Destination increment mode.
817 *
818 * Register|BitsName
819 * --------|--------
820 * CTL_LO | DINC
821 *
822 * @param DMAx DMAx instance
823 * @param channel This parameter can be one of the following values:
824 * @arg @ref LL_DMA_CHANNEL_0
825 * @arg @ref LL_DMA_CHANNEL_1
826 * @arg @ref LL_DMA_CHANNEL_2
827 * @arg @ref LL_DMA_CHANNEL_3
828 * @arg @ref LL_DMA_CHANNEL_4
829 * @arg @ref LL_DMA_CHANNEL_5
830 * @arg @ref LL_DMA_CHANNEL_6
831 * @arg @ref LL_DMA_CHANNEL_7
832 * @retval Returned value can be one of the following values:
833 * @arg @ref LL_DMA_DST_INCREMENT
834 * @arg @ref LL_DMA_DST_DECREMENT
835 * @arg @ref LL_DMA_DST_NO_CHANGE
836 */
ll_dma_get_destination_increment_mode(dma_regs_t * DMAx,uint32_t channel)837 __STATIC_INLINE uint32_t ll_dma_get_destination_increment_mode(dma_regs_t *DMAx, uint32_t channel)
838 {
839 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DINC);
840 }
841
842 /**
843 * @brief Set Source transfer width.
844 *
845 * Register|BitsName
846 * --------|--------
847 * CTL_LO | SRC_TR_WIDTH
848 *
849 * @param DMAx DMAx instance
850 * @param channel This parameter can be one of the following values:
851 * @arg @ref LL_DMA_CHANNEL_0
852 * @arg @ref LL_DMA_CHANNEL_1
853 * @arg @ref LL_DMA_CHANNEL_2
854 * @arg @ref LL_DMA_CHANNEL_3
855 * @arg @ref LL_DMA_CHANNEL_4
856 * @arg @ref LL_DMA_CHANNEL_5
857 * @arg @ref LL_DMA_CHANNEL_6
858 * @arg @ref LL_DMA_CHANNEL_7
859 * @param src_width This parameter can be one of the following values:
860 * @arg @ref LL_DMA_SDATAALIGN_BYTE
861 * @arg @ref LL_DMA_SDATAALIGN_HALFWORD
862 * @arg @ref LL_DMA_SDATAALIGN_WORD
863 * @retval None
864 */
ll_dma_set_source_width(dma_regs_t * DMAx,uint32_t channel,uint32_t src_width)865 __STATIC_INLINE void ll_dma_set_source_width(dma_regs_t *DMAx, uint32_t channel, uint32_t src_width)
866 {
867 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_TR_WIDTH, src_width);
868 }
869
870 /**
871 * @brief Get Source transfer width.
872 *
873 * Register|BitsName
874 * --------|--------
875 * CTL_LO | SRC_TR_WIDTH
876 *
877 * @param DMAx DMAx instance
878 * @param channel This parameter can be one of the following values:
879 * @arg @ref LL_DMA_CHANNEL_0
880 * @arg @ref LL_DMA_CHANNEL_1
881 * @arg @ref LL_DMA_CHANNEL_2
882 * @arg @ref LL_DMA_CHANNEL_3
883 * @arg @ref LL_DMA_CHANNEL_4
884 * @arg @ref LL_DMA_CHANNEL_5
885 * @arg @ref LL_DMA_CHANNEL_6
886 * @arg @ref LL_DMA_CHANNEL_7
887 * @retval Returned value can be one of the following values:
888 * @arg @ref LL_DMA_SDATAALIGN_BYTE
889 * @arg @ref LL_DMA_SDATAALIGN_HALFWORD
890 * @arg @ref LL_DMA_SDATAALIGN_WORD
891 */
ll_dma_get_source_width(dma_regs_t * DMAx,uint32_t channel)892 __STATIC_INLINE uint32_t ll_dma_get_source_width(dma_regs_t *DMAx, uint32_t channel)
893 {
894 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_TR_WIDTH);
895 }
896
897 /**
898 * @brief Set Destination transfer width.
899 *
900 * Register|BitsName
901 * --------|--------
902 * CTL_LO | DST_TR_WIDTH
903 *
904 * @param DMAx DMAx instance
905 * @param channel This parameter can be one of the following values:
906 * @arg @ref LL_DMA_CHANNEL_0
907 * @arg @ref LL_DMA_CHANNEL_1
908 * @arg @ref LL_DMA_CHANNEL_2
909 * @arg @ref LL_DMA_CHANNEL_3
910 * @arg @ref LL_DMA_CHANNEL_4
911 * @arg @ref LL_DMA_CHANNEL_5
912 * @arg @ref LL_DMA_CHANNEL_6
913 * @arg @ref LL_DMA_CHANNEL_7
914 * @param dst_width This parameter can be one of the following values:
915 * @arg @ref LL_DMA_DDATAALIGN_BYTE
916 * @arg @ref LL_DMA_DDATAALIGN_HALFWORD
917 * @arg @ref LL_DMA_DDATAALIGN_WORD
918 * @retval None
919 */
ll_dma_set_destination_width(dma_regs_t * DMAx,uint32_t channel,uint32_t dst_width)920 __STATIC_INLINE void ll_dma_set_destination_width(dma_regs_t *DMAx, uint32_t channel, uint32_t dst_width)
921 {
922 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_TR_WIDTH, dst_width);
923 }
924
925 /**
926 * @brief Get Destination transfer width.
927 *
928 * Register|BitsName
929 * --------|--------
930 * CTL_LO | DST_TR_WIDTH
931 *
932 * @param DMAx DMAx instance
933 * @param channel This parameter can be one of the following values:
934 * @arg @ref LL_DMA_CHANNEL_0
935 * @arg @ref LL_DMA_CHANNEL_1
936 * @arg @ref LL_DMA_CHANNEL_2
937 * @arg @ref LL_DMA_CHANNEL_3
938 * @arg @ref LL_DMA_CHANNEL_4
939 * @arg @ref LL_DMA_CHANNEL_5
940 * @arg @ref LL_DMA_CHANNEL_6
941 * @arg @ref LL_DMA_CHANNEL_7
942 * @retval Returned value can be one of the following values:
943 * @arg @ref LL_DMA_DDATAALIGN_BYTE
944 * @arg @ref LL_DMA_DDATAALIGN_HALFWORD
945 * @arg @ref LL_DMA_DDATAALIGN_WORD
946 */
ll_dma_get_destination_width(dma_regs_t * DMAx,uint32_t channel)947 __STATIC_INLINE uint32_t ll_dma_get_destination_width(dma_regs_t *DMAx, uint32_t channel)
948 {
949 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_TR_WIDTH);
950 }
951
952 /**
953 * @brief Set Source Burst Transaction Length.
954 *
955 * Register|BitsName
956 * --------|--------
957 * CTL_LO | SRC_MSIZE
958 *
959 * @param DMAx DMAx instance
960 * @param channel This parameter can be one of the following values:
961 * @arg @ref LL_DMA_CHANNEL_0
962 * @arg @ref LL_DMA_CHANNEL_1
963 * @arg @ref LL_DMA_CHANNEL_2
964 * @arg @ref LL_DMA_CHANNEL_3
965 * @arg @ref LL_DMA_CHANNEL_4
966 * @arg @ref LL_DMA_CHANNEL_5
967 * @arg @ref LL_DMA_CHANNEL_6
968 * @arg @ref LL_DMA_CHANNEL_7
969 * @param burst_length This parameter can be one of the following values:
970 * @arg @ref LL_DMA_SRC_BURST_LENGTH_1
971 * @arg @ref LL_DMA_SRC_BURST_LENGTH_4
972 * @arg @ref LL_DMA_SRC_BURST_LENGTH_8
973 * @retval None
974 */
ll_dma_set_source_burst_length(dma_regs_t * DMAx,uint32_t channel,uint32_t burst_length)975 __STATIC_INLINE void ll_dma_set_source_burst_length(dma_regs_t *DMAx, uint32_t channel, uint32_t burst_length)
976 {
977 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_MSIZE, burst_length);
978 }
979
980 /**
981 * @brief Get Burst Transaction Length.
982 *
983 * Register|BitsName
984 * --------|--------
985 * CTL_LO | SRC_MSIZE
986 *
987 * @param DMAx DMAx instance
988 * @param channel This parameter can be one of the following values:
989 * @arg @ref LL_DMA_CHANNEL_0
990 * @arg @ref LL_DMA_CHANNEL_1
991 * @arg @ref LL_DMA_CHANNEL_2
992 * @arg @ref LL_DMA_CHANNEL_3
993 * @arg @ref LL_DMA_CHANNEL_4
994 * @arg @ref LL_DMA_CHANNEL_5
995 * @arg @ref LL_DMA_CHANNEL_6
996 * @arg @ref LL_DMA_CHANNEL_7
997 * @retval Returned value can be one of the following values:
998 * @arg @ref LL_DMA_SRC_BURST_LENGTH_1
999 * @arg @ref LL_DMA_SRC_BURST_LENGTH_4
1000 * @arg @ref LL_DMA_SRC_BURST_LENGTH_8
1001 */
ll_dma_get_source_burst_length(dma_regs_t * DMAx,uint32_t channel)1002 __STATIC_INLINE uint32_t ll_dma_get_source_burst_length(dma_regs_t *DMAx, uint32_t channel)
1003 {
1004 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_SRC_MSIZE);
1005 }
1006
1007 /**
1008 * @brief Set Destination Burst Transaction Length.
1009 *
1010 * Register|BitsName
1011 * --------|--------
1012 * CTL_LO | DST_MSIZE
1013 *
1014 * @param DMAx DMAx instance
1015 * @param channel This parameter can be one of the following values:
1016 * @arg @ref LL_DMA_CHANNEL_0
1017 * @arg @ref LL_DMA_CHANNEL_1
1018 * @arg @ref LL_DMA_CHANNEL_2
1019 * @arg @ref LL_DMA_CHANNEL_3
1020 * @arg @ref LL_DMA_CHANNEL_4
1021 * @arg @ref LL_DMA_CHANNEL_5
1022 * @arg @ref LL_DMA_CHANNEL_6
1023 * @arg @ref LL_DMA_CHANNEL_7
1024 * @param burst_length This parameter can be one of the following values:
1025 * @arg @ref LL_DMA_DST_BURST_LENGTH_1
1026 * @arg @ref LL_DMA_DST_BURST_LENGTH_4
1027 * @arg @ref LL_DMA_DST_BURST_LENGTH_8
1028 * @retval None
1029 */
ll_dma_set_destination_burst_length(dma_regs_t * DMAx,uint32_t channel,uint32_t burst_length)1030 __STATIC_INLINE void ll_dma_set_destination_burst_length(dma_regs_t *DMAx, uint32_t channel, uint32_t burst_length)
1031 {
1032 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_MSIZE, burst_length);
1033 }
1034
1035 /**
1036 * @brief Get Destination Burst Transaction Length.
1037 *
1038 * Register|BitsName
1039 * --------|--------
1040 * CTL_LO | DST_MSIZE
1041 *
1042 * @param DMAx DMAx instance
1043 * @param channel This parameter can be one of the following values:
1044 * @arg @ref LL_DMA_CHANNEL_0
1045 * @arg @ref LL_DMA_CHANNEL_1
1046 * @arg @ref LL_DMA_CHANNEL_2
1047 * @arg @ref LL_DMA_CHANNEL_3
1048 * @arg @ref LL_DMA_CHANNEL_4
1049 * @arg @ref LL_DMA_CHANNEL_5
1050 * @arg @ref LL_DMA_CHANNEL_6
1051 * @arg @ref LL_DMA_CHANNEL_7
1052 * @retval Returned value can be one of the following values:
1053 * @arg @ref LL_DMA_DST_BURST_LENGTH_1
1054 * @arg @ref LL_DMA_DST_BURST_LENGTH_4
1055 * @arg @ref LL_DMA_DST_BURST_LENGTH_8
1056 */
ll_dma_get_destination_burst_length(dma_regs_t * DMAx,uint32_t channel)1057 __STATIC_INLINE uint32_t ll_dma_get_destination_burst_length(dma_regs_t *DMAx, uint32_t channel)
1058 {
1059 return READ_BITS(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_DST_MSIZE);
1060 }
1061
1062 /**
1063 * @brief Set Channel priority level.
1064 *
1065 * Register|BitsName
1066 * --------|--------
1067 * CFG_LO | CH_PRIOR
1068 *
1069 * @param DMAx DMAx instance
1070 * @param channel This parameter can be one of the following values:
1071 * @arg @ref LL_DMA_CHANNEL_0
1072 * @arg @ref LL_DMA_CHANNEL_1
1073 * @arg @ref LL_DMA_CHANNEL_2
1074 * @arg @ref LL_DMA_CHANNEL_3
1075 * @arg @ref LL_DMA_CHANNEL_4
1076 * @arg @ref LL_DMA_CHANNEL_5
1077 * @arg @ref LL_DMA_CHANNEL_6
1078 * @arg @ref LL_DMA_CHANNEL_7
1079 * @param priority This parameter can be one of the following values:
1080 * @arg @ref LL_DMA_PRIORITY_0
1081 * @arg @ref LL_DMA_PRIORITY_1
1082 * @arg @ref LL_DMA_PRIORITY_2
1083 * @arg @ref LL_DMA_PRIORITY_3
1084 * @arg @ref LL_DMA_PRIORITY_4
1085 * @arg @ref LL_DMA_PRIORITY_5
1086 * @arg @ref LL_DMA_PRIORITY_6
1087 * @arg @ref LL_DMA_PRIORITY_7
1088 * @retval None
1089 */
ll_dma_set_channel_priority_level(dma_regs_t * DMAx,uint32_t channel,uint32_t priority)1090 __STATIC_INLINE void ll_dma_set_channel_priority_level(dma_regs_t *DMAx, uint32_t channel, uint32_t priority)
1091 {
1092 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_PRIOR, priority);
1093 }
1094
1095 /**
1096 * @brief Get Channel priority level.
1097 *
1098 * Register|BitsName
1099 * --------|--------
1100 * CFG_LO | CH_PRIOR
1101 *
1102 * @param DMAx DMAx instance
1103 * @param channel This parameter can be one of the following values:
1104 * @arg @ref LL_DMA_CHANNEL_0
1105 * @arg @ref LL_DMA_CHANNEL_1
1106 * @arg @ref LL_DMA_CHANNEL_2
1107 * @arg @ref LL_DMA_CHANNEL_3
1108 * @arg @ref LL_DMA_CHANNEL_4
1109 * @arg @ref LL_DMA_CHANNEL_5
1110 * @arg @ref LL_DMA_CHANNEL_6
1111 * @arg @ref LL_DMA_CHANNEL_7
1112 * @retval Returned value can be one of the following values:
1113 * @arg @ref LL_DMA_PRIORITY_0
1114 * @arg @ref LL_DMA_PRIORITY_1
1115 * @arg @ref LL_DMA_PRIORITY_2
1116 * @arg @ref LL_DMA_PRIORITY_3
1117 * @arg @ref LL_DMA_PRIORITY_4
1118 * @arg @ref LL_DMA_PRIORITY_5
1119 * @arg @ref LL_DMA_PRIORITY_6
1120 * @arg @ref LL_DMA_PRIORITY_7
1121 */
ll_dma_get_channel_priority_level(dma_regs_t * DMAx,uint32_t channel)1122 __STATIC_INLINE uint32_t ll_dma_get_channel_priority_level(dma_regs_t *DMAx, uint32_t channel)
1123 {
1124 return READ_BITS(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_CH_PRIOR);
1125 }
1126
1127 /**
1128 * @brief Set the block size of a transfer.
1129 * @note This action has no effect if channel is enabled.
1130 *
1131 * Register|BitsName
1132 * --------|--------
1133 * CTL_HI | BLOCK_TS
1134 *
1135 * @param DMAx DMAx instance
1136 * @param channel This parameter can be one of the following values:
1137 * @arg @ref LL_DMA_CHANNEL_0
1138 * @arg @ref LL_DMA_CHANNEL_1
1139 * @arg @ref LL_DMA_CHANNEL_2
1140 * @arg @ref LL_DMA_CHANNEL_3
1141 * @arg @ref LL_DMA_CHANNEL_4
1142 * @arg @ref LL_DMA_CHANNEL_5
1143 * @arg @ref LL_DMA_CHANNEL_6
1144 * @arg @ref LL_DMA_CHANNEL_7
1145 * @param block_size Between Min_Data = 0 and Max_Data = 0xFFF
1146 * @retval None
1147 */
ll_dma_set_block_size(dma_regs_t * DMAx,uint32_t channel,uint32_t block_size)1148 __STATIC_INLINE void ll_dma_set_block_size(dma_regs_t *DMAx, uint32_t channel, uint32_t block_size)
1149 {
1150 MODIFY_REG(DMAx->CHANNEL[channel].CTL_HI, DMA_CTLH_BLOCK_TS, block_size);
1151 }
1152
1153 /**
1154 * @brief Get the block size of a transfer.
1155 * @note Once the channel is enabled, the return value indicate the
1156 * remaining bytes to be transmitted.
1157 *
1158 * Register|BitsName
1159 * --------|--------
1160 * CTL_HI | BLOCK_TS
1161 *
1162 * @param DMAx DMAx instance
1163 * @param channel This parameter can be one of the following values:
1164 * @arg @ref LL_DMA_CHANNEL_0
1165 * @arg @ref LL_DMA_CHANNEL_1
1166 * @arg @ref LL_DMA_CHANNEL_2
1167 * @arg @ref LL_DMA_CHANNEL_3
1168 * @arg @ref LL_DMA_CHANNEL_4
1169 * @arg @ref LL_DMA_CHANNEL_5
1170 * @arg @ref LL_DMA_CHANNEL_6
1171 * @arg @ref LL_DMA_CHANNEL_7
1172 * @retval Between Min_Data = 0 and Max_Data = 0xFFF
1173 */
ll_dma_get_block_size(dma_regs_t * DMAx,uint32_t channel)1174 __STATIC_INLINE uint32_t ll_dma_get_block_size(dma_regs_t *DMAx, uint32_t channel)
1175 {
1176 return READ_BITS(DMAx->CHANNEL[channel].CTL_HI, DMA_CTLH_BLOCK_TS);
1177 }
1178
1179 /**
1180 * @brief Configure the Source and Destination addresses.
1181 * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr)
1182 *
1183 * Register|BitsName
1184 * --------|--------
1185 * SAR | SAR
1186 * DAR | DAR
1187 * CTL_LO | TT_FC
1188 *
1189 * @param DMAx DMAx instance
1190 * @param channel This parameter can be one of the following values:
1191 * @arg @ref LL_DMA_CHANNEL_0
1192 * @arg @ref LL_DMA_CHANNEL_1
1193 * @arg @ref LL_DMA_CHANNEL_2
1194 * @arg @ref LL_DMA_CHANNEL_3
1195 * @arg @ref LL_DMA_CHANNEL_4
1196 * @arg @ref LL_DMA_CHANNEL_5
1197 * @arg @ref LL_DMA_CHANNEL_6
1198 * @arg @ref LL_DMA_CHANNEL_7
1199 * @param src_address Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1200 * @param dst_address Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1201 * @param direction This parameter can be one of the following values:
1202 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
1203 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
1204 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
1205 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_PERIPH
1206 * @retval None
1207 */
ll_dma_config_address(dma_regs_t * DMAx,uint32_t channel,uint32_t src_address,uint32_t dst_address,uint32_t direction)1208 __STATIC_INLINE void ll_dma_config_address(dma_regs_t *DMAx, uint32_t channel, uint32_t src_address,
1209 uint32_t dst_address, uint32_t direction)
1210 {
1211 WRITE_REG(DMAx->CHANNEL[channel].SAR, src_address);
1212 WRITE_REG(DMAx->CHANNEL[channel].DAR, dst_address);
1213 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, direction);
1214 }
1215
1216 /**
1217 * @brief Set the Source address.
1218 *
1219 * Register|BitsName
1220 * --------|--------
1221 * SAR | SAR
1222 *
1223 * @param DMAx DMAx instance
1224 * @param channel This parameter can be one of the following values:
1225 * @arg @ref LL_DMA_CHANNEL_0
1226 * @arg @ref LL_DMA_CHANNEL_1
1227 * @arg @ref LL_DMA_CHANNEL_2
1228 * @arg @ref LL_DMA_CHANNEL_3
1229 * @arg @ref LL_DMA_CHANNEL_4
1230 * @arg @ref LL_DMA_CHANNEL_5
1231 * @arg @ref LL_DMA_CHANNEL_6
1232 * @arg @ref LL_DMA_CHANNEL_7
1233 * @param address Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1234 * @retval None
1235 */
ll_dma_set_source_address(dma_regs_t * DMAx,uint32_t channel,uint32_t address)1236 __STATIC_INLINE void ll_dma_set_source_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
1237 {
1238 WRITE_REG(DMAx->CHANNEL[channel].SAR, address);
1239 }
1240
1241 /**
1242 * @brief Set the Destination address.
1243 *
1244 * Register|BitsName
1245 * --------|--------
1246 * DAR | DAR
1247 *
1248 * @param DMAx DMAx instance
1249 * @param channel This parameter can be one of the following values:
1250 * @arg @ref LL_DMA_CHANNEL_0
1251 * @arg @ref LL_DMA_CHANNEL_1
1252 * @arg @ref LL_DMA_CHANNEL_2
1253 * @arg @ref LL_DMA_CHANNEL_3
1254 * @arg @ref LL_DMA_CHANNEL_4
1255 * @arg @ref LL_DMA_CHANNEL_5
1256 * @arg @ref LL_DMA_CHANNEL_6
1257 * @arg @ref LL_DMA_CHANNEL_7
1258 * @param address Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1259 * @retval None
1260 */
ll_dma_set_destination_address(dma_regs_t * DMAx,uint32_t channel,uint32_t address)1261 __STATIC_INLINE void ll_dma_set_destination_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
1262 {
1263 WRITE_REG(DMAx->CHANNEL[channel].DAR, address);
1264 }
1265
1266 /**
1267 * @brief Get Source address.
1268 *
1269 * Register|BitsName
1270 * --------|--------
1271 * SAR | SAR
1272 *
1273 * @param DMAx DMAx instance
1274 * @param channel This parameter can be one of the following values:
1275 * @arg @ref LL_DMA_CHANNEL_0
1276 * @arg @ref LL_DMA_CHANNEL_1
1277 * @arg @ref LL_DMA_CHANNEL_2
1278 * @arg @ref LL_DMA_CHANNEL_3
1279 * @arg @ref LL_DMA_CHANNEL_4
1280 * @arg @ref LL_DMA_CHANNEL_5
1281 * @arg @ref LL_DMA_CHANNEL_6
1282 * @arg @ref LL_DMA_CHANNEL_7
1283 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1284 */
ll_dma_get_source_address(dma_regs_t * DMAx,uint32_t channel)1285 __STATIC_INLINE uint32_t ll_dma_get_source_address(dma_regs_t *DMAx, uint32_t channel)
1286 {
1287 return READ_REG(DMAx->CHANNEL[channel].SAR);
1288 }
1289
1290 /**
1291 * @brief Get Destination address.
1292 *
1293 * Register|BitsName
1294 * --------|--------
1295 * DAR | DAR
1296 *
1297 * @param DMAx DMAx instance
1298 * @param channel This parameter can be one of the following values:
1299 * @arg @ref LL_DMA_CHANNEL_0
1300 * @arg @ref LL_DMA_CHANNEL_1
1301 * @arg @ref LL_DMA_CHANNEL_2
1302 * @arg @ref LL_DMA_CHANNEL_3
1303 * @arg @ref LL_DMA_CHANNEL_4
1304 * @arg @ref LL_DMA_CHANNEL_5
1305 * @arg @ref LL_DMA_CHANNEL_6
1306 * @arg @ref LL_DMA_CHANNEL_7
1307 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1308 */
ll_dma_get_destination_address(dma_regs_t * DMAx,uint32_t channel)1309 __STATIC_INLINE uint32_t ll_dma_get_destination_address(dma_regs_t *DMAx, uint32_t channel)
1310 {
1311 return READ_REG(DMAx->CHANNEL[channel].DAR);
1312 }
1313
1314 /**
1315 * @brief Set the Memory to Memory Source address.
1316 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1317 *
1318 * Register|BitsName
1319 * --------|--------
1320 * SAR | SAR
1321 * CTL_LO | TT_FC
1322 * @param DMAx DMAx instance
1323 * @param channel This parameter can be one of the following values:
1324 * @arg @ref LL_DMA_CHANNEL_0
1325 * @arg @ref LL_DMA_CHANNEL_1
1326 * @arg @ref LL_DMA_CHANNEL_2
1327 * @arg @ref LL_DMA_CHANNEL_3
1328 * @arg @ref LL_DMA_CHANNEL_4
1329 * @arg @ref LL_DMA_CHANNEL_5
1330 * @arg @ref LL_DMA_CHANNEL_6
1331 * @arg @ref LL_DMA_CHANNEL_7
1332 * @param address Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1333 * @retval None
1334 */
ll_dma_set_m2m_src_address(dma_regs_t * DMAx,uint32_t channel,uint32_t address)1335 __STATIC_INLINE void ll_dma_set_m2m_src_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
1336 {
1337 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, 0);
1338 WRITE_REG(DMAx->CHANNEL[channel].SAR, address);
1339 }
1340
1341 /**
1342 * @brief Set the Memory to Memory Destination address.
1343 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1344 *
1345 * Register|BitsName
1346 * --------|--------
1347 * DAR | DAR
1348 * CTL_LO | TT_FC
1349 *
1350 * @param DMAx DMAx instance
1351 * @param channel This parameter can be one of the following values:
1352 * @arg @ref LL_DMA_CHANNEL_0
1353 * @arg @ref LL_DMA_CHANNEL_1
1354 * @arg @ref LL_DMA_CHANNEL_2
1355 * @arg @ref LL_DMA_CHANNEL_3
1356 * @arg @ref LL_DMA_CHANNEL_4
1357 * @arg @ref LL_DMA_CHANNEL_5
1358 * @arg @ref LL_DMA_CHANNEL_6
1359 * @arg @ref LL_DMA_CHANNEL_7
1360 * @param address Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1361 * @retval None
1362 */
ll_dma_set_m2m_dst_address(dma_regs_t * DMAx,uint32_t channel,uint32_t address)1363 __STATIC_INLINE void ll_dma_set_m2m_dst_address(dma_regs_t *DMAx, uint32_t channel, uint32_t address)
1364 {
1365 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_TT_FC, 0);
1366 WRITE_REG(DMAx->CHANNEL[channel].DAR, address);
1367 }
1368
1369 /**
1370 * @brief Get the Memory to Memory Source address.
1371 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1372 *
1373 * Register|BitsName
1374 * --------|--------
1375 * SAR | SAR
1376 *
1377 * @param DMAx DMAx instance
1378 * @param channel This parameter can be one of the following values:
1379 * @arg @ref LL_DMA_CHANNEL_0
1380 * @arg @ref LL_DMA_CHANNEL_1
1381 * @arg @ref LL_DMA_CHANNEL_2
1382 * @arg @ref LL_DMA_CHANNEL_3
1383 * @arg @ref LL_DMA_CHANNEL_4
1384 * @arg @ref LL_DMA_CHANNEL_5
1385 * @arg @ref LL_DMA_CHANNEL_6
1386 * @arg @ref LL_DMA_CHANNEL_7
1387 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1388 */
ll_dma_get_m2m_src_address(dma_regs_t * DMAx,uint32_t channel)1389 __STATIC_INLINE uint32_t ll_dma_get_m2m_src_address(dma_regs_t *DMAx, uint32_t channel)
1390 {
1391 return READ_REG(DMAx->CHANNEL[channel].SAR);
1392 }
1393
1394 /**
1395 * @brief Get the Memory to Memory Destination address.
1396 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1397 *
1398 * Register|BitsName
1399 * --------|--------
1400 * DAR | DAR
1401 *
1402 * @param DMAx DMAx instance
1403 * @param channel This parameter can be one of the following values:
1404 * @arg @ref LL_DMA_CHANNEL_0
1405 * @arg @ref LL_DMA_CHANNEL_1
1406 * @arg @ref LL_DMA_CHANNEL_2
1407 * @arg @ref LL_DMA_CHANNEL_3
1408 * @arg @ref LL_DMA_CHANNEL_4
1409 * @arg @ref LL_DMA_CHANNEL_5
1410 * @arg @ref LL_DMA_CHANNEL_6
1411 * @arg @ref LL_DMA_CHANNEL_7
1412 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1413 */
ll_dma_get_m2m_dst_address(dma_regs_t * DMAx,uint32_t channel)1414 __STATIC_INLINE uint32_t ll_dma_get_m2m_dst_address(dma_regs_t *DMAx, uint32_t channel)
1415 {
1416 return READ_REG(DMAx->CHANNEL[channel].DAR);
1417 }
1418
1419 /**
1420 * @brief Set source peripheral for DMA instance on Channel x.
1421 *
1422 * Register|BitsName
1423 * --------|--------
1424 * CFG_HI | SRC_PER
1425 *
1426 * @param DMAx DMAx instance
1427 * @param channel This parameter can be one of the following values:
1428 * @arg @ref LL_DMA_CHANNEL_0
1429 * @arg @ref LL_DMA_CHANNEL_1
1430 * @arg @ref LL_DMA_CHANNEL_2
1431 * @arg @ref LL_DMA_CHANNEL_3
1432 * @arg @ref LL_DMA_CHANNEL_4
1433 * @arg @ref LL_DMA_CHANNEL_5
1434 * @arg @ref LL_DMA_CHANNEL_6
1435 * @arg @ref LL_DMA_CHANNEL_7
1436 * @param peripheral This parameter can be one of the following values:
1437 * @arg @ref LL_DMA_PERIPH_SPIM_TX
1438 * @arg @ref LL_DMA_PERIPH_SPIM_RX
1439 * @arg @ref LL_DMA_PERIPH_SPIS_TX
1440 * @arg @ref LL_DMA_PERIPH_SPIS_RX
1441 * @arg @ref LL_DMA_PERIPH_QSPI0_TX
1442 * @arg @ref LL_DMA_PERIPH_QSPI0_RX
1443 * @arg @ref LL_DMA_PERIPH_I2C0_TX
1444 * @arg @ref LL_DMA_PERIPH_I2C0_RX
1445 * @arg @ref LL_DMA_PERIPH_I2C1_TX
1446 * @arg @ref LL_DMA_PERIPH_I2C1_RX
1447 * @arg @ref LL_DMA_PERIPH_I2S_S_TX
1448 * @arg @ref LL_DMA_PERIPH_I2S_S_RX
1449 * @arg @ref LL_DMA_PERIPH_UART0_TX
1450 * @arg @ref LL_DMA_PERIPH_UART0_RX
1451 * @arg @ref LL_DMA_PERIPH_QSPI1_TX
1452 * @arg @ref LL_DMA_PERIPH_QSPI1_RX
1453 * @arg @ref LL_DMA_PERIPH_I2S_M_TX
1454 * @arg @ref LL_DMA_PERIPH_I2S_M_RX
1455 * @arg @ref LL_DMA_PERIPH_SNSADC
1456 * @retval None
1457 */
ll_dma_set_source_peripheral(dma_regs_t * DMAx,uint32_t channel,uint32_t peripheral)1458 __STATIC_INLINE void ll_dma_set_source_peripheral(dma_regs_t *DMAx, uint32_t channel, uint32_t peripheral)
1459 {
1460 MODIFY_REG(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_SRC_PER, (peripheral << DMA_CFGH_SRC_PER_Pos));
1461 }
1462
1463 /**
1464 * @brief Get source peripheral for DMA instance on Channel x.
1465 *
1466 * Register|BitsName
1467 * --------|--------
1468 * CFG_HI | SRC_PER
1469 *
1470 * @param DMAx DMAx instance
1471 * @param channel This parameter can be one of the following values:
1472 * @arg @ref LL_DMA_CHANNEL_0
1473 * @arg @ref LL_DMA_CHANNEL_1
1474 * @arg @ref LL_DMA_CHANNEL_2
1475 * @arg @ref LL_DMA_CHANNEL_3
1476 * @arg @ref LL_DMA_CHANNEL_4
1477 * @arg @ref LL_DMA_CHANNEL_5
1478 * @arg @ref LL_DMA_CHANNEL_6
1479 * @arg @ref LL_DMA_CHANNEL_7
1480 * @retval Returned value can be one of the following values:
1481 * @arg @ref LL_DMA_PERIPH_SPIM_TX
1482 * @arg @ref LL_DMA_PERIPH_SPIM_RX
1483 * @arg @ref LL_DMA_PERIPH_SPIS_TX
1484 * @arg @ref LL_DMA_PERIPH_SPIS_RX
1485 * @arg @ref LL_DMA_PERIPH_QSPI0_TX
1486 * @arg @ref LL_DMA_PERIPH_QSPI0_RX
1487 * @arg @ref LL_DMA_PERIPH_I2C0_TX
1488 * @arg @ref LL_DMA_PERIPH_I2C0_RX
1489 * @arg @ref LL_DMA_PERIPH_I2C1_TX
1490 * @arg @ref LL_DMA_PERIPH_I2C1_RX
1491 * @arg @ref LL_DMA_PERIPH_I2S_S_TX
1492 * @arg @ref LL_DMA_PERIPH_I2S_S_RX
1493 * @arg @ref LL_DMA_PERIPH_UART0_TX
1494 * @arg @ref LL_DMA_PERIPH_UART0_RX
1495 * @arg @ref LL_DMA_PERIPH_QSPI1_TX
1496 * @arg @ref LL_DMA_PERIPH_QSPI1_RX
1497 * @arg @ref LL_DMA_PERIPH_I2S_M_TX
1498 * @arg @ref LL_DMA_PERIPH_I2S_M_RX
1499 * @arg @ref LL_DMA_PERIPH_SNSADC
1500 */
ll_dma_get_source_peripheral(dma_regs_t * DMAx,uint32_t channel)1501 __STATIC_INLINE uint32_t ll_dma_get_source_peripheral(dma_regs_t *DMAx, uint32_t channel)
1502 {
1503 return READ_BITS(DMAx->CHANNEL[channel].CTL_HI, DMA_CFGH_SRC_PER) >> DMA_CFGH_SRC_PER_Pos;
1504 }
1505
1506 /**
1507 * @brief Set destination peripheral for DMA instance on Channel x.
1508 *
1509 * Register|BitsName
1510 * --------|--------
1511 * CFG_HI | DST_PER
1512 *
1513 * @param DMAx DMAx instance
1514 * @param channel This parameter can be one of the following values:
1515 * @arg @ref LL_DMA_CHANNEL_0
1516 * @arg @ref LL_DMA_CHANNEL_1
1517 * @arg @ref LL_DMA_CHANNEL_2
1518 * @arg @ref LL_DMA_CHANNEL_3
1519 * @arg @ref LL_DMA_CHANNEL_4
1520 * @arg @ref LL_DMA_CHANNEL_5
1521 * @arg @ref LL_DMA_CHANNEL_6
1522 * @arg @ref LL_DMA_CHANNEL_7
1523 * @param peripheral This parameter can be one of the following values:
1524 * @arg @ref LL_DMA_PERIPH_SPIM_TX
1525 * @arg @ref LL_DMA_PERIPH_SPIM_RX
1526 * @arg @ref LL_DMA_PERIPH_SPIS_TX
1527 * @arg @ref LL_DMA_PERIPH_SPIS_RX
1528 * @arg @ref LL_DMA_PERIPH_QSPI0_TX
1529 * @arg @ref LL_DMA_PERIPH_QSPI0_RX
1530 * @arg @ref LL_DMA_PERIPH_I2C0_TX
1531 * @arg @ref LL_DMA_PERIPH_I2C0_RX
1532 * @arg @ref LL_DMA_PERIPH_I2C1_TX
1533 * @arg @ref LL_DMA_PERIPH_I2C1_RX
1534 * @arg @ref LL_DMA_PERIPH_I2S_S_TX
1535 * @arg @ref LL_DMA_PERIPH_I2S_S_RX
1536 * @arg @ref LL_DMA_PERIPH_UART0_TX
1537 * @arg @ref LL_DMA_PERIPH_UART0_RX
1538 * @arg @ref LL_DMA_PERIPH_QSPI1_TX
1539 * @arg @ref LL_DMA_PERIPH_QSPI1_RX
1540 * @arg @ref LL_DMA_PERIPH_I2S_M_TX
1541 * @arg @ref LL_DMA_PERIPH_I2S_M_RX
1542 * @arg @ref LL_DMA_PERIPH_SNSADC
1543 * @retval None
1544 */
ll_dma_set_destination_peripheral(dma_regs_t * DMAx,uint32_t channel,uint32_t peripheral)1545 __STATIC_INLINE void ll_dma_set_destination_peripheral(dma_regs_t *DMAx, uint32_t channel, uint32_t peripheral)
1546 {
1547 MODIFY_REG(DMAx->CHANNEL[channel].CFG_HI, DMA_CFGH_DST_PER, (peripheral << DMA_CFGH_DST_PER_Pos));
1548 }
1549
1550 /**
1551 * @brief Get destination peripheral for DMA instance on Channel x.
1552 *
1553 * Register|BitsName
1554 * --------|--------
1555 * CFG_HI | DST_PER
1556 *
1557 * @param DMAx DMAx instance
1558 * @param channel This parameter can be one of the following values:
1559 * @arg @ref LL_DMA_CHANNEL_0
1560 * @arg @ref LL_DMA_CHANNEL_1
1561 * @arg @ref LL_DMA_CHANNEL_2
1562 * @arg @ref LL_DMA_CHANNEL_3
1563 * @arg @ref LL_DMA_CHANNEL_4
1564 * @arg @ref LL_DMA_CHANNEL_5
1565 * @arg @ref LL_DMA_CHANNEL_6
1566 * @arg @ref LL_DMA_CHANNEL_7
1567 * @retval Returned value can be one of the following values:
1568 * @arg @ref LL_DMA_PERIPH_SPIM_TX
1569 * @arg @ref LL_DMA_PERIPH_SPIM_RX
1570 * @arg @ref LL_DMA_PERIPH_SPIS_TX
1571 * @arg @ref LL_DMA_PERIPH_SPIS_RX
1572 * @arg @ref LL_DMA_PERIPH_QSPI0_TX
1573 * @arg @ref LL_DMA_PERIPH_QSPI0_RX
1574 * @arg @ref LL_DMA_PERIPH_I2C0_TX
1575 * @arg @ref LL_DMA_PERIPH_I2C0_RX
1576 * @arg @ref LL_DMA_PERIPH_I2C1_TX
1577 * @arg @ref LL_DMA_PERIPH_I2C1_RX
1578 * @arg @ref LL_DMA_PERIPH_I2S_S_TX
1579 * @arg @ref LL_DMA_PERIPH_I2S_S_RX
1580 * @arg @ref LL_DMA_PERIPH_UART0_TX
1581 * @arg @ref LL_DMA_PERIPH_UART0_RX
1582 * @arg @ref LL_DMA_PERIPH_QSPI1_TX
1583 * @arg @ref LL_DMA_PERIPH_QSPI1_RX
1584 * @arg @ref LL_DMA_PERIPH_I2S_M_TX
1585 * @arg @ref LL_DMA_PERIPH_I2S_M_RX
1586 * @arg @ref LL_DMA_PERIPH_SNSADC
1587 */
ll_dma_get_destination_peripheral(dma_regs_t * DMAx,uint32_t channel)1588 __STATIC_INLINE uint32_t ll_dma_get_destination_peripheral(dma_regs_t *DMAx, uint32_t channel)
1589 {
1590 return READ_BITS(DMAx->CHANNEL[channel].CTL_HI, DMA_CFGH_DST_PER) >> DMA_CFGH_DST_PER_Pos;
1591 }
1592
1593 /**
1594 * @brief Set source and destination source handshaking interface.
1595 *
1596 * Register|BitsName
1597 * --------|--------
1598 * CFG_HI | DST_PER
1599 *
1600 * @param DMAx DMAx instance
1601 * @param channel This parameter can be one of the following values:
1602 * @arg @ref LL_DMA_CHANNEL_0
1603 * @arg @ref LL_DMA_CHANNEL_1
1604 * @arg @ref LL_DMA_CHANNEL_2
1605 * @arg @ref LL_DMA_CHANNEL_3
1606 * @arg @ref LL_DMA_CHANNEL_4
1607 * @arg @ref LL_DMA_CHANNEL_5
1608 * @arg @ref LL_DMA_CHANNEL_6
1609 * @arg @ref LL_DMA_CHANNEL_7
1610 * @param src_handshaking This parameter can be one of the following values:
1611 * @arg @ref LL_DMA_SHANDSHAKING_HW
1612 * @arg @ref LL_DMA_SHANDSHAKING_HW
1613 * @param dst_handshaking This parameter can be one of the following values:
1614 * @arg @ref LL_DMA_DHANDSHAKING_HW
1615 * @arg @ref LL_DMA_DHANDSHAKING_HW
1616 * @retval None
1617 */
ll_dma_select_handshaking(dma_regs_t * DMAx,uint32_t channel,uint32_t src_handshaking,uint32_t dst_handshaking)1618 __STATIC_INLINE void ll_dma_select_handshaking(dma_regs_t *DMAx, uint32_t channel,
1619 uint32_t src_handshaking, uint32_t dst_handshaking)
1620 {
1621 MODIFY_REG(DMAx->CHANNEL[channel].CFG_LO, DMA_CFGL_HS_SEL_SRC | DMA_CFGL_HS_SEL_DST,
1622 src_handshaking | dst_handshaking);
1623 }
1624
1625 /**
1626 * @brief Source Single Transaction Request.
1627 *
1628 * Register|BitsName
1629 * --------|--------
1630 * SGL_REQ_SRC | REQ_SRC_WE&REQ_SRC
1631 * REQ_SRC | SRC_WE&SRC
1632 *
1633 * @param DMAx DMA instance.
1634 * @param channel This parameter can be one of the following values:
1635 * @arg @ref LL_DMA_CHANNEL_0
1636 * @arg @ref LL_DMA_CHANNEL_1
1637 * @arg @ref LL_DMA_CHANNEL_2
1638 * @arg @ref LL_DMA_CHANNEL_3
1639 * @arg @ref LL_DMA_CHANNEL_4
1640 * @arg @ref LL_DMA_CHANNEL_5
1641 * @arg @ref LL_DMA_CHANNEL_6
1642 * @arg @ref LL_DMA_CHANNEL_7
1643 * @retval None
1644 */
ll_dma_req_src_single_transaction(dma_regs_t * DMAx,uint32_t channel)1645 __STATIC_INLINE void ll_dma_req_src_single_transaction(dma_regs_t *DMAx, uint32_t channel)
1646 {
1647 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_SRC, (1 << (channel + DMA_SGL_REQ_SRC_WE_Pos)) + (1 << channel));
1648 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
1649 }
1650
1651 /**
1652 * @brief Source Burst Transaction Request.
1653 *
1654 * Register|BitsName
1655 * --------|--------
1656 * REQ_SRC | SRC_WE&SRC
1657 *
1658 * @param DMAx DMA instance.
1659 * @param channel This parameter can be one of the following values:
1660 * @arg @ref LL_DMA_CHANNEL_0
1661 * @arg @ref LL_DMA_CHANNEL_1
1662 * @arg @ref LL_DMA_CHANNEL_2
1663 * @arg @ref LL_DMA_CHANNEL_3
1664 * @arg @ref LL_DMA_CHANNEL_4
1665 * @arg @ref LL_DMA_CHANNEL_5
1666 * @arg @ref LL_DMA_CHANNEL_6
1667 * @arg @ref LL_DMA_CHANNEL_7
1668 * @retval None
1669 */
ll_dma_req_src_burst_transaction(dma_regs_t * DMAx,uint32_t channel)1670 __STATIC_INLINE void ll_dma_req_src_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
1671 {
1672 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
1673 }
1674
1675 /**
1676 * @brief Source Last Single Transaction Request.
1677 *
1678 * Register|BitsName
1679 * --------|--------
1680 * SGL_REQ_SRC | REQ_SRC_WE&REQ_SRC
1681 * LST_SRC | LST_SRC_WE&LST_SRC
1682 * REQ_SRC | SRC_WE&SRC
1683 *
1684 * @param DMAx DMA instance.
1685 * @param channel This parameter can be one of the following values:
1686 * @arg @ref LL_DMA_CHANNEL_0
1687 * @arg @ref LL_DMA_CHANNEL_1
1688 * @arg @ref LL_DMA_CHANNEL_2
1689 * @arg @ref LL_DMA_CHANNEL_3
1690 * @arg @ref LL_DMA_CHANNEL_4
1691 * @arg @ref LL_DMA_CHANNEL_5
1692 * @arg @ref LL_DMA_CHANNEL_6
1693 * @arg @ref LL_DMA_CHANNEL_7
1694 * @retval None
1695 */
ll_dma_req_src_last_single_transaction(dma_regs_t * DMAx,uint32_t channel)1696 __STATIC_INLINE void ll_dma_req_src_last_single_transaction(dma_regs_t *DMAx, uint32_t channel)
1697 {
1698 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_SRC, (1 << (channel + DMA_SGL_REQ_SRC_WE_Pos)) + (1 << channel));
1699 WRITE_REG(DMAx->HANDSHAKE.LST_SRC, (1 << (channel + DMA_LST_SRC_WE_Pos)) + (1 << channel));
1700 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
1701 }
1702
1703 /**
1704 * @brief Source Last Burst Transaction Request.
1705 *
1706 * Register|BitsName
1707 * --------|--------
1708 * LST_SRC | LST_SRC_WE&LST_SRC
1709 * REQ_SRC | SRC_WE&SRC
1710 *
1711 * @param DMAx DMA instance.
1712 * @param channel This parameter can be one of the following values:
1713 * @arg @ref LL_DMA_CHANNEL_0
1714 * @arg @ref LL_DMA_CHANNEL_1
1715 * @arg @ref LL_DMA_CHANNEL_2
1716 * @arg @ref LL_DMA_CHANNEL_3
1717 * @arg @ref LL_DMA_CHANNEL_4
1718 * @arg @ref LL_DMA_CHANNEL_5
1719 * @arg @ref LL_DMA_CHANNEL_6
1720 * @arg @ref LL_DMA_CHANNEL_7
1721 * @retval None
1722 */
ll_dma_req_src_last_burst_transaction(dma_regs_t * DMAx,uint32_t channel)1723 __STATIC_INLINE void ll_dma_req_src_last_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
1724 {
1725 WRITE_REG(DMAx->HANDSHAKE.LST_SRC, (1 << (channel + DMA_LST_SRC_WE_Pos)) + (1 << channel));
1726 WRITE_REG(DMAx->HANDSHAKE.REQ_SRC, (1 << (channel + DMA_REQ_SRC_WE_Pos)) + (1 << channel));
1727 }
1728
1729 /**
1730 * @brief Destination Single Transaction Request.
1731 *
1732 * Register|BitsName
1733 * --------|--------
1734 * SGL_REQ_DST | REQ_DST_WE&REQ_DST
1735 * REQ_DST | DST_WE&DST
1736 *
1737 * @param DMAx DMA instance.
1738 * @param channel This parameter can be one of the following values:
1739 * @arg @ref LL_DMA_CHANNEL_0
1740 * @arg @ref LL_DMA_CHANNEL_1
1741 * @arg @ref LL_DMA_CHANNEL_2
1742 * @arg @ref LL_DMA_CHANNEL_3
1743 * @arg @ref LL_DMA_CHANNEL_4
1744 * @arg @ref LL_DMA_CHANNEL_5
1745 * @arg @ref LL_DMA_CHANNEL_6
1746 * @arg @ref LL_DMA_CHANNEL_7
1747 * @retval None
1748 */
ll_dma_req_dst_single_transaction(dma_regs_t * DMAx,uint32_t channel)1749 __STATIC_INLINE void ll_dma_req_dst_single_transaction(dma_regs_t *DMAx, uint32_t channel)
1750 {
1751 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_DST, (1 << (channel + DMA_SGL_REQ_DST_WE_Pos)) + (1 << channel));
1752 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
1753 }
1754
1755 /**
1756 * @brief Destination Burst Transaction Request.
1757 *
1758 * Register|BitsName
1759 * --------|--------
1760 * REQ_DST | DST_WE&DST
1761 *
1762 * @param DMAx DMA instance.
1763 * @param channel This parameter can be one of the following values:
1764 * @arg @ref LL_DMA_CHANNEL_0
1765 * @arg @ref LL_DMA_CHANNEL_1
1766 * @arg @ref LL_DMA_CHANNEL_2
1767 * @arg @ref LL_DMA_CHANNEL_3
1768 * @arg @ref LL_DMA_CHANNEL_4
1769 * @arg @ref LL_DMA_CHANNEL_5
1770 * @arg @ref LL_DMA_CHANNEL_6
1771 * @arg @ref LL_DMA_CHANNEL_7
1772 * @retval None
1773 */
ll_dma_req_dst_burst_transaction(dma_regs_t * DMAx,uint32_t channel)1774 __STATIC_INLINE void ll_dma_req_dst_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
1775 {
1776 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
1777 }
1778
1779 /**
1780 * @brief Destination Last Single Transaction Request.
1781 *
1782 * Register|BitsName
1783 * --------|--------
1784 * SGL_REQ_DST | REQ_DST_WE&REQ_DST
1785 * LST_DST | LST_DST_WE&LST_DST
1786 * REQ_DST | DST_WE&DST
1787 *
1788 * @param DMAx DMA instance.
1789 * @param channel This parameter can be one of the following values:
1790 * @arg @ref LL_DMA_CHANNEL_0
1791 * @arg @ref LL_DMA_CHANNEL_1
1792 * @arg @ref LL_DMA_CHANNEL_2
1793 * @arg @ref LL_DMA_CHANNEL_3
1794 * @arg @ref LL_DMA_CHANNEL_4
1795 * @arg @ref LL_DMA_CHANNEL_5
1796 * @arg @ref LL_DMA_CHANNEL_6
1797 * @arg @ref LL_DMA_CHANNEL_7
1798 * @retval None
1799 */
ll_dma_req_dst_last_single_transaction(dma_regs_t * DMAx,uint32_t channel)1800 __STATIC_INLINE void ll_dma_req_dst_last_single_transaction(dma_regs_t *DMAx, uint32_t channel)
1801 {
1802 WRITE_REG(DMAx->HANDSHAKE.SGL_RQ_DST, (1 << (channel + DMA_SGL_REQ_DST_WE_Pos)) + (1 << channel));
1803 WRITE_REG(DMAx->HANDSHAKE.LST_DST, (1 << (channel + DMA_LST_DST_WE_Pos)) + (1 << channel));
1804 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
1805 }
1806
1807 /**
1808 * @brief Destination Last Burst Transaction Request.
1809 *
1810 * Register|BitsName
1811 * --------|--------
1812 * LST_DST | LST_DST_WE&LST_DST
1813 * REQ_DST | DST_WE&DST
1814 *
1815 * @param DMAx DMA instance.
1816 * @param channel This parameter can be one of the following values:
1817 * @arg @ref LL_DMA_CHANNEL_0
1818 * @arg @ref LL_DMA_CHANNEL_1
1819 * @arg @ref LL_DMA_CHANNEL_2
1820 * @arg @ref LL_DMA_CHANNEL_3
1821 * @arg @ref LL_DMA_CHANNEL_4
1822 * @arg @ref LL_DMA_CHANNEL_5
1823 * @arg @ref LL_DMA_CHANNEL_6
1824 * @arg @ref LL_DMA_CHANNEL_7
1825 * @retval None
1826 */
ll_dma_req_dst_last_burst_transaction(dma_regs_t * DMAx,uint32_t channel)1827 __STATIC_INLINE void ll_dma_req_dst_last_burst_transaction(dma_regs_t *DMAx, uint32_t channel)
1828 {
1829 WRITE_REG(DMAx->HANDSHAKE.LST_DST, (1 << (channel + DMA_LST_DST_WE_Pos)) + (1 << channel));
1830 WRITE_REG(DMAx->HANDSHAKE.REQ_DST, (1 << (channel + DMA_REQ_DST_WE_Pos)) + (1 << channel));
1831 }
1832
1833 /** @} */
1834
1835 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
1836 * @{
1837 */
1838
1839 /**
1840 * @brief Get DMA Module global transfer complete interrupt status.
1841 *
1842 * Register|BitsName
1843 * --------|--------
1844 * STATUS_INT | TFR
1845 *
1846 * @param DMAx DMAx instance
1847 * @retval State of bit (1 or 0).
1848 */
ll_dma_is_active_flag_gtfr(dma_regs_t * DMAx)1849 __STATIC_INLINE uint32_t ll_dma_is_active_flag_gtfr(dma_regs_t *DMAx)
1850 {
1851 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_TFR) == DMA_STAT_INT_TFR);
1852 }
1853
1854 /**
1855 * @brief Get DMA Module global block complete interrupt status.
1856 *
1857 * Register|BitsName
1858 * --------|--------
1859 * STATUS_INT | BLOCK
1860 *
1861 * @param DMAx DMAx instance
1862 * @retval State of bit (1 or 0).
1863 */
ll_dma_is_active_flag_gblk(dma_regs_t * DMAx)1864 __STATIC_INLINE uint32_t ll_dma_is_active_flag_gblk(dma_regs_t *DMAx)
1865 {
1866 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_BLK) == DMA_STAT_INT_BLK);
1867 }
1868
1869 /**
1870 * @brief Get DMA Module global source transaction complete interrupt status.
1871 *
1872 * Register|BitsName
1873 * --------|--------
1874 * STATUS_INT | SRCT
1875 *
1876 * @param DMAx DMAx instance
1877 * @retval State of bit (1 or 0).
1878 */
ll_dma_is_active_flag_gsrct(dma_regs_t * DMAx)1879 __STATIC_INLINE uint32_t ll_dma_is_active_flag_gsrct(dma_regs_t *DMAx)
1880 {
1881 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_SRC) == DMA_STAT_INT_SRC);
1882 }
1883
1884 /**
1885 * @brief Get DMA Module global destination transaction complete interrupt status.
1886 *
1887 * Register|BitsName
1888 * --------|--------
1889 * STATUS_INT | DSTT
1890 *
1891 * @param DMAx DMAx instance
1892 * @retval State of bit (1 or 0).
1893 */
ll_dma_is_active_flag_gdstt(dma_regs_t * DMAx)1894 __STATIC_INLINE uint32_t ll_dma_is_active_flag_gdstt(dma_regs_t *DMAx)
1895 {
1896 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_DST) == DMA_STAT_INT_DST);
1897 }
1898
1899 /**
1900 * @brief Get DMA Module global error interrupt status.
1901 *
1902 * Register|BitsName
1903 * --------|--------
1904 * STATUS_INT | ERR
1905 *
1906 * @param DMAx DMAx instance
1907 * @retval State of bit (1 or 0).
1908 */
ll_dma_is_active_flag_gerr(dma_regs_t * DMAx)1909 __STATIC_INLINE uint32_t ll_dma_is_active_flag_gerr(dma_regs_t *DMAx)
1910 {
1911 return (READ_BITS(DMAx->EVENT.STATUS_EVT, DMA_STAT_INT_ERR) == DMA_STAT_INT_ERR);
1912 }
1913
1914 /**
1915 * @brief Indicate the Raw Status of IntTfr Interrupt flag.
1916 *
1917 * Register|BitsName
1918 * --------|--------
1919 * RAW_TFR | RAW
1920 *
1921 * @param DMAx DMAx instance
1922 * @param channel This parameter can be one of the following values:
1923 * @arg @ref LL_DMA_CHANNEL_0
1924 * @arg @ref LL_DMA_CHANNEL_1
1925 * @arg @ref LL_DMA_CHANNEL_2
1926 * @arg @ref LL_DMA_CHANNEL_3
1927 * @arg @ref LL_DMA_CHANNEL_4
1928 * @arg @ref LL_DMA_CHANNEL_5
1929 * @arg @ref LL_DMA_CHANNEL_6
1930 * @arg @ref LL_DMA_CHANNEL_7
1931 * @retval State of bit (1 or 0).
1932 */
ll_dma_is_active_flag_rtfr(dma_regs_t * DMAx,uint32_t channel)1933 __STATIC_INLINE uint32_t ll_dma_is_active_flag_rtfr(dma_regs_t *DMAx, uint32_t channel)
1934 {
1935 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[0], (1 << channel)) == (1 << channel));
1936 }
1937
1938 /**
1939 * @brief Indicate the Raw Status of IntBlock Interrupt flag.
1940 *
1941 * Register|BitsName
1942 * --------|--------
1943 * RAW_BLK | RAW
1944 *
1945 * @param DMAx DMAx instance
1946 * @param channel This parameter can be one of the following values:
1947 * @arg @ref LL_DMA_CHANNEL_0
1948 * @arg @ref LL_DMA_CHANNEL_1
1949 * @arg @ref LL_DMA_CHANNEL_2
1950 * @arg @ref LL_DMA_CHANNEL_3
1951 * @arg @ref LL_DMA_CHANNEL_4
1952 * @arg @ref LL_DMA_CHANNEL_5
1953 * @arg @ref LL_DMA_CHANNEL_6
1954 * @arg @ref LL_DMA_CHANNEL_7
1955 * @retval State of bit (1 or 0).
1956 */
ll_dma_is_active_flag_rblk(dma_regs_t * DMAx,uint32_t channel)1957 __STATIC_INLINE uint32_t ll_dma_is_active_flag_rblk(dma_regs_t *DMAx, uint32_t channel)
1958 {
1959 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[ITEM_2], (1 << channel)) == (1 << channel));
1960 }
1961
1962 /**
1963 * @brief Indicate the Raw Status of IntSrcTran Interrupt flag.
1964 *
1965 * Register|BitsName
1966 * --------|--------
1967 * RAW_SRC_TRN | RAW
1968 *
1969 * @param DMAx DMAx instance
1970 * @param channel This parameter can be one of the following values:
1971 * @arg @ref LL_DMA_CHANNEL_0
1972 * @arg @ref LL_DMA_CHANNEL_1
1973 * @arg @ref LL_DMA_CHANNEL_2
1974 * @arg @ref LL_DMA_CHANNEL_3
1975 * @arg @ref LL_DMA_CHANNEL_4
1976 * @arg @ref LL_DMA_CHANNEL_5
1977 * @arg @ref LL_DMA_CHANNEL_6
1978 * @arg @ref LL_DMA_CHANNEL_7
1979 * @retval State of bit (1 or 0).
1980 */
ll_dma_is_active_flag_rsrct(dma_regs_t * DMAx,uint32_t channel)1981 __STATIC_INLINE uint32_t ll_dma_is_active_flag_rsrct(dma_regs_t *DMAx, uint32_t channel)
1982 {
1983 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[ITEM_4], (1 << channel)) == (1 << channel));
1984 }
1985
1986 /**
1987 * @brief Indicate the Raw Status of IntDstTran Interrupt flag.
1988 *
1989 * Register|BitsName
1990 * --------|--------
1991 * RAW_DST_TRN | RAW
1992 *
1993 * @param DMAx DMAx instance
1994 * @param channel This parameter can be one of the following values:
1995 * @arg @ref LL_DMA_CHANNEL_0
1996 * @arg @ref LL_DMA_CHANNEL_1
1997 * @arg @ref LL_DMA_CHANNEL_2
1998 * @arg @ref LL_DMA_CHANNEL_3
1999 * @arg @ref LL_DMA_CHANNEL_4
2000 * @arg @ref LL_DMA_CHANNEL_5
2001 * @arg @ref LL_DMA_CHANNEL_6
2002 * @arg @ref LL_DMA_CHANNEL_7
2003 * @retval State of bit (1 or 0).
2004 */
ll_dma_is_active_flag_rdstt(dma_regs_t * DMAx,uint32_t channel)2005 __STATIC_INLINE uint32_t ll_dma_is_active_flag_rdstt(dma_regs_t *DMAx, uint32_t channel)
2006 {
2007 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[ITEM_6], (1 << channel)) == (1 << channel));
2008 }
2009
2010 /**
2011 * @brief Indicate the Raw Status of IntErr Interrupt flag.
2012 *
2013 * Register|BitsName
2014 * --------|--------
2015 * RAW_ERR | RAW
2016 *
2017 * @param DMAx DMAx instance
2018 * @param channel This parameter can be one of the following values:
2019 * @arg @ref LL_DMA_CHANNEL_0
2020 * @arg @ref LL_DMA_CHANNEL_1
2021 * @arg @ref LL_DMA_CHANNEL_2
2022 * @arg @ref LL_DMA_CHANNEL_3
2023 * @arg @ref LL_DMA_CHANNEL_4
2024 * @arg @ref LL_DMA_CHANNEL_5
2025 * @arg @ref LL_DMA_CHANNEL_6
2026 * @arg @ref LL_DMA_CHANNEL_7
2027 * @retval State of bit (1 or 0).
2028 */
ll_dma_is_active_flag_rerr(dma_regs_t * DMAx,uint32_t channel)2029 __STATIC_INLINE uint32_t ll_dma_is_active_flag_rerr(dma_regs_t *DMAx, uint32_t channel)
2030 {
2031 return (READ_BITS(DMAx->EVENT.RAW_CH_EVT[ITEM_8], (1 << channel)) == (1 << channel));
2032 }
2033
2034 /**
2035 * @brief Indicate the status of DMA Channel transfer complete flag.
2036 *
2037 * Register|BitsName
2038 * --------|--------
2039 * STAT_TFR | STATUS
2040 *
2041 * @param DMAx DMAx instance
2042 * @param channel This parameter can be one of the following values:
2043 * @arg @ref LL_DMA_CHANNEL_0
2044 * @arg @ref LL_DMA_CHANNEL_1
2045 * @arg @ref LL_DMA_CHANNEL_2
2046 * @arg @ref LL_DMA_CHANNEL_3
2047 * @arg @ref LL_DMA_CHANNEL_4
2048 * @arg @ref LL_DMA_CHANNEL_5
2049 * @arg @ref LL_DMA_CHANNEL_6
2050 * @arg @ref LL_DMA_CHANNEL_7
2051 * @retval State of bit (1 or 0).
2052 */
ll_dma_is_active_flag_tfr(dma_regs_t * DMAx,uint32_t channel)2053 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr(dma_regs_t *DMAx, uint32_t channel)
2054 {
2055 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << channel)) == (1 << channel));
2056 }
2057
2058 /**
2059 * @brief Indicate the status of Channel 0 transfer complete flag.
2060 *
2061 * Register|BitsName
2062 * --------|--------
2063 * STAT_TFR | STATUS
2064 *
2065 * @param DMAx DMAx instance
2066 * @retval State of bit (1 or 0).
2067 */
ll_dma_is_active_flag_tfr0(dma_regs_t * DMAx)2068 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr0(dma_regs_t *DMAx)
2069 {
2070 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 0)) == (1 << 0));
2071 }
2072
2073 /**
2074 * @brief Indicate the status of Channel 1 transfer complete flag.
2075 *
2076 * Register|BitsName
2077 * --------|--------
2078 * STAT_TFR | STATUS
2079 *
2080 * @param DMAx DMAx instance
2081 * @retval State of bit (1 or 0).
2082 */
ll_dma_is_active_flag_tfr1(dma_regs_t * DMAx)2083 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr1(dma_regs_t *DMAx)
2084 {
2085 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << 1)) == (1 << 1));
2086 }
2087
2088 /**
2089 * @brief Indicate the status of Channel 2 transfer complete flag.
2090 *
2091 * Register|BitsName
2092 * --------|--------
2093 * STAT_TFR | STATUS
2094 *
2095 * @param DMAx DMAx instance
2096 * @retval State of bit (1 or 0).
2097 */
ll_dma_is_active_flag_tfr2(dma_regs_t * DMAx)2098 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr2(dma_regs_t *DMAx)
2099 {
2100 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << ITEM_2)) == (1 << ITEM_2));
2101 }
2102
2103 /**
2104 * @brief Indicate the status of Channel 3 transfer complete flag.
2105 *
2106 * Register|BitsName
2107 * --------|--------
2108 * STAT_TFR | STATUS
2109 *
2110 * @param DMAx DMAx instance
2111 * @retval State of bit (1 or 0).
2112 */
ll_dma_is_active_flag_tfr3(dma_regs_t * DMAx)2113 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr3(dma_regs_t *DMAx)
2114 {
2115 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << ITEM_3)) == (1 << ITEM_3));
2116 }
2117
2118 /**
2119 * @brief Indicate the status of Channel 4 transfer complete flag.
2120 *
2121 * Register|BitsName
2122 * --------|--------
2123 * STAT_TFR | STATUS
2124 *
2125 * @param DMAx DMAx instance
2126 * @retval State of bit (1 or 0).
2127 */
ll_dma_is_active_flag_tfr4(dma_regs_t * DMAx)2128 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr4(dma_regs_t *DMAx)
2129 {
2130 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << ITEM_4)) == (1 << ITEM_4));
2131 }
2132
2133 /**
2134 * @brief Indicate the status of Channel 5 transfer complete flag.
2135 *
2136 * Register|BitsName
2137 * --------|--------
2138 * STAT_TFR | STATUS
2139 *
2140 * @param DMAx DMAx instance
2141 * @retval State of bit (1 or 0).
2142 */
ll_dma_is_active_flag_tfr5(dma_regs_t * DMAx)2143 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr5(dma_regs_t *DMAx)
2144 {
2145 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << ITEM_5)) == (1 << ITEM_5));
2146 }
2147
2148 /**
2149 * @brief Indicate the status of Channel 6 transfer complete flag.
2150 *
2151 * Register|BitsName
2152 * --------|--------
2153 * STAT_TFR | STATUS
2154 *
2155 * @param DMAx DMAx instance
2156 * @retval State of bit (1 or 0).
2157 */
ll_dma_is_active_flag_tfr6(dma_regs_t * DMAx)2158 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr6(dma_regs_t *DMAx)
2159 {
2160 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << ITEM_6)) == (1 << ITEM_6));
2161 }
2162
2163 /**
2164 * @brief Indicate the status of Channel 7 transfer complete flag.
2165 *
2166 * Register|BitsName
2167 * --------|--------
2168 * STAT_TFR | STATUS
2169 *
2170 * @param DMAx DMAx instance
2171 * @retval State of bit (1 or 0).
2172 */
ll_dma_is_active_flag_tfr7(dma_regs_t * DMAx)2173 __STATIC_INLINE uint32_t ll_dma_is_active_flag_tfr7(dma_regs_t *DMAx)
2174 {
2175 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[0], (1 << ITEM_7)) == (1 << ITEM_7));
2176 }
2177
2178 /**
2179 * @brief Indicate the status of DMA Channel block complete flag.
2180 *
2181 * Register|BitsName
2182 * --------|--------
2183 * STAT_BLK | STATUS
2184 *
2185 * @param DMAx DMAx instance
2186 * @param channel This parameter can be one of the following values:
2187 * @arg @ref LL_DMA_CHANNEL_0
2188 * @arg @ref LL_DMA_CHANNEL_1
2189 * @arg @ref LL_DMA_CHANNEL_2
2190 * @arg @ref LL_DMA_CHANNEL_3
2191 * @arg @ref LL_DMA_CHANNEL_4
2192 * @arg @ref LL_DMA_CHANNEL_5
2193 * @arg @ref LL_DMA_CHANNEL_6
2194 * @arg @ref LL_DMA_CHANNEL_7
2195 * @retval State of bit (1 or 0).
2196 */
ll_dma_is_active_flag_blk(dma_regs_t * DMAx,uint32_t channel)2197 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk(dma_regs_t *DMAx, uint32_t channel)
2198 {
2199 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[ITEM_2], (1 << channel)) == (1 << channel));
2200 }
2201
2202 /**
2203 * @brief Indicate the status of Channel 0 block complete flag.
2204 *
2205 * Register|BitsName
2206 * --------|--------
2207 * STAT_BLK | STATUS
2208 *
2209 * @param DMAx DMAx instance
2210 * @retval State of bit (1 or 0).
2211 */
ll_dma_is_active_flag_blk0(dma_regs_t * DMAx)2212 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk0(dma_regs_t *DMAx)
2213 {
2214 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[ITEM_2], (1 << 0)) == (1 << 0));
2215 }
2216
2217 /**
2218 * @brief Indicate the status of Channel 1 block complete flag.
2219 *
2220 * Register|BitsName
2221 * --------|--------
2222 * STAT_BLK | STATUS
2223 *
2224 * @param DMAx DMAx instance
2225 * @retval State of bit (1 or 0).
2226 */
ll_dma_is_active_flag_blk1(dma_regs_t * DMAx)2227 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk1(dma_regs_t *DMAx)
2228 {
2229 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[ITEM_2], (1 << 1)) == (1 << 1));
2230 }
2231
2232 /**
2233 * @brief Indicate the status of Channel 2 block complete flag.
2234 *
2235 * Register|BitsName
2236 * --------|--------
2237 * STAT_BLK | STATUS
2238 *
2239 * @param DMAx DMAx instance
2240 * @retval State of bit (1 or 0).
2241 */
ll_dma_is_active_flag_blk2(dma_regs_t * DMAx)2242 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk2(dma_regs_t *DMAx)
2243 {
2244 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[ITEM_2], (1 << ITEM_2)) == (1 << ITEM_2));
2245 }
2246
2247 /**
2248 * @brief Indicate the status of Channel 3 block complete flag.
2249 *
2250 * Register|BitsName
2251 * --------|--------
2252 * STAT_BLK | STATUS
2253 *
2254 * @param DMAx DMAx instance
2255 * @retval State of bit (1 or 0).
2256 */
ll_dma_is_active_flag_blk3(dma_regs_t * DMAx)2257 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk3(dma_regs_t *DMAx)
2258 {
2259 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[ITEM_2], (1 << ITEM_3)) == (1 << ITEM_3));
2260 }
2261
2262 /**
2263 * @brief Indicate the status of Channel 4 block complete flag.
2264 *
2265 * Register|BitsName
2266 * --------|--------
2267 * STAT_BLK | STATUS
2268 *
2269 * @param DMAx DMAx instance
2270 * @retval State of bit (1 or 0).
2271 */
ll_dma_is_active_flag_blk4(dma_regs_t * DMAx)2272 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk4(dma_regs_t *DMAx)
2273 {
2274 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[ITEM_2], (1 << ITEM_4)) == (1 << ITEM_4));
2275 }
2276
2277 /**
2278 * @brief Indicate the status of Channel 5 block complete flag.
2279 *
2280 * Register|BitsName
2281 * --------|--------
2282 * STAT_BLK | STATUS
2283 *
2284 * @param DMAx DMAx instance
2285 * @retval State of bit (1 or 0).
2286 */
ll_dma_is_active_flag_blk5(dma_regs_t * DMAx)2287 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk5(dma_regs_t *DMAx)
2288 {
2289 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[ITEM_2], (1 << ITEM_5)) == (1 << ITEM_5));
2290 }
2291
2292 /**
2293 * @brief Indicate the status of Channel 6 block complete flag.
2294 *
2295 * Register|BitsName
2296 * --------|--------
2297 * STAT_BLK | STATUS
2298 *
2299 * @param DMAx DMAx instance
2300 * @retval State of bit (1 or 0).
2301 */
ll_dma_is_active_flag_blk6(dma_regs_t * DMAx)2302 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk6(dma_regs_t *DMAx)
2303 {
2304 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[ITEM_2], (1 << ITEM_6)) == (1 << ITEM_6));
2305 }
2306
2307 /**
2308 * @brief Indicate the status of Channel 7 block complete flag.
2309 *
2310 * Register|BitsName
2311 * --------|--------
2312 * STAT_BLK | STATUS
2313 *
2314 * @param DMAx DMAx instance
2315 * @retval State of bit (1 or 0).
2316 */
ll_dma_is_active_flag_blk7(dma_regs_t * DMAx)2317 __STATIC_INLINE uint32_t ll_dma_is_active_flag_blk7(dma_regs_t *DMAx)
2318 {
2319 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[ITEM_2], (1 << ITEM_7)) == (1 << ITEM_7));
2320 }
2321
2322 /**
2323 * @brief Indicate the status of DMA Channel source transaction complete flag.
2324 *
2325 * Register|BitsName
2326 * --------|--------
2327 * STAT_SRC_TRN | STATUS
2328 *
2329 * @param DMAx DMAx instance
2330 * @param channel This parameter can be one of the following values:
2331 * @arg @ref LL_DMA_CHANNEL_0
2332 * @arg @ref LL_DMA_CHANNEL_1
2333 * @arg @ref LL_DMA_CHANNEL_2
2334 * @arg @ref LL_DMA_CHANNEL_3
2335 * @arg @ref LL_DMA_CHANNEL_4
2336 * @arg @ref LL_DMA_CHANNEL_5
2337 * @arg @ref LL_DMA_CHANNEL_6
2338 * @arg @ref LL_DMA_CHANNEL_7
2339 * @retval State of bit (1 or 0).
2340 */
ll_dma_is_active_flag_srct(dma_regs_t * DMAx,uint32_t channel)2341 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct(dma_regs_t *DMAx, uint32_t channel)
2342 {
2343 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[ITEM_4], (1 << channel)) == (1 << channel));
2344 }
2345
2346 /**
2347 * @brief Indicate the status of Channel 0 source transaction complete flag.
2348 *
2349 * Register|BitsName
2350 * --------|--------
2351 * STAT_SRC_TRN | STATUS
2352 *
2353 * @param DMAx DMAx instance
2354 * @retval State of bit (1 or 0).
2355 */
ll_dma_is_active_flag_srct0(dma_regs_t * DMAx)2356 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct0(dma_regs_t *DMAx)
2357 {
2358 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[ITEM_4], (1 << 0)) == (1 << 0));
2359 }
2360
2361 /**
2362 * @brief Indicate the status of Channel 1 source transaction complete flag.
2363 *
2364 * Register|BitsName
2365 * --------|--------
2366 * STAT_SRC_TRN | STATUS
2367 *
2368 * @param DMAx DMAx instance
2369 * @retval State of bit (1 or 0).
2370 */
ll_dma_is_active_flag_srct1(dma_regs_t * DMAx)2371 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct1(dma_regs_t *DMAx)
2372 {
2373 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[ITEM_4], (1 << 1)) == (1 << 1));
2374 }
2375
2376 /**
2377 * @brief Indicate the status of Channel 2 source transaction complete flag.
2378 *
2379 * Register|BitsName
2380 * --------|--------
2381 * STAT_SRC_TRN | STATUS
2382 *
2383 * @param DMAx DMAx instance
2384 * @retval State of bit (1 or 0).
2385 */
ll_dma_is_active_flag_srct2(dma_regs_t * DMAx)2386 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct2(dma_regs_t *DMAx)
2387 {
2388 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[ITEM_4], (1 << ITEM_2)) == (1 << ITEM_2));
2389 }
2390
2391 /**
2392 * @brief Indicate the status of Channel 3 source transaction complete flag.
2393 *
2394 * Register|BitsName
2395 * --------|--------
2396 * STAT_SRC_TRN | STATUS
2397 *
2398 * @param DMAx DMAx instance
2399 * @retval State of bit (1 or 0).
2400 */
ll_dma_is_active_flag_srct3(dma_regs_t * DMAx)2401 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct3(dma_regs_t *DMAx)
2402 {
2403 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[ITEM_4], (1 << ITEM_3)) == (1 << ITEM_3));
2404 }
2405
2406 /**
2407 * @brief Indicate the status of Channel 4 source transaction complete flag.
2408 *
2409 * Register|BitsName
2410 * --------|--------
2411 * STAT_SRC_TRN | STATUS
2412 *
2413 * @param DMAx DMAx instance
2414 * @retval State of bit (1 or 0).
2415 */
ll_dma_is_active_flag_srct4(dma_regs_t * DMAx)2416 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct4(dma_regs_t *DMAx)
2417 {
2418 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[ITEM_4], (1 << ITEM_4)) == (1 << ITEM_4));
2419 }
2420
2421 /**
2422 * @brief Indicate the status of Channel 5 source transaction complete flag.
2423 *
2424 * Register|BitsName
2425 * --------|--------
2426 * STAT_SRC_TRN | STATUS
2427 *
2428 * @param DMAx DMAx instance
2429 * @retval State of bit (1 or 0).
2430 */
ll_dma_is_active_flag_srct5(dma_regs_t * DMAx)2431 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct5(dma_regs_t *DMAx)
2432 {
2433 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[ITEM_4], (1 << ITEM_5)) == (1 << ITEM_5));
2434 }
2435
2436 /**
2437 * @brief Indicate the status of Channel 6 source transaction complete flag.
2438 *
2439 * Register|BitsName
2440 * --------|--------
2441 * STAT_SRC_TRN | STATUS
2442 *
2443 * @param DMAx DMAx instance
2444 * @retval State of bit (1 or 0).
2445 */
ll_dma_is_active_flag_srct6(dma_regs_t * DMAx)2446 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct6(dma_regs_t *DMAx)
2447 {
2448 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[ITEM_4], (1 << ITEM_6)) == (1 << ITEM_6));
2449 }
2450
2451 /**
2452 * @brief Indicate the status of Channel 7 source transaction complete flag.
2453 *
2454 * Register|BitsName
2455 * --------|--------
2456 * STAT_SRC_TRN | STATUS
2457 *
2458 * @param DMAx DMAx instance
2459 * @retval State of bit (1 or 0).
2460 */
ll_dma_is_active_flag_srct7(dma_regs_t * DMAx)2461 __STATIC_INLINE uint32_t ll_dma_is_active_flag_srct7(dma_regs_t *DMAx)
2462 {
2463 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[ITEM_4], (1 << ITEM_7)) == (1 << ITEM_7));
2464 }
2465
2466 /**
2467 * @brief Indicate the status of DMA Channel destination transaction complete flag.
2468 *
2469 * Register|BitsName
2470 * --------|--------
2471 * STAT_DST_TRN | STATUS
2472 *
2473 * @param DMAx DMAx instance
2474 * @param channel This parameter can be one of the following values:
2475 * @arg @ref LL_DMA_CHANNEL_0
2476 * @arg @ref LL_DMA_CHANNEL_1
2477 * @arg @ref LL_DMA_CHANNEL_2
2478 * @arg @ref LL_DMA_CHANNEL_3
2479 * @arg @ref LL_DMA_CHANNEL_4
2480 * @arg @ref LL_DMA_CHANNEL_5
2481 * @arg @ref LL_DMA_CHANNEL_6
2482 * @arg @ref LL_DMA_CHANNEL_7
2483 * @retval State of bit (1 or 0).
2484 */
ll_dma_is_active_flag_dstt(dma_regs_t * DMAx,uint32_t channel)2485 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt(dma_regs_t *DMAx, uint32_t channel)
2486 {
2487 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[ITEM_6], (1 << channel)) == (1 << channel));
2488 }
2489
2490 /**
2491 * @brief Indicate the status of Channel 0 destination transaction complete flag.
2492 *
2493 * Register|BitsName
2494 * --------|--------
2495 * STAT_DST_TRN | STATUS
2496 *
2497 * @param DMAx DMAx instance
2498 * @retval State of bit (1 or 0).
2499 */
ll_dma_is_active_flag_dstt0(dma_regs_t * DMAx)2500 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt0(dma_regs_t *DMAx)
2501 {
2502 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[ITEM_6], (1 << 0)) == (1 << 0));
2503 }
2504
2505 /**
2506 * @brief Indicate the status of Channel 1 destination transaction complete flag.
2507 *
2508 * Register|BitsName
2509 * --------|--------
2510 * STAT_DST_TRN | STATUS
2511 *
2512 * @param DMAx DMAx instance
2513 * @retval State of bit (1 or 0).
2514 */
ll_dma_is_active_flag_dstt1(dma_regs_t * DMAx)2515 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt1(dma_regs_t *DMAx)
2516 {
2517 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[ITEM_6], (1 << 1)) == (1 << 1));
2518 }
2519
2520 /**
2521 * @brief Indicate the status of Channel 2 destination transaction complete flag.
2522 *
2523 * Register|BitsName
2524 * --------|--------
2525 * STAT_DST_TRN | STATUS
2526 *
2527 * @param DMAx DMAx instance
2528 * @retval State of bit (1 or 0).
2529 */
ll_dma_is_active_flag_dstt2(dma_regs_t * DMAx)2530 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt2(dma_regs_t *DMAx)
2531 {
2532 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[ITEM_6], (1 << ITEM_2)) == (1 << ITEM_2));
2533 }
2534
2535 /**
2536 * @brief Indicate the status of Channel 3 destination transaction complete flag.
2537 *
2538 * Register|BitsName
2539 * --------|--------
2540 * STAT_DST_TRN | STATUS
2541 *
2542 * @param DMAx DMAx instance
2543 * @retval State of bit (1 or 0).
2544 */
ll_dma_is_active_flag_dstt3(dma_regs_t * DMAx)2545 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt3(dma_regs_t *DMAx)
2546 {
2547 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[ITEM_6], (1 << ITEM_3)) == (1 << ITEM_3));
2548 }
2549
2550 /**
2551 * @brief Indicate the status of Channel 4 destination transaction complete flag.
2552 *
2553 * Register|BitsName
2554 * --------|--------
2555 * STAT_DST_TRN | STATUS
2556 *
2557 * @param DMAx DMAx instance
2558 * @retval State of bit (1 or 0).
2559 */
ll_dma_is_active_flag_dstt4(dma_regs_t * DMAx)2560 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt4(dma_regs_t *DMAx)
2561 {
2562 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[ITEM_6], (1 << ITEM_4)) == (1 << ITEM_4));
2563 }
2564
2565 /**
2566 * @brief Indicate the status of Channel 5 destination transaction complete flag.
2567 *
2568 * Register|BitsName
2569 * --------|--------
2570 * STAT_DST_TRN | STATUS
2571 *
2572 * @param DMAx DMAx instance
2573 * @retval State of bit (1 or 0).
2574 */
ll_dma_is_active_flag_dstt5(dma_regs_t * DMAx)2575 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt5(dma_regs_t *DMAx)
2576 {
2577 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[ITEM_6], (1 << ITEM_5)) == (1 << ITEM_5));
2578 }
2579
2580 /**
2581 * @brief Indicate the status of Channel 6 destination transaction complete flag.
2582 *
2583 * Register|BitsName
2584 * --------|--------
2585 * STAT_DST_TRN | STATUS
2586 *
2587 * @param DMAx DMAx instance
2588 * @retval State of bit (1 or 0).
2589 */
ll_dma_is_active_flag_dstt6(dma_regs_t * DMAx)2590 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt6(dma_regs_t *DMAx)
2591 {
2592 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[ITEM_6], (1 << ITEM_6)) == (1 << ITEM_6));
2593 }
2594
2595 /**
2596 * @brief Indicate the status of Channel 7 destination transaction complete flag.
2597 *
2598 * Register|BitsName
2599 * --------|--------
2600 * STAT_DST_TRN | STATUS
2601 *
2602 * @param DMAx DMAx instance
2603 * @retval State of bit (1 or 0).
2604 */
ll_dma_is_active_flag_dstt7(dma_regs_t * DMAx)2605 __STATIC_INLINE uint32_t ll_dma_is_active_flag_dstt7(dma_regs_t *DMAx)
2606 {
2607 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[ITEM_6], (1 << ITEM_7)) == (1 << ITEM_7));
2608 }
2609
2610 /**
2611 * @brief Indicate the status of DMA Channel error flag.
2612 *
2613 * Register|BitsName
2614 * --------|--------
2615 * STAT_ERR | STATUS
2616 *
2617 * @param DMAx DMAx instance
2618 * @param channel This parameter can be one of the following values:
2619 * @arg @ref LL_DMA_CHANNEL_0
2620 * @arg @ref LL_DMA_CHANNEL_1
2621 * @arg @ref LL_DMA_CHANNEL_2
2622 * @arg @ref LL_DMA_CHANNEL_3
2623 * @arg @ref LL_DMA_CHANNEL_4
2624 * @arg @ref LL_DMA_CHANNEL_5
2625 * @arg @ref LL_DMA_CHANNEL_6
2626 * @arg @ref LL_DMA_CHANNEL_7
2627 * @retval State of bit (1 or 0).
2628 */
ll_dma_is_active_flag_err(dma_regs_t * DMAx,uint32_t channel)2629 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err(dma_regs_t *DMAx, uint32_t channel)
2630 {
2631 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[ITEM_8], (1 << channel)) == (1 << channel));
2632 }
2633
2634 /**
2635 * @brief Indicate the status of Channel 0 error flag.
2636 *
2637 * Register|BitsName
2638 * --------|--------
2639 * STAT_ERR | STATUS
2640 *
2641 * @param DMAx DMAx instance
2642 * @retval State of bit (1 or 0).
2643 */
ll_dma_is_active_flag_err0(dma_regs_t * DMAx)2644 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err0(dma_regs_t *DMAx)
2645 {
2646 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[ITEM_8], (1 << 0)) == (1 << 0));
2647 }
2648
2649 /**
2650 * @brief Indicate the status of Channel 1 error flag.
2651 *
2652 * Register|BitsName
2653 * --------|--------
2654 * STAT_ERR | STATUS
2655 *
2656 * @param DMAx DMAx instance
2657 * @retval State of bit (1 or 0).
2658 */
ll_dma_is_active_flag_err1(dma_regs_t * DMAx)2659 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err1(dma_regs_t *DMAx)
2660 {
2661 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[ITEM_8], (1 << 1)) == (1 << 1));
2662 }
2663
2664 /**
2665 * @brief Indicate the status of Channel 2 error flag.
2666 *
2667 * Register|BitsName
2668 * --------|--------
2669 * STAT_ERR | STATUS
2670 *
2671 * @param DMAx DMAx instance
2672 * @retval State of bit (1 or 0).
2673 */
ll_dma_is_active_flag_err2(dma_regs_t * DMAx)2674 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err2(dma_regs_t *DMAx)
2675 {
2676 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[ITEM_8], (1 << ITEM_2)) == (1 << ITEM_2));
2677 }
2678
2679 /**
2680 * @brief Indicate the status of Channel 3 error flag.
2681 *
2682 * Register|BitsName
2683 * --------|--------
2684 * STAT_ERR | STATUS
2685 *
2686 * @param DMAx DMAx instance
2687 * @retval State of bit (1 or 0).
2688 */
ll_dma_is_active_flag_err3(dma_regs_t * DMAx)2689 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err3(dma_regs_t *DMAx)
2690 {
2691 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[ITEM_8], (1 << ITEM_3)) == (1 << ITEM_3));
2692 }
2693
2694 /**
2695 * @brief Indicate the status of Channel 4 error flag.
2696 *
2697 * Register|BitsName
2698 * --------|--------
2699 * STAT_ERR | STATUS
2700 *
2701 * @param DMAx DMAx instance
2702 * @retval State of bit (1 or 0).
2703 */
ll_dma_is_active_flag_err4(dma_regs_t * DMAx)2704 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err4(dma_regs_t *DMAx)
2705 {
2706 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[ITEM_8], (1 << ITEM_4)) == (1 << ITEM_4));
2707 }
2708
2709 /**
2710 * @brief Indicate the status of Channel 5 error flag.
2711 *
2712 * Register|BitsName
2713 * --------|--------
2714 * STAT_ERR | STATUS
2715 *
2716 * @param DMAx DMAx instance
2717 * @retval State of bit (1 or 0).
2718 */
ll_dma_is_active_flag_err5(dma_regs_t * DMAx)2719 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err5(dma_regs_t *DMAx)
2720 {
2721 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[ITEM_8], (1 << ITEM_5)) == (1 << ITEM_5));
2722 }
2723
2724 /**
2725 * @brief Indicate the status of Channel 6 error flag.
2726 *
2727 * Register|BitsName
2728 * --------|--------
2729 * STAT_ERR | STATUS
2730 *
2731 * @param DMAx DMAx instance
2732 * @retval State of bit (1 or 0).
2733 */
ll_dma_is_active_flag_err6(dma_regs_t * DMAx)2734 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err6(dma_regs_t *DMAx)
2735 {
2736 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[ITEM_8], (1 << ITEM_6)) == (1 << ITEM_6));
2737 }
2738
2739 /**
2740 * @brief Indicate the status of Channel 7 error flag.
2741 *
2742 * Register|BitsName
2743 * --------|--------
2744 * STAT_ERR | STATUS
2745 *
2746 * @param DMAx DMAx instance
2747 * @retval State of bit (1 or 0).
2748 */
ll_dma_is_active_flag_err7(dma_regs_t * DMAx)2749 __STATIC_INLINE uint32_t ll_dma_is_active_flag_err7(dma_regs_t *DMAx)
2750 {
2751 return (READ_BITS(DMAx->EVENT.STATUS_CH_EVT[ITEM_8], (1 << ITEM_7)) == (1 << ITEM_7));
2752 }
2753
2754 /**
2755 * @brief Clear DMA Channel transfer complete flag.
2756 *
2757 * Register|BitsName
2758 * --------|--------
2759 * CLR_TFR | CLEAR
2760 *
2761 * @param DMAx DMAx instance
2762 * @param channel This parameter can be one of the following values:
2763 * @arg @ref LL_DMA_CHANNEL_0
2764 * @arg @ref LL_DMA_CHANNEL_1
2765 * @arg @ref LL_DMA_CHANNEL_2
2766 * @arg @ref LL_DMA_CHANNEL_3
2767 * @arg @ref LL_DMA_CHANNEL_4
2768 * @arg @ref LL_DMA_CHANNEL_5
2769 * @arg @ref LL_DMA_CHANNEL_6
2770 * @arg @ref LL_DMA_CHANNEL_7
2771 * @retval None.
2772 */
ll_dma_clear_flag_tfr(dma_regs_t * DMAx,uint32_t channel)2773 __STATIC_INLINE void ll_dma_clear_flag_tfr(dma_regs_t *DMAx, uint32_t channel)
2774 {
2775 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << channel));
2776 }
2777
2778 /**
2779 * @brief Clear Channel 0 transfer complete flag.
2780 *
2781 * Register|BitsName
2782 * --------|--------
2783 * CLR_TFR | CLEAR
2784 *
2785 * @param DMAx DMAx instance
2786 * @retval None.
2787 */
ll_dma_clear_flag_tfr0(dma_regs_t * DMAx)2788 __STATIC_INLINE void ll_dma_clear_flag_tfr0(dma_regs_t *DMAx)
2789 {
2790 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 0));
2791 }
2792
2793 /**
2794 * @brief Clear Channel 1 transfer complete flag.
2795 *
2796 * Register|BitsName
2797 * --------|--------
2798 * CLR_TFR | CLEAR
2799 *
2800 * @param DMAx DMAx instance
2801 * @retval None.
2802 */
ll_dma_clear_flag_tfr1(dma_regs_t * DMAx)2803 __STATIC_INLINE void ll_dma_clear_flag_tfr1(dma_regs_t *DMAx)
2804 {
2805 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << 1));
2806 }
2807
2808 /**
2809 * @brief Clear Channel 2 transfer complete flag.
2810 *
2811 * Register|BitsName
2812 * --------|--------
2813 * CLR_TFR | CLEAR
2814 *
2815 * @param DMAx DMAx instance
2816 * @retval None.
2817 */
ll_dma_clear_flag_tfr2(dma_regs_t * DMAx)2818 __STATIC_INLINE void ll_dma_clear_flag_tfr2(dma_regs_t *DMAx)
2819 {
2820 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << ITEM_2));
2821 }
2822
2823 /**
2824 * @brief Clear Channel 3 transfer complete flag.
2825 *
2826 * Register|BitsName
2827 * --------|--------
2828 * CLR_TFR | CLEAR
2829 *
2830 * @param DMAx DMAx instance
2831 * @retval None.
2832 */
ll_dma_clear_flag_tfr3(dma_regs_t * DMAx)2833 __STATIC_INLINE void ll_dma_clear_flag_tfr3(dma_regs_t *DMAx)
2834 {
2835 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << ITEM_3));
2836 }
2837
2838 /**
2839 * @brief Clear Channel 4 transfer complete flag.
2840 *
2841 * Register|BitsName
2842 * --------|--------
2843 * CLR_TFR | CLEAR
2844 *
2845 * @param DMAx DMAx instance
2846 * @retval None.
2847 */
ll_dma_clear_flag_tfr4(dma_regs_t * DMAx)2848 __STATIC_INLINE void ll_dma_clear_flag_tfr4(dma_regs_t *DMAx)
2849 {
2850 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << ITEM_4));
2851 }
2852
2853 /**
2854 * @brief Clear Channel 5 transfer complete flag.
2855 *
2856 * Register|BitsName
2857 * --------|--------
2858 * CLR_TFR | CLEAR
2859 *
2860 * @param DMAx DMAx instance
2861 * @retval None.
2862 */
ll_dma_clear_flag_tfr5(dma_regs_t * DMAx)2863 __STATIC_INLINE void ll_dma_clear_flag_tfr5(dma_regs_t *DMAx)
2864 {
2865 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << ITEM_5));
2866 }
2867
2868 /**
2869 * @brief Clear Channel 6 transfer complete flag.
2870 *
2871 * Register|BitsName
2872 * --------|--------
2873 * CLR_TFR | CLEAR
2874 *
2875 * @param DMAx DMAx instance
2876 * @retval None.
2877 */
ll_dma_clear_flag_tfr6(dma_regs_t * DMAx)2878 __STATIC_INLINE void ll_dma_clear_flag_tfr6(dma_regs_t *DMAx)
2879 {
2880 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << ITEM_6));
2881 }
2882
2883 /**
2884 * @brief Clear Channel 7 transfer complete flag.
2885 *
2886 * Register|BitsName
2887 * --------|--------
2888 * CLR_TFR | CLEAR
2889 *
2890 * @param DMAx DMAx instance
2891 * @retval None.
2892 */
ll_dma_clear_flag_tfr7(dma_regs_t * DMAx)2893 __STATIC_INLINE void ll_dma_clear_flag_tfr7(dma_regs_t *DMAx)
2894 {
2895 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[0], (1 << ITEM_7));
2896 }
2897
2898 /**
2899 * @brief Clear DMA Channel block complete flag.
2900 *
2901 * Register|BitsName
2902 * --------|--------
2903 * CLR_BLK | CLEAR
2904 *
2905 * @param DMAx DMAx instance
2906 * @param channel This parameter can be one of the following values:
2907 * @arg @ref LL_DMA_CHANNEL_0
2908 * @arg @ref LL_DMA_CHANNEL_1
2909 * @arg @ref LL_DMA_CHANNEL_2
2910 * @arg @ref LL_DMA_CHANNEL_3
2911 * @arg @ref LL_DMA_CHANNEL_4
2912 * @arg @ref LL_DMA_CHANNEL_5
2913 * @arg @ref LL_DMA_CHANNEL_6
2914 * @arg @ref LL_DMA_CHANNEL_7
2915 * @retval None.
2916 */
ll_dma_clear_flag_blk(dma_regs_t * DMAx,uint32_t channel)2917 __STATIC_INLINE void ll_dma_clear_flag_blk(dma_regs_t *DMAx, uint32_t channel)
2918 {
2919 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[ITEM_2], (1 << channel));
2920 }
2921
2922 /**
2923 * @brief Clear Channel 0 Block Complete flag.
2924 *
2925 * Register|BitsName
2926 * --------|--------
2927 * CLR_BLK | CLEAR
2928 *
2929 * @param DMAx DMAx instance
2930 * @retval None.
2931 */
ll_dma_clear_flag_blk0(dma_regs_t * DMAx)2932 __STATIC_INLINE void ll_dma_clear_flag_blk0(dma_regs_t *DMAx)
2933 {
2934 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[ITEM_2], (1 << 0));
2935 }
2936
2937 /**
2938 * @brief Clear Channel 1 Block Complete flag.
2939 *
2940 * Register|BitsName
2941 * --------|--------
2942 * CLR_BLK | CLEAR
2943 *
2944 * @param DMAx DMAx instance
2945 * @retval None.
2946 */
ll_dma_clear_flag_blk1(dma_regs_t * DMAx)2947 __STATIC_INLINE void ll_dma_clear_flag_blk1(dma_regs_t *DMAx)
2948 {
2949 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[ITEM_2], (1 << 1));
2950 }
2951
2952 /**
2953 * @brief Clear Channel 2 Block Complete flag.
2954 *
2955 * Register|BitsName
2956 * --------|--------
2957 * CLR_BLK | CLEAR
2958 *
2959 * @param DMAx DMAx instance
2960 * @retval None.
2961 */
ll_dma_clear_flag_blk2(dma_regs_t * DMAx)2962 __STATIC_INLINE void ll_dma_clear_flag_blk2(dma_regs_t *DMAx)
2963 {
2964 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[ITEM_2], (1 << ITEM_2));
2965 }
2966
2967 /**
2968 * @brief Clear Channel 3 Block Complete flag.
2969 *
2970 * Register|BitsName
2971 * --------|--------
2972 * CLR_BLK | CLEAR
2973 *
2974 * @param DMAx DMAx instance
2975 * @retval None.
2976 */
ll_dma_clear_flag_blk3(dma_regs_t * DMAx)2977 __STATIC_INLINE void ll_dma_clear_flag_blk3(dma_regs_t *DMAx)
2978 {
2979 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[ITEM_2], (1 << ITEM_3));
2980 }
2981
2982 /**
2983 * @brief Clear Channel 4 Block Complete flag.
2984 *
2985 * Register|BitsName
2986 * --------|--------
2987 * CLR_BLK | CLEAR
2988 *
2989 * @param DMAx DMAx instance
2990 * @retval None.
2991 */
ll_dma_clear_flag_blk4(dma_regs_t * DMAx)2992 __STATIC_INLINE void ll_dma_clear_flag_blk4(dma_regs_t *DMAx)
2993 {
2994 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[ITEM_2], (1 << ITEM_4));
2995 }
2996
2997 /**
2998 * @brief Clear Channel 5 Block Complete flag.
2999 *
3000 * Register|BitsName
3001 * --------|--------
3002 * CLR_BLK | CLEAR
3003 *
3004 * @param DMAx DMAx instance
3005 * @retval None.
3006 */
ll_dma_clear_flag_blk5(dma_regs_t * DMAx)3007 __STATIC_INLINE void ll_dma_clear_flag_blk5(dma_regs_t *DMAx)
3008 {
3009 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[ITEM_2], (1 << ITEM_5));
3010 }
3011
3012 /**
3013 * @brief Clear Channel 6 Block Cmplete flag.
3014 *
3015 * Register|BitsName
3016 * --------|--------
3017 * CLR_BLK | CLEAR
3018 *
3019 * @param DMAx DMAx instance
3020 * @retval None.
3021 */
ll_dma_clear_flag_blk6(dma_regs_t * DMAx)3022 __STATIC_INLINE void ll_dma_clear_flag_blk6(dma_regs_t *DMAx)
3023 {
3024 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[ITEM_2], (1 << ITEM_6));
3025 }
3026
3027 /**
3028 * @brief Clear Channel 7 Block Complete flag.
3029 *
3030 * Register|BitsName
3031 * --------|--------
3032 * CLR_BLK | CLEAR
3033 *
3034 * @param DMAx DMAx instance
3035 * @retval None.
3036 */
ll_dma_clear_flag_blk7(dma_regs_t * DMAx)3037 __STATIC_INLINE void ll_dma_clear_flag_blk7(dma_regs_t *DMAx)
3038 {
3039 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[ITEM_2], (1 << ITEM_7));
3040 }
3041
3042 /**
3043 * @brief Clear DMA Channel source transaction Complete flag.
3044 *
3045 * Register|BitsName
3046 * --------|--------
3047 * CLR_SRC_TRN | CLEAR
3048 *
3049 * @param DMAx DMAx instance
3050 * @param channel This parameter can be one of the following values:
3051 * @arg @ref LL_DMA_CHANNEL_0
3052 * @arg @ref LL_DMA_CHANNEL_1
3053 * @arg @ref LL_DMA_CHANNEL_2
3054 * @arg @ref LL_DMA_CHANNEL_3
3055 * @arg @ref LL_DMA_CHANNEL_4
3056 * @arg @ref LL_DMA_CHANNEL_5
3057 * @arg @ref LL_DMA_CHANNEL_6
3058 * @arg @ref LL_DMA_CHANNEL_7
3059 * @retval None.
3060 */
ll_dma_clear_flag_srct(dma_regs_t * DMAx,uint32_t channel)3061 __STATIC_INLINE void ll_dma_clear_flag_srct(dma_regs_t *DMAx, uint32_t channel)
3062 {
3063 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[ITEM_4], (1 << channel));
3064 }
3065
3066 /**
3067 * @brief Clear Channel 0 source transaction Complete flag.
3068 *
3069 * Register|BitsName
3070 * --------|--------
3071 * CLR_SRC_TRN | CLEAR
3072 *
3073 * @param DMAx DMAx instance
3074 * @retval None.
3075 */
ll_dma_clear_flag_srct0(dma_regs_t * DMAx)3076 __STATIC_INLINE void ll_dma_clear_flag_srct0(dma_regs_t *DMAx)
3077 {
3078 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[ITEM_4], (1 << 0));
3079 }
3080
3081 /**
3082 * @brief Clear Channel 1 source transaction Complete flag.
3083 *
3084 * Register|BitsName
3085 * --------|--------
3086 * CLR_SRC_TRN | CLEAR
3087 *
3088 * @param DMAx DMAx instance
3089 * @retval None.
3090 */
ll_dma_clear_flag_srct1(dma_regs_t * DMAx)3091 __STATIC_INLINE void ll_dma_clear_flag_srct1(dma_regs_t *DMAx)
3092 {
3093 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[ITEM_4], (1 << 1));
3094 }
3095
3096 /**
3097 * @brief Clear Channel 2 source transaction Complete flag.
3098 *
3099 * Register|BitsName
3100 * --------|--------
3101 * CLR_SRC_TRN | CLEAR
3102 *
3103 * @param DMAx DMAx instance
3104 * @retval None.
3105 */
ll_dma_clear_flag_srct2(dma_regs_t * DMAx)3106 __STATIC_INLINE void ll_dma_clear_flag_srct2(dma_regs_t *DMAx)
3107 {
3108 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[ITEM_4], (1 << ITEM_2));
3109 }
3110
3111 /**
3112 * @brief Clear Channel 3 source transaction Complete flag.
3113 *
3114 * Register|BitsName
3115 * --------|--------
3116 * CLR_SRC_TRN | CLEAR
3117 *
3118 * @param DMAx DMAx instance
3119 * @retval None.
3120 */
ll_dma_clear_flag_srct3(dma_regs_t * DMAx)3121 __STATIC_INLINE void ll_dma_clear_flag_srct3(dma_regs_t *DMAx)
3122 {
3123 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[ITEM_4], (1 << ITEM_3));
3124 }
3125
3126 /**
3127 * @brief Clear Channel 4 source transaction Complete flag.
3128 *
3129 * Register|BitsName
3130 * --------|--------
3131 * CLR_SRC_TRN | CLEAR
3132 *
3133 * @param DMAx DMAx instance
3134 * @retval None.
3135 */
ll_dma_clear_flag_srct4(dma_regs_t * DMAx)3136 __STATIC_INLINE void ll_dma_clear_flag_srct4(dma_regs_t *DMAx)
3137 {
3138 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[ITEM_4], (1 << ITEM_4));
3139 }
3140
3141 /**
3142 * @brief Clear Channel 5 source transaction Complete flag.
3143 *
3144 * Register|BitsName
3145 * --------|--------
3146 * CLR_SRC_TRN | CLEAR
3147 *
3148 * @param DMAx DMAx instance
3149 * @retval None.
3150 */
ll_dma_clear_flag_srct5(dma_regs_t * DMAx)3151 __STATIC_INLINE void ll_dma_clear_flag_srct5(dma_regs_t *DMAx)
3152 {
3153 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[ITEM_4], (1 << ITEM_5));
3154 }
3155
3156 /**
3157 * @brief Clear Channel 6 source transaction Complete flag.
3158 *
3159 * Register|BitsName
3160 * --------|--------
3161 * CLR_SRC_TRN | CLEAR
3162 *
3163 * @param DMAx DMAx instance
3164 * @retval None.
3165 */
ll_dma_clear_flag_srct6(dma_regs_t * DMAx)3166 __STATIC_INLINE void ll_dma_clear_flag_srct6(dma_regs_t *DMAx)
3167 {
3168 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[ITEM_4], (1 << ITEM_6));
3169 }
3170
3171 /**
3172 * @brief Clear Channel 7 source transaction Complete flag.
3173 *
3174 * Register|BitsName
3175 * --------|--------
3176 * CLR_SRC_TRN | CLEAR
3177 *
3178 * @param DMAx DMAx instance
3179 * @retval None.
3180 */
ll_dma_clear_flag_srct7(dma_regs_t * DMAx)3181 __STATIC_INLINE void ll_dma_clear_flag_srct7(dma_regs_t *DMAx)
3182 {
3183 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[ITEM_4], (1 << ITEM_7));
3184 }
3185
3186 /**
3187 * @brief Clear DMA Channel destination transaction Complete flag.
3188 *
3189 * Register|BitsName
3190 * --------|--------
3191 * CLR_DST_TRN | CLEAR
3192 *
3193 * @param DMAx DMAx instance
3194 * @param channel This parameter can be one of the following values:
3195 * @arg @ref LL_DMA_CHANNEL_0
3196 * @arg @ref LL_DMA_CHANNEL_1
3197 * @arg @ref LL_DMA_CHANNEL_2
3198 * @arg @ref LL_DMA_CHANNEL_3
3199 * @arg @ref LL_DMA_CHANNEL_4
3200 * @arg @ref LL_DMA_CHANNEL_5
3201 * @arg @ref LL_DMA_CHANNEL_6
3202 * @arg @ref LL_DMA_CHANNEL_7
3203 * @retval None.
3204 */
ll_dma_clear_flag_dstt(dma_regs_t * DMAx,uint32_t channel)3205 __STATIC_INLINE void ll_dma_clear_flag_dstt(dma_regs_t *DMAx, uint32_t channel)
3206 {
3207 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[ITEM_6], (1 << channel));
3208 }
3209
3210 /**
3211 * @brief Clear Channel 0 destination transaction Complete status.
3212 *
3213 * Register|BitsName
3214 * --------|--------
3215 * CLR_DST_TRN | CLEAR
3216 *
3217 * @param DMAx DMAx instance
3218 * @retval None.
3219 */
ll_dma_clear_flag_dstt0(dma_regs_t * DMAx)3220 __STATIC_INLINE void ll_dma_clear_flag_dstt0(dma_regs_t *DMAx)
3221 {
3222 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[ITEM_6], (1 << 0));
3223 }
3224
3225 /**
3226 * @brief Clear Channel 1 destination transaction Complete flag.
3227 *
3228 * Register|BitsName
3229 * --------|--------
3230 * CLR_DST_TRN | CLEAR
3231 *
3232 * @param DMAx DMAx instance
3233 * @retval None.
3234 */
ll_dma_clear_flag_dstt1(dma_regs_t * DMAx)3235 __STATIC_INLINE void ll_dma_clear_flag_dstt1(dma_regs_t *DMAx)
3236 {
3237 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[ITEM_6], (1 << 1));
3238 }
3239
3240 /**
3241 * @brief Clear Channel 2 destination transaction Complete flag.
3242 *
3243 * Register|BitsName
3244 * --------|--------
3245 * CLR_DST_TRN | CLEAR
3246 *
3247 * @param DMAx DMAx instance
3248 * @retval None.
3249 */
ll_dma_clear_flag_dstt2(dma_regs_t * DMAx)3250 __STATIC_INLINE void ll_dma_clear_flag_dstt2(dma_regs_t *DMAx)
3251 {
3252 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[ITEM_6], (1 << ITEM_2));
3253 }
3254
3255 /**
3256 * @brief Clear Channel 3 destination transaction Complete flag.
3257 *
3258 * Register|BitsName
3259 * --------|--------
3260 * CLR_DST_TRN | CLEAR
3261 *
3262 * @param DMAx DMAx instance
3263 * @retval None.
3264 */
ll_dma_clear_flag_dstt3(dma_regs_t * DMAx)3265 __STATIC_INLINE void ll_dma_clear_flag_dstt3(dma_regs_t *DMAx)
3266 {
3267 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[ITEM_6], (1 << ITEM_3));
3268 }
3269
3270 /**
3271 * @brief Clear Channel 4 destination transaction Complete flag.
3272 *
3273 * Register|BitsName
3274 * --------|--------
3275 * CLR_DST_TRN | CLEAR
3276 *
3277 * @param DMAx DMAx instance
3278 * @retval None.
3279 */
ll_dma_clear_flag_dstt4(dma_regs_t * DMAx)3280 __STATIC_INLINE void ll_dma_clear_flag_dstt4(dma_regs_t *DMAx)
3281 {
3282 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[ITEM_6], (1 << ITEM_4));
3283 }
3284
3285 /**
3286 * @brief Clear Channel 5 destination transaction Complete flag.
3287 *
3288 * Register|BitsName
3289 * --------|--------
3290 * CLR_DST_TRN | CLEAR
3291 *
3292 * @param DMAx DMAx instance
3293 * @retval None.
3294 */
ll_dma_clear_flag_dstt5(dma_regs_t * DMAx)3295 __STATIC_INLINE void ll_dma_clear_flag_dstt5(dma_regs_t *DMAx)
3296 {
3297 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[ITEM_6], (1 << ITEM_5));
3298 }
3299
3300 /**
3301 * @brief Clear Channel 6 destination transaction Complete flag.
3302 *
3303 * Register|BitsName
3304 * --------|--------
3305 * CLR_DST_TRN | CLEAR
3306 *
3307 * @param DMAx DMAx instance
3308 * @retval None.
3309 */
ll_dma_clear_flag_dstt6(dma_regs_t * DMAx)3310 __STATIC_INLINE void ll_dma_clear_flag_dstt6(dma_regs_t *DMAx)
3311 {
3312 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[ITEM_6], (1 << ITEM_6));
3313 }
3314
3315 /**
3316 * @brief Clear Channel 7 destination transaction Complete flag.
3317 *
3318 * Register|BitsName
3319 * --------|--------
3320 * CLR_DST_TRN | CLEAR
3321 *
3322 * @param DMAx DMAx instance
3323 * @retval None.
3324 */
ll_dma_clear_flag_dstt7(dma_regs_t * DMAx)3325 __STATIC_INLINE void ll_dma_clear_flag_dstt7(dma_regs_t *DMAx)
3326 {
3327 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[ITEM_6], (1 << ITEM_7));
3328 }
3329
3330 /**
3331 * @brief Clear DMA Channel error flag.
3332 *
3333 * Register|BitsName
3334 * --------|--------
3335 * CLR_ERR | CLEAR
3336 *
3337 * @param DMAx DMAx instance
3338 * @param channel This parameter can be one of the following values:
3339 * @arg @ref LL_DMA_CHANNEL_0
3340 * @arg @ref LL_DMA_CHANNEL_1
3341 * @arg @ref LL_DMA_CHANNEL_2
3342 * @arg @ref LL_DMA_CHANNEL_3
3343 * @arg @ref LL_DMA_CHANNEL_4
3344 * @arg @ref LL_DMA_CHANNEL_5
3345 * @arg @ref LL_DMA_CHANNEL_6
3346 * @arg @ref LL_DMA_CHANNEL_7
3347 * @retval None.
3348 */
ll_dma_clear_flag_err(dma_regs_t * DMAx,uint32_t channel)3349 __STATIC_INLINE void ll_dma_clear_flag_err(dma_regs_t *DMAx, uint32_t channel)
3350 {
3351 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[ITEM_8], (1 << channel));
3352 }
3353
3354 /**
3355 * @brief Clear Channel 0 error flag.
3356 *
3357 * Register|BitsName
3358 * --------|--------
3359 * CLR_ERR | CLEAR
3360 *
3361 * @param DMAx DMAx instance
3362 * @retval None.
3363 */
ll_dma_clear_flag_err0(dma_regs_t * DMAx)3364 __STATIC_INLINE void ll_dma_clear_flag_err0(dma_regs_t *DMAx)
3365 {
3366 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[ITEM_8], (1 << 0));
3367 }
3368
3369 /**
3370 * @brief Clear Channel 1 error flag.
3371 *
3372 * Register|BitsName
3373 * --------|--------
3374 * CLR_ERR | CLEAR
3375 *
3376 * @param DMAx DMAx instance
3377 * @retval None.
3378 */
ll_dma_clear_flag_err1(dma_regs_t * DMAx)3379 __STATIC_INLINE void ll_dma_clear_flag_err1(dma_regs_t *DMAx)
3380 {
3381 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[ITEM_8], (1 << 1));
3382 }
3383
3384 /**
3385 * @brief Clear Channel 2 error flag.
3386 *
3387 * Register|BitsName
3388 * --------|--------
3389 * CLR_ERR | CLEAR
3390 *
3391 * @param DMAx DMAx instance
3392 * @retval None.
3393 */
ll_dma_clear_flag_err2(dma_regs_t * DMAx)3394 __STATIC_INLINE void ll_dma_clear_flag_err2(dma_regs_t *DMAx)
3395 {
3396 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[ITEM_8], (1 << ITEM_2));
3397 }
3398
3399 /**
3400 * @brief Clear Channel 3 error flag.
3401 *
3402 * Register|BitsName
3403 * --------|--------
3404 * CLR_ERR | CLEAR
3405 *
3406 * @param DMAx DMAx instance
3407 * @retval None.
3408 */
ll_dma_clear_flag_err3(dma_regs_t * DMAx)3409 __STATIC_INLINE void ll_dma_clear_flag_err3(dma_regs_t *DMAx)
3410 {
3411 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[ITEM_8], (1 << ITEM_3));
3412 }
3413
3414 /**
3415 * @brief Clear Channel 4 error flag.
3416 *
3417 * Register|BitsName
3418 * --------|--------
3419 * CLR_ERR | CLEAR
3420 *
3421 * @param DMAx DMAx instance
3422 * @retval None.
3423 */
ll_dma_clear_flag_err4(dma_regs_t * DMAx)3424 __STATIC_INLINE void ll_dma_clear_flag_err4(dma_regs_t *DMAx)
3425 {
3426 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[ITEM_8], (1 << ITEM_4));
3427 }
3428
3429 /**
3430 * @brief Clear Channel 5 error flag.
3431 *
3432 * Register|BitsName
3433 * --------|--------
3434 * CLR_ERR | CLEAR
3435 *
3436 * @param DMAx DMAx instance
3437 * @retval None.
3438 */
ll_dma_clear_flag_err5(dma_regs_t * DMAx)3439 __STATIC_INLINE void ll_dma_clear_flag_err5(dma_regs_t *DMAx)
3440 {
3441 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[ITEM_8], (1 << ITEM_5));
3442 }
3443
3444 /**
3445 * @brief Clear Channel 6 error flag.
3446 *
3447 * Register|BitsName
3448 * --------|--------
3449 * CLR_ERR | CLEAR
3450 *
3451 * @param DMAx DMAx instance
3452 * @retval None.
3453 */
ll_dma_clear_flag_err6(dma_regs_t * DMAx)3454 __STATIC_INLINE void ll_dma_clear_flag_err6(dma_regs_t *DMAx)
3455 {
3456 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[ITEM_8], (1 << ITEM_6));
3457 }
3458
3459 /**
3460 * @brief Clear Channel 7 error flag.
3461 *
3462 * Register|BitsName
3463 * --------|--------
3464 * CLR_ERR | CLEAR
3465 *
3466 * @param DMAx DMAx instance
3467 * @retval None.
3468 */
ll_dma_clear_flag_err7(dma_regs_t * DMAx)3469 __STATIC_INLINE void ll_dma_clear_flag_err7(dma_regs_t *DMAx)
3470 {
3471 WRITE_REG(DMAx->EVENT.CLEAR_CH_EVT[ITEM_8], (1 << ITEM_7));
3472 }
3473
3474 /** @} */
3475
3476 /** @defgroup DMA_LL_EF_IT_Management IT_Management
3477 * @{
3478 */
3479
3480 /**
3481 * @brief Enable Transfer Complete interrupt.
3482 *
3483 * Register|BitsName
3484 * --------|--------
3485 * MASK_TFR | TFR_WE&TFR
3486 *
3487 * @param DMAx DMAx instance
3488 * @param channel This parameter can be one of the following values:
3489 * @arg @ref LL_DMA_CHANNEL_0
3490 * @arg @ref LL_DMA_CHANNEL_1
3491 * @arg @ref LL_DMA_CHANNEL_2
3492 * @arg @ref LL_DMA_CHANNEL_3
3493 * @arg @ref LL_DMA_CHANNEL_4
3494 * @arg @ref LL_DMA_CHANNEL_5
3495 * @arg @ref LL_DMA_CHANNEL_6
3496 * @arg @ref LL_DMA_CHANNEL_7
3497 * @retval None
3498 */
ll_dma_enable_it_tfr(dma_regs_t * DMAx,uint32_t channel)3499 __STATIC_INLINE void ll_dma_enable_it_tfr(dma_regs_t *DMAx, uint32_t channel)
3500 {
3501 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[0], (1 << (channel + DMA_MASK_TFR_WE_Pos)) + (1 << channel));
3502 }
3503
3504 /**
3505 * @brief Enable Block Complete interrupt.
3506 *
3507 * Register|BitsName
3508 * --------|--------
3509 * MASK_BLK | BLK_WE&BLK
3510 *
3511 * @param DMAx DMAx instance
3512 * @param channel This parameter can be one of the following values:
3513 * @arg @ref LL_DMA_CHANNEL_0
3514 * @arg @ref LL_DMA_CHANNEL_1
3515 * @arg @ref LL_DMA_CHANNEL_2
3516 * @arg @ref LL_DMA_CHANNEL_3
3517 * @arg @ref LL_DMA_CHANNEL_4
3518 * @arg @ref LL_DMA_CHANNEL_5
3519 * @arg @ref LL_DMA_CHANNEL_6
3520 * @arg @ref LL_DMA_CHANNEL_7
3521 * @retval None
3522 */
ll_dma_enable_it_blk(dma_regs_t * DMAx,uint32_t channel)3523 __STATIC_INLINE void ll_dma_enable_it_blk(dma_regs_t *DMAx, uint32_t channel)
3524 {
3525 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[ITEM_2], (1 << (channel + DMA_MASK_BLK_WE_Pos)) + (1 << channel));
3526 }
3527
3528 /**
3529 * @brief Enable source transaction Complete interrupt.
3530 *
3531 * Register|BitsName
3532 * --------|--------
3533 * MASK_SRC_TRN | SRC_TRN_WE&SRC_TRN
3534 *
3535 * @param DMAx DMAx instance
3536 * @param channel This parameter can be one of the following values:
3537 * @arg @ref LL_DMA_CHANNEL_0
3538 * @arg @ref LL_DMA_CHANNEL_1
3539 * @arg @ref LL_DMA_CHANNEL_2
3540 * @arg @ref LL_DMA_CHANNEL_3
3541 * @arg @ref LL_DMA_CHANNEL_4
3542 * @arg @ref LL_DMA_CHANNEL_5
3543 * @arg @ref LL_DMA_CHANNEL_6
3544 * @arg @ref LL_DMA_CHANNEL_7
3545 * @retval None
3546 */
ll_dma_enable_it_srct(dma_regs_t * DMAx,uint32_t channel)3547 __STATIC_INLINE void ll_dma_enable_it_srct(dma_regs_t *DMAx, uint32_t channel)
3548 {
3549 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[ITEM_4], (1 << (channel + DMA_MASK_SRC_TRN_WE_Pos)) + (1 << channel));
3550 }
3551
3552 /**
3553 * @brief Enable destination transaction Complete interrupt.
3554 *
3555 * Register|BitsName
3556 * --------|--------
3557 * MASK_DST_TRN | DST_TRN_WE&DST_TRN
3558 *
3559 * @param DMAx DMAx instance
3560 * @param channel This parameter can be one of the following values:
3561 * @arg @ref LL_DMA_CHANNEL_0
3562 * @arg @ref LL_DMA_CHANNEL_1
3563 * @arg @ref LL_DMA_CHANNEL_2
3564 * @arg @ref LL_DMA_CHANNEL_3
3565 * @arg @ref LL_DMA_CHANNEL_4
3566 * @arg @ref LL_DMA_CHANNEL_5
3567 * @arg @ref LL_DMA_CHANNEL_6
3568 * @arg @ref LL_DMA_CHANNEL_7
3569 * @retval None
3570 */
ll_dma_enable_it_dstt(dma_regs_t * DMAx,uint32_t channel)3571 __STATIC_INLINE void ll_dma_enable_it_dstt(dma_regs_t *DMAx, uint32_t channel)
3572 {
3573 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[ITEM_6], (1 << (channel + DMA_MASK_DST_TRN_WE_Pos)) + (1 << channel));
3574 }
3575
3576 /**
3577 * @brief Enable error interrupt.
3578 *
3579 * Register|BitsName
3580 * --------|--------
3581 * MASK_ERR | ERR_WE&ERR
3582 *
3583 * @param DMAx DMAx instance
3584 * @param channel This parameter can be one of the following values:
3585 * @arg @ref LL_DMA_CHANNEL_0
3586 * @arg @ref LL_DMA_CHANNEL_1
3587 * @arg @ref LL_DMA_CHANNEL_2
3588 * @arg @ref LL_DMA_CHANNEL_3
3589 * @arg @ref LL_DMA_CHANNEL_4
3590 * @arg @ref LL_DMA_CHANNEL_5
3591 * @arg @ref LL_DMA_CHANNEL_6
3592 * @arg @ref LL_DMA_CHANNEL_7
3593 * @retval None
3594 */
ll_dma_enable_it_err(dma_regs_t * DMAx,uint32_t channel)3595 __STATIC_INLINE void ll_dma_enable_it_err(dma_regs_t *DMAx, uint32_t channel)
3596 {
3597 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[ITEM_8], (1 << (channel + DMA_MASK_ERR_WE_Pos)) + (1 << channel));
3598 }
3599
3600 /**
3601 * @brief Disable Transfer Complete interrupt.
3602 *
3603 * Register|BitsName
3604 * --------|--------
3605 * MASK_TFR | TFR_WE&TFR
3606 *
3607 * @param DMAx DMAx instance
3608 * @param channel This parameter can be one of the following values:
3609 * @arg @ref LL_DMA_CHANNEL_0
3610 * @arg @ref LL_DMA_CHANNEL_1
3611 * @arg @ref LL_DMA_CHANNEL_2
3612 * @arg @ref LL_DMA_CHANNEL_3
3613 * @arg @ref LL_DMA_CHANNEL_4
3614 * @arg @ref LL_DMA_CHANNEL_5
3615 * @arg @ref LL_DMA_CHANNEL_6
3616 * @arg @ref LL_DMA_CHANNEL_7
3617 * @retval None
3618 */
ll_dma_disable_it_tfr(dma_regs_t * DMAx,uint32_t channel)3619 __STATIC_INLINE void ll_dma_disable_it_tfr(dma_regs_t *DMAx, uint32_t channel)
3620 {
3621 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[0], (1 << (channel + DMA_MASK_TFR_WE_Pos)));
3622 }
3623
3624 /**
3625 * @brief Disable Block Complete interrupt.
3626 *
3627 * Register|BitsName
3628 * --------|--------
3629 * MASK_BLK | BLK_WE&BLK
3630 *
3631 * @param DMAx DMAx instance
3632 * @param channel This parameter can be one of the following values:
3633 * @arg @ref LL_DMA_CHANNEL_0
3634 * @arg @ref LL_DMA_CHANNEL_1
3635 * @arg @ref LL_DMA_CHANNEL_2
3636 * @arg @ref LL_DMA_CHANNEL_3
3637 * @arg @ref LL_DMA_CHANNEL_4
3638 * @arg @ref LL_DMA_CHANNEL_5
3639 * @arg @ref LL_DMA_CHANNEL_6
3640 * @arg @ref LL_DMA_CHANNEL_7
3641 * @retval None
3642 */
ll_dma_disable_it_blk(dma_regs_t * DMAx,uint32_t channel)3643 __STATIC_INLINE void ll_dma_disable_it_blk(dma_regs_t *DMAx, uint32_t channel)
3644 {
3645 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[ITEM_2], (1 << (channel + DMA_MASK_BLK_WE_Pos)));
3646 }
3647
3648 /**
3649 * @brief Disable source transaction Complete interrupt.
3650 *
3651 * Register|BitsName
3652 * --------|--------
3653 * MASK_SRC_TRN | SRC_TRN_WE&SRC_TRN
3654 *
3655 * @param DMAx DMAx instance
3656 * @param channel This parameter can be one of the following values:
3657 * @arg @ref LL_DMA_CHANNEL_0
3658 * @arg @ref LL_DMA_CHANNEL_1
3659 * @arg @ref LL_DMA_CHANNEL_2
3660 * @arg @ref LL_DMA_CHANNEL_3
3661 * @arg @ref LL_DMA_CHANNEL_4
3662 * @arg @ref LL_DMA_CHANNEL_5
3663 * @arg @ref LL_DMA_CHANNEL_6
3664 * @arg @ref LL_DMA_CHANNEL_7
3665 * @retval None
3666 */
ll_dma_disable_it_srct(dma_regs_t * DMAx,uint32_t channel)3667 __STATIC_INLINE void ll_dma_disable_it_srct(dma_regs_t *DMAx, uint32_t channel)
3668 {
3669 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[ITEM_4], (1 << (channel + DMA_MASK_SRC_TRN_WE_Pos)));
3670 }
3671
3672 /**
3673 * @brief Disable destination transaction Complete interrupt.
3674 *
3675 * Register|BitsName
3676 * --------|--------
3677 * MASK_DST_TRN | DST_TRN_WE&DST_TRN
3678 *
3679 * @param DMAx DMAx instance
3680 * @param channel This parameter can be one of the following values:
3681 * @arg @ref LL_DMA_CHANNEL_0
3682 * @arg @ref LL_DMA_CHANNEL_1
3683 * @arg @ref LL_DMA_CHANNEL_2
3684 * @arg @ref LL_DMA_CHANNEL_3
3685 * @arg @ref LL_DMA_CHANNEL_4
3686 * @arg @ref LL_DMA_CHANNEL_5
3687 * @arg @ref LL_DMA_CHANNEL_6
3688 * @arg @ref LL_DMA_CHANNEL_7
3689 * @retval None
3690 */
ll_dma_disable_it_dstt(dma_regs_t * DMAx,uint32_t channel)3691 __STATIC_INLINE void ll_dma_disable_it_dstt(dma_regs_t *DMAx, uint32_t channel)
3692 {
3693 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[ITEM_6], (1 << (channel + DMA_MASK_DST_TRN_WE_Pos)));
3694 }
3695
3696 /**
3697 * @brief Disable error interrupt.
3698 *
3699 * Register|BitsName
3700 * --------|--------
3701 * MASK_ERR | ERR_WE&ERR
3702 *
3703 * @param DMAx DMAx instance
3704 * @param channel This parameter can be one of the following values:
3705 * @arg @ref LL_DMA_CHANNEL_0
3706 * @arg @ref LL_DMA_CHANNEL_1
3707 * @arg @ref LL_DMA_CHANNEL_2
3708 * @arg @ref LL_DMA_CHANNEL_3
3709 * @arg @ref LL_DMA_CHANNEL_4
3710 * @arg @ref LL_DMA_CHANNEL_5
3711 * @arg @ref LL_DMA_CHANNEL_6
3712 * @arg @ref LL_DMA_CHANNEL_7
3713 * @retval None
3714 */
ll_dma_disable_it_err(dma_regs_t * DMAx,uint32_t channel)3715 __STATIC_INLINE void ll_dma_disable_it_err(dma_regs_t *DMAx, uint32_t channel)
3716 {
3717 WRITE_REG(DMAx->EVENT.MASK_CH_EVT[ITEM_8], (1 << (channel + DMA_MASK_ERR_WE_Pos)));
3718 }
3719
3720 /**
3721 * @brief Check if DMA Transfer interrupt is enabled or disabled.
3722 *
3723 * Register|BitsName
3724 * --------|--------
3725 * MASK_TFR | TFR
3726 *
3727 * @param DMAx DMA instance.
3728 * @param channel This parameter can be one of the following values:
3729 * @arg @ref LL_DMA_CHANNEL_0
3730 * @arg @ref LL_DMA_CHANNEL_1
3731 * @arg @ref LL_DMA_CHANNEL_2
3732 * @arg @ref LL_DMA_CHANNEL_3
3733 * @arg @ref LL_DMA_CHANNEL_4
3734 * @arg @ref LL_DMA_CHANNEL_5
3735 * @arg @ref LL_DMA_CHANNEL_6
3736 * @arg @ref LL_DMA_CHANNEL_7
3737 * @retval State of bit (1 or 0).
3738 */
ll_dma_is_enable_it_tfr(dma_regs_t * DMAx,uint32_t channel)3739 __STATIC_INLINE uint32_t ll_dma_is_enable_it_tfr(dma_regs_t *DMAx, uint32_t channel)
3740 {
3741 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[0], (1 << channel)) == (1 << channel));
3742 }
3743
3744 /**
3745 * @brief Check if DMA block interrupt is enabled or disabled.
3746 *
3747 * Register|BitsName
3748 * --------|--------
3749 * MASK_BLK | BLK_WE&BLK
3750 *
3751 * @param DMAx DMA instance.
3752 * @param channel This parameter can be one of the following values:
3753 * @arg @ref LL_DMA_CHANNEL_0
3754 * @arg @ref LL_DMA_CHANNEL_1
3755 * @arg @ref LL_DMA_CHANNEL_2
3756 * @arg @ref LL_DMA_CHANNEL_3
3757 * @arg @ref LL_DMA_CHANNEL_4
3758 * @arg @ref LL_DMA_CHANNEL_5
3759 * @arg @ref LL_DMA_CHANNEL_6
3760 * @arg @ref LL_DMA_CHANNEL_7
3761 * @retval State of bit (1 or 0).
3762 */
ll_dma_is_enable_it_blk(dma_regs_t * DMAx,uint32_t channel)3763 __STATIC_INLINE uint32_t ll_dma_is_enable_it_blk(dma_regs_t *DMAx, uint32_t channel)
3764 {
3765 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[ITEM_2], (1 << channel)) == (1 << channel));
3766 }
3767
3768 /**
3769 * @brief Check if DMA source transaction interrupt is enabled or disabled.
3770 *
3771 * Register|BitsName
3772 * --------|--------
3773 * MASK_SRC_TRN | SRC_TRN
3774 *
3775 * @param DMAx DMA instance.
3776 * @param channel This parameter can be one of the following values:
3777 * @arg @ref LL_DMA_CHANNEL_0
3778 * @arg @ref LL_DMA_CHANNEL_1
3779 * @arg @ref LL_DMA_CHANNEL_2
3780 * @arg @ref LL_DMA_CHANNEL_3
3781 * @arg @ref LL_DMA_CHANNEL_4
3782 * @arg @ref LL_DMA_CHANNEL_5
3783 * @arg @ref LL_DMA_CHANNEL_6
3784 * @arg @ref LL_DMA_CHANNEL_7
3785 * @retval State of bit (1 or 0).
3786 */
ll_dma_is_enable_it_srct(dma_regs_t * DMAx,uint32_t channel)3787 __STATIC_INLINE uint32_t ll_dma_is_enable_it_srct(dma_regs_t *DMAx, uint32_t channel)
3788 {
3789 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[ITEM_4], (1 << channel)) == (1 << channel));
3790 }
3791
3792 /**
3793 * @brief Check if DMA destination transaction interrupt is enabled or disabled.
3794 *
3795 * Register|BitsName
3796 * --------|--------
3797 * MASK_DST_TRN | DST_TRN
3798 *
3799 * @param DMAx DMA instance.
3800 * @param channel This parameter can be one of the following values:
3801 * @arg @ref LL_DMA_CHANNEL_0
3802 * @arg @ref LL_DMA_CHANNEL_1
3803 * @arg @ref LL_DMA_CHANNEL_2
3804 * @arg @ref LL_DMA_CHANNEL_3
3805 * @arg @ref LL_DMA_CHANNEL_4
3806 * @arg @ref LL_DMA_CHANNEL_5
3807 * @arg @ref LL_DMA_CHANNEL_6
3808 * @arg @ref LL_DMA_CHANNEL_7
3809 * @retval State of bit (1 or 0).
3810 */
ll_dma_is_enable_it_dstt(dma_regs_t * DMAx,uint32_t channel)3811 __STATIC_INLINE uint32_t ll_dma_is_enable_it_dstt(dma_regs_t *DMAx, uint32_t channel)
3812 {
3813 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[ITEM_6], (1 << channel)) == (1 << channel));
3814 }
3815
3816 /**
3817 * @brief Check if DMA error interrupt is enabled or disabled.
3818 *
3819 * Register|BitsName
3820 * --------|--------
3821 * MASK_ERR | ERR
3822 *
3823 * @param DMAx DMA instance.
3824 * @param channel This parameter can be one of the following values:
3825 * @arg @ref LL_DMA_CHANNEL_0
3826 * @arg @ref LL_DMA_CHANNEL_1
3827 * @arg @ref LL_DMA_CHANNEL_2
3828 * @arg @ref LL_DMA_CHANNEL_3
3829 * @arg @ref LL_DMA_CHANNEL_4
3830 * @arg @ref LL_DMA_CHANNEL_5
3831 * @arg @ref LL_DMA_CHANNEL_6
3832 * @arg @ref LL_DMA_CHANNEL_7
3833 * @retval State of bit (1 or 0).
3834 */
ll_dma_is_enable_it_err(dma_regs_t * DMAx,uint32_t channel)3835 __STATIC_INLINE uint32_t ll_dma_is_enable_it_err(dma_regs_t *DMAx, uint32_t channel)
3836 {
3837 return (READ_BITS(DMAx->EVENT.MASK_CH_EVT[ITEM_8], (1 << channel)) == (1 << channel));
3838 }
3839
3840 /**
3841 * @brief Enable DMA channel interrupt.
3842 *
3843 * Register|BitsName
3844 * --------|--------
3845 * CTLL | INI_EN
3846 *
3847 * @param DMAx DMA instance.
3848 * @param channel This parameter can be one of the following values:
3849 * @arg @ref LL_DMA_CHANNEL_0
3850 * @arg @ref LL_DMA_CHANNEL_1
3851 * @arg @ref LL_DMA_CHANNEL_2
3852 * @arg @ref LL_DMA_CHANNEL_3
3853 * @arg @ref LL_DMA_CHANNEL_4
3854 * @arg @ref LL_DMA_CHANNEL_5
3855 * @arg @ref LL_DMA_CHANNEL_6
3856 * @arg @ref LL_DMA_CHANNEL_7
3857 * @retval None
3858 */
ll_dma_enable_it(dma_regs_t * DMAx,uint32_t channel)3859 __STATIC_INLINE void ll_dma_enable_it(dma_regs_t *DMAx, uint32_t channel)
3860 {
3861 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_INI_EN, DMA_CTLL_INI_EN);
3862 }
3863
3864 /**
3865 * @brief Disable DMA channel interrupt.
3866 *
3867 * Register|BitsName
3868 * --------|--------
3869 * CTLL | INI_EN
3870 *
3871 * @param DMAx DMA instance.
3872 * @param channel This parameter can be one of the following values:
3873 * @arg @ref LL_DMA_CHANNEL_0
3874 * @arg @ref LL_DMA_CHANNEL_1
3875 * @arg @ref LL_DMA_CHANNEL_2
3876 * @arg @ref LL_DMA_CHANNEL_3
3877 * @arg @ref LL_DMA_CHANNEL_4
3878 * @arg @ref LL_DMA_CHANNEL_5
3879 * @arg @ref LL_DMA_CHANNEL_6
3880 * @arg @ref LL_DMA_CHANNEL_7
3881 * @retval None
3882 */
ll_dma_disable_it(dma_regs_t * DMAx,uint32_t channel)3883 __STATIC_INLINE void ll_dma_disable_it(dma_regs_t *DMAx, uint32_t channel)
3884 {
3885 MODIFY_REG(DMAx->CHANNEL[channel].CTL_LO, DMA_CTLL_INI_EN, 0);
3886 }
3887
3888 /** @} */
3889
3890 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
3891 * @{
3892 */
3893
3894 /**
3895 * @brief De-initialize the DMA registers to their default reset values.
3896 * @param DMAx DMAx instance
3897 * @param channel This parameter can be one of the following values:
3898 * @arg @ref LL_DMA_CHANNEL_0
3899 * @arg @ref LL_DMA_CHANNEL_1
3900 * @arg @ref LL_DMA_CHANNEL_2
3901 * @arg @ref LL_DMA_CHANNEL_3
3902 * @arg @ref LL_DMA_CHANNEL_4
3903 * @arg @ref LL_DMA_CHANNEL_5
3904 * @arg @ref LL_DMA_CHANNEL_6
3905 * @arg @ref LL_DMA_CHANNEL_7
3906 * @retval An error_status_t enumeration value:
3907 * - SUCCESS: DMA registers are de-initialized
3908 * - ERROR: DMA registers are not de-initialized
3909 */
3910 error_status_t ll_dma_deinit(dma_regs_t *DMAx, uint32_t channel);
3911
3912 /**
3913 * @brief Initialize the DMA registers according to the specified parameters in p_dma_init.
3914 * @param DMAx DMAx instance
3915 * @param channel This parameter can be one of the following values:
3916 * @arg @ref LL_DMA_CHANNEL_0
3917 * @arg @ref LL_DMA_CHANNEL_1
3918 * @arg @ref LL_DMA_CHANNEL_2
3919 * @arg @ref LL_DMA_CHANNEL_3
3920 * @arg @ref LL_DMA_CHANNEL_4
3921 * @arg @ref LL_DMA_CHANNEL_5
3922 * @arg @ref LL_DMA_CHANNEL_6
3923 * @arg @ref LL_DMA_CHANNEL_7
3924 * @param p_dma_init pointer to a @ref ll_dma_init_t structure.
3925 * @retval An error_status_t enumeration value:
3926 * - SUCCESS: DMA registers are initialized
3927 * - ERROR: Not applicable
3928 */
3929 error_status_t ll_dma_init(dma_regs_t *DMAx, uint32_t channel, ll_dma_init_t *p_dma_init);
3930
3931 /**
3932 * @brief Set each field of a @ref ll_dma_init_t type structure to default value.
3933 * @param p_dma_init Pointer to a @ref ll_dma_init_t structure
3934 * whose fields will be set to default values.
3935 * @retval None
3936 */
3937 void ll_dma_struct_init(ll_dma_init_t *p_dma_init);
3938
3939 /** @} */
3940
3941 /** @} */
3942
3943 #endif /* DMA */
3944
3945 #ifdef __cplusplus
3946 }
3947 #endif
3948
3949 #endif /* __GR55xx_LL_DMA_H__ */
3950
3951 /** @} */
3952
3953 /** @} */
3954
3955 /** @} */
3956