1 /* 2 * Copyright (c) 2021-2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_MIPI_DSI_PHY_H 10 #define HPM_MIPI_DSI_PHY_H 11 12 typedef struct { 13 __RW uint32_t CLANE_PARA0; /* 0x0: timer counter about clock lane parameter */ 14 __RW uint32_t CLANE_PARA1; /* 0x4: timer counter about clock lane parameter */ 15 __RW uint32_t CLANE_PARA2; /* 0x8: timer counter about clock lane parameter */ 16 __RW uint32_t CLANE_PARA3; /* 0xC: timer counter about clock lane parameter */ 17 __RW uint32_t DLANE0_PARA0; /* 0x10: timer counter about datalane0 parameter */ 18 __RW uint32_t DLANE0_PARA1; /* 0x14: timer counter about datalane0 parameter */ 19 __RW uint32_t DLANE0_PARA2; /* 0x18: timer counter about datalane0 parameter */ 20 __RW uint32_t DLANE0_PARA3; /* 0x1C: timer counter about datalane0 parameter */ 21 __RW uint32_t DLANE0_PARA4; /* 0x20: timer counter about datalane0 parameter */ 22 __RW uint32_t DLANE1_PARA0; /* 0x24: timer counter about datalane1 parameter */ 23 __RW uint32_t DLANE1_PARA1; /* 0x28: timer counter about datalane1 parameter */ 24 __RW uint32_t DLANE1_PARA2; /* 0x2C: timer counter about datalane1 parameter */ 25 __RW uint32_t DLANE1_PARA3; /* 0x30: timer counter about datalane1 parameter */ 26 __RW uint32_t DLANE2_PARA0; /* 0x34: timer counter about datalane2 parameter */ 27 __RW uint32_t DLANE2_PARA1; /* 0x38: timer counter about datalane2 parameter */ 28 __RW uint32_t DLANE2_PARA2; /* 0x3C: timer counter about datalane2 parameter */ 29 __RW uint32_t DLANE2_PARA3; /* 0x40: timer counter about datalane2 parameter */ 30 __RW uint32_t DLANE3_PARA0; /* 0x44: timer counter about datalane3 parameter */ 31 __RW uint32_t DLANE3_PARA1; /* 0x48: timer counter about datalane3 parameter */ 32 __RW uint32_t DLANE3_PARA2; /* 0x4C: timer counter about datalane3 parameter */ 33 __RW uint32_t DLANE3_PARA3; /* 0x50: timer counter about datalane3 parameter */ 34 __RW uint32_t COMMON_PARA0; /* 0x54: timing parameter for all lanes */ 35 __RW uint32_t CTRL_PARA0; /* 0x58: dphy control parameter */ 36 __RW uint32_t PLL_CTRL_PARA0; /* 0x5C: dphy pll control parameter */ 37 __R uint8_t RESERVED0[4]; /* 0x60 - 0x63: Reserved */ 38 __RW uint32_t RCAL_CTRL; /* 0x64: dphy calibration control parameter */ 39 __RW uint32_t TRIM_PARA; /* 0x68: dphy trimming parameter */ 40 __RW uint32_t TEST_PARA0; /* 0x6C: dphy test control parameter */ 41 __RW uint32_t TEST_PARA1; /* 0x70: dphy bist test control parameter */ 42 __RW uint32_t MISC_PARA; /* 0x74: dphy control parameter */ 43 __RW uint32_t CLANE_PARA4; /* 0x78: dphy clock lane control parameter */ 44 __RW uint32_t INTERFACE_PARA; /* 0x7C: dphy clock lane control parameter */ 45 __RW uint32_t PCS_RESERVED_PIN_PARA; /* 0x80: reserved the pins for pcs */ 46 __R uint8_t RESERVED1[8]; /* 0x84 - 0x8B: Reserved */ 47 __RW uint32_t CLANE_DATA_PARA; /* 0x8C: parallel data about clock lane parameter */ 48 __RW uint32_t PMA_LANE_SEL_PARA; /* 0x90: pma about clock lane select parameter */ 49 } MIPI_DSI_PHY_Type; 50 51 52 /* Bitfield definition for register: CLANE_PARA0 */ 53 /* 54 * T_RST2ENLPTX_C (RW) 55 * 56 * the soft reset of clk_cfg domain 57 */ 58 #define MIPI_DSI_PHY_CLANE_PARA0_T_RST2ENLPTX_C_MASK (0xFFFFU) 59 #define MIPI_DSI_PHY_CLANE_PARA0_T_RST2ENLPTX_C_SHIFT (0U) 60 #define MIPI_DSI_PHY_CLANE_PARA0_T_RST2ENLPTX_C_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_PARA0_T_RST2ENLPTX_C_SHIFT) & MIPI_DSI_PHY_CLANE_PARA0_T_RST2ENLPTX_C_MASK) 61 #define MIPI_DSI_PHY_CLANE_PARA0_T_RST2ENLPTX_C_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_PARA0_T_RST2ENLPTX_C_MASK) >> MIPI_DSI_PHY_CLANE_PARA0_T_RST2ENLPTX_C_SHIFT) 62 63 /* Bitfield definition for register: CLANE_PARA1 */ 64 /* 65 * T_INITTIME_C (RW) 66 * 67 * the number of byteclk cycles that clklane drive LP-11 during initialization period 68 */ 69 #define MIPI_DSI_PHY_CLANE_PARA1_T_INITTIME_C_MASK (0xFFFFFFFFUL) 70 #define MIPI_DSI_PHY_CLANE_PARA1_T_INITTIME_C_SHIFT (0U) 71 #define MIPI_DSI_PHY_CLANE_PARA1_T_INITTIME_C_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_PARA1_T_INITTIME_C_SHIFT) & MIPI_DSI_PHY_CLANE_PARA1_T_INITTIME_C_MASK) 72 #define MIPI_DSI_PHY_CLANE_PARA1_T_INITTIME_C_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_PARA1_T_INITTIME_C_MASK) >> MIPI_DSI_PHY_CLANE_PARA1_T_INITTIME_C_SHIFT) 73 74 /* Bitfield definition for register: CLANE_PARA2 */ 75 /* 76 * T_CLKPREPARE_C (RW) 77 * 78 * the number of byteclk cycles that clock lane clkp/n lines are at the hs prepare state lp-00 during a hs clock transmission 79 */ 80 #define MIPI_DSI_PHY_CLANE_PARA2_T_CLKPREPARE_C_MASK (0xFF0000UL) 81 #define MIPI_DSI_PHY_CLANE_PARA2_T_CLKPREPARE_C_SHIFT (16U) 82 #define MIPI_DSI_PHY_CLANE_PARA2_T_CLKPREPARE_C_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_PARA2_T_CLKPREPARE_C_SHIFT) & MIPI_DSI_PHY_CLANE_PARA2_T_CLKPREPARE_C_MASK) 83 #define MIPI_DSI_PHY_CLANE_PARA2_T_CLKPREPARE_C_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_PARA2_T_CLKPREPARE_C_MASK) >> MIPI_DSI_PHY_CLANE_PARA2_T_CLKPREPARE_C_SHIFT) 84 85 /* 86 * T_CLKZERO_C (RW) 87 * 88 * the number of byteclk cycles that clock lane clkp/n lines are at the hs-zero state hs-0 during a hs clock transmission 89 */ 90 #define MIPI_DSI_PHY_CLANE_PARA2_T_CLKZERO_C_MASK (0xFF00U) 91 #define MIPI_DSI_PHY_CLANE_PARA2_T_CLKZERO_C_SHIFT (8U) 92 #define MIPI_DSI_PHY_CLANE_PARA2_T_CLKZERO_C_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_PARA2_T_CLKZERO_C_SHIFT) & MIPI_DSI_PHY_CLANE_PARA2_T_CLKZERO_C_MASK) 93 #define MIPI_DSI_PHY_CLANE_PARA2_T_CLKZERO_C_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_PARA2_T_CLKZERO_C_MASK) >> MIPI_DSI_PHY_CLANE_PARA2_T_CLKZERO_C_SHIFT) 94 95 /* 96 * T_CLKPRE_C (RW) 97 * 98 * the number of byteclk cycles that hs clock shall be driven prior to data lane beginning the transition from lp to hs mode 99 */ 100 #define MIPI_DSI_PHY_CLANE_PARA2_T_CLKPRE_C_MASK (0xFFU) 101 #define MIPI_DSI_PHY_CLANE_PARA2_T_CLKPRE_C_SHIFT (0U) 102 #define MIPI_DSI_PHY_CLANE_PARA2_T_CLKPRE_C_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_PARA2_T_CLKPRE_C_SHIFT) & MIPI_DSI_PHY_CLANE_PARA2_T_CLKPRE_C_MASK) 103 #define MIPI_DSI_PHY_CLANE_PARA2_T_CLKPRE_C_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_PARA2_T_CLKPRE_C_MASK) >> MIPI_DSI_PHY_CLANE_PARA2_T_CLKPRE_C_SHIFT) 104 105 /* Bitfield definition for register: CLANE_PARA3 */ 106 /* 107 * T_CLKPOST_C (RW) 108 * 109 * the number of byteclk cycles that the clock lane should keep sending the hs-clock after the last associated data lane has transitioned to LP mode. 110 */ 111 #define MIPI_DSI_PHY_CLANE_PARA3_T_CLKPOST_C_MASK (0xFF0000UL) 112 #define MIPI_DSI_PHY_CLANE_PARA3_T_CLKPOST_C_SHIFT (16U) 113 #define MIPI_DSI_PHY_CLANE_PARA3_T_CLKPOST_C_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_PARA3_T_CLKPOST_C_SHIFT) & MIPI_DSI_PHY_CLANE_PARA3_T_CLKPOST_C_MASK) 114 #define MIPI_DSI_PHY_CLANE_PARA3_T_CLKPOST_C_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_PARA3_T_CLKPOST_C_MASK) >> MIPI_DSI_PHY_CLANE_PARA3_T_CLKPOST_C_SHIFT) 115 116 /* 117 * T_CLKTRIAL_C (RW) 118 * 119 * the number of byteclk cycles that the clock lane clkp/n lines are at state hs-tail sate hs-0 during a hs clock transmission 120 */ 121 #define MIPI_DSI_PHY_CLANE_PARA3_T_CLKTRIAL_C_MASK (0xFF00U) 122 #define MIPI_DSI_PHY_CLANE_PARA3_T_CLKTRIAL_C_SHIFT (8U) 123 #define MIPI_DSI_PHY_CLANE_PARA3_T_CLKTRIAL_C_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_PARA3_T_CLKTRIAL_C_SHIFT) & MIPI_DSI_PHY_CLANE_PARA3_T_CLKTRIAL_C_MASK) 124 #define MIPI_DSI_PHY_CLANE_PARA3_T_CLKTRIAL_C_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_PARA3_T_CLKTRIAL_C_MASK) >> MIPI_DSI_PHY_CLANE_PARA3_T_CLKTRIAL_C_SHIFT) 125 126 /* 127 * T_HSEXIT_C (RW) 128 * 129 * the number of byteclk cycles that the clock lane clkp/n lines are at hs-exit state after a hs clock transmission 130 */ 131 #define MIPI_DSI_PHY_CLANE_PARA3_T_HSEXIT_C_MASK (0xFFU) 132 #define MIPI_DSI_PHY_CLANE_PARA3_T_HSEXIT_C_SHIFT (0U) 133 #define MIPI_DSI_PHY_CLANE_PARA3_T_HSEXIT_C_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_PARA3_T_HSEXIT_C_SHIFT) & MIPI_DSI_PHY_CLANE_PARA3_T_HSEXIT_C_MASK) 134 #define MIPI_DSI_PHY_CLANE_PARA3_T_HSEXIT_C_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_PARA3_T_HSEXIT_C_MASK) >> MIPI_DSI_PHY_CLANE_PARA3_T_HSEXIT_C_SHIFT) 135 136 /* Bitfield definition for register: DLANE0_PARA0 */ 137 /* 138 * T_RST2ENLPTX_D0 (RW) 139 * 140 * the number of byteclk cycles that datalane0 wait to enable lptx_en after reset release 141 */ 142 #define MIPI_DSI_PHY_DLANE0_PARA0_T_RST2ENLPTX_D0_MASK (0xFFFFU) 143 #define MIPI_DSI_PHY_DLANE0_PARA0_T_RST2ENLPTX_D0_SHIFT (0U) 144 #define MIPI_DSI_PHY_DLANE0_PARA0_T_RST2ENLPTX_D0_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA0_T_RST2ENLPTX_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA0_T_RST2ENLPTX_D0_MASK) 145 #define MIPI_DSI_PHY_DLANE0_PARA0_T_RST2ENLPTX_D0_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA0_T_RST2ENLPTX_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA0_T_RST2ENLPTX_D0_SHIFT) 146 147 /* Bitfield definition for register: DLANE0_PARA1 */ 148 /* 149 * T_INITTIME_D0 (RW) 150 * 151 * the number of byteclk cycles that datalane0 drive lp-11 during initiaalization period 152 */ 153 #define MIPI_DSI_PHY_DLANE0_PARA1_T_INITTIME_D0_MASK (0xFFFFFFFFUL) 154 #define MIPI_DSI_PHY_DLANE0_PARA1_T_INITTIME_D0_SHIFT (0U) 155 #define MIPI_DSI_PHY_DLANE0_PARA1_T_INITTIME_D0_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA1_T_INITTIME_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA1_T_INITTIME_D0_MASK) 156 #define MIPI_DSI_PHY_DLANE0_PARA1_T_INITTIME_D0_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA1_T_INITTIME_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA1_T_INITTIME_D0_SHIFT) 157 158 /* Bitfield definition for register: DLANE0_PARA2 */ 159 /* 160 * T_HSPREPARE_D0 (RW) 161 * 162 * the number of byteclk cycles that the datalane0 stay at hs prepare state lp-00 during a hs transmission 163 */ 164 #define MIPI_DSI_PHY_DLANE0_PARA2_T_HSPREPARE_D0_MASK (0xFF000000UL) 165 #define MIPI_DSI_PHY_DLANE0_PARA2_T_HSPREPARE_D0_SHIFT (24U) 166 #define MIPI_DSI_PHY_DLANE0_PARA2_T_HSPREPARE_D0_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA2_T_HSPREPARE_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA2_T_HSPREPARE_D0_MASK) 167 #define MIPI_DSI_PHY_DLANE0_PARA2_T_HSPREPARE_D0_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA2_T_HSPREPARE_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA2_T_HSPREPARE_D0_SHIFT) 168 169 /* 170 * T_HSZERO_D0 (RW) 171 * 172 * the number of byteclk cycles that the datalane0 stay at hs-zero sate during a hs transmission 173 */ 174 #define MIPI_DSI_PHY_DLANE0_PARA2_T_HSZERO_D0_MASK (0xFF0000UL) 175 #define MIPI_DSI_PHY_DLANE0_PARA2_T_HSZERO_D0_SHIFT (16U) 176 #define MIPI_DSI_PHY_DLANE0_PARA2_T_HSZERO_D0_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA2_T_HSZERO_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA2_T_HSZERO_D0_MASK) 177 #define MIPI_DSI_PHY_DLANE0_PARA2_T_HSZERO_D0_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA2_T_HSZERO_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA2_T_HSZERO_D0_SHIFT) 178 179 /* 180 * T_HSTRAIL_D0 (RW) 181 * 182 * the number of byteclk cycles that the datalane0 stay at hs-trail state during a hs clock trasmission 183 */ 184 #define MIPI_DSI_PHY_DLANE0_PARA2_T_HSTRAIL_D0_MASK (0xFF00U) 185 #define MIPI_DSI_PHY_DLANE0_PARA2_T_HSTRAIL_D0_SHIFT (8U) 186 #define MIPI_DSI_PHY_DLANE0_PARA2_T_HSTRAIL_D0_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA2_T_HSTRAIL_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA2_T_HSTRAIL_D0_MASK) 187 #define MIPI_DSI_PHY_DLANE0_PARA2_T_HSTRAIL_D0_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA2_T_HSTRAIL_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA2_T_HSTRAIL_D0_SHIFT) 188 189 /* 190 * T_HSEXIT_D0 (RW) 191 * 192 * the number of byteclk cycles that the datalane0 stay at state hs-exit sate after a hs clock trasmission 193 */ 194 #define MIPI_DSI_PHY_DLANE0_PARA2_T_HSEXIT_D0_MASK (0xFFU) 195 #define MIPI_DSI_PHY_DLANE0_PARA2_T_HSEXIT_D0_SHIFT (0U) 196 #define MIPI_DSI_PHY_DLANE0_PARA2_T_HSEXIT_D0_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA2_T_HSEXIT_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA2_T_HSEXIT_D0_MASK) 197 #define MIPI_DSI_PHY_DLANE0_PARA2_T_HSEXIT_D0_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA2_T_HSEXIT_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA2_T_HSEXIT_D0_SHIFT) 198 199 /* Bitfield definition for register: DLANE0_PARA3 */ 200 /* 201 * T_WAKEUP_D0 (RW) 202 * 203 * the number of byteclk cycles from exiting ultra low power sate to enabling the low-power driver 204 */ 205 #define MIPI_DSI_PHY_DLANE0_PARA3_T_WAKEUP_D0_MASK (0xFFFFFFFFUL) 206 #define MIPI_DSI_PHY_DLANE0_PARA3_T_WAKEUP_D0_SHIFT (0U) 207 #define MIPI_DSI_PHY_DLANE0_PARA3_T_WAKEUP_D0_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA3_T_WAKEUP_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA3_T_WAKEUP_D0_MASK) 208 #define MIPI_DSI_PHY_DLANE0_PARA3_T_WAKEUP_D0_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA3_T_WAKEUP_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA3_T_WAKEUP_D0_SHIFT) 209 210 /* Bitfield definition for register: DLANE0_PARA4 */ 211 /* 212 * T_TAGO_D0 (RW) 213 * 214 * the number of byteclk cycles that the tx drives the bridge state during a turnaroud procedure 215 */ 216 #define MIPI_DSI_PHY_DLANE0_PARA4_T_TAGO_D0_MASK (0xFF0000UL) 217 #define MIPI_DSI_PHY_DLANE0_PARA4_T_TAGO_D0_SHIFT (16U) 218 #define MIPI_DSI_PHY_DLANE0_PARA4_T_TAGO_D0_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA4_T_TAGO_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA4_T_TAGO_D0_MASK) 219 #define MIPI_DSI_PHY_DLANE0_PARA4_T_TAGO_D0_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA4_T_TAGO_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA4_T_TAGO_D0_SHIFT) 220 221 /* 222 * T_TASURE_D0 (RW) 223 * 224 * the number of byteclk cycles that the rx waits after a bridge state has been detected during a turnaround procedure 225 */ 226 #define MIPI_DSI_PHY_DLANE0_PARA4_T_TASURE_D0_MASK (0xFF00U) 227 #define MIPI_DSI_PHY_DLANE0_PARA4_T_TASURE_D0_SHIFT (8U) 228 #define MIPI_DSI_PHY_DLANE0_PARA4_T_TASURE_D0_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA4_T_TASURE_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA4_T_TASURE_D0_MASK) 229 #define MIPI_DSI_PHY_DLANE0_PARA4_T_TASURE_D0_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA4_T_TASURE_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA4_T_TASURE_D0_SHIFT) 230 231 /* 232 * T_TAGET_D0 (RW) 233 * 234 * the number of byteclk cycles that the new transmitter drivers the bridge state after accepting control during bta 235 */ 236 #define MIPI_DSI_PHY_DLANE0_PARA4_T_TAGET_D0_MASK (0xFFU) 237 #define MIPI_DSI_PHY_DLANE0_PARA4_T_TAGET_D0_SHIFT (0U) 238 #define MIPI_DSI_PHY_DLANE0_PARA4_T_TAGET_D0_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA4_T_TAGET_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA4_T_TAGET_D0_MASK) 239 #define MIPI_DSI_PHY_DLANE0_PARA4_T_TAGET_D0_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA4_T_TAGET_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA4_T_TAGET_D0_SHIFT) 240 241 /* Bitfield definition for register: DLANE1_PARA0 */ 242 /* 243 * T_RST2ENLPTX_D1 (RW) 244 * 245 * the number of byteclk cycles that datalane1 wait to enable lptx_en after reset release 246 */ 247 #define MIPI_DSI_PHY_DLANE1_PARA0_T_RST2ENLPTX_D1_MASK (0xFFFFU) 248 #define MIPI_DSI_PHY_DLANE1_PARA0_T_RST2ENLPTX_D1_SHIFT (0U) 249 #define MIPI_DSI_PHY_DLANE1_PARA0_T_RST2ENLPTX_D1_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE1_PARA0_T_RST2ENLPTX_D1_SHIFT) & MIPI_DSI_PHY_DLANE1_PARA0_T_RST2ENLPTX_D1_MASK) 250 #define MIPI_DSI_PHY_DLANE1_PARA0_T_RST2ENLPTX_D1_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE1_PARA0_T_RST2ENLPTX_D1_MASK) >> MIPI_DSI_PHY_DLANE1_PARA0_T_RST2ENLPTX_D1_SHIFT) 251 252 /* Bitfield definition for register: DLANE1_PARA1 */ 253 /* 254 * T_INITTIME_D1 (RW) 255 * 256 * the number of byteclk cycles that datalane1 drive lp-11 during initiaalization period 257 */ 258 #define MIPI_DSI_PHY_DLANE1_PARA1_T_INITTIME_D1_MASK (0xFFFFFFFFUL) 259 #define MIPI_DSI_PHY_DLANE1_PARA1_T_INITTIME_D1_SHIFT (0U) 260 #define MIPI_DSI_PHY_DLANE1_PARA1_T_INITTIME_D1_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE1_PARA1_T_INITTIME_D1_SHIFT) & MIPI_DSI_PHY_DLANE1_PARA1_T_INITTIME_D1_MASK) 261 #define MIPI_DSI_PHY_DLANE1_PARA1_T_INITTIME_D1_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE1_PARA1_T_INITTIME_D1_MASK) >> MIPI_DSI_PHY_DLANE1_PARA1_T_INITTIME_D1_SHIFT) 262 263 /* Bitfield definition for register: DLANE1_PARA2 */ 264 /* 265 * T_HSPREPARE_D1 (RW) 266 * 267 * the number of byteclk cycles that the datalane1 stay at hs prepare state lp-00 during a hs transmission 268 */ 269 #define MIPI_DSI_PHY_DLANE1_PARA2_T_HSPREPARE_D1_MASK (0xFF000000UL) 270 #define MIPI_DSI_PHY_DLANE1_PARA2_T_HSPREPARE_D1_SHIFT (24U) 271 #define MIPI_DSI_PHY_DLANE1_PARA2_T_HSPREPARE_D1_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE1_PARA2_T_HSPREPARE_D1_SHIFT) & MIPI_DSI_PHY_DLANE1_PARA2_T_HSPREPARE_D1_MASK) 272 #define MIPI_DSI_PHY_DLANE1_PARA2_T_HSPREPARE_D1_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE1_PARA2_T_HSPREPARE_D1_MASK) >> MIPI_DSI_PHY_DLANE1_PARA2_T_HSPREPARE_D1_SHIFT) 273 274 /* 275 * T_HSZERO_D1 (RW) 276 * 277 * the number of byteclk cycles that the datalane1 stay at hs-zero sate during a hs transmission 278 */ 279 #define MIPI_DSI_PHY_DLANE1_PARA2_T_HSZERO_D1_MASK (0xFF0000UL) 280 #define MIPI_DSI_PHY_DLANE1_PARA2_T_HSZERO_D1_SHIFT (16U) 281 #define MIPI_DSI_PHY_DLANE1_PARA2_T_HSZERO_D1_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE1_PARA2_T_HSZERO_D1_SHIFT) & MIPI_DSI_PHY_DLANE1_PARA2_T_HSZERO_D1_MASK) 282 #define MIPI_DSI_PHY_DLANE1_PARA2_T_HSZERO_D1_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE1_PARA2_T_HSZERO_D1_MASK) >> MIPI_DSI_PHY_DLANE1_PARA2_T_HSZERO_D1_SHIFT) 283 284 /* 285 * T_HSTRAIL_D1 (RW) 286 * 287 * the number of byteclk cycles that the datalane1 stay at hs-trail state during a hs clock trasmission 288 */ 289 #define MIPI_DSI_PHY_DLANE1_PARA2_T_HSTRAIL_D1_MASK (0xFF00U) 290 #define MIPI_DSI_PHY_DLANE1_PARA2_T_HSTRAIL_D1_SHIFT (8U) 291 #define MIPI_DSI_PHY_DLANE1_PARA2_T_HSTRAIL_D1_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE1_PARA2_T_HSTRAIL_D1_SHIFT) & MIPI_DSI_PHY_DLANE1_PARA2_T_HSTRAIL_D1_MASK) 292 #define MIPI_DSI_PHY_DLANE1_PARA2_T_HSTRAIL_D1_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE1_PARA2_T_HSTRAIL_D1_MASK) >> MIPI_DSI_PHY_DLANE1_PARA2_T_HSTRAIL_D1_SHIFT) 293 294 /* 295 * T_HSEXIT_D1 (RW) 296 * 297 * the number of byteclk cycles that the datalane1 stay at state hs-exit sate after a hs clock trasmission 298 */ 299 #define MIPI_DSI_PHY_DLANE1_PARA2_T_HSEXIT_D1_MASK (0xFFU) 300 #define MIPI_DSI_PHY_DLANE1_PARA2_T_HSEXIT_D1_SHIFT (0U) 301 #define MIPI_DSI_PHY_DLANE1_PARA2_T_HSEXIT_D1_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE1_PARA2_T_HSEXIT_D1_SHIFT) & MIPI_DSI_PHY_DLANE1_PARA2_T_HSEXIT_D1_MASK) 302 #define MIPI_DSI_PHY_DLANE1_PARA2_T_HSEXIT_D1_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE1_PARA2_T_HSEXIT_D1_MASK) >> MIPI_DSI_PHY_DLANE1_PARA2_T_HSEXIT_D1_SHIFT) 303 304 /* Bitfield definition for register: DLANE1_PARA3 */ 305 /* 306 * T_WAKEUP_D1 (RW) 307 * 308 * the number of byteclk cycles from exiting ultra low power sate to enabling the low-power driver 309 */ 310 #define MIPI_DSI_PHY_DLANE1_PARA3_T_WAKEUP_D1_MASK (0xFFFFFFFFUL) 311 #define MIPI_DSI_PHY_DLANE1_PARA3_T_WAKEUP_D1_SHIFT (0U) 312 #define MIPI_DSI_PHY_DLANE1_PARA3_T_WAKEUP_D1_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE1_PARA3_T_WAKEUP_D1_SHIFT) & MIPI_DSI_PHY_DLANE1_PARA3_T_WAKEUP_D1_MASK) 313 #define MIPI_DSI_PHY_DLANE1_PARA3_T_WAKEUP_D1_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE1_PARA3_T_WAKEUP_D1_MASK) >> MIPI_DSI_PHY_DLANE1_PARA3_T_WAKEUP_D1_SHIFT) 314 315 /* Bitfield definition for register: DLANE2_PARA0 */ 316 /* 317 * T_RST2ENLPTX_D2 (RW) 318 * 319 * the number of byteclk cycles that datalane2 wait to enable lptx_en after reset release 320 */ 321 #define MIPI_DSI_PHY_DLANE2_PARA0_T_RST2ENLPTX_D2_MASK (0xFFFFU) 322 #define MIPI_DSI_PHY_DLANE2_PARA0_T_RST2ENLPTX_D2_SHIFT (0U) 323 #define MIPI_DSI_PHY_DLANE2_PARA0_T_RST2ENLPTX_D2_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE2_PARA0_T_RST2ENLPTX_D2_SHIFT) & MIPI_DSI_PHY_DLANE2_PARA0_T_RST2ENLPTX_D2_MASK) 324 #define MIPI_DSI_PHY_DLANE2_PARA0_T_RST2ENLPTX_D2_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE2_PARA0_T_RST2ENLPTX_D2_MASK) >> MIPI_DSI_PHY_DLANE2_PARA0_T_RST2ENLPTX_D2_SHIFT) 325 326 /* Bitfield definition for register: DLANE2_PARA1 */ 327 /* 328 * T_INITTIME_D2 (RW) 329 * 330 * the number of byteclk cycles that datalane2 drive lp-11 during initiaalization period 331 */ 332 #define MIPI_DSI_PHY_DLANE2_PARA1_T_INITTIME_D2_MASK (0xFFFFFFFFUL) 333 #define MIPI_DSI_PHY_DLANE2_PARA1_T_INITTIME_D2_SHIFT (0U) 334 #define MIPI_DSI_PHY_DLANE2_PARA1_T_INITTIME_D2_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE2_PARA1_T_INITTIME_D2_SHIFT) & MIPI_DSI_PHY_DLANE2_PARA1_T_INITTIME_D2_MASK) 335 #define MIPI_DSI_PHY_DLANE2_PARA1_T_INITTIME_D2_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE2_PARA1_T_INITTIME_D2_MASK) >> MIPI_DSI_PHY_DLANE2_PARA1_T_INITTIME_D2_SHIFT) 336 337 /* Bitfield definition for register: DLANE2_PARA2 */ 338 /* 339 * T_HSPREPARE_D2 (RW) 340 * 341 * the number of byteclk cycles that the datalane2 stay at hs prepare state lp-00 during a hs transmission 342 */ 343 #define MIPI_DSI_PHY_DLANE2_PARA2_T_HSPREPARE_D2_MASK (0xFF000000UL) 344 #define MIPI_DSI_PHY_DLANE2_PARA2_T_HSPREPARE_D2_SHIFT (24U) 345 #define MIPI_DSI_PHY_DLANE2_PARA2_T_HSPREPARE_D2_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE2_PARA2_T_HSPREPARE_D2_SHIFT) & MIPI_DSI_PHY_DLANE2_PARA2_T_HSPREPARE_D2_MASK) 346 #define MIPI_DSI_PHY_DLANE2_PARA2_T_HSPREPARE_D2_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE2_PARA2_T_HSPREPARE_D2_MASK) >> MIPI_DSI_PHY_DLANE2_PARA2_T_HSPREPARE_D2_SHIFT) 347 348 /* 349 * T_HSZERO_D2 (RW) 350 * 351 * the number of byteclk cycles that the datalane2 stay at hs-zero sate during a hs transmission 352 */ 353 #define MIPI_DSI_PHY_DLANE2_PARA2_T_HSZERO_D2_MASK (0xFF0000UL) 354 #define MIPI_DSI_PHY_DLANE2_PARA2_T_HSZERO_D2_SHIFT (16U) 355 #define MIPI_DSI_PHY_DLANE2_PARA2_T_HSZERO_D2_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE2_PARA2_T_HSZERO_D2_SHIFT) & MIPI_DSI_PHY_DLANE2_PARA2_T_HSZERO_D2_MASK) 356 #define MIPI_DSI_PHY_DLANE2_PARA2_T_HSZERO_D2_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE2_PARA2_T_HSZERO_D2_MASK) >> MIPI_DSI_PHY_DLANE2_PARA2_T_HSZERO_D2_SHIFT) 357 358 /* 359 * T_HSTRAIL_D2 (RW) 360 * 361 * the number of byteclk cycles that the datalane2 stay at hs-trail state during a hs clock trasmission 362 */ 363 #define MIPI_DSI_PHY_DLANE2_PARA2_T_HSTRAIL_D2_MASK (0xFF00U) 364 #define MIPI_DSI_PHY_DLANE2_PARA2_T_HSTRAIL_D2_SHIFT (8U) 365 #define MIPI_DSI_PHY_DLANE2_PARA2_T_HSTRAIL_D2_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE2_PARA2_T_HSTRAIL_D2_SHIFT) & MIPI_DSI_PHY_DLANE2_PARA2_T_HSTRAIL_D2_MASK) 366 #define MIPI_DSI_PHY_DLANE2_PARA2_T_HSTRAIL_D2_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE2_PARA2_T_HSTRAIL_D2_MASK) >> MIPI_DSI_PHY_DLANE2_PARA2_T_HSTRAIL_D2_SHIFT) 367 368 /* 369 * T_HSEXIT_D2 (RW) 370 * 371 * the number of byteclk cycles that the datalane2 stay at state hs-exit sate after a hs clock trasmission 372 */ 373 #define MIPI_DSI_PHY_DLANE2_PARA2_T_HSEXIT_D2_MASK (0xFFU) 374 #define MIPI_DSI_PHY_DLANE2_PARA2_T_HSEXIT_D2_SHIFT (0U) 375 #define MIPI_DSI_PHY_DLANE2_PARA2_T_HSEXIT_D2_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE2_PARA2_T_HSEXIT_D2_SHIFT) & MIPI_DSI_PHY_DLANE2_PARA2_T_HSEXIT_D2_MASK) 376 #define MIPI_DSI_PHY_DLANE2_PARA2_T_HSEXIT_D2_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE2_PARA2_T_HSEXIT_D2_MASK) >> MIPI_DSI_PHY_DLANE2_PARA2_T_HSEXIT_D2_SHIFT) 377 378 /* Bitfield definition for register: DLANE2_PARA3 */ 379 /* 380 * T_WAKEUP_D2 (RW) 381 * 382 * the number of byteclk cycles from exiting ultra low power sate to enabling the low-power driver 383 */ 384 #define MIPI_DSI_PHY_DLANE2_PARA3_T_WAKEUP_D2_MASK (0xFFFFFFFFUL) 385 #define MIPI_DSI_PHY_DLANE2_PARA3_T_WAKEUP_D2_SHIFT (0U) 386 #define MIPI_DSI_PHY_DLANE2_PARA3_T_WAKEUP_D2_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE2_PARA3_T_WAKEUP_D2_SHIFT) & MIPI_DSI_PHY_DLANE2_PARA3_T_WAKEUP_D2_MASK) 387 #define MIPI_DSI_PHY_DLANE2_PARA3_T_WAKEUP_D2_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE2_PARA3_T_WAKEUP_D2_MASK) >> MIPI_DSI_PHY_DLANE2_PARA3_T_WAKEUP_D2_SHIFT) 388 389 /* Bitfield definition for register: DLANE3_PARA0 */ 390 /* 391 * T_RST2ENLPTX_D3 (RW) 392 * 393 * the number of byteclk cycles that datalane3 wait to enable lptx_en after reset release 394 */ 395 #define MIPI_DSI_PHY_DLANE3_PARA0_T_RST2ENLPTX_D3_MASK (0xFFFFU) 396 #define MIPI_DSI_PHY_DLANE3_PARA0_T_RST2ENLPTX_D3_SHIFT (0U) 397 #define MIPI_DSI_PHY_DLANE3_PARA0_T_RST2ENLPTX_D3_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE3_PARA0_T_RST2ENLPTX_D3_SHIFT) & MIPI_DSI_PHY_DLANE3_PARA0_T_RST2ENLPTX_D3_MASK) 398 #define MIPI_DSI_PHY_DLANE3_PARA0_T_RST2ENLPTX_D3_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE3_PARA0_T_RST2ENLPTX_D3_MASK) >> MIPI_DSI_PHY_DLANE3_PARA0_T_RST2ENLPTX_D3_SHIFT) 399 400 /* Bitfield definition for register: DLANE3_PARA1 */ 401 /* 402 * T_INITTIME_D3 (RW) 403 * 404 * the number of byteclk cycles that datalane3 drive lp-11 during initiaalization period 405 */ 406 #define MIPI_DSI_PHY_DLANE3_PARA1_T_INITTIME_D3_MASK (0xFFFFFFFFUL) 407 #define MIPI_DSI_PHY_DLANE3_PARA1_T_INITTIME_D3_SHIFT (0U) 408 #define MIPI_DSI_PHY_DLANE3_PARA1_T_INITTIME_D3_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE3_PARA1_T_INITTIME_D3_SHIFT) & MIPI_DSI_PHY_DLANE3_PARA1_T_INITTIME_D3_MASK) 409 #define MIPI_DSI_PHY_DLANE3_PARA1_T_INITTIME_D3_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE3_PARA1_T_INITTIME_D3_MASK) >> MIPI_DSI_PHY_DLANE3_PARA1_T_INITTIME_D3_SHIFT) 410 411 /* Bitfield definition for register: DLANE3_PARA2 */ 412 /* 413 * T_HSPREPARE_D3 (RW) 414 * 415 * the number of byteclk cycles that the datalane3 stay at hs prepare state lp-00 during a hs transmission 416 */ 417 #define MIPI_DSI_PHY_DLANE3_PARA2_T_HSPREPARE_D3_MASK (0xFF000000UL) 418 #define MIPI_DSI_PHY_DLANE3_PARA2_T_HSPREPARE_D3_SHIFT (24U) 419 #define MIPI_DSI_PHY_DLANE3_PARA2_T_HSPREPARE_D3_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE3_PARA2_T_HSPREPARE_D3_SHIFT) & MIPI_DSI_PHY_DLANE3_PARA2_T_HSPREPARE_D3_MASK) 420 #define MIPI_DSI_PHY_DLANE3_PARA2_T_HSPREPARE_D3_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE3_PARA2_T_HSPREPARE_D3_MASK) >> MIPI_DSI_PHY_DLANE3_PARA2_T_HSPREPARE_D3_SHIFT) 421 422 /* 423 * T_HSZERO_D3 (RW) 424 * 425 * the number of byteclk cycles that the datalane3 stay at hs-zero sate during a hs transmission 426 */ 427 #define MIPI_DSI_PHY_DLANE3_PARA2_T_HSZERO_D3_MASK (0xFF0000UL) 428 #define MIPI_DSI_PHY_DLANE3_PARA2_T_HSZERO_D3_SHIFT (16U) 429 #define MIPI_DSI_PHY_DLANE3_PARA2_T_HSZERO_D3_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE3_PARA2_T_HSZERO_D3_SHIFT) & MIPI_DSI_PHY_DLANE3_PARA2_T_HSZERO_D3_MASK) 430 #define MIPI_DSI_PHY_DLANE3_PARA2_T_HSZERO_D3_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE3_PARA2_T_HSZERO_D3_MASK) >> MIPI_DSI_PHY_DLANE3_PARA2_T_HSZERO_D3_SHIFT) 431 432 /* 433 * T_HSTRAIL_D3 (RW) 434 * 435 * the number of byteclk cycles that the datalane3 stay at hs-trail state during a hs clock trasmission 436 */ 437 #define MIPI_DSI_PHY_DLANE3_PARA2_T_HSTRAIL_D3_MASK (0xFF00U) 438 #define MIPI_DSI_PHY_DLANE3_PARA2_T_HSTRAIL_D3_SHIFT (8U) 439 #define MIPI_DSI_PHY_DLANE3_PARA2_T_HSTRAIL_D3_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE3_PARA2_T_HSTRAIL_D3_SHIFT) & MIPI_DSI_PHY_DLANE3_PARA2_T_HSTRAIL_D3_MASK) 440 #define MIPI_DSI_PHY_DLANE3_PARA2_T_HSTRAIL_D3_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE3_PARA2_T_HSTRAIL_D3_MASK) >> MIPI_DSI_PHY_DLANE3_PARA2_T_HSTRAIL_D3_SHIFT) 441 442 /* 443 * T_HSEXIT_D3 (RW) 444 * 445 * the number of byteclk cycles that the datalane3 stay at state hs-exit sate after a hs clock trasmission 446 */ 447 #define MIPI_DSI_PHY_DLANE3_PARA2_T_HSEXIT_D3_MASK (0xFFU) 448 #define MIPI_DSI_PHY_DLANE3_PARA2_T_HSEXIT_D3_SHIFT (0U) 449 #define MIPI_DSI_PHY_DLANE3_PARA2_T_HSEXIT_D3_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE3_PARA2_T_HSEXIT_D3_SHIFT) & MIPI_DSI_PHY_DLANE3_PARA2_T_HSEXIT_D3_MASK) 450 #define MIPI_DSI_PHY_DLANE3_PARA2_T_HSEXIT_D3_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE3_PARA2_T_HSEXIT_D3_MASK) >> MIPI_DSI_PHY_DLANE3_PARA2_T_HSEXIT_D3_SHIFT) 451 452 /* Bitfield definition for register: DLANE3_PARA3 */ 453 /* 454 * T_WAKEUP_D3 (RW) 455 * 456 * the number of byteclk cycles from exiting ultra low power sate to enabling the low-power driver 457 */ 458 #define MIPI_DSI_PHY_DLANE3_PARA3_T_WAKEUP_D3_MASK (0xFFFFFFFFUL) 459 #define MIPI_DSI_PHY_DLANE3_PARA3_T_WAKEUP_D3_SHIFT (0U) 460 #define MIPI_DSI_PHY_DLANE3_PARA3_T_WAKEUP_D3_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE3_PARA3_T_WAKEUP_D3_SHIFT) & MIPI_DSI_PHY_DLANE3_PARA3_T_WAKEUP_D3_MASK) 461 #define MIPI_DSI_PHY_DLANE3_PARA3_T_WAKEUP_D3_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE3_PARA3_T_WAKEUP_D3_MASK) >> MIPI_DSI_PHY_DLANE3_PARA3_T_WAKEUP_D3_SHIFT) 462 463 /* Bitfield definition for register: COMMON_PARA0 */ 464 /* 465 * T_LPX (RW) 466 * 467 * the number of byteclk cycles of transmitted length of any low-power state period 468 */ 469 #define MIPI_DSI_PHY_COMMON_PARA0_T_LPX_MASK (0xFFU) 470 #define MIPI_DSI_PHY_COMMON_PARA0_T_LPX_SHIFT (0U) 471 #define MIPI_DSI_PHY_COMMON_PARA0_T_LPX_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_COMMON_PARA0_T_LPX_SHIFT) & MIPI_DSI_PHY_COMMON_PARA0_T_LPX_MASK) 472 #define MIPI_DSI_PHY_COMMON_PARA0_T_LPX_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_COMMON_PARA0_T_LPX_MASK) >> MIPI_DSI_PHY_COMMON_PARA0_T_LPX_SHIFT) 473 474 /* Bitfield definition for register: CTRL_PARA0 */ 475 /* 476 * VBG_RDY (RO) 477 * 478 * the indicator signal of reference generator is ready 479 */ 480 #define MIPI_DSI_PHY_CTRL_PARA0_VBG_RDY_MASK (0x80U) 481 #define MIPI_DSI_PHY_CTRL_PARA0_VBG_RDY_SHIFT (7U) 482 #define MIPI_DSI_PHY_CTRL_PARA0_VBG_RDY_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CTRL_PARA0_VBG_RDY_MASK) >> MIPI_DSI_PHY_CTRL_PARA0_VBG_RDY_SHIFT) 483 484 /* 485 * EN_ULPRX_D0 (RW) 486 * 487 * ulp-rx enable for lane0 488 */ 489 #define MIPI_DSI_PHY_CTRL_PARA0_EN_ULPRX_D0_MASK (0x40U) 490 #define MIPI_DSI_PHY_CTRL_PARA0_EN_ULPRX_D0_SHIFT (6U) 491 #define MIPI_DSI_PHY_CTRL_PARA0_EN_ULPRX_D0_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CTRL_PARA0_EN_ULPRX_D0_SHIFT) & MIPI_DSI_PHY_CTRL_PARA0_EN_ULPRX_D0_MASK) 492 #define MIPI_DSI_PHY_CTRL_PARA0_EN_ULPRX_D0_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CTRL_PARA0_EN_ULPRX_D0_MASK) >> MIPI_DSI_PHY_CTRL_PARA0_EN_ULPRX_D0_SHIFT) 493 494 /* 495 * EN_LPRX_D0 (RW) 496 * 497 * lp-rx enable for lane0 498 */ 499 #define MIPI_DSI_PHY_CTRL_PARA0_EN_LPRX_D0_MASK (0x20U) 500 #define MIPI_DSI_PHY_CTRL_PARA0_EN_LPRX_D0_SHIFT (5U) 501 #define MIPI_DSI_PHY_CTRL_PARA0_EN_LPRX_D0_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CTRL_PARA0_EN_LPRX_D0_SHIFT) & MIPI_DSI_PHY_CTRL_PARA0_EN_LPRX_D0_MASK) 502 #define MIPI_DSI_PHY_CTRL_PARA0_EN_LPRX_D0_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CTRL_PARA0_EN_LPRX_D0_MASK) >> MIPI_DSI_PHY_CTRL_PARA0_EN_LPRX_D0_SHIFT) 503 504 /* 505 * EN_LPCD_D0 (RW) 506 * 507 * lp-cd enable for lane0 508 */ 509 #define MIPI_DSI_PHY_CTRL_PARA0_EN_LPCD_D0_MASK (0x10U) 510 #define MIPI_DSI_PHY_CTRL_PARA0_EN_LPCD_D0_SHIFT (4U) 511 #define MIPI_DSI_PHY_CTRL_PARA0_EN_LPCD_D0_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CTRL_PARA0_EN_LPCD_D0_SHIFT) & MIPI_DSI_PHY_CTRL_PARA0_EN_LPCD_D0_MASK) 512 #define MIPI_DSI_PHY_CTRL_PARA0_EN_LPCD_D0_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CTRL_PARA0_EN_LPCD_D0_MASK) >> MIPI_DSI_PHY_CTRL_PARA0_EN_LPCD_D0_SHIFT) 513 514 /* 515 * PWON_SEL (RW) 516 * 517 * select the cource of PMA power on control signals 518 */ 519 #define MIPI_DSI_PHY_CTRL_PARA0_PWON_SEL_MASK (0x8U) 520 #define MIPI_DSI_PHY_CTRL_PARA0_PWON_SEL_SHIFT (3U) 521 #define MIPI_DSI_PHY_CTRL_PARA0_PWON_SEL_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CTRL_PARA0_PWON_SEL_SHIFT) & MIPI_DSI_PHY_CTRL_PARA0_PWON_SEL_MASK) 522 #define MIPI_DSI_PHY_CTRL_PARA0_PWON_SEL_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CTRL_PARA0_PWON_SEL_MASK) >> MIPI_DSI_PHY_CTRL_PARA0_PWON_SEL_SHIFT) 523 524 /* 525 * PWON_PLL (RW) 526 * 527 * power on pll high active 528 */ 529 #define MIPI_DSI_PHY_CTRL_PARA0_PWON_PLL_MASK (0x4U) 530 #define MIPI_DSI_PHY_CTRL_PARA0_PWON_PLL_SHIFT (2U) 531 #define MIPI_DSI_PHY_CTRL_PARA0_PWON_PLL_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CTRL_PARA0_PWON_PLL_SHIFT) & MIPI_DSI_PHY_CTRL_PARA0_PWON_PLL_MASK) 532 #define MIPI_DSI_PHY_CTRL_PARA0_PWON_PLL_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CTRL_PARA0_PWON_PLL_MASK) >> MIPI_DSI_PHY_CTRL_PARA0_PWON_PLL_SHIFT) 533 534 /* 535 * PWON_DSI (RW) 536 * 537 * power on all dsi lane 538 */ 539 #define MIPI_DSI_PHY_CTRL_PARA0_PWON_DSI_MASK (0x2U) 540 #define MIPI_DSI_PHY_CTRL_PARA0_PWON_DSI_SHIFT (1U) 541 #define MIPI_DSI_PHY_CTRL_PARA0_PWON_DSI_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CTRL_PARA0_PWON_DSI_SHIFT) & MIPI_DSI_PHY_CTRL_PARA0_PWON_DSI_MASK) 542 #define MIPI_DSI_PHY_CTRL_PARA0_PWON_DSI_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CTRL_PARA0_PWON_DSI_MASK) >> MIPI_DSI_PHY_CTRL_PARA0_PWON_DSI_SHIFT) 543 544 /* 545 * SU_IDDQ_EN (RW) 546 * 547 * power down all modules inside su includes ivref, r-calibration and pll, high effective 548 */ 549 #define MIPI_DSI_PHY_CTRL_PARA0_SU_IDDQ_EN_MASK (0x1U) 550 #define MIPI_DSI_PHY_CTRL_PARA0_SU_IDDQ_EN_SHIFT (0U) 551 #define MIPI_DSI_PHY_CTRL_PARA0_SU_IDDQ_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CTRL_PARA0_SU_IDDQ_EN_SHIFT) & MIPI_DSI_PHY_CTRL_PARA0_SU_IDDQ_EN_MASK) 552 #define MIPI_DSI_PHY_CTRL_PARA0_SU_IDDQ_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CTRL_PARA0_SU_IDDQ_EN_MASK) >> MIPI_DSI_PHY_CTRL_PARA0_SU_IDDQ_EN_SHIFT) 553 554 /* Bitfield definition for register: PLL_CTRL_PARA0 */ 555 /* 556 * PLL_LOCK (RO) 557 * 558 * pll lock indication 559 */ 560 #define MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_LOCK_MASK (0x8000000UL) 561 #define MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_LOCK_SHIFT (27U) 562 #define MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_LOCK_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_LOCK_MASK) >> MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_LOCK_SHIFT) 563 564 /* 565 * RATE (RW) 566 * 567 * data reate control signal 568 */ 569 #define MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_MASK (0x7000000UL) 570 #define MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_SHIFT (24U) 571 #define MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_SHIFT) & MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_MASK) 572 #define MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_MASK) >> MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_SHIFT) 573 574 /* 575 * REFCLK_DIV (RW) 576 * 577 * input refrence clock divider ratio control 578 */ 579 #define MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_MASK (0xF80000UL) 580 #define MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_SHIFT (19U) 581 #define MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_SHIFT) & MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_MASK) 582 #define MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_MASK) >> MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_SHIFT) 583 584 /* 585 * PLL_DIV (RW) 586 * 587 * pll loop divider ratio control 588 */ 589 #define MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_MASK (0x7FFF0UL) 590 #define MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_SHIFT (4U) 591 #define MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_SHIFT) & MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_MASK) 592 #define MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_MASK) >> MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_SHIFT) 593 594 /* 595 * DSI_PIXELCLK_DIV (RW) 596 * 597 * pixell clock divided from pll output 598 */ 599 #define MIPI_DSI_PHY_PLL_CTRL_PARA0_DSI_PIXELCLK_DIV_MASK (0xFU) 600 #define MIPI_DSI_PHY_PLL_CTRL_PARA0_DSI_PIXELCLK_DIV_SHIFT (0U) 601 #define MIPI_DSI_PHY_PLL_CTRL_PARA0_DSI_PIXELCLK_DIV_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_PLL_CTRL_PARA0_DSI_PIXELCLK_DIV_SHIFT) & MIPI_DSI_PHY_PLL_CTRL_PARA0_DSI_PIXELCLK_DIV_MASK) 602 #define MIPI_DSI_PHY_PLL_CTRL_PARA0_DSI_PIXELCLK_DIV_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_PLL_CTRL_PARA0_DSI_PIXELCLK_DIV_MASK) >> MIPI_DSI_PHY_PLL_CTRL_PARA0_DSI_PIXELCLK_DIV_SHIFT) 603 604 /* Bitfield definition for register: RCAL_CTRL */ 605 /* 606 * RCAL_EN (RW) 607 * 608 * enable hs-tx output impedance trimming 609 */ 610 #define MIPI_DSI_PHY_RCAL_CTRL_RCAL_EN_MASK (0x2000U) 611 #define MIPI_DSI_PHY_RCAL_CTRL_RCAL_EN_SHIFT (13U) 612 #define MIPI_DSI_PHY_RCAL_CTRL_RCAL_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_RCAL_CTRL_RCAL_EN_SHIFT) & MIPI_DSI_PHY_RCAL_CTRL_RCAL_EN_MASK) 613 #define MIPI_DSI_PHY_RCAL_CTRL_RCAL_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_RCAL_CTRL_RCAL_EN_MASK) >> MIPI_DSI_PHY_RCAL_CTRL_RCAL_EN_SHIFT) 614 615 /* 616 * RCAL_TRIM (RW) 617 * 618 * default value of hs-tx output resistance configure 619 */ 620 #define MIPI_DSI_PHY_RCAL_CTRL_RCAL_TRIM_MASK (0x1E00U) 621 #define MIPI_DSI_PHY_RCAL_CTRL_RCAL_TRIM_SHIFT (9U) 622 #define MIPI_DSI_PHY_RCAL_CTRL_RCAL_TRIM_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_RCAL_CTRL_RCAL_TRIM_SHIFT) & MIPI_DSI_PHY_RCAL_CTRL_RCAL_TRIM_MASK) 623 #define MIPI_DSI_PHY_RCAL_CTRL_RCAL_TRIM_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_RCAL_CTRL_RCAL_TRIM_MASK) >> MIPI_DSI_PHY_RCAL_CTRL_RCAL_TRIM_SHIFT) 624 625 /* 626 * RCAL_CTRL (RW) 627 * 628 * resistor calibration control, reserved for test 629 */ 630 #define MIPI_DSI_PHY_RCAL_CTRL_RCAL_CTRL_MASK (0x1FEU) 631 #define MIPI_DSI_PHY_RCAL_CTRL_RCAL_CTRL_SHIFT (1U) 632 #define MIPI_DSI_PHY_RCAL_CTRL_RCAL_CTRL_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_RCAL_CTRL_RCAL_CTRL_SHIFT) & MIPI_DSI_PHY_RCAL_CTRL_RCAL_CTRL_MASK) 633 #define MIPI_DSI_PHY_RCAL_CTRL_RCAL_CTRL_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_RCAL_CTRL_RCAL_CTRL_MASK) >> MIPI_DSI_PHY_RCAL_CTRL_RCAL_CTRL_SHIFT) 634 635 /* 636 * RCAL_DONE (RO) 637 * 638 * hs-tx output impedance trimming done indicator signal 639 */ 640 #define MIPI_DSI_PHY_RCAL_CTRL_RCAL_DONE_MASK (0x1U) 641 #define MIPI_DSI_PHY_RCAL_CTRL_RCAL_DONE_SHIFT (0U) 642 #define MIPI_DSI_PHY_RCAL_CTRL_RCAL_DONE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_RCAL_CTRL_RCAL_DONE_MASK) >> MIPI_DSI_PHY_RCAL_CTRL_RCAL_DONE_SHIFT) 643 644 /* Bitfield definition for register: TRIM_PARA */ 645 /* 646 * HSTX_AMP_TRIM (RW) 647 * 648 * hs-tx output vod trimming for lane-0~4 649 */ 650 #define MIPI_DSI_PHY_TRIM_PARA_HSTX_AMP_TRIM_MASK (0x3800U) 651 #define MIPI_DSI_PHY_TRIM_PARA_HSTX_AMP_TRIM_SHIFT (11U) 652 #define MIPI_DSI_PHY_TRIM_PARA_HSTX_AMP_TRIM_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TRIM_PARA_HSTX_AMP_TRIM_SHIFT) & MIPI_DSI_PHY_TRIM_PARA_HSTX_AMP_TRIM_MASK) 653 #define MIPI_DSI_PHY_TRIM_PARA_HSTX_AMP_TRIM_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TRIM_PARA_HSTX_AMP_TRIM_MASK) >> MIPI_DSI_PHY_TRIM_PARA_HSTX_AMP_TRIM_SHIFT) 654 655 /* 656 * LPTX_SR_TRIM (RW) 657 * 658 * lp-tx output slew-rate trimming for lane0~4 659 */ 660 #define MIPI_DSI_PHY_TRIM_PARA_LPTX_SR_TRIM_MASK (0x700U) 661 #define MIPI_DSI_PHY_TRIM_PARA_LPTX_SR_TRIM_SHIFT (8U) 662 #define MIPI_DSI_PHY_TRIM_PARA_LPTX_SR_TRIM_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TRIM_PARA_LPTX_SR_TRIM_SHIFT) & MIPI_DSI_PHY_TRIM_PARA_LPTX_SR_TRIM_MASK) 663 #define MIPI_DSI_PHY_TRIM_PARA_LPTX_SR_TRIM_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TRIM_PARA_LPTX_SR_TRIM_MASK) >> MIPI_DSI_PHY_TRIM_PARA_LPTX_SR_TRIM_SHIFT) 664 665 /* 666 * LPRX_VREF_TRIM (RW) 667 * 668 * lp-rx input threshold voltage trimming for lane0 669 */ 670 #define MIPI_DSI_PHY_TRIM_PARA_LPRX_VREF_TRIM_MASK (0xF0U) 671 #define MIPI_DSI_PHY_TRIM_PARA_LPRX_VREF_TRIM_SHIFT (4U) 672 #define MIPI_DSI_PHY_TRIM_PARA_LPRX_VREF_TRIM_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TRIM_PARA_LPRX_VREF_TRIM_SHIFT) & MIPI_DSI_PHY_TRIM_PARA_LPRX_VREF_TRIM_MASK) 673 #define MIPI_DSI_PHY_TRIM_PARA_LPRX_VREF_TRIM_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TRIM_PARA_LPRX_VREF_TRIM_MASK) >> MIPI_DSI_PHY_TRIM_PARA_LPRX_VREF_TRIM_SHIFT) 674 675 /* 676 * LPCD_VREF_TRIM (RW) 677 * 678 * lp-cd input threshold voltage trimming for lane0 679 */ 680 #define MIPI_DSI_PHY_TRIM_PARA_LPCD_VREF_TRIM_MASK (0xFU) 681 #define MIPI_DSI_PHY_TRIM_PARA_LPCD_VREF_TRIM_SHIFT (0U) 682 #define MIPI_DSI_PHY_TRIM_PARA_LPCD_VREF_TRIM_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TRIM_PARA_LPCD_VREF_TRIM_SHIFT) & MIPI_DSI_PHY_TRIM_PARA_LPCD_VREF_TRIM_MASK) 683 #define MIPI_DSI_PHY_TRIM_PARA_LPCD_VREF_TRIM_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TRIM_PARA_LPCD_VREF_TRIM_MASK) >> MIPI_DSI_PHY_TRIM_PARA_LPCD_VREF_TRIM_SHIFT) 684 685 /* Bitfield definition for register: TEST_PARA0 */ 686 /* 687 * ERROR_NUM (RO) 688 * 689 * the byte num of mismatch data of lane in bist mode 690 */ 691 #define MIPI_DSI_PHY_TEST_PARA0_ERROR_NUM_MASK (0x7E0000UL) 692 #define MIPI_DSI_PHY_TEST_PARA0_ERROR_NUM_SHIFT (17U) 693 #define MIPI_DSI_PHY_TEST_PARA0_ERROR_NUM_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA0_ERROR_NUM_MASK) >> MIPI_DSI_PHY_TEST_PARA0_ERROR_NUM_SHIFT) 694 695 /* 696 * BIST_N_DONE (RO) 697 * 698 * indicate prbs7 bist test is done 699 */ 700 #define MIPI_DSI_PHY_TEST_PARA0_BIST_N_DONE_MASK (0x1F000UL) 701 #define MIPI_DSI_PHY_TEST_PARA0_BIST_N_DONE_SHIFT (12U) 702 #define MIPI_DSI_PHY_TEST_PARA0_BIST_N_DONE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA0_BIST_N_DONE_MASK) >> MIPI_DSI_PHY_TEST_PARA0_BIST_N_DONE_SHIFT) 703 704 /* 705 * BIST_N_OK (RO) 706 * 707 * indicate prbs7 bist test is ok 708 */ 709 #define MIPI_DSI_PHY_TEST_PARA0_BIST_N_OK_MASK (0xF80U) 710 #define MIPI_DSI_PHY_TEST_PARA0_BIST_N_OK_SHIFT (7U) 711 #define MIPI_DSI_PHY_TEST_PARA0_BIST_N_OK_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA0_BIST_N_OK_MASK) >> MIPI_DSI_PHY_TEST_PARA0_BIST_N_OK_SHIFT) 712 713 /* 714 * ATEST_EN (RW) 715 * 716 * analog test signal enable 717 */ 718 #define MIPI_DSI_PHY_TEST_PARA0_ATEST_EN_MASK (0x40U) 719 #define MIPI_DSI_PHY_TEST_PARA0_ATEST_EN_SHIFT (6U) 720 #define MIPI_DSI_PHY_TEST_PARA0_ATEST_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA0_ATEST_EN_SHIFT) & MIPI_DSI_PHY_TEST_PARA0_ATEST_EN_MASK) 721 #define MIPI_DSI_PHY_TEST_PARA0_ATEST_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA0_ATEST_EN_MASK) >> MIPI_DSI_PHY_TEST_PARA0_ATEST_EN_SHIFT) 722 723 /* 724 * ATEST_SEL (RW) 725 * 726 * analog test signal select 727 */ 728 #define MIPI_DSI_PHY_TEST_PARA0_ATEST_SEL_MASK (0x30U) 729 #define MIPI_DSI_PHY_TEST_PARA0_ATEST_SEL_SHIFT (4U) 730 #define MIPI_DSI_PHY_TEST_PARA0_ATEST_SEL_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA0_ATEST_SEL_SHIFT) & MIPI_DSI_PHY_TEST_PARA0_ATEST_SEL_MASK) 731 #define MIPI_DSI_PHY_TEST_PARA0_ATEST_SEL_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA0_ATEST_SEL_MASK) >> MIPI_DSI_PHY_TEST_PARA0_ATEST_SEL_SHIFT) 732 733 /* 734 * FSET_EN (RW) 735 * 736 * enable fast transmission between lp-tx and hs-tx 737 */ 738 #define MIPI_DSI_PHY_TEST_PARA0_FSET_EN_MASK (0x8U) 739 #define MIPI_DSI_PHY_TEST_PARA0_FSET_EN_SHIFT (3U) 740 #define MIPI_DSI_PHY_TEST_PARA0_FSET_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA0_FSET_EN_SHIFT) & MIPI_DSI_PHY_TEST_PARA0_FSET_EN_MASK) 741 #define MIPI_DSI_PHY_TEST_PARA0_FSET_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA0_FSET_EN_MASK) >> MIPI_DSI_PHY_TEST_PARA0_FSET_EN_SHIFT) 742 743 /* 744 * FT_SEL (RW) 745 * 746 * pt/ft test mode select 747 */ 748 #define MIPI_DSI_PHY_TEST_PARA0_FT_SEL_MASK (0x7U) 749 #define MIPI_DSI_PHY_TEST_PARA0_FT_SEL_SHIFT (0U) 750 #define MIPI_DSI_PHY_TEST_PARA0_FT_SEL_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA0_FT_SEL_SHIFT) & MIPI_DSI_PHY_TEST_PARA0_FT_SEL_MASK) 751 #define MIPI_DSI_PHY_TEST_PARA0_FT_SEL_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA0_FT_SEL_MASK) >> MIPI_DSI_PHY_TEST_PARA0_FT_SEL_SHIFT) 752 753 /* Bitfield definition for register: TEST_PARA1 */ 754 /* 755 * CHECK_NUM (RW) 756 * 757 * the byte num of prbs bist check num 758 */ 759 #define MIPI_DSI_PHY_TEST_PARA1_CHECK_NUM_MASK (0xFFFFFC00UL) 760 #define MIPI_DSI_PHY_TEST_PARA1_CHECK_NUM_SHIFT (10U) 761 #define MIPI_DSI_PHY_TEST_PARA1_CHECK_NUM_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA1_CHECK_NUM_SHIFT) & MIPI_DSI_PHY_TEST_PARA1_CHECK_NUM_MASK) 762 #define MIPI_DSI_PHY_TEST_PARA1_CHECK_NUM_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA1_CHECK_NUM_MASK) >> MIPI_DSI_PHY_TEST_PARA1_CHECK_NUM_SHIFT) 763 764 /* 765 * ERR_THRESHOLD (RW) 766 * 767 * the threshold of prbs bit error 768 */ 769 #define MIPI_DSI_PHY_TEST_PARA1_ERR_THRESHOLD_MASK (0x3C0U) 770 #define MIPI_DSI_PHY_TEST_PARA1_ERR_THRESHOLD_SHIFT (6U) 771 #define MIPI_DSI_PHY_TEST_PARA1_ERR_THRESHOLD_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA1_ERR_THRESHOLD_SHIFT) & MIPI_DSI_PHY_TEST_PARA1_ERR_THRESHOLD_MASK) 772 #define MIPI_DSI_PHY_TEST_PARA1_ERR_THRESHOLD_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA1_ERR_THRESHOLD_MASK) >> MIPI_DSI_PHY_TEST_PARA1_ERR_THRESHOLD_SHIFT) 773 774 /* 775 * BIST_BIT_ERROR (RW) 776 * 777 * enable insert error in bist test pattern 778 */ 779 #define MIPI_DSI_PHY_TEST_PARA1_BIST_BIT_ERROR_MASK (0x20U) 780 #define MIPI_DSI_PHY_TEST_PARA1_BIST_BIT_ERROR_SHIFT (5U) 781 #define MIPI_DSI_PHY_TEST_PARA1_BIST_BIT_ERROR_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA1_BIST_BIT_ERROR_SHIFT) & MIPI_DSI_PHY_TEST_PARA1_BIST_BIT_ERROR_MASK) 782 #define MIPI_DSI_PHY_TEST_PARA1_BIST_BIT_ERROR_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA1_BIST_BIT_ERROR_MASK) >> MIPI_DSI_PHY_TEST_PARA1_BIST_BIT_ERROR_SHIFT) 783 784 /* 785 * BIST_EN (RW) 786 * 787 * bist enable 788 */ 789 #define MIPI_DSI_PHY_TEST_PARA1_BIST_EN_MASK (0x18U) 790 #define MIPI_DSI_PHY_TEST_PARA1_BIST_EN_SHIFT (3U) 791 #define MIPI_DSI_PHY_TEST_PARA1_BIST_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA1_BIST_EN_SHIFT) & MIPI_DSI_PHY_TEST_PARA1_BIST_EN_MASK) 792 #define MIPI_DSI_PHY_TEST_PARA1_BIST_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA1_BIST_EN_MASK) >> MIPI_DSI_PHY_TEST_PARA1_BIST_EN_SHIFT) 793 794 /* 795 * BIST_SEL (RW) 796 * 797 * bist mode select 798 */ 799 #define MIPI_DSI_PHY_TEST_PARA1_BIST_SEL_MASK (0x4U) 800 #define MIPI_DSI_PHY_TEST_PARA1_BIST_SEL_SHIFT (2U) 801 #define MIPI_DSI_PHY_TEST_PARA1_BIST_SEL_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA1_BIST_SEL_SHIFT) & MIPI_DSI_PHY_TEST_PARA1_BIST_SEL_MASK) 802 #define MIPI_DSI_PHY_TEST_PARA1_BIST_SEL_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA1_BIST_SEL_MASK) >> MIPI_DSI_PHY_TEST_PARA1_BIST_SEL_SHIFT) 803 804 /* 805 * PRBS_SEL (RW) 806 * 807 * prbs generator and checker pattern select signal 808 */ 809 #define MIPI_DSI_PHY_TEST_PARA1_PRBS_SEL_MASK (0x3U) 810 #define MIPI_DSI_PHY_TEST_PARA1_PRBS_SEL_SHIFT (0U) 811 #define MIPI_DSI_PHY_TEST_PARA1_PRBS_SEL_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA1_PRBS_SEL_SHIFT) & MIPI_DSI_PHY_TEST_PARA1_PRBS_SEL_MASK) 812 #define MIPI_DSI_PHY_TEST_PARA1_PRBS_SEL_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA1_PRBS_SEL_MASK) >> MIPI_DSI_PHY_TEST_PARA1_PRBS_SEL_SHIFT) 813 814 /* Bitfield definition for register: MISC_PARA */ 815 /* 816 * DLL_SEL (RW) 817 * 818 * the phase select of clk_rxesc 819 */ 820 #define MIPI_DSI_PHY_MISC_PARA_DLL_SEL_MASK (0x780U) 821 #define MIPI_DSI_PHY_MISC_PARA_DLL_SEL_SHIFT (7U) 822 #define MIPI_DSI_PHY_MISC_PARA_DLL_SEL_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_MISC_PARA_DLL_SEL_SHIFT) & MIPI_DSI_PHY_MISC_PARA_DLL_SEL_MASK) 823 #define MIPI_DSI_PHY_MISC_PARA_DLL_SEL_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_MISC_PARA_DLL_SEL_MASK) >> MIPI_DSI_PHY_MISC_PARA_DLL_SEL_SHIFT) 824 825 /* 826 * LANE_NUM (RW) 827 * 828 * the number of active data lanes 829 */ 830 #define MIPI_DSI_PHY_MISC_PARA_LANE_NUM_MASK (0x60U) 831 #define MIPI_DSI_PHY_MISC_PARA_LANE_NUM_SHIFT (5U) 832 #define MIPI_DSI_PHY_MISC_PARA_LANE_NUM_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_MISC_PARA_LANE_NUM_SHIFT) & MIPI_DSI_PHY_MISC_PARA_LANE_NUM_MASK) 833 #define MIPI_DSI_PHY_MISC_PARA_LANE_NUM_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_MISC_PARA_LANE_NUM_MASK) >> MIPI_DSI_PHY_MISC_PARA_LANE_NUM_SHIFT) 834 835 /* 836 * PHYERR_MASK (RW) 837 * 838 * mask the phy error 839 */ 840 #define MIPI_DSI_PHY_MISC_PARA_PHYERR_MASK_MASK (0x1FU) 841 #define MIPI_DSI_PHY_MISC_PARA_PHYERR_MASK_SHIFT (0U) 842 #define MIPI_DSI_PHY_MISC_PARA_PHYERR_MASK_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_MISC_PARA_PHYERR_MASK_SHIFT) & MIPI_DSI_PHY_MISC_PARA_PHYERR_MASK_MASK) 843 #define MIPI_DSI_PHY_MISC_PARA_PHYERR_MASK_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_MISC_PARA_PHYERR_MASK_MASK) >> MIPI_DSI_PHY_MISC_PARA_PHYERR_MASK_SHIFT) 844 845 /* Bitfield definition for register: CLANE_PARA4 */ 846 /* 847 * T_WAKEUP_C (RW) 848 * 849 * the number of byteclk cycles from exiting ultra low power state to enabling the low-power driver 850 */ 851 #define MIPI_DSI_PHY_CLANE_PARA4_T_WAKEUP_C_MASK (0xFFFFFFFFUL) 852 #define MIPI_DSI_PHY_CLANE_PARA4_T_WAKEUP_C_SHIFT (0U) 853 #define MIPI_DSI_PHY_CLANE_PARA4_T_WAKEUP_C_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_PARA4_T_WAKEUP_C_SHIFT) & MIPI_DSI_PHY_CLANE_PARA4_T_WAKEUP_C_MASK) 854 #define MIPI_DSI_PHY_CLANE_PARA4_T_WAKEUP_C_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_PARA4_T_WAKEUP_C_MASK) >> MIPI_DSI_PHY_CLANE_PARA4_T_WAKEUP_C_SHIFT) 855 856 /* Bitfield definition for register: INTERFACE_PARA */ 857 /* 858 * TXREADYESC_EXTEND_VLD (RW) 859 * 860 * the extend length of txreadyesc 861 */ 862 #define MIPI_DSI_PHY_INTERFACE_PARA_TXREADYESC_EXTEND_VLD_MASK (0xFF00U) 863 #define MIPI_DSI_PHY_INTERFACE_PARA_TXREADYESC_EXTEND_VLD_SHIFT (8U) 864 #define MIPI_DSI_PHY_INTERFACE_PARA_TXREADYESC_EXTEND_VLD_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_INTERFACE_PARA_TXREADYESC_EXTEND_VLD_SHIFT) & MIPI_DSI_PHY_INTERFACE_PARA_TXREADYESC_EXTEND_VLD_MASK) 865 #define MIPI_DSI_PHY_INTERFACE_PARA_TXREADYESC_EXTEND_VLD_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_INTERFACE_PARA_TXREADYESC_EXTEND_VLD_MASK) >> MIPI_DSI_PHY_INTERFACE_PARA_TXREADYESC_EXTEND_VLD_SHIFT) 866 867 /* 868 * RXVALIDESC_EXTEND_VLD (RW) 869 * 870 * the extend length of rxvalidesc 871 */ 872 #define MIPI_DSI_PHY_INTERFACE_PARA_RXVALIDESC_EXTEND_VLD_MASK (0xFFU) 873 #define MIPI_DSI_PHY_INTERFACE_PARA_RXVALIDESC_EXTEND_VLD_SHIFT (0U) 874 #define MIPI_DSI_PHY_INTERFACE_PARA_RXVALIDESC_EXTEND_VLD_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_INTERFACE_PARA_RXVALIDESC_EXTEND_VLD_SHIFT) & MIPI_DSI_PHY_INTERFACE_PARA_RXVALIDESC_EXTEND_VLD_MASK) 875 #define MIPI_DSI_PHY_INTERFACE_PARA_RXVALIDESC_EXTEND_VLD_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_INTERFACE_PARA_RXVALIDESC_EXTEND_VLD_MASK) >> MIPI_DSI_PHY_INTERFACE_PARA_RXVALIDESC_EXTEND_VLD_SHIFT) 876 877 /* Bitfield definition for register: PCS_RESERVED_PIN_PARA */ 878 /* 879 * CLK_TXHS_SEL_INNER (RW) 880 * 881 * select the clock source of clk_txhs in pcs 882 */ 883 #define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_CLK_TXHS_SEL_INNER_MASK (0x10U) 884 #define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_CLK_TXHS_SEL_INNER_SHIFT (4U) 885 #define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_CLK_TXHS_SEL_INNER_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_CLK_TXHS_SEL_INNER_SHIFT) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_CLK_TXHS_SEL_INNER_MASK) 886 #define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_CLK_TXHS_SEL_INNER_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_CLK_TXHS_SEL_INNER_MASK) >> MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_CLK_TXHS_SEL_INNER_SHIFT) 887 888 /* 889 * INV_CLK_TXHS (RW) 890 * 891 * clk_txhs inverter signal 892 */ 893 #define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXHS_MASK (0x8U) 894 #define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXHS_SHIFT (3U) 895 #define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXHS_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXHS_SHIFT) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXHS_MASK) 896 #define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXHS_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXHS_MASK) >> MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXHS_SHIFT) 897 898 /* 899 * INV_CLK_TXESC (RW) 900 * 901 * clk_txesc inverter signal 902 */ 903 #define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXESC_MASK (0x4U) 904 #define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXESC_SHIFT (2U) 905 #define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXESC_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXESC_SHIFT) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXESC_MASK) 906 #define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXESC_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXESC_MASK) >> MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXESC_SHIFT) 907 908 /* 909 * INV_PCLK (RW) 910 * 911 * pclk inverter signal 912 */ 913 #define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_PCLK_MASK (0x2U) 914 #define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_PCLK_SHIFT (1U) 915 #define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_PCLK_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_PCLK_SHIFT) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_PCLK_MASK) 916 #define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_PCLK_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_PCLK_MASK) >> MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_PCLK_SHIFT) 917 918 /* 919 * INV_DSI_RCLK (RW) 920 * 921 * pma clock dsi_rclk_i inverter signal 922 */ 923 #define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_DSI_RCLK_MASK (0x1U) 924 #define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_DSI_RCLK_SHIFT (0U) 925 #define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_DSI_RCLK_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_DSI_RCLK_SHIFT) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_DSI_RCLK_MASK) 926 #define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_DSI_RCLK_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_DSI_RCLK_MASK) >> MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_DSI_RCLK_SHIFT) 927 928 /* Bitfield definition for register: CLANE_DATA_PARA */ 929 /* 930 * CLANE_DATA_SEL (RW) 931 * 932 * select the data about clock lane 933 */ 934 #define MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SEL_MASK (0x100U) 935 #define MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SEL_SHIFT (8U) 936 #define MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SEL_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SEL_SHIFT) & MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SEL_MASK) 937 #define MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SEL_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SEL_MASK) >> MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SEL_SHIFT) 938 939 /* 940 * CLANE_DATA (RW) 941 * 942 * the parallel data about clock lane 943 */ 944 #define MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_MASK (0xFFU) 945 #define MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SHIFT (0U) 946 #define MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SHIFT) & MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_MASK) 947 #define MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_MASK) >> MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SHIFT) 948 949 /* Bitfield definition for register: PMA_LANE_SEL_PARA */ 950 /* 951 * PMA_DLANE4_SEL (RW) 952 * 953 * select the channel 4 as the data lane 954 */ 955 #define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE4_SEL_MASK (0x8U) 956 #define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE4_SEL_SHIFT (3U) 957 #define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE4_SEL_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE4_SEL_SHIFT) & MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE4_SEL_MASK) 958 #define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE4_SEL_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE4_SEL_MASK) >> MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE4_SEL_SHIFT) 959 960 /* 961 * PMA_DLANE3_SEL (RW) 962 * 963 * select the channel 3 as the data lane 964 */ 965 #define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE3_SEL_MASK (0x4U) 966 #define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE3_SEL_SHIFT (2U) 967 #define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE3_SEL_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE3_SEL_SHIFT) & MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE3_SEL_MASK) 968 #define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE3_SEL_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE3_SEL_MASK) >> MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE3_SEL_SHIFT) 969 970 /* 971 * PMA_DLANE2_SEL (RW) 972 * 973 * select the channel 2 as the data lane 974 */ 975 #define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE2_SEL_MASK (0x2U) 976 #define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE2_SEL_SHIFT (1U) 977 #define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE2_SEL_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE2_SEL_SHIFT) & MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE2_SEL_MASK) 978 #define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE2_SEL_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE2_SEL_MASK) >> MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE2_SEL_SHIFT) 979 980 /* 981 * PMA_DLANE1_SEL (RW) 982 * 983 * select the channel 1 as the data lane 984 */ 985 #define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE1_SEL_MASK (0x1U) 986 #define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE1_SEL_SHIFT (0U) 987 #define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE1_SEL_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE1_SEL_SHIFT) & MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE1_SEL_MASK) 988 #define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE1_SEL_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE1_SEL_MASK) >> MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE1_SEL_SHIFT) 989 990 991 992 993 #endif /* HPM_MIPI_DSI_PHY_H */ 994