1 /* 2 // Copyright (C) 2022 Beken Corporation 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 #ifndef __PMU_H__ 16 #define __PMU_H__ 17 18 #define PMU_BASE (0x00800200) 19 20 #define SCTRL_LOW_PWR_CLK (PMU_BASE + 0 * 4) 21 #define LPO_CLK_MUX_POSI (0) 22 #define LPO_CLK_MUX_MASK (0x3) 23 #define LPO_SRC_ROSC (0x0) 24 #define LPO_SRC_32K_XTAL (0x1) 25 #define LPO_SRC_32K_DIV (0x2) 26 27 #define SCTRL_SLEEP (PMU_BASE + 1 * 4) 28 #define PROCORE_DLY_POSI (20) 29 #define PROCORE_DLY_MASK (0xF) 30 #define DCO_PWD_SLEEP_BIT (1 << 18) 31 #define FLASH_PWD_SLEEP_BIT (1 << 17) 32 #define ROSC_PWD_DEEPSLEEP_BIT (1 << 16) 33 #define SLEEP_MODE_POSI (0) 34 #define SLEEP_MODE_MASK (0xFFFF) 35 #define SLEEP_MODE_CFG_NORMAL_VOL_WORD (0x4F89) 36 #define SLEEP_MODE_CFG_LOW_VOL_WORD (0xB706) 37 #define SLEEP_MODE_CFG_DEEP_WORD (0xADC1) 38 39 #define SCTRL_DIGTAL_VDD (PMU_BASE + 2 * 4) 40 #define DIG_VDD_ACTIVE_POSI (4) 41 #define DIG_VDD_ACTIVE_MASK (0x7) 42 #define DIG_VDD_SLEEP_POSI (0) 43 #define DIG_VDD_SLEEP_MASK (0x7) 44 #define VDD_1_DOT_51 (0x7) 45 #define VDD_1_DOT_38 (0x6) 46 #define VDD_1_DOT_25 (0x5) 47 #define VDD_1_DOT_12 (0x4) 48 #define VDD_0_DOT_99 (0x3) 49 #define VDD_0_DOT_86 (0x2) 50 #define VDD_0_DOT_73 (0x1) 51 #define VDD_0_DOT_60 (0x0) 52 53 #define SCTRL_PWR_MAC_MODEM (PMU_BASE + 3 * 4) 54 #define MODEM_PWD_POSI (0) 55 #define MODEM_PWD_MASK (0xFFFFU) 56 #define MODEM_PWD (0xD802U) 57 #define MODEM_PWU (0x0000U) 58 59 #define SCTRL_DSP_PWR (PMU_BASE + 4 * 4) 60 #define DSP_PWD_POSI (0) 61 #define DSP_PWD_MASK (0xFFFF) 62 #define DSP_PWD (0xD410) 63 #define DSP_PWU (0x0000) 64 65 #define ICU_TL410_CLK_PWD SCTRL_DSP_PWR //need_confirm 66 #define TL410_CLK_PWD_VALUE (0xD410) 67 68 #define SCTRL_BT_PWR (PMU_BASE + 5 * 4) 69 #define BT_PWD_POSI (0) 70 #define BT_PWD_MASK (0xFFFF) 71 #define BT_PWD (0xDB1E) 72 #define BT_PWU (0x0000) 73 74 #define SCTRL_BLOCK_EN_CFG (PMU_BASE + 9 * 4) 75 #define BLOCK_EN_WORD_POSI (20) 76 #define BLOCK_EN_WORD_MASK (0xFFFUL) 77 #define BLOCK_EN_WORD_PWD (0xA5CUL) 78 79 #define BLOCK_EN_VALID_MASK (0xFFFFF) 80 #define BLK_BIT_MIC_QSPI_RAM_OR_FLASH (1 << 19) 81 #define BLK_BIT_LCD (1 << 18) 82 #define BLK_BIT_AUDIO_PLL (1 << 17) 83 #define BLK_BIT_AUDIO_RANDOM_GENERATOR (1 << 16) 84 #define BLK_BIT_USB2 (1 << 15) 85 #define BLK_BIT_USB (1 << 14) 86 #define BLK_BIT_SARADC (1 << 13) 87 #define BLK_BIT_TEMPRATURE_SENSOR (1 << 12) 88 #define BLK_BIT_26M_XTAL_LOW_POWER (1 << 11) 89 #define BLK_BIT_XTAL2RF (1 << 10) 90 #define BLK_BIT_IO_LDO_LOW_POWER (1 << 09) 91 #define BLK_BIT_ANALOG_SYS_LDO (1 << 08) 92 #define BLK_BIT_DIGITAL_CORE_LDO_LOW_POWER (1 << 07) 93 #define BLK_BIT_DIGITAL_CORE (1 << 06) 94 #define BLK_BIT_DPLL_480M (1 << 05) 95 #define BLK_BIT_32K_XTAL (1 << 04) 96 #define BLK_BIT_26M_XTAL (1 << 03) 97 #define BLK_BIT_ROSC32K (1 << 02) 98 #define BLK_BIT_DCO (1 << 01) 99 #define BLK_BIT_FLASH (1 << 00) 100 101 #define SCTRL_PMU_STATUS (PMU_BASE + 6 * 4) 102 #define SYNC_BUS_PWD_POSI (0) 103 #define SYNC_BUS_PWD_MASK (0xFFFF) 104 #define SYNC_BUS_PWD (0xD884) 105 #define SYNC_BUS_PWU (0x0000) 106 107 #define SCTRL_BLOCK_EN_MUX (PMU_BASE + 11 * 4) 108 109 #define PMU_RTC_WKU (PMU_BASE + 15 * 4) 110 111 #define PMU_CO_MCU_CONFIG (PMU_BASE + 0x13 * 4) 112 #define BT_CLK_ENABLE (1 << 05) 113 #define DSP_CLK_ENABLE (1 << 04) 114 #define BT_SW_RESET_ENABLE (1 << 03) 115 #define DSP_SW_RESET_ENABLE (1 << 02) 116 #define BT_PROGRAM_DOWNLOAD_EN (1 << 01) 117 #define DSP_PROGRAM_DOWNLOAD_EN (1 << 00) 118 119 #define PMU_STATUS (PMU_BASE + 18 * 4) 120 #define PMU_BAIS_CAL_OUT_POSI (12) 121 #define PMU_BAIS_CAL_OUT_MASK (0x1F) 122 #endif 123 // eof 124 125 126