1 /* 2 * Copyright (c) 2021 Bestechnic (Shanghai) Co., Ltd. All rights reserved. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 #ifndef __REG_PSC_BEST2003_H__ 16 #define __REG_PSC_BEST2003_H__ 17 18 #include "plat_types.h" 19 20 struct AONPSC_T { 21 __IO uint32_t REG_000; 22 __IO uint32_t REG_004; 23 __IO uint32_t REG_008; 24 __IO uint32_t REG_00C; 25 __IO uint32_t REG_010; 26 __IO uint32_t REG_014; 27 __IO uint32_t REG_018; 28 __IO uint32_t REG_01C; 29 __IO uint32_t REG_020; 30 __IO uint32_t REG_024; 31 __IO uint32_t REG_028; 32 __IO uint32_t REG_02C; 33 __IO uint32_t REG_030; 34 __IO uint32_t REG_034; 35 __IO uint32_t REG_038; 36 __IO uint32_t REG_03C; 37 __IO uint32_t REG_040; 38 __IO uint32_t REG_044; 39 __IO uint32_t REG_048; 40 __IO uint32_t REG_04C; 41 __IO uint32_t REG_050; 42 __IO uint32_t REG_054; 43 __IO uint32_t REG_058; 44 __IO uint32_t REG_05C; 45 __IO uint32_t REG_060; 46 __IO uint32_t REG_064; 47 __IO uint32_t REG_068; 48 __IO uint32_t REG_06C; 49 __IO uint32_t REG_070; 50 __IO uint32_t REG_074; 51 __IO uint32_t REG_078; 52 __IO uint32_t REG_07C; 53 __IO uint32_t REG_080; 54 __IO uint32_t REG_084; 55 __IO uint32_t REG_088; 56 __IO uint32_t REG_08C; 57 __IO uint32_t REG_090; 58 __IO uint32_t REG_094; 59 __IO uint32_t REG_098; 60 __IO uint32_t REG_09C; 61 __IO uint32_t REG_0A0; 62 __IO uint32_t REG_0A4; 63 __IO uint32_t REG_0A8; 64 __IO uint32_t REG_0AC; 65 __IO uint32_t REG_0B0; 66 __IO uint32_t REG_0B4; 67 __IO uint32_t REG_0B8; 68 __IO uint32_t REG_0BC; 69 __IO uint32_t REG_0C0; 70 __IO uint32_t REG_0C4; 71 __IO uint32_t REG_0C8; 72 __IO uint32_t REG_0CC; 73 __IO uint32_t REG_0D0; 74 __IO uint32_t REG_0D4; 75 __IO uint32_t REG_0D8; 76 __IO uint32_t REG_0DC; 77 __IO uint32_t REG_0E0; 78 __IO uint32_t REG_0E4; 79 __IO uint32_t REG_0E8; 80 __IO uint32_t REG_0EC; 81 __IO uint32_t REG_0F0; 82 __IO uint32_t REG_0F4; 83 __IO uint32_t REG_0F8; 84 __IO uint32_t REG_0FC; 85 __IO uint32_t REG_100; 86 __IO uint32_t REG_104; 87 __IO uint32_t REG_108; 88 __IO uint32_t REG_10C; 89 __IO uint32_t REG_110; 90 __IO uint32_t REG_114; 91 __IO uint32_t REG_118; 92 __IO uint32_t REG_11C; 93 __IO uint32_t REG_120; 94 __IO uint32_t REG_124; 95 __IO uint32_t REG_128; 96 __IO uint32_t REG_12C; 97 __IO uint32_t REG_130; 98 __IO uint32_t REG_134; 99 __IO uint32_t REG_138; 100 __IO uint32_t REG_13C; 101 __IO uint32_t REG_140; 102 __IO uint32_t REG_144; 103 }; 104 105 // reg_000 106 #define PSC_AON_MCU_PG_AUTO_EN (1 << 0) 107 #define PSC_AON_MCU_PG_HW_EN (1 << 1) 108 109 // reg_004 110 #define PSC_AON_MCU_PSW_ACK_VALID (1 << 0) 111 #define PSC_AON_MCU_RESERVED(n) (((n) & 0x7F) << 1) 112 #define PSC_AON_MCU_RESERVED_MASK (0x7F << 1) 113 #define PSC_AON_MCU_RESERVED_SHIFT (1) 114 #define PSC_AON_MCU_MAIN_STATE(n) (((n) & 0x3) << 8) 115 #define PSC_AON_MCU_MAIN_STATE_MASK (0x3 << 8) 116 #define PSC_AON_MCU_MAIN_STATE_SHIFT (8) 117 #define PSC_AON_MCU_POWERDN_STATE(n) (((n) & 0x7) << 10) 118 #define PSC_AON_MCU_POWERDN_STATE_MASK (0x7 << 10) 119 #define PSC_AON_MCU_POWERDN_STATE_SHIFT (10) 120 #define PSC_AON_MCU_POWERUP_STATE(n) (((n) & 0x7) << 13) 121 #define PSC_AON_MCU_POWERUP_STATE_MASK (0x7 << 13) 122 #define PSC_AON_MCU_POWERUP_STATE_SHIFT (13) 123 124 // reg_008 125 #define PSC_AON_MCU_POWERDN_TIMER1(n) (((n) & 0x3F) << 0) 126 #define PSC_AON_MCU_POWERDN_TIMER1_MASK (0x3F << 0) 127 #define PSC_AON_MCU_POWERDN_TIMER1_SHIFT (0) 128 #define PSC_AON_MCU_POWERDN_TIMER2(n) (((n) & 0x3F) << 6) 129 #define PSC_AON_MCU_POWERDN_TIMER2_MASK (0x3F << 6) 130 #define PSC_AON_MCU_POWERDN_TIMER2_SHIFT (6) 131 #define PSC_AON_MCU_POWERDN_TIMER3(n) (((n) & 0x3F) << 12) 132 #define PSC_AON_MCU_POWERDN_TIMER3_MASK (0x3F << 12) 133 #define PSC_AON_MCU_POWERDN_TIMER3_SHIFT (12) 134 #define PSC_AON_MCU_POWERDN_TIMER4(n) (((n) & 0x3F) << 18) 135 #define PSC_AON_MCU_POWERDN_TIMER4_MASK (0x3F << 18) 136 #define PSC_AON_MCU_POWERDN_TIMER4_SHIFT (18) 137 #define PSC_AON_MCU_POWERDN_TIMER5(n) (((n) & 0xFF) << 24) 138 #define PSC_AON_MCU_POWERDN_TIMER5_MASK (0xFF << 24) 139 #define PSC_AON_MCU_POWERDN_TIMER5_SHIFT (24) 140 141 // reg_00c 142 #define PSC_AON_MCU_POWERUP_TIMER1(n) (((n) & 0x3F) << 0) 143 #define PSC_AON_MCU_POWERUP_TIMER1_MASK (0x3F << 0) 144 #define PSC_AON_MCU_POWERUP_TIMER1_SHIFT (0) 145 #define PSC_AON_MCU_POWERUP_TIMER2(n) (((n) & 0xFF) << 6) 146 #define PSC_AON_MCU_POWERUP_TIMER2_MASK (0xFF << 6) 147 #define PSC_AON_MCU_POWERUP_TIMER2_SHIFT (6) 148 #define PSC_AON_MCU_POWERUP_TIMER3(n) (((n) & 0x3F) << 14) 149 #define PSC_AON_MCU_POWERUP_TIMER3_MASK (0x3F << 14) 150 #define PSC_AON_MCU_POWERUP_TIMER3_SHIFT (14) 151 #define PSC_AON_MCU_POWERUP_TIMER4(n) (((n) & 0x3F) << 20) 152 #define PSC_AON_MCU_POWERUP_TIMER4_MASK (0x3F << 20) 153 #define PSC_AON_MCU_POWERUP_TIMER4_SHIFT (20) 154 #define PSC_AON_MCU_POWERUP_TIMER5(n) (((n) & 0x3F) << 26) 155 #define PSC_AON_MCU_POWERUP_TIMER5_MASK (0x3F << 26) 156 #define PSC_AON_MCU_POWERUP_TIMER5_SHIFT (26) 157 158 // reg_010 159 #define PSC_AON_MCU_POWERDN_START (1 << 0) 160 161 // reg_014 162 #define PSC_AON_MCU_POWERUP_START (1 << 0) 163 164 // reg_018 165 #define PSC_AON_MCU_CLK_STOP_REG (1 << 0) 166 #define PSC_AON_MCU_ISO_EN_REG (1 << 1) 167 #define PSC_AON_MCU_RESETN_ASSERT_REG (1 << 2) 168 #define PSC_AON_MCU_PSW_EN_REG (1 << 3) 169 #define PSC_AON_MCU_CLK_STOP_DR (1 << 4) 170 #define PSC_AON_MCU_ISO_EN_DR (1 << 5) 171 #define PSC_AON_MCU_RESETN_ASSERT_DR (1 << 6) 172 #define PSC_AON_MCU_PSW_EN_DR (1 << 7) 173 174 #if 0 175 // reg_01c 176 #define PSC_AON_MCU_MAIN_STATE(n) (((n) & 0x3) << 0) 177 #define PSC_AON_MCU_MAIN_STATE_MASK (0x3 << 0) 178 #define PSC_AON_MCU_MAIN_STATE_SHIFT (0) 179 #define PSC_AON_MCU_POWERDN_STATE(n) (((n) & 0x7) << 2) 180 #define PSC_AON_MCU_POWERDN_STATE_MASK (0x7 << 2) 181 #define PSC_AON_MCU_POWERDN_STATE_SHIFT (2) 182 #define PSC_AON_MCU_POWERUP_STATE(n) (((n) & 0x7) << 5) 183 #define PSC_AON_MCU_POWERUP_STATE_MASK (0x7 << 5) 184 #define PSC_AON_MCU_POWERUP_STATE_SHIFT (5) 185 #define PSC_AON_BT_MAIN_STATE(n) (((n) & 0x3) << 8) 186 #define PSC_AON_BT_MAIN_STATE_MASK (0x3 << 8) 187 #define PSC_AON_BT_MAIN_STATE_SHIFT (8) 188 #define PSC_AON_BT_POWERDN_STATE(n) (((n) & 0x7) << 10) 189 #define PSC_AON_BT_POWERDN_STATE_MASK (0x7 << 10) 190 #define PSC_AON_BT_POWERDN_STATE_SHIFT (10) 191 #define PSC_AON_BT_POWERUP_STATE(n) (((n) & 0x7) << 13) 192 #define PSC_AON_BT_POWERUP_STATE_MASK (0x7 << 13) 193 #define PSC_AON_BT_POWERUP_STATE_SHIFT (13) 194 #define PSC_AON_WLAN_MAIN_STATE(n) (((n) & 0x3) << 16) 195 #define PSC_AON_WLAN_MAIN_STATE_MASK (0x3 << 16) 196 #define PSC_AON_WLAN_MAIN_STATE_SHIFT (16) 197 #define PSC_AON_WLAN_POWERDN_STATE(n) (((n) & 0x7) << 18) 198 #define PSC_AON_WLAN_POWERDN_STATE_MASK (0x7 << 18) 199 #define PSC_AON_WLAN_POWERDN_STATE_SHIFT (18) 200 #define PSC_AON_WLAN_POWERUP_STATE(n) (((n) & 0x7) << 21) 201 #define PSC_AON_WLAN_POWERUP_STATE_MASK (0x7 << 21) 202 #define PSC_AON_WLAN_POWERUP_STATE_SHIFT (21) 203 #define PSC_AON_CODEC_MAIN_STATE(n) (((n) & 0x3) << 24) 204 #define PSC_AON_CODEC_MAIN_STATE_MASK (0x3 << 24) 205 #define PSC_AON_CODEC_MAIN_STATE_SHIFT (24) 206 #define PSC_AON_CODEC_POWERDN_STATE(n) (((n) & 0x7) << 26) 207 #define PSC_AON_CODEC_POWERDN_STATE_MASK (0x7 << 26) 208 #define PSC_AON_CODEC_POWERDN_STATE_SHIFT (26) 209 #define PSC_AON_CODEC_POWERUP_STATE(n) (((n) & 0x7) << 29) 210 #define PSC_AON_CODEC_POWERUP_STATE_MASK (0x7 << 29) 211 #define PSC_AON_CODEC_POWERUP_STATE_SHIFT (29) 212 #endif 213 214 // reg_020 215 #define PSC_AON_BT_PG_AUTO_EN (1 << 0) 216 #define PSC_AON_BT_PG_HW_EN (1 << 1) 217 218 // reg_024 219 #define PSC_AON_BT_PSW_ACK_VALID (1 << 0) 220 #define PSC_AON_BT_RESERVED(n) (((n) & 0x7F) << 1) 221 #define PSC_AON_BT_RESERVED_MASK (0x7F << 1) 222 #define PSC_AON_BT_RESERVED_SHIFT (1) 223 #define PSC_AON_BT_MAIN_STATE(n) (((n) & 0x3) << 8) 224 #define PSC_AON_BT_MAIN_STATE_MASK (0x3 << 8) 225 #define PSC_AON_BT_MAIN_STATE_SHIFT (8) 226 #define PSC_AON_BT_POWERDN_STATE(n) (((n) & 0x7) << 10) 227 #define PSC_AON_BT_POWERDN_STATE_MASK (0x7 << 10) 228 #define PSC_AON_BT_POWERDN_STATE_SHIFT (10) 229 #define PSC_AON_BT_POWERUP_STATE(n) (((n) & 0x7) << 13) 230 #define PSC_AON_BT_POWERUP_STATE_MASK (0x7 << 13) 231 #define PSC_AON_BT_POWERUP_STATE_SHIFT (13) 232 233 #define PSC_AON_BT_SLEEP_NO_WFI (1 << 2) 234 235 // reg_028 236 #define PSC_AON_BT_POWERDN_TIMER1(n) (((n) & 0x3F) << 0) 237 #define PSC_AON_BT_POWERDN_TIMER1_MASK (0x3F << 0) 238 #define PSC_AON_BT_POWERDN_TIMER1_SHIFT (0) 239 #define PSC_AON_BT_POWERDN_TIMER2(n) (((n) & 0x3F) << 6) 240 #define PSC_AON_BT_POWERDN_TIMER2_MASK (0x3F << 6) 241 #define PSC_AON_BT_POWERDN_TIMER2_SHIFT (6) 242 #define PSC_AON_BT_POWERDN_TIMER3(n) (((n) & 0x3F) << 12) 243 #define PSC_AON_BT_POWERDN_TIMER3_MASK (0x3F << 12) 244 #define PSC_AON_BT_POWERDN_TIMER3_SHIFT (12) 245 #define PSC_AON_BT_POWERDN_TIMER4(n) (((n) & 0x3F) << 18) 246 #define PSC_AON_BT_POWERDN_TIMER4_MASK (0x3F << 18) 247 #define PSC_AON_BT_POWERDN_TIMER4_SHIFT (18) 248 #define PSC_AON_BT_POWERDN_TIMER5(n) (((n) & 0xFF) << 24) 249 #define PSC_AON_BT_POWERDN_TIMER5_MASK (0xFF << 24) 250 #define PSC_AON_BT_POWERDN_TIMER5_SHIFT (24) 251 252 // reg_02c 253 #define PSC_AON_BT_POWERUP_TIMER1(n) (((n) & 0x3F) << 0) 254 #define PSC_AON_BT_POWERUP_TIMER1_MASK (0x3F << 0) 255 #define PSC_AON_BT_POWERUP_TIMER1_SHIFT (0) 256 #define PSC_AON_BT_POWERUP_TIMER2(n) (((n) & 0xFF) << 6) 257 #define PSC_AON_BT_POWERUP_TIMER2_MASK (0xFF << 6) 258 #define PSC_AON_BT_POWERUP_TIMER2_SHIFT (6) 259 #define PSC_AON_BT_POWERUP_TIMER3(n) (((n) & 0x3F) << 14) 260 #define PSC_AON_BT_POWERUP_TIMER3_MASK (0x3F << 14) 261 #define PSC_AON_BT_POWERUP_TIMER3_SHIFT (14) 262 #define PSC_AON_BT_POWERUP_TIMER4(n) (((n) & 0x3F) << 20) 263 #define PSC_AON_BT_POWERUP_TIMER4_MASK (0x3F << 20) 264 #define PSC_AON_BT_POWERUP_TIMER4_SHIFT (20) 265 #define PSC_AON_BT_POWERUP_TIMER5(n) (((n) & 0x3F) << 26) 266 #define PSC_AON_BT_POWERUP_TIMER5_MASK (0x3F << 26) 267 #define PSC_AON_BT_POWERUP_TIMER5_SHIFT (26) 268 269 // reg_030 270 #define PSC_AON_BT_POWERDN_START (1 << 0) 271 272 // reg_034 273 #define PSC_AON_BT_POWERUP_START (1 << 0) 274 275 // reg_038 276 #define PSC_AON_BT_CLK_STOP_REG (1 << 0) 277 #define PSC_AON_BT_ISO_EN_REG (1 << 1) 278 #define PSC_AON_BT_RESETN_ASSERT_REG (1 << 2) 279 #define PSC_AON_BT_PSW_EN_REG (1 << 3) 280 #define PSC_AON_BT_CLK_STOP_DR (1 << 4) 281 #define PSC_AON_BT_ISO_EN_DR (1 << 5) 282 #define PSC_AON_BT_RESETN_ASSERT_DR (1 << 6) 283 #define PSC_AON_BT_PSW_EN_DR (1 << 7) 284 285 // reg_040 286 #define PSC_AON_WLAN_PG_AUTO_EN (1 << 0) 287 #define PSC_AON_WLAN_PG_HW_EN (1 << 1) 288 289 // reg_044 290 #define PSC_AON_WLAN_PSW_ACK_VALID (1 << 0) 291 #define PSC_AON_WLAN_RESERVED(n) (((n) & 0x7F) << 1) 292 #define PSC_AON_WLAN_RESERVED_MASK (0x7F << 1) 293 #define PSC_AON_WLAN_RESERVED_SHIFT (1) 294 #define PSC_AON_WLAN_MAIN_STATE(n) (((n) & 0x3) << 8) 295 #define PSC_AON_WLAN_MAIN_STATE_MASK (0x3 << 8) 296 #define PSC_AON_WLAN_MAIN_STATE_SHIFT (8) 297 #define PSC_AON_WLAN_POWERDN_STATE(n) (((n) & 0x7) << 10) 298 #define PSC_AON_WLAN_POWERDN_STATE_MASK (0x7 << 10) 299 #define PSC_AON_WLAN_POWERDN_STATE_SHIFT (10) 300 #define PSC_AON_WLAN_POWERUP_STATE(n) (((n) & 0x7) << 13) 301 #define PSC_AON_WLAN_POWERUP_STATE_MASK (0x7 << 13) 302 #define PSC_AON_WLAN_POWERUP_STATE_SHIFT (13) 303 304 // reg_048 305 #define PSC_AON_WLAN_POWERDN_TIMER1(n) (((n) & 0x3F) << 0) 306 #define PSC_AON_WLAN_POWERDN_TIMER1_MASK (0x3F << 0) 307 #define PSC_AON_WLAN_POWERDN_TIMER1_SHIFT (0) 308 #define PSC_AON_WLAN_POWERDN_TIMER2(n) (((n) & 0x3F) << 6) 309 #define PSC_AON_WLAN_POWERDN_TIMER2_MASK (0x3F << 6) 310 #define PSC_AON_WLAN_POWERDN_TIMER2_SHIFT (6) 311 #define PSC_AON_WLAN_POWERDN_TIMER3(n) (((n) & 0x3F) << 12) 312 #define PSC_AON_WLAN_POWERDN_TIMER3_MASK (0x3F << 12) 313 #define PSC_AON_WLAN_POWERDN_TIMER3_SHIFT (12) 314 #define PSC_AON_WLAN_POWERDN_TIMER4(n) (((n) & 0x3F) << 18) 315 #define PSC_AON_WLAN_POWERDN_TIMER4_MASK (0x3F << 18) 316 #define PSC_AON_WLAN_POWERDN_TIMER4_SHIFT (18) 317 #define PSC_AON_WLAN_POWERDN_TIMER5(n) (((n) & 0xFF) << 24) 318 #define PSC_AON_WLAN_POWERDN_TIMER5_MASK (0xFF << 24) 319 #define PSC_AON_WLAN_POWERDN_TIMER5_SHIFT (24) 320 321 // reg_04c 322 #define PSC_AON_WLAN_POWERUP_TIMER1(n) (((n) & 0x3F) << 0) 323 #define PSC_AON_WLAN_POWERUP_TIMER1_MASK (0x3F << 0) 324 #define PSC_AON_WLAN_POWERUP_TIMER1_SHIFT (0) 325 #define PSC_AON_WLAN_POWERUP_TIMER2(n) (((n) & 0xFF) << 6) 326 #define PSC_AON_WLAN_POWERUP_TIMER2_MASK (0xFF << 6) 327 #define PSC_AON_WLAN_POWERUP_TIMER2_SHIFT (6) 328 #define PSC_AON_WLAN_POWERUP_TIMER3(n) (((n) & 0x3F) << 14) 329 #define PSC_AON_WLAN_POWERUP_TIMER3_MASK (0x3F << 14) 330 #define PSC_AON_WLAN_POWERUP_TIMER3_SHIFT (14) 331 #define PSC_AON_WLAN_POWERUP_TIMER4(n) (((n) & 0x3F) << 20) 332 #define PSC_AON_WLAN_POWERUP_TIMER4_MASK (0x3F << 20) 333 #define PSC_AON_WLAN_POWERUP_TIMER4_SHIFT (20) 334 #define PSC_AON_WLAN_POWERUP_TIMER5(n) (((n) & 0x3F) << 26) 335 #define PSC_AON_WLAN_POWERUP_TIMER5_MASK (0x3F << 26) 336 #define PSC_AON_WLAN_POWERUP_TIMER5_SHIFT (26) 337 338 // reg_050 339 #define PSC_AON_WLAN_POWERDN_START (1 << 0) 340 341 // reg_054 342 #define PSC_AON_WLAN_POWERUP_START (1 << 0) 343 344 // reg_058 345 #define PSC_AON_WLAN_CLK_STOP_REG (1 << 0) 346 #define PSC_AON_WLAN_ISO_EN_REG (1 << 1) 347 #define PSC_AON_WLAN_RESETN_ASSERT_REG (1 << 2) 348 #define PSC_AON_WLAN_PSW_EN_REG (1 << 3) 349 #define PSC_AON_WLAN_CLK_STOP_DR (1 << 4) 350 #define PSC_AON_WLAN_ISO_EN_DR (1 << 5) 351 #define PSC_AON_WLAN_RESETN_ASSERT_DR (1 << 6) 352 #define PSC_AON_WLAN_PSW_EN_DR (1 << 7) 353 354 // reg_060 355 #define PSC_AON_CODEC_PG_AUTO_EN (1 << 0) 356 357 // reg_064 358 #define PSC_AON_CODEC_PSW_ACK_VALID (1 << 0) 359 #define PSC_AON_CODEC_RESERVED(n) (((n) & 0x7F) << 1) 360 #define PSC_AON_CODEC_RESERVED_MASK (0x7F << 1) 361 #define PSC_AON_CODEC_RESERVED_SHIFT (1) 362 #define PSC_AON_CODEC_MAIN_STATE(n) (((n) & 0x3) << 8) 363 #define PSC_AON_CODEC_MAIN_STATE_MASK (0x3 << 8) 364 #define PSC_AON_CODEC_MAIN_STATE_SHIFT (8) 365 #define PSC_AON_CODEC_POWERDN_STATE(n) (((n) & 0x7) << 10) 366 #define PSC_AON_CODEC_POWERDN_STATE_MASK (0x7 << 10) 367 #define PSC_AON_CODEC_POWERDN_STATE_SHIFT (10) 368 #define PSC_AON_CODEC_POWERUP_STATE(n) (((n) & 0x7) << 13) 369 #define PSC_AON_CODEC_POWERUP_STATE_MASK (0x7 << 13) 370 #define PSC_AON_CODEC_POWERUP_STATE_SHIFT (13) 371 372 // reg_068 373 #define PSC_AON_CODEC_POWERDN_TIMER1(n) (((n) & 0x3F) << 0) 374 #define PSC_AON_CODEC_POWERDN_TIMER1_MASK (0x3F << 0) 375 #define PSC_AON_CODEC_POWERDN_TIMER1_SHIFT (0) 376 #define PSC_AON_CODEC_POWERDN_TIMER2(n) (((n) & 0x3F) << 6) 377 #define PSC_AON_CODEC_POWERDN_TIMER2_MASK (0x3F << 6) 378 #define PSC_AON_CODEC_POWERDN_TIMER2_SHIFT (6) 379 #define PSC_AON_CODEC_POWERDN_TIMER3(n) (((n) & 0x3F) << 12) 380 #define PSC_AON_CODEC_POWERDN_TIMER3_MASK (0x3F << 12) 381 #define PSC_AON_CODEC_POWERDN_TIMER3_SHIFT (12) 382 #define PSC_AON_CODEC_POWERDN_TIMER4(n) (((n) & 0x3F) << 18) 383 #define PSC_AON_CODEC_POWERDN_TIMER4_MASK (0x3F << 18) 384 #define PSC_AON_CODEC_POWERDN_TIMER4_SHIFT (18) 385 #define PSC_AON_CODEC_POWERDN_TIMER5(n) (((n) & 0xFF) << 24) 386 #define PSC_AON_CODEC_POWERDN_TIMER5_MASK (0xFF << 24) 387 #define PSC_AON_CODEC_POWERDN_TIMER5_SHIFT (24) 388 389 // reg_06c 390 #define PSC_AON_CODEC_POWERUP_TIMER1(n) (((n) & 0x3F) << 0) 391 #define PSC_AON_CODEC_POWERUP_TIMER1_MASK (0x3F << 0) 392 #define PSC_AON_CODEC_POWERUP_TIMER1_SHIFT (0) 393 #define PSC_AON_CODEC_POWERUP_TIMER2(n) (((n) & 0xFF) << 6) 394 #define PSC_AON_CODEC_POWERUP_TIMER2_MASK (0xFF << 6) 395 #define PSC_AON_CODEC_POWERUP_TIMER2_SHIFT (6) 396 #define PSC_AON_CODEC_POWERUP_TIMER3(n) (((n) & 0x3F) << 14) 397 #define PSC_AON_CODEC_POWERUP_TIMER3_MASK (0x3F << 14) 398 #define PSC_AON_CODEC_POWERUP_TIMER3_SHIFT (14) 399 #define PSC_AON_CODEC_POWERUP_TIMER4(n) (((n) & 0x3F) << 20) 400 #define PSC_AON_CODEC_POWERUP_TIMER4_MASK (0x3F << 20) 401 #define PSC_AON_CODEC_POWERUP_TIMER4_SHIFT (20) 402 #define PSC_AON_CODEC_POWERUP_TIMER5(n) (((n) & 0x3F) << 26) 403 #define PSC_AON_CODEC_POWERUP_TIMER5_MASK (0x3F << 26) 404 #define PSC_AON_CODEC_POWERUP_TIMER5_SHIFT (26) 405 406 // reg_070 407 #define PSC_AON_CODEC_POWERDN_START (1 << 0) 408 409 // reg_074 410 #define PSC_AON_CODEC_POWERUP_START (1 << 0) 411 412 // reg_078 413 #define PSC_AON_CODEC_CLK_STOP_REG (1 << 0) 414 #define PSC_AON_CODEC_ISO_EN_REG (1 << 1) 415 #define PSC_AON_CODEC_RESETN_ASSERT_REG (1 << 2) 416 #define PSC_AON_CODEC_PSW_EN_REG (1 << 3) 417 #define PSC_AON_CODEC_CLK_STOP_DR (1 << 4) 418 #define PSC_AON_CODEC_ISO_EN_DR (1 << 5) 419 #define PSC_AON_CODEC_RESETN_ASSERT_DR (1 << 6) 420 #define PSC_AON_CODEC_PSW_EN_DR (1 << 7) 421 422 // reg_080 423 #define PSC_AON_MCU_INTR_MASK(n) (((n) & 0xFFFFFFFF) << 0) 424 #define PSC_AON_MCU_INTR_MASK_MASK (0xFFFFFFFF << 0) 425 #define PSC_AON_MCU_INTR_MASK_SHIFT (0) 426 427 // reg_084 428 #define PSC_AON_MCU_INTR_MASK2(n) (((n) & 0xFFFF) << 0) 429 #define PSC_AON_MCU_INTR_MASK2_MASK (0xFFFF << 0) 430 #define PSC_AON_MCU_INTR_MASK2_SHIFT (0) 431 432 // reg_088 433 #define PSC_AON_MCU_INTR_MASK_STATUS(n) (((n) & 0xFFFFFFFF) << 0) 434 #define PSC_AON_MCU_INTR_MASK_STATUS_MASK (0xFFFFFFFF << 0) 435 #define PSC_AON_MCU_INTR_MASK_STATUS_SHIFT (0) 436 437 // reg_08c 438 #define PSC_AON_MCU_INTR_MASK_STATUS2(n) (((n) & 0xFFFF) << 0) 439 #define PSC_AON_MCU_INTR_MASK_STATUS2_MASK (0xFFFF << 0) 440 #define PSC_AON_MCU_INTR_MASK_STATUS2_SHIFT (0) 441 442 // reg_090 443 #define PSC_AON_BT_INTR_MASK(n) (((n) & 0xFFFFFFFF) << 0) 444 #define PSC_AON_BT_INTR_MASK_MASK (0xFFFFFFFF << 0) 445 #define PSC_AON_BT_INTR_MASK_SHIFT (0) 446 447 // reg_094 448 #define PSC_AON_BT_INTR_MASK2(n) (((n) & 0xFFFF) << 0) 449 #define PSC_AON_BT_INTR_MASK2_MASK (0xFFFF << 0) 450 #define PSC_AON_BT_INTR_MASK2_SHIFT (0) 451 452 // reg_098 453 #define PSC_AON_BT_INTR_MASK_STATUS(n) (((n) & 0xFFFFFFFF) << 0) 454 #define PSC_AON_BT_INTR_MASK_STATUS_MASK (0xFFFFFFFF << 0) 455 #define PSC_AON_BT_INTR_MASK_STATUS_SHIFT (0) 456 457 // reg_09c 458 #define PSC_AON_BT_INTR_MASK_STATUS2(n) (((n) & 0xFFFF) << 0) 459 #define PSC_AON_BT_INTR_MASK_STATUS2_MASK (0xFFFF << 0) 460 #define PSC_AON_BT_INTR_MASK_STATUS2_SHIFT (0) 461 462 // reg_0a0 463 #define PSC_AON_WLAN_INTR_MASK(n) (((n) & 0xFFFFFFFF) << 0) 464 #define PSC_AON_WLAN_INTR_MASK_MASK (0xFFFFFFFF << 0) 465 #define PSC_AON_WLAN_INTR_MASK_SHIFT (0) 466 467 // reg_0a4 468 #define PSC_AON_WLAN_INTR_MASK2(n) (((n) & 0xFFFF) << 0) 469 #define PSC_AON_WLAN_INTR_MASK2_MASK (0xFFFF << 0) 470 #define PSC_AON_WLAN_INTR_MASK2_SHIFT (0) 471 472 // reg_0a8 473 #define PSC_AON_WLAN_INTR_MASK_STATUS(n) (((n) & 0xFFFFFFFF) << 0) 474 #define PSC_AON_WLAN_INTR_MASK_STATUS_MASK (0xFFFFFFFF << 0) 475 #define PSC_AON_WLAN_INTR_MASK_STATUS_SHIFT (0) 476 477 // reg_0ac 478 #define PSC_AON_WLAN_INTR_MASK_STATUS2(n) (((n) & 0xFFFF) << 0) 479 #define PSC_AON_WLAN_INTR_MASK_STATUS2_MASK (0xFFFF << 0) 480 #define PSC_AON_WLAN_INTR_MASK_STATUS2_SHIFT (0) 481 482 // reg_0b0 483 #define PSC_AON_INTR_RAW_STATUS(n) (((n) & 0xFFFFFFFF) << 0) 484 #define PSC_AON_INTR_RAW_STATUS_MASK (0xFFFFFFFF << 0) 485 #define PSC_AON_INTR_RAW_STATUS_SHIFT (0) 486 487 // reg_0b4 488 #define PSC_AON_INTR_RAW_STATUS2(n) (((n) & 0xFFFF) << 0) 489 #define PSC_AON_INTR_RAW_STATUS2_MASK (0xFFFF << 0) 490 #define PSC_AON_INTR_RAW_STATUS2_SHIFT (0) 491 492 // reg_0c0 493 #define PSC_AON_A7_PG_AUTO_EN (1 << 0) 494 #define PSC_AON_A7_PG_HW_EN (1 << 1) 495 496 // reg_0c4 497 #define PSC_AON_A7_PSW_ACK_VALID (1 << 0) 498 #define PSC_AON_A7_RESERVED(n) (((n) & 0x7F) << 1) 499 #define PSC_AON_A7_RESERVED_MASK (0x7F << 1) 500 #define PSC_AON_A7_RESERVED_SHIFT (1) 501 #define PSC_AON_A7_MAIN_STATE(n) (((n) & 0x3) << 8) 502 #define PSC_AON_A7_MAIN_STATE_MASK (0x3 << 8) 503 #define PSC_AON_A7_MAIN_STATE_SHIFT (8) 504 #define PSC_AON_A7_POWERDN_STATE(n) (((n) & 0x7) << 10) 505 #define PSC_AON_A7_POWERDN_STATE_MASK (0x7 << 10) 506 #define PSC_AON_A7_POWERDN_STATE_SHIFT (10) 507 #define PSC_AON_A7_POWERUP_STATE(n) (((n) & 0x7) << 13) 508 #define PSC_AON_A7_POWERUP_STATE_MASK (0x7 << 13) 509 #define PSC_AON_A7_POWERUP_STATE_SHIFT (13) 510 511 // reg_0c8 512 #define PSC_AON_A7_POWERDN_TIMER1(n) (((n) & 0x3F) << 0) 513 #define PSC_AON_A7_POWERDN_TIMER1_MASK (0x3F << 0) 514 #define PSC_AON_A7_POWERDN_TIMER1_SHIFT (0) 515 #define PSC_AON_A7_POWERDN_TIMER2(n) (((n) & 0x3F) << 6) 516 #define PSC_AON_A7_POWERDN_TIMER2_MASK (0x3F << 6) 517 #define PSC_AON_A7_POWERDN_TIMER2_SHIFT (6) 518 #define PSC_AON_A7_POWERDN_TIMER3(n) (((n) & 0x3F) << 12) 519 #define PSC_AON_A7_POWERDN_TIMER3_MASK (0x3F << 12) 520 #define PSC_AON_A7_POWERDN_TIMER3_SHIFT (12) 521 #define PSC_AON_A7_POWERDN_TIMER4(n) (((n) & 0x3F) << 18) 522 #define PSC_AON_A7_POWERDN_TIMER4_MASK (0x3F << 18) 523 #define PSC_AON_A7_POWERDN_TIMER4_SHIFT (18) 524 #define PSC_AON_A7_POWERDN_TIMER5(n) (((n) & 0xFF) << 24) 525 #define PSC_AON_A7_POWERDN_TIMER5_MASK (0xFF << 24) 526 #define PSC_AON_A7_POWERDN_TIMER5_SHIFT (24) 527 528 // reg_0cc 529 #define PSC_AON_A7_POWERUP_TIMER1(n) (((n) & 0x3F) << 0) 530 #define PSC_AON_A7_POWERUP_TIMER1_MASK (0x3F << 0) 531 #define PSC_AON_A7_POWERUP_TIMER1_SHIFT (0) 532 #define PSC_AON_A7_POWERUP_TIMER2(n) (((n) & 0xFF) << 6) 533 #define PSC_AON_A7_POWERUP_TIMER2_MASK (0xFF << 6) 534 #define PSC_AON_A7_POWERUP_TIMER2_SHIFT (6) 535 #define PSC_AON_A7_POWERUP_TIMER3(n) (((n) & 0x3F) << 14) 536 #define PSC_AON_A7_POWERUP_TIMER3_MASK (0x3F << 14) 537 #define PSC_AON_A7_POWERUP_TIMER3_SHIFT (14) 538 #define PSC_AON_A7_POWERUP_TIMER4(n) (((n) & 0x3F) << 20) 539 #define PSC_AON_A7_POWERUP_TIMER4_MASK (0x3F << 20) 540 #define PSC_AON_A7_POWERUP_TIMER4_SHIFT (20) 541 #define PSC_AON_A7_POWERUP_TIMER5(n) (((n) & 0x3F) << 26) 542 #define PSC_AON_A7_POWERUP_TIMER5_MASK (0x3F << 26) 543 #define PSC_AON_A7_POWERUP_TIMER5_SHIFT (26) 544 545 // reg_0d0 546 #define PSC_AON_A7_POWERDN_START (1 << 0) 547 548 // reg_0d4 549 #define PSC_AON_A7_POWERUP_START (1 << 0) 550 551 // reg_0d8 552 #define PSC_AON_A7_CLK_STOP_REG (1 << 0) 553 #define PSC_AON_A7_ISO_EN_REG (1 << 1) 554 #define PSC_AON_A7_RESETN_ASSERT_REG (1 << 2) 555 #define PSC_AON_A7_PSW_EN_REG (1 << 3) 556 #define PSC_AON_A7_CLK_STOP_DR (1 << 4) 557 #define PSC_AON_A7_ISO_EN_DR (1 << 5) 558 #define PSC_AON_A7_RESETN_ASSERT_DR (1 << 6) 559 #define PSC_AON_A7_PSW_EN_DR (1 << 7) 560 561 // reg_0e0 562 #define PSC_AON_A7_INTR_MASK(n) (((n) & 0xFFFFFFFF) << 0) 563 #define PSC_AON_A7_INTR_MASK_MASK (0xFFFFFFFF << 0) 564 #define PSC_AON_A7_INTR_MASK_SHIFT (0) 565 566 // reg_0e4 567 #define PSC_AON_A7_INTR_MASK2(n) (((n) & 0xFFFF) << 0) 568 #define PSC_AON_A7_INTR_MASK2_MASK (0xFFFF << 0) 569 #define PSC_AON_A7_INTR_MASK2_SHIFT (0) 570 571 // reg_0e8 572 #define PSC_AON_A7_INTR_MASK_STATUS(n) (((n) & 0xFFFFFFFF) << 0) 573 #define PSC_AON_A7_INTR_MASK_STATUS_MASK (0xFFFFFFFF << 0) 574 #define PSC_AON_A7_INTR_MASK_STATUS_SHIFT (0) 575 576 // reg_0ec 577 #define PSC_AON_A7_INTR_MASK_STATUS2(n) (((n) & 0xFFFF) << 0) 578 #define PSC_AON_A7_INTR_MASK_STATUS2_MASK (0xFFFF << 0) 579 #define PSC_AON_A7_INTR_MASK_STATUS2_SHIFT (0) 580 581 // reg_0f0 582 #define PSC_AON_A7SYS_PG_AUTO_EN (1 << 0) 583 #define PSC_AON_A7SYS_PG_HW_EN (1 << 1) 584 585 // reg_0f4 586 #define PSC_AON_A7SYS_PSW_ACK_VALID (1 << 0) 587 #define PSC_AON_A7SYS_RESERVED(n) (((n) & 0x7F) << 1) 588 #define PSC_AON_A7SYS_RESERVED_MASK (0x7F << 1) 589 #define PSC_AON_A7SYS_RESERVED_SHIFT (1) 590 #define PSC_AON_A7SYS_MAIN_STATE(n) (((n) & 0x3) << 8) 591 #define PSC_AON_A7SYS_MAIN_STATE_MASK (0x3 << 8) 592 #define PSC_AON_A7SYS_MAIN_STATE_SHIFT (8) 593 #define PSC_AON_A7SYS_POWERDN_STATE(n) (((n) & 0x7) << 10) 594 #define PSC_AON_A7SYS_POWERDN_STATE_MASK (0x7 << 10) 595 #define PSC_AON_A7SYS_POWERDN_STATE_SHIFT (10) 596 #define PSC_AON_A7SYS_POWERUP_STATE(n) (((n) & 0x7) << 13) 597 #define PSC_AON_A7SYS_POWERUP_STATE_MASK (0x7 << 13) 598 #define PSC_AON_A7SYS_POWERUP_STATE_SHIFT (13) 599 600 // reg_0f8 601 #define PSC_AON_A7SYS_POWERDN_TIMER1(n) (((n) & 0x3F) << 0) 602 #define PSC_AON_A7SYS_POWERDN_TIMER1_MASK (0x3F << 0) 603 #define PSC_AON_A7SYS_POWERDN_TIMER1_SHIFT (0) 604 #define PSC_AON_A7SYS_POWERDN_TIMER2(n) (((n) & 0x3F) << 6) 605 #define PSC_AON_A7SYS_POWERDN_TIMER2_MASK (0x3F << 6) 606 #define PSC_AON_A7SYS_POWERDN_TIMER2_SHIFT (6) 607 #define PSC_AON_A7SYS_POWERDN_TIMER3(n) (((n) & 0x3F) << 12) 608 #define PSC_AON_A7SYS_POWERDN_TIMER3_MASK (0x3F << 12) 609 #define PSC_AON_A7SYS_POWERDN_TIMER3_SHIFT (12) 610 #define PSC_AON_A7SYS_POWERDN_TIMER4(n) (((n) & 0x3F) << 18) 611 #define PSC_AON_A7SYS_POWERDN_TIMER4_MASK (0x3F << 18) 612 #define PSC_AON_A7SYS_POWERDN_TIMER4_SHIFT (18) 613 #define PSC_AON_A7SYS_POWERDN_TIMER5(n) (((n) & 0xFF) << 24) 614 #define PSC_AON_A7SYS_POWERDN_TIMER5_MASK (0xFF << 24) 615 #define PSC_AON_A7SYS_POWERDN_TIMER5_SHIFT (24) 616 617 // reg_0fc 618 #define PSC_AON_A7SYS_POWERUP_TIMER1(n) (((n) & 0x3F) << 0) 619 #define PSC_AON_A7SYS_POWERUP_TIMER1_MASK (0x3F << 0) 620 #define PSC_AON_A7SYS_POWERUP_TIMER1_SHIFT (0) 621 #define PSC_AON_A7SYS_POWERUP_TIMER2(n) (((n) & 0xFF) << 6) 622 #define PSC_AON_A7SYS_POWERUP_TIMER2_MASK (0xFF << 6) 623 #define PSC_AON_A7SYS_POWERUP_TIMER2_SHIFT (6) 624 #define PSC_AON_A7SYS_POWERUP_TIMER3(n) (((n) & 0x3F) << 14) 625 #define PSC_AON_A7SYS_POWERUP_TIMER3_MASK (0x3F << 14) 626 #define PSC_AON_A7SYS_POWERUP_TIMER3_SHIFT (14) 627 #define PSC_AON_A7SYS_POWERUP_TIMER4(n) (((n) & 0x3F) << 20) 628 #define PSC_AON_A7SYS_POWERUP_TIMER4_MASK (0x3F << 20) 629 #define PSC_AON_A7SYS_POWERUP_TIMER4_SHIFT (20) 630 #define PSC_AON_A7SYS_POWERUP_TIMER5(n) (((n) & 0x3F) << 26) 631 #define PSC_AON_A7SYS_POWERUP_TIMER5_MASK (0x3F << 26) 632 #define PSC_AON_A7SYS_POWERUP_TIMER5_SHIFT (26) 633 634 // reg_100 635 #define PSC_AON_A7SYS_POWERDN_START (1 << 0) 636 637 // reg_104 638 #define PSC_AON_A7SYS_POWERUP_START (1 << 0) 639 640 // reg_108 641 #define PSC_AON_A7SYS_CLK_STOP_REG (1 << 0) 642 #define PSC_AON_A7SYS_ISO_EN_REG (1 << 1) 643 #define PSC_AON_A7SYS_RESETN_ASSERT_REG (1 << 2) 644 #define PSC_AON_A7SYS_PSW_EN_REG (1 << 3) 645 #define PSC_AON_A7SYS_CLK_STOP_DR (1 << 4) 646 #define PSC_AON_A7SYS_ISO_EN_DR (1 << 5) 647 #define PSC_AON_A7SYS_RESETN_ASSERT_DR (1 << 6) 648 #define PSC_AON_A7SYS_PSW_EN_DR (1 << 7) 649 650 // reg_110 651 #define PSC_AON_A7SYS_INTR_MASK(n) (((n) & 0xFFFFFFFF) << 0) 652 #define PSC_AON_A7SYS_INTR_MASK_MASK (0xFFFFFFFF << 0) 653 #define PSC_AON_A7SYS_INTR_MASK_SHIFT (0) 654 655 // reg_114 656 #define PSC_AON_A7SYS_INTR_MASK2(n) (((n) & 0xFFFF) << 0) 657 #define PSC_AON_A7SYS_INTR_MASK2_MASK (0xFFFF << 0) 658 #define PSC_AON_A7SYS_INTR_MASK2_SHIFT (0) 659 660 // reg_118 661 #define PSC_AON_A7SYS_INTR_MASK_STATUS(n) (((n) & 0xFFFFFFFF) << 0) 662 #define PSC_AON_A7SYS_INTR_MASK_STATUS_MASK (0xFFFFFFFF << 0) 663 #define PSC_AON_A7SYS_INTR_MASK_STATUS_SHIFT (0) 664 665 // reg_11c 666 #define PSC_AON_A7SYS_INTR_MASK_STATUS2(n) (((n) & 0xFFFF) << 0) 667 #define PSC_AON_A7SYS_INTR_MASK_STATUS2_MASK (0xFFFF << 0) 668 #define PSC_AON_A7SYS_INTR_MASK_STATUS2_SHIFT (0) 669 670 // reg_124 671 #define PSC_AON_TIMER1_MCU_REG(n) (((n) & 0xF) << 0) 672 #define PSC_AON_TIMER1_MCU_REG_MASK (0xF << 0) 673 #define PSC_AON_TIMER1_MCU_REG_SHIFT (0) 674 #define PSC_AON_TIMER2_MCU_REG(n) (((n) & 0xF) << 4) 675 #define PSC_AON_TIMER2_MCU_REG_MASK (0xF << 4) 676 #define PSC_AON_TIMER2_MCU_REG_SHIFT (4) 677 #define PSC_AON_TIMER3_MCU_REG(n) (((n) & 0xF) << 8) 678 #define PSC_AON_TIMER3_MCU_REG_MASK (0xF << 8) 679 #define PSC_AON_TIMER3_MCU_REG_SHIFT (8) 680 #define PSC_AON_PG_AUTO_EN_MCU_REG (1 << 12) 681 #define PSC_AON_PG_AUTO_EN_BT_REG (1 << 13) 682 #define PSC_AON_PG_AUTO_EN_WF_REG (1 << 14) 683 #define PSC_AON_PG_AUTO_EN_A7_REG (1 << 15) 684 #define PSC_AON_POWER_MODE_BT_DR (1 << 16) 685 #define PSC_AON_DSLP_FORCE_ON_BT_REG (1 << 17) 686 #define PSC_AON_PWR_MEM_SEL_AON_MCU (1 << 18) 687 #define PSC_AON_PWR_MEM_SEL_AON_BT (1 << 19) 688 #define PSC_AON_PWR_MEM_SEL_AON_WF (1 << 20) 689 #define PSC_AON_PWR_MEM_SEL_AON_A7 (1 << 21) 690 #define PSC_AON_DEEPSLEEP_MODE_A7_REG (1 << 22) 691 #define PSC_AON_DEEPSLEEP_MODE_WF_REG (1 << 23) 692 693 // reg_128 694 #define PSC_AON_RAM_RET1N0_0(n) (((n) & 0xFFFFFFFF) << 0) 695 #define PSC_AON_RAM_RET1N0_0_MASK (0xFFFFFFFF << 0) 696 #define PSC_AON_RAM_RET1N0_0_SHIFT (0) 697 698 // reg_12c 699 #define PSC_AON_RAM_RET1N0_1(n) (((n) & 0x1F) << 0) 700 #define PSC_AON_RAM_RET1N0_1_MASK (0x1F << 0) 701 #define PSC_AON_RAM_RET1N0_1_SHIFT (0) 702 703 // reg_130 704 #define PSC_AON_RAM_RET2N0_0(n) (((n) & 0xFFFFFFFF) << 0) 705 #define PSC_AON_RAM_RET2N0_0_MASK (0xFFFFFFFF << 0) 706 #define PSC_AON_RAM_RET2N0_0_SHIFT (0) 707 708 // reg_134 709 #define PSC_AON_RAM_RET2N0_1(n) (((n) & 0x1F) << 0) 710 #define PSC_AON_RAM_RET2N0_1_MASK (0x1F << 0) 711 #define PSC_AON_RAM_RET2N0_1_SHIFT (0) 712 713 // reg_138 714 #define PSC_AON_RAM_PGEN0_0(n) (((n) & 0xFFFFFFFF) << 0) 715 #define PSC_AON_RAM_PGEN0_0_MASK (0xFFFFFFFF << 0) 716 #define PSC_AON_RAM_PGEN0_0_SHIFT (0) 717 718 // reg_13c 719 #define PSC_AON_RAM_PGEN0_1(n) (((n) & 0x1F) << 0) 720 #define PSC_AON_RAM_PGEN0_1_MASK (0x1F << 0) 721 #define PSC_AON_RAM_PGEN0_1_SHIFT (0) 722 723 // reg_140 724 #define PSC_AON_RAM_RET1N1_0(n) (((n) & 0xFFFFFFFF) << 0) 725 #define PSC_AON_RAM_RET1N1_0_MASK (0xFFFFFFFF << 0) 726 #define PSC_AON_RAM_RET1N1_0_SHIFT (0) 727 728 // reg_144 729 #define PSC_AON_RAM_RET1N1_1(n) (((n) & 0x1F) << 0) 730 #define PSC_AON_RAM_RET1N1_1_MASK (0x1F << 0) 731 #define PSC_AON_RAM_RET1N1_1_SHIFT (0) 732 733 // reg_148 734 #define PSC_AON_RAM_RET2N1_0(n) (((n) & 0xFFFFFFFF) << 0) 735 #define PSC_AON_RAM_RET2N1_0_MASK (0xFFFFFFFF << 0) 736 #define PSC_AON_RAM_RET2N1_0_SHIFT (0) 737 738 // reg_14c 739 #define PSC_AON_RAM_RET2N1_1(n) (((n) & 0x1F) << 0) 740 #define PSC_AON_RAM_RET2N1_1_MASK (0x1F << 0) 741 #define PSC_AON_RAM_RET2N1_1_SHIFT (0) 742 743 // reg_150 744 #define PSC_AON_RAM_PGEN1_0(n) (((n) & 0xFFFFFFFF) << 0) 745 #define PSC_AON_RAM_PGEN1_0_MASK (0xFFFFFFFF << 0) 746 #define PSC_AON_RAM_PGEN1_0_SHIFT (0) 747 748 // reg_154 749 #define PSC_AON_RAM_PGEN1_1(n) (((n) & 0x1F) << 0) 750 #define PSC_AON_RAM_PGEN1_1_MASK (0x1F << 0) 751 #define PSC_AON_RAM_PGEN1_1_SHIFT (0) 752 753 // reg_158 754 #define PSC_AON_SRAM_AUTO_EN_MODE_0(n) (((n) & 0xFFFFFFFF) << 0) 755 #define PSC_AON_SRAM_AUTO_EN_MODE_0_MASK (0xFFFFFFFF << 0) 756 #define PSC_AON_SRAM_AUTO_EN_MODE_0_SHIFT (0) 757 758 // reg_15c 759 #define PSC_AON_SRAM_AUTO_EN_MODE_1(n) (((n) & 0x1F) << 0) 760 #define PSC_AON_SRAM_AUTO_EN_MODE_1_MASK (0x1F << 0) 761 #define PSC_AON_SRAM_AUTO_EN_MODE_1_SHIFT (0) 762 763 // reg_160 764 #define PSC_AON_CEN_MSK_A7_DR(n) (((n) & 0x3) << 0) 765 #define PSC_AON_CEN_MSK_A7_DR_MASK (0x3 << 0) 766 #define PSC_AON_CEN_MSK_A7_DR_SHIFT (0) 767 #define PSC_AON_CEN_MSK_WF_DR(n) (((n) & 0x3) << 2) 768 #define PSC_AON_CEN_MSK_WF_DR_MASK (0x3 << 2) 769 #define PSC_AON_CEN_MSK_WF_DR_SHIFT (2) 770 #define PSC_AON_CEN_MSK_BT_DR(n) (((n) & 0x1FF) << 4) 771 #define PSC_AON_CEN_MSK_BT_DR_MASK (0x1FF << 4) 772 #define PSC_AON_CEN_MSK_BT_DR_SHIFT (4) 773 774 // reg_164 775 #define PSC_AON_CEN_MSK_MCU_DR(n) (((n) & 0x3FFFFF) << 0) 776 #define PSC_AON_CEN_MSK_MCU_DR_MASK (0x3FFFFF << 0) 777 #define PSC_AON_CEN_MSK_MCU_DR_SHIFT (0) 778 779 // reg_168 780 #define PSC_AON_CEN_MSK_A7_REG(n) (((n) & 0x3) << 0) 781 #define PSC_AON_CEN_MSK_A7_REG_MASK (0x3 << 0) 782 #define PSC_AON_CEN_MSK_A7_REG_SHIFT (0) 783 #define PSC_AON_CEN_MSK_WF_REG(n) (((n) & 0x3) << 2) 784 #define PSC_AON_CEN_MSK_WF_REG_MASK (0x3 << 2) 785 #define PSC_AON_CEN_MSK_WF_REG_SHIFT (2) 786 #define PSC_AON_CEN_MSK_BT_REG(n) (((n) & 0x1FF) << 4) 787 #define PSC_AON_CEN_MSK_BT_REG_MASK (0x1FF << 4) 788 #define PSC_AON_CEN_MSK_BT_REG_SHIFT (4) 789 790 // reg_16c 791 #define PSC_AON_CEN_MSK_MCU_REG(n) (((n) & 0x3FFFFF) << 0) 792 #define PSC_AON_CEN_MSK_MCU_REG_MASK (0x3FFFFF << 0) 793 #define PSC_AON_CEN_MSK_MCU_REG_SHIFT (0) 794 795 // reg_170 796 #define PSC_AON_POWER_MODE_MCU_0(n) (((n) & 0xFFFFFFFF) << 0) 797 #define PSC_AON_POWER_MODE_MCU_0_MASK (0xFFFFFFFF << 0) 798 #define PSC_AON_POWER_MODE_MCU_0_SHIFT (0) 799 800 // reg_174 801 #define PSC_AON_POWER_MODE_MCU_1(n) (((n) & 0x1F) << 0) 802 #define PSC_AON_POWER_MODE_MCU_1_MASK (0x1F << 0) 803 #define PSC_AON_POWER_MODE_MCU_1_SHIFT (0) 804 805 #endif 806