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1 /**
2   ******************************************************************************
3   * @file    stm32mp157axx_ca7.h
4   * @author  MCD Application Team
5   * @brief   CMSIS stm32mp157axx_ca7 Device Peripheral Access Layer Header File.
6   *
7   *          This file contains:
8   *           - Data structures and the address mapping for all peripherals
9   *           - Peripheral's registers declarations and bits definition
10   *           - Macros to access peripherals registers hardware
11   *
12   ******************************************************************************
13   * @attention
14   *
15   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
16   * All rights reserved.</center></h2>
17   *
18   * This software component is licensed by ST under BSD 3-Clause license,
19   * the "License"; You may not use this file except in compliance with the
20   * License. You may obtain a copy of the License at:
21   *                        opensource.org/licenses/BSD-3-Clause
22   *
23   ******************************************************************************
24   */
25 
26 /** @addtogroup CMSIS_Device
27   * @{
28   */
29 
30 /** @addtogroup stm32mp157axx_ca7
31   * @{
32   */
33 
34 #ifndef __STM32MP157Axx_CA7_H
35 #define __STM32MP157Axx_CA7_H
36 
37 #include "osal_io.h"
38 
39 #ifdef __cplusplus
40  extern "C" {
41 #endif /* __cplusplus */
42 
43 #ifdef __cplusplus
44   #define   __I     volatile             /*!< defines 'read only' permissions                 */
45 #else
46   #define   __I     volatile const       /*!< defines 'read only' permissions                 */
47 #endif
48 #define     __O     volatile             /*!< defines 'write only' permissions                */
49 #define     __IO    volatile             /*!< defines 'read / write' permissions              */
50 
51 /**
52   * @brief Bit position definition inside a 32 bits registers
53   */
54 #define  B(x) \
55         ((uint32_t) 1 << x)
56 /**
57   * @}
58   */
59 
60 /** @addtogroup Peripheral_interrupt_number_definition
61   * @{
62   */
63 
64 /**
65  * @brief STM32MP1XX Interrupt Number Definition, according to the selected device
66  *        in @ref Library_configuration_section
67  */
68  typedef enum IRQn
69  {
70    /******  Cortex-A Processor Specific Interrupt Numbers ***************************************************************/
71    /* Software Generated Interrupts                                                                                     */
72    SGI0_IRQn                        =  0,     /*!< Software Generated Interrupt  0                                      */
73    SGI1_IRQn                        =  1,     /*!< Software Generated Interrupt  1                                      */
74    SGI2_IRQn                        =  2,     /*!< Software Generated Interrupt  2                                      */
75    SGI3_IRQn                        =  3,     /*!< Software Generated Interrupt  3                                      */
76    SGI4_IRQn                        =  4,     /*!< Software Generated Interrupt  4                                      */
77    SGI5_IRQn                        =  5,     /*!< Software Generated Interrupt  5                                      */
78    SGI6_IRQn                        =  6,     /*!< Software Generated Interrupt  6                                      */
79    SGI7_IRQn                        =  7,     /*!< Software Generated Interrupt  7                                      */
80    SGI8_IRQn                        =  8,     /*!< Software Generated Interrupt  8                                      */
81    SGI9_IRQn                        =  9,     /*!< Software Generated Interrupt  9                                      */
82    SGI10_IRQn                       = 10,     /*!< Software Generated Interrupt 10                                      */
83    SGI11_IRQn                       = 11,     /*!< Software Generated Interrupt 11                                      */
84    SGI12_IRQn                       = 12,     /*!< Software Generated Interrupt 12                                      */
85    SGI13_IRQn                       = 13,     /*!< Software Generated Interrupt 13                                      */
86    SGI14_IRQn                       = 14,     /*!< Software Generated Interrupt 14                                      */
87    SGI15_IRQn                       = 15,     /*!< Software Generated Interrupt 15                                      */
88    /* Private Peripheral Interrupts                                                                                     */
89    VirtualMaintenanceInterrupt_IRQn = 25,     /*!< Virtual Maintenance Interrupt                                        */
90    HypervisorTimer_IRQn             = 26,     /*!< Hypervisor Timer Interrupt                                           */
91    VirtualTimer_IRQn                = 27,     /*!< Virtual Timer Interrupt                                              */
92    Legacy_nFIQ_IRQn                 = 28,     /*!< Legacy nFIQ Interrupt                                                */
93    SecurePhysicalTimer_IRQn         = 29,     /*!< Secure Physical Timer Interrupt                                      */
94    NonSecurePhysicalTimer_IRQn      = 30,     /*!< Non-Secure Physical Timer Interrupt                                  */
95    Legacy_nIRQ_IRQn                 = 31,     /*!< Legacy nIRQ Interrupt                                                */
96    /******  STM32 specific Interrupt Numbers ****************************************************************************/
97    WWDG1_IRQn                       = 32,     /*!< Window WatchDog Interrupt                                            */
98    PVD_AVD_IRQn                     = 33,     /*!< PVD & AVD detector through EXTI                                      */
99    TAMP_IRQn                        = 34,     /*!< Tamper interrupts through the EXTI line                              */
100    RTC_WKUP_ALARM_IRQn              = 35,     /*!< RTC Wakeup and Alarm (A & B) interrupt through the EXTI line         */
101    RESERVED_36                      = 36,     /*!< RESERVED interrupt                                                   */
102    RCC_IRQn                         = 37,     /*!< RCC global Interrupt                                                 */
103    EXTI0_IRQn                       = 38,     /*!< EXTI Line0 Interrupt                                                 */
104    EXTI1_IRQn                       = 39,     /*!< EXTI Line1 Interrupt                                                 */
105    EXTI2_IRQn                       = 40,     /*!< EXTI Line2 Interrupt                                                 */
106    EXTI3_IRQn                       = 41,     /*!< EXTI Line3 Interrupt                                                 */
107    EXTI4_IRQn                       = 42,     /*!< EXTI Line4 Interrupt                                                 */
108    DMA1_Stream0_IRQn                = 43,     /*!< DMA1 Stream 0 global Interrupt                                       */
109    DMA1_Stream1_IRQn                = 44,     /*!< DMA1 Stream 1 global Interrupt                                       */
110    DMA1_Stream2_IRQn                = 45,     /*!< DMA1 Stream 2 global Interrupt                                       */
111    DMA1_Stream3_IRQn                = 46,     /*!< DMA1 Stream 3 global Interrupt                                       */
112    DMA1_Stream4_IRQn                = 47,     /*!< DMA1 Stream 4 global Interrupt                                       */
113    DMA1_Stream5_IRQn                = 48,     /*!< DMA1 Stream 5 global Interrupt                                       */
114    DMA1_Stream6_IRQn                = 49,     /*!< DMA1 Stream 6 global Interrupt                                       */
115    ADC1_IRQn                        = 50,     /*!< ADC1 global Interrupts                                               */
116    FDCAN1_IT0_IRQn                  = 51,     /*!< FDCAN1 Interrupt line 0                                              */
117    FDCAN2_IT0_IRQn                  = 52,     /*!< FDCAN2 Interrupt line 0                                              */
118    FDCAN1_IT1_IRQn                  = 53,     /*!< FDCAN1 Interrupt line 1                                              */
119    FDCAN2_IT1_IRQn                  = 54,     /*!< FDCAN2 Interrupt line 1                                              */
120    EXTI5_IRQn                       = 55,     /*!< External Line[9:5] Interrupts                                        */
121    TIM1_BRK_IRQn                    = 56,     /*!< TIM1 Break interrupt                                                 */
122    TIM1_UP_IRQn                     = 57,     /*!< TIM1 Update Interrupt                                                */
123    TIM1_TRG_COM_IRQn                = 58,     /*!< TIM1 Trigger and Commutation Interrupt                               */
124    TIM1_CC_IRQn                     = 59,     /*!< TIM1 Capture Compare Interrupt                                       */
125    TIM2_IRQn                        = 60,     /*!< TIM2 global Interrupt                                                */
126    TIM3_IRQn                        = 61,     /*!< TIM3 global Interrupt                                                */
127    TIM4_IRQn                        = 62,     /*!< TIM4 global Interrupt                                                */
128    I2C1_EV_IRQn                     = 63,     /*!< I2C1 Event Interrupt                                                 */
129    I2C1_ER_IRQn                     = 64,     /*!< I2C1 Error Interrupt                                                 */
130    I2C2_EV_IRQn                     = 65,     /*!< I2C2 Event Interrupt                                                 */
131    I2C2_ER_IRQn                     = 66,     /*!< I2C2 Error Interrupt                                                 */
132    SPI1_IRQn                        = 67,     /*!< SPI1 global Interrupt                                                */
133    SPI2_IRQn                        = 68,     /*!< SPI2 global Interrupt                                                */
134    USART1_IRQn                      = 69,     /*!< USART1 global Interrupt                                              */
135    USART2_IRQn                      = 70,     /*!< USART2 global Interrupt                                              */
136    USART3_IRQn                      = 71,     /*!< USART3 global Interrupt                                              */
137    EXTI10_IRQn                      = 72,     /*!< EXTI Line 10 Interrupts                                              */
138    RTC_TIMESTAMP_IRQn               = 73,     /*!< RTC TimeStamp through EXTI Line Interrupt                            */
139    EXTI11_IRQn                      = 74,     /*!< EXTI Line 11 Interrupts                                              */
140    TIM8_BRK_IRQn                    = 75,     /*!< TIM8 Break Interrupt                                                 */
141    TIM8_UP_IRQn                     = 76,     /*!< TIM8 Update Interrupt                                                */
142    TIM8_TRG_COM_IRQn                = 77,     /*!< TIM8 Trigger and Commutation Interrupt                               */
143    TIM8_CC_IRQn                     = 78,     /*!< TIM8 Capture Compare Interrupt                                       */
144    DMA1_Stream7_IRQn                = 79,     /*!< DMA1 Stream7 Interrupt                                               */
145    FMC_IRQn                         = 80,     /*!< FMC global Interrupt                                                 */
146    SDMMC1_IRQn                      = 81,     /*!< SDMMC1 global Interrupt                                              */
147    TIM5_IRQn                        = 82,     /*!< TIM5 global Interrupt                                                */
148    SPI3_IRQn                        = 83,     /*!< SPI3 global Interrupt                                                */
149    UART4_IRQn                       = 84,     /*!< UART4 global Interrupt                                               */
150    UART5_IRQn                       = 85,     /*!< UART5 global Interrupt                                               */
151    TIM6_IRQn                        = 86,     /*!< TIM6 global                                                          */
152    TIM7_IRQn                        = 87,     /*!< TIM7 global interrupt                                                */
153    DMA2_Stream0_IRQn                = 88,     /*!< DMA2 Stream 0 global Interrupt                                       */
154    DMA2_Stream1_IRQn                = 89,     /*!< DMA2 Stream 1 global Interrupt                                       */
155    DMA2_Stream2_IRQn                = 90,     /*!< DMA2 Stream 2 global Interrupt                                       */
156    DMA2_Stream3_IRQn                = 91,     /*!< GPDMA2 Stream 3 global Interrupt                                     */
157    DMA2_Stream4_IRQn                = 92,     /*!< GPDMA2 Stream 4 global Interrupt                                     */
158    ETH1_IRQn                        = 93,     /*!< Ethernet global Interrupt                                            */
159    ETH1_WKUP_IRQn                   = 94,     /*!< Ethernet Wakeup through EXTI line Interrupt                          */
160    FDCAN_CAL_IRQn                   = 95,     /*!< CAN calibration unit interrupt                                       */
161    EXTI6_IRQn                       = 96,     /*!< EXTI Line 6 Interrupts                                               */
162    EXTI7_IRQn                       = 97,     /*!< EXTI Line 7 Interrupts                                               */
163    EXTI8_IRQn                       = 98,     /*!< EXTI Line 8 Interrupts                                               */
164    EXTI9_IRQn                       = 99,     /*!< EXTI Line 9 Interrupts                                               */
165    DMA2_Stream5_IRQn                = 100,    /*!< DMA2 Stream 5 global interrupt                                       */
166    DMA2_Stream6_IRQn                = 101,    /*!< DMA2 Stream 6 global interrupt                                       */
167    DMA2_Stream7_IRQn                = 102,    /*!< DMA2 Stream 7 global interrupt                                       */
168    USART6_IRQn                      = 103,    /*!< USART6 global interrupt                                              */
169    I2C3_EV_IRQn                     = 104,    /*!< I2C3 event interrupt                                                 */
170    I2C3_ER_IRQn                     = 105,    /*!< I2C3 error interrupt                                                 */
171    USBH_OHCI_IRQn                   = 106,    /*!< USB OHCI global interrupt                                            */
172    USBH_EHCI_IRQn                   = 107,    /*!< USB EHCI global interrupt                                            */
173    EXTI12_IRQn                      = 108,    /*!< EXTI Line 76 Interrupts                                              */
174    EXTI13_IRQn                      = 109,    /*!< EXTI Line 77 Interrupts                                              */
175    DCMI_IRQn                        = 110,    /*!< DCMI global interrupt                                                */
176    RESERVED_111                     = 111,    /*!< reserved                                                             */
177    HASH1_IRQn                       = 112,    /*!< Hash global interrupt                                                */
178    RESERVED_113                     = 113,    /*!< reserved                                                             */
179    UART7_IRQn                       = 114,    /*!< UART7 global interrupt                                               */
180    UART8_IRQn                       = 115,    /*!< UART8 global interrupt                                               */
181    SPI4_IRQn                        = 116,    /*!< SPI4 global Interrupt                                                */
182    SPI5_IRQn                        = 117,    /*!< SPI5 global Interrupt                                                */
183    SPI6_IRQn                        = 118,    /*!< SPI6 global Interrupt                                                */
184    SAI1_IRQn                        = 119,    /*!< SAI1 global Interrupt                                                */
185    LTDC_IRQn                        = 120,    /*!< LTDC global Interrupt                                                */
186    LTDC_ER_IRQn                     = 121,    /*!< LTDC Error global Interrupt                                          */
187    ADC2_IRQn                        = 122,    /*!< ADC2 global Interrupts                                               */
188    SAI2_IRQn                        = 123,    /*!< SAI2 global Interrupt                                                */
189    QUADSPI_IRQn                     = 124,    /*!< Quad SPI global interrupt                                            */
190    LPTIM1_IRQn                      = 125,    /*!< LP TIM1 interrupt                                                    */
191    CEC_IRQn                         = 126,    /*!< HDMI-CEC global Interrupt                                            */
192    I2C4_EV_IRQn                     = 127,    /*!< I2C4 Event Interrupt                                                 */
193    I2C4_ER_IRQn                     = 128,    /*!< I2C4 Error Interrupt                                                 */
194    SPDIF_RX_IRQn                    = 129,    /*!< SPDIF-RX global Interrupt                                            */
195    OTG_IRQn                         = 130,    /*!< USB On The Go global interrupt                                       */
196    RESERVED_131                     = 131,    /*!< RESERVED interrupt                                                   */
197    IPCC_RX0_IRQn                    = 132,    /*!< IPCC RX0 Occupied interrupt (interrupt going to AIEC input as well)  */
198    IPCC_TX0_IRQn                    = 133,    /*!< IPCC TX0 Free interrupt (interrupt going to AIEC input as well)      */
199    DMAMUX1_OVR_IRQn                 = 134,    /*!< DMAMUX1 Overrun interrupt                                            */
200    IPCC_RX1_IRQn                    = 135,    /*!< IPCC RX1 Occupied interrupt (interrupt going to AIEC input as well)  */
201    IPCC_TX1_IRQn                    = 136,    /*!< IPCC TX1 Free interrupt (interrupt going to AIEC input as well)      */
202    RESERVED_137                     = 137,    /*!< reserved                                                             */
203    HASH2_IRQn                       = 138,    /*!< Crypto Hash2 interrupt                                               */
204    I2C5_EV_IRQn                     = 139,    /*!< I2C5 Event Interrupt                                                 */
205    I2C5_ER_IRQn                     = 140,    /*!< I2C5 Error Interrupt                                                 */
206    GPU_IRQn                         = 141,    /*!< GPU global Interrupt                                                 */
207    DFSDM1_FLT0_IRQn                 = 142,    /*!< DFSDM Filter1 Interrupt                                              */
208    DFSDM1_FLT1_IRQn                 = 143,    /*!< DFSDM Filter2 Interrupt                                              */
209    DFSDM1_FLT2_IRQn                 = 144,    /*!< DFSDM Filter3 Interrupt                                              */
210    DFSDM1_FLT3_IRQn                 = 145,    /*!< DFSDM Filter4 Interrupt                                              */
211    SAI3_IRQn                        = 146,    /*!< SAI3 global Interrupt                                                */
212    DFSDM1_FLT4_IRQn                 = 147,    /*!< DFSDM Filter5 Interrupt                                              */
213    TIM15_IRQn                       = 148,    /*!< TIM15 global Interrupt                                               */
214    TIM16_IRQn                       = 149,    /*!< TIM16 global Interrupt                                               */
215    TIM17_IRQn                       = 150,    /*!< TIM17 global Interrupt                                               */
216    TIM12_IRQn                       = 151,    /*!< TIM12 global Interrupt                                               */
217    MDIOS_IRQn                       = 152,    /*!< MDIOS global Interrupt                                               */
218    EXTI14_IRQn                      = 153,    /*!< EXTI Line 14 Interrupts                                              */
219    MDMA_IRQn                        = 154,    /*!< MDMA global Interrupt                                                */
220    DSI_IRQn                         = 155,    /*!< DSI global Interrupt                                                 */
221    SDMMC2_IRQn                      = 156,    /*!< SDMMC2 global Interrupt                                              */
222    HSEM_IT1_IRQn                    = 157,    /*!< HSEM Semaphore Interrupt 1                                           */
223    DFSDM1_FLT5_IRQn                 = 158,    /*!< DFSDM Filter6 Interrupt                                              */
224    EXTI15_IRQn                      = 159,    /*!< EXTI Line 15 Interrupts                                              */
225    MDMA_SEC_IT_IRQn                 = 160,    /*!< MDMA global Secure interrupt                                         */
226    SYSRESETQ_IRQn                   = 161,    /*!< MCU local Reset Request                                              */
227    TIM13_IRQn                       = 162,    /*!< TIM13 global interrupt                                               */
228    TIM14_IRQn                       = 163,    /*!< TIM14 global interrupt                                               */
229    DAC_IRQn                         = 164,    /*!< DAC1 and DAC2 underrun error interrupts                              */
230    RNG1_IRQn                        = 165,    /*!< RNG1 interrupt                                                       */
231    RNG2_IRQn                        = 166,    /*!< RNG2 interrupt                                                       */
232    I2C6_EV_IRQn                     = 167,    /*!< I2C6 Event Interrupt                                                 */
233    I2C6_ER_IRQn                     = 168,    /*!< I2C6 Error Interrupt                                                 */
234    SDMMC3_IRQn                      = 169,    /*!< SDMMC3 global Interrupt                                              */
235    LPTIM2_IRQn                      = 170,    /*!< LP TIM2 global interrupt                                             */
236    LPTIM3_IRQn                      = 171,    /*!< LP TIM3 global interrupt                                             */
237    LPTIM4_IRQn                      = 172,    /*!< LP TIM4 global interrupt                                             */
238    LPTIM5_IRQn                      = 173,    /*!< LP TIM5 global interrupt                                             */
239    ETH1_LPI_IRQn                    = 174,    /*!< ETH1_LPI interrupt (LPI: lpi_intr_o)                                 */
240    WWDG1_RST                        = 175,    /*!< Window Watchdog 1 Reset through AIEC                                 */
241    MCU_SEV_IRQn                     = 176,    /*!< MCU Send Event  interrupt                                            */
242    RCC_WAKEUP_IRQn                  = 177,    /*!< RCC Wake up interrupt                                                */
243    SAI4_IRQn                        = 178,    /*!< SAI4 global interrupt                                                */
244    DTS_IRQn                         = 179,    /*!< Temperature sensor Global Interrupt                                  */
245    RESERVED_180                     = 180,    /*!< reserved                                                             */
246    WAKEUP_PIN_IRQn                  = 181,    /*!< Interrupt for all 6 wake-up pins                                     */
247    IWDG1_IRQn                       = 182,    /*!< IWDG1 Early Interrupt                                                */
248    IWDG2_IRQn                       = 183,    /*!< IWDG2 Early Interrupt                                                */
249    TAMP_SERR_S_IRQn                 = 229,    /*!< TAMP Tamper and Security Error Secure interrupts                     */
250    RTC_WKUP_ALARM_S_IRQn            = 230,    /*!< RTC Wakeup Timer and Alarms (A and B) Secure interrupt               */
251    RTC_TS_SERR_S_IRQn               = 231,    /*!< RTC TimeStamp and Security Error Secure interrupt                    */
252    MAX_IRQ_n,
253    Force_IRQn_enum_size             = 1048    /* Dummy entry to ensure IRQn_Type is more than 8 bits. Otherwise GIC init loop would fail */
254  } IRQn_Type;
255 
256 /** @addtogroup Configuration_section_for_CMSIS
257   * @{
258   */
259 
260 #define SDC        /*!< Step Down Converter feature */
261 
262 /**
263   * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals
264    */
265 
266 /* =========================================================================================================================== */
267 /* ================                           Processor and Core Peripheral Section                           ================ */
268 /* =========================================================================================================================== */
269 
270 /* ===========================  Configuration of the ARM Cortex-A Processor and Core Peripherals  ============================ */
271 #define __CORTEX_A                    7U      /*!< Cortex-A# Core                              */
272 #define __CA_REV                 0x0005U      /*!< Core revision r0p0                          */
273 #define __FPU_PRESENT                 1U      /*!< Set to 1 if FPU is present                  */
274 #define __GIC_PRESENT                 1U      /*!< Set to 1 if GIC is present                  */
275 #define __TIM_PRESENT                 1U      /*!< Set to 1 if TIM is present                  */
276 #define __L2C_PRESENT                 0U      /*!< Set to 1 if L2C is present                  */
277 
278 #define GIC_BASE             0xA0021000
279 #define GIC_DISTRIBUTOR_BASE GIC_BASE
280 #define GIC_INTERFACE_BASE   (GIC_BASE+0x1000)
281 
282 
283 #include "system_stm32mp1xx.h"
284 #include <stdint.h>
285 
286 /** @addtogroup Peripheral_registers_structures
287   * @{
288   */
289 
290 /**
291   * @brief Analog to Digital Converter
292   */
293 
294 typedef struct
295 {
296   __IO uint32_t ISR;              /*!< ADC Interrupt and Status Register,                 Address offset: 0x00 */
297   __IO uint32_t IER;              /*!< ADC Interrupt Enable Register,                     Address offset: 0x04 */
298   __IO uint32_t CR;               /*!< ADC control register,                              Address offset: 0x08 */
299   __IO uint32_t CFGR;             /*!< ADC Configuration register,                        Address offset: 0x0C */
300   __IO uint32_t CFGR2;            /*!< ADC Configuration register 2,                      Address offset: 0x10 */
301   __IO uint32_t SMPR1;            /*!< ADC sample time register 1,                        Address offset: 0x14 */
302   __IO uint32_t SMPR2;            /*!< ADC sample time register 2,                        Address offset: 0x18 */
303   __IO uint32_t PCSEL;            /*!< ADC pre-channel selection,                         Address offset: 0x1C */
304   __IO uint32_t LTR1;             /*!< ADC watchdog Lower threshold register 1,           Address offset: 0x20 */
305   __IO uint32_t HTR1;             /*!< ADC watchdog higher threshold register 1,          Address offset: 0x24 */
306   uint32_t      RESERVED1;        /*!< Reserved, 0x028                                                         */
307   uint32_t      RESERVED2;        /*!< Reserved, 0x02C                                                         */
308   __IO uint32_t SQR1;             /*!< ADC regular sequence register 1,                   Address offset: 0x30 */
309   __IO uint32_t SQR2;             /*!< ADC regular sequence register 2,                   Address offset: 0x34 */
310   __IO uint32_t SQR3;             /*!< ADC regular sequence register 3,                   Address offset: 0x38 */
311   __IO uint32_t SQR4;             /*!< ADC regular sequence register 4,                   Address offset: 0x3C */
312   __IO uint32_t DR;               /*!< ADC regular data register,                         Address offset: 0x40 */
313   uint32_t      RESERVED3;        /*!< Reserved, 0x044                                                         */
314   uint32_t      RESERVED4;        /*!< Reserved, 0x048                                                         */
315   __IO uint32_t JSQR;             /*!< ADC injected sequence register,                    Address offset: 0x4C */
316   uint32_t      RESERVED5[4];     /*!< Reserved, 0x050 - 0x05C                                                 */
317   __IO uint32_t OFR1;             /*!< ADC offset register 1,                             Address offset: 0x60 */
318   __IO uint32_t OFR2;             /*!< ADC offset register 2,                             Address offset: 0x64 */
319   __IO uint32_t OFR3;             /*!< ADC offset register 3,                             Address offset: 0x68 */
320   __IO uint32_t OFR4;             /*!< ADC offset register 4,                             Address offset: 0x6C */
321   uint32_t      RESERVED6[4];     /*!< Reserved, 0x070 - 0x07C                                                 */
322   __IO uint32_t JDR1;             /*!< ADC injected data register 1,                      Address offset: 0x80 */
323   __IO uint32_t JDR2;             /*!< ADC injected data register 2,                      Address offset: 0x84 */
324   __IO uint32_t JDR3;             /*!< ADC injected data register 3,                      Address offset: 0x88 */
325   __IO uint32_t JDR4;             /*!< ADC injected data register 4,                      Address offset: 0x8C */
326   uint32_t      RESERVED7[4];     /*!< Reserved, 0x090 - 0x09C                                                 */
327   __IO uint32_t AWD2CR;           /*!< ADC  Analog Watchdog 2 Configuration Register,     Address offset: 0xA0 */
328   __IO uint32_t AWD3CR;           /*!< ADC  Analog Watchdog 3 Configuration Register,     Address offset: 0xA4 */
329   uint32_t      RESERVED8;        /*!< Reserved, 0x0A8                                                         */
330   uint32_t      RESERVED9;        /*!< Reserved, 0x0AC                                                         */
331   __IO uint32_t LTR2;             /*!< ADC watchdog Lower threshold register 2,           Address offset: 0xB0 */
332   __IO uint32_t HTR2;             /*!< ADC watchdog Higher threshold register 2,          Address offset: 0xB4 */
333   __IO uint32_t LTR3;             /*!< ADC watchdog Lower threshold register 3,           Address offset: 0xB8 */
334   __IO uint32_t HTR3;             /*!< ADC watchdog Higher threshold register 3,          Address offset: 0xBC */
335   __IO uint32_t DIFSEL;           /*!< ADC  Differential Mode Selection Register,         Address offset: 0xC0 */
336   __IO uint32_t CALFACT;          /*!< ADC  Calibration Factors,                          Address offset: 0xC4 */
337   __IO uint32_t CALFACT2;         /*!< ADC  Linearity Calibration Factors,                Address offset: 0xC8 */
338   uint32_t      RESERVED10;       /*!< Reserved,                                                         0x0CC */
339   __IO uint32_t OR;               /*!< ADC  Calibration Factors,                         Address offset: 0x0D0 */
340   uint32_t  RESERVED11[200];       /*!< Reserved,                                                 0x0D4 - 0x3F0 */
341   __IO uint32_t VERR;             /*!< ADC version register,                             Address offset: 0x3F4 */
342   __IO uint32_t IPIDR;            /*!< ADC ID register,                                  Address offset: 0x3F8 */
343   __IO uint32_t SIDR;             /*!< ADC Size ID register,                             Address offset: 0x3FC */
344 } ADC_TypeDef;
345 
346 
347 typedef struct
348 {
349   __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
350   uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
351   __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
352   __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */
353   __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */
354 
355 } ADC_Common_TypeDef;
356 
357 /**
358   * @brief FD Controller Area Network
359   */
360 
361 typedef struct
362 {
363   __IO uint32_t CREL;         /*!< FDCAN Core Release register,                                     Address offset: 0x000 */
364   __IO uint32_t ENDN;         /*!< FDCAN Endian register,                                           Address offset: 0x004 */
365   __IO uint32_t RESERVED1;    /*!< Reserved,                                                                        0x008 */
366   __IO uint32_t DBTP;         /*!< FDCAN Data Bit Timing & Prescaler register,                      Address offset: 0x00C */
367   __IO uint32_t TEST;         /*!< FDCAN Test register,                                             Address offset: 0x010 */
368   __IO uint32_t RWD;          /*!< FDCAN RAM Watchdog register,                                     Address offset: 0x014 */
369   __IO uint32_t CCCR;         /*!< FDCAN CC Control register,                                       Address offset: 0x018 */
370   __IO uint32_t NBTP;         /*!< FDCAN Nominal Bit Timing & Prescaler register,                   Address offset: 0x01C */
371   __IO uint32_t TSCC;         /*!< FDCAN Timestamp Counter Configuration register,                  Address offset: 0x020 */
372   __IO uint32_t TSCV;         /*!< FDCAN Timestamp Counter Value register,                          Address offset: 0x024 */
373   __IO uint32_t TOCC;         /*!< FDCAN Timeout Counter Configuration register,                    Address offset: 0x028 */
374   __IO uint32_t TOCV;         /*!< FDCAN Timeout Counter Value register,                            Address offset: 0x02C */
375   __IO uint32_t RESERVED2[4]; /*!< Reserved,                                                                0x030 - 0x03C */
376   __IO uint32_t ECR;          /*!< FDCAN Error Counter register,                                    Address offset: 0x040 */
377   __IO uint32_t PSR;          /*!< FDCAN Protocol Status register,                                  Address offset: 0x044 */
378   __IO uint32_t TDCR;         /*!< FDCAN Transmitter Delay Compensation register,                   Address offset: 0x048 */
379   __IO uint32_t RESERVED3;    /*!< Reserved,                                                                        0x04C */
380   __IO uint32_t IR;           /*!< FDCAN Interrupt register,                                        Address offset: 0x050 */
381   __IO uint32_t IE;           /*!< FDCAN Interrupt Enable register,                                 Address offset: 0x054 */
382   __IO uint32_t ILS;          /*!< FDCAN Interrupt Line Select register,                            Address offset: 0x058 */
383   __IO uint32_t ILE;          /*!< FDCAN Interrupt Line Enable register,                            Address offset: 0x05C */
384   __IO uint32_t RESERVED4[8]; /*!< Reserved,                                                                0x060 - 0x07C */
385   __IO uint32_t GFC;          /*!< FDCAN Global Filter Configuration register,                      Address offset: 0x080 */
386   __IO uint32_t SIDFC;        /*!< FDCAN Standard ID Filter Configuration register,                 Address offset: 0x084 */
387   __IO uint32_t XIDFC;        /*!< FDCAN Extended ID Filter Configuration register,                 Address offset: 0x088 */
388   __IO uint32_t RESERVED5;    /*!< Reserved,                                                                        0x08C */
389   __IO uint32_t XIDAM;        /*!< FDCAN Extended ID AND Mask register,                             Address offset: 0x090 */
390   __IO uint32_t HPMS;         /*!< FDCAN High Priority Message Status register,                     Address offset: 0x094 */
391   __IO uint32_t NDAT1;        /*!< FDCAN New Data 1 register,                                       Address offset: 0x098 */
392   __IO uint32_t NDAT2;        /*!< FDCAN New Data 2 register,                                       Address offset: 0x09C */
393   __IO uint32_t RXF0C;        /*!< FDCAN Rx FIFO 0 Configuration register,                          Address offset: 0x0A0 */
394   __IO uint32_t RXF0S;        /*!< FDCAN Rx FIFO 0 Status register,                                 Address offset: 0x0A4 */
395   __IO uint32_t RXF0A;        /*!< FDCAN Rx FIFO 0 Acknowledge register,                            Address offset: 0x0A8 */
396   __IO uint32_t RXBC;         /*!< FDCAN Rx Buffer Configuration register,                          Address offset: 0x0AC */
397   __IO uint32_t RXF1C;        /*!< FDCAN Rx FIFO 1 Configuration register,                          Address offset: 0x0B0 */
398   __IO uint32_t RXF1S;        /*!< FDCAN Rx FIFO 1 Status register,                                 Address offset: 0x0B4 */
399   __IO uint32_t RXF1A;        /*!< FDCAN Rx FIFO 1 Acknowledge register,                            Address offset: 0x0B8 */
400   __IO uint32_t RXESC;        /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register,        Address offset: 0x0BC */
401   __IO uint32_t TXBC;         /*!< FDCAN Tx Buffer Configuration register,                          Address offset: 0x0C0 */
402   __IO uint32_t TXFQS;        /*!< FDCAN Tx FIFO/Queue Status register,                             Address offset: 0x0C4 */
403   __IO uint32_t TXESC;        /*!< FDCAN Tx Buffer Element Size Configuration register,             Address offset: 0x0C8 */
404   __IO uint32_t TXBRP;        /*!< FDCAN Tx Buffer Request Pending register,                        Address offset: 0x0CC */
405   __IO uint32_t TXBAR;        /*!< FDCAN Tx Buffer Add Request register,                            Address offset: 0x0D0 */
406   __IO uint32_t TXBCR;        /*!< FDCAN Tx Buffer Cancellation Request register,                   Address offset: 0x0D4 */
407   __IO uint32_t TXBTO;        /*!< FDCAN Tx Buffer Transmission Occurred register,                  Address offset: 0x0D8 */
408   __IO uint32_t TXBCF;        /*!< FDCAN Tx Buffer Cancellation Finished register,                  Address offset: 0x0DC */
409   __IO uint32_t TXBTIE;       /*!< FDCAN Tx Buffer Transmission Interrupt Enable register,          Address offset: 0x0E0 */
410   __IO uint32_t TXBCIE;       /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */
411   __IO uint32_t RESERVED6[2]; /*!< Reserved,                                                                0x0E8 - 0x0EC */
412   __IO uint32_t TXEFC;        /*!< FDCAN Tx Event FIFO Configuration register,                      Address offset: 0x0F0 */
413   __IO uint32_t TXEFS;        /*!< FDCAN Tx Event FIFO Status register,                             Address offset: 0x0F4 */
414   __IO uint32_t TXEFA;        /*!< FDCAN Tx Event FIFO Acknowledge register,                        Address offset: 0x0F8 */
415   __IO uint32_t RESERVED7;    /*!< Reserved,                                                                        0x0FC */
416 } FDCAN_GlobalTypeDef;
417 
418 /**
419   * @brief TTFD Controller Area Network
420   */
421 
422 typedef struct
423 {
424   __IO uint32_t TTTMC;          /*!< TT Trigger Memory Configuration register,    Address offset: 0x100 */
425   __IO uint32_t TTRMC;          /*!< TT Reference Message Configuration register, Address offset: 0x104 */
426   __IO uint32_t TTOCF;          /*!< TT Operation Configuration register,         Address offset: 0x108 */
427   __IO uint32_t TTMLM;          /*!< TT Matrix Limits register,                   Address offset: 0x10C */
428   __IO uint32_t TURCF;          /*!< TUR Configuration register,                  Address offset: 0x110 */
429   __IO uint32_t TTOCN;          /*!< TT Operation Control register,               Address offset: 0x114 */
430   __IO uint32_t TTGTP;          /*!< TT Global Time Preset register,              Address offset: 0x118 */
431   __IO uint32_t TTTMK;          /*!< TT Time Mark register,                       Address offset: 0x11C */
432   __IO uint32_t TTIR;           /*!< TT Interrupt register,                       Address offset: 0x120 */
433   __IO uint32_t TTIE;           /*!< TT Interrupt Enable register,                Address offset: 0x124 */
434   __IO uint32_t TTILS;          /*!< TT Interrupt Line Select register,           Address offset: 0x128 */
435   __IO uint32_t TTOST;          /*!< TT Operation Status register,                Address offset: 0x12C */
436   __IO uint32_t TURNA;          /*!< TT TUR Numerator Actual register,            Address offset: 0x130 */
437   __IO uint32_t TTLGT;          /*!< TT Local and Global Time register,           Address offset: 0x134 */
438   __IO uint32_t TTCTC;          /*!< TT Cycle Time and Count register,            Address offset: 0x138 */
439   __IO uint32_t TTCPT;          /*!< TT Capture Time register,                    Address offset: 0x13C */
440   __IO uint32_t TTCSM;          /*!< TT Cycle Sync Mark register,                 Address offset: 0x140 */
441   __IO uint32_t RESERVED1[111]; /*!< Reserved,                                            0x144 - 0x2FC */
442   __IO uint32_t TTTS;           /*!< TT Trigger Select register,                  Address offset: 0x300 */
443 } TTCAN_TypeDef;
444 
445 /**
446   * @brief FD Controller Area Network
447   */
448 
449 typedef struct
450 {
451   __IO uint32_t CREL;  /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */
452   __IO uint32_t CCFG;  /*!< Calibration Configuration register,           Address offset: 0x04 */
453   __IO uint32_t CSTAT; /*!< Calibration Status register,                  Address offset: 0x08 */
454   __IO uint32_t CWD;   /*!< Calibration Watchdog register,                Address offset: 0x0C */
455   __IO uint32_t IR;    /*!< CCU Interrupt register,                       Address offset: 0x10 */
456   __IO uint32_t IE;    /*!< CCU Interrupt Enable register,                Address offset: 0x14 */
457 } FDCAN_ClockCalibrationUnit_TypeDef;
458 
459 /**
460   * @brief Consumer Electronics Control
461   */
462 
463 typedef struct
464 {
465   __IO uint32_t CR;           /*!< CEC control register,               Address offset: 0x000 */
466   __IO uint32_t CFGR;         /*!< CEC configuration register,         Address offset: 0x004 */
467   __IO uint32_t TXDR;         /*!< CEC Tx data register ,              Address offset: 0x008 */
468   __IO uint32_t RXDR;         /*!< CEC Rx Data Register,               Address offset: 0x00C */
469   __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register,  Address offset: 0x010 */
470   __IO uint32_t IER;          /*!< CEC interrupt enable register,      Address offset: 0x014 */
471   uint32_t  RESERVED3[247];   /*!< Reserved,                                   0x018 - 0x3F0 */
472   __IO uint32_t VERR;         /*!< CEC version register,               Address offset: 0x3F4 */
473   __IO uint32_t IPIDR;        /*!< CEC ID register,                    Address offset: 0x3F8 */
474   __IO uint32_t SIDR;         /*!< CEC Size ID register,               Address offset: 0x3FC */
475 }CEC_TypeDef;
476 
477 /**
478   * @brief CRC calculation unit
479   */
480 
481 typedef struct
482 {
483   __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x000 */
484   __IO uint32_t IDR;         /*!< CRC Independent data register,               Address offset: 0x004 */
485   __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x008 */
486   uint32_t      RESERVED2;   /*!< Reserved,                                                    0x00C */
487   __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x010 */
488   __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x014 */
489   uint32_t      RESERVED3[247];   /*!< Reserved,                                       0x018 - 0x3F0 */
490   __IO uint32_t VERR;        /*!< CRC version register,                        Address offset: 0x3F4 */
491   __IO uint32_t IPIDR;       /*!< CRC ID register,                             Address offset: 0x3F8 */
492   __IO uint32_t SIDR;        /*!< CRC Size ID register,                        Address offset: 0x3FC */
493 } CRC_TypeDef;
494 
495 
496 /**
497   * @brief Clock Recovery System
498   */
499 typedef struct
500 {
501   __IO uint32_t CR;            /*!< CRS ccontrol register,              Address offset: 0x00 */
502   __IO uint32_t CFGR;          /*!< CRS configuration register,         Address offset: 0x04 */
503   __IO uint32_t ISR;           /*!< CRS interrupt and status register,  Address offset: 0x08 */
504   __IO uint32_t ICR;           /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
505 } CRS_TypeDef;
506 
507 
508 /**
509   * @brief Digital to Analog Converter
510   */
511 
512 typedef struct
513 {
514   __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
515   __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
516   __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
517   __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
518   __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
519   __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
520   __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
521   __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
522   __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
523   __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
524   __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
525   __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
526   __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
527   __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
528   __IO uint32_t CCR;      /*!< DAC calibration control register,                        Address offset: 0x38 */
529   __IO uint32_t MCR;      /*!< DAC mode control register,                               Address offset: 0x3C */
530   __IO uint32_t SHSR1;    /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */
531   __IO uint32_t SHSR2;    /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */
532   __IO uint32_t SHHR;     /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */
533   __IO uint32_t SHRR;     /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */
534   uint32_t    RESERVED0[232];  /*!< Reserved,                                           Address offset: 0x50 - 0x3EC */
535   __IO uint32_t HWCFGR0;  /*!< DAC x IP hardware configuration register,                Address offset: 0x3F0 */
536   __IO uint32_t VERR;      /*!< DAC version register,                                    Address offset: 0x3F4 */
537   __IO uint32_t IPIDR;       /*!< DAC ID register,                                      Address offset: 0x3F8 */
538   __IO uint32_t SIDR;        /*!< DAC magic ID register,                                Address offset: 0x3FC */
539 } DAC_TypeDef;
540 
541 /**
542   * @brief DFSDM module registers
543   */
544 typedef struct
545 {
546   __IO uint32_t FLTCR1;      /*!< DFSDM control register1,                          Address offset: 0x100 */
547   __IO uint32_t FLTCR2;      /*!< DFSDM control register2,                          Address offset: 0x104 */
548   __IO uint32_t FLTISR;      /*!< DFSDM interrupt and status register,              Address offset: 0x108 */
549   __IO uint32_t FLTICR;      /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */
550   __IO uint32_t FLTJCHGR;    /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */
551   __IO uint32_t FLTFCR;      /*!< DFSDM filter control register,                    Address offset: 0x114 */
552   __IO uint32_t FLTJDATAR;   /*!< DFSDM data register for injected group,           Address offset: 0x118 */
553   __IO uint32_t FLTRDATAR;   /*!< DFSDM data register for regular group,            Address offset: 0x11C */
554   __IO uint32_t FLTAWHTR;    /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */
555   __IO uint32_t FLTAWLTR;    /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */
556   __IO uint32_t FLTAWSR;     /*!< DFSDM analog watchdog status register             Address offset: 0x128 */
557   __IO uint32_t FLTAWCFR;    /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */
558   __IO uint32_t FLTEXMAX;    /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */
559   __IO uint32_t FLTEXMIN;    /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */
560   __IO uint32_t FLTCNVTIMR;  /*!< DFSDM conversion timer,                           Address offset: 0x138 */
561 } DFSDM_Filter_TypeDef;
562 
563 /**
564   * @brief DFSDM channel configuration registers
565   */
566 typedef struct
567 {
568   __IO uint32_t CHCFGR1;     /*!< DFSDM channel configuration register1,            Address offset: 0x00 */
569   __IO uint32_t CHCFGR2;     /*!< DFSDM channel configuration register2,            Address offset: 0x04 */
570   __IO uint32_t CHAWSCDR;    /*!< DFSDM channel analog watchdog and
571                                   short circuit detector register,                  Address offset: 0x08 */
572   __IO uint32_t CHWDATAR;    /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */
573   __IO uint32_t CHDATINR;    /*!< DFSDM channel data input register,                Address offset: 0x10 */
574   __IO uint32_t CHDLYR;      /*!< DFSDM channel delay register,                     Address offset: 0x14 */
575 } DFSDM_Channel_TypeDef;
576 
577 
578 /**
579   * @brief DFSDM registers
580   */
581 typedef struct
582 {
583   uint32_t RESERVED[508];/*!< Reserved,                                       0x000 - 0x7F0 */
584   __IO uint32_t HWCFGR;  /*!< DFSDM HW Configuration register ,       Address offset: 0x7F0 */
585   __IO uint32_t VERR;    /*!< DFSDM Version register,                 Address offset: 0x7F4 */
586   __IO uint32_t IPDR;    /*!< DFSDM Identification register,          Address offset: 0x7F8 */
587   __IO uint32_t SIDR;    /*!< DFSDM Size Identification register,     Address offset: 0x7FC */
588 } DFSDM_TypeDef;
589 
590 
591 /**
592   * @brief Debug MCU
593   */
594 
595 typedef struct
596 {
597   __IO uint32_t IDCODE;        /*!< MCU device ID code,                         Address offset: 0x00 */
598   __IO uint32_t CR;            /*!< Debug MCU configuration register,           Address offset: 0x04 */
599   __IO uint32_t RESERVED4[9];  /*!< Reserved,                                   Address offset: 0x08 */
600   __IO uint32_t APB4FZ1;       /*!< Debug MCU APB4FZ1 freeze register CPU1,     Address offset: 0x2C */
601   __IO uint32_t APB4FZ2;       /*!< Debug MCU APB4FZ2 freeze register CPU2,     Address offset: 0x30 */
602   __IO uint32_t APB1FZ1;       /*!< Debug MCU APB1FZ1 freeze register CPU1,     Address offset: 0x34 */
603   __IO uint32_t APB1FZ2;       /*!< Debug MCU APB1FZ2 freeze register CPU2,     Address offset: 0x38 */
604   __IO uint32_t APB2FZ1;       /*!< Debug MCU APB2FZ1 freeze register CPU1,     Address offset: 0x3C */
605   __IO uint32_t APB2FZ2;       /*!< Debug MCU APB2FZ2 freeze register CPU2,     Address offset: 0x40 */
606   __IO uint32_t APB3FZ1;       /*!< Debug MCU APB3FZ1 freeze register CPU1,     Address offset: 0x44 */
607   __IO uint32_t APB3FZ2;       /*!< Debug MCU APB3FZ2 freeze register CPU2,     Address offset: 0x48 */
608   __IO uint32_t APB5FZ1;       /*!< Debug MCU APB5FZ1 freeze register CPU1,     Address offset: 0x4C */
609   __IO uint32_t APB5FZ2;       /*!< Debug MCU APB5FZ2 freeze register CPU2,     Address offset: 0x50 */
610 }DBGMCU_TypeDef;
611 
612 /**
613   * @brief DCMI
614   */
615 
616 typedef struct
617 {
618   __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x000 */
619   __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x004 */
620   __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x008 */
621   __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x00C */
622   __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x010 */
623   __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x014 */
624   __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x018 */
625   __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x01C */
626   __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x020 */
627   __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x024 */
628   __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x028 */
629   uint32_t RESERVED[242]; /*!< Reserved,                                              0x02C - 0x3F0 */
630   __IO uint32_t VERR;     /*!< DCMI Version register,                         Address offset: 0x3F4 */
631   __IO uint32_t IPDR;     /*!< DCMI Identification register,                  Address offset: 0x3F8 */
632   __IO uint32_t SIDR;     /*!< DCMI Size Identification register,             Address offset: 0x3FC */
633 } DCMI_TypeDef;
634 
635 /**
636   * @brief DMA Controller
637   */
638 
639 typedef struct
640 {
641   __IO uint32_t CR;     /*!< DMA stream x configuration register      */
642   __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
643   __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
644   __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
645   __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
646   __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
647 } DMA_Stream_TypeDef;
648 
649 typedef struct
650 {
651   __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
652   __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
653   __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
654   __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
655   __IO uint32_t RESERVED[247];  /*!< Reserved,               Address offset: 0x10 - 0x3E8 */
656   __IO uint32_t HWCFGR2; /*!< DMA HW Configuration register 2,      Address offset: 0x3EC */
657   __IO uint32_t HWCFGR1; /*!< DMA HW Configuration register 1,      Address offset: 0x3F0 */
658   __IO uint32_t VERR;    /*!< DMA Version register,                 Address offset: 0x3F4 */
659   __IO uint32_t IPDR;    /*!< DMA Identification register,          Address offset: 0x3F8 */
660   __IO uint32_t SIDR;    /*!< DMA Size Identification register,     Address offset: 0x3FC */
661 } DMA_TypeDef;
662 
663 typedef struct
664 {
665   __IO uint32_t  CCR;        /*!< DMA Multiplexer Channel x Control Register   */
666 }DMAMUX_Channel_TypeDef;
667 
668 typedef struct
669 {
670   __IO uint32_t  CSR;      /*!< DMA Channel Status Register     */
671   __IO uint32_t  CFR;      /*!< DMA Channel Clear Flag Register */
672 }DMAMUX_ChannelStatus_TypeDef;
673 
674 typedef struct
675 {
676   __IO uint32_t  RGCR;        /*!< DMA Request Generator x Control Register   */
677 }DMAMUX_RequestGen_TypeDef;
678 
679 typedef struct
680 {
681   __IO uint32_t  RGSR;            /*!< DMAMUX Request Generator Status Register,           Address offset: 0x140 */
682   __IO uint32_t  RGCFR;           /*!< DMAMUX Request Generator Clear Flag Register,       Address offset: 0x144 */
683   uint32_t       RESERVED0[169];  /*!< Reserved, 0x144 -> 0x144                                                  */
684   __IO uint32_t  HWCFGR2;         /*!< DMAMUX Configuration register 2,                    Address offset: 0x3EC */
685   __IO uint32_t  HWCFGR1;         /*!< DMAMUX Configuration register 1,                    Address offset: 0x3F0 */
686   __IO uint32_t  VERR;            /*!< DMAMUX Verion Register,                             Address offset: 0x3F4 */
687   __IO uint32_t  IPDR;            /*!< DMAMUX Identification register,                     Address offset: 0x3F8 */
688   __IO uint32_t  SIDR;            /*!< DMAMUX Size Identification register,                Address offset: 0x3FC */
689 
690 }DMAMUX_RequestGenStatus_TypeDef;
691 
692 /**
693   * @brief MDMA Controller
694   */
695 typedef struct
696 {
697   __IO uint32_t  GISR0;   /*!< MDMA Global Interrupt/Status Register 0,          Address offset: 0x000 */
698   uint32_t RESERVED1;      /*!< Reserved,                                                         0x004 */
699 //  __IO uint32_t  GISR1;   /*!< MDMA Global Interrupt/Status Register 1,          Address offset: 0x004 */
700   __IO uint32_t  SGISR0;  /*!< MDMA Secure Global Interrupt/Status Register 0,   Address offset: 0x008 */
701 //  __IO uint32_t  SGISR1;  /*!< MDMA Secure Global Interrupt/Status Register 1,   Address offset: 0x00C */
702   uint32_t RESERVED2[250]; /*!< Reserved,                                                  0x10 - 0x3F0 */
703   __IO uint32_t  VERR;    /*!< MDMA Verion Register,                             Address offset: 0x3F4 */
704   __IO uint32_t  IPDR;    /*!< MDMA Identification register,                     Address offset: 0x3F8 */
705   __IO uint32_t  SIDR;    /*!< MDMA Size Identification register,                Address offset: 0x3FC */
706 }MDMA_TypeDef;
707 
708 typedef struct
709 {
710   __IO uint32_t  CISR;      /*!< MDMA channel x interrupt/status register,             Address offset: 0x40 */
711   __IO uint32_t  CIFCR;     /*!< MDMA channel x interrupt flag clear register,         Address offset: 0x44 */
712   __IO uint32_t  CESR;      /*!< MDMA Channel x error status register,                 Address offset: 0x48 */
713   __IO uint32_t  CCR;       /*!< MDMA channel x control register,                      Address offset: 0x4C */
714   __IO uint32_t  CTCR;      /*!< MDMA channel x Transfer Configuration register,       Address offset: 0x50 */
715   __IO uint32_t  CBNDTR;    /*!< MDMA Channel x block number of data register,         Address offset: 0x54 */
716   __IO uint32_t  CSAR;      /*!< MDMA channel x source address register,               Address offset: 0x58 */
717   __IO uint32_t  CDAR;      /*!< MDMA channel x destination address register,          Address offset: 0x5C */
718   __IO uint32_t  CBRUR;     /*!< MDMA channel x Block Repeat address Update register,  Address offset: 0x60 */
719   __IO uint32_t  CLAR;      /*!< MDMA channel x Link Address register,                 Address offset: 0x64 */
720   __IO uint32_t  CTBR;      /*!< MDMA channel x Trigger and Bus selection Register,    Address offset: 0x68 */
721   uint32_t       RESERVED0; /*!< Reserved, 0x68                                                             */
722  __IO uint32_t    CMAR;      /*!< MDMA channel x Mask address register,                Address offset: 0x70 */
723  __IO uint32_t   CMDR;       /*!< MDMA channel x Mask Data register,                   Address offset: 0x74 */
724 }MDMA_Channel_TypeDef;
725 
726 /**
727   * @brief DSI Controller
728   */
729 
730 typedef struct
731 {
732   __IO uint32_t VR;            /*!< DSI Host Version Register,                                 Address offset: 0x00      */
733   __IO uint32_t CR;            /*!< DSI Host Control Register,                                 Address offset: 0x04      */
734   __IO uint32_t CCR;           /*!< DSI HOST Clock Control Register,                           Address offset: 0x08      */
735   __IO uint32_t LVCIDR;        /*!< DSI Host LTDC VCID Register,                               Address offset: 0x0C      */
736   __IO uint32_t LCOLCR;        /*!< DSI Host LTDC Color Coding Register,                       Address offset: 0x10      */
737   __IO uint32_t LPCR;          /*!< DSI Host LTDC Polarity Configuration Register,             Address offset: 0x14      */
738   __IO uint32_t LPMCR;         /*!< DSI Host Low-Power Mode Configuration Register,            Address offset: 0x18      */
739   uint32_t      RESERVED0[4];  /*!< Reserved, 0x1C - 0x2B                                                                */
740   __IO uint32_t PCR;           /*!< DSI Host Protocol Configuration Register,                  Address offset: 0x2C      */
741   __IO uint32_t GVCIDR;        /*!< DSI Host Generic VCID Register,                            Address offset: 0x30      */
742   __IO uint32_t MCR;           /*!< DSI Host Mode Configuration Register,                      Address offset: 0x34      */
743   __IO uint32_t VMCR;          /*!< DSI Host Video Mode Configuration Register,                Address offset: 0x38      */
744   __IO uint32_t VPCR;          /*!< DSI Host Video Packet Configuration Register,              Address offset: 0x3C      */
745   __IO uint32_t VCCR;          /*!< DSI Host Video Chunks Configuration Register,              Address offset: 0x40      */
746   __IO uint32_t VNPCR;         /*!< DSI Host Video Null Packet Configuration Register,         Address offset: 0x44      */
747   __IO uint32_t VHSACR;        /*!< DSI Host Video HSA Configuration Register,                 Address offset: 0x48      */
748   __IO uint32_t VHBPCR;        /*!< DSI Host Video HBP Configuration Register,                 Address offset: 0x4C      */
749   __IO uint32_t VLCR;          /*!< DSI Host Video Line Configuration Register,                Address offset: 0x50      */
750   __IO uint32_t VVSACR;        /*!< DSI Host Video VSA Configuration Register,                 Address offset: 0x54      */
751   __IO uint32_t VVBPCR;        /*!< DSI Host Video VBP Configuration Register,                 Address offset: 0x58      */
752   __IO uint32_t VVFPCR;        /*!< DSI Host Video VFP Configuration Register,                 Address offset: 0x5C      */
753   __IO uint32_t VVACR;         /*!< DSI Host Video VA Configuration Register,                  Address offset: 0x60      */
754   __IO uint32_t LCCR;          /*!< DSI Host LTDC Command Configuration Register,              Address offset: 0x64      */
755   __IO uint32_t CMCR;          /*!< DSI Host Command Mode Configuration Register,              Address offset: 0x68      */
756   __IO uint32_t GHCR;          /*!< DSI Host Generic Header Configuration Register,            Address offset: 0x6C      */
757   __IO uint32_t GPDR;          /*!< DSI Host Generic Payload Data Register,                    Address offset: 0x70      */
758   __IO uint32_t GPSR;          /*!< DSI Host Generic Packet Status Register,                   Address offset: 0x74      */
759   __IO uint32_t TCCR[6];       /*!< DSI Host Timeout Counter Configuration Register,           Address offset: 0x78-0x8F */
760   __IO uint32_t TDCR;          /*!< DSI Host 3D Configuration Register,                        Address offset: 0x90      */
761   __IO uint32_t CLCR;          /*!< DSI Host Clock Lane Configuration Register,                Address offset: 0x94      */
762   __IO uint32_t CLTCR;         /*!< DSI Host Clock Lane Timer Configuration Register,          Address offset: 0x98      */
763   __IO uint32_t DLTCR;         /*!< DSI Host Data Lane Timer Configuration Register,           Address offset: 0x9C      */
764   __IO uint32_t PCTLR;         /*!< DSI Host PHY Control Register,                             Address offset: 0xA0      */
765   __IO uint32_t PCONFR;        /*!< DSI Host PHY Configuration Register,                       Address offset: 0xA4      */
766   __IO uint32_t PUCR;          /*!< DSI Host PHY ULPS Control Register,                        Address offset: 0xA8      */
767   __IO uint32_t PTTCR;         /*!< DSI Host PHY TX Triggers Configuration Register,           Address offset: 0xAC      */
768   __IO uint32_t PSR;           /*!< DSI Host PHY Status Register,                              Address offset: 0xB0      */
769   uint32_t      RESERVED1[2];  /*!< Reserved, 0xB4 - 0xBB                                                                */
770   __IO uint32_t ISR[2];        /*!< DSI Host Interrupt & Status Register,                      Address offset: 0xBC-0xC3 */
771   __IO uint32_t IER[2];        /*!< DSI Host Interrupt Enable Register,                        Address offset: 0xC4-0xCB */
772   uint32_t      RESERVED2[3];  /*!< Reserved, 0xD0 - 0xD7                                                                */
773   __IO uint32_t FIR[2];        /*!< DSI Host Force Interrupt Register,                         Address offset: 0xD8-0xDF */
774   uint32_t      RESERVED3[5];  /*!< Reserved, 0xE0 - 0xF3                                                                */
775   __IO uint32_t DLTRCR;        /*!< DSI Host Data Lane Timer Read Configuration Register,      Address offset: 0xF4      */
776   uint32_t      RESERVED4[2];  /*!< Reserved, 0xF8 - 0xFF                                                                */
777   __IO uint32_t VSCR;          /*!< DSI Host Video Shadow Control Register,                    Address offset: 0x100     */
778   uint32_t      RESERVED5[2];  /*!< Reserved, 0x104 - 0x10B                                                              */
779   __IO uint32_t LCVCIDR;       /*!< DSI Host LTDC Current VCID Register,                       Address offset: 0x10C     */
780   __IO uint32_t LCCCR;         /*!< DSI Host LTDC Current Color Coding Register,               Address offset: 0x110     */
781   uint32_t      RESERVED6;     /*!< Reserved, 0x114                                                                      */
782   __IO uint32_t LPMCCR;        /*!< DSI Host Low-power Mode Current Configuration Register,    Address offset: 0x118     */
783   uint32_t      RESERVED7[7];  /*!< Reserved, 0x11C - 0x137                                                              */
784   __IO uint32_t VMCCR;         /*!< DSI Host Video Mode Current Configuration Register,        Address offset: 0x138     */
785   __IO uint32_t VPCCR;         /*!< DSI Host Video Packet Current Configuration Register,      Address offset: 0x13C     */
786   __IO uint32_t VCCCR;         /*!< DSI Host Video Chuncks Current Configuration Register,     Address offset: 0x140     */
787   __IO uint32_t VNPCCR;        /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144     */
788   __IO uint32_t VHSACCR;       /*!< DSI Host Video HSA Current Configuration Register,         Address offset: 0x148     */
789   __IO uint32_t VHBPCCR;       /*!< DSI Host Video HBP Current Configuration Register,         Address offset: 0x14C     */
790   __IO uint32_t VLCCR;         /*!< DSI Host Video Line Current Configuration Register,        Address offset: 0x150     */
791   __IO uint32_t VVSACCR;       /*!< DSI Host Video VSA Current Configuration Register,         Address offset: 0x154     */
792   __IO uint32_t VVBPCCR;       /*!< DSI Host Video VBP Current Configuration Register,         Address offset: 0x158     */
793   __IO uint32_t VVFPCCR;       /*!< DSI Host Video VFP Current Configuration Register,         Address offset: 0x15C     */
794   __IO uint32_t VVACCR;        /*!< DSI Host Video VA Current Configuration Register,          Address offset: 0x160     */
795   uint32_t      RESERVED8[11]; /*!< Reserved, 0x164 - 0x18F                                                              */
796   __IO uint32_t TDCCR;         /*!< DSI Host 3D Current Configuration Register,                Address offset: 0x190     */
797   uint32_t      RESERVED9[155]; /*!< Reserved, 0x194 - 0x3FF                                                             */
798   __IO uint32_t WCFGR;          /*!< DSI Wrapper Configuration Register,                       Address offset: 0x400     */
799   __IO uint32_t WCR;            /*!< DSI Wrapper Control Register,                             Address offset: 0x404     */
800   __IO uint32_t WIER;           /*!< DSI Wrapper Interrupt Enable Register,                    Address offset: 0x408     */
801   __IO uint32_t WISR;           /*!< DSI Wrapper Interrupt and Status Register,                Address offset: 0x40C     */
802   __IO uint32_t WIFCR;          /*!< DSI Wrapper Interrupt Flag Clear Register,                Address offset: 0x410     */
803   uint32_t      RESERVED10;     /*!< Reserved, 0x414                                                                     */
804   __IO uint32_t WPCR[2];        /*!< DSI Wrapper PHY Configuration Register,                   Address offset: 0x418-41C */
805   uint32_t      RESERVED11[4];  /*!< Reserved, 0x420 - 0x42F                                                             */
806   __IO uint32_t WRPCR;          /*!< DSI Wrapper Regulator and PLL Control Register,           Address offset: 0x430     */
807   uint32_t      RESERVED12[239];  /*!< Reserved, 0x434 - 0x7EC                                                           */
808   __IO uint32_t HWCFGR;         /*!< DSI Host hardware configuration register,                 Address offset: 0x7F0     */
809   __IO uint32_t VERR;           /*!< DSI Host version register,                                Address offset: 0x7F4     */
810   __IO uint32_t IPIDR;          /*!< DSI Host Identification register,                         Address offset: 0x7F8     */
811   __IO uint32_t SIDR;           /*!< DSI Host Size ID register,                                Address offset: 0x7FC     */
812 } DSI_TypeDef;
813 
814 /**
815   * @brief Ethernet MAC
816   */
817 typedef struct
818 {
819   __IO uint32_t MACCR;            /*!< Operating mode configuration register                      Address offset: 0x0000 */
820   __IO uint32_t MACECR;           /*!< Extended operating mode configuration register             Address offset: 0x0004 */
821   __IO uint32_t MACPFR;           /*!< Packet filtering control register                          Address offset: 0x0008 */
822   __IO uint32_t MACWTR;           /*!< Watchdog timeout register                                  Address offset: 0x000C */
823   __IO uint32_t MACHT0R;          /*!< Hash Table 0 register                                      Address offset: 0x0010 */
824   __IO uint32_t MACHT1R;          /*!< Hash Table 1 register                                      Address offset: 0x0014 */
825        uint32_t RESERVED0[14];    /*!< Reserved                                                   Address offset: 0x0018-0x004C */
826   __IO uint32_t MACVTR;           /*!< VLAN tag register                                          Address offset: 0x0050 */
827        uint32_t RESERVED1;        /*!< Reserved                                                   Address offset: 0x0054 */
828   __IO uint32_t MACVHTR;          /*!< VLAN Hash table register                                   Address offset: 0x0058 */
829        uint32_t RESERVED2;        /*!< Reserved                                                   Address offset: 0x005C */
830   __IO uint32_t MACVIR;           /*!< VLAN inclusion register                                    Address offset: 0x0060 */
831   __IO uint32_t MACIVIR;          /*!< Inner VLAN inclusion register                              Address offset: 0x0064 */
832        uint32_t RESERVED3[2];     /*!< Reserved                                                   Address offset: 0x0068-0x006C */
833   __IO uint32_t MACQ0TXFCR;       /*!< Tx Queue 0 flow control register                           Address offset: 0x0070 */
834        uint32_t RESERVED4[7];     /*!< Reserved                                                   Address offset: 0x0074-0x008C */
835   __IO uint32_t MACRXFCR;         /*!< Rx flow control register                                   Address offset: 0x0090 */
836        uint32_t RESERVED5;        /*!< Reserved                                                   Address offset: 0x0094 */
837   __IO uint32_t MACTXQPMR;        /*!< Tx queue priority mapping 0 register                       Address offset: 0x0098 */
838        uint32_t RESERVED6;        /*!< Reserved                                                   Address offset: 0x009C */
839   __IO uint32_t MACRXQC0R;        /*!< Rx queue control 0 register                                Address offset: 0x00A0 */
840   __IO uint32_t MACRXQC1R;        /*!< Rx queue control 1 register                                Address offset: 0x00A4 */
841   __IO uint32_t MACRXQC2R;        /*!< Rx queue control 2 register                                Address offset: 0x00A8 */
842        uint32_t RESERVED7;        /*!< Reserved                                                   Address offset: 0x00AC */
843   __IO uint32_t MACISR;           /*!< Interrupt status register                                  Address offset: 0x00B0 */
844   __IO uint32_t MACIER;           /*!< Interrupt enable register                                  Address offset: 0x00B4 */
845   __IO uint32_t MACRXTXSR;        /*!< Rx Tx status register                                      Address offset: 0x00B8 */
846        uint32_t RESERVED8;        /*!< Reserved                                                   Address offset: 0x00BC */
847   __IO uint32_t MACPCSR;          /*!< PMT control status register                                Address offset: 0x00C0 */
848   __IO uint32_t MACRWKPFR;        /*!< Remote wakeup packet filter register                       Address offset: 0x00C4 */
849        uint32_t RESERVED9[2];     /*!< Reserved                                                   Address offset: 0x00C8-0x00CC */
850   __IO uint32_t MACLCSR;          /*!< LPI control status register                                Address offset: 0x00D0 */
851   __IO uint32_t MACLTCR;          /*!< LPI timers control register                                Address offset: 0x00D4 */
852   __IO uint32_t MACLETR;          /*!< LPI entry timer register                                   Address offset: 0x00D8 */
853   __IO uint32_t MAC1USTCR;        /*!< microsecond-tick counter register                          Address offset: 0x00DC */
854        uint32_t RESERVED10[6];    /*!< Reserved                                                   Address offset: 0x00E0-0x00F4 */
855   __IO uint32_t MACPHYCSR;        /*!< PHYIF control status register                              Address offset: 0x00F8 */
856        uint32_t RESERVED11[5];    /*!< Reserved                                                   Address offset: 0x00FC-0x010C */
857   __IO uint32_t MACVR;            /*!< Version register                                           Address offset: 0x0110 */
858   __IO uint32_t MACDR;            /*!< Debug register                                             Address offset: 0x0114 */
859        uint32_t RESERVED12[2];    /*!< Reserved                                                   Address offset: 0x0118-0x011C */
860   __IO uint32_t MACHWF1R;         /*!< HW feature 1 register                                      Address offset: 0x0120 */
861   __IO uint32_t MACHWF2R;         /*!< HW feature 2 register                                      Address offset: 0x0124 */
862        uint32_t RESERVED13[54];   /*!< Reserved                                                   Address offset: 0x0128-0x01FC */
863   __IO uint32_t MACMDIOAR;        /*!< MDIO address register                                      Address offset: 0x0200 */
864   __IO uint32_t MACMDIODR;        /*!< MDIO data register                                         Address offset: 0x0204 */
865        uint32_t RESERVED14[62];   /*!< Reserved                                                   Address offset: 0x0208-0x02FC */
866   __IO uint32_t MACA0HR;          /*!< Address 0 high register                                    Address offset: 0x0300 */
867   __IO uint32_t MACA0LR;          /*!< Address 0 low register                                     Address offset: 0x0304 */
868   __IO uint32_t MACA1HR;          /*!< Address 1 high register                                    Address offset: 0x0308 */
869   __IO uint32_t MACA1LR;          /*!< Address 1 low register                                     Address offset: 0x030C */
870   __IO uint32_t MACA2HR;          /*!< Address 2 high register                                    Address offset: 0x0310 */
871   __IO uint32_t MACA2LR;          /*!< Address 2 low register                                     Address offset: 0x0314 */
872   __IO uint32_t MACA3HR;          /*!< Address 3 high register                                    Address offset: 0x0318 */
873   __IO uint32_t MACA3LR;          /*!< Address 3 low register                                     Address offset: 0x031C */
874        uint32_t RESERVED15[248];  /*!< Reserved                                                   Address offset: 0x0320-0x06FC */
875   __IO uint32_t MMCCR;            /*!< MMC control register                                       Address offset: 0x0700 */
876   __IO uint32_t MMCRXIR;          /*!< MMC Rx interrupt register                                  Address offset: 0x704 */
877   __IO uint32_t MMCTXIR;          /*!< MMC Tx interrupt register                                  Address offset: 0x708 */
878   __IO uint32_t MMCRXIMR;         /*!< MMC Rx interrupt mask register                             Address offset: 0x70C */
879   __IO uint32_t MMCTXIMR;         /*!< MMC Tx interrupt mask register                      Address offset: 0x710 */
880        uint32_t RESERVED16[14];   /*!< Reserved                                                    Address offset: 0x0714-0x0748 */
881   __IO uint32_t MMCTXSCGPR;       /*!< Tx single collision good packets register      Address offset: 0x74C */
882   __IO uint32_t MMCTXMCGPR;       /*!< Tx multiple collision good packets register  Address offset: 0x750 */
883        uint32_t RESERVED16_1[5];  /*!< Reserved                                                   Address offset: 0x0754-0x0764 */
884   __IO uint32_t MMCTXPCGR;        /*!< Tx packet count good register                     Address offset: 0x768 */
885        uint32_t RESERVED16_2[10]; /*!< Reserved                                                  Address offset: 0x076C-0x0790 */
886   __IO uint32_t MMCRXCRCEPR;      /*!< Rx CRC error packets register                   Address offset: 0x794 */
887   __IO uint32_t MMCRXAEPR;        /*!< Rx alignment error packets register         Address offset: 0x798 */
888        uint32_t RESERVED16_3[10]; /*!< Reserved                                                  Address offset: 0x079C-0x07C0 */
889   __IO uint32_t MMCRXUPGR;        /*!< Rx unicast packets good register               Address offset: 0x7C4 */
890        uint32_t RESERVED16_4[9];  /*!< Reserved                                                   Address offset: 0x07C8-0x07E8 */
891   __IO uint32_t MMCTXLPIMSTR;     /*!< Tx LPI microsecond timer register                     Address offset: 0x7EC */
892   __IO uint32_t MMCTXLPITCR;      /*!< Tx LPI transition counter register                    Address offset: 0x7F0 */
893   __IO uint32_t MMCRXLPIMSTR;     /*!< Rx LPI microsecond counter register                   Address offset: 0x7F4 */
894   __IO uint32_t MMCRXLPITCR;  /*!< Rx LPI transition counter register                    Address offset: 0x7F8 */
895        uint32_t RESERVED16_5[65];  /*!< Reserved                                                  Address offset: 0x07FC-0x08FC */
896   __IO uint32_t MACL3L4C0R;       /*!< L3 and L4 control 0 register                               Address offset: 0x0900 */
897   __IO uint32_t MACL4A0R;         /*!< Layer4 address filter 0 register                           Address offset: 0x0904 */
898        uint32_t RESERVED17[2];    /*!< Reserved                                                   Address offset: 0x0908-0x090C */
899   __IO uint32_t MACL3A00R;        /*!< Layer 3 Address 0 filter 0 register                        Address offset: 0x0910 */
900   __IO uint32_t MACL3A10R;        /*!< Layer3 address 1 filter 0 register                         Address offset: 0x0914 */
901   __IO uint32_t MACL3A20;         /*!< Layer3 Address 2 filter 0 register                         Address offset: 0x0918 */
902   __IO uint32_t MACL3A30;         /*!< Layer3 Address 3 filter 0 register                         Address offset: 0x091C */
903        uint32_t RESERVED18[4];    /*!< Reserved                                                   Address offset: 0x0920-0x092C */
904   __IO uint32_t MACL3L4C1R;       /*!< L3 and L4 control 1 register                               Address offset: 0x0930 */
905   __IO uint32_t MACL4A1R;         /*!< Layer 4 address filter 1 register                          Address offset: 0x0934 */
906        uint32_t RESERVED19[2];    /*!< Reserved                                                   Address offset: 0x0938-0x093C */
907   __IO uint32_t MACL3A01R;        /*!< Layer3 address 0 filter 1 Register                         Address offset: 0x0940 */
908   __IO uint32_t MACL3A11R;        /*!< Layer3 address 1 filter 1 register                         Address offset: 0x0944 */
909   __IO uint32_t MACL3A21R;        /*!< Layer3 address 2 filter 1 Register                         Address offset: 0x0948 */
910   __IO uint32_t MACL3A31R;        /*!< Layer3 address 3 filter 1 register                         Address offset: 0x094C */
911        uint32_t RESERVED20[100];  /*!< Reserved                                                   Address offset: 0x0950-0x0ADC */
912   __IO uint32_t MACARPAR;         /*!< ARP address register                                       Address offset: 0x0AE0 */
913        uint32_t RESERVED21[7];    /*!< Reserved                                                   Address offset: 0x0AE4-0x0AFC */
914   __IO uint32_t MACTSCR;          /*!< Timestamp control Register                                 Address offset: 0x0B00 */
915   __IO uint32_t MACSSIR;          /*!< Sub-second increment register                              Address offset: 0x0B04 */
916   __IO uint32_t MACSTSR;          /*!< System time seconds register                               Address offset: 0x0B08 */
917   __IO uint32_t MACSTNR;          /*!< System time nanoseconds register                           Address offset: 0x0B0C */
918   __IO uint32_t MACSTSUR;         /*!< System time seconds update register                        Address offset: 0x0B10 */
919   __IO uint32_t MACSTNUR;         /*!< System time nanoseconds update register                    Address offset: 0x0B14 */
920   __IO uint32_t MACTSAR;          /*!< Timestamp addend register                                  Address offset: 0x0B18 */
921        uint32_t RESERVED22;       /*!< Reserved                                                   Address offset: 0x0B1C */
922   __IO uint32_t MACTSSR;          /*!< Timestamp status register                                  Address offset: 0x0B20 */
923        uint32_t RESERVED23[3];    /*!< Reserved                                                   Address offset: 0x0B24-0x0B2C */
924   __IO uint32_t MACTXTSSNR;       /*!< Tx timestamp status nanoseconds register                   Address offset: 0x0B30 */
925   __IO uint32_t MACTXTSSSR;       /*!< Tx timestamp status seconds register                       Address offset: 0x0B34 */
926        uint32_t RESERVED24[2];    /*!< Reserved                                                   Address offset: 0x0B38-0x0B3C */
927   __IO uint32_t MACACR;           /*!< Auxiliary control register                                 Address offset: 0x0B40 */
928        uint32_t RESERVED25;       /*!< Reserved                                                   Address offset: 0x0B44 */
929   __IO uint32_t MACATSNR;         /*!< Auxiliary timestamp nanoseconds register                   Address offset: 0x0B48 */
930   __IO uint32_t MACATSSR;         /*!< Auxiliary timestamp seconds register                       Address offset: 0x0B4C */
931   __IO uint32_t MACTSIACR;        /*!< Timestamp Ingress asymmetric correction register           Address offset: 0x0B50 */
932   __IO uint32_t MACTSEACR;        /*!< Timestamp Egress asymmetric correction register            Address offset: 0x0B54 */
933   __IO uint32_t MACTSICNR;        /*!< Timestamp Ingress correction nanosecond register           Address offset: 0x0B58 */
934   __IO uint32_t MACTSECNR;        /*!< Timestamp Egress correction nanosecond register            Address offset: 0x0B5C */
935        uint32_t RESERVED26[4];    /*!< Reserved                                                   Address offset: 0x0B60-0x0B6C */
936   __IO uint32_t MACPPSCR;         /*!< PPS control register [alternate]                           Address offset: 0x0B70 */
937        uint32_t RESERVED27[3];    /*!< Reserved                                                   Address offset: 0x0B74-0x0B7C */
938   __IO uint32_t MACPPSTTSR;       /*!< PPS target time seconds register                           Address offset: 0x0B80 */
939   __IO uint32_t MACPPSTTNR;       /*!< PPS target time nanoseconds register                       Address offset: 0x0B84 */
940   __IO uint32_t MACPPSIR;         /*!< PPS interval register                                      Address offset: 0x0B88 */
941   __IO uint32_t MACPPSWR;         /*!< PPS width register                                         Address offset: 0x0B8C */
942        uint32_t RESERVED28[12];   /*!< Reserved                                                   Address offset: 0x0B90-0x0BBC */
943   __IO uint32_t MACPOCR;          /*!< PTP Offload control register                               Address offset: 0x0BC0 */
944   __IO uint32_t MACSPI0R;         /*!< PTP Source Port Identity 0 Register                        Address offset: 0x0BC4 */
945   __IO uint32_t MACSPI1R;         /*!< PTP Source port identity 1 register                        Address offset: 0x0BC8 */
946   __IO uint32_t MACSPI2R;         /*!< PTP Source port identity 2 register                        Address offset: 0x0BCC */
947   __IO uint32_t MACLMIR;          /*!< Log message interval register                              Address offset: 0x0BD0 */
948        uint32_t RESERVED29[11];   /*!< Reserved                                                   Address offset: 0x0BD4-0x0BFC */
949   __IO uint32_t MTLOMR;           /*!< Operating mode Register                                    Address offset: 0x0C00 */
950        uint32_t RESERVED30[7];    /*!< Reserved                                                   Address offset: 0x0C04-0x0C1C */
951   __IO uint32_t MTLISR;           /*!< Interrupt status Register                                  Address offset: 0x0C20 */
952        uint32_t RESERVED31[55];   /*!< Reserved                                                   Address offset: 0x0C24-0x0CFC */
953   __IO uint32_t MTLTXQ0OMR;       /*!< Tx queue 0 operating mode Register                         Address offset: 0x0D00 */
954   __IO uint32_t MTLTXQ0UR;        /*!< Tx queue 0 underflow register                              Address offset: 0x0D04 */
955   __IO uint32_t MTLTXQ0DR;        /*!< Tx queue 0 debug Register                                  Address offset: 0x0D08 */
956        uint32_t RESERVED32[2];    /*!< Reserved                                                   Address offset: 0x0D0C-0x0D10 */
957   __IO uint32_t MTLTXQ0ESR;       /*!< Tx queue x ETS status Register                             Address offset: 0x0D14 */
958        uint32_t RESERVED33[5];    /*!< Reserved                                                   Address offset: 0x0D18-0x0D28 */
959   __IO uint32_t MTLQ0ICSR;        /*!< Queue 0 interrupt control status Register                  Address offset: 0x0D2C */
960   __IO uint32_t MTLRXQ0OMR;       /*!< Rx queue 0 operating mode register                         Address offset: 0x0D30 */
961   __IO uint32_t MTLRXQ0MPOCR;     /*!< Rx queue 0 missed packet and overflow counter register     Address offset: 0x0D34 */
962   __IO uint32_t MTLRXQ0DR;        /*!< Rx queue 0 debug register                                  Address offset: 0x0D38 */
963   __IO uint32_t MTLRXQ0CR;        /*!< Rx queue 0 control register                                Address offset: 0x0D3C */
964   __IO uint32_t MTLTXQ1OMR;       /*!< Tx queue 1 operating mode Register                         Address offset: 0x0D40 */
965   __IO uint32_t MTLTXQ1UR;        /*!< Tx queue 1 underflow register                              Address offset: 0x0D44 */
966   __IO uint32_t MTLTXQ1DR;        /*!< Tx queue 1 debug Register                                  Address offset: 0x0D48 */
967        uint32_t RESERVED34;       /*!< Reserved                                                   Address offset: 0x0D4C */
968   __IO uint32_t MTLTXQ1ECR;       /*!< Tx queue 1 ETS control Register                            Address offset: 0x0D50 */
969   __IO uint32_t MTLTXQ1ESR;       /*!< Tx queue x ETS status Register                             Address offset: 0x0D54 */
970   __IO uint32_t MTLTXQ1QWR;       /*!< Tx queue 1 quantum weight register                         Address offset: 0x0D58 */
971   __IO uint32_t MTLTXQ1SSCR;      /*!< Tx queue 1 send slope credit Register                      Address offset: 0x0D5C */
972   __IO uint32_t MTLTXQ1HCR;       /*!< Tx Queue 1 hiCredit register                               Address offset: 0x0D60 */
973   __IO uint32_t MTLTXQ1LCR;       /*!< Tx queue 1 loCredit register                               Address offset: 0x0D64 */
974        uint32_t RESERVED35;       /*!< Reserved                                                   Address offset: 0x0D68 */
975   __IO uint32_t MTLQ1ICSR;        /*!< Queue 1 interrupt control status Register                  Address offset: 0x0D6C */
976   __IO uint32_t MTLRXQ1OMR;       /*!< Rx queue 1 operating mode register                         Address offset: 0x0D70 */
977   __IO uint32_t MTLRXQ1MPOCR;     /*!< Rx queue 1 missed packet and overflow counter register     Address offset: 0x0D74 */
978   __IO uint32_t MTLRXQ1DR;        /*!< Rx queue 1 debug register                                  Address offset: 0x0D78 */
979   __IO uint32_t MTLRXQ1CR;        /*!< Rx queue 1 control register                                Address offset: 0x0D7C */
980        uint32_t RESERVED36[160];  /*!< Reserved                                                   Address offset: 0x0D80-0x0FFC */
981   __IO uint32_t DMAMR;            /*!< DMA mode register                                          Address offset: 0x1000 */
982   __IO uint32_t DMASBMR;          /*!< System bus mode register                                   Address offset: 0x1004 */
983   __IO uint32_t DMAISR;           /*!< Interrupt status register                                  Address offset: 0x1008 */
984   __IO uint32_t DMADSR;           /*!< Debug status register                                      Address offset: 0x100C */
985        uint32_t RESERVED37[4];    /*!< Reserved                                                   Address offset: 0x1010-0x101C */
986   __IO uint32_t DMAA4TXACR;       /*!< AXI4 transmit channel ACE control register                 Address offset: 0x1020 */
987   __IO uint32_t DMAA4RXACR;       /*!< AXI4 receive channel ACE control register                  Address offset: 0x1024 */
988   __IO uint32_t DMAA4DACR;        /*!< AXI4 descriptor ACE control register                       Address offset: 0x1028 */
989        uint32_t RESERVED38[53];   /*!< Reserved                                                   Address offset: 0x102C-0x10FC */
990   __IO uint32_t DMAC0CR;          /*!< Channel 0 control register                                 Address offset: 0x1100 */
991   __IO uint32_t DMAC0TXCR;        /*!< Channel 0 transmit control register                        Address offset: 0x1104 */
992   __IO uint32_t DMAC0RXCR;        /*!< Channel 0 receive control register                         Address offset: 0x1108 */
993        uint32_t RESERVED39[2];    /*!< Reserved                                                   Address offset: 0x110C-0x1110 */
994   __IO uint32_t DMAC0TXDLAR;      /*!< Channel 0 Tx descriptor list address register              Address offset: 0x1114 */
995        uint32_t RESERVED40;       /*!< Reserved                                                   Address offset: 0x1118 */
996   __IO uint32_t DMAC0RXDLAR;      /*!< Channel 0 Rx descriptor list address register              Address offset: 0x111C */
997   __IO uint32_t DMAC0TXDTPR;      /*!< Channel 0 Tx descriptor tail pointer register              Address offset: 0x1120 */
998        uint32_t RESERVED41;       /*!< Reserved                                                   Address offset: 0x1124 */
999   __IO uint32_t DMAC0RXDTPR;      /*!< Channel 0 Rx descriptor tail pointer register              Address offset: 0x1128 */
1000   __IO uint32_t DMAC0TXRLR;       /*!< Channel 0 Tx descriptor ring length register               Address offset: 0x112C */
1001   __IO uint32_t DMAC0RXRLR;       /*!< Channel 0 Rx descriptor ring length register               Address offset: 0x1130 */
1002   __IO uint32_t DMAC0IER;         /*!< Channel 0 interrupt enable register                        Address offset: 0x1134 */
1003   __IO uint32_t DMAC0RXIWTR;      /*!< Channel 0 Rx interrupt watchdog timer register             Address offset: 0x1138 */
1004   __IO uint32_t DMAC0SFCSR;       /*!< Channel 0 slot function control status register            Address offset: 0x113C */
1005        uint32_t RESERVED42;       /*!< Reserved                                                   Address offset: 0x1140 */
1006   __IO uint32_t DMAC0CATXDR;      /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */
1007        uint32_t RESERVED43;       /*!< Reserved                                                   Address offset: 0x1148 */
1008   __IO uint32_t DMAC0CARXDR;      /*!< Channel 0 current application receive descriptor register  Address offset: 0x114C */
1009        uint32_t RESERVED44;       /*!< Reserved                                                   Address offset: 0x1150 */
1010   __IO uint32_t DMAC0CATXBR;      /*!< Channel 0 current application transmit buffer register     Address offset: 0x1154 */
1011        uint32_t RESERVED45;       /*!< Reserved                                                   Address offset: 0x1158 */
1012   __IO uint32_t DMAC0CARXBR;      /*!< Channel 0 current application receive buffer register      Address offset: 0x115C */
1013   __IO uint32_t DMAC0SR;          /*!< Channel 0 status register                                  Address offset: 0x1160 */
1014        uint32_t RESERVED46[2];    /*!< Reserved                                                   Address offset: 0x1164-0x1168 */
1015   __IO uint32_t DMAC0MFCR;        /*!< Channel 0 missed frame count register                      Address offset: 0x116C */
1016        uint32_t RESERVED47[4];    /*!< Reserved                                                   Address offset: 0x1170-0x117C */
1017   __IO uint32_t DMAC1CR;          /*!< Channel 1 control register                                 Address offset: 0x1180 */
1018   __IO uint32_t DMAC1TXCR;        /*!< Channel 1 transmit control register                        Address offset: 0x1184 */
1019        uint32_t RESERVED48[3];    /*!< Reserved                                                   Address offset: 0x1188-0x1190 */
1020   __IO uint32_t DMAC1TXDLAR;      /*!< Channel 1 Tx descriptor list address register              Address offset: 0x1194 */
1021        uint32_t RESERVED49[2];    /*!< Reserved                                                   Address offset: 0x1198-0x119C */
1022   __IO uint32_t DMAC1TXDTPR;      /*!< Channel 1 Tx descriptor tail pointer register              Address offset: 0x11A0 */
1023        uint32_t RESERVED50[2];    /*!< Reserved                                                   Address offset: 0x11A4-0x11A8 */
1024   __IO uint32_t DMAC1TXRLR;       /*!< Channel 1 Tx descriptor ring length register               Address offset: 0x11AC */
1025        uint32_t RESERVED51;       /*!< Reserved                                                   Address offset: 0x11B0 */
1026   __IO uint32_t DMAC1IER;         /*!< Channel 1 interrupt enable register                        Address offset: 0x11B4 */
1027        uint32_t RESERVED52;       /*!< Reserved                                                   Address offset: 0x11B8 */
1028   __IO uint32_t DMAC1SFCSR;       /*!< Channel 1 slot function control status register            Address offset: 0x11BC */
1029        uint32_t RESERVED53;       /*!< Reserved                                                   Address offset: 0x11C0 */
1030   __IO uint32_t DMAC1CATXDR;      /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */
1031        uint32_t RESERVED54[3];    /*!< Reserved                                                   Address offset: 0x11C8-0x11D0 */
1032   __IO uint32_t DMAC1CATXBR;      /*!< Channel 1 current application transmit buffer register     Address offset: 0x11D4 */
1033        uint32_t RESERVED55[2];    /*!< Reserved                                                   Address offset: 0x11D8-0x11DC */
1034   __IO uint32_t DMAC1SR;          /*!< Channel 1 status register                                  Address offset: 0x11E0 */
1035        uint32_t RESERVED56[2];    /*!< Reserved                                                   Address offset: 0x11E4-0x11E8 */
1036   __IO uint32_t DMAC1MFCR;        /*!< Channel 1 missed frame count register                      Address offset: 0x11EC */
1037 } ETH_TypeDef;
1038 
1039 /**
1040   * @brief External Interrupt/Event Controller
1041   */
1042 
1043 typedef struct
1044 {
1045   __IO uint32_t RTSR1;               /*!< EXTI Rising trigger selection register,                   Address offset: 0x00 */
1046   __IO uint32_t FTSR1;               /*!< EXTI Falling trigger selection register,                  Address offset: 0x04 */
1047   __IO uint32_t SWIER1;              /*!< EXTI Software interrupt event register,                   Address offset: 0x08 */
1048   __IO uint32_t RPR1;                /*!< EXTI Rising Edge Pending mask register,                   Address offset: 0x0C */
1049   __IO uint32_t FPR1;                /*!< EXTI Falling Edge Pending mask register,                  Address offset: 0x10 */
1050   __IO uint32_t TZENR1;              /*!< EXTI Trust Zone enable register,                          Address offset: 0x14 */
1051   uint32_t      RESERVED1[2];        /*!< Reserved, offset 0x18 -> 0x20                                                  */
1052   __IO uint32_t RTSR2;               /*!< EXTI Rising trigger selection register,                   Address offset: 0x20 */
1053   __IO uint32_t FTSR2;               /*!< EXTI Falling trigger selection register,                  Address offset: 0x24 */
1054   __IO uint32_t SWIER2;              /*!< EXTI Software interrupt event register,                   Address offset: 0x28 */
1055   __IO uint32_t RPR2;                /*!< EXTI Rising Edge Pending mask register,                   Address offset: 0x2C */
1056   __IO uint32_t FPR2;                /*!< EXTI Falling Edge Pending mask register,                  Address offset: 0x30 */
1057   __IO uint32_t TZENR2;              /*!< EXTI Trust Zone enable register,                          Address offset: 0x34 */
1058   uint32_t      RESERVED2[2];        /*!< Reserved, offset 0x38 -> 0x40                                                  */
1059   __IO uint32_t RTSR3;               /*!< EXTI Rising trigger selection register,                   Address offset: 0x40 */
1060   __IO uint32_t FTSR3;               /*!< EXTI Falling trigger selection register,                  Address offset: 0x44 */
1061   __IO uint32_t SWIER3;              /*!< EXTI Software interrupt event register,                   Address offset: 0x48 */
1062   __IO uint32_t RPR3;                /*!< EXTI Rising Edge Pending mask register,                   Address offset: 0x4C */
1063   __IO uint32_t FPR3;                /*!< EXTI Falling Edge Pending mask register,                  Address offset: 0x50 */
1064   __IO uint32_t TZENR3;              /*!< EXTI Trust Zone enable register,                          Address offset: 0x54 */
1065   uint32_t      RESERVED3[2];        /*!< Reserved, offset 0x58 -> 0x5C                                                  */
1066   __IO uint32_t EXTICR[4];           /*!< EXTI Configuration Register mask register,                Address offset: 0x60 */
1067   uint32_t      RESERVED4[4];        /*!< Reserved, offset 0x70 -> 0x7C                                                  */
1068   __IO uint32_t C1IMR1;              /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */
1069   __IO uint32_t C1EMR1;              /*!< EXTI wakeup with event mask register for cpu1 [31:0],     Address offset: 0x84 */
1070   __IO uint32_t RESERVED5[2];        /*!< Reserved,                                                 Address offset: 0x88 - 0x8C */
1071   __IO uint32_t C1IMR2;              /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */
1072   __IO uint32_t C1EMR2;              /*!< EXTI wakeup with event mask register for cpu1 [31:0],     Address offset: 0x94 */
1073   __IO uint32_t RESERVED6[2];        /*!< Reserved,                                                 Address offset: 0x98 - 0x9C */
1074   __IO uint32_t C1IMR3;              /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */
1075   __IO uint32_t C1EMR3;              /*!< EXTI wakeup with event mask register for cpu1 [31:0],     Address offset: 0xA4 */
1076   __IO uint32_t RESERVED7[6];        /*!< Reserved,                                                 Address offset: 0xA8 - 0xBC */
1077   __IO uint32_t C2IMR1;              /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */
1078   __IO uint32_t C2EMR1;              /*!< EXTI wakeup with event mask register for cpu2 [31:0],     Address offset: 0xC4 */
1079   __IO uint32_t RESERVED8[2];        /*!< Reserved,                                                 Address offset: 0xC8 - 0xCC */
1080   __IO uint32_t C2IMR2;              /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xD0 */
1081   __IO uint32_t C2EMR2;              /*!< EXTI wakeup with event mask register for cpu2 [31:0],     Address offset: 0xD4 */
1082   __IO uint32_t RESERVED9[2];        /*!< Reserved,                                                 Address offset: 0xD8 - 0xDC */
1083   __IO uint32_t C2IMR3;              /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xE0 */
1084   __IO uint32_t C2EMR3;              /*!< EXTI wakeup with event mask register for cpu2 [31:0],     Address offset: 0xE4 */
1085   uint32_t      RESERVED10[182];     /*!< Reserved, offset 0xE8 -> 0x3BC                                                 */
1086   __IO uint32_t HWCFGR13;            /*!< EXTI HW Configuration Register 13,                        Address offset: 0x3C0 */
1087   __IO uint32_t HWCFGR12;            /*!< EXTI HW Configuration Register 12,                        Address offset: 0x3C4 */
1088   __IO uint32_t HWCFGR11;            /*!< EXTI HW Configuration Register 11,                        Address offset: 0x3C8 */
1089   __IO uint32_t HWCFGR10;            /*!< EXTI HW Configuration Register 10,                        Address offset: 0x3CC */
1090   __IO uint32_t HWCFGR9;             /*!< EXTI HW Configuration Register 9,                         Address offset: 0x3D0 */
1091   __IO uint32_t HWCFGR8;             /*!< EXTI HW Configuration Register 8,                         Address offset: 0x3D4 */
1092   __IO uint32_t HWCFGR7;             /*!< EXTI HW Configuration Register 7,                         Address offset: 0x3D8 */
1093   __IO uint32_t HWCFGR6;             /*!< EXTI HW Configuration Register 6,                         Address offset: 0x3DC */
1094   __IO uint32_t HWCFGR5;             /*!< EXTI HW Configuration Register 5,                         Address offset: 0x3E0 */
1095   __IO uint32_t HWCFGR4;             /*!< EXTI HW Configuration Register 4,                         Address offset: 0x3E4 */
1096   __IO uint32_t HWCFGR3;             /*!< EXTI HW Configuration Register 3,                         Address offset: 0x3E8 */
1097   __IO uint32_t HWCFGR2;             /*!< EXTI HW Configuration Register 2,                         Address offset: 0x3EC */
1098   __IO uint32_t HWCFGR1;             /*!< EXTI HW Configuration Register 1,                         Address offset: 0x3F0 */
1099   __IO uint32_t VERR;                /*!< EXTI Version Register ,                                   Address offset: 0x3F4 */
1100   __IO uint32_t IPIDR;               /*!< EXTI Identification Register ,                            Address offset: 0x3F8 */
1101   __IO uint32_t SIDR;                /*!< EXTI Size ID Register ,                                   Address offset: 0x3FC */
1102 
1103 }EXTI_TypeDef;
1104 
1105 typedef struct
1106 {
1107   __IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                Address offset: 0x00 */
1108   __IO uint32_t EMR1;                /*!< EXTI Event mask register,                    Address offset: 0x04 */
1109   uint32_t      RESERVED1[2];        /*!< Reserved, offset 0x08 -> 0x10                                     */
1110   __IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                Address offset: 0x10 */
1111   __IO uint32_t EMR2;                /*!< EXTI Event mask register,                    Address offset: 0x14 */
1112   uint32_t      RESERVED2[2];        /*!< Reserved, offset 0x18 -> 0x20                                     */
1113   __IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                Address offset: 0x20 */
1114   __IO uint32_t EMR3;                /*!< EXTI Event mask register,                    Address offset: 0x24 */
1115   uint32_t      RESERVED3[6];        /*!< Reserved, offset 0x28 -> 0x40                                     */
1116 }EXTI_Core_TypeDef;
1117 
1118 
1119 /**
1120   * @brief Flexible Memory Controller
1121   */
1122 
1123 typedef struct
1124 {
1125   __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
1126   __IO uint32_t PCSCNTR;    /*!< PSRAM chip-select counter register(PCSCNTR),                                      Address offset: 0x20 */
1127 } FMC_Bank1_TypeDef;
1128 
1129 /**
1130   * @brief Flexible Memory Controller Bank1E
1131   */
1132 
1133 typedef struct
1134 {
1135   __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
1136 } FMC_Bank1E_TypeDef;
1137 
1138 /**
1139   * @brief Flexible Memory Controller Bank3
1140   */
1141 
1142 typedef struct
1143 {
1144   __IO uint32_t PCR;         /*!< NAND Flash control register 3,                       Address offset: 0x80 */
1145   __IO uint32_t SR;          /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */
1146   __IO uint32_t PMEM;        /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */
1147   __IO uint32_t PATT;        /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
1148   __IO uint32_t HPR;         /*!< NAND Flash Hamming Parity result registers 3,        Address offset: 0x90 */
1149   __IO uint32_t HECCR;       /*!< NAND Flash Hamming ECC result registers 3,           Address offset: 0x94 */
1150   uint32_t RESERVED[110];    /*!< Reserved, 0x94->0x250 */
1151   __IO uint32_t BCHIER;      /*!< BCH Interrupt Enable Register,                       Address offset: 0x250 */
1152   __IO uint32_t BCHISR;      /*!< BCH Interrupt Status Register,                       Address offset: 0x254 */
1153   __IO uint32_t BCHICR;      /*!< BCH Interrupt Clear Register,                        Address offset: 0x258 */
1154   uint32_t RESERVED1;        /*!< Reserved, 0x25C */
1155   __IO uint32_t BCHPBR1;     /*!< BCH Parity Bits Register 1,                          Address offset: 0x260 */
1156   __IO uint32_t BCHPBR2;     /*!< BCH Parity Bits Register 2,                          Address offset: 0x264 */
1157   __IO uint32_t BCHPBR3;     /*!< BCH Parity Bits Register 3,                          Address offset: 0x268 */
1158   __IO uint32_t BCHPBR4;     /*!< BCH Parity Bits Register 4,                          Address offset: 0x26C */
1159   uint32_t RESERVED2[3];        /*!< Reserved, 0x25C */
1160   __IO uint32_t BCHDSR0;     /*!< BCH Decoder Status Register 0,                       Address offset: 0x27C */
1161   __IO uint32_t BCHDSR1;     /*!< BCH Decoder Status Register 1,                       Address offset: 0x280 */
1162   __IO uint32_t BCHDSR2;     /*!< BCH Decoder Status Register 2,                       Address offset: 0x284 */
1163   __IO uint32_t BCHDSR3;     /*!< BCH Decoder Status Register 3,                       Address offset: 0x288 */
1164   __IO uint32_t BCHDSR4;     /*!< BCH Decoder Status Register 4,                       Address offset: 0x28C */
1165   uint32_t RESERVED3[87];    /*!< Reserved, 0x28C->0x3EC */
1166   __IO uint32_t HWCFGR2;     /*!< FMC HW Configuration register 2,                     Address offset: 0x3EC */
1167   __IO uint32_t HWCFGR1;     /*!< FMC HW Configuration register 1,                     Address offset: 0x3F0 */
1168   __IO uint32_t VERR;        /*!< FMC Version register ,                               Address offset: 0x3F4 */
1169   __IO uint32_t IDR;         /*!< FMC Identification register ,                        Address offset: 0x3F8 */
1170   __IO uint32_t SIDR;        /*!< FMC Size ID register ,                               Address offset: 0x3FC */
1171 } FMC_Bank3_TypeDef;
1172 
1173 
1174 /**
1175   * @brief General Purpose I/O
1176   */
1177 
1178 typedef struct
1179 {
1180   __IO uint32_t MODER;           /*!< GPIO port mode register,                      Address offset: 0x000 */
1181   __IO uint32_t OTYPER;          /*!< GPIO port output type register,               Address offset: 0x004 */
1182   __IO uint32_t OSPEEDR;         /*!< GPIO port output speed register,              Address offset: 0x008 */
1183   __IO uint32_t PUPDR;           /*!< GPIO port pull-up/pull-down register,         Address offset: 0x00C */
1184   __IO uint32_t IDR;             /*!< GPIO port input data register,                Address offset: 0x010 */
1185   __IO uint32_t ODR;             /*!< GPIO port output data register,               Address offset: 0x014 */
1186   __IO uint32_t BSRR;            /*!< GPIO port bit set/reset register,             Address offset: 0x018 */
1187   __IO uint32_t LCKR;            /*!< GPIO port configuration lock register,        Address offset: 0x01C */
1188   __IO uint32_t AFR[2];          /*!< GPIO alternate function registers,            Address offset: 0x020-0x024 */
1189   __IO uint32_t BRR;             /*!< GPIO port bit reset register,                 Address offset: 0x028 */
1190        uint32_t RESERVED0;       /*!< Reserved,                                     Address offset: 0x02C */
1191   __IO uint32_t SECCFGR;         /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */
1192        uint32_t RESERVED1[229];  /*!< Reserved,                                     Address offset: 0x034-0x3C4 */
1193   __IO uint32_t HWCFGR10;        /*!< GPIO hardware configuration register 10,      Address offset: 0x3C8 */
1194   __IO uint32_t HWCFGR9;         /*!< GPIO hardware configuration register 9,       Address offset: 0x3CC */
1195   __IO uint32_t HWCFGR8;         /*!< GPIO hardware configuration register 8,       Address offset: 0x3D0 */
1196   __IO uint32_t HWCFGR7;         /*!< GPIO hardware configuration register 7,       Address offset: 0x3D4 */
1197   __IO uint32_t HWCFGR6;         /*!< GPIO hardware configuration register 6,       Address offset: 0x3D8 */
1198   __IO uint32_t HWCFGR5;         /*!< GPIO hardware configuration register 5,       Address offset: 0x3DC */
1199   __IO uint32_t HWCFGR4;         /*!< GPIO hardware configuration register 4,       Address offset: 0x3E0 */
1200   __IO uint32_t HWCFGR3;         /*!< GPIO hardware configuration register 3,       Address offset: 0x3E4 */
1201   __IO uint32_t HWCFGR2;         /*!< GPIO hardware configuration register 2,       Address offset: 0x3E8 */
1202   __IO uint32_t HWCFGR1;         /*!< GPIO hardware configuration register 1,       Address offset: 0x3EC */
1203   __IO uint32_t HWCFGR0;         /*!< GPIO hardware configuration register 0,       Address offset: 0x3F0 */
1204   __IO uint32_t VERR;            /*!< GPIO version register,                        Address offset: 0x3F4 */
1205   __IO uint32_t IPIDR;           /*!< GPIO identification register,                 Address offset: 0x3F8 */
1206   __IO uint32_t SIDR;            /*!< GPIO size identification register,            Address offset: 0x3FC */
1207 } GPIO_TypeDef;
1208 
1209 
1210 /**
1211   * @brief System configuration controller
1212   */
1213 
1214 typedef struct
1215 {
1216   __IO uint32_t BOOTR;          /*!< SYSCFG Boot pin control register,                                Address offset: 0x00        */
1217   __IO uint32_t PMCSETR;        /*!< SYSCFG Peripheral Mode configuration set register,               Address offset: 0x04        */
1218   __IO uint32_t RESERVED1[4];   /*!< Reserved,                                                        Address offset: 0x08-0x18   */
1219   __IO uint32_t IOCTRLSETR;     /*!< SYSCFG ioctl set register,                                       Address offset: 0x18        */
1220   __IO uint32_t ICNR;           /*!< SYSCFG interconnect control register,                            Address offset: 0x1C        */
1221   __IO uint32_t CMPCR;          /*!< SYSCFG compensation cell control register,                       Address offset: 0x20        */
1222   __IO uint32_t CMPENSETR;      /*!< SYSCFG compensation cell enable set register,                    Address offset: 0x24        */
1223   __IO uint32_t CMPENCLRR;      /*!< SYSCFG compensation cell enable clear register,                  Address offset: 0x28        */
1224   __IO uint32_t CBR;            /*!< SYSCFG control timer break register,                             Address offset: 0x2C        */
1225   __IO uint32_t RESERVED2[5];   /*!< Reserved,                                                        Address offset: 0x30-0x40   */
1226   __IO uint32_t PMCCLRR;        /*!< SYSCFG Peripheral Mode configuration clear register,             Address offset: 0x44        */
1227   __IO uint32_t RESERVED3[4];   /*!< Reserved,                                                        Address offset: 0x48-0x54   */
1228   __IO uint32_t IOCTRLCLRR;     /*!< SYSCFG ioctl clear register,                                     Address offset: 0x58        */
1229        uint32_t RESERVED4[230]; /*!< Reserved,                                                        Address offset: 0x5C->0x3F4 */
1230   __IO uint32_t VERR;           /*!< SYSCFG version register,                                         Address offset: 0x3F4       */
1231   __IO uint32_t IPIDR;          /*!< SYSCFG ID register,                                              Address offset: 0x3F8       */
1232   __IO uint32_t SIDR;           /*!< SYSCFG magic ID register,                                        Address offset: 0x3FC       */
1233 } SYSCFG_TypeDef;
1234 
1235 
1236 /**
1237   * @briefVoltage reference buffer
1238   */
1239 typedef struct
1240 {
1241   __IO uint32_t CSR;                /*VREF control and status register                      Address offset: 0x00      */
1242   __IO uint32_t CCR;                /*VREF control and status register                      Address offset: 0x04      */
1243 } VREF_TypeDef;
1244 
1245 
1246 /**
1247   * @brief Inter-integrated Circuit Interface
1248   */
1249 
1250 typedef struct
1251 {
1252   __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
1253   __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
1254   __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
1255   __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
1256   __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
1257   __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
1258   __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
1259   __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
1260   __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
1261   __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
1262   __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
1263   uint32_t RESERVED[241]; /*!< Reserved, 0x2C->0x3F0 */
1264   __IO uint32_t HWCFGR;   /*!< I2C hardware configuration register,  Address offset: 0x3F0 */
1265   __IO uint32_t VERR;     /*!< I2C version register,                 Address offset: 0x3F4 */
1266   __IO uint32_t IPIDR;    /*!< I2C identification register,          Address offset: 0x3F8 */
1267   __IO uint32_t SIDR;     /*!< I2C size identification register,     Address offset: 0x3FC */
1268 } I2C_TypeDef;
1269 
1270 /**
1271   * @brief Independent WATCHDOG
1272   */
1273 
1274 typedef struct
1275 {
1276   __IO uint32_t KR;   /*!< IWDG Key register,                          Address offset: 0x00 */
1277   __IO uint32_t PR;   /*!< IWDG Prescaler register,                    Address offset: 0x04 */
1278   __IO uint32_t RLR;  /*!< IWDG Reload register,                       Address offset: 0x08 */
1279   __IO uint32_t SR;   /*!< IWDG Status register,                       Address offset: 0x0C */
1280   __IO uint32_t WINR; /*!< IWDG Window register,                       Address offset: 0x10 */
1281   __IO uint32_t EWCR; /*!< IWDG Window register,                       Address offset: 0x14 */
1282   uint32_t RESERVED[246]; /*!< Reserved,                                        0x18->0x3EC */
1283   __IO uint32_t HWCFGR;   /*!< IWDG hardware configuration register,  Address offset: 0x3F0 */
1284   __IO uint32_t VERR;     /*!< IWDG version register,                 Address offset: 0x3F4 */
1285   __IO uint32_t IDR;    /*!< IWDG identification register,            Address offset: 0x3F8 */
1286   __IO uint32_t SIDR;     /*!< IWDG size identification register,     Address offset: 0x3FC */
1287 } IWDG_TypeDef;
1288 
1289 
1290 /**
1291   * @brief JPEG Codec
1292   */
1293 typedef struct
1294 {
1295   __IO uint32_t CONFR0;          /*!< JPEG Codec Control Register (JPEG_CONFR0),        Address offset: 00h       */
1296   __IO uint32_t CONFR1;          /*!< JPEG Codec Control Register (JPEG_CONFR1),        Address offset: 04h       */
1297   __IO uint32_t CONFR2;          /*!< JPEG Codec Control Register (JPEG_CONFR2),        Address offset: 08h       */
1298   __IO uint32_t CONFR3;          /*!< JPEG Codec Control Register (JPEG_CONFR3),        Address offset: 0Ch       */
1299   __IO uint32_t CONFR4;          /*!< JPEG Codec Control Register (JPEG_CONFR4),        Address offset: 10h       */
1300   __IO uint32_t CONFR5;          /*!< JPEG Codec Control Register (JPEG_CONFR5),        Address offset: 14h       */
1301   __IO uint32_t CONFR6;          /*!< JPEG Codec Control Register (JPEG_CONFR6),        Address offset: 18h       */
1302   __IO uint32_t CONFR7;          /*!< JPEG Codec Control Register (JPEG_CONFR7),        Address offset: 1Ch       */
1303   uint32_t  Reserved20[4];       /* Reserved                                            Address offset: 20h-2Ch   */
1304   __IO uint32_t CR;              /*!< JPEG Control Register (JPEG_CR),                  Address offset: 30h       */
1305   __IO uint32_t SR;              /*!< JPEG Status Register (JPEG_SR),                   Address offset: 34h       */
1306   __IO uint32_t CFR;             /*!< JPEG Clear Flag Register (JPEG_CFR),              Address offset: 38h       */
1307   uint32_t  Reserved3c;          /* Reserved                                            Address offset: 3Ch       */
1308   __IO uint32_t DIR;             /*!< JPEG Data Input Register (JPEG_DIR),              Address offset: 40h       */
1309   __IO uint32_t DOR;             /*!< JPEG Data Output Register (JPEG_DOR),             Address offset: 44h       */
1310   uint32_t  Reserved48[2];       /* Reserved                                            Address offset: 48h-4Ch   */
1311   __IO uint32_t QMEM0[16];       /*!< JPEG quantization tables 0,                       Address offset: 50h-8Ch   */
1312   __IO uint32_t QMEM1[16];       /*!< JPEG quantization tables 1,                       Address offset: 90h-CCh   */
1313   __IO uint32_t QMEM2[16];       /*!< JPEG quantization tables 2,                       Address offset: D0h-10Ch  */
1314   __IO uint32_t QMEM3[16];       /*!< JPEG quantization tables 3,                       Address offset: 110h-14Ch */
1315   __IO uint32_t HUFFMIN[16];     /*!< JPEG HuffMin tables,                              Address offset: 150h-18Ch */
1316   __IO uint32_t HUFFBASE[32];    /*!< JPEG HuffSymb tables,                             Address offset: 190h-20Ch */
1317   __IO uint32_t HUFFSYMB[84];    /*!< JPEG HUFFSYMB tables,                             Address offset: 210h-35Ch */
1318   __IO uint32_t DHTMEM[103];     /*!< JPEG DHTMem tables,                               Address offset: 360h-4F8h */
1319   uint32_t  Reserved4FC;         /* Reserved                                            Address offset: 4FCh      */
1320   __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0,                 Address offset: 500h-65Ch */
1321   __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1,                 Address offset: 660h-7BCh */
1322   __IO uint32_t HUFFENC_DC0[8];  /*!< JPEG encodor, DC Huffman table 0,                 Address offset: 7C0h-7DCh */
1323   __IO uint32_t HUFFENC_DC1[8];  /*!< JPEG encodor, DC Huffman table 1,                 Address offset: 7E0h-7FCh */
1324 
1325 } JPEG_TypeDef;
1326 
1327 
1328 /**
1329   * @brief LCD
1330   */
1331 
1332 typedef struct
1333 {
1334   __IO uint32_t CR;        /*!< LCD control register,              Address offset: 0x00 */
1335   __IO uint32_t FCR;       /*!< LCD frame control register,        Address offset: 0x04 */
1336   __IO uint32_t SR;        /*!< LCD status register,               Address offset: 0x08 */
1337   __IO uint32_t CLR;       /*!< LCD clear register,                Address offset: 0x0C */
1338   uint32_t RESERVED;       /*!< Reserved,                          Address offset: 0x10 */
1339   __IO uint32_t RAM[16];   /*!< LCD display memory,           Address offset: 0x14-0x50 */
1340 } LCD_TypeDef;
1341 
1342 /**
1343   * @brief LCD-TFT Display Controller
1344   */
1345 
1346 typedef struct
1347 {
1348   uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04 */
1349   __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */
1350   __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */
1351   __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */
1352   __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */
1353   __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */
1354   uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20 */
1355   __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */
1356   uint32_t      RESERVED2[1];  /*!< Reserved, 0x28 */
1357   __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */
1358   uint32_t      RESERVED3[1];  /*!< Reserved, 0x30 */
1359   __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */
1360   __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */
1361   __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */
1362   __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
1363   __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */
1364   __IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                       Address offset: 0x48 */
1365 } LTDC_TypeDef;
1366 
1367 /**
1368   * @brief LCD-TFT Display layer x Controller
1369   */
1370 
1371 typedef struct
1372 {
1373   __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */
1374   __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
1375   __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */
1376   __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */
1377   __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */
1378   __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */
1379   __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */
1380   __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */
1381   uint32_t      RESERVED0[2];  /*!< Reserved */
1382   __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */
1383   __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */
1384   __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */
1385   uint32_t      RESERVED1[3];  /*!< Reserved */
1386   __IO uint32_t CLUTWR;         /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */
1387 
1388 } LTDC_Layer_TypeDef;
1389 
1390 
1391 /**
1392   * @brief DDRPHYC DDR Physical Interface Control
1393   */
1394 typedef struct
1395 {
1396   __IO uint32_t RIDR;             /*!< DDR_PHY: PUBL revision Identification register,              Address offset: 0x000 */
1397   __IO uint32_t PIR;              /*!< DDR_PHY: PUBL PHY Initialization register,                   Address offset: 0x004 */
1398   __IO uint32_t PGCR;             /*!< DDR_PHY:                                                     Address offset: 0x008 */
1399   __IO uint32_t PGSR;             /*!< DDR_PHY:                                                     Address offset: 0x00C */
1400   __IO uint32_t DLLGCR;           /*!< DDR_PHY:                                                     Address offset: 0x010 */
1401   __IO uint32_t ACDLLCR;          /*!< DDR_PHY:                                                     Address offset: 0x014 */
1402   __IO uint32_t PTR0;             /*!< DDR_PHY:                                                     Address offset: 0x018 */
1403   __IO uint32_t PTR1;             /*!< DDR_PHY:                                                     Address offset: 0x01C */
1404   __IO uint32_t PTR2;             /*!< DDR_PHY:                                                     Address offset: 0x020 */
1405   __IO uint32_t ACIOCR;           /*!< DDR_PHY: PUBL AC I/O Configuration Register,                 Address offset: 0x024 */
1406   __IO uint32_t DXCCR;            /*!< DDR_PHY: PUBL DATX8 Common Configuration Register,           Address offset: 0x028 */
1407   __IO uint32_t DSGCR;            /*!< DDR_PHY: PUBL DDR System General Configuration Register,     Address offset: 0x02C */
1408   __IO uint32_t DCR;              /*!< DDR_PHY:                                                     Address offset: 0x030 */
1409   __IO uint32_t DTPR0;            /*!< DDR_PHY:                                                     Address offset: 0x034 */
1410   __IO uint32_t DTPR1;            /*!< DDR_PHY:                                                     Address offset: 0x038 */
1411   __IO uint32_t DTPR2;            /*!< DDR_PHY:                                                     Address offset: 0x03C */
1412   __IO uint32_t MR0;              /*!< DDR_PHY:H                                                    Address offset: 0x040 */
1413   __IO uint32_t MR1;              /*!< DDR_PHY:H                                                    Address offset: 0x044 */
1414   __IO uint32_t MR2;              /*!< DDR_PHY:H                                                    Address offset: 0x048 */
1415   __IO uint32_t MR3;              /*!< DDR_PHY:B                                                    Address offset: 0x04C */
1416   __IO uint32_t ODTCR;            /*!< DDR_PHY:H                                                    Address offset: 0x050 */
1417   __IO uint32_t DTAR;             /*!< DDR_PHY:                                                     Address offset: 0x054 */
1418   __IO uint32_t DTDR0;            /*!< DDR_PHY:                                                     Address offset: 0x058 */
1419   __IO uint32_t DTDR1;            /*!< DDR_PHY:                                                     Address offset: 0x05C */
1420   uint32_t      RESERVED0[24];    /*!< Reserved */
1421   __IO uint32_t DCUAR;            /*!< DDR_PHY:H                                                    Address offset: 0x0C0 */
1422   __IO uint32_t DCUDR;            /*!< DDR_PHY:                                                     Address offset: 0x0C4 */
1423   __IO uint32_t DCURR;            /*!< DDR_PHY:                                                     Address offset: 0x0C8 */
1424   __IO uint32_t DCULR;            /*!< DDR_PHY:                                                     Address offset: 0x0CC */
1425   __IO uint32_t DCUGCR;           /*!< DDR_PHY:H                                                    Address offset: 0x0D0 */
1426   __IO uint32_t DCUTPR;           /*!< DDR_PHY:                                                     Address offset: 0x0D4 */
1427   __IO uint32_t DCUSR0;           /*!< DDR_PHY:B                                                    Address offset: 0x0D8 */
1428   __IO uint32_t DCUSR1;           /*!< DDR_PHY:                                                     Address offset: 0x0DC */
1429   uint32_t      RESERVED1[8];    /*!< Reserved */
1430   __IO uint32_t BISTRR;           /*!< DDR_PHY:                                                     Address offset: 0x100 */
1431   __IO uint32_t BISTMSKR0;        /*!< DDR_PHY:                                                     Address offset: 0x104 */
1432   __IO uint32_t BISTMSKR1;        /*!< DDR_PHY:                                                     Address offset: 0x108 */
1433   __IO uint32_t BISTWCR;          /*!< DDR_PHY:H                                                    Address offset: 0x10C */
1434   __IO uint32_t BISTLSR;          /*!< DDR_PHY:                                                     Address offset: 0x110 */
1435   __IO uint32_t BISTAR0;          /*!< DDR_PHY:                                                     Address offset: 0x114 */
1436   __IO uint32_t BISTAR1;          /*!< DDR_PHY:H                                                    Address offset: 0x118 */
1437   __IO uint32_t BISTAR2;          /*!< DDR_PHY:                                                     Address offset: 0x11C */
1438   __IO uint32_t BISTUDPR;         /*!< DDR_PHY:                                                     Address offset: 0x120 */
1439   __IO uint32_t BISTGSR;          /*!< DDR_PHY:                                                     Address offset: 0x124 */
1440   __IO uint32_t BISTWER;          /*!< DDR_PHY:                                                     Address offset: 0x128 */
1441   __IO uint32_t BISTBER0;         /*!< DDR_PHY:                                                     Address offset: 0x12C */
1442   __IO uint32_t BISTBER1;         /*!< DDR_PHY:                                                     Address offset: 0x130 */
1443   __IO uint32_t BISTBER2;         /*!< DDR_PHY:                                                     Address offset: 0x134 */
1444   __IO uint32_t BISTWCSR;         /*!< DDR_PHY:                                                     Address offset: 0x138 */
1445   __IO uint32_t BISTFWR0;         /*!< DDR_PHY:                                                     Address offset: 0x13C */
1446   __IO uint32_t BISTFWR1;         /*!< DDR_PHY:                                                     Address offset: 0x140 */
1447   uint32_t      RESERVED2[13];    /*!< Reserved */
1448   __IO uint32_t GPR0;             /*!< DDR_PHY:                                                     Address offset: 0x178 */
1449   __IO uint32_t GPR1;             /*!< DDR_PHY:                                                     Address offset: 0x17C */
1450   __IO uint32_t ZQ0CR0;           /*!< DDR_PHY:                                                     Address offset: 0x180 */
1451   __IO uint32_t ZQ0CR1;           /*!< DDR_PHY:B                                                    Address offset: 0x184 */
1452   __IO uint32_t ZQ0SR0;           /*!< DDR_PHY:                                                     Address offset: 0x188 */
1453   __IO uint32_t ZQ0SR1;           /*!< DDR_PHY:B                                                    Address offset: 0x18C */
1454   uint32_t      RESERVED3[12];    /*!< Reserved */
1455   __IO uint32_t DX0GCR;           /*!< DDR_PHY:                                                     Address offset: 0x1C0 */
1456   __IO uint32_t DX0GSR0;          /*!< DDR_PHY:H                                                    Address offset: 0x1C4 */
1457   __IO uint32_t DX0GSR1;          /*!< DDR_PHY:                                                     Address offset: 0x1C8 */
1458   __IO uint32_t DX0DLLCR;         /*!< DDR_PHY:                                                     Address offset: 0x1CC */
1459   __IO uint32_t DX0DQTR;          /*!< DDR_PHY:                                                     Address offset: 0x1D0 */
1460   __IO uint32_t DX0DQSTR;         /*!< DDR_PHY:                                                     Address offset: 0x1D4 */
1461   uint32_t      RESERVED4[10];    /*!< Reserved */
1462   __IO uint32_t DX1GCR;           /*!< DDR_PHY:                                                     Address offset: 0x200 */
1463   __IO uint32_t DX1GSR0;          /*!< DDR_PHY:H                                                    Address offset: 0x204 */
1464   __IO uint32_t DX1GSR1;          /*!< DDR_PHY:                                                     Address offset: 0x208 */
1465   __IO uint32_t DX1DLLCR;         /*!< DDR_PHY:                                                     Address offset: 0x20C */
1466   __IO uint32_t DX1DQTR;          /*!< DDR_PHY:                                                     Address offset: 0x210 */
1467   __IO uint32_t DX1DQSTR;         /*!< DDR_PHY:                                                     Address offset: 0x214 */
1468   uint32_t      RESERVED5[10];    /*!< Reserved */
1469   __IO uint32_t DX2GCR;           /*!< DDR_PHY:                                                     Address offset: 0x240 */
1470   __IO uint32_t DX2GSR0;          /*!< DDR_PHY:H                                                    Address offset: 0x244 */
1471   __IO uint32_t DX2GSR1;          /*!< DDR_PHY:                                                     Address offset: 0x248 */
1472   __IO uint32_t DX2DLLCR;         /*!< DDR_PHY:                                                     Address offset: 0x24C */
1473   __IO uint32_t DX2DQTR;          /*!< DDR_PHY:                                                     Address offset: 0x250 */
1474   __IO uint32_t DX2DQSTR;         /*!< DDR_PHY:                                                     Address offset: 0x254 */
1475   uint32_t      RESERVED6[10];    /*!< Reserved */
1476   __IO uint32_t DX3GCR;           /*!< DDR_PHY:                                                     Address offset: 0x280 */
1477   __IO uint32_t DX3GSR0;          /*!< DDR_PHY:H                                                    Address offset: 0x284 */
1478   __IO uint32_t DX3GSR1;          /*!< DDR_PHY:                                                     Address offset: 0x288 */
1479   __IO uint32_t DX3DLLCR;         /*!< DDR_PHY:                                                     Address offset: 0x28C */
1480   __IO uint32_t DX3DQTR;          /*!< DDR_PHY:                                                     Address offset: 0x290 */
1481   __IO uint32_t DX3DQSTR;         /*!< DDR_PHY:                                                     Address offset: 0x294 */
1482 }DDRPHYC_TypeDef;
1483 
1484 
1485 /**
1486   * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL)
1487   */
1488 typedef struct
1489 {
1490   __IO uint32_t MSTR;      /*!< DDR_PHY: PUBL revision Identification register,              Address offset: 0x00 */
1491   /* @TODO : TypeDef to be compleated */
1492 }DDRC_TypeDef;
1493 
1494 
1495 /**
1496   * @brief USBPHYC  USB HS PHY Control
1497   */
1498 typedef struct
1499 {
1500   __IO uint32_t PLL;                       /*!< USBPHYC PLL control register,               Address offset: 0x000 */
1501   uint32_t RESERVED0;                      /*! Reserved                                     Address offset: 0x004 */
1502   __IO uint32_t MISC;                      /*!< USBPHYC Misc Control register,              Address offset: 0x008 */
1503   uint32_t RESERVED1[250] ;                /*! Reserved                              Address offset: 0x00C - 0x3F0*/
1504   __IO uint32_t VERR;                      /*!< USBPHYC Version register,                   Address offset: 0x3F4 */
1505   __IO uint32_t IPIDR;                     /*!< USBPHYC Identification register,            Address offset: 0x3F8 */
1506   __IO uint32_t SIDR;                      /*!< USBPHYC Size ID register,                   Address offset: 0x3FC */
1507 }USBPHYC_GlobalTypeDef;
1508 
1509 
1510 /**
1511   * @brief USBPHYC  USB HS PHY Control PHYx
1512   */
1513 typedef struct
1514 {
1515   uint32_t RESERVED0[3];                   /*! Reserved                              Address offset: 0x000 - 0x008 */
1516   __IO uint32_t TUNE;                     /*!< USBPHYC x TUNE register  ter,                Address offset: 0x00C */
1517 }USBPHYC_InstanceTypeDef;
1518 
1519 
1520 /**
1521   * @brief TZC TrustZone Address Space Controller for DDR
1522   */
1523 typedef struct
1524 {
1525   __IO uint32_t BUILD_CONFIG;       /*!< Build config register,               Address offset: 0x00 */
1526   __IO uint32_t ACTION;             /*!< Action register,                     Address offset: 0x04 */
1527   __IO uint32_t GATE_KEEPER;        /*!< Gate keeper register,                Address offset: 0x08 */
1528   __IO uint32_t SPECULATION_CTRL;   /*!< Speculation control register,        Address offset: 0x0C */
1529   uint8_t RESERVED0[0x100 - 0x10];
1530   __IO uint32_t REG_BASE_LOWO;      /*!< Region 0 base address low register,  Address offset: 0x100 */
1531   __IO uint32_t REG_BASE_HIGHO;     /*!< Region 0 base address high register, Address offset: 0x104 */
1532   __IO uint32_t REG_TOP_LOWO;       /*!< Region 0 top address low register,   Address offset: 0x108 */
1533   __IO uint32_t REG_TOP_HIGHO;      /*!< Region 0 top address high register,  Address offset: 0x10C */
1534   __IO uint32_t REG_ATTRIBUTESO;    /*!< Region 0 attribute register,         Address offset: 0x110 */
1535   __IO uint32_t REG_ID_ACCESSO;     /*!< Region 0 ID access register,         Address offset: 0x114 */
1536   /* @TODO : TypeDef to be compleated if needed*/
1537 }TZC_TypeDef;
1538 
1539 
1540 
1541 /**
1542   * @brief TZPC TrustZone Protection Controller
1543   */
1544 typedef struct
1545 {
1546   __IO uint32_t   TZMA0_SIZE;         /*!<TZPC ROM Secure Size Definition register,             Address offset: 0x00 */
1547   __IO uint32_t   TZMA1_SIZE;         /*!<TZPC SYSRAM Secure Size Definition register,          Address offset: 0x04 */
1548   uint32_t        RESERVED0[2];       /*!< Reserved */
1549   __IO uint32_t   DECPROT0;           /*!<TZPC Securable peripheral definition register 0,      Address offset: 0x10 */
1550   __IO uint32_t   DECPROT1;           /*!<TZPC Securable peripheral definition register 1,      Address offset: 0x14 */
1551   __IO uint32_t   DECPROT2;           /*!<TZPC Securable peripheral definition register 2,      Address offset: 0x18 */
1552   __IO uint32_t   DECPROT3;           /*!<TZPC Securable peripheral definition register 3,      Address offset: 0x1C */
1553   __IO uint32_t   DECPROT4;           /*!<TZPC Securable peripheral definition register 4,      Address offset: 0x20 */
1554   __IO uint32_t   DECPROT5;           /*!<TZPC Securable peripheral definition register 5,      Address offset: 0x24 */
1555   uint32_t        RESERVED1[2];       /*!< Reserved */
1556   __IO uint32_t   DECPROT_LOCK0;      /*!<TZPC Securable lock of security register 0,           Address offset: 0x30 */
1557   __IO uint32_t   DECPROT_LOCK1;      /*!<TZPC Securable lock of security register 1,           Address offset: 0x34 */
1558   __IO uint32_t   DECPROT_LOCK2;      /*!<TZPC Securable lock of security register 2,           Address offset: 0x38 */
1559   uint32_t        RESERVED2[237];     /*!< Reserved */
1560   __IO uint32_t   HWCFGR;             /*!< TZPC IP HW configuration register                    Address offset:0x3F0  */
1561   __IO uint32_t   IP_VER;             /*!< TZPC IP version register                             Address offset:0x3F4  */
1562   __IO uint32_t   ID;                 /*!< TZPC IP version register                             Address offset:0x3F8  */
1563   __IO uint32_t   SID;                /*!< TZPC IP version register                             Address offset:0x3FC  */
1564 }TZPC_TypeDef;
1565 
1566 
1567 
1568 /**
1569   * @brief STGENC System Generic Counter Control
1570   */
1571 typedef struct
1572 {
1573   __IO uint32_t CNTCR;       /*!< STGEN Counter Control Register,               Address offset: 0x00 */
1574   /* @TODO : TypeDef to be compleated if needed*/
1575 }STGENC_TypeDef;
1576 
1577 /**
1578   * @brief Firewall
1579   */
1580 
1581 typedef struct
1582 {
1583   __IO uint32_t CSSA;     /*!< Code Segment Start Address register,              Address offset: 0x00 */
1584   __IO uint32_t CSL;      /*!< Code Segment Length register,                      Address offset: 0x04 */
1585   __IO uint32_t NVDSSA;   /*!< NON volatile data Segment Start Address register,  Address offset: 0x08 */
1586   __IO uint32_t NVDSL;    /*!< NON volatile data Segment Length register,         Address offset: 0x0C */
1587   __IO uint32_t VDSSA ;   /*!< Volatile data Segment Start Address register,      Address offset: 0x10 */
1588   __IO uint32_t VDSL ;    /*!< Volatile data Segment Length register,             Address offset: 0x14 */
1589   __IO uint32_t CR ;      /*!< Configuration  register,                           Address offset: 0x20 */
1590 
1591 } FIREWALL_TypeDef;
1592 
1593 /**
1594   * @brief Power Control
1595   */
1596 
1597 typedef struct
1598 {
1599   __IO uint32_t CR1;              /*!< PWR control register 1,                   Address offset: 0x00 */
1600   __IO uint32_t CSR1;             /*!< PWR control status register 1,            Address offset: 0x04 */
1601   __IO uint32_t CR2;              /*!< PWR control register 2,                   Address offset: 0x08 */
1602   __IO uint32_t CR3;              /*!< PWR control register 3,                   Address offset: 0x0C */
1603   __IO uint32_t MPUCR;            /*!< PWR MPU control register,                 Address offset: 0x10 */
1604   __IO uint32_t MCUCR;            /*!< PWR MCU control register,                 Address offset: 0x14 */
1605        uint32_t RESERVED0[2];     /*!< Reserved, 0x18-0x1C                       Address offset: 0x18 */
1606   __IO uint32_t WKUPCR;           /*!< PWR wakeup clear register,                Address offset: 0x20 */
1607   __IO uint32_t WKUPFR;           /*!< PWR wakeup flag register,                 Address offset: 0x24 */
1608   __IO uint32_t MPUWKUPENR;       /*!< PWR wakeup enable and polarity register,  Address offset: 0x28 */
1609   __IO uint32_t MCUWKUPENR;       /*!< PWR wakeup enable and polarity register,  Address offset: 0x2C */
1610        uint32_t RESERVED1[241];   /*!< Reserved, 0x30-0x3F0                      Address offset: 0x30 */
1611   __IO uint32_t VER;              /*!< PWR IP version register,                  Address offset: 0x3F4 */
1612   __IO uint32_t ID;               /*!< PWR IP identification register,           Address offset: 0x3F8 */
1613   __IO uint32_t SID;              /*!< PWR size ID register,                     Address offset: 0x3FC */
1614 } PWR_TypeDef;
1615 
1616 
1617 /**
1618   * @brief Reset and Clock Control
1619   */
1620 
1621 typedef struct
1622 {
1623   __IO uint32_t TZCR;                      /*!< RCC TrustZone Control Register                       Address offset: 0x00 */
1624        uint32_t RESERVED0[2];              /*!< Reserved, 0x04-0x08                                  Address offset: 0x04 */
1625   __IO uint32_t OCENSETR;                  /*!< RCC Oscillator Clock Enable Set Register             Address offset: 0x0C */
1626   __IO uint32_t OCENCLRR;                  /*!< RCC Oscillator Enable Control Clear Register         Address offset: 0x10 */
1627        uint32_t RESERVED1;                 /*!< Reserved,                                            Address offset: 0x14 */
1628   __IO uint32_t HSICFGR;                   /*!< RCC HSI Configuration Register                       Address offset: 0x18 */
1629   __IO uint32_t CSICFGR;                   /*!< RCC CSI Configuration Register                       Address offset: 0x1C */
1630   __IO uint32_t MPCKSELR;                  /*!< RCC MPU Clock Selection Register                     Address offset: 0x20 */
1631   __IO uint32_t ASSCKSELR;                 /*!< RCC AXI Sub-System Clock Selection Register          Address offset: 0x24 */
1632   __IO uint32_t RCK12SELR;                 /*!< RCC PLL 1 and 2 Ref. Clock Selection Register        Address offset: 0x28 */
1633   __IO uint32_t MPCKDIVR;                  /*!< RCC MPU Clock Divider Register                       Address offset: 0x2C */
1634   __IO uint32_t AXIDIVR;                   /*!< RCC AXI Clock Divider Register                       Address offset: 0x30 */
1635        uint32_t RESERVED2[2];              /*!< Reserved, 0x34-0x38                                  Address offset: 0x34 */
1636   __IO uint32_t APB4DIVR;                  /*!< RCC APB4 Clock Divider Register                      Address offset: 0x3C */
1637   __IO uint32_t APB5DIVR;                  /*!< RCC APB5 Clock Divider Register                      Address offset: 0x40 */
1638   __IO uint32_t RTCDIVR;                   /*!< RCC RTC Clock Division Register                      Address offset: 0x44 */
1639   __IO uint32_t MSSCKSELR;                 /*!< RCC MCU Sub-System Clock Selection Register          Address offset: 0x48 */
1640        uint32_t RESERVED3[13];             /*!< Reserved, 0x4C-0x7C                                  Address offset: 0x4C */
1641   __IO uint32_t PLL1CR;                    /*!< RCC PLL1 Control Register                            Address offset: 0x80 */
1642   __IO uint32_t PLL1CFGR1;                 /*!< RCC PLL1 Configuration Register 1                    Address offset: 0x84 */
1643   __IO uint32_t PLL1CFGR2;                 /*!< RCC PLL1 Configuration Register 2                    Address offset: 0x88 */
1644   __IO uint32_t PLL1FRACR;                 /*!< RCC PLL1 Fractional Register                         Address offset: 0x8C */
1645   __IO uint32_t PLL1CSGR;                  /*!< RCC PLL1 Clock Spreading Generator Register          Address offset: 0x90 */
1646   __IO uint32_t PLL2CR;                    /*!< RCC PLL2 Control Register                            Address offset: 0x94 */
1647   __IO uint32_t PLL2CFGR1;                 /*!< RCC PLL2 Configuration Register 1                    Address offset: 0x98 */
1648   __IO uint32_t PLL2CFGR2;                 /*!< RCC PLL2 Configuration Register 2                    Address offset: 0x9C */
1649   __IO uint32_t PLL2FRACR;                 /*!< RCC PLL2 Fractional Register                         Address offset: 0xA0 */
1650   __IO uint32_t PLL2CSGR;                  /*!< RCC PLL2 Clock Spreading Generator Register          Address offset: 0xA4 */
1651        uint32_t RESERVED4[6];              /*!< Reserved, 0xA8-0xBC                                  Address offset: 0xA8 */
1652   __IO uint32_t I2C46CKSELR;               /*!< RCC I2C46 Kernel Clock Selection Register            Address offset: 0xC0 */
1653   __IO uint32_t SPI6CKSELR;                /*!< RCC SPI6 Kernel Clock Selection Register             Address offset: 0xC4 */
1654   __IO uint32_t UART1CKSELR;               /*!< RCC USART1 Kernel Clock Selection Register           Address offset: 0xC8 */
1655   __IO uint32_t RNG1CKSELR;                /*!< RCC RNG1 Kernel Clock Selection Register             Address offset: 0xCC */
1656   __IO uint32_t CPERCKSELR;                /*!< RCC Common Peripheral Clock Selection Register       Address offset: 0xD0 */
1657   __IO uint32_t STGENCKSELR;               /*!< RCC STGEN Clock Selection Register                   Address offset: 0xD4 */
1658   __IO uint32_t DDRITFCR;                  /*!< RCC control DDR interface, DDRC and DDRPHYC Register Address offset: 0xD8 */
1659        uint32_t RESERVED5;                 /*!< Reserved,                                            Address offset: 0xDC */
1660        uint32_t RESERVED6[8];              /*!< Reserved, 0xE0-0xFC                                  Address offset: 0xE0 */
1661   __IO uint32_t MP_BOOTCR;                 /*!< RCC Hold Boot Control Register                       Address offset: 0x100 */
1662   __IO uint32_t MP_SREQSETR;               /*!< RCC Stop Request Set Register                        Address offset: 0x104 */
1663   __IO uint32_t MP_SREQCLRR;               /*!< RCC Stop Request Clear Register                      Address offset: 0x108 */
1664   __IO uint32_t MP_GCR;                    /*!< RCC Global Control Register                          Address offset: 0x10C */
1665   __IO uint32_t MP_APRSTCR;                /*!< RCC Application Reset Control Register               Address offset: 0x110 */
1666   __IO uint32_t MP_APRSTSR;                /*!< RCC Application Reset Status Register                Address offset: 0x114 */
1667        uint32_t RESERVED7[10];             /*!< Reserved, 0x118-0x13C                                Address offset: 0x118 */
1668   __IO uint32_t BDCR;                      /*!< RCC Backup Domain Control Register                   Address offset: 0x140 */
1669   __IO uint32_t RDLSICR;                   /*!< RCC Reset Duration and LSI Control Register          Address offset: 0x144 */
1670        uint32_t RESERVED8[14];             /*!< Reserved, 0x148-0x17C                                Address offset: 0x148 */
1671   __IO uint32_t APB4RSTSETR;               /*!< RCC APB4 Peripheral Reset Set Register               Address offset: 0x180 */
1672   __IO uint32_t APB4RSTCLRR;               /*!< RCC APB4 Peripheral Reset Clear Register             Address offset: 0x184 */
1673   __IO uint32_t APB5RSTSETR;               /*!< RCC APB5 Peripheral Reset Set Register               Address offset: 0x188 */
1674   __IO uint32_t APB5RSTCLRR;               /*!< RCC APB5 Peripheral Reset Clear Register             Address offset: 0x18C */
1675   __IO uint32_t AHB5RSTSETR;               /*!< RCC AHB5 Peripheral Reset Set Register               Address offset: 0x190 */
1676   __IO uint32_t AHB5RSTCLRR;               /*!< RCC AHB5 Peripheral Reset Clear Register             Address offset: 0x194 */
1677   __IO uint32_t AHB6RSTSETR;               /*!< RCC AHB6 Peripheral Reset Set Register               Address offset: 0x198 */
1678   __IO uint32_t AHB6RSTCLRR;               /*!< RCC AHB6 Peripheral Reset Clear Register             Address offset: 0x19C */
1679   __IO uint32_t TZAHB6RSTSETR;             /*!< RCC AHB6 Peripheral Reset Set Register               Address offset: 0x1A0 */
1680   __IO uint32_t TZAHB6RSTCLRR;             /*!< RCC AHB6 Peripheral Reset Clear Register             Address offset: 0x1A4 */
1681        uint32_t RESERVED9[22];             /*!< Reserved, 0x1A8-0x1FC                                Address offset: 0x1A8 */
1682   __IO uint32_t MP_APB4ENSETR;             /*!< RCC APB4 Periph. Enable For MPU Set Register         Address offset: 0x200 */
1683   __IO uint32_t MP_APB4ENCLRR;             /*!< RCC APB4 Periph. Enable For MPU Clear Register       Address offset: 0x204 */
1684   __IO uint32_t MP_APB5ENSETR;             /*!< RCC APB5 Periph. Enable For MPU Set Register         Address offset: 0x208 */
1685   __IO uint32_t MP_APB5ENCLRR;             /*!< RCC APB5 Periph. Enable For MPU Clear Register       Address offset: 0x20C */
1686   __IO uint32_t MP_AHB5ENSETR;             /*!< RCC AHB5 Periph. Enable For MPU Set Register         Address offset: 0x210 */
1687   __IO uint32_t MP_AHB5ENCLRR;             /*!< RCC AHB5 Periph. Enable For MPU Clear Register       Address offset: 0x214 */
1688   __IO uint32_t MP_AHB6ENSETR;             /*!< RCC AHB6 Periph. Enable For MPU Set Register         Address offset: 0x218 */
1689   __IO uint32_t MP_AHB6ENCLRR;             /*!< RCC AHB6 Periph. Enable For MPU Clear Register       Address offset: 0x21C */
1690        uint32_t RESERVED10[24];             /*!< Reserved, 0x220-0x27C                                Address offset: 0x220 */
1691   __IO uint32_t MC_APB4ENSETR;             /*!< RCC APB4 Periph. Enable For MCU Set Register         Address offset: 0x280 */
1692   __IO uint32_t MC_APB4ENCLRR;             /*!< RCC APB4 Periph. Enable For MCU Clear Register       Address offset: 0x284 */
1693   __IO uint32_t MC_APB5ENSETR;             /*!< RCC APB5 Periph. Enable For MCU Set Register         Address offset: 0x288 */
1694   __IO uint32_t MC_APB5ENCLRR;             /*!< RCC APB5 Periph. Enable For MCU Clear Register       Address offset: 0x28C */
1695   __IO uint32_t MC_AHB5ENSETR;             /*!< RCC AHB5 Periph. Enable For MCU Set Register         Address offset: 0x290 */
1696   __IO uint32_t MC_AHB5ENCLRR;             /*!< RCC AHB5 Periph. Enable For MCU Clear Register       Address offset: 0x294 */
1697   __IO uint32_t MC_AHB6ENSETR;             /*!< RCC AHB6 Periph. Enable For MCU Set Register         Address offset: 0x298 */
1698   __IO uint32_t MC_AHB6ENCLRR;             /*!< RCC AHB6 Periph. Enable For MCU Clear Register       Address offset: 0x29C */
1699        uint32_t RESERVED11[24];            /*!< Reserved, 0x2A0-0x2FC                                Address offset: 0x2A0 */
1700   __IO uint32_t MP_APB4LPENSETR;           /*!< RCC APB4 Sleep Clock Ena. For MPU Set Register       Address offset: 0x300 */
1701   __IO uint32_t MP_APB4LPENCLRR;           /*!< RCC APB4 Sleep Clock Ena. For MPU Clear Register     Address offset: 0x304 */
1702   __IO uint32_t MP_APB5LPENSETR;           /*!< RCC APB5 Sleep Clock Ena. For MPU Set Register       Address offset: 0x308 */
1703   __IO uint32_t MP_APB5LPENCLRR;           /*!< RCC APB5 Sleep Clock Ena. For MPU Clear Register     Address offset: 0x30C */
1704   __IO uint32_t MP_AHB5LPENSETR;           /*!< RCC AHB5 Sleep Clock Ena. For MPU Set Register       Address offset: 0x310 */
1705   __IO uint32_t MP_AHB5LPENCLRR;           /*!< RCC AHB5 Sleep Clock Ena. For MPU Clear Register     Address offset: 0x314 */
1706   __IO uint32_t MP_AHB6LPENSETR;           /*!< RCC AHB6 Sleep Clock Ena. For MPU Set Register       Address offset: 0x318 */
1707   __IO uint32_t MP_AHB6LPENCLRR;           /*!< RCC AHB6 Sleep Clock Ena. For MPU Clear Register     Address offset: 0x31C */
1708        uint32_t RESERVED12[24];            /*!< Reserved, 0x320-0x30C                                Address offset: 0x320 */
1709   __IO uint32_t MC_APB4LPENSETR;           /*!< RCC APB4 Sleep Clock Ena. For MCU Set Register       Address offset: 0x380 */
1710   __IO uint32_t MC_APB4LPENCLRR;           /*!< RCC APB4 Sleep Clock Ena. For MCU Clear Register     Address offset: 0x384 */
1711   __IO uint32_t MC_APB5LPENSETR;           /*!< RCC APB5 Sleep Clock Ena. For MCU Set Register       Address offset: 0x388 */
1712   __IO uint32_t MC_APB5LPENCLRR;           /*!< RCC APB5 Sleep Clock Ena. For MCU Clear Register     Address offset: 0x38C */
1713   __IO uint32_t MC_AHB5LPENSETR;           /*!< RCC AHB5 Sleep Clock Ena. For MCU Set Register       Address offset: 0x390 */
1714   __IO uint32_t MC_AHB5LPENCLRR;           /*!< RCC AHB5 Sleep Clock Ena. For MCU Clear Register     Address offset: 0x394 */
1715   __IO uint32_t MC_AHB6LPENSETR;           /*!< RCC AHB6 Sleep Clock Ena. For MCU Set Register       Address offset: 0x398 */
1716   __IO uint32_t MC_AHB6LPENCLRR;           /*!< RCC AHB6 Sleep Clock Ena. For MCU Clear Register     Address offset: 0x39C */
1717        uint32_t RESERVED13[24];            /*!< Reserved, 0x3A0-0x3FC                                Address offset: 0x3A0 */
1718   __IO uint32_t BR_RSTSCLRR;               /*!< RCC BootRom Reset Status Clear Register              Address offset: 0x400 */
1719   __IO uint32_t MP_GRSTCSETR;              /*!< RCC Global Reset Control Set Register                Address offset: 0x404 */
1720   __IO uint32_t MP_RSTSCLRR;               /*!< RCC MPU Reset Status Clear Register                  Address offset: 0x408 */
1721   __IO uint32_t MP_IWDGFZSETR;             /*!< RCC IWDG Clock Freeze Set Register                   Address offset: 0x40C */
1722   __IO uint32_t MP_IWDGFZCLRR;             /*!< RCC IWDG Clock Freeze Clear Register                 Address offset: 0x410 */
1723   __IO uint32_t MP_CIER;                   /*!< RCC Clock Source Interrupt Enable Register           Address offset: 0x414 */
1724   __IO uint32_t MP_CIFR;                   /*!< RCC Clock Source Interrupt Flag Register             Address offset: 0x418 */
1725   __IO uint32_t PWRLPDLYCR;                /*!< RCC PWR_LP Delay Control Register                    Address offset: 0x41C */
1726   __IO uint32_t MP_RSTSSETR;               /*!< RCC MPU Reset Status Set Register                    Address offset: 0x420 */
1727        uint32_t RESERVED14[247];           /*!< Reserved, 0x424-0x7FC                                Address offset: 0x424 */
1728   __IO uint32_t MCO1CFGR;                  /*!< RCC MCO1 Configuration Register                      Address offset: 0x800 */
1729   __IO uint32_t MCO2CFGR;                  /*!< RCC MCO2 Configuration Register                      Address offset: 0x804 */
1730   __IO uint32_t OCRDYR;                    /*!< RCC Oscillator Clock Ready Register                  Address offset: 0x808 */
1731   __IO uint32_t DBGCFGR;                   /*!< Debug Configuration Register                         Address offset: 0x80C */
1732        uint32_t RESERVED15[4];             /*!< Reserved, 0x810-0x81C                                Address offset: 0x810 */
1733   __IO uint32_t RCK3SELR;                  /*!< RCC PLL 3 Ref. Clock Selection Register              Address offset: 0x820 */
1734   __IO uint32_t RCK4SELR;                  /*!< RCC PLL4 Ref. Clock Selection Register               Address offset: 0x824 */
1735   __IO uint32_t TIMG1PRER;                 /*!< RCC TIM Group 1 Prescaler Register                   Address offset: 0x828 */
1736   __IO uint32_t TIMG2PRER;                 /*!< RCC TIM Group 2 Prescaler Register                   Address offset: 0x82C */
1737   __IO uint32_t MCUDIVR;                   /*!< RCC MCU Clock Prescaler Register                     Address offset: 0x830 */
1738   __IO uint32_t APB1DIVR;                  /*!< RCC APB1 Clock Prescaler Register                    Address offset: 0x834 */
1739   __IO uint32_t APB2DIVR;                  /*!< RCC APB2 Clock Prescaler Register                    Address offset: 0x838 */
1740   __IO uint32_t APB3DIVR;                  /*!< RCC APB3 Clock Prescaler Register                    Address offset: 0x83C */
1741        uint32_t RESERVED16[16];            /*!< Reserved, 0x840-0x87C                                Address offset: 0x840 */
1742   __IO uint32_t PLL3CR;                    /*!< RCC PLL3 Control Register                            Address offset: 0x880 */
1743   __IO uint32_t PLL3CFGR1;                 /*!< RCC PLL3 Configuration Register 1                    Address offset: 0x884 */
1744   __IO uint32_t PLL3CFGR2;                 /*!< RCC PLL3 Configuration Register 2                    Address offset: 0x888 */
1745   __IO uint32_t PLL3FRACR;                 /*!< RCC PLL3 Fractional Register                         Address offset: 0x88C */
1746   __IO uint32_t PLL3CSGR;                  /*!< RCC PLL3 Clock Spreading Generator Register          Address offset: 0x890 */
1747   __IO uint32_t PLL4CR;                    /*!< RCC PLL4 Control Register                            Address offset: 0x894 */
1748   __IO uint32_t PLL4CFGR1;                 /*!< RCC PLL4 Configuration Register 1                    Address offset: 0x898 */
1749   __IO uint32_t PLL4CFGR2;                 /*!< RCC PLL4 Configuration Register 2                    Address offset: 0x89C */
1750   __IO uint32_t PLL4FRACR;                 /*!< RCC PLL4 Fractional Register                         Address offset: 0x8A0 */
1751   __IO uint32_t PLL4CSGR;                  /*!< RCC PLL4 Clock Spreading Generator Register          Address offset: 0x8A4 */
1752        uint32_t RESERVED17[6];             /*!< Reserved, 0x8A8-0x8BC                                Address offset: 0x8A8 */
1753   __IO uint32_t I2C12CKSELR;               /*!< RCC I2C1,2 Kernel Clock Selection Register           Address offset: 0x8C0 */
1754   __IO uint32_t I2C35CKSELR;               /*!< RCC I2C3,5 Kernel Clock Selection Register           Address offset: 0x8C4 */
1755   __IO uint32_t SAI1CKSELR;                /*!< RCC SAI1 Kernel Clock Selection Register             Address offset: 0x8C8 */
1756   __IO uint32_t SAI2CKSELR;                /*!< RCC SAI2 Kernel Clock Selection Register             Address offset: 0x8CC */
1757   __IO uint32_t SAI3CKSELR;                /*!< RCC SAI3 Kernel Clock Selection Register             Address offset: 0x8D0 */
1758   __IO uint32_t SAI4CKSELR;                /*!< RCC SAI4 Kernel Clock Selection Register             Address offset: 0x8D4 */
1759   __IO uint32_t SPI2S1CKSELR;              /*!< RCC SPI/I2S1 Kernel Clock Selection Register         Address offset: 0x8D8 */
1760   __IO uint32_t SPI2S23CKSELR;             /*!< RCC SPI/I2S2,3 Kernel Clock Selection Register       Address offset: 0x8DC */
1761   __IO uint32_t SPI45CKSELR;               /*!< RCC SPI4,5 Kernel Clock Selection Register           Address offset: 0x8E0 */
1762   __IO uint32_t UART6CKSELR;               /*!< RCC USART6 Kernel Clock Selection Register           Address offset: 0x8E4 */
1763   __IO uint32_t UART24CKSELR;              /*!< RCC UART2,4 Kernel Clock Selection Register          Address offset: 0x8E8 */
1764   __IO uint32_t UART35CKSELR;              /*!< RCC UART3,5 Kernel Clock Selection Register          Address offset: 0x8EC */
1765   __IO uint32_t UART78CKSELR;              /*!< RCC UART7,8 Kernel Clock Selection Register          Address offset: 0x8F0 */
1766   __IO uint32_t SDMMC12CKSELR;             /*!< RCC SDMMC1&2 Kernel Clock Selection Register         Address offset: 0x8F4 */
1767   __IO uint32_t SDMMC3CKSELR;              /*!< RCC SDMMC3 Kernel Clock Selection Register           Address offset: 0x8F8 */
1768   __IO uint32_t ETHCKSELR;                 /*!< RCC Ethernet Kernel Clock Selection Register         Address offset: 0x8FC */
1769   __IO uint32_t QSPICKSELR;                /*!< RCC QUADSPI Kernel Clock Selection Register          Address offset: 0x900 */
1770   __IO uint32_t FMCCKSELR;                 /*!< RCC FMC Kernel Clock Selection Register              Address offset: 0x904 */
1771        uint32_t RESERVED18;                /*!< Reserved,                                            Address offset: 0x908 */
1772   __IO uint32_t FDCANCKSELR;               /*!< RCC FDCAN Kernel Clock Selection Register            Address offset: 0x90C */
1773        uint32_t RESERVED19;                /*!< Reserved,                                            Address offset: 0x910 */
1774   __IO uint32_t SPDIFCKSELR;               /*!< RCC SPDIF Kernel Clock Selection Register            Address offset: 0x914 */
1775   __IO uint32_t CECCKSELR;                 /*!< RCC CEC Kernel Clock Selection Register              Address offset: 0x918 */
1776   __IO uint32_t USBCKSELR;                 /*!< RCC USB Kernel Clock Selection Register              Address offset: 0x91C */
1777   __IO uint32_t RNG2CKSELR;                /*!< RCC RNG2 Kernel Clock Selection Register             Address offset: 0x920 */
1778   __IO uint32_t DSICKSELR;                 /*!< RCC DSI Kernel Clock Selection Register              Address offset: 0x924 */
1779   __IO uint32_t ADCCKSELR;                 /*!< RCC ADC Kernel Clock Selection Register              Address offset: 0x928 */
1780   __IO uint32_t LPTIM45CKSELR;             /*!< RCC LPTIM4&5 Kernel Clock Selection Register         Address offset: 0x92C */
1781   __IO uint32_t LPTIM23CKSELR;             /*!< RCC LPTIM2&3 Kernel Clock Selection Register         Address offset: 0x930 */
1782   __IO uint32_t LPTIM1CKSELR;              /*!< RCC LPTIM1 Kernel Clock Selection Register           Address offset: 0x934 */
1783        uint32_t RESERVED20[18];            /*!< Reserved, 0x938-0x97C                                Address offset: 0x938 */
1784   __IO uint32_t APB1RSTSETR;               /*!< RCC APB1 Peripheral Reset Set Register               Address offset: 0x980 */
1785   __IO uint32_t APB1RSTCLRR;               /*!< RCC APB1 Peripheral Reset Clear Register             Address offset: 0x984 */
1786   __IO uint32_t APB2RSTSETR;               /*!< RCC APB2 Peripheral Reset Set Register               Address offset: 0x988 */
1787   __IO uint32_t APB2RSTCLRR;               /*!< RCC APB2 Peripheral Reset Clear Register             Address offset: 0x98C */
1788   __IO uint32_t APB3RSTSETR;               /*!< RCC APB3 Peripheral Reset Set Register               Address offset: 0x990 */
1789   __IO uint32_t APB3RSTCLRR;               /*!< RCC APB3 Peripheral Reset Clear Register             Address offset: 0x994 */
1790   __IO uint32_t AHB2RSTSETR;               /*!< RCC AHB2 Peripheral Reset Set Register               Address offset: 0x998 */
1791   __IO uint32_t AHB2RSTCLRR;               /*!< RCC AHB2 Peripheral Reset Clear Register             Address offset: 0x99C */
1792   __IO uint32_t AHB3RSTSETR;               /*!< RCC AHB3 Peripheral Reset Set Register               Address offset: 0x9A0 */
1793   __IO uint32_t AHB3RSTCLRR;               /*!< RCC AHB3 Peripheral Reset Clear Register             Address offset: 0x9A4 */
1794   __IO uint32_t AHB4RSTSETR;               /*!< RCC AHB4 Peripheral Reset Set Register               Address offset: 0x9A8 */
1795   __IO uint32_t AHB4RSTCLRR;               /*!< RCC AHB4 Peripheral Reset Clear Register             Address offset: 0x9AC */
1796        uint32_t RESERVED21[20];            /*!< Reserved, 0x9B0-0x9FC                                Address offset: 0x9B0 */
1797   __IO uint32_t MP_APB1ENSETR;             /*!< RCC APB1 Peripheral Enable For MPU Set Register      Address offset: 0xA00 */
1798   __IO uint32_t MP_APB1ENCLRR;             /*!< RCC APB1 Peripheral Enable For MPU Clear Register    Address offset: 0xA04 */
1799   __IO uint32_t MP_APB2ENSETR;             /*!< RCC APB2 Peripheral Enable For MPU Set Register      Address offset: 0xA08 */
1800   __IO uint32_t MP_APB2ENCLRR;             /*!< RCC APB2 Peripheral Enable For MPU Clear Register    Address offset: 0xA0C */
1801   __IO uint32_t MP_APB3ENSETR;             /*!< RCC APB3 Peripheral Enable For MPU Set Register      Address offset: 0xA10 */
1802   __IO uint32_t MP_APB3ENCLRR;             /*!< RCC APB3 Peripheral Enable For MPU Clear Register    Address offset: 0xA14 */
1803   __IO uint32_t MP_AHB2ENSETR;             /*!< RCC AHB2 Peripheral Enable For MPU Set Register      Address offset: 0xA18 */
1804   __IO uint32_t MP_AHB2ENCLRR;             /*!< RCC AHB2 Peripheral Enable For MPU Clear Register    Address offset: 0xA1C */
1805   __IO uint32_t MP_AHB3ENSETR;             /*!< RCC AHB3 Peripheral Enable For MPU Set Register      Address offset: 0xA20 */
1806   __IO uint32_t MP_AHB3ENCLRR;             /*!< RCC AHB3 Peripheral Enable For MPU Clear Register    Address offset: 0xA24 */
1807   __IO uint32_t MP_AHB4ENSETR;             /*!< RCC AHB4 Peripheral Enable For MPU Set Register      Address offset: 0xA28 */
1808   __IO uint32_t MP_AHB4ENCLRR;             /*!< RCC AHB4 Peripheral Enable For MPU Clear Register    Address offset: 0xA2C */
1809        uint32_t RESERVED22[2];             /*!< Reserved, 0xA30-0xA34                                Address offset: 0xA30 */
1810   __IO uint32_t MP_MLAHBENSETR;            /*!< RCC MLAHB Periph. Enable For MPU Set Register        Address offset: 0xA38 */
1811   __IO uint32_t MP_MLAHBENCLRR;            /*!< RCC MLAHB Periph. Enable For MPU Clear Register      Address offset: 0xA3C */
1812        uint32_t RESERVED23[16];            /*!< Reserved, 0x940-0xA7C                                Address offset: 0x940 */
1813   __IO uint32_t MC_APB1ENSETR;             /*!< RCC APB1 Peripheral Enable For MCU Set Register      Address offset: 0xA80 */
1814   __IO uint32_t MC_APB1ENCLRR;             /*!< RCC APB1 Peripheral Enable For MCU Clear Register    Address offset: 0xA84 */
1815   __IO uint32_t MC_APB2ENSETR;             /*!< RCC APB2 Peripheral Enable For MCU Set Register      Address offset: 0xA88 */
1816   __IO uint32_t MC_APB2ENCLRR;             /*!< RCC APB2 Peripheral Enable For MCU Clear Register    Address offset: 0xA8C */
1817   __IO uint32_t MC_APB3ENSETR;             /*!< RCC APB3 Peripheral Enable For MCU Set Register      Address offset: 0xA90 */
1818   __IO uint32_t MC_APB3ENCLRR;             /*!< RCC APB3 Peripheral Enable For MCU Clear Register    Address offset: 0xA94 */
1819   __IO uint32_t MC_AHB2ENSETR;             /*!< RCC AHB2 Peripheral Enable For MCU Set Register      Address offset: 0xA98 */
1820   __IO uint32_t MC_AHB2ENCLRR;             /*!< RCC AHB2 Peripheral Enable For MCU Clear Register    Address offset: 0xA9C */
1821   __IO uint32_t MC_AHB3ENSETR;             /*!< RCC AHB3 Peripheral Enable For MCU Set Register      Address offset: 0xAA0 */
1822   __IO uint32_t MC_AHB3ENCLRR;             /*!< RCC AHB3 Peripheral Enable For MCU Clear Register    Address offset: 0xAA4 */
1823   __IO uint32_t MC_AHB4ENSETR;             /*!< RCC AHB4 Peripheral Enable For MCU Set Register      Address offset: 0xAA8 */
1824   __IO uint32_t MC_AHB4ENCLRR;             /*!< RCC AHB4 Peripheral Enable For MCU Clear Register    Address offset: 0xAAC */
1825   __IO uint32_t MC_AXIMENSETR;             /*!< RCC AXI Periph. Enable For MCU Set Register          Address offset: 0xAB0 */
1826   __IO uint32_t MC_AXIMENCLRR;             /*!< RCC AXI Periph. Enable For MCU Clear Register        Address offset: 0xAB4 */
1827   __IO uint32_t MC_MLAHBENSETR;            /*!< RCC MLAHB Periph. Enable For MCU Set Register        Address offset: 0xAB8 */
1828   __IO uint32_t MC_MLAHBENCLRR;            /*!< RCC MLAHB Periph. Enable For MCU Clear Register      Address offset: 0xABC */
1829        uint32_t RESERVED24[16];            /*!< Reserved, 0xAC0-0xAFC                                Address offset: 0xAC0 */
1830   __IO uint32_t MP_APB1LPENSETR;           /*!< RCC APB1 Sleep Clock Ena. For MPU Set Register       Address offset: 0xB00 */
1831   __IO uint32_t MP_APB1LPENCLRR;           /*!< RCC APB1 Sleep Clock Ena. For MPU Clear Register     Address offset: 0xB04 */
1832   __IO uint32_t MP_APB2LPENSETR;           /*!< RCC APB2 Sleep Clock Ena. For MPU Set Register       Address offset: 0xB08 */
1833   __IO uint32_t MP_APB2LPENCLRR;           /*!< RCC APB2 Sleep Clock Ena. For MPU Clear Register     Address offset: 0xB0C */
1834   __IO uint32_t MP_APB3LPENSETR;           /*!< RCC APB3 Sleep Clock Ena. For MPU Set Register       Address offset: 0xB10 */
1835   __IO uint32_t MP_APB3LPENCLRR;           /*!< RCC APB3 Sleep Clock Ena. For MPU Clear Register     Address offset: 0xB14 */
1836   __IO uint32_t MP_AHB2LPENSETR;           /*!< RCC AHB2 Sleep Clock Ena. For MPU Set Register       Address offset: 0xB18 */
1837   __IO uint32_t MP_AHB2LPENCLRR;           /*!< RCC AHB2 Sleep Clock Ena. For MPU Clear Register     Address offset: 0xB1C */
1838   __IO uint32_t MP_AHB3LPENSETR;           /*!< RCC AHB3 Sleep Clock Ena. For MPU Set Register       Address offset: 0xB20 */
1839   __IO uint32_t MP_AHB3LPENCLRR;           /*!< RCC AHB3 Sleep Clock Ena. For MPU Clear Register     Address offset: 0xB24 */
1840   __IO uint32_t MP_AHB4LPENSETR;           /*!< RCC AHB4 Sleep Clock Ena. For MPU Set Register       Address offset: 0xB28 */
1841   __IO uint32_t MP_AHB4LPENCLRR;           /*!< RCC AHB4 Sleep Clock Ena. For MPU Clear Register     Address offset: 0xB2C */
1842   __IO uint32_t MP_AXIMLPENSETR;           /*!< RCC AXI Sleep Clock Ena. For MPU Set Register        Address offset: 0xB30 */
1843   __IO uint32_t MP_AXIMLPENCLRR;           /*!< RCC AXI Sleep Clock Ena. For MPU Clear Register      Address offset: 0xB34 */
1844   __IO uint32_t MP_MLAHBLPENSETR;          /*!< RCC MLAHB Sleep Clock Ena. For MPU Set Register      Address offset: 0xB38 */
1845   __IO uint32_t MP_MLAHBLPENCLRR;          /*!< RCC MLAHB Sleep Clock Ena. For MPU Clear Register    Address offset: 0xB3C */
1846        uint32_t RESERVED25[16];            /*!< Reserved, 0xB40-0xB7C                                Address offset: 0xB40 */
1847   __IO uint32_t MC_APB1LPENSETR;           /*!< RCC APB1 Sleep Clock Ena. For MCU Set Register       Address offset: 0xB80 */
1848   __IO uint32_t MC_APB1LPENCLRR;           /*!< RCC APB1 Sleep Clock Ena. For MCU Clear Register     Address offset: 0xB84 */
1849   __IO uint32_t MC_APB2LPENSETR;           /*!< RCC APB2 Sleep Clock Ena. For MCU Set Register       Address offset: 0xB88 */
1850   __IO uint32_t MC_APB2LPENCLRR;           /*!< RCC APB2 Sleep Clock Ena. For MCU Clear Register     Address offset: 0xB8C */
1851   __IO uint32_t MC_APB3LPENSETR;           /*!< RCC APB3 Sleep Clock Ena. For MCU Set Register       Address offset: 0xB90 */
1852   __IO uint32_t MC_APB3LPENCLRR;           /*!< RCC APB3 Sleep Clock Ena. For MCU Clear Register     Address offset: 0xB94 */
1853   __IO uint32_t MC_AHB2LPENSETR;           /*!< RCC AHB2 Sleep Clock Ena. For MCU Set Register       Address offset: 0xB98 */
1854   __IO uint32_t MC_AHB2LPENCLRR;           /*!< RCC AHB2 Sleep Clock Ena. For MCU Clear Register     Address offset: 0xB9C */
1855   __IO uint32_t MC_AHB3LPENSETR;           /*!< RCC AHB3 Sleep Clock Ena. For MCU Set Register       Address offset: 0xBA0 */
1856   __IO uint32_t MC_AHB3LPENCLRR;           /*!< RCC AHB3 Sleep Clock Ena. For MCU Clear Register     Address offset: 0xBA4 */
1857   __IO uint32_t MC_AHB4LPENSETR;           /*!< RCC AHB4 Sleep Clock Ena. For MCU Set Register       Address offset: 0xBA8 */
1858   __IO uint32_t MC_AHB4LPENCLRR;           /*!< RCC AHB4 Sleep Clock Ena. For MCU Clear Register     Address offset: 0xBAC */
1859   __IO uint32_t MC_AXIMLPENSETR;           /*!< RCC AXI Sleep Clock Ena. For MCU Set Register        Address offset: 0xBB0 */
1860   __IO uint32_t MC_AXIMLPENCLRR;           /*!< RCC AXI Sleep Clock Ena. For MCU Clear Register      Address offset: 0xBB4 */
1861   __IO uint32_t MC_MLAHBLPENSETR;          /*!< RCC MLAHB Sleep Clock Ena. For MCU Set Register      Address offset: 0xBB8 */
1862   __IO uint32_t MC_MLAHBLPENCLRR;          /*!< RCC MLAHB Sleep Clock Ena. For MCU Clear Register    Address offset: 0xBBC */
1863        uint32_t RESERVED26[16];            /*!< Reserved, 0xBC0-0xBFC                                Address offset: 0xBC0 */
1864   __IO uint32_t MC_RSTSCLRR;               /*!< RCC MCU Reset Status Clear Register                  Address offset: 0xC00 */
1865        uint32_t RESERVED27[4];             /*!< Reserved, 0xC04-0xC10                                Address offset: 0xC04 */
1866   __IO uint32_t MC_CIER;                   /*!< RCC Clock Source Interrupt Enable Register           Address offset: 0xC14 */
1867   __IO uint32_t MC_CIFR;                   /*!< RCC Clock Source Interrupt Flag Register             Address offset: 0xC18 */
1868        uint32_t RESERVED28[246];           /*!< Reserved, 0xC1C-0xFF0                                Address offset: 0xC1C */
1869   __IO uint32_t VERR;                      /*!< RCC Version register                                 Address offset: 0xFF4 */
1870   __IO uint32_t IPIDR;                     /*!< RCC ID register                                      Address offset: 0xFF8 */
1871   __IO uint32_t SIDR;                      /*!< Size ID register                                     Address offset: 0xFFC */
1872 } RCC_TypeDef;
1873 
1874 /**
1875   * @brief Hardware Debug Port
1876   */
1877 
1878 typedef struct
1879 {
1880   __IO uint32_t HDP_CTRL;                  /*!< HDP Control Register,                                Address offset: 0x00 */
1881   __IO uint32_t HDP_MUX;                   /*!< HDP Multiplexers Control Register,                   Address offset: 0x04 */
1882        uint32_t RESERVED0[2];              /*!< Reserved, 0x08-0x0C                                  Address offset: 0x08 */
1883   __IO uint32_t HDP_VAL;                   /*!< HDP Read Back Value Register,                        Address offset: 0x10 */
1884   __IO uint32_t HDP_GPOSET;                /*!< HDP General Purpose Output Set Register,             Address offset: 0x14 */
1885   __IO uint32_t HDP_GPOCLR;                /*!< HDP General Purpose Output Clear Register,           Address offset: 0x18 */
1886   __IO uint32_t HDP_GPOVAL;                /*!< HDP General Purpose Output Value Register,           Address offset: 0x1C */
1887        uint32_t RESERVED1[245];            /*!< Reserved, 0x20-0x3F4                                 Address offset: 0x20 */
1888   __IO uint32_t VERR;                  /*!< HDP Version Register,                                Address offset: 0x3F4 */
1889   __IO uint32_t IPIDR;                 /*!< HDP IP Identification Register,                      Address offset: 0x3F8 */
1890   __IO uint32_t SIDR;                  /*!< HDP Size Identification register,                    Address offset: 0x3FC */
1891 } HDP_TypeDef;
1892 
1893 
1894 /**
1895   * @brief Boot and Security and OTP Control
1896   */
1897 
1898 typedef struct
1899 {
1900   __IO uint32_t BSEC_OTP_CONFIG;           /*!< BSEC OTP Configuration,                              Address offset: 0x00 */
1901   __IO uint32_t BSEC_OTP_CONTROL;          /*!< BSEC OTP Control,                                    Address offset: 0x04 */
1902   __IO uint32_t BSEC_OTP_WRDATA;           /*!< BSEC OTP Write Data,                                 Address offset: 0x08 */
1903   __IO uint32_t BSEC_OTP_STATUS;           /*!< BSEC OTP Status,                                     Address offset: 0x0C */
1904   __IO uint32_t BSEC_OTP_LOCK;             /*!< BSEC OTP Configuration,                              Address offset: 0x10 */
1905   __IO uint32_t BSEC_DENABLE;              /*!< BSEC Debug Configuration,                            Address offset: 0x14 */
1906   __IO uint32_t BSEC_FENABLE;              /*!< BSEC Feature Configuration,                          Address offset: 0x18 */
1907   __IO uint32_t BSEC_OTP_DISTURBED0;       /*!< BSEC OTP Disturbed Status,                           Address offset: 0x1C */
1908   __IO uint32_t BSEC_OTP_DISTURBED1;       /*!< BSEC OTP Disturbed Status,                           Address offset: 0x20 */
1909   __IO uint32_t BSEC_OTP_DISTURBED2;       /*!< BSEC OTP Disturbed Status,                           Address offset: 0x24 */
1910        uint32_t RESERVED0x28;              /*!< Reserved,                                            Address offset: 0x28 */
1911        uint32_t RESERVED0x2C;              /*!< Reserved,                                            Address offset: 0x2C */
1912        uint32_t RESERVED0x30;              /*!< Reserved,                                            Address offset: 0x30 */
1913   __IO uint32_t BSEC_OTP_ERROR0;           /*!< BSEC OTP Error Status,                               Address offset: 0x34 */
1914   __IO uint32_t BSEC_OTP_ERROR1;           /*!< BSEC OTP Error Status,                               Address offset: 0x38 */
1915   __IO uint32_t BSEC_OTP_ERROR2;           /*!< BSEC OTP Error Status,                               Address offset: 0x3C */
1916        uint32_t RESERVED0x40;              /*!< Reserved,                                            Address offset: 0x40 */
1917        uint32_t RESERVED0x44;              /*!< Reserved,                                            Address offset: 0x44 */
1918        uint32_t RESERVED0x48;              /*!< Reserved,                                            Address offset: 0x48 */
1919   __IO uint32_t BSEC_OTP_WRLOCK0;          /*!< BSEC OTP Lock status,                                Address offset: 0x4C */
1920   __IO uint32_t BSEC_OTP_WRLOCK1;          /*!< BSEC OTP Lock status,                                Address offset: 0x50 */
1921   __IO uint32_t BSEC_OTP_WRLOCK2;          /*!< BSEC OTP Lock status,                                Address offset: 0x54 */
1922        uint32_t RESERVED0x58;              /*!< Reserved,                                            Address offset: 0x58 */
1923        uint32_t RESERVED0x5C;              /*!< Reserved,                                            Address offset: 0x5C */
1924        uint32_t RESERVED0x60;              /*!< Reserved,                                            Address offset: 0x60 */
1925   __IO uint32_t BSEC_OTP_SPLOCK0;          /*!< BSEC OTP prg lock under ctrl by stick bits,          Address offset: 0x64 */
1926   __IO uint32_t BSEC_OTP_SPLOCK1;          /*!< BSEC OTP prg lock under ctrl by stick bits,          Address offset: 0x68 */
1927   __IO uint32_t BSEC_OTP_SPLOCK2;          /*!< BSEC OTP prg lock under ctrl by stick bits,          Address offset: 0x6C */
1928        uint32_t RESERVED0x70;              /*!< Reserved,                                            Address offset: 0x70 */
1929        uint32_t RESERVED0x74;              /*!< Reserved,                                            Address offset: 0x74 */
1930        uint32_t RESERVED0x78;              /*!< Reserved,                                            Address offset: 0x78 */
1931   __IO uint32_t BSEC_OTP_SWLOCK0;          /*!< BSEC OTP Shadow Write Lck under ctrl by sticky bits, Address offset: 0x7C */
1932   __IO uint32_t BSEC_OTP_SWLOCK1;          /*!< BSEC OTP Shadow Write Lck under ctrl by sticky bits, Address offset: 0x80 */
1933   __IO uint32_t BSEC_OTP_SWLOCK2;          /*!< BSEC OTP Shadow Write Lck under ctrl by sticky bits, Address offset: 0x84 */
1934        uint32_t RESERVED0x88;              /*!< Reserved,                                            Address offset: 0x88 */
1935        uint32_t RESERVED0x8C;              /*!< Reserved,                                            Address offset: 0x8C */
1936        uint32_t RESERVED0x90;              /*!< Reserved,                                            Address offset: 0x90 */
1937   __IO uint32_t BSEC_OTP_SRLOCK0;          /*!< BSEC OTP Shadow read lock under ctrl by sticky bits, Address offset: 0x94 */
1938   __IO uint32_t BSEC_OTP_SRLOCK1;          /*!< BSEC OTP Shadow read lock under ctrl by sticky bits, Address offset: 0x98 */
1939   __IO uint32_t BSEC_OTP_SRLOCK2;          /*!< BSEC OTP Shadow read lock under ctrl by sticky bits, Address offset: 0x9C */
1940        uint32_t RESERVED0xA0;              /*!< Reserved,                                            Address offset: 0xA0 */
1941        uint32_t RESERVED0xA4;              /*!< Reserved,                                            Address offset: 0xA4 */
1942        uint32_t RESERVED0xA8;              /*!< Reserved,                                            Address offset: 0xA8 */
1943   __IO uint32_t BSEC_JTAGIN;               /*!< BSEC JTAG Input,                                     Address offset: 0xAC */
1944   __IO uint32_t BSEC_JTAGOUT;              /*!< BSEC JTAG Output,                                    Address offset: 0xB0 */
1945   __IO uint32_t BSEC_SCRATCH;              /*!< BSEC SCRATCH,                                        Address offset: 0xB4 */
1946        uint32_t RESERVED0xB8[82];          /*!< Reserved, 0x0B8-0x200                                Address offset: 0xB8 */
1947   __IO uint32_t BSEC_OTP_DATA[96];         /*!< BSEC Shadow Registers,                               Address offset: 0x200 */
1948        uint32_t RESERVED0x380[796];        /*!< Reserved, 0x0380-0xFF0                               Address offset: 0x380 */
1949   __IO uint32_t HWCFGR;                    /*!< BSEC IP HW Configuration Register,                   Address offset: 0xFF0 */
1950   __IO uint32_t VERR;                      /*!< BSEC IP version Register,                            Address offset: 0xFF4 */
1951   __IO uint32_t IPIDR;                     /*!< BSEC ID Register,                                    Address offset: 0xFF8 */
1952   __IO uint32_t SIDR;                      /*!< BSEC SID Register,                                   Address offset: 0xFFC */
1953 } BSEC_TypeDef;
1954 
1955 
1956 /**
1957   * @brief RTC Specific device feature definitions
1958   */
1959 #define RTC_BACKUP_NB       32u /* Backup registers implemented */
1960 #define RTC_TAMP_NB         3u  /* External tamper events (input pins) supported */
1961 
1962 /**
1963   * @brief Real-Time Clock
1964   */
1965 
1966 typedef struct
1967 {
1968     __IO uint32_t TR;             /*!< RTC time register,                                         Address offset: 0x00 */
1969     __IO uint32_t DR;             /*!< RTC date register,                                         Address offset: 0x04 */
1970     __IO uint32_t SSR;            /*!< RTC sub-second register,                                   Address offset: 0x08 */
1971     __IO uint32_t ICSR;           /*!< RTC initialization control and status register,            Address offset: 0x0C */
1972     __IO uint32_t PRER;           /*!< RTC prescaler register,                                    Address offset: 0x10 */
1973     __IO uint32_t WUTR;           /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
1974     __IO uint32_t CR;             /*!< RTC control register,                                      Address offset: 0x18 */
1975          uint32_t RESERVED;       /*!< Reserved                                                                        */
1976     __IO uint32_t SMCR;           /*!< RTC secure mode control register,                          Address offset: 0x20 */
1977     __IO uint32_t WPR;            /*!< RTC write protection register,                             Address offset: 0x24 */
1978     __IO uint32_t CALR;           /*!< RTC calibration register,                                  Address offset: 0x28 */
1979     __IO uint32_t SHIFTR;         /*!< RTC shift control register,                                Address offset: 0x2C */
1980     __IO uint32_t TSTR;           /*!< RTC time stamp time register,                              Address offset: 0x30 */
1981     __IO uint32_t TSDR;           /*!< RTC time stamp date register,                              Address offset: 0x34 */
1982     __IO uint32_t TSSSR;           /*!< RTC time stamp sub second register,                        Address offset: 0x38 */
1983          uint32_t RESERVED1;      /*!< Reserved                                                                        */
1984     __IO uint32_t ALRMAR;         /*!< RTC alarm A register,                                      Address offset: 0x40 */
1985     __IO uint32_t ALRMASSR;       /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
1986     __IO uint32_t ALRMBR;         /*!< RTC alarm B register,                                      Address offset: 0x48 */
1987     __IO uint32_t ALRMBSSR;       /*!< RTC alarm B sub second register,                           Address offset: 0x4C */
1988     __IO uint32_t SR;             /*!< RTC status register,                                       Address offset: 0x50 */
1989     __IO uint32_t MISR;           /*!< RTC masked interrupt status register,                      Address offset: 0x54 */
1990     __IO uint32_t SMISR;          /*!< RTC secure masked interrupt status register,               Address offset: 0x58 */
1991     __IO uint32_t SCR;            /*!< RTC status clear register,                                 Address offset: 0x5C */
1992     __IO uint32_t CFGR;           /*!< RTC Configuration register,                               Address offset: 0x60 */
1993          uint32_t RESERVED2[227]; /*!< Reserved                                                                        */
1994     __IO uint32_t HWCFGR;         /*!< RTC hardware configuration register,                       Address offset: 0x3F0 */
1995     __IO uint32_t VERR;            /*!< RTC version register,                                     Address offset: 0x3F4 */
1996     __IO uint32_t IPIDR;          /*!< RTC identification register,                               Address offset: 0x3F8 */
1997     __IO uint32_t SIDR;           /*!< RTC size identification register,                          Address offset: 0x3FC */
1998 } RTC_TypeDef;
1999 
2000 
2001 /**
2002   * @brief Tamper and Backup registers
2003   */
2004 typedef struct
2005 {
2006   __IO uint32_t CR1;           /*!< TAMP tamper control register 1,                         Address offset: 0x00 */
2007   __IO uint32_t CR2;           /*!< TAMP tamper control register 2,                         Address offset: 0x04 */
2008        uint32_t RESERVED;      /*!< Reserved                                                                     */
2009   __IO uint32_t FLTCR;         /*!< TAMP filter control register,                           Address offset: 0x0C */
2010   __IO uint32_t ATCR1;          /*!< TAMP active tamper control register,                   Address offset: 0x10 */
2011   __IO uint32_t ATSEEDR;       /*!< TAMP active tamper seed register,                       Address offset: 0x14 */
2012   __IO uint32_t ATOR;          /*!< TAMP active tamper output register,                     Address offset: 0x18 */
2013        uint32_t RESERVED1;     /*!< Reserved                                                                     */
2014   __IO uint32_t SMCR;          /*!< TAMP secure mode control register,                      Address offset: 0x20 */
2015        uint32_t RESERVED2[2];  /*!< Reserved, 0x024 - 0x028                                                      */
2016   __IO uint32_t IER;           /*!< TAMP interrupt enable register,                         Address offset: 0x2C */
2017   __IO uint32_t SR;            /*!< TAMP status register,                                   Address offset: 0x30 */
2018   __IO uint32_t MISR;          /*!< TAMP masked interrupt status register,                  Address offset: 0x34 */
2019   __IO uint32_t SMISR;         /*!< TAMP secure masked interrupt status register,           Address offset: 0x38 */
2020   __IO uint32_t SCR;           /*!< TAMP status clear register,                             Address offset: 0x3C */
2021   __IO uint32_t COUNTR;        /*!< TAMP monotonic counter register,                        Address offset: 0x40 */
2022   uint32_t RESERVED3[3];       /*!< Reserved, 0x044 - 0x04C                                                      */
2023   __IO uint32_t CFGR;          /*!< TAMP Configuration register,                            Address offset: 0x50 */
2024   uint32_t RESERVED4[43];      /*!< Reserved, 0x054 - 0x0FC                                                      */
2025   __IO uint32_t BKP0R;         /*!< TAMP backup register 0,                                 Address offset: 0x100 */
2026   __IO uint32_t BKP1R;         /*!< TAMP backup register 1,                                 Address offset: 0x104 */
2027   __IO uint32_t BKP2R;         /*!< TAMP backup register 2,                                 Address offset: 0x108 */
2028   __IO uint32_t BKP3R;         /*!< TAMP backup register 3,                                 Address offset: 0x10C */
2029   __IO uint32_t BKP4R;         /*!< TAMP backup register 4,                                 Address offset: 0x110 */
2030   __IO uint32_t BKP5R;         /*!< TAMP backup register 5,                                 Address offset: 0x114 */
2031   __IO uint32_t BKP6R;         /*!< TAMP backup register 6,                                 Address offset: 0x118 */
2032   __IO uint32_t BKP7R;         /*!< TAMP backup register 7,                                 Address offset: 0x11C */
2033   __IO uint32_t BKP8R;         /*!< TAMP backup register 8,                                 Address offset: 0x120 */
2034   __IO uint32_t BKP9R;         /*!< TAMP backup register 9,                                 Address offset: 0x124 */
2035   __IO uint32_t BKP10R;        /*!< TAMP backup register 10,                                Address offset: 0x128 */
2036   __IO uint32_t BKP11R;        /*!< TAMP backup register 11,                                Address offset: 0x12C */
2037   __IO uint32_t BKP12R;        /*!< TAMP backup register 12,                                Address offset: 0x130 */
2038   __IO uint32_t BKP13R;        /*!< TAMP backup register 13,                                Address offset: 0x134 */
2039   __IO uint32_t BKP14R;        /*!< TAMP backup register 14,                                Address offset: 0x138 */
2040   __IO uint32_t BKP15R;        /*!< TAMP backup register 15,                                Address offset: 0x13C */
2041   __IO uint32_t BKP16R;        /*!< TAMP backup register 16,                                Address offset: 0x140 */
2042   __IO uint32_t BKP17R;        /*!< TAMP backup register 17,                                Address offset: 0x144 */
2043   __IO uint32_t BKP18R;        /*!< TAMP backup register 18,                                Address offset: 0x148 */
2044   __IO uint32_t BKP19R;        /*!< TAMP backup register 19,                                Address offset: 0x14C */
2045   __IO uint32_t BKP20R;        /*!< TAMP backup register 20,                                Address offset: 0x150 */
2046   __IO uint32_t BKP21R;        /*!< TAMP backup register 21,                                Address offset: 0x154 */
2047   __IO uint32_t BKP22R;        /*!< TAMP backup register 22,                                Address offset: 0x158 */
2048   __IO uint32_t BKP23R;        /*!< TAMP backup register 23,                                Address offset: 0x15C */
2049   __IO uint32_t BKP24R;        /*!< TAMP backup register 24,                                Address offset: 0x160 */
2050   __IO uint32_t BKP25R;        /*!< TAMP backup register 25,                                Address offset: 0x164 */
2051   __IO uint32_t BKP26R;        /*!< TAMP backup register 26,                                Address offset: 0x168 */
2052   __IO uint32_t BKP27R;        /*!< TAMP backup register 27,                                Address offset: 0x16C */
2053   __IO uint32_t BKP28R;        /*!< TAMP backup register 28,                                Address offset: 0x170 */
2054   __IO uint32_t BKP29R;        /*!< TAMP backup register 29,                                Address offset: 0x174 */
2055   __IO uint32_t BKP30R;        /*!< TAMP backup register 30,                                Address offset: 0x178 */
2056   __IO uint32_t BKP31R;        /*!< TAMP backup register 31,                                Address offset: 0x17C */
2057        uint32_t RESERVED5[155]; /*!< Reserved, 0x180 - 0x3E8                                                      */
2058   __IO uint32_t HWCFGR2;        /*!< TAMP hardware configuration register,                  Address offset: 0x3EC */
2059   __IO uint32_t HWCFGR1;        /*!< TAMP hardware configuration register,                  Address offset: 0x3F0 */
2060   __IO uint32_t VERR;           /*!< TAMP version register,                                 Address offset: 0x3F4 */
2061   __IO uint32_t IPIDR;          /*!< TAMP identification register,                          Address offset: 0x3F8 */
2062   __IO uint32_t SIDR;           /*!< TAMP size identification register,                     Address offset: 0x3FC */
2063 
2064 } TAMP_TypeDef;
2065 
2066 
2067 /**
2068   * @brief Serial Audio Interface
2069   */
2070 
2071 typedef struct
2072 {
2073   __IO uint32_t GCR;           /*!< SAI global configuration register, Address offset: 0x00  */
2074   uint32_t      RESERVED0[16]; /*!< Reserved, 0x04 - 0x43                                    */
2075   __IO uint32_t PDMCR;         /*!< SAI PDM control register,          Address offset: 0x44  */
2076   __IO uint32_t PDMDLY;        /*!< SAI PDM delay register,            Address offset: 0x48  */
2077   uint32_t      RESERVED1[233]; /*!< Reserved, 0x4C - 0x3EC                                  */
2078   __IO uint32_t HWCFGR;        /*!< SAI HW Configuration register,     Address offset: 0x3F0 */
2079   __IO uint32_t VERR;          /*!< SAI PVersion register,             Address offset: 0x3F4 */
2080   __IO uint32_t IPIDR;           /*!< SAI Identification register,       Address offset: 0x3F8 */
2081   __IO uint32_t SIDR;          /*!< SAI Size Identification register,  Address offset: 0x3FC */
2082 } SAI_TypeDef;
2083 
2084 typedef struct
2085 {
2086   __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */
2087   __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */
2088   __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */
2089   __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */
2090   __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,       Address offset: 0x14 */
2091   __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */
2092   __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */
2093   __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */
2094 } SAI_Block_TypeDef;
2095 
2096 
2097 
2098 /**
2099   * @brief  Process Monitor Block
2100   */
2101 
2102 typedef struct
2103 {
2104   uint32_t Reserved;            /*!< Reserved, Address offset: 0x00 */
2105   __IO uint32_t SENS_CTRL;      /*!< PMB Sensor control,         Address offset: 0x04 */
2106   __IO uint32_t REF_COUNTER;    /*!< PMB Reference counter,      Address offset: 0x08 */
2107   __IO uint32_t SENSOR_STATUS;  /*!< PMB Sensor Status,          Address offset: 0x0C */
2108 }PMB_TypeDef;
2109 
2110 
2111 /**
2112   * @brief SPDIF-RX Interface
2113   */
2114 
2115 typedef struct
2116 {
2117   __IO uint32_t   CR;           /*!< Control register,                      Address offset: 0x00 */
2118   __IO uint32_t   IMR;          /*!< Interrupt mask register,               Address offset: 0x04 */
2119   __IO uint32_t   SR;           /*!< Status register,                       Address offset: 0x08 */
2120   __IO uint32_t   IFCR;         /*!< Interrupt Flag Clear register,         Address offset: 0x0C */
2121   __IO uint32_t   DR;           /*!< Data input register,                   Address offset: 0x10 */
2122   __IO uint32_t   CSR;          /*!< Channel Status register,               Address offset: 0x14 */
2123   __IO uint32_t   DIR;          /*!< Debug Information register,            Address offset: 0x18 */
2124   uint32_t        RESERVED2[246];   /*!< Reserved,                                0x1C   - 0x3F0 */
2125   __IO uint32_t   VERR;         /*!< SPDIFRX version register,             Address offset: 0x3F4 */
2126   __IO uint32_t   IPIDR;          /*!< SPDIFRX Identificationn register,     Address offset: 0x3F8 */
2127   __IO uint32_t   SIDR;         /*!< SPDIFRX Size Identification register, Address offset: 0x3FC */
2128 } SPDIFRX_TypeDef;
2129 
2130 
2131 /**
2132   * @brief Secure digital input/output Interface
2133   */
2134 
2135 typedef struct
2136 {
2137   __IO uint32_t POWER;          /*!< SDMMC power control register,             Address offset: 0x00 */
2138   __IO uint32_t CLKCR;          /*!< SDMMC clock control register,             Address offset: 0x04 */
2139   __IO uint32_t ARG;            /*!< SDMMC argument register,                  Address offset: 0x08 */
2140   __IO uint32_t CMD;            /*!< SDMMC command register,                   Address offset: 0x0C */
2141   __I uint32_t  RESPCMD;        /*!< SDMMC command response register,          Address offset: 0x10 */
2142   __I uint32_t  RESP1;          /*!< SDMMC response 1 register,                Address offset: 0x14 */
2143   __I uint32_t  RESP2;          /*!< SDMMC response 2 register,                Address offset: 0x18 */
2144   __I uint32_t  RESP3;          /*!< SDMMC response 3 register,                Address offset: 0x1C */
2145   __I uint32_t  RESP4;          /*!< SDMMC response 4 register,                Address offset: 0x20 */
2146   __IO uint32_t DTIMER;         /*!< SDMMC data timer register,                Address offset: 0x24 */
2147   __IO uint32_t DLEN;           /*!< SDMMC data length register,               Address offset: 0x28 */
2148   __IO uint32_t DCTRL;          /*!< SDMMC data control register,              Address offset: 0x2C */
2149   __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,              Address offset: 0x30 */
2150   __I uint32_t  STA;            /*!< SDMMC status register,                    Address offset: 0x34 */
2151   __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,           Address offset: 0x38 */
2152   __IO uint32_t MASK;           /*!< SDMMC mask register,                      Address offset: 0x3C */
2153   __IO uint32_t ACKTIME;        /*!< SDMMC Acknowledgement timer register,     Address offset: 0x40 */
2154   uint32_t      RESERVED0[3];   /*!< Reserved, 0x44 - 0x4C - 0x4C                                   */
2155   __IO uint32_t IDMACTRL;       /*!< SDMMC DMA control register,               Address offset: 0x50 */
2156   __IO uint32_t IDMABSIZE;      /*!< SDMMC DMA buffer size register,           Address offset: 0x54 */
2157   __IO uint32_t IDMABASE0;      /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58 */
2158   __IO uint32_t IDMABASE1;      /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */
2159   uint32_t      RESERVED1[1];   /*!< Reserved, 0x60                                            */
2160   __IO uint32_t IDMALAR;        /*!< SDMMC DMA linked list address register,   Address offset: 0x64 */
2161   __IO uint32_t IDMABAR;        /*!< SDMMC DMA linked list memory base register, Address offset: 0x68 */
2162   uint32_t      RESERVED2[5];   /*!< Reserved, 0x6C-0x7C                                            */
2163   __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,               Address offset: 0x80 - 0xBC */
2164   uint32_t      RESERVED3[220]; /*!< Reserved, 0xBC-0x3F4                                           */
2165   __IO uint32_t VERR;           /*!< SDMMC version register,                  Address offset: 0x3F4 */
2166   __IO uint32_t IPIDR;           /*!< SDMMC identification register,          Address offset: 0x3F8 */
2167   __IO uint32_t SIDR;           /*!< SDMMCsize ID register,                   Address offset: 0x3FC */
2168 } SDMMC_TypeDef;
2169 
2170 
2171 /**
2172   * @brief Delay Block DLYB
2173   */
2174 
2175 typedef struct
2176 {
2177   __IO uint32_t CR;          /*!< DELAY BLOCK control register,          Address offset: 0x00 */
2178   __IO uint32_t CFGR;        /*!< DELAY BLOCK configuration register,    Address offset: 0x04 */
2179   uint32_t  Reserved[249];   /* Reserved                         Address offset: 0x08 - 0x3F0 */
2180   __IO uint32_t VERR;        /*!< DELAY BLOCK Version register,         Address offset: 0x3F4 */
2181   __IO uint32_t IPIDR;       /*!< DELAY BLOCK Identification register,  Address offset: 0x3F8 */
2182   __IO uint32_t SIDR;        /*!< DELAY BLOCK Size ID register,         Address offset: 0x3FC */
2183 } DLYB_TypeDef;
2184 
2185 /**
2186   * @brief HW Semaphore HSEM
2187   */
2188 
2189 typedef struct
2190 {
2191   __IO uint32_t R[32];      /*!< 2-step write lock and read back registers,     Address offset: 00h-7Ch  */
2192   __IO uint32_t RLR[32];    /*!< 1-step read lock registers,                    Address offset: 80h-FCh  */
2193   __IO uint32_t C1IER;      /*!< HSEM Interrupt 0 enable register ,             Address offset: 100h     */
2194   __IO uint32_t C1ICR;      /*!< HSEM Interrupt 0 clear register ,              Address offset: 104h     */
2195   __IO uint32_t C1ISR;      /*!< HSEM Interrupt 0 Status register ,             Address offset: 108h     */
2196   __IO uint32_t C1MISR;     /*!< HSEM Interrupt 0 Masked Status register ,      Address offset: 10Ch     */
2197   __IO uint32_t C2IER;      /*!< HSEM Interrupt 1 enable register ,             Address offset: 110h     */
2198   __IO uint32_t C2ICR;      /*!< HSEM Interrupt 1 clear register ,              Address offset: 114h     */
2199   __IO uint32_t C2ISR;      /*!< HSEM Interrupt 1 Status register ,             Address offset: 118h     */
2200   __IO uint32_t C2MISR;     /*!< HSEM Interrupt 1 Masked Status register ,      Address offset: 11Ch     */
2201    uint32_t  Reserved[8];        /* Reserved                                         Address offset: 120h-13Ch*/
2202   __IO uint32_t CR;         /*!< HSEM Semaphore clear register ,                Address offset: 140h      */
2203   __IO uint32_t KEYR;       /*!< HSEM Semaphore clear key register ,            Address offset: 144h      */
2204   uint32_t  Reserved1[169];      /* Reserved                                         Address offset: 148h-3E8h */
2205   __IO uint32_t HWCFGR2;    /*!< HSEM Hardware Configuration Register 2 ,       Address offset: 3ECh      */
2206   __IO uint32_t HWCFGR1;    /*!< HSEM Hardware Configuration Register 1 ,       Address offset: 3F0h      */
2207   __IO uint32_t VERR;       /*!< HSEM IP Version Register ,                     Address offset: 3F4h      */
2208   __IO uint32_t IPIDR;      /*!< HSEM IP Identification Register ,              Address offset: 3F8h      */
2209   __IO uint32_t SIDR;      /*!< HSEM Size Identification Register ,             Address offset: 3FCh      */
2210 } HSEM_TypeDef;
2211 
2212 typedef struct
2213 {
2214   __IO uint32_t IER;        /*!< HSEM interrupt enable register ,                Address offset:   0h     */
2215   __IO uint32_t ICR;        /*!< HSEM interrupt clear register ,                 Address offset:   4h     */
2216   __IO uint32_t ISR;        /*!< HSEM interrupt status register ,                Address offset:   8h     */
2217   __IO uint32_t MISR;       /*!< HSEM masked interrupt status register ,         Address offset:   Ch     */
2218 } HSEM_Common_TypeDef;
2219 
2220 /**
2221   * @brief Serial Peripheral Interface
2222   */
2223 
2224 typedef struct
2225 {
2226   __IO uint32_t CR1;          /*!< SPI Control register 1,                             Address offset: 0x00 */
2227   __IO uint32_t CR2;          /*!< SPI Control register 2,                             Address offset: 0x04 */
2228   __IO uint32_t CFG1;         /*!< SPI Status register,                                Address offset: 0x08 */
2229   __IO uint32_t CFG2;         /*!< SPI Status register,                                Address offset: 0x0C */
2230   __IO uint32_t IER;          /*!< SPI data register,                                  Address offset: 0x10 */
2231   __IO uint32_t SR;           /*!< SPI data register,                                  Address offset: 0x14 */
2232   __IO uint32_t IFCR;         /*!< SPI data register,                                  Address offset: 0x18 */
2233   uint32_t      RESERVED0;    /*!< SPI data register,                                  Address offset: 0x1C */
2234   __IO uint32_t TXDR;         /*!< SPI data register,                                  Address offset: 0x20 */
2235   uint32_t      RESERVED1[3]; /*!< Reserved, 0x24-0x2C                                                      */
2236   __IO uint32_t RXDR;         /*!< SPI data register,                                  Address offset: 0x30 */
2237   uint32_t      RESERVED2[3]; /*!< Reserved, 0x34-0x3C                                                      */
2238   __IO uint32_t CRCPOLY;     /*!< SPI data register,                                   Address offset: 0x40 */
2239   __IO uint32_t TXCRC;       /*!< SPI data register,                                   Address offset: 0x44 */
2240   __IO uint32_t RXCRC;       /*!< SPI data register,                                   Address offset: 0x48 */
2241   __IO uint32_t UDRDR;       /*!< SPI data register,                                   Address offset: 0x4C */
2242   __IO uint32_t I2SCFGR;     /*!< SPI data register,                                   Address offset: 0x50 */
2243   uint32_t      RESERVED3[231]; /*!< Reserved, 0x54-0x3EC                                                   */
2244   __IO uint32_t HWCFGR;       /*!< SPI HW Configuration register,                     Address offset: 0x3F0 */
2245   __IO uint32_t VERR;         /*!< SPI Version register,                              Address offset: 0x3F4 */
2246   __IO uint32_t IPIDR;        /*!< SPI identification register,                       Address offset: 0x3F8 */
2247   __IO uint32_t SIDR;         /*!< SPI Size Identification register,                  Address offset: 0x3FC */
2248 } SPI_TypeDef;
2249 
2250 /**
2251   * @brief QUAD Serial Peripheral Interface
2252   */
2253 
2254 typedef struct
2255 {
2256   __IO uint32_t CR;       /*!< QUADSPI Control register,                           Address offset: 0x00 */
2257   __IO uint32_t DCR;      /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */
2258   __IO uint32_t SR;       /*!< QUADSPI Status register,                            Address offset: 0x08 */
2259   __IO uint32_t FCR;      /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */
2260   __IO uint32_t DLR;      /*!< QUADSPI Data Length register,                       Address offset: 0x10 */
2261   __IO uint32_t CCR;      /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */
2262   __IO uint32_t AR;       /*!< QUADSPI Address register,                           Address offset: 0x18 */
2263   __IO uint32_t ABR;      /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */
2264   __IO uint32_t DR;       /*!< QUADSPI Data register,                              Address offset: 0x20 */
2265   __IO uint32_t PSMKR;    /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */
2266   __IO uint32_t PSMAR;    /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */
2267   __IO uint32_t PIR;      /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */
2268   __IO uint32_t LPTR;     /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */
2269   uint32_t      RESERVED[239]; /*!< Reserved, 0x34-0x3EC                                                */
2270   __IO uint32_t HWCFGR;   /*!< QUADSPI HW configuration register,                  Address offset: 0x3F0*/
2271   __IO uint32_t VERR;     /*!< QUADSPI version register,                           Address offset: 0x3F4*/
2272   __IO uint32_t IPIDR;    /*!< QUADSPI dentification register,                     Address offset: 0x3F8*/
2273   __IO uint32_t SIDR;    /*!< QUADSPI size identification register,                Address offset: 0x3FC*/
2274 } QUADSPI_TypeDef;
2275 
2276 /**
2277   * @brief Temperature Sensor
2278   */
2279 /* TMPSENS has been renamed in DTS*/
2280 typedef struct
2281 {
2282   __IO uint32_t CFGR1;    /*!< Temperature Sensor Configuration Register 1,         Address offset: 0x00 */
2283   uint32_t RESERVED0;     /*!< Reserved,                                            Address offset: 0x04 */
2284   __IO uint32_t T0VALR1;  /*!< Temperature sensor T0 Value Register 1,              Address offset: 0x08 */
2285   uint32_t RESERVED1;     /*!< Reserved,                                            Address offset: 0x0C */
2286   __IO uint32_t RAMPVALR; /*!< Temperature sensor Ramp Value Register,              Address offset: 0x10 */
2287   __IO uint32_t ITR1;     /*!< Temperature sensor Interrupt Threshold Register 1,   Address offset: 0x14 */
2288   uint32_t RESERVED2;     /*!< Reserved,                                            Address offset: 0x18 */
2289   __IO uint32_t DR;       /*!< Temperature sensor Data Register,                    Address offset: 0x1C */
2290   __IO uint32_t SR;       /*!< Temperature sensor Status Register,                  Address offset: 0x20 */
2291   __IO uint32_t ITENR;    /*!< Temperature sensor Interrupt Enable Register,        Address offset: 0x24 */
2292   __IO uint32_t ICIFR;    /*!< Temperature sensor clear interrupt flag register,    Address offset: 0x28 */
2293   __IO uint32_t OR;       /*!< Temperature sensor option register,                  Address offset: 0x2C */
2294 }DTS_TypeDef;
2295 
2296 /**
2297   * @brief TIM
2298   */
2299 
2300 typedef struct
2301 {
2302   __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */
2303   __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */
2304   __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */
2305   __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */
2306   __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */
2307   __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */
2308   __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */
2309   __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */
2310   __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */
2311   __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */
2312   __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */
2313   __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */
2314   __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */
2315   __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */
2316   __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */
2317   __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */
2318   __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */
2319   __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */
2320   __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */
2321   __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */
2322   uint32_t      RESERVED0;   /*!< Reserved,                                 Address offset: 0x50 */
2323   __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */
2324   __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */
2325   __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */
2326   __IO uint32_t AF1;         /*!< TIM alternate function option register 1, Address offset: 0x60 */
2327   __IO uint32_t AF2;         /*!< TIM alternate function option register 2, Address offset: 0x64 */
2328   __IO uint32_t TISEL;       /*!< TIM Input Selection register,             Address offset: 0x68 */
2329   uint32_t  RESERVED1[226];  /*!< Reserved,                                 Address offset: 0x6C-0x3F0 */
2330   __IO uint32_t VERR;        /*!< TIM version register,                     Address offset: 0x3F4 */
2331   __IO uint32_t IPIDR;       /*!< TIM Identification register,              Address offset: 0x3F8 */
2332   __IO uint32_t SIDR;        /*!< TIM Size Identification register,         Address offset: 0x3FC */
2333 } TIM_TypeDef;
2334 
2335 /**
2336   * @brief LPTIMIMER
2337   */
2338 typedef struct
2339 {
2340   __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */
2341   __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */
2342   __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */
2343   __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                       Address offset: 0x0C */
2344   __IO uint32_t CR;       /*!< LPTIM Control register,                             Address offset: 0x10 */
2345   __IO uint32_t CMP;      /*!< LPTIM Compare register,                             Address offset: 0x14 */
2346   __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                          Address offset: 0x18 */
2347   __IO uint32_t CNT;      /*!< LPTIM Counter register,                             Address offset: 0x1C */
2348   uint16_t  RESERVED1;    /*!< Reserved, 0x20                                                 */
2349   __IO uint32_t CFGR2;    /*!< LPTIM Option register,                              Address offset: 0x24 */
2350   uint32_t  RESERVED2[242];    /*!< Reserved, 0x28-0x3EC                                                */
2351   __IO uint32_t HWCFGR;   /*!< LPTIM HW configuration register,                    Address offset: 0x3F0 */
2352   __IO uint32_t VERR;     /*!< LPTIM version register,                             Address offset: 0x3F4 */
2353   __IO uint32_t PIDR;     /*!< LPTIM Identification register,                      Address offset: 0x3F8 */
2354   __IO uint32_t SIDR;     /*!< LPTIM Size Identification register,                 Address offset: 0x3FC */
2355 } LPTIM_TypeDef;
2356 
2357 /**
2358   * @brief Comparator
2359   */
2360 typedef struct
2361 {
2362   __IO uint32_t SR;        /*!< Comparator status register,                    Address offset: 0x00 */
2363   __IO uint32_t ICFR;      /*!< Comparator interrupt clear flag register,      Address offset: 0x04 */
2364   __IO uint32_t OR;        /*!< Comparator option register,                    Address offset: 0x08 */
2365 } COMPOPT_TypeDef;
2366 
2367 typedef struct
2368 {
2369   __IO uint32_t CFGR;      /*!< Comparator configuration register  ,           Address offset: 0x00 */
2370 } COMP_TypeDef;
2371 
2372 typedef struct
2373 {
2374   __IO uint32_t CFGR;       /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
2375 } COMP_Common_TypeDef;
2376 /**
2377   * @brief Universal Synchronous Asynchronous Receiver Transmitter
2378   */
2379 
2380 typedef struct
2381 {
2382   __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */
2383   __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */
2384   __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
2385   __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */
2386   __IO uint16_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
2387   uint16_t  RESERVED2;  /*!< Reserved, 0x12                                                 */
2388   __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */
2389   __IO uint16_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
2390   uint16_t  RESERVED3;  /*!< Reserved, 0x1A                                                 */
2391   __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
2392   __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
2393   __IO uint16_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
2394   uint16_t  RESERVED4;  /*!< Reserved, 0x26                                                 */
2395   __IO uint16_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
2396   uint16_t  RESERVED5;  /*!< Reserved, 0x2A                                                 */
2397   __IO uint32_t PRESC;  /*!< USART clock Prescaler register,           Address offset: 0x2C */
2398   uint32_t  RESERVED6[239];  /*!< Reserved,                                    0x30 - 0x3E8 */
2399   __IO uint32_t HWCFGR2;  /*!< USART Configuration2 register,          Address offset: 0x3EC */
2400   __IO uint32_t HWCFGR1;  /*!< USART Configuration1 register,          Address offset: 0x3F0 */
2401   __IO uint32_t VERR;   /*!< USART Version register,                   Address offset: 0x3F4 */
2402   __IO uint32_t IPIDR;  /*!< USART Identification register,            Address offset: 0x3F8 */
2403   __IO uint32_t SIDR;   /*!< USART clock Size Identification register, Address offset: 0x3FC */
2404 
2405 } USART_TypeDef;
2406 
2407 /**
2408   * @brief Single Wire Protocol Master Interface SPWMI
2409   */
2410 typedef struct
2411 {
2412   __IO uint32_t CR;          /*!< SWPMI Configuration/Control register,     Address offset: 0x00 */
2413   __IO uint32_t BRR;         /*!< SWPMI bitrate register,                   Address offset: 0x04 */
2414     uint32_t  RESERVED1;     /*!< Reserved, 0x08                                                 */
2415   __IO uint32_t ISR;         /*!< SWPMI Interrupt and Status register,      Address offset: 0x0C */
2416   __IO uint32_t ICR;         /*!< SWPMI Interrupt Flag Clear register,      Address offset: 0x10 */
2417   __IO uint32_t IER;         /*!< SWPMI Interrupt Enable register,          Address offset: 0x14 */
2418   __IO uint32_t RFL;         /*!< SWPMI Receive Frame Length register,      Address offset: 0x18 */
2419   __IO uint32_t TDR;         /*!< SWPMI Transmit data register,             Address offset: 0x1C */
2420   __IO uint32_t RDR;         /*!< SWPMI Receive data register,              Address offset: 0x20 */
2421   __IO uint32_t OR;          /*!< SWPMI Option register,                    Address offset: 0x24 */
2422 } SWPMI_TypeDef;
2423 
2424 /**
2425   * @brief Window WATCHDOG
2426   */
2427 
2428 typedef struct
2429 {
2430   __IO uint32_t CR;      /*!< WWDG Control register,        Address offset:  0x00 */
2431   __IO uint32_t CFR;     /*!< WWDG Configuration register,  Address offset:  0x04 */
2432   __IO uint32_t SR;      /*!< WWDG Status register,         Address offset:  0x08 */
2433   uint32_t  RESERVED1[249];   /*!< Reserved,                         0x0C - 0x3EC */
2434   __IO uint32_t HWCFGR;  /*!< WWDG HW Config register,      Address offset: 0x3F0 */
2435   __IO uint32_t VERR;    /*!< WWDG Version register,        Address offset: 0x3F4 */
2436   __IO uint32_t IPIDR;   /*!< WWDG Identification register, Address offset: 0x3F8 */
2437   __IO uint32_t SIDR;    /*!< WWDG Size ID register,        Address offset: 0x3FC */
2438 
2439 } WWDG_TypeDef;
2440 /**
2441   * @brief HASH
2442   */
2443 
2444 typedef struct
2445 {
2446   __IO uint32_t CR;               /*!< HASH control register,          Address offset: 0x00        */
2447   __IO uint32_t DIN;              /*!< HASH data input register,       Address offset: 0x04        */
2448   __IO uint32_t STR;              /*!< HASH start register,            Address offset: 0x08        */
2449   __IO uint32_t HR[5];            /*!< HASH digest registers,          Address offset: 0x0C-0x1C   */
2450   __IO uint32_t IMR;              /*!< HASH interrupt enable register, Address offset: 0x20        */
2451   __IO uint32_t SR;               /*!< HASH status register,           Address offset: 0x24        */
2452        uint32_t RESERVED[52];     /*!< Reserved, 0x28-0xF4                                         */
2453   __IO uint32_t CSR[54];          /*!< HASH context swap registers,    Address offset: 0x0F8-0x1CC */
2454        uint32_t RESERVED2[80];
2455   __IO uint32_t HR2[8];
2456        uint32_t RESERVED3[48];
2457   __IO uint32_t HWCFGR;           /*!< HASH Hardware configuration register, Address offset: 0x3F0 */
2458   __IO uint32_t VERR;           /*!< HASH Version register,                   Address offset: 0x3F4 */
2459   __IO uint32_t IPIDR;           /*!< HASH identification register,             Address offset: 0x3F8 */
2460   __IO uint32_t MID;           /*!< HASH Hardware Magic ID register,         Address offset: 0x3FC */
2461 } HASH_TypeDef;
2462 
2463 /**
2464   * @brief HASH_DIGEST
2465   */
2466 
2467 typedef struct
2468 {
2469   __IO uint32_t HR[8];     /*!< HASH digest registers,          Address offset: 0x310-0x32C */
2470 } HASH_DIGEST_TypeDef;
2471 
2472 
2473 /**
2474   * @brief RNG
2475   */
2476 
2477 typedef struct
2478 {
2479   __IO uint32_t CR;      /*!< RNG control register,             Address offset: 0x00  */
2480   __IO uint32_t SR;      /*!< RNG status register,              Address offset: 0x04  */
2481   __IO uint32_t DR;      /*!< RNG data register,                Address offset: 0x08  */
2482   __IO uint32_t RESERVED1[249];   /*!< Reserved                 0x0C - 0x3EC          */
2483   __IO uint32_t HWCFGR;  /*!< RNG HW Configuration register,    Address offset: 0x3F0 */
2484   __IO uint32_t VERR;    /*!< RNG Version register,             Address offset: 0x3F4 */
2485   __IO uint32_t IPIDR;   /*!< RNG identification register,      Address offset: 0x3F8 */
2486   __IO uint32_t SIDR;    /*!< RNG HW magic ID,                  Address offset: 0x3FC */
2487 } RNG_TypeDef;
2488 
2489 /**
2490   * @brief Inter-Processor Communication
2491   */
2492 typedef struct
2493 {
2494   __IO uint32_t C1CR;             /*!< Inter-Processor Communication: C1 control register,                  Address offset: 0x000 */
2495   __IO uint32_t C1MR ;            /*!< Inter-Processor Communication: C1 mask register,                     Address offset: 0x004 */
2496   __IO uint32_t C1SCR;            /*!< Inter-Processor Communication: C1 status set clear register,         Address offset: 0x008 */
2497   __IO uint32_t C1TOC2SR;         /*!< Inter-Processor Communication: C1 to processor M4  status register,  Address offset: 0x00C */
2498   __IO uint32_t C2CR;             /*!< Inter-Processor Communication: C2 control register,                  Address offset: 0x010 */
2499   __IO uint32_t C2MR ;            /*!< Inter-Processor Communication: C2 mask register,                     Address offset: 0x014 */
2500   __IO uint32_t C2SCR;            /*!< Inter-Processor Communication: C2 status set clear register,         Address offset: 0x018 */
2501   __IO uint32_t C2TOC1SR;         /*!< Inter-Processor Communication: C2 to processor M4 status register,   Address offset: 0x01C */
2502   __IO uint32_t RESERVED1[244];   /*!< Reserved                                                                                   */
2503   __IO uint32_t HWCFGR;           /*!< Inter-Processor Communication hardware configuration register,       Address offset: 0x3F0 */
2504   __IO uint32_t VER;             /*!< Inter-Processor Communication version register,                      Address offset: 0x3F4 */
2505   __IO uint32_t ID;            /*!< Inter-Processor Communication identification register,               Address offset: 0x3F8 */
2506   __IO uint32_t SID;             /*!< Inter-Processor Communication size identification register,          Address offset: 0x3FC */
2507 } IPCC_TypeDef;
2508 
2509 typedef struct
2510 {
2511   __IO uint32_t CR;               /*!< Control register,                                                    Address offset: 0x000 */
2512   __IO uint32_t MR;               /*!< Mask register,                                                       Address offset: 0x004 */
2513   __IO uint32_t SCR;              /*!< Status set clear register,                                           Address offset: 0x008 */
2514   __IO uint32_t SR;               /*!< Status register,                                                     Address offset: 0x00C */
2515 } IPCC_CommonTypeDef;
2516 
2517 /**
2518   * @brief MDIOS
2519   */
2520 
2521 typedef struct
2522 {
2523   __IO uint32_t CR;               /*!< Control register,                                                    Address offset: 0x000 */
2524   __IO uint32_t WRFR;             /*!< Write Flag register,                                                 Address offset: 0x004 */
2525   __IO uint32_t CWRFR;            /*!< Clear Write Flag register,                                           Address offset: 0x008 */
2526   __IO uint32_t RDFR;             /*!< Read Flag register,                                                  Address offset: 0x00C */
2527   __IO uint32_t CRDFR;            /*!< Clear Read Flag register,                                            Address offset: 0x010 */
2528   __IO uint32_t SR;               /*!< Status register,                                                     Address offset: 0x014 */
2529   __IO uint32_t CLRFR;            /*!< Clear Flag register,                                                 Address offset: 0x018 */
2530   uint32_t RESERVED[57];          /*!< Reserved,                                                    Address offset: 0x01C - 0x0FC */
2531   __IO uint32_t DINR0;            /*!< Input Data register 0                                                Address offset: 0x100 */
2532   __IO uint32_t DINR1;            /*!< Input Data register 1                                                Address offset: 0x104 */
2533   __IO uint32_t DINR2;            /*!< Input Data register 2                                                Address offset: 0x108 */
2534   __IO uint32_t DINR3;            /*!< Input Data register 3                                                Address offset: 0x10C */
2535   __IO uint32_t DINR4;            /*!< Input Data register 4                                                Address offset: 0x110 */
2536   __IO uint32_t DINR5;            /*!< Input Data register 5                                                Address offset: 0x114 */
2537   __IO uint32_t DINR6;            /*!< Input Data register 6                                                Address offset: 0x118 */
2538   __IO uint32_t DINR7;            /*!< Input Data register 7                                                Address offset: 0x11C */
2539   __IO uint32_t DINR8;            /*!< Input Data register 8                                                Address offset: 0x120 */
2540   __IO uint32_t DINR9;            /*!< Input Data register 9                                                Address offset: 0x124 */
2541   __IO uint32_t DINR10;           /*!< Input Data register 10                                               Address offset: 0x128 */
2542   __IO uint32_t DINR11;           /*!< Input Data register 11                                               Address offset: 0x12C */
2543   __IO uint32_t DINR12;           /*!< Input Data register 12                                               Address offset: 0x130 */
2544   __IO uint32_t DINR13;           /*!< Input Data register 13                                               Address offset: 0x134 */
2545   __IO uint32_t DINR14;           /*!< Input Data register 14                                               Address offset: 0x138 */
2546   __IO uint32_t DINR15;           /*!< Input Data register 15                                               Address offset: 0x13C */
2547   __IO uint32_t DINR16;           /*!< Input Data register 16                                               Address offset: 0x140 */
2548   __IO uint32_t DINR17;           /*!< Input Data register 17                                               Address offset: 0x144 */
2549   __IO uint32_t DINR18;           /*!< Input Data register 18                                               Address offset: 0x148 */
2550   __IO uint32_t DINR19;           /*!< Input Data register 19                                               Address offset: 0x14C */
2551   __IO uint32_t DINR20;           /*!< Input Data register 20                                               Address offset: 0x150 */
2552   __IO uint32_t DINR21;           /*!< Input Data register 21                                               Address offset: 0x154 */
2553   __IO uint32_t DINR22;           /*!< Input Data register 22                                               Address offset: 0x158 */
2554   __IO uint32_t DINR23;           /*!< Input Data register 23                                               Address offset: 0x15C */
2555   __IO uint32_t DINR24;           /*!< Input Data register 24                                               Address offset: 0x160 */
2556   __IO uint32_t DINR25;           /*!< Input Data register 25                                               Address offset: 0x164 */
2557   __IO uint32_t DINR26;           /*!< Input Data register 26                                               Address offset: 0x168 */
2558   __IO uint32_t DINR27;           /*!< Input Data register 27                                               Address offset: 0x16C */
2559   __IO uint32_t DINR28;           /*!< Input Data register 28                                               Address offset: 0x170 */
2560   __IO uint32_t DINR29;           /*!< Input Data register 29                                               Address offset: 0x174 */
2561   __IO uint32_t DINR30;           /*!< Input Data register 30                                               Address offset: 0x178 */
2562   __IO uint32_t DINR31;           /*!< Input Data register 31                                               Address offset: 0x17C */
2563   __IO uint32_t DOUTR0;           /*!< Output Data register 0                                               Address offset: 0x180 */
2564   __IO uint32_t DOUTR1;           /*!< Output Data register 1                                               Address offset: 0x184 */
2565   __IO uint32_t DOUTR2;           /*!< Output Data register 2                                               Address offset: 0x188 */
2566   __IO uint32_t DOUTR3;           /*!< Output Data register 3                                               Address offset: 0x18C */
2567   __IO uint32_t DOUTR4;           /*!< Output Data register 4                                               Address offset: 0x190 */
2568   __IO uint32_t DOUTR5;           /*!< Output Data register 5                                               Address offset: 0x194 */
2569   __IO uint32_t DOUTR6;           /*!< Output Data register 6                                               Address offset: 0x198 */
2570   __IO uint32_t DOUTR7;           /*!< Output Data register 7                                               Address offset: 0x19C */
2571   __IO uint32_t DOUTR8;           /*!< Output Data register 8                                               Address offset: 0x1A0 */
2572   __IO uint32_t DOUTR9;           /*!< Output Data register 9                                               Address offset: 0x1A4 */
2573   __IO uint32_t DOUTR10;          /*!< Output Data register 10                                              Address offset: 0x1A8 */
2574   __IO uint32_t DOUTR11;          /*!< Output Data register 11                                              Address offset: 0x1AC */
2575   __IO uint32_t DOUTR12;          /*!< Output Data register 12                                              Address offset: 0x1B0 */
2576   __IO uint32_t DOUTR13;          /*!< Output Data register 13                                              Address offset: 0x1B4 */
2577   __IO uint32_t DOUTR14;          /*!< Output Data register 14                                              Address offset: 0x1B8 */
2578   __IO uint32_t DOUTR15;          /*!< Output Data register 15                                              Address offset: 0x1BC */
2579   __IO uint32_t DOUTR16;          /*!< Output Data register 16                                              Address offset: 0x1C0 */
2580   __IO uint32_t DOUTR17;          /*!< Output Data register 17                                              Address offset: 0x1C4 */
2581   __IO uint32_t DOUTR18;          /*!< Output Data register 18                                              Address offset: 0x1C8 */
2582   __IO uint32_t DOUTR19;          /*!< Output Data register 19                                              Address offset: 0x1CC */
2583   __IO uint32_t DOUTR20;          /*!< Output Data register 20                                              Address offset: 0x1D0 */
2584   __IO uint32_t DOUTR21;          /*!< Output Data register 21                                              Address offset: 0x1D4 */
2585   __IO uint32_t DOUTR22;          /*!< Output Data register 22                                              Address offset: 0x1D8 */
2586   __IO uint32_t DOUTR23;          /*!< Output Data register 23                                              Address offset: 0x1DC */
2587   __IO uint32_t DOUTR24;          /*!< Output Data register 24                                              Address offset: 0x1E0 */
2588   __IO uint32_t DOUTR25;          /*!< Output Data register 25                                              Address offset: 0x1E4 */
2589   __IO uint32_t DOUTR26;          /*!< Output Data register 26                                              Address offset: 0x1E8 */
2590   __IO uint32_t DOUTR27;          /*!< Output Data register 27                                              Address offset: 0x1EC */
2591   __IO uint32_t DOUTR28;          /*!< Output Data register 28                                              Address offset: 0x1F0 */
2592   __IO uint32_t DOUTR29;          /*!< Output Data register 29                                              Address offset: 0x1F4 */
2593   __IO uint32_t DOUTR30;          /*!< Output Data register 30                                              Address offset: 0x1F8 */
2594   __IO uint32_t DOUTR31;          /*!< Output Data register 31                                              Address offset: 0x1FC */
2595   uint32_t RESERVED1[124]; /*!< Reserved                                     0x200 - 0x3EC */
2596   __IO uint32_t HWCFGR;    /*!< MDIOS HW Configuration register,     Address offset: 0x3F0 */
2597   __IO uint32_t VERR;      /*!< MDIOS Version register,              Address offset: 0x3F4 */
2598   __IO uint32_t IPIDR;     /*!< MDIOS identification register,       Address offset: 0x3F8 */
2599   __IO uint32_t SIDR;      /*!< MDIOS Size ID register,              Address offset: 0x3FC */
2600 } MDIOS_TypeDef;
2601 
2602 
2603 /**
2604   * @brief USB_OTG_Core_Registers
2605   */
2606 typedef struct
2607 {
2608  __IO uint32_t GOTGCTL;               /*!< USB_OTG Control and Status Register          000h */
2609   __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */
2610   __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */
2611   __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */
2612   __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */
2613   __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */
2614   __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */
2615   __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */
2616   __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */
2617   __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */
2618   __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */
2619   __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */
2620   __IO uint32_t GI2CCTL;              /*!< I2C Access Register                          030h */
2621   uint32_t Reserved30;                /*!< Reserved                                     034h */
2622   __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */
2623   __IO uint32_t CID;                  /*!< User ID Register                             03Ch */
2624   uint32_t  Reserved5[4];             /*!< Reserved                                040h-048h */
2625   uint32_t  Reserved6;                /*!< Reserved                                     050h */
2626   __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */
2627   uint32_t  Reserved43[42];         /*!< Reserved                                  058h-0FFh */
2628   __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */
2629   __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */
2630 } USB_OTG_GlobalTypeDef;
2631 
2632 
2633 /**
2634   * @brief USB_OTG_device_Registers
2635   */
2636 typedef struct
2637 {
2638   __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */
2639   __IO uint32_t DCTL;            /*!< dev Control Register         804h */
2640   __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */
2641   uint32_t Reserved0C;           /*!< Reserved                     80Ch */
2642   __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */
2643   __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */
2644   __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */
2645   __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */
2646   uint32_t  Reserved20;          /*!< Reserved                     820h */
2647   uint32_t Reserved9;            /*!< Reserved                     824h */
2648   __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */
2649   __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */
2650   __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */
2651   __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */
2652   __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */
2653   __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */
2654   uint32_t Reserved40;           /*!< dedicated EP mask            840h */
2655   __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */
2656   uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */
2657   __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */
2658 } USB_OTG_DeviceTypeDef;
2659 
2660 
2661 /**
2662   * @brief USB_OTG_IN_Endpoint-Specific_Register
2663   */
2664 typedef struct
2665 {
2666   __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */
2667   uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */
2668   __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */
2669   uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */
2670   __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */
2671   __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */
2672   __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
2673   uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
2674 } USB_OTG_INEndpointTypeDef;
2675 
2676 
2677 /**
2678   * @brief USB_OTG_OUT_Endpoint-Specific_Registers
2679   */
2680 typedef struct
2681 {
2682   __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */
2683   uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */
2684   __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */
2685   uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */
2686   __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */
2687   __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */
2688   uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
2689 } USB_OTG_OUTEndpointTypeDef;
2690 
2691 
2692 /**
2693   * @brief USB_OTG_Host_Mode_Register_Structures
2694   */
2695 typedef struct
2696 {
2697   __IO uint32_t HCFG;             /*!< Host Configuration Register           400h */
2698   __IO uint32_t HFIR;             /*!< Host Frame Interval Register          404h */
2699   __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining        408h */
2700   uint32_t Reserved40C;           /*!< Reserved                              40Ch */
2701   __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status   410h */
2702   __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register  414h */
2703   __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask      418h */
2704   __IO uint32_t HFLBADDR;         /*!< Host frame list base address register 41Ch */
2705   uint32_t Reserved420[8];        /*!< Reserved                              420h */
2706   __IO uint32_t HPRT;             /*!< Host port control and status register 440h */
2707 } USB_OTG_HostTypeDef;
2708 
2709 /**
2710   * @brief USB_OTG_Host_Channel_Specific_Registers
2711   */
2712 typedef struct
2713 {
2714   __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */
2715   __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */
2716   __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */
2717   __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */
2718   __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */
2719   __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */
2720   uint32_t Reserved0;             /*!< Reserved                                 518h */
2721   __IO uint32_t HCDMAB;           /*!< Host Channel DMA Address Buffer Register 51Ch */
2722   uint32_t Reserved[2];           /*!< Reserved                                      */
2723 } USB_OTG_HostChannelTypeDef;
2724 /**
2725   * @}
2726   */
2727 
2728 /**
2729   * @brief USB_EHCI Capability Registers
2730   */
2731 typedef struct
2732 {
2733   __IO uint32_t HCCAPBASE;        /*!< Capability Register register,              Address offset: 0x00 */
2734   __IO uint32_t HCSPARAMS;        /*!< Structural Parameter register              Address offset: 0x04 */
2735   __IO uint32_t HCCPARAMS;        /*!< Capability Parameter register,             Address offset: 0x08 */
2736        uint32_t RESERVED;         /*!< USB Command register,                      Address offset: 0x0C */
2737   __IO uint32_t USBCMD;           /*!< USB Command register,                      Address offset: 0x10 */
2738   __IO uint32_t USBSTS;           /*!< USB Status register,                       Address offset: 0x14 */
2739   __IO uint32_t USBINTR;          /*!< USB Interrupt Enable register,             Address offset: 0x18 */
2740   __IO uint32_t FRINDEX;          /*!< USB Frame Index register ,                 Address offset: 0x1C */
2741   __IO uint32_t CTRLDSSEGMENT;    /*!< 4G Segment Selector register,              Address offset: 0x20 */
2742   __IO uint32_t PERIODICLISTBASE; /*!< Periodic Frame List Base Address register, Address offset: 0x24 */
2743   __IO uint32_t ASYNCLISTADDR;    /*!< Asynchronous List Address register,        Address offset: 0x28 */
2744 } USB_EHCI_CapabilityTypeDef;
2745 /**
2746   * @}
2747   */
2748 
2749 /**
2750   * @brief GPU host interface registers
2751   */
2752 typedef struct
2753 {
2754   __IO uint32_t CLKCTRLR;     /*!< Clock control register                           Address offset: 0x00 */
2755   __IO uint32_t IDLESR;       /*!< IDLE status register                             Address offset: 0x04 */
2756   __IO uint32_t AXICFGR;      /*!< AXI Configuration register                       Address offset: 0x08 */
2757   __IO uint32_t AXISR;        /*!< AXI Status register,                             Address offset: 0x0C */
2758   __IO uint32_t INTRACK;      /*!< Interrupt acknowledge register,                  Address offset: 0x10 */
2759   __IO uint32_t INTREN;       /*!< Interrupt enable register,                       Address offset: 0x14 */
2760   __IO uint32_t CHIPID;       /*!< Chip ID,                                         Address offset: 0x18 */
2761   __IO uint32_t CHIPREV;      /*!< Chip revision register,                          Address offset: 0x1C */
2762   __IO uint32_t CHIPDATE;     /*!< Release date register,                           Address offset: 0x20 */
2763   __IO uint32_t CHIPTIME;     /*!< Release Time register,                           Address offset: 0x24 */
2764   __IO uint32_t TOTALCYCLES;  /*!< Total number of Cycles register,                 Address offset: 0x28 */
2765   __IO uint32_t PRODUCTID;    /*!< Product ID register,                             Address offset: 0x2C */
2766   __IO uint32_t POWERCTRLR;   /*!< Power control register,                          Address offset: 0x30 */
2767   __IO uint32_t MMUCTRLR;     /*!< MMU control register,                            Address offset: 0x34 */
2768   __IO uint32_t MEMDEBUG;     /*!< Memory debug register,                           Address offset: 0x38 */
2769   __IO uint32_t CMDBUFADDR;   /*!< Command buffer base address register,            Address offset: 0x3C */
2770   __IO uint32_t CMDBUFCTRL;   /*!< Command buffer control register,                 Address offset: 0x40 */
2771 } GPU_Host_InterfaceTypeDef;
2772 /**
2773   * @}
2774   */
2775 
2776 
2777 /** @addtogroup Peripheral_memory_map
2778   * @{
2779   */
2780 #define MCU_AHB_SRAM            ((uint32_t)0x30000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB             */
2781 #define MCU_AHB_RETRAM          ((uint32_t)0x38000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB                */
2782 
2783 #define SYSRAM_BASE             ((uint32_t)0x2FFC0000) /*!< Base address of : (up to 256KB) System RAM accessible over over AXI                  */
2784 #define RETRAM_BASE             MCU_AHB_RETRAM
2785 #define SRAM_BASE               MCU_AHB_SRAM
2786 #define PERIPH_BASE             ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals                                                */
2787 #define MPU_AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus                                                            */
2788 
2789 #define FMC_NOR_MEM_BASE        (MPU_AXI_BUS_MEMORY_BASE)              /*!< Base address of : FMC NOR memories  accessible over AXI              */
2790 #define QSPI_MEM_BASE           (MPU_AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories  accessible over AXI                 */
2791 #define FMC_NAND_MEM_BASE       (MPU_AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories  accessible over AXI             */
2792 #define STM_DATA_BASE           (MPU_AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI                       */
2793 #define DRAM_MEM_BASE           (MPU_AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI                                */
2794 
2795 /*!< Device electronic signature memory map */
2796 #define UID_BASE                  (0x5C005234L)            /*!< Unique Device ID register base address */
2797 #define PACKAGE_BASE              (0x5C005240L)            /*!< Package Data register base address */
2798 #define RPN_BASE                  (0x5C005204L)            /*!< Device Part Number register base address */
2799 #define DV_BASE                   (0x50081000L)            /*!< Device Version register base address */
2800 
2801 /*!< Peripheral memory map */
2802 #define MCU_APB1_PERIPH_BASE        (PERIPH_BASE + 0x00000000)
2803 #define MCU_APB2_PERIPH_BASE        (PERIPH_BASE + 0x04000000)
2804 #define MCU_AHB2_PERIPH_BASE        (PERIPH_BASE + 0x08000000)
2805 #define MCU_AHB3_PERIPH_BASE        (PERIPH_BASE + 0x0C000000)
2806 #define MCU_AHB4_PERIPH_BASE        (PERIPH_BASE + 0x10000000)
2807 #define MCU_APB3_PERIPH_BASE        (PERIPH_BASE + 0x10020000)
2808 #define APB_DEBUG_PERIPH_BASE       (PERIPH_BASE + 0x10080000)
2809 #define MPU_AHB5_PERIPH_BASE        (PERIPH_BASE + 0x14000000)
2810 #define GPV_PERIPH_BASE             (PERIPH_BASE + 0x17000000)
2811 #define MPU_AHB6_PERIPH_BASE        (PERIPH_BASE + 0x18000000)
2812 #define MPU_APB4_PERIPH_BASE        (PERIPH_BASE + 0x1A000000)
2813 #define MPU_APB5_PERIPH_BASE        (PERIPH_BASE + 0x1C000000)
2814 
2815 
2816 /*!< MCU_APB1 */
2817 #define TIM2_BASE             (MCU_APB1_PERIPH_BASE + 0x0000)
2818 #define TIM3_BASE             (MCU_APB1_PERIPH_BASE + 0x1000)
2819 #define TIM4_BASE             (MCU_APB1_PERIPH_BASE + 0x2000)
2820 #define TIM5_BASE             (MCU_APB1_PERIPH_BASE + 0x3000)
2821 #define TIM6_BASE             (MCU_APB1_PERIPH_BASE + 0x4000)
2822 #define TIM7_BASE             (MCU_APB1_PERIPH_BASE + 0x5000)
2823 #define TIM12_BASE            (MCU_APB1_PERIPH_BASE + 0x6000)
2824 #define TIM13_BASE            (MCU_APB1_PERIPH_BASE + 0x7000)
2825 #define TIM14_BASE            (MCU_APB1_PERIPH_BASE + 0x8000)
2826 #define LPTIM1_BASE           (MCU_APB1_PERIPH_BASE + 0x9000)
2827 #define WWDG1_BASE            (MCU_APB1_PERIPH_BASE + 0xA000)
2828 #define SPI2_BASE             (MCU_APB1_PERIPH_BASE + 0xB000)
2829 #define SPI3_BASE             (MCU_APB1_PERIPH_BASE + 0xC000)
2830 #define SPDIFRX_BASE          (MCU_APB1_PERIPH_BASE + 0xD000)
2831 #define USART2_BASE           (MCU_APB1_PERIPH_BASE + 0xE000)
2832 #define USART3_BASE           (MCU_APB1_PERIPH_BASE + 0xF000)
2833 #define UART4_BASE            (MCU_APB1_PERIPH_BASE + 0x10000)
2834 #define UART5_BASE            (MCU_APB1_PERIPH_BASE + 0x11000)
2835 #define I2C1_BASE             (MCU_APB1_PERIPH_BASE + 0x12000)
2836 #define I2C2_BASE             (MCU_APB1_PERIPH_BASE + 0x13000)
2837 #define I2C3_BASE             (MCU_APB1_PERIPH_BASE + 0x14000)
2838 #define I2C5_BASE             (MCU_APB1_PERIPH_BASE + 0x15000)
2839 #define CEC_BASE              (MCU_APB1_PERIPH_BASE + 0x16000)
2840 #define DAC1_BASE             (MCU_APB1_PERIPH_BASE + 0x17000)
2841 #define UART7_BASE            (MCU_APB1_PERIPH_BASE + 0x18000)
2842 #define UART8_BASE            (MCU_APB1_PERIPH_BASE + 0x19000)
2843 #define MDIOS_BASE            (MCU_APB1_PERIPH_BASE + 0x1C000)
2844 
2845 /*!< MCU_APB2 */
2846 #define TIM1_BASE             (MCU_APB2_PERIPH_BASE + 0x0000)
2847 #define TIM8_BASE             (MCU_APB2_PERIPH_BASE + 0x1000)
2848 #define USART6_BASE           (MCU_APB2_PERIPH_BASE + 0x3000)
2849 #define SPI1_BASE             (MCU_APB2_PERIPH_BASE + 0x4000)
2850 #define SPI4_BASE             (MCU_APB2_PERIPH_BASE + 0x5000)
2851 #define TIM15_BASE            (MCU_APB2_PERIPH_BASE + 0x6000)
2852 #define TIM16_BASE            (MCU_APB2_PERIPH_BASE + 0x7000)
2853 #define TIM17_BASE            (MCU_APB2_PERIPH_BASE + 0x8000)
2854 #define SPI5_BASE             (MCU_APB2_PERIPH_BASE + 0x9000)
2855 #define SAI1_BASE             (MCU_APB2_PERIPH_BASE + 0xA000)
2856 #define SAI1_Block_A_BASE     (SAI1_BASE + 0x004)
2857 #define SAI1_Block_B_BASE     (SAI1_BASE + 0x024)
2858 #define SAI2_BASE             (MCU_APB2_PERIPH_BASE + 0xB000)
2859 #define SAI2_Block_A_BASE     (SAI2_BASE + 0x004)
2860 #define SAI2_Block_B_BASE     (SAI2_BASE + 0x024)
2861 #define SAI3_BASE             (MCU_APB2_PERIPH_BASE + 0xC000)
2862 #define SAI3_Block_A_BASE     (SAI3_BASE + 0x004)
2863 #define SAI3_Block_B_BASE     (SAI3_BASE + 0x024)
2864 #define DFSDM1_BASE           (MCU_APB2_PERIPH_BASE + 0xD000)
2865 #define DFSDM1_Channel0_BASE  (DFSDM1_BASE + 0x00)
2866 #define DFSDM1_Channel1_BASE  (DFSDM1_BASE + 0x20)
2867 #define DFSDM1_Channel2_BASE  (DFSDM1_BASE + 0x40)
2868 #define DFSDM1_Channel3_BASE  (DFSDM1_BASE + 0x60)
2869 #define DFSDM1_Channel4_BASE  (DFSDM1_BASE + 0x80)
2870 #define DFSDM1_Channel5_BASE  (DFSDM1_BASE + 0xA0)
2871 #define DFSDM1_Channel6_BASE  (DFSDM1_BASE + 0xC0)
2872 #define DFSDM1_Channel7_BASE  (DFSDM1_BASE + 0xE0)
2873 #define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100)
2874 #define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180)
2875 #define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200)
2876 #define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280)
2877 #define DFSDM1_Filter4_BASE   (DFSDM1_BASE + 0x300)
2878 #define DFSDM1_Filter5_BASE   (DFSDM1_BASE + 0x380)
2879 #define FDCAN1_BASE           (MCU_APB2_PERIPH_BASE + 0xE000)
2880 #define FDCAN2_BASE           (MCU_APB2_PERIPH_BASE + 0xF000)
2881 #define TTFDCAN1_BASE         (MCU_APB2_PERIPH_BASE + 0xE100)
2882 #define FDCAN_CCU_BASE (MCU_APB2_PERIPH_BASE + 0x10000)
2883 #define SRAMCAN_BASE          (MCU_APB2_PERIPH_BASE + 0x11000)
2884 
2885 /*!< MCU_AHB2 */
2886 #define DMA1_BASE             (MCU_AHB2_PERIPH_BASE + 0x0000)
2887 #define DMA2_BASE             (MCU_AHB2_PERIPH_BASE + 0x1000)
2888 #define DMAMUX1_BASE          (MCU_AHB2_PERIPH_BASE + 0x2000)
2889 #define ADC1_BASE             (MCU_AHB2_PERIPH_BASE + 0x3000)
2890 #define ADC2_BASE             (MCU_AHB2_PERIPH_BASE + 0x3100)
2891 #define ADC12_COMMON_BASE     (MCU_AHB2_PERIPH_BASE + 0x3300)
2892 #define SDMMC3_BASE           (MCU_AHB2_PERIPH_BASE + 0x4000)
2893 #define DLYB_SDMMC3_BASE          (MCU_AHB2_PERIPH_BASE + 0x5000)
2894 #define USBOTG_BASE           (MCU_AHB2_PERIPH_BASE + 0x1000000)
2895 
2896 
2897 /*!< MCU_AHB3 */
2898 #define HSEM_BASE             (MCU_AHB3_PERIPH_BASE + 0x0000)
2899 #define IPCC_BASE             (MCU_AHB3_PERIPH_BASE + 0x1000)
2900 #define HASH2_BASE            (MCU_AHB3_PERIPH_BASE + 0x2000)
2901 #define HASH2_DIGEST_BASE     (MCU_AHB3_PERIPH_BASE + 0x2310)
2902 #define RNG2_BASE             (MCU_AHB3_PERIPH_BASE + 0x3000)
2903 #define CRC2_BASE             (MCU_AHB3_PERIPH_BASE + 0x4000)
2904 #define DCMI_BASE             (MCU_AHB3_PERIPH_BASE + 0x6000)
2905 
2906 /*!< MCU_AHB4 */
2907 #define RCC_BASE              (MCU_AHB4_PERIPH_BASE + 0x0000)
2908 #define PWR_BASE              (MCU_AHB4_PERIPH_BASE + 0x1000)
2909 #define GPIOA_BASE            (MCU_AHB4_PERIPH_BASE + 0x2000)
2910 #define GPIOB_BASE            (MCU_AHB4_PERIPH_BASE + 0x3000)
2911 #define GPIOC_BASE            (MCU_AHB4_PERIPH_BASE + 0x4000)
2912 #define GPIOD_BASE            (MCU_AHB4_PERIPH_BASE + 0x5000)
2913 #define GPIOE_BASE            (MCU_AHB4_PERIPH_BASE + 0x6000)
2914 #define GPIOF_BASE            (MCU_AHB4_PERIPH_BASE + 0x7000)
2915 #define GPIOG_BASE            (MCU_AHB4_PERIPH_BASE + 0x8000)
2916 #define GPIOH_BASE            (MCU_AHB4_PERIPH_BASE + 0x9000)
2917 #define GPIOI_BASE            (MCU_AHB4_PERIPH_BASE + 0xA000)
2918 #define GPIOJ_BASE            (MCU_AHB4_PERIPH_BASE + 0xB000)
2919 #define GPIOK_BASE            (MCU_AHB4_PERIPH_BASE + 0xC000)
2920 #define AIEC_BASE             (MCU_AHB4_PERIPH_BASE + 0xD000)
2921 #define AIEC_C1_BASE          (AIEC_BASE + 0x0080)
2922 #define AIEC_C2_BASE          (AIEC_BASE + 0x00C0)
2923 /* Alias EXTI_BASE defined because HAL code not yet reworked with new name AIEC*/
2924 #define EXTI_BASE             AIEC_BASE
2925 #define EXTI_C1_BASE          AIEC_C1_BASE
2926 #define EXTI_C2_BASE          AIEC_C2_BASE
2927 
2928 
2929 /*!< MCU_APB3 */
2930 #define SYSCFG_BASE           (MCU_APB3_PERIPH_BASE + 0x0000)
2931 #define LPTIM2_BASE           (MCU_APB3_PERIPH_BASE + 0x1000)
2932 #define LPTIM3_BASE           (MCU_APB3_PERIPH_BASE + 0x2000)
2933 #define LPTIM4_BASE           (MCU_APB3_PERIPH_BASE + 0x3000)
2934 #define LPTIM5_BASE           (MCU_APB3_PERIPH_BASE + 0x4000)
2935 #define VREFBUF_BASE          (MCU_APB3_PERIPH_BASE + 0x5000)
2936 #define SAI4_BASE             (MCU_APB3_PERIPH_BASE + 0x7000)
2937 #define SAI4_Block_A_BASE     (SAI4_BASE + 0x004)
2938 #define SAI4_Block_B_BASE     (SAI4_BASE + 0x024)
2939 #define DTS_BASE              (MCU_APB3_PERIPH_BASE + 0x8000)
2940 #define PMB_BASE              (MCU_APB3_PERIPH_BASE + 0x9000)
2941 #define HDP_BASE              (MCU_APB3_PERIPH_BASE + 0xA000)
2942 
2943 /*!< MCU_AHB4 _APB_Debug */
2944 #define DBGMCU_BASE           ((uint32_t )0x50081000)
2945 
2946 /*!< MCU_AHB5 */
2947 #define BKPSRAM_BASE          (MPU_AHB5_PERIPH_BASE + 0x0000)
2948 #define HASH1_BASE            (MPU_AHB5_PERIPH_BASE + 0x2000)
2949 #define HASH1_DIGEST_BASE     (MPU_AHB5_PERIPH_BASE + 0x2310)
2950 #define RNG1_BASE             (MPU_AHB5_PERIPH_BASE + 0x3000)
2951 #define GPIOZ_BASE            (MPU_AHB5_PERIPH_BASE + 0x4000)
2952 
2953 /*!< GPV */
2954 
2955 /*!< MPU_AHB6 */
2956 #define MDMA_BASE               (MPU_AHB6_PERIPH_BASE + 0x0000)
2957 #define FMC_R_BASE              (MPU_AHB6_PERIPH_BASE + 0x2000)
2958 #define QSPI_R_BASE             (MPU_AHB6_PERIPH_BASE + 0x3000)
2959 #define DLYB_QSPI_BASE          (MPU_AHB6_PERIPH_BASE + 0x4000)
2960 #define SDMMC1_BASE             (MPU_AHB6_PERIPH_BASE + 0x5000)
2961 #define DLYB_SDMMC1_BASE        (MPU_AHB6_PERIPH_BASE + 0x6000)
2962 #define SDMMC2_BASE             (MPU_AHB6_PERIPH_BASE + 0x7000)
2963 #define DLYB_SDMMC2_BASE        (MPU_AHB6_PERIPH_BASE + 0x8000)
2964 #define CRC1_BASE               (MPU_AHB6_PERIPH_BASE + 0x9000)
2965 #define ETH_BASE                (MPU_AHB6_PERIPH_BASE + 0xA000)
2966 #define ETH_MAC_BASE            (ETH_BASE)
2967 #define USB1HSFSP2_BASE         (MPU_AHB6_PERIPH_BASE + 0xC000)
2968 #define USB1HSFSP1_BASE         (MPU_AHB6_PERIPH_BASE + 0xD000)
2969 #define GPU_BASE                (MPU_AHB6_PERIPH_BASE + 0x1000000)
2970 
2971 /*!< MPU_APB4 */
2972 #define DSI_BASE              (MPU_APB4_PERIPH_BASE + 0x0000)
2973 #define LTDC_BASE             (MPU_APB4_PERIPH_BASE + 0x1000)
2974 #define LTDC_Layer1_BASE      (LTDC_BASE + 0x84)
2975 #define LTDC_Layer2_BASE      (LTDC_BASE + 0x104)
2976 #define IWDG2_BASE            (MPU_APB4_PERIPH_BASE + 0x2000)
2977 #define DDRC_BASE             (MPU_APB4_PERIPH_BASE + 0x3000)
2978 #define DDRPHYC_BASE          (MPU_APB4_PERIPH_BASE + 0x4000)
2979 #define STGENR_BASE           (MPU_APB4_PERIPH_BASE + 0x5000)
2980 #define USBPHYC_BASE          (MPU_APB4_PERIPH_BASE + 0x6000)
2981 #define USBPHYC_PHY1_BASE     (USBPHYC_BASE + 0x100)
2982 #define USBPHYC_PHY2_BASE     (USBPHYC_BASE + 0x200)
2983 
2984 /*!< MPU_APB5 */
2985 #define USART1_BASE           (MPU_APB5_PERIPH_BASE + 0x0000)
2986 #define SPI6_BASE             (MPU_APB5_PERIPH_BASE + 0x1000)
2987 #define I2C4_BASE             (MPU_APB5_PERIPH_BASE + 0x2000)
2988 #define IWDG1_BASE            (MPU_APB5_PERIPH_BASE + 0x3000)
2989 #define RTC_BASE              (MPU_APB5_PERIPH_BASE + 0x4000)
2990 #define BSEC_BASE             (MPU_APB5_PERIPH_BASE + 0x5000)
2991 #define TZC_BASE              (MPU_APB5_PERIPH_BASE + 0x6000)
2992 #define TZPC_BASE             (MPU_APB5_PERIPH_BASE + 0x7000)
2993 #define STGENC_BASE           (MPU_APB5_PERIPH_BASE + 0x8000)
2994 #define I2C6_BASE             (MPU_APB5_PERIPH_BASE + 0x9000)
2995 #define TAMP_BASE             (MPU_APB5_PERIPH_BASE + 0xA000)
2996 
2997 
2998 
2999 /*!< USB registers base address */
3000 #define USB_OTG_GLOBAL_BASE                  ((uint32_t )0x000)
3001 #define USB_OTG_DEVICE_BASE                  ((uint32_t )0x800)
3002 #define USB_OTG_IN_ENDPOINT_BASE             ((uint32_t )0x900)
3003 #define USB_OTG_OUT_ENDPOINT_BASE            ((uint32_t )0xB00)
3004 #define USB_OTG_EP_REG_SIZE                  ((uint32_t )0x20)
3005 #define USB_OTG_HOST_BASE                    ((uint32_t )0x400)
3006 #define USB_OTG_HOST_PORT_BASE               ((uint32_t )0x440)
3007 #define USB_OTG_HOST_CHANNEL_BASE            ((uint32_t )0x500)
3008 #define USB_OTG_HOST_CHANNEL_SIZE            ((uint32_t )0x20)
3009 #define USB_OTG_PCGCCTL_BASE                 ((uint32_t )0xE00)
3010 #define USB_OTG_FIFO_BASE                    ((uint32_t )0x1000)
3011 #define USB_OTG_FIFO_SIZE                    ((uint32_t )0x1000)
3012 
3013 
3014 
3015 #define DMA1_Stream0_BASE     (DMA1_BASE + 0x010)
3016 #define DMA1_Stream1_BASE     (DMA1_BASE + 0x028)
3017 #define DMA1_Stream2_BASE     (DMA1_BASE + 0x040)
3018 #define DMA1_Stream3_BASE     (DMA1_BASE + 0x058)
3019 #define DMA1_Stream4_BASE     (DMA1_BASE + 0x070)
3020 #define DMA1_Stream5_BASE     (DMA1_BASE + 0x088)
3021 #define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0)
3022 #define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8)
3023 
3024 #define DMA2_Stream0_BASE     (DMA2_BASE + 0x010)
3025 #define DMA2_Stream1_BASE     (DMA2_BASE + 0x028)
3026 #define DMA2_Stream2_BASE     (DMA2_BASE + 0x040)
3027 #define DMA2_Stream3_BASE     (DMA2_BASE + 0x058)
3028 #define DMA2_Stream4_BASE     (DMA2_BASE + 0x070)
3029 #define DMA2_Stream5_BASE     (DMA2_BASE + 0x088)
3030 #define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0)
3031 #define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8)
3032 
3033 #define DMAMUX1_Channel0_BASE    (DMAMUX1_BASE)
3034 #define DMAMUX1_Channel1_BASE    (DMAMUX1_BASE + 0x0004)
3035 #define DMAMUX1_Channel2_BASE    (DMAMUX1_BASE + 0x0008)
3036 #define DMAMUX1_Channel3_BASE    (DMAMUX1_BASE + 0x000C)
3037 #define DMAMUX1_Channel4_BASE    (DMAMUX1_BASE + 0x0010)
3038 #define DMAMUX1_Channel5_BASE    (DMAMUX1_BASE + 0x0014)
3039 #define DMAMUX1_Channel6_BASE    (DMAMUX1_BASE + 0x0018)
3040 #define DMAMUX1_Channel7_BASE    (DMAMUX1_BASE + 0x001C)
3041 #define DMAMUX1_Channel8_BASE    (DMAMUX1_BASE + 0x0020)
3042 #define DMAMUX1_Channel9_BASE    (DMAMUX1_BASE + 0x0024)
3043 #define DMAMUX1_Channel10_BASE   (DMAMUX1_BASE + 0x0028)
3044 #define DMAMUX1_Channel11_BASE   (DMAMUX1_BASE + 0x002C)
3045 #define DMAMUX1_Channel12_BASE   (DMAMUX1_BASE + 0x0030)
3046 #define DMAMUX1_Channel13_BASE   (DMAMUX1_BASE + 0x0034)
3047 #define DMAMUX1_Channel14_BASE   (DMAMUX1_BASE + 0x0038)
3048 #define DMAMUX1_Channel15_BASE   (DMAMUX1_BASE + 0x003C)
3049 
3050 #define DMAMUX1_RequestGenerator0_BASE  (DMAMUX1_BASE + 0x0100)
3051 #define DMAMUX1_RequestGenerator1_BASE  (DMAMUX1_BASE + 0x0104)
3052 #define DMAMUX1_RequestGenerator2_BASE  (DMAMUX1_BASE + 0x0108)
3053 #define DMAMUX1_RequestGenerator3_BASE  (DMAMUX1_BASE + 0x010C)
3054 
3055 #define DMAMUX1_ChannelStatus_BASE      (DMAMUX1_BASE + 0x0080)
3056 #define DMAMUX1_RequestGenStatus_BASE   (DMAMUX1_BASE + 0x0140)
3057 
3058 
3059 
3060 /*!< FMC Banks registers base  address */
3061 #define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000)
3062 #define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104)
3063 #define FMC_Bank2_R_BASE      (FMC_R_BASE + 0x0060)
3064 #define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080)
3065 #define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140)
3066 
3067 #define MDMA_NB_CHANNELS        32
3068 #define MDMA_Channel0_BASE    (MDMA_BASE + 0x00000040)
3069 #define MDMA_Channel1_BASE    (MDMA_BASE + 0x00000080)
3070 #define MDMA_Channel2_BASE    (MDMA_BASE + 0x000000C0)
3071 #define MDMA_Channel3_BASE    (MDMA_BASE + 0x00000100)
3072 #define MDMA_Channel4_BASE    (MDMA_BASE + 0x00000140)
3073 #define MDMA_Channel5_BASE    (MDMA_BASE + 0x00000180)
3074 #define MDMA_Channel6_BASE    (MDMA_BASE + 0x000001C0)
3075 #define MDMA_Channel7_BASE    (MDMA_BASE + 0x00000200)
3076 #define MDMA_Channel8_BASE    (MDMA_BASE + 0x00000240)
3077 #define MDMA_Channel9_BASE    (MDMA_BASE + 0x00000280)
3078 #define MDMA_Channel10_BASE   (MDMA_BASE + 0x000002C0)
3079 #define MDMA_Channel11_BASE   (MDMA_BASE + 0x00000300)
3080 #define MDMA_Channel12_BASE   (MDMA_BASE + 0x00000340)
3081 #define MDMA_Channel13_BASE   (MDMA_BASE + 0x00000380)
3082 #define MDMA_Channel14_BASE   (MDMA_BASE + 0x000003C0)
3083 #define MDMA_Channel15_BASE   (MDMA_BASE + 0x00000400)
3084 #define MDMA_Channel16_BASE   (MDMA_BASE + 0x00000440)
3085 #define MDMA_Channel17_BASE   (MDMA_BASE + 0x00000480)
3086 #define MDMA_Channel18_BASE   (MDMA_BASE + 0x000004C0)
3087 #define MDMA_Channel19_BASE   (MDMA_BASE + 0x00000500)
3088 #define MDMA_Channel20_BASE   (MDMA_BASE + 0x00000540)
3089 #define MDMA_Channel21_BASE   (MDMA_BASE + 0x00000580)
3090 #define MDMA_Channel22_BASE   (MDMA_BASE + 0x000005C0)
3091 #define MDMA_Channel23_BASE   (MDMA_BASE + 0x00000600)
3092 #define MDMA_Channel24_BASE   (MDMA_BASE + 0x00000640)
3093 #define MDMA_Channel25_BASE   (MDMA_BASE + 0x00000680)
3094 #define MDMA_Channel26_BASE   (MDMA_BASE + 0x000006C0)
3095 #define MDMA_Channel27_BASE   (MDMA_BASE + 0x00000700)
3096 #define MDMA_Channel28_BASE   (MDMA_BASE + 0x00000740)
3097 #define MDMA_Channel29_BASE   (MDMA_BASE + 0x00000780)
3098 #define MDMA_Channel30_BASE   (MDMA_BASE + 0x000007C0)
3099 #define MDMA_Channel31_BASE   (MDMA_BASE + 0x00000800)
3100 
3101 /**
3102   * @}
3103   */
3104 
3105 /** @addtogroup Peripheral_declaration
3106   * @{
3107   */
3108 #define TIM2                ((TIM_TypeDef *) TIM2_BASE)
3109 #define TIM3                ((TIM_TypeDef *) TIM3_BASE)
3110 #define TIM4                ((TIM_TypeDef *) TIM4_BASE)
3111 #define TIM5                ((TIM_TypeDef *) TIM5_BASE)
3112 #define TIM6                ((TIM_TypeDef *) TIM6_BASE)
3113 #define TIM7                ((TIM_TypeDef *) TIM7_BASE)
3114 #define TIM12               ((TIM_TypeDef *) TIM12_BASE)
3115 #define TIM13               ((TIM_TypeDef *) TIM13_BASE)
3116 #define TIM14               ((TIM_TypeDef *) TIM14_BASE)
3117 #define LCD                 ((LCD_TypeDef *) LCD_BASE)
3118 #define RTC                 ((RTC_TypeDef *) RTC_BASE)
3119 #define TAMP                 ((TAMP_TypeDef *) TAMP_BASE)
3120 #define WWDG1               ((WWDG_TypeDef *) WWDG1_BASE)
3121 #define IWDG1               ((IWDG_TypeDef *) IWDG1_BASE)
3122 #define IWDG2               ((IWDG_TypeDef *) IWDG2_BASE)
3123 #define SPI2                ((SPI_TypeDef *) SPI2_BASE)
3124 #define SPI3                ((SPI_TypeDef *) SPI3_BASE)
3125 #define SPI4                ((SPI_TypeDef *) SPI4_BASE)
3126 #define SPI5                ((SPI_TypeDef *) SPI5_BASE)
3127 #define SPI6                ((SPI_TypeDef *) SPI6_BASE)
3128 #define USART2              ((USART_TypeDef *) USART2_BASE)
3129 #define USART3              ((USART_TypeDef *) USART3_BASE)
3130 #define USART6              ((USART_TypeDef *) USART6_BASE)
3131 #define UART7               ((USART_TypeDef *) UART7_BASE)
3132 #define UART8               ((USART_TypeDef *) UART8_BASE)
3133 #define UART4               ((USART_TypeDef *) UART4_BASE)
3134 #define UART5               ((USART_TypeDef *) UART5_BASE)
3135 #define I2C1                ((I2C_TypeDef *) I2C1_BASE)
3136 #define I2C2                ((I2C_TypeDef *) I2C2_BASE)
3137 #define I2C3                ((I2C_TypeDef *) I2C3_BASE)
3138 #define I2C4                ((I2C_TypeDef *) I2C4_BASE)
3139 #define I2C5                ((I2C_TypeDef *) I2C5_BASE)
3140 #define I2C6                ((I2C_TypeDef *) I2C6_BASE)
3141 #define FDCAN1              ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
3142 #define FDCAN2              ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)
3143 #define TTFDCAN1            ((TTCAN_TypeDef *) TTFDCAN1_BASE)
3144 #define FDCAN_CCU           ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)
3145 #define CEC                 ((CEC_TypeDef *) CEC_BASE)
3146 #define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
3147 #define PWR                 ((PWR_TypeDef *) PWR_BASE)
3148 #define DAC1                ((DAC_TypeDef *) DAC1_BASE)
3149 #define LPTIM2              ((LPTIM_TypeDef *) LPTIM2_BASE)
3150 #define LPTIM3              ((LPTIM_TypeDef *) LPTIM3_BASE)
3151 #define LPTIM4              ((LPTIM_TypeDef *) LPTIM4_BASE)
3152 #define LPTIM5              ((LPTIM_TypeDef *) LPTIM5_BASE)
3153 #define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
3154 #define VREFBUF             ((VREF_TypeDef *) VREFBUF_BASE)
3155 
3156 
3157 #define EXTI                ((EXTI_TypeDef *) IO_DEVICE_ADDR(EXTI_BASE))
3158 #define EXTI_C1             ((EXTI_Core_TypeDef *) EXTI_C1_BASE)
3159 #define EXTI_C2             ((EXTI_Core_TypeDef *) EXTI_C2_BASE)
3160 #define TIM1                ((TIM_TypeDef *) TIM1_BASE)
3161 #define SPI1                ((SPI_TypeDef *) SPI1_BASE)
3162 #define TIM8                ((TIM_TypeDef *) TIM8_BASE)
3163 #define USART1              ((USART_TypeDef *) USART1_BASE)
3164 #define TIM15               ((TIM_TypeDef *) TIM15_BASE)
3165 #define TIM16               ((TIM_TypeDef *) TIM16_BASE)
3166 #define TIM17               ((TIM_TypeDef *) TIM17_BASE)
3167 #define SAI1                ((SAI_TypeDef *) SAI1_BASE)
3168 #define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
3169 #define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
3170 #define SAI2                ((SAI_TypeDef *) SAI2_BASE)
3171 #define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
3172 #define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
3173 #define SAI3                ((SAI_TypeDef *) SAI3_BASE)
3174 #define SAI3_Block_A        ((SAI_Block_TypeDef *)SAI3_Block_A_BASE)
3175 #define SAI3_Block_B        ((SAI_Block_TypeDef *)SAI3_Block_B_BASE)
3176 #define SAI4                ((SAI_TypeDef *) SAI4_BASE)
3177 #define SAI4_Block_A        ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)
3178 #define SAI4_Block_B        ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)
3179 #define DTS1                ((DTS_TypeDef *) DTS_BASE)
3180 #define PMB                 ((PMB_TypeDef *) PMB_BASE)
3181 #define SPDIFRX             ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
3182 #define DFSDM1              ((DFSDM_TypeDef *) DFSDM1_BASE)
3183 #define DFSDM1_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
3184 #define DFSDM1_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
3185 #define DFSDM1_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
3186 #define DFSDM1_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
3187 #define DFSDM1_Channel4     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
3188 #define DFSDM1_Channel5     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
3189 #define DFSDM1_Channel6     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
3190 #define DFSDM1_Channel7     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
3191 #define DFSDM1_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
3192 #define DFSDM1_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
3193 #define DFSDM1_Filter2      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
3194 #define DFSDM1_Filter3      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
3195 #define DFSDM1_Filter4      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter4_BASE)
3196 #define DFSDM1_Filter5      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter5_BASE)
3197 #define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
3198 
3199 #define RCC                 ((RCC_TypeDef *) IO_DEVICE_ADDR(RCC_BASE))
3200 
3201 #define HDP                 ((HDP_TypeDef *) HDP_BASE)
3202 
3203 #define BSEC                ((BSEC_TypeDef *) BSEC_BASE)
3204 
3205 
3206 #define CRC2                 ((CRC_TypeDef *) CRC2_BASE)
3207 #define CRC1                     ((CRC_TypeDef *) CRC1_BASE)
3208 
3209 #define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
3210 #define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
3211 #define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
3212 #define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
3213 #define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
3214 #define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
3215 #define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
3216 #define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
3217 #define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
3218 #define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)
3219 #define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)
3220 #define ADC1                ((ADC_TypeDef *) ADC1_BASE)
3221 #define ADC2                ((ADC_TypeDef *) ADC2_BASE)
3222 #define ADC12_COMMON        ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
3223 
3224 #define IPCC                ((IPCC_TypeDef *) IPCC_BASE)
3225 #define IPCC_C1             ((IPCC_CommonTypeDef *) IPCC_BASE)
3226 #define IPCC_C2             ((IPCC_CommonTypeDef *) (IPCC_BASE + 0x10U))
3227 #define HASH2               ((HASH_TypeDef *) HASH2_BASE)
3228 #define HASH1               ((HASH_TypeDef *) HASH1_BASE)
3229 #define HASH2_DIGEST        ((HASH_DIGEST_TypeDef *) HASH2_DIGEST_BASE)
3230 #define HASH1_DIGEST        ((HASH_DIGEST_TypeDef *) HASH1_DIGEST_BASE)
3231 #define HASH                ((HASH_TypeDef *) HASH1)
3232 #define HASH_DIGEST         ((HASH_DIGEST_TypeDef *) HASH1_DIGEST)
3233 #define RNG2                ((RNG_TypeDef *) RNG2_BASE)
3234 #define RNG1                ((RNG_TypeDef *) RNG1_BASE)
3235 #define GPIOZ               ((GPIO_TypeDef *) GPIOZ_BASE)
3236 #define SDMMC2              ((SDMMC_TypeDef *) SDMMC2_BASE)
3237 
3238 #define DLYB_SDMMC1         ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)
3239 #define DLYB_SDMMC2         ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)
3240 #define DLYB_SDMMC3         ((DLYB_TypeDef *) DLYB_SDMMC3_BASE)
3241 
3242 #define DMA2                ((DMA_TypeDef *) DMA2_BASE)
3243 #define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
3244 #define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
3245 #define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
3246 #define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
3247 #define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
3248 #define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
3249 #define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
3250 #define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
3251 
3252 #define DMA1                ((DMA_TypeDef *) DMA1_BASE)
3253 #define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
3254 #define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
3255 #define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
3256 #define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
3257 #define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
3258 #define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
3259 #define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
3260 #define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
3261 
3262 
3263 #define DMAMUX1              ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
3264 #define DMAMUX1_Channel0     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
3265 #define DMAMUX1_Channel1     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
3266 #define DMAMUX1_Channel2     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
3267 #define DMAMUX1_Channel3     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
3268 #define DMAMUX1_Channel4     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
3269 #define DMAMUX1_Channel5     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
3270 #define DMAMUX1_Channel6     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
3271 #define DMAMUX1_Channel7     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
3272 #define DMAMUX1_Channel8     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
3273 #define DMAMUX1_Channel9     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
3274 #define DMAMUX1_Channel10    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
3275 #define DMAMUX1_Channel11    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
3276 #define DMAMUX1_Channel12    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
3277 #define DMAMUX1_Channel13    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
3278 #define DMAMUX1_Channel14    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)
3279 #define DMAMUX1_Channel15    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)
3280 
3281 #define DMAMUX1_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
3282 #define DMAMUX1_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
3283 #define DMAMUX1_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
3284 #define DMAMUX1_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
3285 
3286 #define DMAMUX1_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *)    DMAMUX1_ChannelStatus_BASE)
3287 #define DMAMUX1_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
3288 
3289 
3290 #define FMC_Bank1_R         ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
3291 #define FMC_Bank1E_R        ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
3292 #define FMC_Bank3_R         ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
3293 
3294 #define QUADSPI               ((QUADSPI_TypeDef *) QSPI_R_BASE)
3295 #define DLYB_QUADSPI          ((DLYB_TypeDef *) DLYB_QSPI_BASE)
3296 
3297 #define SDMMC1                ((SDMMC_TypeDef *) SDMMC1_BASE)
3298 #define SDMMC3                ((SDMMC_TypeDef *) SDMMC3_BASE)
3299 
3300 #define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
3301 
3302 #define JPEG                ((JPEG_TypeDef *) JPGDEC_BASE)
3303 #define HSEM                ((HSEM_TypeDef *) HSEM_BASE)
3304 #define HSEM_COMMON         ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100U))
3305 
3306 
3307 #define USBPHYC             ((USBPHYC_GlobalTypeDef *)USBPHYC_BASE)
3308 #define USBPHYC_PHY1        ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY1_BASE)
3309 #define USBPHYC_PHY2        ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY2_BASE)
3310 
3311 #define DDRC                ((DDRC_TypeDef *)DDRC_BASE)
3312 #define DDRPHYC             ((DDRPHYC_TypeDef *)DDRPHYC_BASE)
3313 #define LTDC                ((LTDC_TypeDef *)LTDC_BASE)
3314 #define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
3315 #define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
3316 #define DSI                 ((DSI_TypeDef *)DSI_BASE)
3317 
3318 #define TZC                 ((TZC_TypeDef *)TZC_BASE)
3319 #define TZPC                ((TZPC_TypeDef *)TZPC_BASE)
3320 #define STGENC              ((STGENC_TypeDef *)STGENC_BASE)
3321 
3322 
3323 #define MDIOS               ((MDIOS_TypeDef *) MDIOS_BASE)
3324 
3325 #define ETH                 ((ETH_TypeDef *) ETH_BASE)
3326 #define MDMA                ((MDMA_TypeDef *) MDMA_BASE)
3327 #define MDMA_Channel0       ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)
3328 #define MDMA_Channel1       ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)
3329 #define MDMA_Channel2       ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)
3330 #define MDMA_Channel3       ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)
3331 #define MDMA_Channel4       ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)
3332 #define MDMA_Channel5       ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)
3333 #define MDMA_Channel6       ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)
3334 #define MDMA_Channel7       ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)
3335 #define MDMA_Channel8       ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)
3336 #define MDMA_Channel9       ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)
3337 #define MDMA_Channel10      ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)
3338 #define MDMA_Channel11      ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)
3339 #define MDMA_Channel12      ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)
3340 #define MDMA_Channel13      ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)
3341 #define MDMA_Channel14      ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)
3342 #define MDMA_Channel15      ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)
3343 #define MDMA_Channel16      ((MDMA_Channel_TypeDef *)MDMA_Channel16_BASE)
3344 #define MDMA_Channel17      ((MDMA_Channel_TypeDef *)MDMA_Channel17_BASE)
3345 #define MDMA_Channel18      ((MDMA_Channel_TypeDef *)MDMA_Channel18_BASE)
3346 #define MDMA_Channel19      ((MDMA_Channel_TypeDef *)MDMA_Channel19_BASE)
3347 #define MDMA_Channel20      ((MDMA_Channel_TypeDef *)MDMA_Channel20_BASE)
3348 #define MDMA_Channel21      ((MDMA_Channel_TypeDef *)MDMA_Channel21_BASE)
3349 #define MDMA_Channel22      ((MDMA_Channel_TypeDef *)MDMA_Channel22_BASE)
3350 #define MDMA_Channel23      ((MDMA_Channel_TypeDef *)MDMA_Channel23_BASE)
3351 #define MDMA_Channel24      ((MDMA_Channel_TypeDef *)MDMA_Channel24_BASE)
3352 #define MDMA_Channel25      ((MDMA_Channel_TypeDef *)MDMA_Channel25_BASE)
3353 #define MDMA_Channel26      ((MDMA_Channel_TypeDef *)MDMA_Channel26_BASE)
3354 #define MDMA_Channel27      ((MDMA_Channel_TypeDef *)MDMA_Channel27_BASE)
3355 #define MDMA_Channel28      ((MDMA_Channel_TypeDef *)MDMA_Channel28_BASE)
3356 #define MDMA_Channel29      ((MDMA_Channel_TypeDef *)MDMA_Channel29_BASE)
3357 #define MDMA_Channel30      ((MDMA_Channel_TypeDef *)MDMA_Channel30_BASE)
3358 #define MDMA_Channel31      ((MDMA_Channel_TypeDef *)MDMA_Channel31_BASE)
3359 
3360 #define USB_OTG_HS            ((USB_OTG_GlobalTypeDef *) USBOTG_BASE)
3361 /* backward compatibility */
3362 #define USB1_OTG_HS           USB_OTG_HS
3363 #define USB2_OTG_FS           ((USB_OTG_GlobalTypeDef *) 0x00000000)
3364 #define USB_OTG_FS            USB2_OTG_FS
3365 
3366 #define USB1_EHCI             ((USB_EHCI_CapabilityTypeDef *) USB1HSFSP1_BASE)
3367 
3368 #define GPU                   ((GPU_Host_InterfaceTypeDef *) GPU_BASE)
3369 
3370 
3371 
3372 /**
3373   * @}
3374   */
3375 
3376 /** @addtogroup Exported_constants
3377   * @{
3378   */
3379 
3380   /** @addtogroup Peripheral_Registers_Bits_Definition
3381   * @{
3382   */
3383 
3384 /******************************************************************************/
3385 /*                         Peripheral Registers_Bits_Definition               */
3386 /******************************************************************************/
3387 
3388 /******************************************************************************/
3389 /*                                                                            */
3390 /*                        Device Electronic Signature                         */
3391 /*                                                                            */
3392 /******************************************************************************/
3393 #define PKG_ID_Pos              (27U)
3394 #define PKG_ID_Msk              (0x7U << PKG_ID_Pos)        /*!< 0x38000000 */
3395 #define PKG_ID                  PKG_ID_Msk                  /*!< Package Type */
3396 
3397 #define RPN_ID_Pos              (0U)
3398 #define RPN_ID_Msk              (0xFFU << RPN_ID_Pos)       /*!< 0x000000FF */
3399 #define RPN_ID                  RPN_ID_Msk                  /*!< Device Part Number */
3400 
3401 #define DV_DEV_ID_Pos           (0U)
3402 #define DV_DEV_ID_Msk           (0xFFFU << DV_DEV_ID_Pos)   /*!< 0x00000FFF */
3403 #define DV_DEV_ID               DV_DEV_ID_Msk               /*!< Device ID */
3404 #define DV_REV_ID_Pos           (16U)
3405 #define DV_REV_ID_Msk           (0xFFFFU << DV_REV_ID_Pos)  /*!< 0xFFFF0000 */
3406 #define DV_REV_ID               DV_REV_ID_Msk               /*!< Device Rev ID */
3407 
3408 /******************************************************************************/
3409 /*                                                                            */
3410 /*                        Analog to Digital Converter                         */
3411 /*                                                                            */
3412 /******************************************************************************/
3413 /*
3414 * @brief Specific device feature definitions
3415 */
3416 #define ADC_MULTIMODE_SUPPORT                          /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
3417 
3418 /********************  Bit definition for ADC_ISR register  ********************/
3419 #define ADC_ISR_ADRDY_Pos                  (0U)
3420 #define ADC_ISR_ADRDY_Msk                  (0x1U << ADC_ISR_ADRDY_Pos)           /*!< 0x00000001 */
3421 #define ADC_ISR_ADRDY                      ADC_ISR_ADRDY_Msk                     /*!< ADC Ready (ADRDY) flag  */
3422 #define ADC_ISR_EOSMP_Pos                 (1U)
3423 #define ADC_ISR_EOSMP_Msk                 (0x1U << ADC_ISR_EOSMP_Pos)          /*!< 0x00000002 */
3424 #define ADC_ISR_EOSMP                     ADC_ISR_EOSMP_Msk                    /*!< ADC End of Sampling flag */
3425 #define ADC_ISR_EOC_Pos                   (2U)
3426 #define ADC_ISR_EOC_Msk                   (0x1U << ADC_ISR_EOC_Pos)            /*!< 0x00000004 */
3427 #define ADC_ISR_EOC                       ADC_ISR_EOC_Msk                      /*!< ADC End of Regular Conversion flag */
3428 #define ADC_ISR_EOS_Pos                   (3U)
3429 #define ADC_ISR_EOS_Msk                   (0x1U << ADC_ISR_EOS_Pos)            /*!< 0x00000008 */
3430 #define ADC_ISR_EOS                       ADC_ISR_EOS_Msk                      /*!< ADC End of Regular sequence of Conversions flag */
3431 #define ADC_ISR_OVR_Pos                   (4U)
3432 #define ADC_ISR_OVR_Msk                   (0x1U << ADC_ISR_OVR_Pos)            /*!< 0x00000010 */
3433 #define ADC_ISR_OVR                       ADC_ISR_OVR_Msk                      /*!< ADC overrun flag */
3434 #define ADC_ISR_JEOC_Pos                  (5U)
3435 #define ADC_ISR_JEOC_Msk                  (0x1U << ADC_ISR_JEOC_Pos)           /*!< 0x00000020 */
3436 #define ADC_ISR_JEOC                      ADC_ISR_JEOC_Msk                     /*!< ADC End of Injected Conversion flag */
3437 #define ADC_ISR_JEOS_Pos                  (6U)
3438 #define ADC_ISR_JEOS_Msk                  (0x1U << ADC_ISR_JEOS_Pos)           /*!< 0x00000040 */
3439 #define ADC_ISR_JEOS                      ADC_ISR_JEOS_Msk                     /*!< ADC End of Injected sequence of Conversions flag */
3440 #define ADC_ISR_AWD1_Pos                  (7U)
3441 #define ADC_ISR_AWD1_Msk                  (0x1U << ADC_ISR_AWD1_Pos)           /*!< 0x00000080 */
3442 #define ADC_ISR_AWD1                      ADC_ISR_AWD1_Msk                     /*!< ADC Analog watchdog 1 flag */
3443 #define ADC_ISR_AWD2_Pos                  (8U)
3444 #define ADC_ISR_AWD2_Msk                  (0x1U << ADC_ISR_AWD2_Pos)           /*!< 0x00000100 */
3445 #define ADC_ISR_AWD2                      ADC_ISR_AWD2_Msk                     /*!< ADC Analog watchdog 2 flag */
3446 #define ADC_ISR_AWD3_Pos                  (9U)
3447 #define ADC_ISR_AWD3_Msk                  (0x1U << ADC_ISR_AWD3_Pos)           /*!< 0x00000200 */
3448 #define ADC_ISR_AWD3                      ADC_ISR_AWD3_Msk                     /*!< ADC Analog watchdog 3 flag */
3449 #define ADC_ISR_JQOVF_Pos                 (10U)
3450 #define ADC_ISR_JQOVF_Msk                 (0x1U << ADC_ISR_JQOVF_Pos)          /*!< 0x00000400 */
3451 #define ADC_ISR_JQOVF                     ADC_ISR_JQOVF_Msk                    /*!< ADC Injected Context Queue Overflow flag */
3452 
3453 /********************  Bit definition for ADC_IER register  ********************/
3454 #define ADC_IER_ADRDYIE_Pos               (0U)
3455 #define ADC_IER_ADRDYIE_Msk               (0x1U << ADC_IER_ADRDYIE_Pos)            /*!< 0x00000001 */
3456 #define ADC_IER_ADRDYIE                   ADC_IER_ADRDYIE_Msk                      /*!< ADC Ready (ADRDY) interrupt source */
3457 #define ADC_IER_EOSMPIE_Pos               (1U)
3458 #define ADC_IER_EOSMPIE_Msk               (0x1U << ADC_IER_EOSMPIE_Pos)          /*!< 0x00000002 */
3459 #define ADC_IER_EOSMPIE                   ADC_IER_EOSMPIE_Msk                    /*!< ADC End of Sampling interrupt source */
3460 #define ADC_IER_EOCIE_Pos                 (2U)
3461 #define ADC_IER_EOCIE_Msk                 (0x1U << ADC_IER_EOCIE_Pos)            /*!< 0x00000004 */
3462 #define ADC_IER_EOCIE                     ADC_IER_EOCIE_Msk                      /*!< ADC End of Regular Conversion interrupt source */
3463 #define ADC_IER_EOSIE_Pos                 (3U)
3464 #define ADC_IER_EOSIE_Msk                 (0x1U << ADC_IER_EOSIE_Pos)            /*!< 0x00000008 */
3465 #define ADC_IER_EOSIE                     ADC_IER_EOSIE_Msk                      /*!< ADC End of Regular sequence of Conversions interrupt source */
3466 #define ADC_IER_OVRIE_Pos                 (4U)
3467 #define ADC_IER_OVRIE_Msk                 (0x1U << ADC_IER_OVRIE_Pos)            /*!< 0x00000010 */
3468 #define ADC_IER_OVRIE                     ADC_IER_OVRIE_Msk                      /*!< ADC overrun interrupt source */
3469 #define ADC_IER_JEOCIE_Pos                (5U)
3470 #define ADC_IER_JEOCIE_Msk                (0x1U << ADC_IER_JEOCIE_Pos)           /*!< 0x00000020 */
3471 #define ADC_IER_JEOCIE                    ADC_IER_JEOCIE_Msk                     /*!< ADC End of Injected Conversion interrupt source */
3472 #define ADC_IER_JEOSIE_Pos                (6U)
3473 #define ADC_IER_JEOSIE_Msk                (0x1U << ADC_IER_JEOSIE_Pos)           /*!< 0x00000040 */
3474 #define ADC_IER_JEOSIE                    ADC_IER_JEOSIE_Msk                     /*!< ADC End of Injected sequence of Conversions interrupt source */
3475 #define ADC_IER_AWD1IE_Pos                (7U)
3476 #define ADC_IER_AWD1IE_Msk                (0x1U << ADC_IER_AWD1IE_Pos)           /*!< 0x00000080 */
3477 #define ADC_IER_AWD1IE                    ADC_IER_AWD1IE_Msk                     /*!< ADC Analog watchdog 1 interrupt source */
3478 #define ADC_IER_AWD2IE_Pos                (8U)
3479 #define ADC_IER_AWD2IE_Msk                (0x1U << ADC_IER_AWD2IE_Pos)           /*!< 0x00000100 */
3480 #define ADC_IER_AWD2IE                    ADC_IER_AWD2IE_Msk                     /*!< ADC Analog watchdog 2 interrupt source */
3481 #define ADC_IER_AWD3IE_Pos                (9U)
3482 #define ADC_IER_AWD3IE_Msk                (0x1U << ADC_IER_AWD3IE_Pos)           /*!< 0x00000200 */
3483 #define ADC_IER_AWD3IE                    ADC_IER_AWD3IE_Msk                     /*!< ADC Analog watchdog 3 interrupt source */
3484 #define ADC_IER_JQOVFIE_Pos               (10U)
3485 #define ADC_IER_JQOVFIE_Msk               (0x1U << ADC_IER_JQOVFIE_Pos)          /*!< 0x00000400 */
3486 #define ADC_IER_JQOVFIE                   ADC_IER_JQOVFIE_Msk                    /*!< ADC Injected Context Queue Overflow interrupt source */
3487 
3488 /********************  Bit definition for ADC_CR register  ********************/
3489 #define ADC_CR_ADEN_Pos                   (0U)
3490 #define ADC_CR_ADEN_Msk                   (0x1U << ADC_CR_ADEN_Pos)            /*!< 0x00000001 */
3491 #define ADC_CR_ADEN                       ADC_CR_ADEN_Msk                      /*!< ADC Enable control */
3492 #define ADC_CR_ADDIS_Pos                  (1U)
3493 #define ADC_CR_ADDIS_Msk                  (0x1U << ADC_CR_ADDIS_Pos)           /*!< 0x00000002 */
3494 #define ADC_CR_ADDIS                      ADC_CR_ADDIS_Msk                     /*!< ADC Disable command */
3495 #define ADC_CR_ADSTART_Pos                (2U)
3496 #define ADC_CR_ADSTART_Msk                (0x1U << ADC_CR_ADSTART_Pos)         /*!< 0x00000004 */
3497 #define ADC_CR_ADSTART                    ADC_CR_ADSTART_Msk                   /*!< ADC Start of Regular conversion */
3498 #define ADC_CR_JADSTART_Pos               (3U)
3499 #define ADC_CR_JADSTART_Msk               (0x1U << ADC_CR_JADSTART_Pos)        /*!< 0x00000008 */
3500 #define ADC_CR_JADSTART                   ADC_CR_JADSTART_Msk                  /*!< ADC Start of injected conversion */
3501 #define ADC_CR_ADSTP_Pos                  (4U)
3502 #define ADC_CR_ADSTP_Msk                  (0x1U << ADC_CR_ADSTP_Pos)           /*!< 0x00000010 */
3503 #define ADC_CR_ADSTP                      ADC_CR_ADSTP_Msk                     /*!< ADC Stop of Regular conversion */
3504 #define ADC_CR_JADSTP_Pos                 (5U)
3505 #define ADC_CR_JADSTP_Msk                 (0x1U << ADC_CR_JADSTP_Pos)          /*!< 0x00000020 */
3506 #define ADC_CR_JADSTP                     ADC_CR_JADSTP_Msk                    /*!< ADC Stop of injected conversion */
3507 #define ADC_CR_BOOST_Pos                  (8U)
3508 #define ADC_CR_BOOST_Msk                  (0x1U << ADC_CR_BOOST_Pos)           /*!< 0x00000100 */
3509 #define ADC_CR_BOOST                      ADC_CR_BOOST_Msk                     /*!< ADC Boost Mode */
3510 #define ADC_CR_ADCALLIN_Pos               (16U)
3511 #define ADC_CR_ADCALLIN_Msk               (0x1U << ADC_CR_ADCALLIN_Pos)        /*!< 0x00010000 */
3512 #define ADC_CR_ADCALLIN                   ADC_CR_ADCALLIN_Msk                  /*!< ADC Linearity calibration */
3513 #define ADC_CR_LINCALRDYW1_Pos            (22U)
3514 #define ADC_CR_LINCALRDYW1_Msk            (0x1U << ADC_CR_LINCALRDYW1_Pos)     /*!< 0x00400000 */
3515 #define ADC_CR_LINCALRDYW1                ADC_CR_LINCALRDYW1_Msk               /*!< ADC Linearity calibration ready Word 1 */
3516 #define ADC_CR_LINCALRDYW2_Pos            (23U)
3517 #define ADC_CR_LINCALRDYW2_Msk            (0x1U << ADC_CR_LINCALRDYW2_Pos)     /*!< 0x00800000 */
3518 #define ADC_CR_LINCALRDYW2                ADC_CR_LINCALRDYW2_Msk               /*!< ADC Linearity calibration ready Word 2 */
3519 #define ADC_CR_LINCALRDYW3_Pos            (24U)
3520 #define ADC_CR_LINCALRDYW3_Msk            (0x1U << ADC_CR_LINCALRDYW3_Pos)     /*!< 0x01000000 */
3521 #define ADC_CR_LINCALRDYW3                ADC_CR_LINCALRDYW3_Msk               /*!< ADC Linearity calibration ready Word 3 */
3522 #define ADC_CR_LINCALRDYW4_Pos            (25U)
3523 #define ADC_CR_LINCALRDYW4_Msk            (0x1U << ADC_CR_LINCALRDYW4_Pos)     /*!< 0x02000000 */
3524 #define ADC_CR_LINCALRDYW4                ADC_CR_LINCALRDYW4_Msk               /*!< ADC Linearity calibration ready Word 4 */
3525 #define ADC_CR_LINCALRDYW5_Pos            (26U)
3526 #define ADC_CR_LINCALRDYW5_Msk            (0x1U << ADC_CR_LINCALRDYW5_Pos)     /*!< 0x04000000 */
3527 #define ADC_CR_LINCALRDYW5                ADC_CR_LINCALRDYW5_Msk               /*!< ADC Linearity calibration ready Word 5 */
3528 #define ADC_CR_LINCALRDYW6_Pos            (27U)
3529 #define ADC_CR_LINCALRDYW6_Msk            (0x1U << ADC_CR_LINCALRDYW6_Pos)     /*!< 0x08000000 */
3530 #define ADC_CR_LINCALRDYW6                ADC_CR_LINCALRDYW6_Msk               /*!< ADC Linearity calibration ready Word 6 */
3531 #define ADC_CR_ADVREGEN_Pos               (28U)
3532 #define ADC_CR_ADVREGEN_Msk               (0x1U << ADC_CR_ADVREGEN_Pos)        /*!< 0x10000000 */
3533 #define ADC_CR_ADVREGEN                   ADC_CR_ADVREGEN_Msk                  /*!< ADC Voltage regulator Enable */
3534 #define ADC_CR_DEEPPWD_Pos                (29U)
3535 #define ADC_CR_DEEPPWD_Msk                (0x1U << ADC_CR_DEEPPWD_Pos)         /*!< 0x20000000 */
3536 #define ADC_CR_DEEPPWD                    ADC_CR_DEEPPWD_Msk                   /*!< ADC Deep power down Enable */
3537 #define ADC_CR_ADCALDIF_Pos               (30U)
3538 #define ADC_CR_ADCALDIF_Msk               (0x1U << ADC_CR_ADCALDIF_Pos)        /*!< 0x40000000 */
3539 #define ADC_CR_ADCALDIF                   ADC_CR_ADCALDIF_Msk                  /*!< ADC Differential Mode for calibration */
3540 #define ADC_CR_ADCAL_Pos                  (31U)
3541 #define ADC_CR_ADCAL_Msk                  (0x1U << ADC_CR_ADCAL_Pos)           /*!< 0x80000000 */
3542 #define ADC_CR_ADCAL                      ADC_CR_ADCAL_Msk                     /*!< ADC Calibration */
3543 
3544 /********************  Bit definition for ADC_CFGR register  ********************/
3545 #define ADC_CFGR_DMNGT_Pos                (0U)
3546 #define ADC_CFGR_DMNGT_Msk                (0x3U << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000003 */
3547 #define ADC_CFGR_DMNGT                    ADC_CFGR_DMNGT_Msk                   /*!< ADC Data Management configuration */
3548 #define ADC_CFGR_DMNGT_0                  (0x1U << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000001 */
3549 #define ADC_CFGR_DMNGT_1                  (0x2U << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000002 */
3550 
3551 #define ADC_CFGR_RES_Pos                  (2U)
3552 #define ADC_CFGR_RES_Msk                  (0x7U << ADC_CFGR_RES_Pos)           /*!< 0x0000001C */
3553 #define ADC_CFGR_RES                      ADC_CFGR_RES_Msk                     /*!< ADC Data resolution */
3554 #define ADC_CFGR_RES_0                    (0x1U << ADC_CFGR_RES_Pos)           /*!< 0x00000004 */
3555 #define ADC_CFGR_RES_1                    (0x2U << ADC_CFGR_RES_Pos)           /*!< 0x00000008 */
3556 #define ADC_CFGR_RES_2                    (0x4U << ADC_CFGR_RES_Pos)           /*!< 0x00000010 */
3557 
3558 #define ADC_CFGR_EXTSEL_Pos               (5U)
3559 #define ADC_CFGR_EXTSEL_Msk               (0x1FU << ADC_CFGR_EXTSEL_Pos)       /*!< 0x000003E0 */
3560 #define ADC_CFGR_EXTSEL                   ADC_CFGR_EXTSEL_Msk                  /*!< ADC External trigger selection for regular group */
3561 #define ADC_CFGR_EXTSEL_0                 (0x01U << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000020 */
3562 #define ADC_CFGR_EXTSEL_1                 (0x02U << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000040 */
3563 #define ADC_CFGR_EXTSEL_2                 (0x04U << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000080 */
3564 #define ADC_CFGR_EXTSEL_3                 (0x08U << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000100 */
3565 #define ADC_CFGR_EXTSEL_4                 (0x10U << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000200 */
3566 
3567 #define ADC_CFGR_EXTEN_Pos                (10U)
3568 #define ADC_CFGR_EXTEN_Msk                (0x3U << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000C00 */
3569 #define ADC_CFGR_EXTEN                    ADC_CFGR_EXTEN_Msk                   /*!< ADC External trigger enable and polarity selection for regular channels */
3570 #define ADC_CFGR_EXTEN_0                  (0x1U << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000400 */
3571 #define ADC_CFGR_EXTEN_1                  (0x2U << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000800 */
3572 
3573 #define ADC_CFGR_OVRMOD_Pos               (12U)
3574 #define ADC_CFGR_OVRMOD_Msk               (0x1U << ADC_CFGR_OVRMOD_Pos)        /*!< 0x00001000 */
3575 #define ADC_CFGR_OVRMOD                   ADC_CFGR_OVRMOD_Msk                  /*!< ADC overrun mode */
3576 #define ADC_CFGR_CONT_Pos                 (13U)
3577 #define ADC_CFGR_CONT_Msk                 (0x1U << ADC_CFGR_CONT_Pos)          /*!< 0x00002000 */
3578 #define ADC_CFGR_CONT                     ADC_CFGR_CONT_Msk                    /*!< ADC Single/continuous conversion mode for regular conversion */
3579 #define ADC_CFGR_AUTDLY_Pos               (14U)
3580 #define ADC_CFGR_AUTDLY_Msk               (0x1U << ADC_CFGR_AUTDLY_Pos)        /*!< 0x00004000 */
3581 #define ADC_CFGR_AUTDLY                   ADC_CFGR_AUTDLY_Msk                  /*!< ADC Delayed conversion mode */
3582 
3583 #define ADC_CFGR_DISCEN_Pos               (16U)
3584 #define ADC_CFGR_DISCEN_Msk               (0x1U << ADC_CFGR_DISCEN_Pos)        /*!< 0x00010000 */
3585 #define ADC_CFGR_DISCEN                   ADC_CFGR_DISCEN_Msk                  /*!< ADC Discontinuous mode for regular channels */
3586 
3587 #define ADC_CFGR_DISCNUM_Pos              (17U)
3588 #define ADC_CFGR_DISCNUM_Msk              (0x7U << ADC_CFGR_DISCNUM_Pos)       /*!< 0x000E0000 */
3589 #define ADC_CFGR_DISCNUM                  ADC_CFGR_DISCNUM_Msk                 /*!< ADC Discontinuous mode channel count */
3590 #define ADC_CFGR_DISCNUM_0                (0x1U << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00020000 */
3591 #define ADC_CFGR_DISCNUM_1                (0x2U << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00040000 */
3592 #define ADC_CFGR_DISCNUM_2                (0x4U << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00080000 */
3593 
3594 #define ADC_CFGR_JDISCEN_Pos              (20U)
3595 #define ADC_CFGR_JDISCEN_Msk              (0x1U << ADC_CFGR_JDISCEN_Pos)       /*!< 0x00100000 */
3596 #define ADC_CFGR_JDISCEN                  ADC_CFGR_JDISCEN_Msk                 /*!< ADC Discontinuous mode on injected channels */
3597 #define ADC_CFGR_JQM_Pos                  (21U)
3598 #define ADC_CFGR_JQM_Msk                  (0x1U << ADC_CFGR_JQM_Pos)           /*!< 0x00200000 */
3599 #define ADC_CFGR_JQM                      ADC_CFGR_JQM_Msk                     /*!< ADC JSQR Queue mode */
3600 #define ADC_CFGR_AWD1SGL_Pos              (22U)
3601 #define ADC_CFGR_AWD1SGL_Msk              (0x1U << ADC_CFGR_AWD1SGL_Pos)       /*!< 0x00400000 */
3602 #define ADC_CFGR_AWD1SGL                  ADC_CFGR_AWD1SGL_Msk                 /*!< Enable the watchdog 1 on a single channel or on all channels */
3603 #define ADC_CFGR_AWD1EN_Pos               (23U)
3604 #define ADC_CFGR_AWD1EN_Msk               (0x1U << ADC_CFGR_AWD1EN_Pos)        /*!< 0x00800000 */
3605 #define ADC_CFGR_AWD1EN                   ADC_CFGR_AWD1EN_Msk                  /*!< ADC Analog watchdog 1 enable on regular Channels */
3606 #define ADC_CFGR_JAWD1EN_Pos              (24U)
3607 #define ADC_CFGR_JAWD1EN_Msk              (0x1U << ADC_CFGR_JAWD1EN_Pos)       /*!< 0x01000000 */
3608 #define ADC_CFGR_JAWD1EN                  ADC_CFGR_JAWD1EN_Msk                 /*!< ADC Analog watchdog 1 enable on injected Channels */
3609 #define ADC_CFGR_JAUTO_Pos                (25U)
3610 #define ADC_CFGR_JAUTO_Msk                (0x1U << ADC_CFGR_JAUTO_Pos)         /*!< 0x02000000 */
3611 #define ADC_CFGR_JAUTO                    ADC_CFGR_JAUTO_Msk                   /*!< ADC Automatic injected group conversion */
3612 
3613 #define ADC_CFGR_AWD1CH_Pos               (26U)
3614 #define ADC_CFGR_AWD1CH_Msk               (0x1FU << ADC_CFGR_AWD1CH_Pos)       /*!< 0x7C000000 */
3615 #define ADC_CFGR_AWD1CH                   ADC_CFGR_AWD1CH_Msk                  /*!< ADC Analog watchdog 1 Channel selection */
3616 #define ADC_CFGR_AWD1CH_0                 (0x01U << ADC_CFGR_AWD1CH_Pos)       /*!< 0x04000000 */
3617 #define ADC_CFGR_AWD1CH_1                 (0x02U << ADC_CFGR_AWD1CH_Pos)       /*!< 0x08000000 */
3618 #define ADC_CFGR_AWD1CH_2                 (0x04U << ADC_CFGR_AWD1CH_Pos)       /*!< 0x10000000 */
3619 #define ADC_CFGR_AWD1CH_3                 (0x08U << ADC_CFGR_AWD1CH_Pos)       /*!< 0x20000000 */
3620 #define ADC_CFGR_AWD1CH_4                 (0x10U << ADC_CFGR_AWD1CH_Pos)       /*!< 0x40000000 */
3621 
3622 #define ADC_CFGR_JQDIS_Pos                (31U)
3623 #define ADC_CFGR_JQDIS_Msk                (0x1U << ADC_CFGR_JQDIS_Pos)         /*!< 0x80000000 */
3624 #define ADC_CFGR_JQDIS                    ADC_CFGR_JQDIS_Msk                   /*!< ADC Injected queue disable */
3625 
3626 /********************  Bit definition for ADC_CFGR2 register  ********************/
3627 #define ADC_CFGR2_ROVSE_Pos               (0U)
3628 #define ADC_CFGR2_ROVSE_Msk               (0x1U << ADC_CFGR2_ROVSE_Pos)        /*!< 0x00000001 */
3629 #define ADC_CFGR2_ROVSE                   ADC_CFGR2_ROVSE_Msk                  /*!< ADC Regular group oversampler enable */
3630 #define ADC_CFGR2_JOVSE_Pos               (1U)
3631 #define ADC_CFGR2_JOVSE_Msk               (0x1U << ADC_CFGR2_JOVSE_Pos)        /*!< 0x00000002 */
3632 #define ADC_CFGR2_JOVSE                   ADC_CFGR2_JOVSE_Msk                  /*!< ADC Injected group oversampler enable */
3633 
3634 #define ADC_CFGR2_OVSR_Pos                (2U)
3635 #define ADC_CFGR2_OVSR_Msk                (0x7U << ADC_CFGR2_OVSR_Pos)         /*!< 0x0000001C */
3636 #define ADC_CFGR2_OVSR                    ADC_CFGR2_OVSR_Msk                   /*!< ADC Regular group oversampler enable TO Be removed after ADC driver update*/
3637 #define ADC_CFGR2_OVSR_0                  (0x1U << ADC_CFGR2_OVSR_Pos)         /*!< 0x00000004 */
3638 #define ADC_CFGR2_OVSR_1                  (0x2U << ADC_CFGR2_OVSR_Pos)         /*!< 0x00000008 */
3639 #define ADC_CFGR2_OVSR_2                  (0x4U << ADC_CFGR2_OVSR_Pos)         /*!< 0x00000010 */
3640 
3641 #define ADC_CFGR2_OVSS_Pos                (5U)
3642 #define ADC_CFGR2_OVSS_Msk                (0xFU << ADC_CFGR2_OVSS_Pos)         /*!< 0x000001E0 */
3643 #define ADC_CFGR2_OVSS                    ADC_CFGR2_OVSS_Msk                   /*!< ADC Regular Oversampling shift */
3644 #define ADC_CFGR2_OVSS_0                  (0x1U << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000020 */
3645 #define ADC_CFGR2_OVSS_1                  (0x2U << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000040 */
3646 #define ADC_CFGR2_OVSS_2                  (0x4U << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000080 */
3647 #define ADC_CFGR2_OVSS_3                  (0x8U << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000100 */
3648 
3649 #define ADC_CFGR2_TROVS_Pos               (9U)
3650 #define ADC_CFGR2_TROVS_Msk               (0x1U << ADC_CFGR2_TROVS_Pos)        /*!< 0x00000200 */
3651 #define ADC_CFGR2_TROVS                   ADC_CFGR2_TROVS_Msk                  /*!< ADC Triggered regular Oversampling */
3652 #define ADC_CFGR2_ROVSM_Pos               (10U)
3653 #define ADC_CFGR2_ROVSM_Msk               (0x1U << ADC_CFGR2_ROVSM_Pos)        /*!< 0x00000400 */
3654 #define ADC_CFGR2_ROVSM                   ADC_CFGR2_ROVSM_Msk                  /*!< ADC Regular oversampling mode */
3655 
3656 #define ADC_CFGR2_RSHIFT1_Pos             (11U)
3657 #define ADC_CFGR2_RSHIFT1_Msk             (0x1U << ADC_CFGR2_RSHIFT1_Pos)      /*!< 0x00000800 */
3658 #define ADC_CFGR2_RSHIFT1                 ADC_CFGR2_RSHIFT1_Msk                /*!< ADC Right-shift data after Offset 1 correction */
3659 #define ADC_CFGR2_RSHIFT2_Pos             (12U)
3660 #define ADC_CFGR2_RSHIFT2_Msk             (0x1U << ADC_CFGR2_RSHIFT2_Pos)      /*!< 0x00001000 */
3661 #define ADC_CFGR2_RSHIFT2                 ADC_CFGR2_RSHIFT2_Msk                /*!< ADC Right-shift data after Offset 2 correction */
3662 #define ADC_CFGR2_RSHIFT3_Pos             (13U)
3663 #define ADC_CFGR2_RSHIFT3_Msk             (0x1U << ADC_CFGR2_RSHIFT3_Pos)      /*!< 0x00002000 */
3664 #define ADC_CFGR2_RSHIFT3                 ADC_CFGR2_RSHIFT3_Msk                /*!< ADC Right-shift data after Offset 3 correction */
3665 #define ADC_CFGR2_RSHIFT4_Pos             (14U)
3666 #define ADC_CFGR2_RSHIFT4_Msk             (0x1U << ADC_CFGR2_RSHIFT4_Pos)      /*!< 0x00004000 */
3667 #define ADC_CFGR2_RSHIFT4                 ADC_CFGR2_RSHIFT4_Msk                /*!< ADC Right-shift data after Offset 4 correction */
3668 
3669 #define ADC_CFGR2_OSR_Pos                 (16U)
3670 #define ADC_CFGR2_OSR_Msk                 (0x3FFU << ADC_CFGR2_OSR_Pos)        /*!< 0x03FF0000 */
3671 #define ADC_CFGR2_OSR                     ADC_CFGR2_OSR_Msk                    /*!< ADC oversampling Ratio */
3672 #define ADC_CFGR2_OSR_0                   (0x001U << ADC_CFGR2_OSR_Pos)        /*!< 0x00010000 */
3673 #define ADC_CFGR2_OSR_1                   (0x002U << ADC_CFGR2_OSR_Pos)        /*!< 0x00020000 */
3674 #define ADC_CFGR2_OSR_2                   (0x004U << ADC_CFGR2_OSR_Pos)        /*!< 0x00040000 */
3675 #define ADC_CFGR2_OSR_3                   (0x008U << ADC_CFGR2_OSR_Pos)        /*!< 0x00080000 */
3676 #define ADC_CFGR2_OSR_4                   (0x010U << ADC_CFGR2_OSR_Pos)        /*!< 0x00100000 */
3677 #define ADC_CFGR2_OSR_5                   (0x020U << ADC_CFGR2_OSR_Pos)        /*!< 0x00200000 */
3678 #define ADC_CFGR2_OSR_6                   (0x040U << ADC_CFGR2_OSR_Pos)        /*!< 0x00400000 */
3679 #define ADC_CFGR2_OSR_7                   (0x080U << ADC_CFGR2_OSR_Pos)        /*!< 0x00800000 */
3680 #define ADC_CFGR2_OSR_8                   (0x100U << ADC_CFGR2_OSR_Pos)        /*!< 0x01000000 */
3681 #define ADC_CFGR2_OSR_9                   (0x200U << ADC_CFGR2_OSR_Pos)        /*!< 0x02000000 */
3682 
3683 #define ADC_CFGR2_LSHIFT_Pos              (28U)
3684 #define ADC_CFGR2_LSHIFT_Msk              (0xFU << ADC_CFGR2_LSHIFT_Pos)       /*!< 0xF0000000 */
3685 #define ADC_CFGR2_LSHIFT                  ADC_CFGR2_LSHIFT_Msk                 /*!< ADC Left shift factor */
3686 #define ADC_CFGR2_LSHIFT_0                (0x1U << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x10000000 */
3687 #define ADC_CFGR2_LSHIFT_1                (0x2U << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x20000000 */
3688 #define ADC_CFGR2_LSHIFT_2                (0x4U << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x40000000 */
3689 #define ADC_CFGR2_LSHIFT_3                (0x8U << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x80000000 */
3690 
3691 /********************  Bit definition for ADC_SMPR1 register  ********************/
3692 #define ADC_SMPR1_SMP0_Pos                (0U)
3693 #define ADC_SMPR1_SMP0_Msk                (0x7U << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000007 */
3694 #define ADC_SMPR1_SMP0                    ADC_SMPR1_SMP0_Msk                   /*!< ADC Channel 0 Sampling time selection  */
3695 #define ADC_SMPR1_SMP0_0                  (0x1U << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000001 */
3696 #define ADC_SMPR1_SMP0_1                  (0x2U << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000002 */
3697 #define ADC_SMPR1_SMP0_2                  (0x4U << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000004 */
3698 
3699 #define ADC_SMPR1_SMP1_Pos                (3U)
3700 #define ADC_SMPR1_SMP1_Msk                (0x7U << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000038 */
3701 #define ADC_SMPR1_SMP1                    ADC_SMPR1_SMP1_Msk                   /*!< ADC Channel 1 Sampling time selection  */
3702 #define ADC_SMPR1_SMP1_0                  (0x1U << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000008 */
3703 #define ADC_SMPR1_SMP1_1                  (0x2U << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000010 */
3704 #define ADC_SMPR1_SMP1_2                  (0x4U << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000020 */
3705 
3706 #define ADC_SMPR1_SMP2_Pos                (6U)
3707 #define ADC_SMPR1_SMP2_Msk                (0x7U << ADC_SMPR1_SMP2_Pos)         /*!< 0x000001C0 */
3708 #define ADC_SMPR1_SMP2                    ADC_SMPR1_SMP2_Msk                   /*!< ADC Channel 2 Sampling time selection  */
3709 #define ADC_SMPR1_SMP2_0                  (0x1U << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000040 */
3710 #define ADC_SMPR1_SMP2_1                  (0x2U << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000080 */
3711 #define ADC_SMPR1_SMP2_2                  (0x4U << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000100 */
3712 
3713 #define ADC_SMPR1_SMP3_Pos                (9U)
3714 #define ADC_SMPR1_SMP3_Msk                (0x7U << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000E00 */
3715 #define ADC_SMPR1_SMP3                    ADC_SMPR1_SMP3_Msk                   /*!< ADC Channel 3 Sampling time selection  */
3716 #define ADC_SMPR1_SMP3_0                  (0x1U << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000200 */
3717 #define ADC_SMPR1_SMP3_1                  (0x2U << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000400 */
3718 #define ADC_SMPR1_SMP3_2                  (0x4U << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000800 */
3719 
3720 #define ADC_SMPR1_SMP4_Pos                (12U)
3721 #define ADC_SMPR1_SMP4_Msk                (0x7U << ADC_SMPR1_SMP4_Pos)         /*!< 0x00007000 */
3722 #define ADC_SMPR1_SMP4                    ADC_SMPR1_SMP4_Msk                   /*!< ADC Channel 4 Sampling time selection  */
3723 #define ADC_SMPR1_SMP4_0                  (0x1U << ADC_SMPR1_SMP4_Pos)         /*!< 0x00001000 */
3724 #define ADC_SMPR1_SMP4_1                  (0x2U << ADC_SMPR1_SMP4_Pos)         /*!< 0x00002000 */
3725 #define ADC_SMPR1_SMP4_2                  (0x4U << ADC_SMPR1_SMP4_Pos)         /*!< 0x00004000 */
3726 
3727 #define ADC_SMPR1_SMP5_Pos                (15U)
3728 #define ADC_SMPR1_SMP5_Msk                (0x7U << ADC_SMPR1_SMP5_Pos)         /*!< 0x00038000 */
3729 #define ADC_SMPR1_SMP5                    ADC_SMPR1_SMP5_Msk                   /*!< ADC Channel 5 Sampling time selection  */
3730 #define ADC_SMPR1_SMP5_0                  (0x1U << ADC_SMPR1_SMP5_Pos)         /*!< 0x00008000 */
3731 #define ADC_SMPR1_SMP5_1                  (0x2U << ADC_SMPR1_SMP5_Pos)         /*!< 0x00010000 */
3732 #define ADC_SMPR1_SMP5_2                  (0x4U << ADC_SMPR1_SMP5_Pos)         /*!< 0x00020000 */
3733 
3734 #define ADC_SMPR1_SMP6_Pos                (18U)
3735 #define ADC_SMPR1_SMP6_Msk                (0x7U << ADC_SMPR1_SMP6_Pos)         /*!< 0x001C0000 */
3736 #define ADC_SMPR1_SMP6                    ADC_SMPR1_SMP6_Msk                   /*!< ADC Channel 6 Sampling time selection  */
3737 #define ADC_SMPR1_SMP6_0                  (0x1U << ADC_SMPR1_SMP6_Pos)         /*!< 0x00040000 */
3738 #define ADC_SMPR1_SMP6_1                  (0x2U << ADC_SMPR1_SMP6_Pos)         /*!< 0x00080000 */
3739 #define ADC_SMPR1_SMP6_2                  (0x4U << ADC_SMPR1_SMP6_Pos)         /*!< 0x00100000 */
3740 
3741 #define ADC_SMPR1_SMP7_Pos                (21U)
3742 #define ADC_SMPR1_SMP7_Msk                (0x7U << ADC_SMPR1_SMP7_Pos)         /*!< 0x00E00000 */
3743 #define ADC_SMPR1_SMP7                    ADC_SMPR1_SMP7_Msk                   /*!< ADC Channel 7 Sampling time selection  */
3744 #define ADC_SMPR1_SMP7_0                  (0x1U << ADC_SMPR1_SMP7_Pos)         /*!< 0x00200000 */
3745 #define ADC_SMPR1_SMP7_1                  (0x2U << ADC_SMPR1_SMP7_Pos)         /*!< 0x00400000 */
3746 #define ADC_SMPR1_SMP7_2                  (0x4U << ADC_SMPR1_SMP7_Pos)         /*!< 0x00800000 */
3747 
3748 #define ADC_SMPR1_SMP8_Pos                (24U)
3749 #define ADC_SMPR1_SMP8_Msk                (0x7U << ADC_SMPR1_SMP8_Pos)         /*!< 0x07000000 */
3750 #define ADC_SMPR1_SMP8                    ADC_SMPR1_SMP8_Msk                   /*!< ADC Channel 8 Sampling time selection  */
3751 #define ADC_SMPR1_SMP8_0                  (0x1U << ADC_SMPR1_SMP8_Pos)         /*!< 0x01000000 */
3752 #define ADC_SMPR1_SMP8_1                  (0x2U << ADC_SMPR1_SMP8_Pos)         /*!< 0x02000000 */
3753 #define ADC_SMPR1_SMP8_2                  (0x4U << ADC_SMPR1_SMP8_Pos)         /*!< 0x04000000 */
3754 
3755 #define ADC_SMPR1_SMP9_Pos                (27U)
3756 #define ADC_SMPR1_SMP9_Msk                (0x7U << ADC_SMPR1_SMP9_Pos)         /*!< 0x38000000 */
3757 #define ADC_SMPR1_SMP9                    ADC_SMPR1_SMP9_Msk                   /*!< ADC Channel 9 Sampling time selection  */
3758 #define ADC_SMPR1_SMP9_0                  (0x1U << ADC_SMPR1_SMP9_Pos)         /*!< 0x08000000 */
3759 #define ADC_SMPR1_SMP9_1                  (0x2U << ADC_SMPR1_SMP9_Pos)         /*!< 0x10000000 */
3760 #define ADC_SMPR1_SMP9_2                  (0x4U << ADC_SMPR1_SMP9_Pos)         /*!< 0x20000000 */
3761 
3762 /********************  Bit definition for ADC_SMPR2 register  ********************/
3763 #define ADC_SMPR2_SMP10_Pos               (0U)
3764 #define ADC_SMPR2_SMP10_Msk               (0x7U << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000007 */
3765 #define ADC_SMPR2_SMP10                   ADC_SMPR2_SMP10_Msk                  /*!< ADC Channel 10 Sampling time selection  */
3766 #define ADC_SMPR2_SMP10_0                 (0x1U << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000001 */
3767 #define ADC_SMPR2_SMP10_1                 (0x2U << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000002 */
3768 #define ADC_SMPR2_SMP10_2                 (0x4U << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000004 */
3769 
3770 #define ADC_SMPR2_SMP11_Pos               (3U)
3771 #define ADC_SMPR2_SMP11_Msk               (0x7U << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000038 */
3772 #define ADC_SMPR2_SMP11                   ADC_SMPR2_SMP11_Msk                  /*!< ADC Channel 11 Sampling time selection  */
3773 #define ADC_SMPR2_SMP11_0                 (0x1U << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000008 */
3774 #define ADC_SMPR2_SMP11_1                 (0x2U << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000010 */
3775 #define ADC_SMPR2_SMP11_2                 (0x4U << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000020 */
3776 
3777 #define ADC_SMPR2_SMP12_Pos               (6U)
3778 #define ADC_SMPR2_SMP12_Msk               (0x7U << ADC_SMPR2_SMP12_Pos)        /*!< 0x000001C0 */
3779 #define ADC_SMPR2_SMP12                   ADC_SMPR2_SMP12_Msk                  /*!< ADC Channel 12 Sampling time selection  */
3780 #define ADC_SMPR2_SMP12_0                 (0x1U << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000040 */
3781 #define ADC_SMPR2_SMP12_1                 (0x2U << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000080 */
3782 #define ADC_SMPR2_SMP12_2                 (0x4U << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000100 */
3783 
3784 #define ADC_SMPR2_SMP13_Pos               (9U)
3785 #define ADC_SMPR2_SMP13_Msk               (0x7U << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000E00 */
3786 #define ADC_SMPR2_SMP13                   ADC_SMPR2_SMP13_Msk                  /*!< ADC Channel 13 Sampling time selection  */
3787 #define ADC_SMPR2_SMP13_0                 (0x1U << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000200 */
3788 #define ADC_SMPR2_SMP13_1                 (0x2U << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000400 */
3789 #define ADC_SMPR2_SMP13_2                 (0x4U << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000800 */
3790 
3791 #define ADC_SMPR2_SMP14_Pos               (12U)
3792 #define ADC_SMPR2_SMP14_Msk               (0x7U << ADC_SMPR2_SMP14_Pos)        /*!< 0x00007000 */
3793 #define ADC_SMPR2_SMP14                   ADC_SMPR2_SMP14_Msk                  /*!< ADC Channel 14 Sampling time selection  */
3794 #define ADC_SMPR2_SMP14_0                 (0x1U << ADC_SMPR2_SMP14_Pos)        /*!< 0x00001000 */
3795 #define ADC_SMPR2_SMP14_1                 (0x2U << ADC_SMPR2_SMP14_Pos)        /*!< 0x00002000 */
3796 #define ADC_SMPR2_SMP14_2                 (0x4U << ADC_SMPR2_SMP14_Pos)        /*!< 0x00004000 */
3797 
3798 #define ADC_SMPR2_SMP15_Pos               (15U)
3799 #define ADC_SMPR2_SMP15_Msk               (0x7U << ADC_SMPR2_SMP15_Pos)        /*!< 0x00038000 */
3800 #define ADC_SMPR2_SMP15                   ADC_SMPR2_SMP15_Msk                  /*!< ADC Channel 15 Sampling time selection  */
3801 #define ADC_SMPR2_SMP15_0                 (0x1U << ADC_SMPR2_SMP15_Pos)        /*!< 0x00008000 */
3802 #define ADC_SMPR2_SMP15_1                 (0x2U << ADC_SMPR2_SMP15_Pos)        /*!< 0x00010000 */
3803 #define ADC_SMPR2_SMP15_2                 (0x4U << ADC_SMPR2_SMP15_Pos)        /*!< 0x00020000 */
3804 
3805 #define ADC_SMPR2_SMP16_Pos               (18U)
3806 #define ADC_SMPR2_SMP16_Msk               (0x7U << ADC_SMPR2_SMP16_Pos)        /*!< 0x001C0000 */
3807 #define ADC_SMPR2_SMP16                   ADC_SMPR2_SMP16_Msk                  /*!< ADC Channel 16 Sampling time selection  */
3808 #define ADC_SMPR2_SMP16_0                 (0x1U << ADC_SMPR2_SMP16_Pos)        /*!< 0x00040000 */
3809 #define ADC_SMPR2_SMP16_1                 (0x2U << ADC_SMPR2_SMP16_Pos)        /*!< 0x00080000 */
3810 #define ADC_SMPR2_SMP16_2                 (0x4U << ADC_SMPR2_SMP16_Pos)        /*!< 0x00100000 */
3811 
3812 #define ADC_SMPR2_SMP17_Pos               (21U)
3813 #define ADC_SMPR2_SMP17_Msk               (0x7U << ADC_SMPR2_SMP17_Pos)        /*!< 0x00E00000 */
3814 #define ADC_SMPR2_SMP17                   ADC_SMPR2_SMP17_Msk                  /*!< ADC Channel 17 Sampling time selection  */
3815 #define ADC_SMPR2_SMP17_0                 (0x1U << ADC_SMPR2_SMP17_Pos)        /*!< 0x00200000 */
3816 #define ADC_SMPR2_SMP17_1                 (0x2U << ADC_SMPR2_SMP17_Pos)        /*!< 0x00400000 */
3817 #define ADC_SMPR2_SMP17_2                 (0x4U << ADC_SMPR2_SMP17_Pos)        /*!< 0x00800000 */
3818 
3819 #define ADC_SMPR2_SMP18_Pos               (24U)
3820 #define ADC_SMPR2_SMP18_Msk               (0x7U << ADC_SMPR2_SMP18_Pos)        /*!< 0x07000000 */
3821 #define ADC_SMPR2_SMP18                   ADC_SMPR2_SMP18_Msk                  /*!< ADC Channel 18 Sampling time selection  */
3822 #define ADC_SMPR2_SMP18_0                 (0x1U << ADC_SMPR2_SMP18_Pos)        /*!< 0x01000000 */
3823 #define ADC_SMPR2_SMP18_1                 (0x2U << ADC_SMPR2_SMP18_Pos)        /*!< 0x02000000 */
3824 #define ADC_SMPR2_SMP18_2                 (0x4U << ADC_SMPR2_SMP18_Pos)        /*!< 0x04000000 */
3825 
3826 #define ADC_SMPR2_SMP19_Pos               (27U)
3827 #define ADC_SMPR2_SMP19_Msk               (0x7U << ADC_SMPR2_SMP19_Pos)        /*!< 0x38000000 */
3828 #define ADC_SMPR2_SMP19                   ADC_SMPR2_SMP19_Msk                  /*!< ADC Channel 19 Sampling time selection  */
3829 #define ADC_SMPR2_SMP19_0                 (0x1U << ADC_SMPR2_SMP19_Pos)        /*!< 0x08000000 */
3830 #define ADC_SMPR2_SMP19_1                 (0x2U << ADC_SMPR2_SMP19_Pos)        /*!< 0x10000000 */
3831 #define ADC_SMPR2_SMP19_2                 (0x4U << ADC_SMPR2_SMP19_Pos)        /*!< 0x20000000 */
3832 
3833 /********************  Bit definition for ADC_PCSEL register  ********************/
3834 #define ADC_PCSEL_PCSEL_Pos               (0U)
3835 #define ADC_PCSEL_PCSEL_Msk               (0xFFFFFU << ADC_PCSEL_PCSEL_Pos)    /*!< 0x000FFFFF */
3836 #define ADC_PCSEL_PCSEL                   ADC_PCSEL_PCSEL_Msk                  /*!< ADC pre channel selection */
3837 #define ADC_PCSEL_PCSEL_0                 (0x00001U << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000001 */
3838 #define ADC_PCSEL_PCSEL_1                 (0x00002U << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000002 */
3839 #define ADC_PCSEL_PCSEL_2                 (0x00004U << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000004 */
3840 #define ADC_PCSEL_PCSEL_3                 (0x00008U << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000008 */
3841 #define ADC_PCSEL_PCSEL_4                 (0x00010U << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000010 */
3842 #define ADC_PCSEL_PCSEL_5                 (0x00020U << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000020 */
3843 #define ADC_PCSEL_PCSEL_6                 (0x00040U << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000040 */
3844 #define ADC_PCSEL_PCSEL_7                 (0x00080U << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000080 */
3845 #define ADC_PCSEL_PCSEL_8                 (0x00100U << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000100 */
3846 #define ADC_PCSEL_PCSEL_9                 (0x00200U << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000200 */
3847 #define ADC_PCSEL_PCSEL_10                (0x00400U << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000400 */
3848 #define ADC_PCSEL_PCSEL_11                (0x00800U << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000800 */
3849 #define ADC_PCSEL_PCSEL_12                (0x01000U << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00001000 */
3850 #define ADC_PCSEL_PCSEL_13                (0x02000U << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00002000 */
3851 #define ADC_PCSEL_PCSEL_14                (0x04000U << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00004000 */
3852 #define ADC_PCSEL_PCSEL_15                (0x08000U << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00008000 */
3853 #define ADC_PCSEL_PCSEL_16                (0x10000U << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00010000 */
3854 #define ADC_PCSEL_PCSEL_17                (0x20000U << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00020000 */
3855 #define ADC_PCSEL_PCSEL_18                (0x40000U << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00040000 */
3856 #define ADC_PCSEL_PCSEL_19                (0x80000U << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00080000 */
3857 
3858 /********************  Bit definition for ADC_LTR1 register  ********************/
3859 #define ADC_LTR1_LT1_Pos                  (0U)
3860 #define ADC_LTR1_LT1_Msk                  (0x3FFFFFFU << ADC_LTR1_LT1_Pos)     /*!< 0x03FFFFFF */
3861 #define ADC_LTR1_LT1                      ADC_LTR1_LT1_Msk                     /*!< ADC Analog watchdog 1 lower threshold */
3862 #define ADC_LTR1_LT1_0                    (0x0000001U << ADC_LTR1_LT1_Pos)     /*!< 0x00000001 */
3863 #define ADC_LTR1_LT1_1                    (0x0000002U << ADC_LTR1_LT1_Pos)     /*!< 0x00000002 */
3864 #define ADC_LTR1_LT1_2                    (0x0000004U << ADC_LTR1_LT1_Pos)     /*!< 0x00000004 */
3865 #define ADC_LTR1_LT1_3                    (0x0000008U << ADC_LTR1_LT1_Pos)     /*!< 0x00000008 */
3866 #define ADC_LTR1_LT1_4                    (0x0000010U << ADC_LTR1_LT1_Pos)     /*!< 0x00000010 */
3867 #define ADC_LTR1_LT1_5                    (0x0000020U << ADC_LTR1_LT1_Pos)     /*!< 0x00000020 */
3868 #define ADC_LTR1_LT1_6                    (0x0000040U << ADC_LTR1_LT1_Pos)     /*!< 0x00000040 */
3869 #define ADC_LTR1_LT1_7                    (0x0000080U << ADC_LTR1_LT1_Pos)     /*!< 0x00000080 */
3870 #define ADC_LTR1_LT1_8                    (0x0000100U << ADC_LTR1_LT1_Pos)     /*!< 0x00000100 */
3871 #define ADC_LTR1_LT1_9                    (0x0000200U << ADC_LTR1_LT1_Pos)     /*!< 0x00000200 */
3872 #define ADC_LTR1_LT1_10                   (0x0000400U << ADC_LTR1_LT1_Pos)     /*!< 0x00000400 */
3873 #define ADC_LTR1_LT1_11                   (0x0000800U << ADC_LTR1_LT1_Pos)     /*!< 0x00000800 */
3874 #define ADC_LTR1_LT1_12                   (0x0001000U << ADC_LTR1_LT1_Pos)     /*!< 0x00001000 */
3875 #define ADC_LTR1_LT1_13                   (0x0002000U << ADC_LTR1_LT1_Pos)     /*!< 0x00002000 */
3876 #define ADC_LTR1_LT1_14                   (0x0004000U << ADC_LTR1_LT1_Pos)     /*!< 0x00004000 */
3877 #define ADC_LTR1_LT1_15                   (0x0008000U << ADC_LTR1_LT1_Pos)     /*!< 0x00008000 */
3878 #define ADC_LTR1_LT1_16                   (0x0010000U << ADC_LTR1_LT1_Pos)     /*!< 0x00010000 */
3879 #define ADC_LTR1_LT1_17                   (0x0020000U << ADC_LTR1_LT1_Pos)     /*!< 0x00020000 */
3880 #define ADC_LTR1_LT1_18                   (0x0040000U << ADC_LTR1_LT1_Pos)     /*!< 0x00040000 */
3881 #define ADC_LTR1_LT1_19                   (0x0080000U << ADC_LTR1_LT1_Pos)     /*!< 0x00080000 */
3882 #define ADC_LTR1_LT1_20                   (0x0100000U << ADC_LTR1_LT1_Pos)     /*!< 0x00100000 */
3883 #define ADC_LTR1_LT1_21                   (0x0200000U << ADC_LTR1_LT1_Pos)     /*!< 0x00200000 */
3884 #define ADC_LTR1_LT1_22                   (0x0400000U << ADC_LTR1_LT1_Pos)     /*!< 0x00400000 */
3885 #define ADC_LTR1_LT1_23                   (0x0800000U << ADC_LTR1_LT1_Pos)     /*!< 0x00800000 */
3886 #define ADC_LTR1_LT1_24                   (0x1000000U << ADC_LTR1_LT1_Pos)     /*!< 0x01000000 */
3887 #define ADC_LTR1_LT1_25                   (0x2000000U << ADC_LTR1_LT1_Pos)     /*!< 0x02000000 */
3888 
3889 /********************  Bit definition for ADC_HTR1 register  ********************/
3890 #define ADC_HTR1_HT1         ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 1 higher threshold */
3891 #define ADC_HTR1_HT1_0                    ((uint32_t)0x00000001)               /*!< ADC HT1 bit 0 */
3892 #define ADC_HTR1_HT1_1                    ((uint32_t)0x00000002)               /*!< ADC HT1 bit 1 */
3893 #define ADC_HTR1_HT1_2                    ((uint32_t)0x00000004)               /*!< ADC HT1 bit 2 */
3894 #define ADC_HTR1_HT1_3                    ((uint32_t)0x00000008)               /*!< ADC HT1 bit 3 */
3895 #define ADC_HTR1_HT1_4                    ((uint32_t)0x00000010)               /*!< ADC HT1 bit 4 */
3896 #define ADC_HTR1_HT1_5                    ((uint32_t)0x00000020)               /*!< ADC HT1 bit 5 */
3897 #define ADC_HTR1_HT1_6                    ((uint32_t)0x00000040)               /*!< ADC HT1 bit 6 */
3898 #define ADC_HTR1_HT1_7                    ((uint32_t)0x00000080)               /*!< ADC HT1 bit 7 */
3899 #define ADC_HTR1_HT1_8                    ((uint32_t)0x00000100)               /*!< ADC HT1 bit 8 */
3900 #define ADC_HTR1_HT1_9                    ((uint32_t)0x00000200)               /*!< ADC HT1 bit 9 */
3901 #define ADC_HTR1_HT1_10                   ((uint32_t)0x00000400)               /*!< ADC HT1 bit 10 */
3902 #define ADC_HTR1_HT1_11                   ((uint32_t)0x00000800)               /*!< ADC HT1 bit 11 */
3903 #define ADC_HTR1_HT1_12                   ((uint32_t)0x00001000)               /*!< ADC HT1 bit 12 */
3904 #define ADC_HTR1_HT1_13                   ((uint32_t)0x00002000)               /*!< ADC HT1 bit 13 */
3905 #define ADC_HTR1_HT1_14                   ((uint32_t)0x00004000)               /*!< ADC HT1 bit 14 */
3906 #define ADC_HTR1_HT1_15                   ((uint32_t)0x00008000)               /*!< ADC HT1 bit 15 */
3907 #define ADC_HTR1_HT1_16                   ((uint32_t)0x00010000)               /*!< ADC HT1 bit 16 */
3908 #define ADC_HTR1_HT1_17                   ((uint32_t)0x00020000)               /*!< ADC HT1 bit 17 */
3909 #define ADC_HTR1_HT1_18                   ((uint32_t)0x00040000)               /*!< ADC HT1 bit 18 */
3910 #define ADC_HTR1_HT1_19                   ((uint32_t)0x00080000)               /*!< ADC HT1 bit 19 */
3911 #define ADC_HTR1_HT1_20                   ((uint32_t)0x00100000)               /*!< ADC HT1 bit 20 */
3912 #define ADC_HTR1_HT1_21                   ((uint32_t)0x00200000)               /*!< ADC HT1 bit 21 */
3913 #define ADC_HTR1_HT1_22                   ((uint32_t)0x00400000)               /*!< ADC HT1 bit 22 */
3914 #define ADC_HTR1_HT1_23                   ((uint32_t)0x00800000)               /*!< ADC HT1 bit 23 */
3915 #define ADC_HTR1_HT1_24                   ((uint32_t)0x01000000)               /*!< ADC HT1 bit 24 */
3916 #define ADC_HTR1_HT1_25                   ((uint32_t)0x02000000)               /*!< ADC HT1 bit 25 */
3917 
3918 /********************  Bit definition for ADC_LTR2 register  ********************/
3919 #define ADC_LTR2_LT2         ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */
3920 #define ADC_LTR2_LT2_0                    ((uint32_t)0x00000001)               /*!< ADC LT2 bit 0 */
3921 #define ADC_LTR2_LT2_1                    ((uint32_t)0x00000002)               /*!< ADC LT2 bit 1 */
3922 #define ADC_LTR2_LT2_2                    ((uint32_t)0x00000004)               /*!< ADC LT2 bit 2 */
3923 #define ADC_LTR2_LT2_3                    ((uint32_t)0x00000008)               /*!< ADC LT2 bit 3 */
3924 #define ADC_LTR2_LT2_4                    ((uint32_t)0x00000010)               /*!< ADC LT2 bit 4 */
3925 #define ADC_LTR2_LT2_5                    ((uint32_t)0x00000020)               /*!< ADC LT2 bit 5 */
3926 #define ADC_LTR2_LT2_6                    ((uint32_t)0x00000040)               /*!< ADC LT2 bit 6 */
3927 #define ADC_LTR2_LT2_7                    ((uint32_t)0x00000080)               /*!< ADC LT2 bit 7 */
3928 #define ADC_LTR2_LT2_8                    ((uint32_t)0x00000100)               /*!< ADC LT2 bit 8 */
3929 #define ADC_LTR2_LT2_9                    ((uint32_t)0x00000200)               /*!< ADC LT2 bit 9 */
3930 #define ADC_LTR2_LT2_10                   ((uint32_t)0x00000400)               /*!< ADC LT2 bit 10 */
3931 #define ADC_LTR2_LT2_11                   ((uint32_t)0x00000800)               /*!< ADC LT2 bit 11 */
3932 #define ADC_LTR2_LT2_12                   ((uint32_t)0x00001000)               /*!< ADC LT2 bit 12 */
3933 #define ADC_LTR2_LT2_13                   ((uint32_t)0x00002000)               /*!< ADC LT2 bit 13 */
3934 #define ADC_LTR2_LT2_14                   ((uint32_t)0x00004000)               /*!< ADC LT2 bit 14 */
3935 #define ADC_LTR2_LT2_15                   ((uint32_t)0x00008000)               /*!< ADC LT2 bit 15 */
3936 #define ADC_LTR2_LT2_16                   ((uint32_t)0x00010000)               /*!< ADC LT2 bit 16 */
3937 #define ADC_LTR2_LT2_17                   ((uint32_t)0x00020000)               /*!< ADC LT2 bit 17 */
3938 #define ADC_LTR2_LT2_18                   ((uint32_t)0x00040000)               /*!< ADC LT2 bit 18 */
3939 #define ADC_LTR2_LT2_19                   ((uint32_t)0x00080000)               /*!< ADC LT2 bit 19 */
3940 #define ADC_LTR2_LT2_20                   ((uint32_t)0x00100000)               /*!< ADC LT2 bit 20 */
3941 #define ADC_LTR2_LT2_21                   ((uint32_t)0x00200000)               /*!< ADC LT2 bit 21 */
3942 #define ADC_LTR2_LT2_22                   ((uint32_t)0x00400000)               /*!< ADC LT2 bit 22 */
3943 #define ADC_LTR2_LT2_23                   ((uint32_t)0x00800000)               /*!< ADC LT2 bit 23 */
3944 #define ADC_LTR2_LT2_24                   ((uint32_t)0x01000000)               /*!< ADC LT2 bit 24 */
3945 #define ADC_LTR2_LT2_25                   ((uint32_t)0x02000000)               /*!< ADC LT2 bit 25 */
3946 
3947 /********************  Bit definition for ADC_HTR2 register  ********************/
3948 #define ADC_HTR2_HT2         ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 higher threshold */
3949 #define ADC_HTR2_HT2_0                    ((uint32_t)0x00000001)               /*!< ADC HT2 bit 0 */
3950 #define ADC_HTR2_HT2_1                    ((uint32_t)0x00000002)               /*!< ADC HT2 bit 1 */
3951 #define ADC_HTR2_HT2_2                    ((uint32_t)0x00000004)               /*!< ADC HT2 bit 2 */
3952 #define ADC_HTR2_HT2_3                    ((uint32_t)0x00000008)               /*!< ADC HT2 bit 3 */
3953 #define ADC_HTR2_HT2_4                    ((uint32_t)0x00000010)               /*!< ADC HT2 bit 4 */
3954 #define ADC_HTR2_HT2_5                    ((uint32_t)0x00000020)               /*!< ADC HT2 bit 5 */
3955 #define ADC_HTR2_HT2_6                    ((uint32_t)0x00000040)               /*!< ADC HT2 bit 6 */
3956 #define ADC_HTR2_HT2_7                    ((uint32_t)0x00000080)               /*!< ADC HT2 bit 7 */
3957 #define ADC_HTR2_HT2_8                    ((uint32_t)0x00000100)               /*!< ADC HT2 bit 8 */
3958 #define ADC_HTR2_HT2_9                    ((uint32_t)0x00000200)               /*!< ADC HT2 bit 9 */
3959 #define ADC_HTR2_HT2_10                   ((uint32_t)0x00000400)               /*!< ADC HT2 bit 10 */
3960 #define ADC_HTR2_HT2_11                   ((uint32_t)0x00000800)               /*!< ADC HT2 bit 11 */
3961 #define ADC_HTR2_HT2_12                   ((uint32_t)0x00001000)               /*!< ADC HT2 bit 12 */
3962 #define ADC_HTR2_HT2_13                   ((uint32_t)0x00002000)               /*!< ADC HT2 bit 13 */
3963 #define ADC_HTR2_HT2_14                   ((uint32_t)0x00004000)               /*!< ADC HT2 bit 14 */
3964 #define ADC_HTR2_HT2_15                   ((uint32_t)0x00008000)               /*!< ADC HT2 bit 15 */
3965 #define ADC_HTR2_HT2_16                   ((uint32_t)0x00010000)               /*!< ADC HT2 bit 16 */
3966 #define ADC_HTR2_HT2_17                   ((uint32_t)0x00020000)               /*!< ADC HT2 bit 17 */
3967 #define ADC_HTR2_HT2_18                   ((uint32_t)0x00040000)               /*!< ADC HT2 bit 18 */
3968 #define ADC_HTR2_HT2_19                   ((uint32_t)0x00080000)               /*!< ADC HT2 bit 19 */
3969 #define ADC_HTR2_HT2_20                   ((uint32_t)0x00100000)               /*!< ADC HT2 bit 20 */
3970 #define ADC_HTR2_HT2_21                   ((uint32_t)0x00200000)               /*!< ADC HT2 bit 21 */
3971 #define ADC_HTR2_HT2_22                   ((uint32_t)0x00400000)               /*!< ADC HT2 bit 22 */
3972 #define ADC_HTR2_HT2_23                   ((uint32_t)0x00800000)               /*!< ADC HT2 bit 23 */
3973 #define ADC_HTR2_HT2_24                   ((uint32_t)0x01000000)               /*!< ADC HT2 bit 24 */
3974 #define ADC_HTR2_HT2_25      ((uint32_t)0x020000000) /*!< ADC HT2 bit 25 */
3975 
3976 /********************  Bit definition for ADC_LTR3 register  ********************/
3977 #define ADC_LTR3_LT3         ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 lower threshold */
3978 #define ADC_LTR3_LT3_0                    ((uint32_t)0x00000001)               /*!< ADC LT3 bit 0 */
3979 #define ADC_LTR3_LT3_1                    ((uint32_t)0x00000002)               /*!< ADC LT3 bit 1 */
3980 #define ADC_LTR3_LT3_2                    ((uint32_t)0x00000004)               /*!< ADC LT3 bit 2 */
3981 #define ADC_LTR3_LT3_3                    ((uint32_t)0x00000008)               /*!< ADC LT3 bit 3 */
3982 #define ADC_LTR3_LT3_4                    ((uint32_t)0x00000010)               /*!< ADC LT3 bit 4 */
3983 #define ADC_LTR3_LT3_5                    ((uint32_t)0x00000020)               /*!< ADC LT3 bit 5 */
3984 #define ADC_LTR3_LT3_6                    ((uint32_t)0x00000040)               /*!< ADC LT3 bit 6 */
3985 #define ADC_LTR3_LT3_7                    ((uint32_t)0x00000080)               /*!< ADC LT3 bit 7 */
3986 #define ADC_LTR3_LT3_8                    ((uint32_t)0x00000100)               /*!< ADC LT3 bit 8 */
3987 #define ADC_LTR3_LT3_9                    ((uint32_t)0x00000200)               /*!< ADC LT3 bit 9 */
3988 #define ADC_LTR3_LT3_10                   ((uint32_t)0x00000400)               /*!< ADC LT3 bit 10 */
3989 #define ADC_LTR3_LT3_11                   ((uint32_t)0x00000800)               /*!< ADC LT3 bit 11 */
3990 #define ADC_LTR3_LT3_12                   ((uint32_t)0x00001000)               /*!< ADC LT3 bit 12 */
3991 #define ADC_LTR3_LT3_13                   ((uint32_t)0x00002000)               /*!< ADC LT3 bit 13 */
3992 #define ADC_LTR3_LT3_14                   ((uint32_t)0x00004000)               /*!< ADC LT3 bit 14 */
3993 #define ADC_LTR3_LT3_15                   ((uint32_t)0x00008000)               /*!< ADC LT3 bit 15 */
3994 #define ADC_LTR3_LT3_16                   ((uint32_t)0x00010000)               /*!< ADC LT3 bit 16 */
3995 #define ADC_LTR3_LT3_17                   ((uint32_t)0x00020000)               /*!< ADC LT3 bit 17 */
3996 #define ADC_LTR3_LT3_18                   ((uint32_t)0x00040000)               /*!< ADC LT3 bit 18 */
3997 #define ADC_LTR3_LT3_19                   ((uint32_t)0x00080000)               /*!< ADC LT3 bit 19 */
3998 #define ADC_LTR3_LT3_20                   ((uint32_t)0x00100000)               /*!< ADC LT3 bit 20 */
3999 #define ADC_LTR3_LT3_21                   ((uint32_t)0x00200000)               /*!< ADC LT3 bit 21 */
4000 #define ADC_LTR3_LT3_22                   ((uint32_t)0x00400000)               /*!< ADC LT3 bit 22 */
4001 #define ADC_LTR3_LT3_23                   ((uint32_t)0x00800000)               /*!< ADC LT3 bit 23 */
4002 #define ADC_LTR3_LT3_24                   ((uint32_t)0x01000000)               /*!< ADC LT3 bit 24*/
4003 #define ADC_LTR3_LT3_25                   ((uint32_t)0x02000000)               /*!< ADC LT3 bit 25 */
4004 
4005 /********************  Bit definition for ADC_HTR3 register  ********************/
4006 #define ADC_HTR3_HT3         ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 higher threshold */
4007 #define ADC_HTR3_HT3_0                    ((uint32_t)0x00000001)               /*!< ADC HT3 bit 0 */
4008 #define ADC_HTR3_HT3_1                    ((uint32_t)0x00000002)               /*!< ADC HT3 bit 1 */
4009 #define ADC_HTR3_HT3_2                    ((uint32_t)0x00000004)               /*!< ADC HT3 bit 2 */
4010 #define ADC_HTR3_HT3_3                    ((uint32_t)0x00000008)               /*!< ADC HT3 bit 3 */
4011 #define ADC_HTR3_HT3_4                    ((uint32_t)0x00000010)               /*!< ADC HT3 bit 4 */
4012 #define ADC_HTR3_HT3_5                    ((uint32_t)0x00000020)               /*!< ADC HT3 bit 5 */
4013 #define ADC_HTR3_HT3_6                    ((uint32_t)0x00000040)               /*!< ADC HT3 bit 6 */
4014 #define ADC_HTR3_HT3_7                    ((uint32_t)0x00000080)               /*!< ADC HT3 bit 7 */
4015 #define ADC_HTR3_HT3_8                    ((uint32_t)0x00000100)               /*!< ADC HT3 bit 8 */
4016 #define ADC_HTR3_HT3_9                    ((uint32_t)0x00000200)               /*!< ADC HT3 bit 9 */
4017 #define ADC_HTR3_HT3_10                   ((uint32_t)0x00000400)               /*!< ADC HT3 bit 10 */
4018 #define ADC_HTR3_HT3_11                   ((uint32_t)0x00000800)               /*!< ADC HT3 bit 11 */
4019 #define ADC_HTR3_HT3_12                   ((uint32_t)0x00001000)               /*!< ADC HT3 bit 12 */
4020 #define ADC_HTR3_HT3_13                   ((uint32_t)0x00002000)               /*!< ADC HT3 bit 13 */
4021 #define ADC_HTR3_HT3_14                   ((uint32_t)0x00004000)               /*!< ADC HT3 bit 14 */
4022 #define ADC_HTR3_HT3_15                   ((uint32_t)0x00008000)               /*!< ADC HT3 bit 15 */
4023 #define ADC_HTR3_HT3_16                   ((uint32_t)0x00010000)               /*!< ADC HT3 bit 16 */
4024 #define ADC_HTR3_HT3_17                   ((uint32_t)0x00020000)               /*!< ADC HT3 bit 17 */
4025 #define ADC_HTR3_HT3_18                   ((uint32_t)0x00040000)               /*!< ADC HT3 bit 18 */
4026 #define ADC_HTR3_HT3_19                   ((uint32_t)0x00080000)               /*!< ADC HT3 bit 19 */
4027 #define ADC_HTR3_HT3_20                   ((uint32_t)0x00100000)               /*!< ADC HT3 bit 20 */
4028 #define ADC_HTR3_HT3_21                   ((uint32_t)0x00200000)               /*!< ADC HT3 bit 21 */
4029 #define ADC_HTR3_HT3_22                   ((uint32_t)0x00400000)               /*!< ADC HT3 bit 22 */
4030 #define ADC_HTR3_HT3_23                   ((uint32_t)0x00800000)               /*!< ADC HT3 bit 23 */
4031 #define ADC_HTR3_HT3_24                   ((uint32_t)0x01000000)               /*!< ADC HT3 bit 24 */
4032 #define ADC_HTR3_HT3_25                   ((uint32_t)0x02000000)               /*!< ADC HT3 bit 25 */
4033 
4034 /********************  Bit definition for ADC_SQR1 register  ********************/
4035 #define ADC_SQR1_L_Pos                    (0U)
4036 #define ADC_SQR1_L_Msk                    (0xFU << ADC_SQR1_L_Pos)             /*!< 0x0000000F */
4037 #define ADC_SQR1_L                        ADC_SQR1_L_Msk                       /*!< ADC regular channel sequence lenght */
4038 #define ADC_SQR1_L_0                      (0x1U << ADC_SQR1_L_Pos)             /*!< 0x00000001 */
4039 #define ADC_SQR1_L_1                      (0x2U << ADC_SQR1_L_Pos)             /*!< 0x00000002 */
4040 #define ADC_SQR1_L_2                      (0x4U << ADC_SQR1_L_Pos)             /*!< 0x00000004 */
4041 #define ADC_SQR1_L_3                      (0x8U << ADC_SQR1_L_Pos)             /*!< 0x00000008 */
4042 
4043 #define ADC_SQR1_SQ1_Pos                  (6U)
4044 #define ADC_SQR1_SQ1_Msk                  (0x1FU << ADC_SQR1_SQ1_Pos)          /*!< 0x000007C0 */
4045 #define ADC_SQR1_SQ1                      ADC_SQR1_SQ1_Msk                     /*!< ADC 1st conversion in regular sequence */
4046 #define ADC_SQR1_SQ1_0                    (0x01U << ADC_SQR1_SQ1_Pos)          /*!< 0x00000040 */
4047 #define ADC_SQR1_SQ1_1                    (0x02U << ADC_SQR1_SQ1_Pos)          /*!< 0x00000080 */
4048 #define ADC_SQR1_SQ1_2                    (0x04U << ADC_SQR1_SQ1_Pos)          /*!< 0x00000100 */
4049 #define ADC_SQR1_SQ1_3                    (0x08U << ADC_SQR1_SQ1_Pos)          /*!< 0x00000200 */
4050 #define ADC_SQR1_SQ1_4                    (0x10U << ADC_SQR1_SQ1_Pos)          /*!< 0x00000400 */
4051 
4052 #define ADC_SQR1_SQ2_Pos                  (12U)
4053 #define ADC_SQR1_SQ2_Msk                  (0x1FU << ADC_SQR1_SQ2_Pos)          /*!< 0x0001F000 */
4054 #define ADC_SQR1_SQ2                      ADC_SQR1_SQ2_Msk                     /*!< ADC 2nd conversion in regular sequence */
4055 #define ADC_SQR1_SQ2_0                    (0x01U << ADC_SQR1_SQ2_Pos)          /*!< 0x00001000 */
4056 #define ADC_SQR1_SQ2_1                    (0x02U << ADC_SQR1_SQ2_Pos)          /*!< 0x00002000 */
4057 #define ADC_SQR1_SQ2_2                    (0x04U << ADC_SQR1_SQ2_Pos)          /*!< 0x00004000 */
4058 #define ADC_SQR1_SQ2_3                    (0x08U << ADC_SQR1_SQ2_Pos)          /*!< 0x00008000 */
4059 #define ADC_SQR1_SQ2_4                    (0x10U << ADC_SQR1_SQ2_Pos)          /*!< 0x00010000 */
4060 
4061 #define ADC_SQR1_SQ3_Pos                  (18U)
4062 #define ADC_SQR1_SQ3_Msk                  (0x1FU << ADC_SQR1_SQ3_Pos)          /*!< 0x007C0000 */
4063 #define ADC_SQR1_SQ3                      ADC_SQR1_SQ3_Msk                     /*!< ADC 3rd conversion in regular sequence */
4064 #define ADC_SQR1_SQ3_0                    (0x01U << ADC_SQR1_SQ3_Pos)          /*!< 0x00040000 */
4065 #define ADC_SQR1_SQ3_1                    (0x02U << ADC_SQR1_SQ3_Pos)          /*!< 0x00080000 */
4066 #define ADC_SQR1_SQ3_2                    (0x04U << ADC_SQR1_SQ3_Pos)          /*!< 0x00100000 */
4067 #define ADC_SQR1_SQ3_3                    (0x08U << ADC_SQR1_SQ3_Pos)          /*!< 0x00200000 */
4068 #define ADC_SQR1_SQ3_4                    (0x10U << ADC_SQR1_SQ3_Pos)          /*!< 0x00400000 */
4069 
4070 #define ADC_SQR1_SQ4_Pos                  (24U)
4071 #define ADC_SQR1_SQ4_Msk                  (0x1FU << ADC_SQR1_SQ4_Pos)          /*!< 0x1F000000 */
4072 #define ADC_SQR1_SQ4                      ADC_SQR1_SQ4_Msk                     /*!< ADC 4th conversion in regular sequence */
4073 #define ADC_SQR1_SQ4_0                    (0x01U << ADC_SQR1_SQ4_Pos)          /*!< 0x01000000 */
4074 #define ADC_SQR1_SQ4_1                    (0x02U << ADC_SQR1_SQ4_Pos)          /*!< 0x02000000 */
4075 #define ADC_SQR1_SQ4_2                    (0x04U << ADC_SQR1_SQ4_Pos)          /*!< 0x04000000 */
4076 #define ADC_SQR1_SQ4_3                    (0x08U << ADC_SQR1_SQ4_Pos)          /*!< 0x08000000 */
4077 #define ADC_SQR1_SQ4_4                    (0x10U << ADC_SQR1_SQ4_Pos)          /*!< 0x10000000 */
4078 
4079 /********************  Bit definition for ADC_SQR2 register  ********************/
4080 #define ADC_SQR2_SQ5_Pos                  (0U)
4081 #define ADC_SQR2_SQ5_Msk                  (0x1FU << ADC_SQR2_SQ5_Pos)          /*!< 0x0000001F */
4082 #define ADC_SQR2_SQ5                      ADC_SQR2_SQ5_Msk                     /*!< ADC 5th conversion in regular sequence */
4083 #define ADC_SQR2_SQ5_0                    (0x01U << ADC_SQR2_SQ5_Pos)          /*!< 0x00000001 */
4084 #define ADC_SQR2_SQ5_1                    (0x02U << ADC_SQR2_SQ5_Pos)          /*!< 0x00000002 */
4085 #define ADC_SQR2_SQ5_2                    (0x04U << ADC_SQR2_SQ5_Pos)          /*!< 0x00000004 */
4086 #define ADC_SQR2_SQ5_3                    (0x08U << ADC_SQR2_SQ5_Pos)          /*!< 0x00000008 */
4087 #define ADC_SQR2_SQ5_4                    (0x10U << ADC_SQR2_SQ5_Pos)          /*!< 0x00000010 */
4088 
4089 #define ADC_SQR2_SQ6_Pos                  (6U)
4090 #define ADC_SQR2_SQ6_Msk                  (0x1FU << ADC_SQR2_SQ6_Pos)          /*!< 0x000007C0 */
4091 #define ADC_SQR2_SQ6                      ADC_SQR2_SQ6_Msk                     /*!< ADC 6th conversion in regular sequence */
4092 #define ADC_SQR2_SQ6_0                    (0x01U << ADC_SQR2_SQ6_Pos)          /*!< 0x00000040 */
4093 #define ADC_SQR2_SQ6_1                    (0x02U << ADC_SQR2_SQ6_Pos)          /*!< 0x00000080 */
4094 #define ADC_SQR2_SQ6_2                    (0x04U << ADC_SQR2_SQ6_Pos)          /*!< 0x00000100 */
4095 #define ADC_SQR2_SQ6_3                    (0x08U << ADC_SQR2_SQ6_Pos)          /*!< 0x00000200 */
4096 #define ADC_SQR2_SQ6_4                    (0x10U << ADC_SQR2_SQ6_Pos)          /*!< 0x00000400 */
4097 
4098 #define ADC_SQR2_SQ7_Pos                  (12U)
4099 #define ADC_SQR2_SQ7_Msk                  (0x1FU << ADC_SQR2_SQ7_Pos)          /*!< 0x0001F000 */
4100 #define ADC_SQR2_SQ7                      ADC_SQR2_SQ7_Msk                     /*!< ADC 7th conversion in regular sequence */
4101 #define ADC_SQR2_SQ7_0                    (0x01U << ADC_SQR2_SQ7_Pos)          /*!< 0x00001000 */
4102 #define ADC_SQR2_SQ7_1                    (0x02U << ADC_SQR2_SQ7_Pos)          /*!< 0x00002000 */
4103 #define ADC_SQR2_SQ7_2                    (0x04U << ADC_SQR2_SQ7_Pos)          /*!< 0x00004000 */
4104 #define ADC_SQR2_SQ7_3                    (0x08U << ADC_SQR2_SQ7_Pos)          /*!< 0x00008000 */
4105 #define ADC_SQR2_SQ7_4                    (0x10U << ADC_SQR2_SQ7_Pos)          /*!< 0x00010000 */
4106 
4107 #define ADC_SQR2_SQ8_Pos                  (18U)
4108 #define ADC_SQR2_SQ8_Msk                  (0x1FU << ADC_SQR2_SQ8_Pos)          /*!< 0x007C0000 */
4109 #define ADC_SQR2_SQ8                      ADC_SQR2_SQ8_Msk                     /*!< ADC 8th conversion in regular sequence */
4110 #define ADC_SQR2_SQ8_0                    (0x01U << ADC_SQR2_SQ8_Pos)          /*!< 0x00040000 */
4111 #define ADC_SQR2_SQ8_1                    (0x02U << ADC_SQR2_SQ8_Pos)          /*!< 0x00080000 */
4112 #define ADC_SQR2_SQ8_2                    (0x04U << ADC_SQR2_SQ8_Pos)          /*!< 0x00100000 */
4113 #define ADC_SQR2_SQ8_3                    (0x08U << ADC_SQR2_SQ8_Pos)          /*!< 0x00200000 */
4114 #define ADC_SQR2_SQ8_4                    (0x10U << ADC_SQR2_SQ8_Pos)          /*!< 0x00400000 */
4115 
4116 #define ADC_SQR2_SQ9_Pos                  (24U)
4117 #define ADC_SQR2_SQ9_Msk                  (0x1FU << ADC_SQR2_SQ9_Pos)          /*!< 0x1F000000 */
4118 #define ADC_SQR2_SQ9                      ADC_SQR2_SQ9_Msk                     /*!< ADC 9th conversion in regular sequence */
4119 #define ADC_SQR2_SQ9_0                    (0x01U << ADC_SQR2_SQ9_Pos)          /*!< 0x01000000 */
4120 #define ADC_SQR2_SQ9_1                    (0x02U << ADC_SQR2_SQ9_Pos)          /*!< 0x02000000 */
4121 #define ADC_SQR2_SQ9_2                    (0x04U << ADC_SQR2_SQ9_Pos)          /*!< 0x04000000 */
4122 #define ADC_SQR2_SQ9_3                    (0x08U << ADC_SQR2_SQ9_Pos)          /*!< 0x08000000 */
4123 #define ADC_SQR2_SQ9_4                    (0x10U << ADC_SQR2_SQ9_Pos)          /*!< 0x10000000 */
4124 
4125 /********************  Bit definition for ADC_SQR3 register  ********************/
4126 #define ADC_SQR3_SQ10_Pos                 (0U)
4127 #define ADC_SQR3_SQ10_Msk                 (0x1FU << ADC_SQR3_SQ10_Pos)         /*!< 0x0000001F */
4128 #define ADC_SQR3_SQ10                     ADC_SQR3_SQ10_Msk                    /*!< ADC 10th conversion in regular sequence */
4129 #define ADC_SQR3_SQ10_0                   (0x01U << ADC_SQR3_SQ10_Pos)         /*!< 0x00000001 */
4130 #define ADC_SQR3_SQ10_1                   (0x02U << ADC_SQR3_SQ10_Pos)         /*!< 0x00000002 */
4131 #define ADC_SQR3_SQ10_2                   (0x04U << ADC_SQR3_SQ10_Pos)         /*!< 0x00000004 */
4132 #define ADC_SQR3_SQ10_3                   (0x08U << ADC_SQR3_SQ10_Pos)         /*!< 0x00000008 */
4133 #define ADC_SQR3_SQ10_4                   (0x10U << ADC_SQR3_SQ10_Pos)         /*!< 0x00000010 */
4134 
4135 #define ADC_SQR3_SQ11_Pos                 (6U)
4136 #define ADC_SQR3_SQ11_Msk                 (0x1FU << ADC_SQR3_SQ11_Pos)         /*!< 0x000007C0 */
4137 #define ADC_SQR3_SQ11                     ADC_SQR3_SQ11_Msk                    /*!< ADC 11th conversion in regular sequence */
4138 #define ADC_SQR3_SQ11_0                   (0x01U << ADC_SQR3_SQ11_Pos)         /*!< 0x00000040 */
4139 #define ADC_SQR3_SQ11_1                   (0x02U << ADC_SQR3_SQ11_Pos)         /*!< 0x00000080 */
4140 #define ADC_SQR3_SQ11_2                   (0x04U << ADC_SQR3_SQ11_Pos)         /*!< 0x00000100 */
4141 #define ADC_SQR3_SQ11_3                   (0x08U << ADC_SQR3_SQ11_Pos)         /*!< 0x00000200 */
4142 #define ADC_SQR3_SQ11_4                   (0x10U << ADC_SQR3_SQ11_Pos)         /*!< 0x00000400 */
4143 
4144 #define ADC_SQR3_SQ12_Pos                 (12U)
4145 #define ADC_SQR3_SQ12_Msk                 (0x1FU << ADC_SQR3_SQ12_Pos)         /*!< 0x0001F000 */
4146 #define ADC_SQR3_SQ12                     ADC_SQR3_SQ12_Msk                    /*!< ADC 12th conversion in regular sequence */
4147 #define ADC_SQR3_SQ12_0                   (0x01U << ADC_SQR3_SQ12_Pos)         /*!< 0x00001000 */
4148 #define ADC_SQR3_SQ12_1                   (0x02U << ADC_SQR3_SQ12_Pos)         /*!< 0x00002000 */
4149 #define ADC_SQR3_SQ12_2                   (0x04U << ADC_SQR3_SQ12_Pos)         /*!< 0x00004000 */
4150 #define ADC_SQR3_SQ12_3                   (0x08U << ADC_SQR3_SQ12_Pos)         /*!< 0x00008000 */
4151 #define ADC_SQR3_SQ12_4                   (0x10U << ADC_SQR3_SQ12_Pos)         /*!< 0x00010000 */
4152 
4153 #define ADC_SQR3_SQ13_Pos                 (18U)
4154 #define ADC_SQR3_SQ13_Msk                 (0x1FU << ADC_SQR3_SQ13_Pos)         /*!< 0x007C0000 */
4155 #define ADC_SQR3_SQ13                     ADC_SQR3_SQ13_Msk                    /*!< ADC 13th conversion in regular sequence */
4156 #define ADC_SQR3_SQ13_0                   (0x01U << ADC_SQR3_SQ13_Pos)         /*!< 0x00040000 */
4157 #define ADC_SQR3_SQ13_1                   (0x02U << ADC_SQR3_SQ13_Pos)         /*!< 0x00080000 */
4158 #define ADC_SQR3_SQ13_2                   (0x04U << ADC_SQR3_SQ13_Pos)         /*!< 0x00100000 */
4159 #define ADC_SQR3_SQ13_3                   (0x08U << ADC_SQR3_SQ13_Pos)         /*!< 0x00200000 */
4160 #define ADC_SQR3_SQ13_4                   (0x10U << ADC_SQR3_SQ13_Pos)         /*!< 0x00400000 */
4161 
4162 #define ADC_SQR3_SQ14_Pos                 (24U)
4163 #define ADC_SQR3_SQ14_Msk                 (0x1FU << ADC_SQR3_SQ14_Pos)         /*!< 0x1F000000 */
4164 #define ADC_SQR3_SQ14                     ADC_SQR3_SQ14_Msk                    /*!< ADC 14th conversion in regular sequence */
4165 #define ADC_SQR3_SQ14_0                   (0x01U << ADC_SQR3_SQ14_Pos)         /*!< 0x01000000 */
4166 #define ADC_SQR3_SQ14_1                   (0x02U << ADC_SQR3_SQ14_Pos)         /*!< 0x02000000 */
4167 #define ADC_SQR3_SQ14_2                   (0x04U << ADC_SQR3_SQ14_Pos)         /*!< 0x04000000 */
4168 #define ADC_SQR3_SQ14_3                   (0x08U << ADC_SQR3_SQ14_Pos)         /*!< 0x08000000 */
4169 #define ADC_SQR3_SQ14_4                   (0x10U << ADC_SQR3_SQ14_Pos)         /*!< 0x10000000 */
4170 
4171 /********************  Bit definition for ADC_SQR4 register  ********************/
4172 #define ADC_SQR4_SQ15_Pos                 (0U)
4173 #define ADC_SQR4_SQ15_Msk                 (0x1FU << ADC_SQR4_SQ15_Pos)         /*!< 0x0000001F */
4174 #define ADC_SQR4_SQ15                     ADC_SQR4_SQ15_Msk                    /*!< ADC 15th conversion in regular sequence */
4175 #define ADC_SQR4_SQ15_0                   (0x01U << ADC_SQR4_SQ15_Pos)         /*!< 0x00000001 */
4176 #define ADC_SQR4_SQ15_1                   (0x02U << ADC_SQR4_SQ15_Pos)         /*!< 0x00000002 */
4177 #define ADC_SQR4_SQ15_2                   (0x04U << ADC_SQR4_SQ15_Pos)         /*!< 0x00000004 */
4178 #define ADC_SQR4_SQ15_3                   (0x08U << ADC_SQR4_SQ15_Pos)         /*!< 0x00000008 */
4179 #define ADC_SQR4_SQ15_4                   (0x10U << ADC_SQR4_SQ15_Pos)         /*!< 0x00000010 */
4180 
4181 #define ADC_SQR4_SQ16_Pos                 (6U)
4182 #define ADC_SQR4_SQ16_Msk                 (0x1FU << ADC_SQR4_SQ16_Pos)         /*!< 0x000007C0 */
4183 #define ADC_SQR4_SQ16                     ADC_SQR4_SQ16_Msk                    /*!< ADC 16th conversion in regular sequence */
4184 #define ADC_SQR4_SQ16_0                   (0x01U << ADC_SQR4_SQ16_Pos)         /*!< 0x00000040 */
4185 #define ADC_SQR4_SQ16_1                   (0x02U << ADC_SQR4_SQ16_Pos)         /*!< 0x00000080 */
4186 #define ADC_SQR4_SQ16_2                   (0x04U << ADC_SQR4_SQ16_Pos)         /*!< 0x00000100 */
4187 #define ADC_SQR4_SQ16_3                   (0x08U << ADC_SQR4_SQ16_Pos)         /*!< 0x00000200 */
4188 #define ADC_SQR4_SQ16_4                   (0x10U << ADC_SQR4_SQ16_Pos)         /*!< 0x00000400 */
4189 /********************  Bit definition for ADC_DR register  ********************/
4190 #define ADC_DR_RDATA_Pos                  (0U)
4191 #define ADC_DR_RDATA_Msk                  (0xFFFFU << ADC_DR_RDATA_Pos)        /*!< 0x0000FFFF */
4192 #define ADC_DR_RDATA                      ADC_DR_RDATA_Msk                     /*!< ADC regular Data converted */
4193 #define ADC_DR_RDATA_0                    (0x0001U << ADC_DR_RDATA_Pos)        /*!< 0x00000001 */
4194 #define ADC_DR_RDATA_1                    (0x0002U << ADC_DR_RDATA_Pos)        /*!< 0x00000002 */
4195 #define ADC_DR_RDATA_2                    (0x0004U << ADC_DR_RDATA_Pos)        /*!< 0x00000004 */
4196 #define ADC_DR_RDATA_3                    (0x0008U << ADC_DR_RDATA_Pos)        /*!< 0x00000008 */
4197 #define ADC_DR_RDATA_4                    (0x0010U << ADC_DR_RDATA_Pos)        /*!< 0x00000010 */
4198 #define ADC_DR_RDATA_5                    (0x0020U << ADC_DR_RDATA_Pos)        /*!< 0x00000020 */
4199 #define ADC_DR_RDATA_6                    (0x0040U << ADC_DR_RDATA_Pos)        /*!< 0x00000040 */
4200 #define ADC_DR_RDATA_7                    (0x0080U << ADC_DR_RDATA_Pos)        /*!< 0x00000080 */
4201 #define ADC_DR_RDATA_8                    (0x0100U << ADC_DR_RDATA_Pos)        /*!< 0x00000100 */
4202 #define ADC_DR_RDATA_9                    (0x0200U << ADC_DR_RDATA_Pos)        /*!< 0x00000200 */
4203 #define ADC_DR_RDATA_10                   (0x0400U << ADC_DR_RDATA_Pos)        /*!< 0x00000400 */
4204 #define ADC_DR_RDATA_11                   (0x0800U << ADC_DR_RDATA_Pos)        /*!< 0x00000800 */
4205 #define ADC_DR_RDATA_12                   (0x1000U << ADC_DR_RDATA_Pos)        /*!< 0x00001000 */
4206 #define ADC_DR_RDATA_13                   (0x2000U << ADC_DR_RDATA_Pos)        /*!< 0x00002000 */
4207 #define ADC_DR_RDATA_14                   (0x4000U << ADC_DR_RDATA_Pos)        /*!< 0x00004000 */
4208 #define ADC_DR_RDATA_15                   (0x8000U << ADC_DR_RDATA_Pos)        /*!< 0x00008000 */
4209 #define ADC_DR_RDATA_16                   (0x10000U << ADC_DR_RDATA_Pos)       /*!< 0x00010000 */
4210 #define ADC_DR_RDATA_17                   (0x20000U << ADC_DR_RDATA_Pos)       /*!< 0x00020000 */
4211 #define ADC_DR_RDATA_18                   (0x40000U << ADC_DR_RDATA_Pos)       /*!< 0x00040000 */
4212 #define ADC_DR_RDATA_19                   (0x80000U << ADC_DR_RDATA_Pos)       /*!< 0x00080000 */
4213 #define ADC_DR_RDATA_20                   (0x100000U << ADC_DR_RDATA_Pos)      /*!< 0x00100000 */
4214 #define ADC_DR_RDATA_21                   (0x200000U << ADC_DR_RDATA_Pos)      /*!< 0x00200000 */
4215 #define ADC_DR_RDATA_22                   (0x400000U << ADC_DR_RDATA_Pos)      /*!< 0x00400000 */
4216 #define ADC_DR_RDATA_23                   (0x800000U << ADC_DR_RDATA_Pos)      /*!< 0x00800000 */
4217 #define ADC_DR_RDATA_24                   (0x1000000U << ADC_DR_RDATA_Pos)     /*!< 0x01000000 */
4218 #define ADC_DR_RDATA_25                   (0x2000000U << ADC_DR_RDATA_Pos)     /*!< 0x02000000 */
4219 #define ADC_DR_RDATA_26                   (0x4000000U << ADC_DR_RDATA_Pos)     /*!< 0x04000000 */
4220 #define ADC_DR_RDATA_27                   (0x8000000U << ADC_DR_RDATA_Pos)     /*!< 0x08000000 */
4221 #define ADC_DR_RDATA_28                   (0x10000000U << ADC_DR_RDATA_Pos)    /*!< 0x10000000 */
4222 #define ADC_DR_RDATA_29                   (0x20000000U << ADC_DR_RDATA_Pos)    /*!< 0x20000000 */
4223 #define ADC_DR_RDATA_30                   (0x40000000U << ADC_DR_RDATA_Pos)    /*!< 0x40000000 */
4224 #define ADC_DR_RDATA_31                   (0x80000000U << ADC_DR_RDATA_Pos)    /*!< 0x80000000 */
4225 
4226 /********************  Bit definition for ADC_JSQR register  ********************/
4227 #define ADC_JSQR_JL_Pos                   (0U)
4228 #define ADC_JSQR_JL_Msk                   (0x3U << ADC_JSQR_JL_Pos)            /*!< 0x00000003 */
4229 #define ADC_JSQR_JL                       ADC_JSQR_JL_Msk                      /*!< ADC injected channel sequence length */
4230 #define ADC_JSQR_JL_0                     (0x1U << ADC_JSQR_JL_Pos)            /*!< 0x00000001 */
4231 #define ADC_JSQR_JL_1                     (0x2U << ADC_JSQR_JL_Pos)            /*!< 0x00000002 */
4232 
4233 #define ADC_JSQR_JEXTSEL_Pos              (2U)
4234 #define ADC_JSQR_JEXTSEL_Msk              (0x1FU << ADC_JSQR_JEXTSEL_Pos)      /*!< 0x0000007C */
4235 #define ADC_JSQR_JEXTSEL                  ADC_JSQR_JEXTSEL_Msk                 /*!< ADC external trigger selection for injected group */
4236 #define ADC_JSQR_JEXTSEL_0                (0x01U << ADC_JSQR_JEXTSEL_Pos)      /*!< 0x00000004 */
4237 #define ADC_JSQR_JEXTSEL_1                (0x02U << ADC_JSQR_JEXTSEL_Pos)      /*!< 0x00000008 */
4238 #define ADC_JSQR_JEXTSEL_2                (0x04U << ADC_JSQR_JEXTSEL_Pos)      /*!< 0x00000010 */
4239 #define ADC_JSQR_JEXTSEL_3                (0x08U << ADC_JSQR_JEXTSEL_Pos)      /*!< 0x00000020 */
4240 #define ADC_JSQR_JEXTSEL_4                (0x10U << ADC_JSQR_JEXTSEL_Pos)      /*!< 0x00000040 */
4241 
4242 #define ADC_JSQR_JEXTEN_Pos               (7U)
4243 #define ADC_JSQR_JEXTEN_Msk               (0x3U << ADC_JSQR_JEXTEN_Pos)        /*!< 0x00000180 */
4244 #define ADC_JSQR_JEXTEN                   ADC_JSQR_JEXTEN_Msk                  /*!< ADC external trigger enable and polarity selection for injected channels */
4245 #define ADC_JSQR_JEXTEN_0                 (0x1U << ADC_JSQR_JEXTEN_Pos)        /*!< 0x00000080 */
4246 #define ADC_JSQR_JEXTEN_1                 (0x2U << ADC_JSQR_JEXTEN_Pos)        /*!< 0x00000100 */
4247 
4248 #define ADC_JSQR_JSQ1_Pos                 (9U)
4249 #define ADC_JSQR_JSQ1_Msk                 (0x1FU << ADC_JSQR_JSQ1_Pos)         /*!< 0x00003E00 */
4250 #define ADC_JSQR_JSQ1                     ADC_JSQR_JSQ1_Msk                    /*!< ADC 1st conversion in injected sequence */
4251 #define ADC_JSQR_JSQ1_0                   (0x01U << ADC_JSQR_JSQ1_Pos)         /*!< 0x00000200 */
4252 #define ADC_JSQR_JSQ1_1                   (0x02U << ADC_JSQR_JSQ1_Pos)         /*!< 0x00000400 */
4253 #define ADC_JSQR_JSQ1_2                   (0x04U << ADC_JSQR_JSQ1_Pos)         /*!< 0x00000800 */
4254 #define ADC_JSQR_JSQ1_3                   (0x08U << ADC_JSQR_JSQ1_Pos)         /*!< 0x00001000 */
4255 #define ADC_JSQR_JSQ1_4                   (0x10U << ADC_JSQR_JSQ1_Pos)         /*!< 0x00002000 */
4256 
4257 #define ADC_JSQR_JSQ2_Pos                 (15U)
4258 #define ADC_JSQR_JSQ2_Msk                 (0x1FU << ADC_JSQR_JSQ2_Pos)         /*!< 0x000F8000 */
4259 #define ADC_JSQR_JSQ2                     ADC_JSQR_JSQ2_Msk                    /*!< ADC 2nd conversion in injected sequence */
4260 #define ADC_JSQR_JSQ2_0                   (0x01U << ADC_JSQR_JSQ2_Pos)         /*!< 0x00008000 */
4261 #define ADC_JSQR_JSQ2_1                   (0x02U << ADC_JSQR_JSQ2_Pos)         /*!< 0x00010000 */
4262 #define ADC_JSQR_JSQ2_2                   (0x04U << ADC_JSQR_JSQ2_Pos)         /*!< 0x00020000 */
4263 #define ADC_JSQR_JSQ2_3                   (0x08U << ADC_JSQR_JSQ2_Pos)         /*!< 0x00040000 */
4264 #define ADC_JSQR_JSQ2_4                   (0x10U << ADC_JSQR_JSQ2_Pos)         /*!< 0x00080000 */
4265 
4266 #define ADC_JSQR_JSQ3_Pos                 (21U)
4267 #define ADC_JSQR_JSQ3_Msk                 (0x1FU << ADC_JSQR_JSQ3_Pos)         /*!< 0x03E00000 */
4268 #define ADC_JSQR_JSQ3                     ADC_JSQR_JSQ3_Msk                    /*!< ADC 3rd conversion in injected sequence */
4269 #define ADC_JSQR_JSQ3_0                   (0x01U << ADC_JSQR_JSQ3_Pos)         /*!< 0x00200000 */
4270 #define ADC_JSQR_JSQ3_1                   (0x02U << ADC_JSQR_JSQ3_Pos)         /*!< 0x00400000 */
4271 #define ADC_JSQR_JSQ3_2                   (0x04U << ADC_JSQR_JSQ3_Pos)         /*!< 0x00800000 */
4272 #define ADC_JSQR_JSQ3_3                   (0x08U << ADC_JSQR_JSQ3_Pos)         /*!< 0x01000000 */
4273 #define ADC_JSQR_JSQ3_4                   (0x10U << ADC_JSQR_JSQ3_Pos)         /*!< 0x02000000 */
4274 
4275 #define ADC_JSQR_JSQ4_Pos                 (27U)
4276 #define ADC_JSQR_JSQ4_Msk                 (0x1FU << ADC_JSQR_JSQ4_Pos)         /*!< 0xF8000000 */
4277 #define ADC_JSQR_JSQ4                     ADC_JSQR_JSQ4_Msk                    /*!< ADC 4th conversion in injected sequence */
4278 #define ADC_JSQR_JSQ4_0                   (0x01U << ADC_JSQR_JSQ4_Pos)         /*!< 0x08000000 */
4279 #define ADC_JSQR_JSQ4_1                   (0x02U << ADC_JSQR_JSQ4_Pos)         /*!< 0x10000000 */
4280 #define ADC_JSQR_JSQ4_2                   (0x04U << ADC_JSQR_JSQ4_Pos)         /*!< 0x20000000 */
4281 #define ADC_JSQR_JSQ4_3                   (0x08U << ADC_JSQR_JSQ4_Pos)         /*!< 0x40000000 */
4282 #define ADC_JSQR_JSQ4_4                   (0x10U << ADC_JSQR_JSQ4_Pos)         /*!< 0x80000000 */
4283 
4284 /********************  Bit definition for ADC_OFR1 register  ********************/
4285 #define ADC_OFR1_OFFSET1_Pos              (0U)
4286 #define ADC_OFR1_OFFSET1_Msk              (0x3FFFFFFU << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */
4287 #define ADC_OFR1_OFFSET1                  ADC_OFR1_OFFSET1_Msk                 /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */
4288 #define ADC_OFR1_OFFSET1_0                (0x0000001U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
4289 #define ADC_OFR1_OFFSET1_1                (0x0000002U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
4290 #define ADC_OFR1_OFFSET1_2                (0x0000004U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
4291 #define ADC_OFR1_OFFSET1_3                (0x0000008U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
4292 #define ADC_OFR1_OFFSET1_4                (0x0000010U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
4293 #define ADC_OFR1_OFFSET1_5                (0x0000020U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
4294 #define ADC_OFR1_OFFSET1_6                (0x0000040U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
4295 #define ADC_OFR1_OFFSET1_7                (0x0000080U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
4296 #define ADC_OFR1_OFFSET1_8                (0x0000100U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
4297 #define ADC_OFR1_OFFSET1_9                (0x0000200U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
4298 #define ADC_OFR1_OFFSET1_10               (0x0000400U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
4299 #define ADC_OFR1_OFFSET1_11               (0x0000800U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
4300 #define ADC_OFR1_OFFSET1_12               (0x0001000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */
4301 #define ADC_OFR1_OFFSET1_13               (0x0002000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */
4302 #define ADC_OFR1_OFFSET1_14               (0x0004000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */
4303 #define ADC_OFR1_OFFSET1_15               (0x0008000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */
4304 #define ADC_OFR1_OFFSET1_16               (0x0010000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */
4305 #define ADC_OFR1_OFFSET1_17               (0x0020000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */
4306 #define ADC_OFR1_OFFSET1_18               (0x0040000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */
4307 #define ADC_OFR1_OFFSET1_19               (0x0080000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */
4308 #define ADC_OFR1_OFFSET1_20               (0x0100000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */
4309 #define ADC_OFR1_OFFSET1_21               (0x0200000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */
4310 #define ADC_OFR1_OFFSET1_22               (0x0400000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */
4311 #define ADC_OFR1_OFFSET1_23               (0x0800000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */
4312 #define ADC_OFR1_OFFSET1_24               (0x1000000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */
4313 #define ADC_OFR1_OFFSET1_25               (0x2000000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */
4314 
4315 #define ADC_OFR1_OFFSET1_CH_Pos           (26U)
4316 #define ADC_OFR1_OFFSET1_CH_Msk           (0x1FU << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x7C000000 */
4317 #define ADC_OFR1_OFFSET1_CH               ADC_OFR1_OFFSET1_CH_Msk              /*!< ADC Channel selection for the data offset 1 */
4318 #define ADC_OFR1_OFFSET1_CH_0             (0x01U << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x04000000 */
4319 #define ADC_OFR1_OFFSET1_CH_1             (0x02U << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x08000000 */
4320 #define ADC_OFR1_OFFSET1_CH_2             (0x04U << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x10000000 */
4321 #define ADC_OFR1_OFFSET1_CH_3             (0x08U << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x20000000 */
4322 #define ADC_OFR1_OFFSET1_CH_4             (0x10U << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x40000000 */
4323 
4324 #define ADC_OFR1_SSATE_Pos                (31U)
4325 #define ADC_OFR1_SSATE_Msk                (0x1U << ADC_OFR1_SSATE_Pos)         /*!< 0x80000000 */
4326 #define ADC_OFR1_SSATE                    ADC_OFR1_SSATE_Msk                   /*!< ADC Signed saturation Enable */
4327 
4328 /********************  Bit definition for ADC_OFR2 register  ********************/
4329 #define ADC_OFR2_OFFSET2_Pos              (0U)
4330 #define ADC_OFR2_OFFSET2_Msk              (0x3FFFFFFU << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */
4331 #define ADC_OFR2_OFFSET2                  ADC_OFR2_OFFSET2_Msk                 /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
4332 #define ADC_OFR2_OFFSET2_0                (0x0000001U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
4333 #define ADC_OFR2_OFFSET2_1                (0x0000002U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
4334 #define ADC_OFR2_OFFSET2_2                (0x0000004U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
4335 #define ADC_OFR2_OFFSET2_3                (0x0000008U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
4336 #define ADC_OFR2_OFFSET2_4                (0x0000010U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
4337 #define ADC_OFR2_OFFSET2_5                (0x0000020U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
4338 #define ADC_OFR2_OFFSET2_6                (0x0000040U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
4339 #define ADC_OFR2_OFFSET2_7                (0x0000080U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
4340 #define ADC_OFR2_OFFSET2_8                (0x0000100U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
4341 #define ADC_OFR2_OFFSET2_9                (0x0000200U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
4342 #define ADC_OFR2_OFFSET2_10               (0x0000400U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
4343 #define ADC_OFR2_OFFSET2_11               (0x0000800U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
4344 #define ADC_OFR2_OFFSET2_12               (0x0001000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */
4345 #define ADC_OFR2_OFFSET2_13               (0x0002000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */
4346 #define ADC_OFR2_OFFSET2_14               (0x0004000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */
4347 #define ADC_OFR2_OFFSET2_15               (0x0008000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */
4348 #define ADC_OFR2_OFFSET2_16               (0x0010000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */
4349 #define ADC_OFR2_OFFSET2_17               (0x0020000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */
4350 #define ADC_OFR2_OFFSET2_18               (0x0040000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */
4351 #define ADC_OFR2_OFFSET2_19               (0x0080000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */
4352 #define ADC_OFR2_OFFSET2_20               (0x0100000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */
4353 #define ADC_OFR2_OFFSET2_21               (0x0200000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */
4354 #define ADC_OFR2_OFFSET2_22               (0x0400000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */
4355 #define ADC_OFR2_OFFSET2_23               (0x0800000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */
4356 #define ADC_OFR2_OFFSET2_24               (0x1000000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */
4357 #define ADC_OFR2_OFFSET2_25               (0x2000000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */
4358 
4359 #define ADC_OFR2_OFFSET2_CH_Pos           (26U)
4360 #define ADC_OFR2_OFFSET2_CH_Msk           (0x1FU << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x7C000000 */
4361 #define ADC_OFR2_OFFSET2_CH               ADC_OFR2_OFFSET2_CH_Msk              /*!< ADC Channel selection for the data offset 2 */
4362 #define ADC_OFR2_OFFSET2_CH_0             (0x01U << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x04000000 */
4363 #define ADC_OFR2_OFFSET2_CH_1             (0x02U << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x08000000 */
4364 #define ADC_OFR2_OFFSET2_CH_2             (0x04U << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x10000000 */
4365 #define ADC_OFR2_OFFSET2_CH_3             (0x08U << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x20000000 */
4366 #define ADC_OFR2_OFFSET2_CH_4             (0x10U << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x40000000 */
4367 
4368 #define ADC_OFR2_SSATE_Pos                (31U)
4369 #define ADC_OFR2_SSATE_Msk                (0x1U << ADC_OFR2_SSATE_Pos)         /*!< 0x80000000 */
4370 #define ADC_OFR2_SSATE                    ADC_OFR2_SSATE_Msk                   /*!< ADC Signed saturation Enable */
4371 
4372 /********************  Bit definition for ADC_OFR3 register  ********************/
4373 #define ADC_OFR3_OFFSET3_Pos              (0U)
4374 #define ADC_OFR3_OFFSET3_Msk              (0x3FFFFFFU << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */
4375 #define ADC_OFR3_OFFSET3                  ADC_OFR3_OFFSET3_Msk                 /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
4376 #define ADC_OFR3_OFFSET3_0                (0x0000001U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
4377 #define ADC_OFR3_OFFSET3_1                (0x0000002U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
4378 #define ADC_OFR3_OFFSET3_2                (0x0000004U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
4379 #define ADC_OFR3_OFFSET3_3                (0x0000008U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
4380 #define ADC_OFR3_OFFSET3_4                (0x0000010U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
4381 #define ADC_OFR3_OFFSET3_5                (0x0000020U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
4382 #define ADC_OFR3_OFFSET3_6                (0x0000040U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
4383 #define ADC_OFR3_OFFSET3_7                (0x0000080U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
4384 #define ADC_OFR3_OFFSET3_8                (0x0000100U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
4385 #define ADC_OFR3_OFFSET3_9                (0x0000200U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
4386 #define ADC_OFR3_OFFSET3_10               (0x0000400U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
4387 #define ADC_OFR3_OFFSET3_11               (0x0000800U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
4388 #define ADC_OFR3_OFFSET3_12               (0x0001000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */
4389 #define ADC_OFR3_OFFSET3_13               (0x0002000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */
4390 #define ADC_OFR3_OFFSET3_14               (0x0004000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */
4391 #define ADC_OFR3_OFFSET3_15               (0x0008000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */
4392 #define ADC_OFR3_OFFSET3_16               (0x0010000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */
4393 #define ADC_OFR3_OFFSET3_17               (0x0020000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */
4394 #define ADC_OFR3_OFFSET3_18               (0x0040000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */
4395 #define ADC_OFR3_OFFSET3_19               (0x0080000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */
4396 #define ADC_OFR3_OFFSET3_20               (0x0100000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */
4397 #define ADC_OFR3_OFFSET3_21               (0x0200000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */
4398 #define ADC_OFR3_OFFSET3_22               (0x0400000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */
4399 #define ADC_OFR3_OFFSET3_23               (0x0800000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */
4400 #define ADC_OFR3_OFFSET3_24               (0x1000000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */
4401 #define ADC_OFR3_OFFSET3_25               (0x2000000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */
4402 
4403 #define ADC_OFR3_OFFSET3_CH_Pos           (26U)
4404 #define ADC_OFR3_OFFSET3_CH_Msk           (0x1FU << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x7C000000 */
4405 #define ADC_OFR3_OFFSET3_CH               ADC_OFR3_OFFSET3_CH_Msk              /*!< ADC Channel selection for the data offset 3 */
4406 #define ADC_OFR3_OFFSET3_CH_0             (0x01U << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x04000000 */
4407 #define ADC_OFR3_OFFSET3_CH_1             (0x02U << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x08000000 */
4408 #define ADC_OFR3_OFFSET3_CH_2             (0x04U << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x10000000 */
4409 #define ADC_OFR3_OFFSET3_CH_3             (0x08U << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x20000000 */
4410 #define ADC_OFR3_OFFSET3_CH_4             (0x10U << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x40000000 */
4411 
4412 #define ADC_OFR3_SSATE_Pos                (31U)
4413 #define ADC_OFR3_SSATE_Msk                (0x1U << ADC_OFR3_SSATE_Pos)         /*!< 0x80000000 */
4414 #define ADC_OFR3_SSATE                    ADC_OFR3_SSATE_Msk                   /*!< ADC Signed saturation Enable */
4415 
4416 /********************  Bit definition for ADC_OFR4 register  ********************/
4417 #define ADC_OFR4_OFFSET4_Pos              (0U)
4418 #define ADC_OFR4_OFFSET4_Msk              (0x3FFFFFFU << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */
4419 #define ADC_OFR4_OFFSET4                  ADC_OFR4_OFFSET4_Msk                 /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
4420 #define ADC_OFR4_OFFSET4_0                (0x0000001U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
4421 #define ADC_OFR4_OFFSET4_1                (0x0000002U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
4422 #define ADC_OFR4_OFFSET4_2                (0x0000004U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
4423 #define ADC_OFR4_OFFSET4_3                (0x0000008U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
4424 #define ADC_OFR4_OFFSET4_4                (0x0000010U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
4425 #define ADC_OFR4_OFFSET4_5                (0x0000020U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
4426 #define ADC_OFR4_OFFSET4_6                (0x0000040U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
4427 #define ADC_OFR4_OFFSET4_7                (0x0000080U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
4428 #define ADC_OFR4_OFFSET4_8                (0x0000100U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
4429 #define ADC_OFR4_OFFSET4_9                (0x0000200U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
4430 #define ADC_OFR4_OFFSET4_10               (0x0000400U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
4431 #define ADC_OFR4_OFFSET4_11               (0x0000800U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
4432 #define ADC_OFR4_OFFSET4_12               (0x0001000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */
4433 #define ADC_OFR4_OFFSET4_13               (0x0002000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */
4434 #define ADC_OFR4_OFFSET4_14               (0x0004000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */
4435 #define ADC_OFR4_OFFSET4_15               (0x0008000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */
4436 #define ADC_OFR4_OFFSET4_16               (0x0010000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */
4437 #define ADC_OFR4_OFFSET4_17               (0x0020000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */
4438 #define ADC_OFR4_OFFSET4_18               (0x0040000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */
4439 #define ADC_OFR4_OFFSET4_19               (0x0080000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */
4440 #define ADC_OFR4_OFFSET4_20               (0x0100000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */
4441 #define ADC_OFR4_OFFSET4_21               (0x0200000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */
4442 #define ADC_OFR4_OFFSET4_22               (0x0400000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */
4443 #define ADC_OFR4_OFFSET4_23               (0x0800000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */
4444 #define ADC_OFR4_OFFSET4_24               (0x1000000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */
4445 #define ADC_OFR4_OFFSET4_25               (0x2000000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */
4446 
4447 #define ADC_OFR4_OFFSET4_CH_Pos           (26U)
4448 #define ADC_OFR4_OFFSET4_CH_Msk           (0x1FU << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x7C000000 */
4449 #define ADC_OFR4_OFFSET4_CH               ADC_OFR4_OFFSET4_CH_Msk              /*!< ADC Channel selection for the data offset 4 */
4450 #define ADC_OFR4_OFFSET4_CH_0             (0x01U << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x04000000 */
4451 #define ADC_OFR4_OFFSET4_CH_1             (0x02U << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x08000000 */
4452 #define ADC_OFR4_OFFSET4_CH_2             (0x04U << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x10000000 */
4453 #define ADC_OFR4_OFFSET4_CH_3             (0x08U << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x20000000 */
4454 #define ADC_OFR4_OFFSET4_CH_4             (0x10U << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x40000000 */
4455 
4456 #define ADC_OFR4_SSATE_Pos                (31U)
4457 #define ADC_OFR4_SSATE_Msk                (0x1U << ADC_OFR4_SSATE_Pos)         /*!< 0x80000000 */
4458 #define ADC_OFR4_SSATE                    ADC_OFR4_SSATE_Msk                   /*!< ADC Signed saturation Enable */
4459 
4460 /********************  Bit definition for ADC_JDR1 register  ********************/
4461 #define ADC_JDR1_JDATA_Pos                (0U)
4462 #define ADC_JDR1_JDATA_Msk                (0xFFFFU << ADC_JDR1_JDATA_Pos)      /*!< 0x0000FFFF */
4463 #define ADC_JDR1_JDATA                    ADC_JDR1_JDATA_Msk                   /*!< ADC Injected DATA */
4464 #define ADC_JDR1_JDATA_0                  (0x0001U << ADC_JDR1_JDATA_Pos)      /*!< 0x00000001 */
4465 #define ADC_JDR1_JDATA_1                  (0x0002U << ADC_JDR1_JDATA_Pos)      /*!< 0x00000002 */
4466 #define ADC_JDR1_JDATA_2                  (0x0004U << ADC_JDR1_JDATA_Pos)      /*!< 0x00000004 */
4467 #define ADC_JDR1_JDATA_3                  (0x0008U << ADC_JDR1_JDATA_Pos)      /*!< 0x00000008 */
4468 #define ADC_JDR1_JDATA_4                  (0x0010U << ADC_JDR1_JDATA_Pos)      /*!< 0x00000010 */
4469 #define ADC_JDR1_JDATA_5                  (0x0020U << ADC_JDR1_JDATA_Pos)      /*!< 0x00000020 */
4470 #define ADC_JDR1_JDATA_6                  (0x0040U << ADC_JDR1_JDATA_Pos)      /*!< 0x00000040 */
4471 #define ADC_JDR1_JDATA_7                  (0x0080U << ADC_JDR1_JDATA_Pos)      /*!< 0x00000080 */
4472 #define ADC_JDR1_JDATA_8                  (0x0100U << ADC_JDR1_JDATA_Pos)      /*!< 0x00000100 */
4473 #define ADC_JDR1_JDATA_9                  (0x0200U << ADC_JDR1_JDATA_Pos)      /*!< 0x00000200 */
4474 #define ADC_JDR1_JDATA_10                 (0x0400U << ADC_JDR1_JDATA_Pos)      /*!< 0x00000400 */
4475 #define ADC_JDR1_JDATA_11                 (0x0800U << ADC_JDR1_JDATA_Pos)      /*!< 0x00000800 */
4476 #define ADC_JDR1_JDATA_12                 (0x1000U << ADC_JDR1_JDATA_Pos)      /*!< 0x00001000 */
4477 #define ADC_JDR1_JDATA_13                 (0x2000U << ADC_JDR1_JDATA_Pos)      /*!< 0x00002000 */
4478 #define ADC_JDR1_JDATA_14                 (0x4000U << ADC_JDR1_JDATA_Pos)      /*!< 0x00004000 */
4479 #define ADC_JDR1_JDATA_15                 (0x8000U << ADC_JDR1_JDATA_Pos)      /*!< 0x00008000 */
4480 #define ADC_JDR1_JDATA_16                 (0x10000U << ADC_JDR1_JDATA_Pos)     /*!< 0x00010000 */
4481 #define ADC_JDR1_JDATA_17                 (0x20000U << ADC_JDR1_JDATA_Pos)     /*!< 0x00020000 */
4482 #define ADC_JDR1_JDATA_18                 (0x40000U << ADC_JDR1_JDATA_Pos)     /*!< 0x00040000 */
4483 #define ADC_JDR1_JDATA_19                 (0x80000U << ADC_JDR1_JDATA_Pos)     /*!< 0x00080000 */
4484 #define ADC_JDR1_JDATA_20                 (0x100000U << ADC_JDR1_JDATA_Pos)    /*!< 0x00100000 */
4485 #define ADC_JDR1_JDATA_21                 (0x200000U << ADC_JDR1_JDATA_Pos)    /*!< 0x00200000 */
4486 #define ADC_JDR1_JDATA_22                 (0x400000U << ADC_JDR1_JDATA_Pos)    /*!< 0x00400000 */
4487 #define ADC_JDR1_JDATA_23                 (0x800000U << ADC_JDR1_JDATA_Pos)    /*!< 0x00800000 */
4488 #define ADC_JDR1_JDATA_24                 (0x1000000U << ADC_JDR1_JDATA_Pos)   /*!< 0x01000000 */
4489 #define ADC_JDR1_JDATA_25                 (0x2000000U << ADC_JDR1_JDATA_Pos)   /*!< 0x02000000 */
4490 #define ADC_JDR1_JDATA_26                 (0x4000000U << ADC_JDR1_JDATA_Pos)   /*!< 0x04000000 */
4491 #define ADC_JDR1_JDATA_27                 (0x8000000U << ADC_JDR1_JDATA_Pos)   /*!< 0x08000000 */
4492 #define ADC_JDR1_JDATA_28                 (0x10000000U << ADC_JDR1_JDATA_Pos)  /*!< 0x10000000 */
4493 #define ADC_JDR1_JDATA_29                 (0x20000000U << ADC_JDR1_JDATA_Pos)  /*!< 0x20000000 */
4494 #define ADC_JDR1_JDATA_30                 (0x40000000U << ADC_JDR1_JDATA_Pos)  /*!< 0x40000000 */
4495 #define ADC_JDR1_JDATA_31                 (0x80000000U << ADC_JDR1_JDATA_Pos)  /*!< 0x80000000 */
4496 
4497 /********************  Bit definition for ADC_JDR2 register  ********************/
4498 #define ADC_JDR2_JDATA_Pos                (0U)
4499 #define ADC_JDR2_JDATA_Msk                (0xFFFFU << ADC_JDR2_JDATA_Pos)      /*!< 0x0000FFFF */
4500 #define ADC_JDR2_JDATA                    ADC_JDR2_JDATA_Msk                   /*!< ADC Injected DATA */
4501 #define ADC_JDR2_JDATA_0                  (0x0001U << ADC_JDR2_JDATA_Pos)      /*!< 0x00000001 */
4502 #define ADC_JDR2_JDATA_1                  (0x0002U << ADC_JDR2_JDATA_Pos)      /*!< 0x00000002 */
4503 #define ADC_JDR2_JDATA_2                  (0x0004U << ADC_JDR2_JDATA_Pos)      /*!< 0x00000004 */
4504 #define ADC_JDR2_JDATA_3                  (0x0008U << ADC_JDR2_JDATA_Pos)      /*!< 0x00000008 */
4505 #define ADC_JDR2_JDATA_4                  (0x0010U << ADC_JDR2_JDATA_Pos)      /*!< 0x00000010 */
4506 #define ADC_JDR2_JDATA_5                  (0x0020U << ADC_JDR2_JDATA_Pos)      /*!< 0x00000020 */
4507 #define ADC_JDR2_JDATA_6                  (0x0040U << ADC_JDR2_JDATA_Pos)      /*!< 0x00000040 */
4508 #define ADC_JDR2_JDATA_7                  (0x0080U << ADC_JDR2_JDATA_Pos)      /*!< 0x00000080 */
4509 #define ADC_JDR2_JDATA_8                  (0x0100U << ADC_JDR2_JDATA_Pos)      /*!< 0x00000100 */
4510 #define ADC_JDR2_JDATA_9                  (0x0200U << ADC_JDR2_JDATA_Pos)      /*!< 0x00000200 */
4511 #define ADC_JDR2_JDATA_10                 (0x0400U << ADC_JDR2_JDATA_Pos)      /*!< 0x00000400 */
4512 #define ADC_JDR2_JDATA_11                 (0x0800U << ADC_JDR2_JDATA_Pos)      /*!< 0x00000800 */
4513 #define ADC_JDR2_JDATA_12                 (0x1000U << ADC_JDR2_JDATA_Pos)      /*!< 0x00001000 */
4514 #define ADC_JDR2_JDATA_13                 (0x2000U << ADC_JDR2_JDATA_Pos)      /*!< 0x00002000 */
4515 #define ADC_JDR2_JDATA_14                 (0x4000U << ADC_JDR2_JDATA_Pos)      /*!< 0x00004000 */
4516 #define ADC_JDR2_JDATA_15                 (0x8000U << ADC_JDR2_JDATA_Pos)      /*!< 0x00008000 */
4517 #define ADC_JDR2_JDATA_16                 (0x10000U << ADC_JDR2_JDATA_Pos)     /*!< 0x00010000 */
4518 #define ADC_JDR2_JDATA_17                 (0x20000U << ADC_JDR2_JDATA_Pos)     /*!< 0x00020000 */
4519 #define ADC_JDR2_JDATA_18                 (0x40000U << ADC_JDR2_JDATA_Pos)     /*!< 0x00040000 */
4520 #define ADC_JDR2_JDATA_19                 (0x80000U << ADC_JDR2_JDATA_Pos)     /*!< 0x00080000 */
4521 #define ADC_JDR2_JDATA_20                 (0x100000U << ADC_JDR2_JDATA_Pos)    /*!< 0x00100000 */
4522 #define ADC_JDR2_JDATA_21                 (0x200000U << ADC_JDR2_JDATA_Pos)    /*!< 0x00200000 */
4523 #define ADC_JDR2_JDATA_22                 (0x400000U << ADC_JDR2_JDATA_Pos)    /*!< 0x00400000 */
4524 #define ADC_JDR2_JDATA_23                 (0x800000U << ADC_JDR2_JDATA_Pos)    /*!< 0x00800000 */
4525 #define ADC_JDR2_JDATA_24                 (0x1000000U << ADC_JDR2_JDATA_Pos)   /*!< 0x01000000 */
4526 #define ADC_JDR2_JDATA_25                 (0x2000000U << ADC_JDR2_JDATA_Pos)   /*!< 0x02000000 */
4527 #define ADC_JDR2_JDATA_26                 (0x4000000U << ADC_JDR2_JDATA_Pos)   /*!< 0x04000000 */
4528 #define ADC_JDR2_JDATA_27                 (0x8000000U << ADC_JDR2_JDATA_Pos)   /*!< 0x08000000 */
4529 #define ADC_JDR2_JDATA_28                 (0x10000000U << ADC_JDR2_JDATA_Pos)  /*!< 0x10000000 */
4530 #define ADC_JDR2_JDATA_29                 (0x20000000U << ADC_JDR2_JDATA_Pos)  /*!< 0x20000000 */
4531 #define ADC_JDR2_JDATA_30                 (0x40000000U << ADC_JDR2_JDATA_Pos)  /*!< 0x40000000 */
4532 #define ADC_JDR2_JDATA_31                 (0x80000000U << ADC_JDR2_JDATA_Pos)  /*!< 0x80000000 */
4533 
4534 /********************  Bit definition for ADC_JDR3 register  ********************/
4535 #define ADC_JDR3_JDATA_Pos                (0U)
4536 #define ADC_JDR3_JDATA_Msk                (0xFFFFU << ADC_JDR3_JDATA_Pos)      /*!< 0x0000FFFF */
4537 #define ADC_JDR3_JDATA                    ADC_JDR3_JDATA_Msk                   /*!< ADC Injected DATA */
4538 #define ADC_JDR3_JDATA_0                  (0x0001U << ADC_JDR3_JDATA_Pos)      /*!< 0x00000001 */
4539 #define ADC_JDR3_JDATA_1                  (0x0002U << ADC_JDR3_JDATA_Pos)      /*!< 0x00000002 */
4540 #define ADC_JDR3_JDATA_2                  (0x0004U << ADC_JDR3_JDATA_Pos)      /*!< 0x00000004 */
4541 #define ADC_JDR3_JDATA_3                  (0x0008U << ADC_JDR3_JDATA_Pos)      /*!< 0x00000008 */
4542 #define ADC_JDR3_JDATA_4                  (0x0010U << ADC_JDR3_JDATA_Pos)      /*!< 0x00000010 */
4543 #define ADC_JDR3_JDATA_5                  (0x0020U << ADC_JDR3_JDATA_Pos)      /*!< 0x00000020 */
4544 #define ADC_JDR3_JDATA_6                  (0x0040U << ADC_JDR3_JDATA_Pos)      /*!< 0x00000040 */
4545 #define ADC_JDR3_JDATA_7                  (0x0080U << ADC_JDR3_JDATA_Pos)      /*!< 0x00000080 */
4546 #define ADC_JDR3_JDATA_8                  (0x0100U << ADC_JDR3_JDATA_Pos)      /*!< 0x00000100 */
4547 #define ADC_JDR3_JDATA_9                  (0x0200U << ADC_JDR3_JDATA_Pos)      /*!< 0x00000200 */
4548 #define ADC_JDR3_JDATA_10                 (0x0400U << ADC_JDR3_JDATA_Pos)      /*!< 0x00000400 */
4549 #define ADC_JDR3_JDATA_11                 (0x0800U << ADC_JDR3_JDATA_Pos)      /*!< 0x00000800 */
4550 #define ADC_JDR3_JDATA_12                 (0x1000U << ADC_JDR3_JDATA_Pos)      /*!< 0x00001000 */
4551 #define ADC_JDR3_JDATA_13                 (0x2000U << ADC_JDR3_JDATA_Pos)      /*!< 0x00002000 */
4552 #define ADC_JDR3_JDATA_14                 (0x4000U << ADC_JDR3_JDATA_Pos)      /*!< 0x00004000 */
4553 #define ADC_JDR3_JDATA_15                 (0x8000U << ADC_JDR3_JDATA_Pos)      /*!< 0x00008000 */
4554 #define ADC_JDR3_JDATA_16                 (0x10000U << ADC_JDR3_JDATA_Pos)     /*!< 0x00010000 */
4555 #define ADC_JDR3_JDATA_17                 (0x20000U << ADC_JDR3_JDATA_Pos)     /*!< 0x00020000 */
4556 #define ADC_JDR3_JDATA_18                 (0x40000U << ADC_JDR3_JDATA_Pos)     /*!< 0x00040000 */
4557 #define ADC_JDR3_JDATA_19                 (0x80000U << ADC_JDR3_JDATA_Pos)     /*!< 0x00080000 */
4558 #define ADC_JDR3_JDATA_20                 (0x100000U << ADC_JDR3_JDATA_Pos)    /*!< 0x00100000 */
4559 #define ADC_JDR3_JDATA_21                 (0x200000U << ADC_JDR3_JDATA_Pos)    /*!< 0x00200000 */
4560 #define ADC_JDR3_JDATA_22                 (0x400000U << ADC_JDR3_JDATA_Pos)    /*!< 0x00400000 */
4561 #define ADC_JDR3_JDATA_23                 (0x800000U << ADC_JDR3_JDATA_Pos)    /*!< 0x00800000 */
4562 #define ADC_JDR3_JDATA_24                 (0x1000000U << ADC_JDR3_JDATA_Pos)   /*!< 0x01000000 */
4563 #define ADC_JDR3_JDATA_25                 (0x2000000U << ADC_JDR3_JDATA_Pos)   /*!< 0x02000000 */
4564 #define ADC_JDR3_JDATA_26                 (0x4000000U << ADC_JDR3_JDATA_Pos)   /*!< 0x04000000 */
4565 #define ADC_JDR3_JDATA_27                 (0x8000000U << ADC_JDR3_JDATA_Pos)   /*!< 0x08000000 */
4566 #define ADC_JDR3_JDATA_28                 (0x10000000U << ADC_JDR3_JDATA_Pos)  /*!< 0x10000000 */
4567 #define ADC_JDR3_JDATA_29                 (0x20000000U << ADC_JDR3_JDATA_Pos)  /*!< 0x20000000 */
4568 #define ADC_JDR3_JDATA_30                 (0x40000000U << ADC_JDR3_JDATA_Pos)  /*!< 0x40000000 */
4569 #define ADC_JDR3_JDATA_31                 (0x80000000U << ADC_JDR3_JDATA_Pos)  /*!< 0x80000000 */
4570 
4571 /********************  Bit definition for ADC_JDR4 register  ********************/
4572 #define ADC_JDR4_JDATA_Pos                (0U)
4573 #define ADC_JDR4_JDATA_Msk                (0xFFFFU << ADC_JDR4_JDATA_Pos)      /*!< 0x0000FFFF */
4574 #define ADC_JDR4_JDATA                    ADC_JDR4_JDATA_Msk                   /*!< ADC Injected DATA */
4575 #define ADC_JDR4_JDATA_0                  (0x0001U << ADC_JDR4_JDATA_Pos)      /*!< 0x00000001 */
4576 #define ADC_JDR4_JDATA_1                  (0x0002U << ADC_JDR4_JDATA_Pos)      /*!< 0x00000002 */
4577 #define ADC_JDR4_JDATA_2                  (0x0004U << ADC_JDR4_JDATA_Pos)      /*!< 0x00000004 */
4578 #define ADC_JDR4_JDATA_3                  (0x0008U << ADC_JDR4_JDATA_Pos)      /*!< 0x00000008 */
4579 #define ADC_JDR4_JDATA_4                  (0x0010U << ADC_JDR4_JDATA_Pos)      /*!< 0x00000010 */
4580 #define ADC_JDR4_JDATA_5                  (0x0020U << ADC_JDR4_JDATA_Pos)      /*!< 0x00000020 */
4581 #define ADC_JDR4_JDATA_6                  (0x0040U << ADC_JDR4_JDATA_Pos)      /*!< 0x00000040 */
4582 #define ADC_JDR4_JDATA_7                  (0x0080U << ADC_JDR4_JDATA_Pos)      /*!< 0x00000080 */
4583 #define ADC_JDR4_JDATA_8                  (0x0100U << ADC_JDR4_JDATA_Pos)      /*!< 0x00000100 */
4584 #define ADC_JDR4_JDATA_9                  (0x0200U << ADC_JDR4_JDATA_Pos)      /*!< 0x00000200 */
4585 #define ADC_JDR4_JDATA_10                 (0x0400U << ADC_JDR4_JDATA_Pos)      /*!< 0x00000400 */
4586 #define ADC_JDR4_JDATA_11                 (0x0800U << ADC_JDR4_JDATA_Pos)      /*!< 0x00000800 */
4587 #define ADC_JDR4_JDATA_12                 (0x1000U << ADC_JDR4_JDATA_Pos)      /*!< 0x00001000 */
4588 #define ADC_JDR4_JDATA_13                 (0x2000U << ADC_JDR4_JDATA_Pos)      /*!< 0x00002000 */
4589 #define ADC_JDR4_JDATA_14                 (0x4000U << ADC_JDR4_JDATA_Pos)      /*!< 0x00004000 */
4590 #define ADC_JDR4_JDATA_15                 (0x8000U << ADC_JDR4_JDATA_Pos)      /*!< 0x00008000 */
4591 #define ADC_JDR4_JDATA_16                 (0x10000U << ADC_JDR4_JDATA_Pos)     /*!< 0x00010000 */
4592 #define ADC_JDR4_JDATA_17                 (0x20000U << ADC_JDR4_JDATA_Pos)     /*!< 0x00020000 */
4593 #define ADC_JDR4_JDATA_18                 (0x40000U << ADC_JDR4_JDATA_Pos)     /*!< 0x00040000 */
4594 #define ADC_JDR4_JDATA_19                 (0x80000U << ADC_JDR4_JDATA_Pos)     /*!< 0x00080000 */
4595 #define ADC_JDR4_JDATA_20                 (0x100000U << ADC_JDR4_JDATA_Pos)    /*!< 0x00100000 */
4596 #define ADC_JDR4_JDATA_21                 (0x200000U << ADC_JDR4_JDATA_Pos)    /*!< 0x00200000 */
4597 #define ADC_JDR4_JDATA_22                 (0x400000U << ADC_JDR4_JDATA_Pos)    /*!< 0x00400000 */
4598 #define ADC_JDR4_JDATA_23                 (0x800000U << ADC_JDR4_JDATA_Pos)    /*!< 0x00800000 */
4599 #define ADC_JDR4_JDATA_24                 (0x1000000U << ADC_JDR4_JDATA_Pos)   /*!< 0x01000000 */
4600 #define ADC_JDR4_JDATA_25                 (0x2000000U << ADC_JDR4_JDATA_Pos)   /*!< 0x02000000 */
4601 #define ADC_JDR4_JDATA_26                 (0x4000000U << ADC_JDR4_JDATA_Pos)   /*!< 0x04000000 */
4602 #define ADC_JDR4_JDATA_27                 (0x8000000U << ADC_JDR4_JDATA_Pos)   /*!< 0x08000000 */
4603 #define ADC_JDR4_JDATA_28                 (0x10000000U << ADC_JDR4_JDATA_Pos)  /*!< 0x10000000 */
4604 #define ADC_JDR4_JDATA_29                 (0x20000000U << ADC_JDR4_JDATA_Pos)  /*!< 0x20000000 */
4605 #define ADC_JDR4_JDATA_30                 (0x40000000U << ADC_JDR4_JDATA_Pos)  /*!< 0x40000000 */
4606 #define ADC_JDR4_JDATA_31                 (0x80000000U << ADC_JDR4_JDATA_Pos)  /*!< 0x80000000 */
4607 
4608 /********************  Bit definition for ADC_AWD2CR register  ********************/
4609 #define ADC_AWD2CR_AWD2CH_Pos             (0U)
4610 #define ADC_AWD2CR_AWD2CH_Msk             (0xFFFFFU << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x000FFFFF */
4611 #define ADC_AWD2CR_AWD2CH                 ADC_AWD2CR_AWD2CH_Msk                /*!< ADC Analog watchdog 2 channel selection */
4612 #define ADC_AWD2CR_AWD2CH_0               (0x00001U << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000001 */
4613 #define ADC_AWD2CR_AWD2CH_1               (0x00002U << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000002 */
4614 #define ADC_AWD2CR_AWD2CH_2               (0x00004U << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000004 */
4615 #define ADC_AWD2CR_AWD2CH_3               (0x00008U << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000008 */
4616 #define ADC_AWD2CR_AWD2CH_4               (0x00010U << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000010 */
4617 #define ADC_AWD2CR_AWD2CH_5               (0x00020U << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000020 */
4618 #define ADC_AWD2CR_AWD2CH_6               (0x00040U << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000040 */
4619 #define ADC_AWD2CR_AWD2CH_7               (0x00080U << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000080 */
4620 #define ADC_AWD2CR_AWD2CH_8               (0x00100U << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000100 */
4621 #define ADC_AWD2CR_AWD2CH_9               (0x00200U << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000200 */
4622 #define ADC_AWD2CR_AWD2CH_10              (0x00400U << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000400 */
4623 #define ADC_AWD2CR_AWD2CH_11              (0x00800U << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000800 */
4624 #define ADC_AWD2CR_AWD2CH_12              (0x01000U << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00001000 */
4625 #define ADC_AWD2CR_AWD2CH_13              (0x02000U << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00002000 */
4626 #define ADC_AWD2CR_AWD2CH_14              (0x04000U << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00004000 */
4627 #define ADC_AWD2CR_AWD2CH_15              (0x08000U << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00008000 */
4628 #define ADC_AWD2CR_AWD2CH_16              (0x10000U << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00010000 */
4629 #define ADC_AWD2CR_AWD2CH_17              (0x20000U << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00020000 */
4630 #define ADC_AWD2CR_AWD2CH_18              (0x40000U << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00040000 */
4631 #define ADC_AWD2CR_AWD2CH_19              (0x80000U << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00080000 */
4632 
4633 /********************  Bit definition for ADC_AWD3CR register  ********************/
4634 #define ADC_AWD3CR_AWD3CH_Pos             (0U)
4635 #define ADC_AWD3CR_AWD3CH_Msk             (0xFFFFFU << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x000FFFFF */
4636 #define ADC_AWD3CR_AWD3CH                 ADC_AWD3CR_AWD3CH_Msk                /*!< ADC Analog watchdog 3 channel selection */
4637 #define ADC_AWD3CR_AWD3CH_0               (0x00001U << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000001 */
4638 #define ADC_AWD3CR_AWD3CH_1               (0x00002U << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000002 */
4639 #define ADC_AWD3CR_AWD3CH_2               (0x00004U << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000004 */
4640 #define ADC_AWD3CR_AWD3CH_3               (0x00008U << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000008 */
4641 #define ADC_AWD3CR_AWD3CH_4               (0x00010U << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000010 */
4642 #define ADC_AWD3CR_AWD3CH_5               (0x00020U << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000020 */
4643 #define ADC_AWD3CR_AWD3CH_6               (0x00040U << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000040 */
4644 #define ADC_AWD3CR_AWD3CH_7               (0x00080U << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000080 */
4645 #define ADC_AWD3CR_AWD3CH_8               (0x00100U << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000100 */
4646 #define ADC_AWD3CR_AWD3CH_9               (0x00200U << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000200 */
4647 #define ADC_AWD3CR_AWD3CH_10              (0x00400U << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000400 */
4648 #define ADC_AWD3CR_AWD3CH_11              (0x00800U << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000800 */
4649 #define ADC_AWD3CR_AWD3CH_12              (0x01000U << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00001000 */
4650 #define ADC_AWD3CR_AWD3CH_13              (0x02000U << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00002000 */
4651 #define ADC_AWD3CR_AWD3CH_14              (0x04000U << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00004000 */
4652 #define ADC_AWD3CR_AWD3CH_15              (0x08000U << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00008000 */
4653 #define ADC_AWD3CR_AWD3CH_16              (0x10000U << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00010000 */
4654 #define ADC_AWD3CR_AWD3CH_17              (0x20000U << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00020000 */
4655 #define ADC_AWD3CR_AWD3CH_18              (0x40000U << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00040000 */
4656 #define ADC_AWD3CR_AWD3CH_19              (0x80000U << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00080000 */
4657 
4658 /********************  Bit definition for ADC_DIFSEL register  ********************/
4659 #define ADC_DIFSEL_DIFSEL_Pos             (0U)
4660 #define ADC_DIFSEL_DIFSEL_Msk             (0xFFFFFU << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x000FFFFF */
4661 #define ADC_DIFSEL_DIFSEL                 ADC_DIFSEL_DIFSEL_Msk                /*!< ADC differential modes for channels 1 to 18 */
4662 #define ADC_DIFSEL_DIFSEL_0               (0x00001U << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000001 */
4663 #define ADC_DIFSEL_DIFSEL_1               (0x00002U << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000002 */
4664 #define ADC_DIFSEL_DIFSEL_2               (0x00004U << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000004 */
4665 #define ADC_DIFSEL_DIFSEL_3               (0x00008U << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000008 */
4666 #define ADC_DIFSEL_DIFSEL_4               (0x00010U << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000010 */
4667 #define ADC_DIFSEL_DIFSEL_5               (0x00020U << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000020 */
4668 #define ADC_DIFSEL_DIFSEL_6               (0x00040U << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000040 */
4669 #define ADC_DIFSEL_DIFSEL_7               (0x00080U << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000080 */
4670 #define ADC_DIFSEL_DIFSEL_8               (0x00100U << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000100 */
4671 #define ADC_DIFSEL_DIFSEL_9               (0x00200U << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000200 */
4672 #define ADC_DIFSEL_DIFSEL_10              (0x00400U << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000400 */
4673 #define ADC_DIFSEL_DIFSEL_11              (0x00800U << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000800 */
4674 #define ADC_DIFSEL_DIFSEL_12              (0x01000U << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00001000 */
4675 #define ADC_DIFSEL_DIFSEL_13              (0x02000U << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00002000 */
4676 #define ADC_DIFSEL_DIFSEL_14              (0x04000U << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00004000 */
4677 #define ADC_DIFSEL_DIFSEL_15              (0x08000U << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00008000 */
4678 #define ADC_DIFSEL_DIFSEL_16              (0x10000U << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00010000 */
4679 #define ADC_DIFSEL_DIFSEL_17              (0x20000U << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00020000 */
4680 #define ADC_DIFSEL_DIFSEL_18              (0x40000U << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00040000 */
4681 #define ADC_DIFSEL_DIFSEL_19              (0x80000U << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00080000 */
4682 
4683 /********************  Bit definition for ADC_CALFACT register  ********************/
4684 #define ADC_CALFACT_CALFACT_S_Pos         (0U)
4685 #define ADC_CALFACT_CALFACT_S_Msk         (0x7FFU << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */
4686 #define ADC_CALFACT_CALFACT_S             ADC_CALFACT_CALFACT_S_Msk            /*!< ADC calibration factors in single-ended mode */
4687 #define ADC_CALFACT_CALFACT_S_0           (0x001U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
4688 #define ADC_CALFACT_CALFACT_S_1           (0x002U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
4689 #define ADC_CALFACT_CALFACT_S_2           (0x004U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
4690 #define ADC_CALFACT_CALFACT_S_3           (0x008U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
4691 #define ADC_CALFACT_CALFACT_S_4           (0x010U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
4692 #define ADC_CALFACT_CALFACT_S_5           (0x020U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
4693 #define ADC_CALFACT_CALFACT_S_6           (0x040U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
4694 #define ADC_CALFACT_CALFACT_S_7           (0x080U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */
4695 #define ADC_CALFACT_CALFACT_S_8           (0x100U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */
4696 #define ADC_CALFACT_CALFACT_S_9           (0x200U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */
4697 #define ADC_CALFACT_CALFACT_S_10          (0x400U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */
4698 #define ADC_CALFACT_CALFACT_D_Pos         (16U)
4699 #define ADC_CALFACT_CALFACT_D_Msk         (0x7FFU << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */
4700 #define ADC_CALFACT_CALFACT_D             ADC_CALFACT_CALFACT_D_Msk            /*!< ADC calibration factors in differential mode */
4701 #define ADC_CALFACT_CALFACT_D_0           (0x001U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
4702 #define ADC_CALFACT_CALFACT_D_1           (0x002U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
4703 #define ADC_CALFACT_CALFACT_D_2           (0x004U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
4704 #define ADC_CALFACT_CALFACT_D_3           (0x008U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
4705 #define ADC_CALFACT_CALFACT_D_4           (0x010U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
4706 #define ADC_CALFACT_CALFACT_D_5           (0x020U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
4707 #define ADC_CALFACT_CALFACT_D_6           (0x040U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
4708 #define ADC_CALFACT_CALFACT_D_7           (0x080U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */
4709 #define ADC_CALFACT_CALFACT_D_8           (0x100U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */
4710 #define ADC_CALFACT_CALFACT_D_9           (0x200U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */
4711 #define ADC_CALFACT_CALFACT_D_10          (0x400U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */
4712 
4713 /********************  Bit definition for ADC_CALFACT2 register  ********************/
4714 #define ADC_CALFACT2_LINCALFACT_Pos       (0U)
4715 #define ADC_CALFACT2_LINCALFACT_Msk       (0x3FFFFFFFU << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */
4716 #define ADC_CALFACT2_LINCALFACT           ADC_CALFACT2_LINCALFACT_Msk          /*!< ADC Linearity calibration factors */
4717 #define ADC_CALFACT2_LINCALFACT_0         (0x00000001U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */
4718 #define ADC_CALFACT2_LINCALFACT_1         (0x00000002U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */
4719 #define ADC_CALFACT2_LINCALFACT_2         (0x00000004U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */
4720 #define ADC_CALFACT2_LINCALFACT_3         (0x00000008U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */
4721 #define ADC_CALFACT2_LINCALFACT_4         (0x00000010U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */
4722 #define ADC_CALFACT2_LINCALFACT_5         (0x00000020U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */
4723 #define ADC_CALFACT2_LINCALFACT_6         (0x00000040U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */
4724 #define ADC_CALFACT2_LINCALFACT_7         (0x00000080U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */
4725 #define ADC_CALFACT2_LINCALFACT_8         (0x00000100U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */
4726 #define ADC_CALFACT2_LINCALFACT_9         (0x00000200U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */
4727 #define ADC_CALFACT2_LINCALFACT_10        (0x00000400U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */
4728 #define ADC_CALFACT2_LINCALFACT_11        (0x00000800U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */
4729 #define ADC_CALFACT2_LINCALFACT_12        (0x00001000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */
4730 #define ADC_CALFACT2_LINCALFACT_13        (0x00002000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */
4731 #define ADC_CALFACT2_LINCALFACT_14        (0x00004000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */
4732 #define ADC_CALFACT2_LINCALFACT_15        (0x00008000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */
4733 #define ADC_CALFACT2_LINCALFACT_16        (0x00010000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */
4734 #define ADC_CALFACT2_LINCALFACT_17        (0x00020000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */
4735 #define ADC_CALFACT2_LINCALFACT_18        (0x00040000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */
4736 #define ADC_CALFACT2_LINCALFACT_19        (0x00080000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */
4737 #define ADC_CALFACT2_LINCALFACT_20        (0x00100000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */
4738 #define ADC_CALFACT2_LINCALFACT_21        (0x00200000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */
4739 #define ADC_CALFACT2_LINCALFACT_22        (0x00400000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */
4740 #define ADC_CALFACT2_LINCALFACT_23        (0x00800000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */
4741 #define ADC_CALFACT2_LINCALFACT_24        (0x01000000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */
4742 #define ADC_CALFACT2_LINCALFACT_25        (0x02000000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */
4743 #define ADC_CALFACT2_LINCALFACT_26        (0x04000000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */
4744 #define ADC_CALFACT2_LINCALFACT_27        (0x08000001U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000001 */
4745 #define ADC_CALFACT2_LINCALFACT_28        (0x10000000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */
4746 #define ADC_CALFACT2_LINCALFACT_29        (0x20000000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */
4747 
4748 /********************  Bit definition for ADC2_OR - Option Register  ********************/
4749 #define ADC2_OR_VDDCOREEN_Pos            (0U)
4750 #define ADC2_OR_VDDCOREEN_Msk            (0x1U << ADC2_OR_VDDCOREEN_Pos) /*!< 0x00000001 */
4751 #define ADC2_OR_VDDCOREEN                ADC2_OR_VDDCOREEN_Msk          /*!< ADC2 Option Register  - VDDCORE enable bit */
4752 
4753 /*************************  ADC Common registers  *****************************/
4754 /********************  Bit definition for ADC_CSR register  ********************/
4755 #define ADC_CSR_ADRDY_MST_Pos          (0U)
4756 #define ADC_CSR_ADRDY_MST_Msk          (0x1U << ADC_CSR_ADRDY_MST_Pos)   /*!< 0x00000001 */
4757 #define ADC_CSR_ADRDY_MST              ADC_CSR_ADRDY_MST_Msk             /*!< Master ADC ready */
4758 #define ADC_CSR_EOSMP_MST_Pos          (1U)
4759 #define ADC_CSR_EOSMP_MST_Msk          (0x1U << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */
4760 #define ADC_CSR_EOSMP_MST              ADC_CSR_EOSMP_MST_Msk       /*!< End of sampling phase flag of the master ADC */
4761 #define ADC_CSR_EOC_MST_Pos      (2U)
4762 #define ADC_CSR_EOC_MST_Msk      (0x1U << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */
4763 #define ADC_CSR_EOC_MST          ADC_CSR_EOC_MST_Msk         /*!< End of regular conversion of the master ADC */
4764 #define ADC_CSR_EOS_MST_Pos      (3U)
4765 #define ADC_CSR_EOS_MST_Msk      (0x1U << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */
4766 #define ADC_CSR_EOS_MST          ADC_CSR_EOS_MST_Msk         /*!< End of regular sequence flag of the master ADC */
4767 #define ADC_CSR_OVR_MST_Pos      (4U)
4768 #define ADC_CSR_OVR_MST_Msk      (0x1U << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */
4769 #define ADC_CSR_OVR_MST          ADC_CSR_OVR_MST_Msk         /*!< Overrun flag of the master ADC */
4770 #define ADC_CSR_JEOC_MST_Pos     (5U)
4771 #define ADC_CSR_JEOC_MST_Msk     (0x1U << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */
4772 #define ADC_CSR_JEOC_MST         ADC_CSR_JEOC_MST_Msk        /*!< End of injected conversion of the master ADC */
4773 #define ADC_CSR_JEOS_MST_Pos     (6U)
4774 #define ADC_CSR_JEOS_MST_Msk     (0x1U << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */
4775 #define ADC_CSR_JEOS_MST         ADC_CSR_JEOS_MST_Msk        /*!< End of injected sequence flag of the master ADC */
4776 #define ADC_CSR_AWD1_MST_Pos           (7U)
4777 #define ADC_CSR_AWD1_MST_Msk           (0x1U << ADC_CSR_AWD1_MST_Pos)    /*!< 0x00000080 */
4778 #define ADC_CSR_AWD1_MST               ADC_CSR_AWD1_MST_Msk              /*!< Analog watchdog 1 flag of the master ADC */
4779 #define ADC_CSR_AWD2_MST_Pos           (8U)
4780 #define ADC_CSR_AWD2_MST_Msk           (0x1U << ADC_CSR_AWD2_MST_Pos)    /*!< 0x00000100 */
4781 #define ADC_CSR_AWD2_MST               ADC_CSR_AWD2_MST_Msk              /*!< Analog watchdog 2 flag of the master ADC */
4782 #define ADC_CSR_AWD3_MST_Pos           (9U)
4783 #define ADC_CSR_AWD3_MST_Msk           (0x1U << ADC_CSR_AWD3_MST_Pos)    /*!< 0x00000200 */
4784 #define ADC_CSR_AWD3_MST               ADC_CSR_AWD3_MST_Msk              /*!< Analog watchdog 3 flag of the master ADC */
4785 #define ADC_CSR_JQOVF_MST_Pos          (10U)
4786 #define ADC_CSR_JQOVF_MST_Msk          (0x1U << ADC_CSR_JQOVF_MST_Pos)   /*!< 0x00000400 */
4787 #define ADC_CSR_JQOVF_MST              ADC_CSR_JQOVF_MST_Msk             /*!< Injected context queue overflow flag of the master ADC */
4788 #define ADC_CSR_ADRDY_SLV_Pos          (16U)
4789 #define ADC_CSR_ADRDY_SLV_Msk          (0x1U << ADC_CSR_ADRDY_SLV_Pos)   /*!< 0x00010000 */
4790 #define ADC_CSR_ADRDY_SLV              ADC_CSR_ADRDY_SLV_Msk             /*!< Slave ADC ready */
4791 #define ADC_CSR_EOSMP_SLV_Pos    (17U)
4792 #define ADC_CSR_EOSMP_SLV_Msk    (0x1U << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */
4793 #define ADC_CSR_EOSMP_SLV        ADC_CSR_EOSMP_SLV_Msk       /*!< End of sampling phase flag of the slave ADC */
4794 #define ADC_CSR_EOC_SLV_Pos      (18U)
4795 #define ADC_CSR_EOC_SLV_Msk      (0x1U << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
4796 #define ADC_CSR_EOC_SLV          ADC_CSR_EOC_SLV_Msk         /*!< End of regular conversion of the slave ADC */
4797 #define ADC_CSR_EOS_SLV_Pos      (19U)
4798 #define ADC_CSR_EOS_SLV_Msk      (0x1U << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */
4799 #define ADC_CSR_EOS_SLV          ADC_CSR_EOS_SLV_Msk         /*!< End of regular sequence flag of the slave ADC */
4800 #define ADC_CSR_OVR_SLV_Pos      (20U)
4801 #define ADC_CSR_OVR_SLV_Msk      (0x1U << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */
4802 #define ADC_CSR_OVR_SLV          ADC_CSR_OVR_SLV_Msk         /*!< Overrun flag of the slave ADC */
4803 #define ADC_CSR_JEOC_SLV_Pos     (21U)
4804 #define ADC_CSR_JEOC_SLV_Msk     (0x1U << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */
4805 #define ADC_CSR_JEOC_SLV         ADC_CSR_JEOC_SLV_Msk        /*!< End of injected conversion of the slave ADC */
4806 #define ADC_CSR_JEOS_SLV_Pos     (22U)
4807 #define ADC_CSR_JEOS_SLV_Msk     (0x1U << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */
4808 #define ADC_CSR_JEOS_SLV         ADC_CSR_JEOS_SLV_Msk        /*!< End of injected sequence flag of the slave ADC */
4809 #define ADC_CSR_AWD1_SLV_Pos           (23U)
4810 #define ADC_CSR_AWD1_SLV_Msk           (0x1U << ADC_CSR_AWD1_SLV_Pos)    /*!< 0x00800000 */
4811 #define ADC_CSR_AWD1_SLV               ADC_CSR_AWD1_SLV_Msk              /*!< Analog watchdog 1 flag of the slave ADC */
4812 #define ADC_CSR_AWD2_SLV_Pos           (24U)
4813 #define ADC_CSR_AWD2_SLV_Msk           (0x1U << ADC_CSR_AWD2_SLV_Pos)    /*!< 0x01000000 */
4814 #define ADC_CSR_AWD2_SLV               ADC_CSR_AWD2_SLV_Msk              /*!< Analog watchdog 2 flag of the slave ADC */
4815 #define ADC_CSR_AWD3_SLV_Pos           (25U)
4816 #define ADC_CSR_AWD3_SLV_Msk           (0x1U << ADC_CSR_AWD3_SLV_Pos)    /*!< 0x02000000 */
4817 #define ADC_CSR_AWD3_SLV               ADC_CSR_AWD3_SLV_Msk              /*!< Analog watchdog 3 flag of the slave ADC */
4818 #define ADC_CSR_JQOVF_SLV_Pos          (26U)
4819 #define ADC_CSR_JQOVF_SLV_Msk          (0x1U << ADC_CSR_JQOVF_SLV_Pos)   /*!< 0x04000000 */
4820 #define ADC_CSR_JQOVF_SLV              ADC_CSR_JQOVF_SLV_Msk             /*!< Injected context queue overflow flag of the slave ADC */
4821 
4822 /********************  Bit definition for ADC_CCR register  ********************/
4823 #define ADC_CCR_DUAL_Pos                  (0U)
4824 #define ADC_CCR_DUAL_Msk                  (0x1FU << ADC_CCR_DUAL_Pos)          /*!< 0x0000001F */
4825 #define ADC_CCR_DUAL                      ADC_CCR_DUAL_Msk                     /*!< Dual ADC mode selection */
4826 #define ADC_CCR_DUAL_0                    (0x01U << ADC_CCR_DUAL_Pos)          /*!< 0x00000001 */
4827 #define ADC_CCR_DUAL_1                    (0x02U << ADC_CCR_DUAL_Pos)          /*!< 0x00000002 */
4828 #define ADC_CCR_DUAL_2                    (0x04U << ADC_CCR_DUAL_Pos)          /*!< 0x00000004 */
4829 #define ADC_CCR_DUAL_3                    (0x08U << ADC_CCR_DUAL_Pos)          /*!< 0x00000008 */
4830 #define ADC_CCR_DUAL_4                    (0x10U << ADC_CCR_DUAL_Pos)          /*!< 0x00000010 */
4831 
4832 #define ADC_CCR_DELAY_Pos                 (8U)
4833 #define ADC_CCR_DELAY_Msk                 (0xFU << ADC_CCR_DELAY_Pos)          /*!< 0x00000F00 */
4834 #define ADC_CCR_DELAY                     ADC_CCR_DELAY_Msk                    /*!< Delay between 2 sampling phases */
4835 #define ADC_CCR_DELAY_0                   (0x1U << ADC_CCR_DELAY_Pos)          /*!< 0x00000100 */
4836 #define ADC_CCR_DELAY_1                   (0x2U << ADC_CCR_DELAY_Pos)          /*!< 0x00000200 */
4837 #define ADC_CCR_DELAY_2                   (0x4U << ADC_CCR_DELAY_Pos)          /*!< 0x00000400 */
4838 #define ADC_CCR_DELAY_3                   (0x8U << ADC_CCR_DELAY_Pos)          /*!< 0x00000800 */
4839 
4840 #define ADC_CCR_DAMDF_Pos                 (14U)
4841 #define ADC_CCR_DAMDF_Msk                 (0x3U << ADC_CCR_DAMDF_Pos)          /*!< 0x0000C000 */
4842 #define ADC_CCR_DAMDF                     ADC_CCR_DAMDF_Msk                    /*!< Dual ADC mode Data format */
4843 #define ADC_CCR_DAMDF_0                   (0x1U << ADC_CCR_DAMDF_Pos)          /*!< 0x00004000 */
4844 #define ADC_CCR_DAMDF_1                   (0x2U << ADC_CCR_DAMDF_Pos)          /*!< 0x00008000 */
4845 
4846 #define ADC_CCR_CKMODE_Pos                (16U)
4847 #define ADC_CCR_CKMODE_Msk                (0x3U << ADC_CCR_CKMODE_Pos)         /*!< 0x00030000 */
4848 #define ADC_CCR_CKMODE                    ADC_CCR_CKMODE_Msk                   /*!< ADC clock mode */
4849 #define ADC_CCR_CKMODE_0                  (0x1U << ADC_CCR_CKMODE_Pos)         /*!< 0x00010000 */
4850 #define ADC_CCR_CKMODE_1                  (0x2U << ADC_CCR_CKMODE_Pos)         /*!< 0x00020000 */
4851 
4852 #define ADC_CCR_PRESC_Pos                 (18U)
4853 #define ADC_CCR_PRESC_Msk                 (0xFU << ADC_CCR_PRESC_Pos)          /*!< 0x003C0000 */
4854 #define ADC_CCR_PRESC                     ADC_CCR_PRESC_Msk                    /*!< ADC prescaler */
4855 #define ADC_CCR_PRESC_0                   (0x1U << ADC_CCR_PRESC_Pos)          /*!< 0x00040000 */
4856 #define ADC_CCR_PRESC_1                   (0x2U << ADC_CCR_PRESC_Pos)          /*!< 0x00080000 */
4857 #define ADC_CCR_PRESC_2                   (0x4U << ADC_CCR_PRESC_Pos)          /*!< 0x00100000 */
4858 #define ADC_CCR_PRESC_3                   (0x8U << ADC_CCR_PRESC_Pos)          /*!< 0x00200000 */
4859 
4860 #define ADC_CCR_VREFEN_Pos                (22U)
4861 #define ADC_CCR_VREFEN_Msk                (0x1U << ADC_CCR_VREFEN_Pos)         /*!< 0x00400000 */
4862 #define ADC_CCR_VREFEN                    ADC_CCR_VREFEN_Msk                   /*!< VREFINT enable */
4863 #define ADC_CCR_VSENSEEN_Pos              (23U)
4864 #define ADC_CCR_VSENSEEN_Msk              (0x1U << ADC_CCR_VSENSEEN_Pos)      /*!< 0x00800000 */
4865 #define ADC_CCR_VSENSEEN                  ADC_CCR_VSENSEEN_Msk                /*!< Temperature sensor enable */
4866 #define ADC_CCR_VBATEN_Pos                (24U)
4867 #define ADC_CCR_VBATEN_Msk                (0x1U << ADC_CCR_VBATEN_Pos)         /*!< 0x01000000 */
4868 #define ADC_CCR_VBATEN                    ADC_CCR_VBATEN_Msk                   /*!< VBAT enable */
4869 
4870 /********************  Bit definition for ADC_CDR register  ********************/
4871 #define ADC_CDR_RDATA_MST_Pos          (0U)
4872 #define ADC_CDR_RDATA_MST_Msk          (0xFFFFU << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */
4873 #define ADC_CDR_RDATA_MST              ADC_CDR_RDATA_MST_Msk             /*!< Regular Data of the master ADC */
4874 #define ADC_CDR_RDATA_MST_0            (0x0001U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000001 */
4875 #define ADC_CDR_RDATA_MST_1            (0x0002U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000002 */
4876 #define ADC_CDR_RDATA_MST_2            (0x0004U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000004 */
4877 #define ADC_CDR_RDATA_MST_3            (0x0008U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000008 */
4878 #define ADC_CDR_RDATA_MST_4            (0x0010U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000010 */
4879 #define ADC_CDR_RDATA_MST_5            (0x0020U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000020 */
4880 #define ADC_CDR_RDATA_MST_6            (0x0040U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000040 */
4881 #define ADC_CDR_RDATA_MST_7            (0x0080U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000080 */
4882 #define ADC_CDR_RDATA_MST_8            (0x0100U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000100 */
4883 #define ADC_CDR_RDATA_MST_9            (0x0200U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000200 */
4884 #define ADC_CDR_RDATA_MST_10           (0x0400U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000400 */
4885 #define ADC_CDR_RDATA_MST_11           (0x0800U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000800 */
4886 #define ADC_CDR_RDATA_MST_12           (0x1000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00001000 */
4887 #define ADC_CDR_RDATA_MST_13           (0x2000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00002000 */
4888 #define ADC_CDR_RDATA_MST_14           (0x4000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00004000 */
4889 #define ADC_CDR_RDATA_MST_15           (0x8000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00008000 */
4890 
4891 #define ADC_CDR_RDATA_SLV_Pos          (16U)
4892 #define ADC_CDR_RDATA_SLV_Msk          (0xFFFFU << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */
4893 #define ADC_CDR_RDATA_SLV              ADC_CDR_RDATA_SLV_Msk             /*!< Regular Data of the master ADC */
4894 #define ADC_CDR_RDATA_SLV_0            (0x0001U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */
4895 #define ADC_CDR_RDATA_SLV_1            (0x0002U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */
4896 #define ADC_CDR_RDATA_SLV_2            (0x0004U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */
4897 #define ADC_CDR_RDATA_SLV_3            (0x0008U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */
4898 #define ADC_CDR_RDATA_SLV_4            (0x0010U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */
4899 #define ADC_CDR_RDATA_SLV_5            (0x0020U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */
4900 #define ADC_CDR_RDATA_SLV_6            (0x0040U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */
4901 #define ADC_CDR_RDATA_SLV_7            (0x0080U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */
4902 #define ADC_CDR_RDATA_SLV_8            (0x0100U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */
4903 #define ADC_CDR_RDATA_SLV_9            (0x0200U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */
4904 #define ADC_CDR_RDATA_SLV_10           (0x0400U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */
4905 #define ADC_CDR_RDATA_SLV_11           (0x0800U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */
4906 #define ADC_CDR_RDATA_SLV_12           (0x1000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */
4907 #define ADC_CDR_RDATA_SLV_13           (0x2000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */
4908 #define ADC_CDR_RDATA_SLV_14           (0x4000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */
4909 #define ADC_CDR_RDATA_SLV_15           (0x8000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */
4910 
4911 /********************  Bit definition for ADC_CDR2 register  ********************/
4912 #define ADC_CDR2_RDATA_ALT_Pos         (0U)
4913 #define ADC_CDR2_RDATA_ALT_Msk         (0xFFFFFFFFU << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */
4914 #define ADC_CDR2_RDATA_ALT             ADC_CDR2_RDATA_ALT_Msk            /*!< Regular Data for dual Mode */
4915 #define ADC_CDR2_RDATA_ALT_0           (0x00000001U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00000001 */
4916 #define ADC_CDR2_RDATA_ALT_1           (0x00000002U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00000002 */
4917 #define ADC_CDR2_RDATA_ALT_2           (0x00000004U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00000004 */
4918 #define ADC_CDR2_RDATA_ALT_3           (0x00000008U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00000008 */
4919 #define ADC_CDR2_RDATA_ALT_4           (0x00000010U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00000010 */
4920 #define ADC_CDR2_RDATA_ALT_5           (0x00000020U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00000020 */
4921 #define ADC_CDR2_RDATA_ALT_6           (0x00000040U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00000040 */
4922 #define ADC_CDR2_RDATA_ALT_7           (0x00000080U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00000080 */
4923 #define ADC_CDR2_RDATA_ALT_8           (0x00000100U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00000100 */
4924 #define ADC_CDR2_RDATA_ALT_9           (0x00000200U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00000200 */
4925 #define ADC_CDR2_RDATA_ALT_10          (0x00000400U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00000400 */
4926 #define ADC_CDR2_RDATA_ALT_11          (0x00000800U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00000800 */
4927 #define ADC_CDR2_RDATA_ALT_12          (0x00001000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00001000 */
4928 #define ADC_CDR2_RDATA_ALT_13          (0x00002000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00002000 */
4929 #define ADC_CDR2_RDATA_ALT_14          (0x00004000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00004000 */
4930 #define ADC_CDR2_RDATA_ALT_15          (0x00008000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00008000 */
4931 #define ADC_CDR2_RDATA_ALT_16          (0x00010000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00010000 */
4932 #define ADC_CDR2_RDATA_ALT_17          (0x00020000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00020000 */
4933 #define ADC_CDR2_RDATA_ALT_18          (0x00040000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00040000 */
4934 #define ADC_CDR2_RDATA_ALT_19          (0x00080000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00080000 */
4935 #define ADC_CDR2_RDATA_ALT_20          (0x00100000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00100000 */
4936 #define ADC_CDR2_RDATA_ALT_21          (0x00200000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00200000 */
4937 #define ADC_CDR2_RDATA_ALT_22          (0x00400000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00400000 */
4938 #define ADC_CDR2_RDATA_ALT_23          (0x00800000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00800000 */
4939 #define ADC_CDR2_RDATA_ALT_24          (0x01000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x01000000 */
4940 #define ADC_CDR2_RDATA_ALT_25          (0x02000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x02000000 */
4941 #define ADC_CDR2_RDATA_ALT_26          (0x04000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x04000000 */
4942 #define ADC_CDR2_RDATA_ALT_27          (0x08000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x08000000 */
4943 #define ADC_CDR2_RDATA_ALT_28          (0x10000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x10000000 */
4944 #define ADC_CDR2_RDATA_ALT_29          (0x20000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x20000000 */
4945 #define ADC_CDR2_RDATA_ALT_30          (0x40000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */
4946 #define ADC_CDR2_RDATA_ALT_31          (0x80000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */
4947 
4948 /******************************************************************************/
4949 /*                                                                            */
4950 /*                                   VREFBUF                                  */
4951 /*                                                                            */
4952 /******************************************************************************/
4953 /*******************  Bit definition for VREFBUF_CSR register  ****************/
4954 #define VREFBUF_CSR_ENVR_Pos        (0U)
4955 #define VREFBUF_CSR_ENVR_Msk        (0x1U << VREFBUF_CSR_ENVR_Pos)             /*!< 0x00000001 */
4956 #define VREFBUF_CSR_ENVR            VREFBUF_CSR_ENVR_Msk                       /*!<Voltage reference buffer enable */
4957 #define VREFBUF_CSR_HIZ_Pos         (1U)
4958 #define VREFBUF_CSR_HIZ_Msk         (0x1U << VREFBUF_CSR_HIZ_Pos)              /*!< 0x00000002 */
4959 #define VREFBUF_CSR_HIZ             VREFBUF_CSR_HIZ_Msk                        /*!<High impedance mode             */
4960 #define VREFBUF_CSR_VRR_Pos         (3U)
4961 #define VREFBUF_CSR_VRR_Msk         (0x1U << VREFBUF_CSR_VRR_Pos)              /*!< 0x00000008 */
4962 #define VREFBUF_CSR_VRR             VREFBUF_CSR_VRR_Msk                        /*!<Voltage reference buffer ready  */
4963 #define VREFBUF_CSR_VRS_Pos         (4U)
4964 #define VREFBUF_CSR_VRS_Msk         (0x7U << VREFBUF_CSR_VRS_Pos)              /*!< 0x00000070 */
4965 #define VREFBUF_CSR_VRS             VREFBUF_CSR_VRS_Msk                        /*!<Voltage reference scale         */
4966 
4967 #define VREFBUF_CSR_VRS_OUT1        ((uint32_t)0x00000000)                     /*!<Voltage reference VREF_OUT1     */
4968 #define VREFBUF_CSR_VRS_OUT2_Pos    (4U)
4969 #define VREFBUF_CSR_VRS_OUT2_Msk    (0x1U << VREFBUF_CSR_VRS_OUT2_Pos)         /*!< 0x00000010 */
4970 #define VREFBUF_CSR_VRS_OUT2        VREFBUF_CSR_VRS_OUT2_Msk                   /*!<Voltage reference VREF_OUT2     */
4971 #define VREFBUF_CSR_VRS_OUT3_Pos    (5U)
4972 #define VREFBUF_CSR_VRS_OUT3_Msk    (0x1U << VREFBUF_CSR_VRS_OUT3_Pos)         /*!< 0x00000020 */
4973 #define VREFBUF_CSR_VRS_OUT3        VREFBUF_CSR_VRS_OUT3_Msk                   /*!<Voltage reference VREF_OUT3     */
4974 #define VREFBUF_CSR_VRS_OUT4_Pos    (4U)
4975 #define VREFBUF_CSR_VRS_OUT4_Msk    (0x3U << VREFBUF_CSR_VRS_OUT4_Pos)         /*!< 0x00000030 */
4976 #define VREFBUF_CSR_VRS_OUT4        VREFBUF_CSR_VRS_OUT4_Msk                   /*!<Voltage reference VREF_OUT4     */
4977 
4978 /*******************  Bit definition for VREFBUF_CCR register  ****************/
4979 #define VREFBUF_CCR_TRIM_Pos        (0U)
4980 #define VREFBUF_CCR_TRIM_Msk        (0x3FU << VREFBUF_CCR_TRIM_Pos)            /*!< 0x0000003F */
4981 #define VREFBUF_CCR_TRIM            VREFBUF_CCR_TRIM_Msk                       /*!<TRIM[5:0] bits (Trimming code)  */
4982 
4983 /******************************************************************************/
4984 /*                                                                            */
4985 /*                 Flexible Datarate Controller Area Network                  */
4986 /*                                                                            */
4987 /******************************************************************************/
4988 /*!<FDCAN control and status registers */
4989 /*****************  Bit definition for FDCAN_CREL register  *******************/
4990 #define FDCAN_CREL_DAY_Pos        (0U)
4991 #define FDCAN_CREL_DAY_Msk        (0xFFU << FDCAN_CREL_DAY_Pos)                /*!< 0x000000FF */
4992 #define FDCAN_CREL_DAY            FDCAN_CREL_DAY_Msk                           /*!<Timestamp Day                           */
4993 #define FDCAN_CREL_MON_Pos        (8U)
4994 #define FDCAN_CREL_MON_Msk        (0xFFU << FDCAN_CREL_MON_Pos)                /*!< 0x0000FF00 */
4995 #define FDCAN_CREL_MON            FDCAN_CREL_MON_Msk                           /*!<Timestamp Month                         */
4996 #define FDCAN_CREL_YEAR_Pos       (16U)
4997 #define FDCAN_CREL_YEAR_Msk       (0xFU << FDCAN_CREL_YEAR_Pos)                /*!< 0x000F0000 */
4998 #define FDCAN_CREL_YEAR           FDCAN_CREL_YEAR_Msk                          /*!<Timestamp Year                          */
4999 #define FDCAN_CREL_SUBSTEP_Pos    (20U)
5000 #define FDCAN_CREL_SUBSTEP_Msk    (0xFU << FDCAN_CREL_SUBSTEP_Pos)             /*!< 0x00F00000 */
5001 #define FDCAN_CREL_SUBSTEP        FDCAN_CREL_SUBSTEP_Msk                       /*!<Sub-step of Core release                */
5002 #define FDCAN_CREL_STEP_Pos       (24U)
5003 #define FDCAN_CREL_STEP_Msk       (0xFU << FDCAN_CREL_STEP_Pos)                /*!< 0x0F000000 */
5004 #define FDCAN_CREL_STEP           FDCAN_CREL_STEP_Msk                          /*!<Step of Core release                    */
5005 #define FDCAN_CREL_REL_Pos        (28U)
5006 #define FDCAN_CREL_REL_Msk        (0xFU << FDCAN_CREL_REL_Pos)                 /*!< 0xF0000000 */
5007 #define FDCAN_CREL_REL            FDCAN_CREL_REL_Msk                           /*!<Core release                            */
5008 
5009 /*****************  Bit definition for FDCAN_ENDN register  *******************/
5010 #define FDCAN_ENDN_ETV_Pos        (0U)
5011 #define FDCAN_ENDN_ETV_Msk        (0xFFFFFFFFU << FDCAN_ENDN_ETV_Pos)          /*!< 0xFFFFFFFF */
5012 #define FDCAN_ENDN_ETV            FDCAN_ENDN_ETV_Msk                           /*!<TEndiannes Test Value                   */
5013 
5014 /*****************  Bit definition for FDCAN_DBTP register  *******************/
5015 #define FDCAN_DBTP_DSJW_Pos       (0U)
5016 #define FDCAN_DBTP_DSJW_Msk       (0xFU << FDCAN_DBTP_DSJW_Pos)                /*!< 0x0000000F */
5017 #define FDCAN_DBTP_DSJW           FDCAN_DBTP_DSJW_Msk                          /*!<Synchronization Jump Width              */
5018 #define FDCAN_DBTP_DTSEG2_Pos     (4U)
5019 #define FDCAN_DBTP_DTSEG2_Msk     (0xFU << FDCAN_DBTP_DTSEG2_Pos)              /*!< 0x000000F0 */
5020 #define FDCAN_DBTP_DTSEG2         FDCAN_DBTP_DTSEG2_Msk                        /*!<Data time segment after sample point    */
5021 #define FDCAN_DBTP_DTSEG1_Pos     (8U)
5022 #define FDCAN_DBTP_DTSEG1_Msk     (0x1FU << FDCAN_DBTP_DTSEG1_Pos)              /*!< 0x00001F00 */
5023 #define FDCAN_DBTP_DTSEG1         FDCAN_DBTP_DTSEG1_Msk                        /*!<Data time segment before sample point   */
5024 #define FDCAN_DBTP_DBRP_Pos       (16U)
5025 #define FDCAN_DBTP_DBRP_Msk       (0x1FU << FDCAN_DBTP_DBRP_Pos)               /*!< 0x001F0000 */
5026 #define FDCAN_DBTP_DBRP           FDCAN_DBTP_DBRP_Msk                          /*!<Data BIt Rate Prescaler                 */
5027 #define FDCAN_DBTP_TDC_Pos        (23U)
5028 #define FDCAN_DBTP_TDC_Msk        (0x1U << FDCAN_DBTP_TDC_Pos)                 /*!< 0x00800000 */
5029 #define FDCAN_DBTP_TDC            FDCAN_DBTP_TDC_Msk                           /*!<Transceiver Delay Compensation          */
5030 
5031 /*****************  Bit definition for FDCAN_TEST register  *******************/
5032 #define FDCAN_TEST_LBCK_Pos       (4U)
5033 #define FDCAN_TEST_LBCK_Msk       (0x1U << FDCAN_TEST_LBCK_Pos)                /*!< 0x00000010 */
5034 #define FDCAN_TEST_LBCK           FDCAN_TEST_LBCK_Msk                          /*!<Loop Back mode                           */
5035 #define FDCAN_TEST_TX_Pos         (5U)
5036 #define FDCAN_TEST_TX_Msk         (0x3U << FDCAN_TEST_TX_Pos)                  /*!< 0x00000060 */
5037 #define FDCAN_TEST_TX             FDCAN_TEST_TX_Msk                            /*!<Control of Transmit Pin                  */
5038 #define FDCAN_TEST_RX_Pos         (7U)
5039 #define FDCAN_TEST_RX_Msk         (0x1U << FDCAN_TEST_RX_Pos)                  /*!< 0x00000080 */
5040 #define FDCAN_TEST_RX             FDCAN_TEST_RX_Msk                            /*!<Receive Pin                              */
5041 
5042 /*****************  Bit definition for FDCAN_RWD register  ********************/
5043 #define FDCAN_RWD_WDC_Pos         (0U)
5044 #define FDCAN_RWD_WDC_Msk         (0xFFU << FDCAN_RWD_WDC_Pos)                  /*!< 0x000000FF */
5045 #define FDCAN_RWD_WDC             FDCAN_RWD_WDC_Msk                            /*!<Watchdog configuration                   */
5046 #define FDCAN_RWD_WDV_Pos         (8U)
5047 #define FDCAN_RWD_WDV_Msk         (0xFFU << FDCAN_RWD_WDV_Pos)                  /*!< 0x0000FF00 */
5048 #define FDCAN_RWD_WDV             FDCAN_RWD_WDV_Msk                            /*!<Watchdog value                           */
5049 
5050 /*****************  Bit definition for FDCAN_CCCR register  ********************/
5051 #define FDCAN_CCCR_INIT_Pos       (0U)
5052 #define FDCAN_CCCR_INIT_Msk       (0x1U << FDCAN_CCCR_INIT_Pos)                /*!< 0x00000001 */
5053 #define FDCAN_CCCR_INIT           FDCAN_CCCR_INIT_Msk                          /*!<Initialization                           */
5054 #define FDCAN_CCCR_CCE_Pos        (1U)
5055 #define FDCAN_CCCR_CCE_Msk        (0x1U << FDCAN_CCCR_CCE_Pos)                 /*!< 0x00000002 */
5056 #define FDCAN_CCCR_CCE            FDCAN_CCCR_CCE_Msk                           /*!<Configuration Change Enable              */
5057 #define FDCAN_CCCR_ASM_Pos        (2U)
5058 #define FDCAN_CCCR_ASM_Msk        (0x1U << FDCAN_CCCR_ASM_Pos)                 /*!< 0x00000004 */
5059 #define FDCAN_CCCR_ASM            FDCAN_CCCR_ASM_Msk                           /*!<ASM Restricted Operation Mode            */
5060 #define FDCAN_CCCR_CSA_Pos        (3U)
5061 #define FDCAN_CCCR_CSA_Msk        (0x1U << FDCAN_CCCR_CSA_Pos)                 /*!< 0x00000008 */
5062 #define FDCAN_CCCR_CSA            FDCAN_CCCR_CSA_Msk                           /*!<Clock Stop Acknowledge                   */
5063 #define FDCAN_CCCR_CSR_Pos        (4U)
5064 #define FDCAN_CCCR_CSR_Msk        (0x1U << FDCAN_CCCR_CSR_Pos)                 /*!< 0x00000010 */
5065 #define FDCAN_CCCR_CSR            FDCAN_CCCR_CSR_Msk                           /*!<Clock Stop Request                       */
5066 #define FDCAN_CCCR_MON_Pos        (5U)
5067 #define FDCAN_CCCR_MON_Msk        (0x1U << FDCAN_CCCR_MON_Pos)                 /*!< 0x00000020 */
5068 #define FDCAN_CCCR_MON            FDCAN_CCCR_MON_Msk                           /*!<Bus Monitoring Mode                      */
5069 #define FDCAN_CCCR_DAR_Pos        (6U)
5070 #define FDCAN_CCCR_DAR_Msk        (0x1U << FDCAN_CCCR_DAR_Pos)                 /*!< 0x00000040 */
5071 #define FDCAN_CCCR_DAR            FDCAN_CCCR_DAR_Msk                           /*!<Disable Automatic Retransmission         */
5072 #define FDCAN_CCCR_TEST_Pos       (7U)
5073 #define FDCAN_CCCR_TEST_Msk       (0x1U << FDCAN_CCCR_TEST_Pos)                /*!< 0x00000080 */
5074 #define FDCAN_CCCR_TEST           FDCAN_CCCR_TEST_Msk                          /*!<Test Mode Enable                         */
5075 #define FDCAN_CCCR_FDOE_Pos       (8U)
5076 #define FDCAN_CCCR_FDOE_Msk       (0x1U << FDCAN_CCCR_FDOE_Pos)                /*!< 0x00000100 */
5077 #define FDCAN_CCCR_FDOE           FDCAN_CCCR_FDOE_Msk                          /*!<FD Operation Enable                      */
5078 #define FDCAN_CCCR_BRSE_Pos       (9U)
5079 #define FDCAN_CCCR_BRSE_Msk       (0x1U << FDCAN_CCCR_BRSE_Pos)                /*!< 0x00000200 */
5080 #define FDCAN_CCCR_BRSE           FDCAN_CCCR_BRSE_Msk                          /*!<FDCAN Bit Rate Switching                 */
5081 #define FDCAN_CCCR_PXHD_Pos       (12U)
5082 #define FDCAN_CCCR_PXHD_Msk       (0x1U << FDCAN_CCCR_PXHD_Pos)                /*!< 0x00001000 */
5083 #define FDCAN_CCCR_PXHD           FDCAN_CCCR_PXHD_Msk                          /*!<Protocol Exception Handling Disable      */
5084 #define FDCAN_CCCR_EFBI_Pos       (13U)
5085 #define FDCAN_CCCR_EFBI_Msk       (0x1U << FDCAN_CCCR_EFBI_Pos)                /*!< 0x00002000 */
5086 #define FDCAN_CCCR_EFBI           FDCAN_CCCR_EFBI_Msk                          /*!<Edge Filtering during Bus Integration    */
5087 #define FDCAN_CCCR_TXP_Pos        (14U)
5088 #define FDCAN_CCCR_TXP_Msk        (0x1U << FDCAN_CCCR_TXP_Pos)                 /*!< 0x00004000 */
5089 #define FDCAN_CCCR_TXP            FDCAN_CCCR_TXP_Msk                           /*!<Two CAN bit times Pause                  */
5090 #define FDCAN_CCCR_NISO_Pos       (15U)
5091 #define FDCAN_CCCR_NISO_Msk       (0x1U << FDCAN_CCCR_NISO_Pos)                /*!< 0x00008000 */
5092 #define FDCAN_CCCR_NISO           FDCAN_CCCR_NISO_Msk                          /*!<Non ISO Operation                        */
5093 
5094 /*****************  Bit definition for FDCAN_NBTP register  ********************/
5095 #define FDCAN_NBTP_NTSEG2_Pos     (0U)
5096 #define FDCAN_NBTP_NTSEG2_Msk     (0x7FU << FDCAN_NBTP_NTSEG2_Pos)             /*!< 0x0000007F */
5097 #define FDCAN_NBTP_NTSEG2         FDCAN_NBTP_NTSEG2_Msk                        /*!<Nominal Time segment after sample point  */
5098 #define FDCAN_NBTP_NTSEG1_Pos     (8U)
5099 #define FDCAN_NBTP_NTSEG1_Msk     (0xFFU << FDCAN_NBTP_NTSEG1_Pos)             /*!< 0x0000FF00 */
5100 #define FDCAN_NBTP_NTSEG1         FDCAN_NBTP_NTSEG1_Msk                        /*!<Nominal Time segment before sample point */
5101 #define FDCAN_NBTP_NBRP_Pos       (16U)
5102 #define FDCAN_NBTP_NBRP_Msk       (0x1FFU << FDCAN_NBTP_NBRP_Pos)              /*!< 0x01FF0000 */
5103 #define FDCAN_NBTP_NBRP           FDCAN_NBTP_NBRP_Msk                          /*!<Bit Rate Prescaler                       */
5104 #define FDCAN_NBTP_NSJW_Pos       (25U)
5105 #define FDCAN_NBTP_NSJW_Msk       (0x7FU << FDCAN_NBTP_NSJW_Pos)               /*!< 0xFE000000 */
5106 #define FDCAN_NBTP_NSJW           FDCAN_NBTP_NSJW_Msk                          /*!<Nominal (Re)Synchronization Jump Width   */
5107 
5108 /*****************  Bit definition for FDCAN_TSCC register  ********************/
5109 #define FDCAN_TSCC_TSS_Pos        (0U)
5110 #define FDCAN_TSCC_TSS_Msk        (0x3U << FDCAN_TSCC_TSS_Pos)                 /*!< 0x00000003 */
5111 #define FDCAN_TSCC_TSS            FDCAN_TSCC_TSS_Msk                           /*!<Timestamp Select                         */
5112 #define FDCAN_TSCC_TCP_Pos        (16U)
5113 #define FDCAN_TSCC_TCP_Msk        (0xFU << FDCAN_TSCC_TCP_Pos)                 /*!< 0x000F0000 */
5114 #define FDCAN_TSCC_TCP            FDCAN_TSCC_TCP_Msk                           /*!<Timestamp Counter Prescaler              */
5115 
5116 /*****************  Bit definition for FDCAN_TSCV register  ********************/
5117 #define FDCAN_TSCV_TSC_Pos        (0U)
5118 #define FDCAN_TSCV_TSC_Msk        (0xFFFFU << FDCAN_TSCV_TSC_Pos)              /*!< 0x0000FFFF */
5119 #define FDCAN_TSCV_TSC            FDCAN_TSCV_TSC_Msk                           /*!<Timestamp Counter                        */
5120 
5121 /*****************  Bit definition for FDCAN_TOCC register  ********************/
5122 #define FDCAN_TOCC_ETOC_Pos       (0U)
5123 #define FDCAN_TOCC_ETOC_Msk       (0x1U << FDCAN_TOCC_ETOC_Pos)                /*!< 0x00000001 */
5124 #define FDCAN_TOCC_ETOC           FDCAN_TOCC_ETOC_Msk                          /*!<Enable Timeout Counter                   */
5125 #define FDCAN_TOCC_TOS_Pos        (1U)
5126 #define FDCAN_TOCC_TOS_Msk        (0x3U << FDCAN_TOCC_TOS_Pos)                 /*!< 0x00000006 */
5127 #define FDCAN_TOCC_TOS            FDCAN_TOCC_TOS_Msk                           /*!<Timeout Select                           */
5128 #define FDCAN_TOCC_TOP_Pos        (16U)
5129 #define FDCAN_TOCC_TOP_Msk        (0xFFFFU << FDCAN_TOCC_TOP_Pos)              /*!< 0xFFFF0000 */
5130 #define FDCAN_TOCC_TOP            FDCAN_TOCC_TOP_Msk                           /*!<Timeout Period                           */
5131 
5132 /*****************  Bit definition for FDCAN_TOCV register  ********************/
5133 #define FDCAN_TOCV_TOC_Pos        (0U)
5134 #define FDCAN_TOCV_TOC_Msk        (0xFFFFU << FDCAN_TOCV_TOC_Pos)              /*!< 0x0000FFFF */
5135 #define FDCAN_TOCV_TOC            FDCAN_TOCV_TOC_Msk                           /*!<Timeout Counter                          */
5136 
5137 /*****************  Bit definition for FDCAN_ECR register  *********************/
5138 #define FDCAN_ECR_TEC_Pos         (0U)
5139 #define FDCAN_ECR_TEC_Msk         (0xFFU << FDCAN_ECR_TEC_Pos)                 /*!< 0x0000000F */
5140 #define FDCAN_ECR_TEC             FDCAN_ECR_TEC_Msk                            /*!<Transmit Error Counter                   */
5141 #define FDCAN_ECR_REC_Pos         (8U)
5142 #define FDCAN_ECR_REC_Msk         (0x7FU << FDCAN_ECR_REC_Pos)                 /*!< 0x00007F00 */
5143 #define FDCAN_ECR_REC             FDCAN_ECR_REC_Msk                            /*!<Receive Error Counter                    */
5144 #define FDCAN_ECR_RP_Pos          (15U)
5145 #define FDCAN_ECR_RP_Msk          (0x1U << FDCAN_ECR_RP_Pos)                   /*!< 0x00008000 */
5146 #define FDCAN_ECR_RP              FDCAN_ECR_RP_Msk                             /*!<Receive Error Passive                    */
5147 #define FDCAN_ECR_CEL_Pos         (16U)
5148 #define FDCAN_ECR_CEL_Msk         (0xFFU << FDCAN_ECR_CEL_Pos)                 /*!< 0x00FF0000 */
5149 #define FDCAN_ECR_CEL             FDCAN_ECR_CEL_Msk                            /*!<CAN Error Logging                        */
5150 
5151 /*****************  Bit definition for FDCAN_PSR register  *********************/
5152 #define FDCAN_PSR_LEC_Pos         (0U)
5153 #define FDCAN_PSR_LEC_Msk         (0x7U << FDCAN_PSR_LEC_Pos)                  /*!< 0x00000007 */
5154 #define FDCAN_PSR_LEC             FDCAN_PSR_LEC_Msk                            /*!<Last Error Code                          */
5155 #define FDCAN_PSR_ACT_Pos         (3U)
5156 #define FDCAN_PSR_ACT_Msk         (0x3U << FDCAN_PSR_ACT_Pos)                  /*!< 0x00000018 */
5157 #define FDCAN_PSR_ACT             FDCAN_PSR_ACT_Msk                            /*!<Activity                                 */
5158 #define FDCAN_PSR_EP_Pos          (5U)
5159 #define FDCAN_PSR_EP_Msk          (0x1U << FDCAN_PSR_EP_Pos)                   /*!< 0x00000020 */
5160 #define FDCAN_PSR_EP              FDCAN_PSR_EP_Msk                             /*!<Error Passive                            */
5161 #define FDCAN_PSR_EW_Pos          (6U)
5162 #define FDCAN_PSR_EW_Msk          (0x1U << FDCAN_PSR_EW_Pos)                   /*!< 0x00000040 */
5163 #define FDCAN_PSR_EW              FDCAN_PSR_EW_Msk                             /*!<Warning Status                           */
5164 #define FDCAN_PSR_BO_Pos          (7U)
5165 #define FDCAN_PSR_BO_Msk          (0x1U << FDCAN_PSR_BO_Pos)                   /*!< 0x00000080 */
5166 #define FDCAN_PSR_BO              FDCAN_PSR_BO_Msk                             /*!<Bus_Off Status                           */
5167 #define FDCAN_PSR_DLEC_Pos        (8U)
5168 #define FDCAN_PSR_DLEC_Msk        (0x7U << FDCAN_PSR_DLEC_Pos)                 /*!< 0x00000700 */
5169 #define FDCAN_PSR_DLEC            FDCAN_PSR_DLEC_Msk                           /*!<Data Last Error Code                     */
5170 #define FDCAN_PSR_RESI_Pos        (11U)
5171 #define FDCAN_PSR_RESI_Msk        (0x1U << FDCAN_PSR_RESI_Pos)                 /*!< 0x00000800 */
5172 #define FDCAN_PSR_RESI            FDCAN_PSR_RESI_Msk                           /*!<ESI flag of last received FDCAN Message  */
5173 #define FDCAN_PSR_RBRS_Pos        (12U)
5174 #define FDCAN_PSR_RBRS_Msk        (0x1U << FDCAN_PSR_RBRS_Pos)                 /*!< 0x00001000 */
5175 #define FDCAN_PSR_RBRS            FDCAN_PSR_RBRS_Msk                           /*!<BRS flag of last received FDCAN Message  */
5176 #define FDCAN_PSR_REDL_Pos        (13U)
5177 #define FDCAN_PSR_REDL_Msk        (0x1U << FDCAN_PSR_REDL_Pos)                 /*!< 0x00002000 */
5178 #define FDCAN_PSR_REDL            FDCAN_PSR_REDL_Msk                           /*!<Received FDCAN Message                   */
5179 #define FDCAN_PSR_PXE_Pos         (14U)
5180 #define FDCAN_PSR_PXE_Msk         (0x1U << FDCAN_PSR_PXE_Pos)                  /*!< 0x00004000 */
5181 #define FDCAN_PSR_PXE             FDCAN_PSR_PXE_Msk                            /*!<Protocol Exception Event                 */
5182 #define FDCAN_PSR_TDCV_Pos        (16U)
5183 #define FDCAN_PSR_TDCV_Msk        (0x7FU << FDCAN_PSR_TDCV_Pos)                /*!< 0x007F0000 */
5184 #define FDCAN_PSR_TDCV            FDCAN_PSR_TDCV_Msk                           /*!<Transmitter Delay Compensation Value     */
5185 
5186 /*****************  Bit definition for FDCAN_TDCR register  ********************/
5187 #define FDCAN_TDCR_TDCF_Pos       (0U)
5188 #define FDCAN_TDCR_TDCF_Msk       (0x7FU << FDCAN_TDCR_TDCF_Pos)               /*!< 0x0000007F */
5189 #define FDCAN_TDCR_TDCF           FDCAN_TDCR_TDCF_Msk                          /*!<Transmitter Delay Compensation Filter    */
5190 #define FDCAN_TDCR_TDCO_Pos       (8U)
5191 #define FDCAN_TDCR_TDCO_Msk       (0x7FU << FDCAN_TDCR_TDCO_Pos)               /*!< 0x00007F00 */
5192 #define FDCAN_TDCR_TDCO           FDCAN_TDCR_TDCO_Msk                          /*!<Transmitter Delay Compensation Offset    */
5193 
5194 /*****************  Bit definition for FDCAN_IR register  **********************/
5195 #define FDCAN_IR_RF0N_Pos         (0U)
5196 #define FDCAN_IR_RF0N_Msk         (0x1U << FDCAN_IR_RF0N_Pos)                  /*!< 0x00000001 */
5197 #define FDCAN_IR_RF0N             FDCAN_IR_RF0N_Msk                            /*!<Rx FIFO 0 New Message                    */
5198 #define FDCAN_IR_RF0W_Pos         (1U)
5199 #define FDCAN_IR_RF0W_Msk         (0x1U << FDCAN_IR_RF0W_Pos)                  /*!< 0x00000002 */
5200 #define FDCAN_IR_RF0W             FDCAN_IR_RF0W_Msk                            /*!<Rx FIFO 0 Watermark Reached              */
5201 #define FDCAN_IR_RF0F_Pos         (2U)
5202 #define FDCAN_IR_RF0F_Msk         (0x1U << FDCAN_IR_RF0F_Pos)                  /*!< 0x00000004 */
5203 #define FDCAN_IR_RF0F             FDCAN_IR_RF0F_Msk                            /*!<Rx FIFO 0 Full                           */
5204 #define FDCAN_IR_RF0L_Pos         (3U)
5205 #define FDCAN_IR_RF0L_Msk         (0x1U << FDCAN_IR_RF0L_Pos)                  /*!< 0x00000008 */
5206 #define FDCAN_IR_RF0L             FDCAN_IR_RF0L_Msk                            /*!<Rx FIFO 0 Message Lost                   */
5207 #define FDCAN_IR_RF1N_Pos         (4U)
5208 #define FDCAN_IR_RF1N_Msk         (0x1U << FDCAN_IR_RF1N_Pos)                  /*!< 0x00000010 */
5209 #define FDCAN_IR_RF1N             FDCAN_IR_RF1N_Msk                            /*!<Rx FIFO 1 New Message                    */
5210 #define FDCAN_IR_RF1W_Pos         (5U)
5211 #define FDCAN_IR_RF1W_Msk         (0x1U << FDCAN_IR_RF1W_Pos)                  /*!< 0x00000020 */
5212 #define FDCAN_IR_RF1W             FDCAN_IR_RF1W_Msk                            /*!<Rx FIFO 1 Watermark Reached              */
5213 #define FDCAN_IR_RF1F_Pos         (6U)
5214 #define FDCAN_IR_RF1F_Msk         (0x1U << FDCAN_IR_RF1F_Pos)                  /*!< 0x00000040 */
5215 #define FDCAN_IR_RF1F             FDCAN_IR_RF1F_Msk                            /*!<Rx FIFO 1 Full                           */
5216 #define FDCAN_IR_RF1L_Pos         (7U)
5217 #define FDCAN_IR_RF1L_Msk         (0x1U << FDCAN_IR_RF1L_Pos)                  /*!< 0x00000080 */
5218 #define FDCAN_IR_RF1L             FDCAN_IR_RF1L_Msk                            /*!<Rx FIFO 1 Message Lost                   */
5219 #define FDCAN_IR_HPM_Pos          (8U)
5220 #define FDCAN_IR_HPM_Msk          (0x1U << FDCAN_IR_HPM_Pos)                   /*!< 0x00000100 */
5221 #define FDCAN_IR_HPM              FDCAN_IR_HPM_Msk                             /*!<High Priority Message                    */
5222 #define FDCAN_IR_TC_Pos           (9U)
5223 #define FDCAN_IR_TC_Msk           (0x1U << FDCAN_IR_TC_Pos)                    /*!< 0x00000200 */
5224 #define FDCAN_IR_TC               FDCAN_IR_TC_Msk                              /*!<Transmission Completed                   */
5225 #define FDCAN_IR_TCF_Pos          (10U)
5226 #define FDCAN_IR_TCF_Msk          (0x1U << FDCAN_IR_TCF_Pos)                   /*!< 0x00000400 */
5227 #define FDCAN_IR_TCF              FDCAN_IR_TCF_Msk                             /*!<Transmission Cancellation Finished       */
5228 #define FDCAN_IR_TFE_Pos          (11U)
5229 #define FDCAN_IR_TFE_Msk          (0x1U << FDCAN_IR_TFE_Pos)                   /*!< 0x00000800 */
5230 #define FDCAN_IR_TFE              FDCAN_IR_TFE_Msk                             /*!<Tx FIFO Empty                            */
5231 #define FDCAN_IR_TEFN_Pos         (12U)
5232 #define FDCAN_IR_TEFN_Msk         (0x1U << FDCAN_IR_TEFN_Pos)                  /*!< 0x00001000 */
5233 #define FDCAN_IR_TEFN             FDCAN_IR_TEFN_Msk                            /*!<Tx Event FIFO New Entry                  */
5234 #define FDCAN_IR_TEFW_Pos         (13U)
5235 #define FDCAN_IR_TEFW_Msk         (0x1U << FDCAN_IR_TEFW_Pos)                  /*!< 0x00002000 */
5236 #define FDCAN_IR_TEFW             FDCAN_IR_TEFW_Msk                            /*!<Tx Event FIFO Watermark Reached          */
5237 #define FDCAN_IR_TEFF_Pos         (14U)
5238 #define FDCAN_IR_TEFF_Msk         (0x1U << FDCAN_IR_TEFF_Pos)                  /*!< 0x00004000 */
5239 #define FDCAN_IR_TEFF             FDCAN_IR_TEFF_Msk                            /*!<Tx Event FIFO Full                       */
5240 #define FDCAN_IR_TEFL_Pos         (15U)
5241 #define FDCAN_IR_TEFL_Msk         (0x1U << FDCAN_IR_TEFL_Pos)                  /*!< 0x00008000 */
5242 #define FDCAN_IR_TEFL             FDCAN_IR_TEFL_Msk                            /*!<Tx Event FIFO Element Lost               */
5243 #define FDCAN_IR_TSW_Pos          (16U)
5244 #define FDCAN_IR_TSW_Msk          (0x1U << FDCAN_IR_TSW_Pos)                   /*!< 0x00010000 */
5245 #define FDCAN_IR_TSW              FDCAN_IR_TSW_Msk                             /*!<Timestamp Wraparound                     */
5246 #define FDCAN_IR_MRAF_Pos         (17U)
5247 #define FDCAN_IR_MRAF_Msk         (0x1U << FDCAN_IR_MRAF_Pos)                  /*!< 0x00020000 */
5248 #define FDCAN_IR_MRAF             FDCAN_IR_MRAF_Msk                            /*!<Message RAM Access Failure               */
5249 #define FDCAN_IR_TOO_Pos          (18U)
5250 #define FDCAN_IR_TOO_Msk          (0x1U << FDCAN_IR_TOO_Pos)                   /*!< 0x00040000 */
5251 #define FDCAN_IR_TOO              FDCAN_IR_TOO_Msk                             /*!<Timeout Occurred                         */
5252 #define FDCAN_IR_DRX_Pos          (19U)
5253 #define FDCAN_IR_DRX_Msk          (0x1U << FDCAN_IR_DRX_Pos)                   /*!< 0x00080000 */
5254 #define FDCAN_IR_DRX              FDCAN_IR_DRX_Msk                             /*!<Message stored to Dedicated Rx Buffer    */
5255 #define FDCAN_IR_ELO_Pos          (22U)
5256 #define FDCAN_IR_ELO_Msk          (0x1U << FDCAN_IR_ELO_Pos)                   /*!< 0x00400000 */
5257 #define FDCAN_IR_ELO              FDCAN_IR_ELO_Msk                             /*!<Error Logging Overflow                   */
5258 #define FDCAN_IR_EP_Pos           (23U)
5259 #define FDCAN_IR_EP_Msk           (0x1U << FDCAN_IR_EP_Pos)                    /*!< 0x00800000 */
5260 #define FDCAN_IR_EP               FDCAN_IR_EP_Msk                              /*!<Error Passive                            */
5261 #define FDCAN_IR_EW_Pos           (24U)
5262 #define FDCAN_IR_EW_Msk           (0x1U << FDCAN_IR_EW_Pos)                    /*!< 0x01000000 */
5263 #define FDCAN_IR_EW               FDCAN_IR_EW_Msk                              /*!<Warning Status                           */
5264 #define FDCAN_IR_BO_Pos           (25U)
5265 #define FDCAN_IR_BO_Msk           (0x1U << FDCAN_IR_BO_Pos)                    /*!< 0x02000000 */
5266 #define FDCAN_IR_BO               FDCAN_IR_BO_Msk                              /*!<Bus_Off Status                           */
5267 #define FDCAN_IR_WDI_Pos          (26U)
5268 #define FDCAN_IR_WDI_Msk          (0x1U << FDCAN_IR_WDI_Pos)                   /*!< 0x04000000 */
5269 #define FDCAN_IR_WDI              FDCAN_IR_WDI_Msk                             /*!<Watchdog Interrupt                       */
5270 #define FDCAN_IR_PEA_Pos          (27U)
5271 #define FDCAN_IR_PEA_Msk          (0x1U << FDCAN_IR_PEA_Pos)                   /*!< 0x08000000 */
5272 #define FDCAN_IR_PEA              FDCAN_IR_PEA_Msk                             /*!<Protocol Error in Arbitration Phase      */
5273 #define FDCAN_IR_PED_Pos          (28U)
5274 #define FDCAN_IR_PED_Msk          (0x1U << FDCAN_IR_PED_Pos)                   /*!< 0x10000000 */
5275 #define FDCAN_IR_PED              FDCAN_IR_PED_Msk                             /*!<Protocol Error in Data Phase             */
5276 #define FDCAN_IR_ARA_Pos          (29U)
5277 #define FDCAN_IR_ARA_Msk          (0x1U << FDCAN_IR_ARA_Pos)                   /*!< 0x20000000 */
5278 #define FDCAN_IR_ARA              FDCAN_IR_ARA_Msk                             /*!<Access to Reserved Address               */
5279 
5280 /*****************  Bit definition for FDCAN_IE register  **********************/
5281 #define FDCAN_IE_RF0NE_Pos        (0U)
5282 #define FDCAN_IE_RF0NE_Msk        (0x1U << FDCAN_IE_RF0NE_Pos)                 /*!< 0x00000001 */
5283 #define FDCAN_IE_RF0NE            FDCAN_IE_RF0NE_Msk                           /*!<Rx FIFO 0 New Message Enable                 */
5284 #define FDCAN_IE_RF0WE_Pos        (1U)
5285 #define FDCAN_IE_RF0WE_Msk        (0x1U << FDCAN_IE_RF0WE_Pos)                 /*!< 0x00000002 */
5286 #define FDCAN_IE_RF0WE            FDCAN_IE_RF0WE_Msk                           /*!<Rx FIFO 0 Watermark Reached Enable           */
5287 #define FDCAN_IE_RF0FE_Pos        (2U)
5288 #define FDCAN_IE_RF0FE_Msk        (0x1U << FDCAN_IE_RF0FE_Pos)                 /*!< 0x00000004 */
5289 #define FDCAN_IE_RF0FE            FDCAN_IE_RF0FE_Msk                           /*!<Rx FIFO 0 Full Enable                        */
5290 #define FDCAN_IE_RF0LE_Pos        (3U)
5291 #define FDCAN_IE_RF0LE_Msk        (0x1U << FDCAN_IE_RF0LE_Pos)                 /*!< 0x00000008 */
5292 #define FDCAN_IE_RF0LE            FDCAN_IE_RF0LE_Msk                           /*!<Rx FIFO 0 Message Lost Enable                */
5293 #define FDCAN_IE_RF1NE_Pos        (4U)
5294 #define FDCAN_IE_RF1NE_Msk        (0x1U << FDCAN_IE_RF1NE_Pos)                 /*!< 0x00000010 */
5295 #define FDCAN_IE_RF1NE            FDCAN_IE_RF1NE_Msk                           /*!<Rx FIFO 1 New Message Enable                 */
5296 #define FDCAN_IE_RF1WE_Pos        (5U)
5297 #define FDCAN_IE_RF1WE_Msk        (0x1U << FDCAN_IE_RF1WE_Pos)                 /*!< 0x00000020 */
5298 #define FDCAN_IE_RF1WE            FDCAN_IE_RF1WE_Msk                           /*!<Rx FIFO 1 Watermark Reached Enable           */
5299 #define FDCAN_IE_RF1FE_Pos        (6U)
5300 #define FDCAN_IE_RF1FE_Msk        (0x1U << FDCAN_IE_RF1FE_Pos)                 /*!< 0x00000040 */
5301 #define FDCAN_IE_RF1FE            FDCAN_IE_RF1FE_Msk                           /*!<Rx FIFO 1 Full Enable                        */
5302 #define FDCAN_IE_RF1LE_Pos        (7U)
5303 #define FDCAN_IE_RF1LE_Msk        (0x1U << FDCAN_IE_RF1LE_Pos)                 /*!< 0x00000080 */
5304 #define FDCAN_IE_RF1LE            FDCAN_IE_RF1LE_Msk                           /*!<Rx FIFO 1 Message Lost Enable                */
5305 #define FDCAN_IE_HPME_Pos         (8U)
5306 #define FDCAN_IE_HPME_Msk         (0x1U << FDCAN_IE_HPME_Pos)                  /*!< 0x00000100 */
5307 #define FDCAN_IE_HPME             FDCAN_IE_HPME_Msk                            /*!<High Priority Message Enable                 */
5308 #define FDCAN_IE_TCE_Pos          (9U)
5309 #define FDCAN_IE_TCE_Msk          (0x1U << FDCAN_IE_TCE_Pos)                   /*!< 0x00000200 */
5310 #define FDCAN_IE_TCE              FDCAN_IE_TCE_Msk                             /*!<Transmission Completed Enable                */
5311 #define FDCAN_IE_TCFE_Pos         (10U)
5312 #define FDCAN_IE_TCFE_Msk         (0x1U << FDCAN_IE_TCFE_Pos)                  /*!< 0x00000400 */
5313 #define FDCAN_IE_TCFE             FDCAN_IE_TCFE_Msk                            /*!<Transmission Cancellation Finished Enable    */
5314 #define FDCAN_IE_TFEE_Pos         (11U)
5315 #define FDCAN_IE_TFEE_Msk         (0x1U << FDCAN_IE_TFEE_Pos)                  /*!< 0x00000800 */
5316 #define FDCAN_IE_TFEE             FDCAN_IE_TFEE_Msk                            /*!<Tx FIFO Empty Enable                         */
5317 #define FDCAN_IE_TEFNE_Pos        (12U)
5318 #define FDCAN_IE_TEFNE_Msk        (0x1U << FDCAN_IE_TEFNE_Pos)                 /*!< 0x00001000 */
5319 #define FDCAN_IE_TEFNE            FDCAN_IE_TEFNE_Msk                           /*!<Tx Event FIFO New Entry Enable               */
5320 #define FDCAN_IE_TEFWE_Pos        (13U)
5321 #define FDCAN_IE_TEFWE_Msk        (0x1U << FDCAN_IE_TEFWE_Pos)                 /*!< 0x00002000 */
5322 #define FDCAN_IE_TEFWE            FDCAN_IE_TEFWE_Msk                           /*!<Tx Event FIFO Watermark Reached Enable       */
5323 #define FDCAN_IE_TEFFE_Pos        (14U)
5324 #define FDCAN_IE_TEFFE_Msk        (0x1U << FDCAN_IE_TEFFE_Pos)                 /*!< 0x00004000 */
5325 #define FDCAN_IE_TEFFE            FDCAN_IE_TEFFE_Msk                           /*!<Tx Event FIFO Full Enable                    */
5326 #define FDCAN_IE_TEFLE_Pos        (15U)
5327 #define FDCAN_IE_TEFLE_Msk        (0x1U << FDCAN_IE_TEFLE_Pos)                 /*!< 0x00008000 */
5328 #define FDCAN_IE_TEFLE            FDCAN_IE_TEFLE_Msk                           /*!<Tx Event FIFO Element Lost Enable            */
5329 #define FDCAN_IE_TSWE_Pos         (16U)
5330 #define FDCAN_IE_TSWE_Msk         (0x1U << FDCAN_IE_TSWE_Pos)                  /*!< 0x00010000 */
5331 #define FDCAN_IE_TSWE             FDCAN_IE_TSWE_Msk                            /*!<Timestamp Wraparound Enable                  */
5332 #define FDCAN_IE_MRAFE_Pos        (17U)
5333 #define FDCAN_IE_MRAFE_Msk        (0x1U << FDCAN_IE_MRAFE_Pos)                 /*!< 0x00020000 */
5334 #define FDCAN_IE_MRAFE            FDCAN_IE_MRAFE_Msk                           /*!<Message RAM Access Failure Enable            */
5335 #define FDCAN_IE_TOOE_Pos         (18U)
5336 #define FDCAN_IE_TOOE_Msk         (0x1U << FDCAN_IE_TOOE_Pos)                  /*!< 0x00040000 */
5337 #define FDCAN_IE_TOOE             FDCAN_IE_TOOE_Msk                            /*!<Timeout Occurred Enable                      */
5338 #define FDCAN_IE_DRXE_Pos         (19U)
5339 #define FDCAN_IE_DRXE_Msk         (0x1U << FDCAN_IE_DRXE_Pos)                  /*!< 0x00080000 */
5340 #define FDCAN_IE_DRXE             FDCAN_IE_DRXE_Msk                            /*!<Message stored to Dedicated Rx Buffer Enable */
5341 #define FDCAN_IE_ELOE_Pos         (22U)
5342 #define FDCAN_IE_ELOE_Msk         (0x1U << FDCAN_IE_ELOE_Pos)                  /*!< 0x00400000 */
5343 #define FDCAN_IE_ELOE             FDCAN_IE_ELOE_Msk                            /*!<Error Logging Overflow Enable                */
5344 #define FDCAN_IE_EPE_Pos          (23U)
5345 #define FDCAN_IE_EPE_Msk          (0x1U << FDCAN_IE_EPE_Pos)                   /*!< 0x00800000 */
5346 #define FDCAN_IE_EPE              FDCAN_IE_EPE_Msk                             /*!<Error Passive Enable                         */
5347 #define FDCAN_IE_EWE_Pos          (24U)
5348 #define FDCAN_IE_EWE_Msk          (0x1U << FDCAN_IE_EWE_Pos)                   /*!< 0x01000000 */
5349 #define FDCAN_IE_EWE              FDCAN_IE_EWE_Msk                             /*!<Warning Status Enable                        */
5350 #define FDCAN_IE_BOE_Pos          (25U)
5351 #define FDCAN_IE_BOE_Msk          (0x1U << FDCAN_IE_BOE_Pos)                   /*!< 0x02000000 */
5352 #define FDCAN_IE_BOE              FDCAN_IE_BOE_Msk                             /*!<Bus_Off Status Enable                        */
5353 #define FDCAN_IE_WDIE_Pos         (26U)
5354 #define FDCAN_IE_WDIE_Msk         (0x1U << FDCAN_IE_WDIE_Pos)                  /*!< 0x04000000 */
5355 #define FDCAN_IE_WDIE             FDCAN_IE_WDIE_Msk                            /*!<Watchdog Interrupt Enable                    */
5356 #define FDCAN_IE_PEAE_Pos         (27U)
5357 #define FDCAN_IE_PEAE_Msk         (0x1U << FDCAN_IE_PEAE_Pos)                  /*!< 0x08000000 */
5358 #define FDCAN_IE_PEAE             FDCAN_IE_PEAE_Msk                            /*!<Protocol Error in Arbitration Phase Enable   */
5359 #define FDCAN_IE_PEDE_Pos         (28U)
5360 #define FDCAN_IE_PEDE_Msk         (0x1U << FDCAN_IE_PEDE_Pos)                  /*!< 0x10000000 */
5361 #define FDCAN_IE_PEDE             FDCAN_IE_PEDE_Msk                            /*!<Protocol Error in Data Phase Enable          */
5362 #define FDCAN_IE_ARAE_Pos         (29U)
5363 #define FDCAN_IE_ARAE_Msk         (0x1U << FDCAN_IE_ARAE_Pos)                  /*!< 0x20000000 */
5364 #define FDCAN_IE_ARAE             FDCAN_IE_ARAE_Msk                            /*!<Access to Reserved Address Enable            */
5365 
5366 /*****************  Bit definition for FDCAN_ILS register  **********************/
5367 #define FDCAN_ILS_RF0NL_Pos       (0U)
5368 #define FDCAN_ILS_RF0NL_Msk       (0x1U << FDCAN_ILS_RF0NL_Pos)                /*!< 0x00000001 */
5369 #define FDCAN_ILS_RF0NL           FDCAN_ILS_RF0NL_Msk                          /*!<Rx FIFO 0 New Message Line                  */
5370 #define FDCAN_ILS_RF0WL_Pos       (1U)
5371 #define FDCAN_ILS_RF0WL_Msk       (0x1U << FDCAN_ILS_RF0WL_Pos)                /*!< 0x00000002 */
5372 #define FDCAN_ILS_RF0WL           FDCAN_ILS_RF0WL_Msk                          /*!<Rx FIFO 0 Watermark Reached Line            */
5373 #define FDCAN_ILS_RF0FL_Pos       (2U)
5374 #define FDCAN_ILS_RF0FL_Msk       (0x1U << FDCAN_ILS_RF0FL_Pos)                /*!< 0x00000004 */
5375 #define FDCAN_ILS_RF0FL           FDCAN_ILS_RF0FL_Msk                          /*!<Rx FIFO 0 Full Line                         */
5376 #define FDCAN_ILS_RF0LL_Pos       (3U)
5377 #define FDCAN_ILS_RF0LL_Msk       (0x1U << FDCAN_ILS_RF0LL_Pos)                /*!< 0x00000008 */
5378 #define FDCAN_ILS_RF0LL           FDCAN_ILS_RF0LL_Msk                          /*!<Rx FIFO 0 Message Lost Line                 */
5379 #define FDCAN_ILS_RF1NL_Pos       (4U)
5380 #define FDCAN_ILS_RF1NL_Msk       (0x1U << FDCAN_ILS_RF1NL_Pos)                /*!< 0x00000010 */
5381 #define FDCAN_ILS_RF1NL           FDCAN_ILS_RF1NL_Msk                          /*!<Rx FIFO 1 New Message Line                  */
5382 #define FDCAN_ILS_RF1WL_Pos       (5U)
5383 #define FDCAN_ILS_RF1WL_Msk       (0x1U << FDCAN_ILS_RF1WL_Pos)                /*!< 0x00000020 */
5384 #define FDCAN_ILS_RF1WL           FDCAN_ILS_RF1WL_Msk                          /*!<Rx FIFO 1 Watermark Reached Line            */
5385 #define FDCAN_ILS_RF1FL_Pos       (6U)
5386 #define FDCAN_ILS_RF1FL_Msk       (0x1U << FDCAN_ILS_RF1FL_Pos)                /*!< 0x00000040 */
5387 #define FDCAN_ILS_RF1FL           FDCAN_ILS_RF1FL_Msk                          /*!<Rx FIFO 1 Full Line                         */
5388 #define FDCAN_ILS_RF1LL_Pos       (7U)
5389 #define FDCAN_ILS_RF1LL_Msk       (0x1U << FDCAN_ILS_RF1LL_Pos)                /*!< 0x00000080 */
5390 #define FDCAN_ILS_RF1LL           FDCAN_ILS_RF1LL_Msk                          /*!<Rx FIFO 1 Message Lost Line                 */
5391 #define FDCAN_ILS_HPML_Pos        (8U)
5392 #define FDCAN_ILS_HPML_Msk        (0x1U << FDCAN_ILS_HPML_Pos)                 /*!< 0x00000100 */
5393 #define FDCAN_ILS_HPML            FDCAN_ILS_HPML_Msk                           /*!<High Priority Message Line                  */
5394 #define FDCAN_ILS_TCL_Pos         (9U)
5395 #define FDCAN_ILS_TCL_Msk         (0x1U << FDCAN_ILS_TCL_Pos)                  /*!< 0x00000200 */
5396 #define FDCAN_ILS_TCL             FDCAN_ILS_TCL_Msk                            /*!<Transmission Completed Line                 */
5397 #define FDCAN_ILS_TCFL_Pos        (10U)
5398 #define FDCAN_ILS_TCFL_Msk        (0x1U << FDCAN_ILS_TCFL_Pos)                 /*!< 0x00000400 */
5399 #define FDCAN_ILS_TCFL            FDCAN_ILS_TCFL_Msk                           /*!<Transmission Cancellation Finished Line     */
5400 #define FDCAN_ILS_TFEL_Pos        (11U)
5401 #define FDCAN_ILS_TFEL_Msk        (0x1U << FDCAN_ILS_TFEL_Pos)                 /*!< 0x00000800 */
5402 #define FDCAN_ILS_TFEL            FDCAN_ILS_TFEL_Msk                           /*!<Tx FIFO Empty Line                          */
5403 #define FDCAN_ILS_TEFNL_Pos       (12U)
5404 #define FDCAN_ILS_TEFNL_Msk       (0x1U << FDCAN_ILS_TEFNL_Pos)                /*!< 0x00001000 */
5405 #define FDCAN_ILS_TEFNL           FDCAN_ILS_TEFNL_Msk                          /*!<Tx Event FIFO New Entry Line                */
5406 #define FDCAN_ILS_TEFWL_Pos       (13U)
5407 #define FDCAN_ILS_TEFWL_Msk       (0x1U << FDCAN_ILS_TEFWL_Pos)                /*!< 0x00002000 */
5408 #define FDCAN_ILS_TEFWL           FDCAN_ILS_TEFWL_Msk                          /*!<Tx Event FIFO Watermark Reached Line        */
5409 #define FDCAN_ILS_TEFFL_Pos       (14U)
5410 #define FDCAN_ILS_TEFFL_Msk       (0x1U << FDCAN_ILS_TEFFL_Pos)                /*!< 0x00004000 */
5411 #define FDCAN_ILS_TEFFL           FDCAN_ILS_TEFFL_Msk                          /*!<Tx Event FIFO Full Line                     */
5412 #define FDCAN_ILS_TEFLL_Pos       (15U)
5413 #define FDCAN_ILS_TEFLL_Msk       (0x1U << FDCAN_ILS_TEFLL_Pos)                /*!< 0x00008000 */
5414 #define FDCAN_ILS_TEFLL           FDCAN_ILS_TEFLL_Msk                          /*!<Tx Event FIFO Element Lost Line             */
5415 #define FDCAN_ILS_TSWL_Pos        (16U)
5416 #define FDCAN_ILS_TSWL_Msk        (0x1U << FDCAN_ILS_TSWL_Pos)                 /*!< 0x00010000 */
5417 #define FDCAN_ILS_TSWL            FDCAN_ILS_TSWL_Msk                           /*!<Timestamp Wraparound Line                   */
5418 #define FDCAN_ILS_MRAFL_Pos       (17U)
5419 #define FDCAN_ILS_MRAFL_Msk       (0x1U << FDCAN_ILS_MRAFL_Pos)                /*!< 0x00020000 */
5420 #define FDCAN_ILS_MRAFL           FDCAN_ILS_MRAFL_Msk                          /*!<Message RAM Access Failure Line             */
5421 #define FDCAN_ILS_TOOL_Pos        (18U)
5422 #define FDCAN_ILS_TOOL_Msk        (0x1U << FDCAN_ILS_TOOL_Pos)                 /*!< 0x00040000 */
5423 #define FDCAN_ILS_TOOL            FDCAN_ILS_TOOL_Msk                           /*!<Timeout Occurred Line                       */
5424 #define FDCAN_ILS_DRXL_Pos        (19U)
5425 #define FDCAN_ILS_DRXL_Msk        (0x1U << FDCAN_ILS_DRXL_Pos)                 /*!< 0x00080000 */
5426 #define FDCAN_ILS_DRXL            FDCAN_ILS_DRXL_Msk                           /*!<Message stored to Dedicated Rx Buffer Line  */
5427 #define FDCAN_ILS_ELOL_Pos        (22U)
5428 #define FDCAN_ILS_ELOL_Msk        (0x1U << FDCAN_ILS_ELOL_Pos)                 /*!< 0x00400000 */
5429 #define FDCAN_ILS_ELOL            FDCAN_ILS_ELOL_Msk                           /*!<Error Logging Overflow Line                 */
5430 #define FDCAN_ILS_EPL_Pos         (23U)
5431 #define FDCAN_ILS_EPL_Msk         (0x1U << FDCAN_ILS_EPL_Pos)                  /*!< 0x00800000 */
5432 #define FDCAN_ILS_EPL             FDCAN_ILS_EPL_Msk                            /*!<Error Passive Line                          */
5433 #define FDCAN_ILS_EWL_Pos         (24U)
5434 #define FDCAN_ILS_EWL_Msk         (0x1U << FDCAN_ILS_EWL_Pos)                  /*!< 0x01000000 */
5435 #define FDCAN_ILS_EWL             FDCAN_ILS_EWL_Msk                            /*!<Warning Status Line                         */
5436 #define FDCAN_ILS_BOL_Pos         (25U)
5437 #define FDCAN_ILS_BOL_Msk         (0x1U << FDCAN_ILS_BOL_Pos)                  /*!< 0x02000000 */
5438 #define FDCAN_ILS_BOL             FDCAN_ILS_BOL_Msk                            /*!<Bus_Off Status Line                         */
5439 #define FDCAN_ILS_WDIL_Pos        (26U)
5440 #define FDCAN_ILS_WDIL_Msk        (0x1U << FDCAN_ILS_WDIL_Pos)                 /*!< 0x04000000 */
5441 #define FDCAN_ILS_WDIL            FDCAN_ILS_WDIL_Msk                           /*!<Watchdog Interrupt Line                     */
5442 #define FDCAN_ILS_PEAL_Pos        (27U)
5443 #define FDCAN_ILS_PEAL_Msk        (0x1U << FDCAN_ILS_PEAL_Pos)                 /*!< 0x08000000 */
5444 #define FDCAN_ILS_PEAL            FDCAN_ILS_PEAL_Msk                           /*!<Protocol Error in Arbitration Phase Line    */
5445 #define FDCAN_ILS_PEDL_Pos        (28U)
5446 #define FDCAN_ILS_PEDL_Msk        (0x1U << FDCAN_ILS_PEDL_Pos)                 /*!< 0x10000000 */
5447 #define FDCAN_ILS_PEDL            FDCAN_ILS_PEDL_Msk                           /*!<Protocol Error in Data Phase Line           */
5448 #define FDCAN_ILS_ARAL_Pos        (29U)
5449 #define FDCAN_ILS_ARAL_Msk        (0x1U << FDCAN_ILS_ARAL_Pos)                 /*!< 0x20000000 */
5450 #define FDCAN_ILS_ARAL            FDCAN_ILS_ARAL_Msk                           /*!<Access to Reserved Address Line             */
5451 
5452 /** @defgroup FDCAN_Interrupt_Group FDCAN interrupt group
5453   * @{
5454   */
5455 #define FDCAN_IT_GROUP_RX_FIFO0          FDCAN_ILS_RF0NL|FDCAN_ILS_RF0FL|FDCAN_ILS_RF0LL|FDCAN_ILS_RF0WL
5456 															/*!< RX FIFO 0 Interrupts Group:
5457                                                                   RF0LL: Rx FIFO 0 Message Lost
5458                                                                   RF0FL: Rx FIFO 0 is Full
5459                                                                   RF0NL: Rx FIFO 0 Has New Message            */
5460 #define FDCAN_IT_GROUP_RX_FIFO1          FDCAN_ILS_RF1NL|FDCAN_ILS_RF1FL|FDCAN_ILS_RF1LL|FDCAN_ILS_RF1WL
5461 															/*!< RX FIFO 1 Interrupts Group:
5462                                                                   RF1LL: Rx FIFO 1 Message Lost
5463                                                                   RF1FL: Rx FIFO 1 is Full
5464                                                                   RF1NL: Rx FIFO 1 Has New Message            */
5465 #define FDCAN_IT_GROUP_SMSG              FDCAN_ILS_HPML|FDCAN_ILS_TCL|FDCAN_ILS_TCFL
5466 															/*!< Status Message Interrupts Group:
5467                                                                   TCFL: Transmission Cancellation Finished
5468                                                                   TCL: Transmission Completed
5469                                                                   HPML: High Priority Message                 */
5470 #define FDCAN_IT_GROUP_TX_FIFO_ERROR     FDCAN_ILS_TFEL|FDCAN_ILS_TEFNL|FDCAN_ILS_TEFWL|FDCAN_ILS_TEFLL
5471 															/*!< TX FIFO Error Interrupts Group:
5472                                                                   TEFLL: Tx Event FIFO Element Lost
5473                                                                   TEFFL: Tx Event FIFO Full
5474                                                                   TEFNL: Tx Event FIFO New Entry
5475                                                                   TFEL: Tx FIFO Empty Interrupt Line          */
5476 #define FDCAN_IT_GROUP_MISC              FDCAN_ILS_TSWL|FDCAN_ILS_MRAFL|FDCAN_ILS_TOOL|FDCAN_ILS_DRXL
5477 															/*!< Misc. Interrupts Group:
5478                                                                   TOOL: Timeout Occurred
5479                                                                   MRAFL: Message RAM Access Failure
5480                                                                   TSWL: Timestamp Wraparound                  */
5481 #define FDCAN_IT_GROUP_BIT_LINE_ERROR    FDCAN_ILS_ELOL|FDCAN_ILS_EPL
5482 															/*!< Bit and Line Error Interrupts Group:
5483                                                                   EPL: Error Passive
5484                                                                   ELOL: Error Logging Overflow                */
5485 #define FDCAN_IT_GROUP_PROTOCOL_ERROR    FDCAN_ILS_EWL|FDCAN_ILS_BOL|FDCAN_ILS_WDIL|FDCAN_ILS_PEAL|FDCAN_ILS_PEDL|FDCAN_ILS_ARAL
5486 															/*!< Protocol Error Group:
5487                                                                   ARAL: Access to Reserved Address Line
5488                                                                   PEDL: Protocol Error in Data Phase Line
5489                                                                   PEAL: Protocol Error in Arbitration Phase Line
5490                                                                   WDIL: Watchdog Interrupt Line
5491                                                                   BOL: Bus_Off Status
5492                                                                   EWL: Warning Status                         */
5493 /**
5494   * @}
5495   */
5496 
5497 /*****************  Bit definition for FDCAN_ILE register  **********************/
5498 #define FDCAN_ILE_EINT0_Pos       (0U)
5499 #define FDCAN_ILE_EINT0_Msk       (0x1U << FDCAN_ILE_EINT0_Pos)                /*!< 0x00000001 */
5500 #define FDCAN_ILE_EINT0           FDCAN_ILE_EINT0_Msk                          /*!<Enable Interrupt Line 0                   */
5501 #define FDCAN_ILE_EINT1_Pos       (1U)
5502 #define FDCAN_ILE_EINT1_Msk       (0x1U << FDCAN_ILE_EINT1_Pos)                /*!< 0x00000002 */
5503 #define FDCAN_ILE_EINT1           FDCAN_ILE_EINT1_Msk                          /*!<Enable Interrupt Line 1                   */
5504 
5505 /*****************  Bit definition for FDCAN_GFC register  **********************/
5506 #define FDCAN_GFC_RRFE_Pos        (0U)
5507 #define FDCAN_GFC_RRFE_Msk        (0x1U << FDCAN_GFC_RRFE_Pos)                 /*!< 0x00000001 */
5508 #define FDCAN_GFC_RRFE            FDCAN_GFC_RRFE_Msk                           /*!<Reject Remote Frames Extended             */
5509 #define FDCAN_GFC_RRFS_Pos        (1U)
5510 #define FDCAN_GFC_RRFS_Msk        (0x1U << FDCAN_GFC_RRFS_Pos)                 /*!< 0x00000002 */
5511 #define FDCAN_GFC_RRFS            FDCAN_GFC_RRFS_Msk                           /*!<Reject Remote Frames Standard             */
5512 #define FDCAN_GFC_ANFE_Pos        (2U)
5513 #define FDCAN_GFC_ANFE_Msk        (0x3U << FDCAN_GFC_ANFE_Pos)                 /*!< 0x0000000C */
5514 #define FDCAN_GFC_ANFE            FDCAN_GFC_ANFE_Msk                           /*!<Accept Non-matching Frames Extended       */
5515 #define FDCAN_GFC_ANFS_Pos        (4U)
5516 #define FDCAN_GFC_ANFS_Msk        (0x3U << FDCAN_GFC_ANFS_Pos)                 /*!< 0x00000030 */
5517 #define FDCAN_GFC_ANFS            FDCAN_GFC_ANFS_Msk                           /*!<Accept Non-matching Frames Standard       */
5518 
5519 /*****************  Bit definition for FDCAN_SIDFC register  ********************/
5520 #define FDCAN_SIDFC_FLSSA_Pos     (2U)
5521 #define FDCAN_SIDFC_FLSSA_Msk     (0x3FFFU << FDCAN_SIDFC_FLSSA_Pos)           /*!< 0x0000FFFC */
5522 #define FDCAN_SIDFC_FLSSA         FDCAN_SIDFC_FLSSA_Msk                        /*!<Filter List Standard Start Address        */
5523 #define FDCAN_SIDFC_LSS_Pos       (16U)
5524 #define FDCAN_SIDFC_LSS_Msk       (0xFFU << FDCAN_SIDFC_LSS_Pos)               /*!< 0x00FF0000 */
5525 #define FDCAN_SIDFC_LSS           FDCAN_SIDFC_LSS_Msk                          /*!<List Size Standard                        */
5526 
5527 /*****************  Bit definition for FDCAN_XIDFC register  ********************/
5528 #define FDCAN_XIDFC_FLESA_Pos     (2U)
5529 #define FDCAN_XIDFC_FLESA_Msk     (0x3FFFU << FDCAN_XIDFC_FLESA_Pos)           /*!< 0x0000FFFC */
5530 #define FDCAN_XIDFC_FLESA         FDCAN_XIDFC_FLESA_Msk                        /*!<Filter List Standard Start Address        */
5531 #define FDCAN_XIDFC_LSE_Pos       (16U)
5532 #define FDCAN_XIDFC_LSE_Msk       (0xFFU << FDCAN_XIDFC_LSE_Pos)               /*!< 0x00FF0000 */
5533 #define FDCAN_XIDFC_LSE           FDCAN_XIDFC_LSE_Msk                          /*!<List Size Extended                        */
5534 
5535 /*****************  Bit definition for FDCAN_XIDAM register  ********************/
5536 #define FDCAN_XIDAM_EIDM_Pos      (0U)
5537 #define FDCAN_XIDAM_EIDM_Msk      (0x1FFFFFFFU << FDCAN_XIDAM_EIDM_Pos)        /*!< 0x1FFFFFFF */
5538 #define FDCAN_XIDAM_EIDM          FDCAN_XIDAM_EIDM_Msk                         /*!<Extended ID Mask                          */
5539 
5540 /*****************  Bit definition for FDCAN_HPMS register  *********************/
5541 #define FDCAN_HPMS_BIDX_Pos       (0U)
5542 #define FDCAN_HPMS_BIDX_Msk       (0x3FU << FDCAN_HPMS_BIDX_Pos)               /*!< 0x0000003F */
5543 #define FDCAN_HPMS_BIDX           FDCAN_HPMS_BIDX_Msk                          /*!<Buffer Index                              */
5544 #define FDCAN_HPMS_MSI_Pos        (6U)
5545 #define FDCAN_HPMS_MSI_Msk        (0x3U << FDCAN_HPMS_MSI_Pos)                 /*!< 0x000000C0 */
5546 #define FDCAN_HPMS_MSI            FDCAN_HPMS_MSI_Msk                           /*!<Message Storage Indicator                 */
5547 #define FDCAN_HPMS_FIDX_Pos       (8U)
5548 #define FDCAN_HPMS_FIDX_Msk       (0x7FU << FDCAN_HPMS_FIDX_Pos)               /*!< 0x00007F00 */
5549 #define FDCAN_HPMS_FIDX           FDCAN_HPMS_FIDX_Msk                          /*!<Filter Index                              */
5550 #define FDCAN_HPMS_FLST_Pos       (15U)
5551 #define FDCAN_HPMS_FLST_Msk       (0x1U << FDCAN_HPMS_FLST_Pos)                /*!< 0x00008000 */
5552 #define FDCAN_HPMS_FLST           FDCAN_HPMS_FLST_Msk                          /*!<Filter List                               */
5553 
5554 /*****************  Bit definition for FDCAN_NDAT1 register  ********************/
5555 #define FDCAN_NDAT1_ND0_Pos       (0U)
5556 #define FDCAN_NDAT1_ND0_Msk       (0x1U << FDCAN_NDAT1_ND0_Pos)                /*!< 0x00000001 */
5557 #define FDCAN_NDAT1_ND0           FDCAN_NDAT1_ND0_Msk                          /*!<New Data flag of Rx Buffer 0              */
5558 #define FDCAN_NDAT1_ND1_Pos       (1U)
5559 #define FDCAN_NDAT1_ND1_Msk       (0x1U << FDCAN_NDAT1_ND1_Pos)                /*!< 0x00000002 */
5560 #define FDCAN_NDAT1_ND1           FDCAN_NDAT1_ND1_Msk                          /*!<New Data flag of Rx Buffer 1              */
5561 #define FDCAN_NDAT1_ND2_Pos       (2U)
5562 #define FDCAN_NDAT1_ND2_Msk       (0x1U << FDCAN_NDAT1_ND2_Pos)                /*!< 0x00000004 */
5563 #define FDCAN_NDAT1_ND2           FDCAN_NDAT1_ND2_Msk                          /*!<New Data flag of Rx Buffer 2              */
5564 #define FDCAN_NDAT1_ND3_Pos       (3U)
5565 #define FDCAN_NDAT1_ND3_Msk       (0x1U << FDCAN_NDAT1_ND3_Pos)                /*!< 0x00000008 */
5566 #define FDCAN_NDAT1_ND3           FDCAN_NDAT1_ND3_Msk                          /*!<New Data flag of Rx Buffer 3              */
5567 #define FDCAN_NDAT1_ND4_Pos       (4U)
5568 #define FDCAN_NDAT1_ND4_Msk       (0x1U << FDCAN_NDAT1_ND4_Pos)                /*!< 0x00000010 */
5569 #define FDCAN_NDAT1_ND4           FDCAN_NDAT1_ND4_Msk                          /*!<New Data flag of Rx Buffer 4              */
5570 #define FDCAN_NDAT1_ND5_Pos       (5U)
5571 #define FDCAN_NDAT1_ND5_Msk       (0x1U << FDCAN_NDAT1_ND5_Pos)                /*!< 0x00000020 */
5572 #define FDCAN_NDAT1_ND5           FDCAN_NDAT1_ND5_Msk                          /*!<New Data flag of Rx Buffer 5              */
5573 #define FDCAN_NDAT1_ND6_Pos       (6U)
5574 #define FDCAN_NDAT1_ND6_Msk       (0x1U << FDCAN_NDAT1_ND6_Pos)                /*!< 0x00000040 */
5575 #define FDCAN_NDAT1_ND6           FDCAN_NDAT1_ND6_Msk                          /*!<New Data flag of Rx Buffer 6              */
5576 #define FDCAN_NDAT1_ND7_Pos       (7U)
5577 #define FDCAN_NDAT1_ND7_Msk       (0x1U << FDCAN_NDAT1_ND7_Pos)                /*!< 0x00000080 */
5578 #define FDCAN_NDAT1_ND7           FDCAN_NDAT1_ND7_Msk                          /*!<New Data flag of Rx Buffer 7              */
5579 #define FDCAN_NDAT1_ND8_Pos       (8U)
5580 #define FDCAN_NDAT1_ND8_Msk       (0x1U << FDCAN_NDAT1_ND8_Pos)                /*!< 0x00000100 */
5581 #define FDCAN_NDAT1_ND8           FDCAN_NDAT1_ND8_Msk                          /*!<New Data flag of Rx Buffer 8              */
5582 #define FDCAN_NDAT1_ND9_Pos       (9U)
5583 #define FDCAN_NDAT1_ND9_Msk       (0x1U << FDCAN_NDAT1_ND9_Pos)                /*!< 0x00000200 */
5584 #define FDCAN_NDAT1_ND9           FDCAN_NDAT1_ND9_Msk                          /*!<New Data flag of Rx Buffer 9              */
5585 #define FDCAN_NDAT1_ND10_Pos      (10U)
5586 #define FDCAN_NDAT1_ND10_Msk      (0x1U << FDCAN_NDAT1_ND10_Pos)               /*!< 0x00000400 */
5587 #define FDCAN_NDAT1_ND10          FDCAN_NDAT1_ND10_Msk                         /*!<New Data flag of Rx Buffer 10             */
5588 #define FDCAN_NDAT1_ND11_Pos      (11U)
5589 #define FDCAN_NDAT1_ND11_Msk      (0x1U << FDCAN_NDAT1_ND11_Pos)               /*!< 0x00000800 */
5590 #define FDCAN_NDAT1_ND11          FDCAN_NDAT1_ND11_Msk                         /*!<New Data flag of Rx Buffer 11             */
5591 #define FDCAN_NDAT1_ND12_Pos      (12U)
5592 #define FDCAN_NDAT1_ND12_Msk      (0x1U << FDCAN_NDAT1_ND12_Pos)               /*!< 0x00001000 */
5593 #define FDCAN_NDAT1_ND12          FDCAN_NDAT1_ND12_Msk                         /*!<New Data flag of Rx Buffer 12             */
5594 #define FDCAN_NDAT1_ND13_Pos      (13U)
5595 #define FDCAN_NDAT1_ND13_Msk      (0x1U << FDCAN_NDAT1_ND13_Pos)               /*!< 0x00002000 */
5596 #define FDCAN_NDAT1_ND13          FDCAN_NDAT1_ND13_Msk                         /*!<New Data flag of Rx Buffer 13             */
5597 #define FDCAN_NDAT1_ND14_Pos      (14U)
5598 #define FDCAN_NDAT1_ND14_Msk      (0x1U << FDCAN_NDAT1_ND14_Pos)               /*!< 0x00004000 */
5599 #define FDCAN_NDAT1_ND14          FDCAN_NDAT1_ND14_Msk                         /*!<New Data flag of Rx Buffer 14             */
5600 #define FDCAN_NDAT1_ND15_Pos      (15U)
5601 #define FDCAN_NDAT1_ND15_Msk      (0x1U << FDCAN_NDAT1_ND15_Pos)               /*!< 0x00008000 */
5602 #define FDCAN_NDAT1_ND15          FDCAN_NDAT1_ND15_Msk                         /*!<New Data flag of Rx Buffer 15             */
5603 #define FDCAN_NDAT1_ND16_Pos      (16U)
5604 #define FDCAN_NDAT1_ND16_Msk      (0x1U << FDCAN_NDAT1_ND16_Pos)               /*!< 0x00010000 */
5605 #define FDCAN_NDAT1_ND16          FDCAN_NDAT1_ND16_Msk                         /*!<New Data flag of Rx Buffer 16             */
5606 #define FDCAN_NDAT1_ND17_Pos      (17U)
5607 #define FDCAN_NDAT1_ND17_Msk      (0x1U << FDCAN_NDAT1_ND17_Pos)               /*!< 0x00020000 */
5608 #define FDCAN_NDAT1_ND17          FDCAN_NDAT1_ND17_Msk                         /*!<New Data flag of Rx Buffer 17             */
5609 #define FDCAN_NDAT1_ND18_Pos      (18U)
5610 #define FDCAN_NDAT1_ND18_Msk      (0x1U << FDCAN_NDAT1_ND18_Pos)               /*!< 0x00040000 */
5611 #define FDCAN_NDAT1_ND18          FDCAN_NDAT1_ND18_Msk                         /*!<New Data flag of Rx Buffer 18             */
5612 #define FDCAN_NDAT1_ND19_Pos      (19U)
5613 #define FDCAN_NDAT1_ND19_Msk      (0x1U << FDCAN_NDAT1_ND19_Pos)               /*!< 0x00080000 */
5614 #define FDCAN_NDAT1_ND19          FDCAN_NDAT1_ND19_Msk                         /*!<New Data flag of Rx Buffer 19             */
5615 #define FDCAN_NDAT1_ND20_Pos      (20U)
5616 #define FDCAN_NDAT1_ND20_Msk      (0x1U << FDCAN_NDAT1_ND20_Pos)               /*!< 0x00100000 */
5617 #define FDCAN_NDAT1_ND20          FDCAN_NDAT1_ND20_Msk                         /*!<New Data flag of Rx Buffer 20             */
5618 #define FDCAN_NDAT1_ND21_Pos      (21U)
5619 #define FDCAN_NDAT1_ND21_Msk      (0x1U << FDCAN_NDAT1_ND21_Pos)               /*!< 0x00200000 */
5620 #define FDCAN_NDAT1_ND21          FDCAN_NDAT1_ND21_Msk                         /*!<New Data flag of Rx Buffer 21             */
5621 #define FDCAN_NDAT1_ND22_Pos      (22U)
5622 #define FDCAN_NDAT1_ND22_Msk      (0x1U << FDCAN_NDAT1_ND22_Pos)               /*!< 0x00400000 */
5623 #define FDCAN_NDAT1_ND22          FDCAN_NDAT1_ND22_Msk                         /*!<New Data flag of Rx Buffer 22             */
5624 #define FDCAN_NDAT1_ND23_Pos      (23U)
5625 #define FDCAN_NDAT1_ND23_Msk      (0x1U << FDCAN_NDAT1_ND23_Pos)               /*!< 0x00800000 */
5626 #define FDCAN_NDAT1_ND23          FDCAN_NDAT1_ND23_Msk                         /*!<New Data flag of Rx Buffer 23             */
5627 #define FDCAN_NDAT1_ND24_Pos      (24U)
5628 #define FDCAN_NDAT1_ND24_Msk      (0x1U << FDCAN_NDAT1_ND24_Pos)               /*!< 0x01000000 */
5629 #define FDCAN_NDAT1_ND24          FDCAN_NDAT1_ND24_Msk                         /*!<New Data flag of Rx Buffer 24             */
5630 #define FDCAN_NDAT1_ND25_Pos      (25U)
5631 #define FDCAN_NDAT1_ND25_Msk      (0x1U << FDCAN_NDAT1_ND25_Pos)               /*!< 0x02000000 */
5632 #define FDCAN_NDAT1_ND25          FDCAN_NDAT1_ND25_Msk                         /*!<New Data flag of Rx Buffer 25             */
5633 #define FDCAN_NDAT1_ND26_Pos      (26U)
5634 #define FDCAN_NDAT1_ND26_Msk      (0x1U << FDCAN_NDAT1_ND26_Pos)               /*!< 0x04000000 */
5635 #define FDCAN_NDAT1_ND26          FDCAN_NDAT1_ND26_Msk                         /*!<New Data flag of Rx Buffer 26             */
5636 #define FDCAN_NDAT1_ND27_Pos      (27U)
5637 #define FDCAN_NDAT1_ND27_Msk      (0x1U << FDCAN_NDAT1_ND27_Pos)               /*!< 0x08000000 */
5638 #define FDCAN_NDAT1_ND27          FDCAN_NDAT1_ND27_Msk                         /*!<New Data flag of Rx Buffer 27             */
5639 #define FDCAN_NDAT1_ND28_Pos      (28U)
5640 #define FDCAN_NDAT1_ND28_Msk      (0x1U << FDCAN_NDAT1_ND28_Pos)               /*!< 0x10000000 */
5641 #define FDCAN_NDAT1_ND28          FDCAN_NDAT1_ND28_Msk                         /*!<New Data flag of Rx Buffer 28             */
5642 #define FDCAN_NDAT1_ND29_Pos      (29U)
5643 #define FDCAN_NDAT1_ND29_Msk      (0x1U << FDCAN_NDAT1_ND29_Pos)               /*!< 0x20000000 */
5644 #define FDCAN_NDAT1_ND29          FDCAN_NDAT1_ND29_Msk                         /*!<New Data flag of Rx Buffer 29             */
5645 #define FDCAN_NDAT1_ND30_Pos      (30U)
5646 #define FDCAN_NDAT1_ND30_Msk      (0x1U << FDCAN_NDAT1_ND30_Pos)               /*!< 0x40000000 */
5647 #define FDCAN_NDAT1_ND30          FDCAN_NDAT1_ND30_Msk                         /*!<New Data flag of Rx Buffer 30             */
5648 #define FDCAN_NDAT1_ND31_Pos      (31U)
5649 #define FDCAN_NDAT1_ND31_Msk      (0x1U << FDCAN_NDAT1_ND31_Pos)               /*!< 0x80000000 */
5650 #define FDCAN_NDAT1_ND31          FDCAN_NDAT1_ND31_Msk                         /*!<New Data flag of Rx Buffer 31             */
5651 
5652 /*****************  Bit definition for FDCAN_NDAT2 register  ********************/
5653 #define FDCAN_NDAT2_ND32_Pos      (0U)
5654 #define FDCAN_NDAT2_ND32_Msk      (0x1U << FDCAN_NDAT2_ND32_Pos)               /*!< 0x00000001 */
5655 #define FDCAN_NDAT2_ND32          FDCAN_NDAT2_ND32_Msk                         /*!<New Data flag of Rx Buffer 32             */
5656 #define FDCAN_NDAT2_ND33_Pos      (1U)
5657 #define FDCAN_NDAT2_ND33_Msk      (0x1U << FDCAN_NDAT2_ND33_Pos)               /*!< 0x00000002 */
5658 #define FDCAN_NDAT2_ND33          FDCAN_NDAT2_ND33_Msk                         /*!<New Data flag of Rx Buffer 33             */
5659 #define FDCAN_NDAT2_ND34_Pos      (2U)
5660 #define FDCAN_NDAT2_ND34_Msk      (0x1U << FDCAN_NDAT2_ND34_Pos)               /*!< 0x00000004 */
5661 #define FDCAN_NDAT2_ND34          FDCAN_NDAT2_ND34_Msk                         /*!<New Data flag of Rx Buffer 34             */
5662 #define FDCAN_NDAT2_ND35_Pos      (3U)
5663 #define FDCAN_NDAT2_ND35_Msk      (0x1U << FDCAN_NDAT2_ND35_Pos)               /*!< 0x00000008 */
5664 #define FDCAN_NDAT2_ND35          FDCAN_NDAT2_ND35_Msk                         /*!<New Data flag of Rx Buffer 35             */
5665 #define FDCAN_NDAT2_ND36_Pos      (4U)
5666 #define FDCAN_NDAT2_ND36_Msk      (0x1U << FDCAN_NDAT2_ND36_Pos)               /*!< 0x00000010 */
5667 #define FDCAN_NDAT2_ND36          FDCAN_NDAT2_ND36_Msk                         /*!<New Data flag of Rx Buffer 36             */
5668 #define FDCAN_NDAT2_ND37_Pos      (5U)
5669 #define FDCAN_NDAT2_ND37_Msk      (0x1U << FDCAN_NDAT2_ND37_Pos)               /*!< 0x00000020 */
5670 #define FDCAN_NDAT2_ND37          FDCAN_NDAT2_ND37_Msk                         /*!<New Data flag of Rx Buffer 37             */
5671 #define FDCAN_NDAT2_ND38_Pos      (6U)
5672 #define FDCAN_NDAT2_ND38_Msk      (0x1U << FDCAN_NDAT2_ND38_Pos)               /*!< 0x00000040 */
5673 #define FDCAN_NDAT2_ND38          FDCAN_NDAT2_ND38_Msk                         /*!<New Data flag of Rx Buffer 38             */
5674 #define FDCAN_NDAT2_ND39_Pos      (7U)
5675 #define FDCAN_NDAT2_ND39_Msk      (0x1U << FDCAN_NDAT2_ND39_Pos)               /*!< 0x00000080 */
5676 #define FDCAN_NDAT2_ND39          FDCAN_NDAT2_ND39_Msk                         /*!<New Data flag of Rx Buffer 39             */
5677 #define FDCAN_NDAT2_ND40_Pos      (8U)
5678 #define FDCAN_NDAT2_ND40_Msk      (0x1U << FDCAN_NDAT2_ND40_Pos)               /*!< 0x00000100 */
5679 #define FDCAN_NDAT2_ND40          FDCAN_NDAT2_ND40_Msk                         /*!<New Data flag of Rx Buffer 40             */
5680 #define FDCAN_NDAT2_ND41_Pos      (9U)
5681 #define FDCAN_NDAT2_ND41_Msk      (0x1U << FDCAN_NDAT2_ND41_Pos)               /*!< 0x00000200 */
5682 #define FDCAN_NDAT2_ND41          FDCAN_NDAT2_ND41_Msk                         /*!<New Data flag of Rx Buffer 41             */
5683 #define FDCAN_NDAT2_ND42_Pos      (10U)
5684 #define FDCAN_NDAT2_ND42_Msk      (0x1U << FDCAN_NDAT2_ND42_Pos)               /*!< 0x00000400 */
5685 #define FDCAN_NDAT2_ND42          FDCAN_NDAT2_ND42_Msk                         /*!<New Data flag of Rx Buffer 42             */
5686 #define FDCAN_NDAT2_ND43_Pos      (11U)
5687 #define FDCAN_NDAT2_ND43_Msk      (0x1U << FDCAN_NDAT2_ND43_Pos)               /*!< 0x00000800 */
5688 #define FDCAN_NDAT2_ND43          FDCAN_NDAT2_ND43_Msk                         /*!<New Data flag of Rx Buffer 43             */
5689 #define FDCAN_NDAT2_ND44_Pos      (12U)
5690 #define FDCAN_NDAT2_ND44_Msk      (0x1U << FDCAN_NDAT2_ND44_Pos)               /*!< 0x00001000 */
5691 #define FDCAN_NDAT2_ND44          FDCAN_NDAT2_ND44_Msk                         /*!<New Data flag of Rx Buffer 44             */
5692 #define FDCAN_NDAT2_ND45_Pos      (13U)
5693 #define FDCAN_NDAT2_ND45_Msk      (0x1U << FDCAN_NDAT2_ND45_Pos)               /*!< 0x00002000 */
5694 #define FDCAN_NDAT2_ND45          FDCAN_NDAT2_ND45_Msk                         /*!<New Data flag of Rx Buffer 45             */
5695 #define FDCAN_NDAT2_ND46_Pos      (14U)
5696 #define FDCAN_NDAT2_ND46_Msk      (0x1U << FDCAN_NDAT2_ND46_Pos)               /*!< 0x00004000 */
5697 #define FDCAN_NDAT2_ND46          FDCAN_NDAT2_ND46_Msk                         /*!<New Data flag of Rx Buffer 46             */
5698 #define FDCAN_NDAT2_ND47_Pos      (15U)
5699 #define FDCAN_NDAT2_ND47_Msk      (0x1U << FDCAN_NDAT2_ND47_Pos)               /*!< 0x00008000 */
5700 #define FDCAN_NDAT2_ND47          FDCAN_NDAT2_ND47_Msk                         /*!<New Data flag of Rx Buffer 47             */
5701 #define FDCAN_NDAT2_ND48_Pos      (16U)
5702 #define FDCAN_NDAT2_ND48_Msk      (0x1U << FDCAN_NDAT2_ND48_Pos)               /*!< 0x00010000 */
5703 #define FDCAN_NDAT2_ND48          FDCAN_NDAT2_ND48_Msk                         /*!<New Data flag of Rx Buffer 48             */
5704 #define FDCAN_NDAT2_ND49_Pos      (17U)
5705 #define FDCAN_NDAT2_ND49_Msk      (0x1U << FDCAN_NDAT2_ND49_Pos)               /*!< 0x00020000 */
5706 #define FDCAN_NDAT2_ND49          FDCAN_NDAT2_ND49_Msk                         /*!<New Data flag of Rx Buffer 49             */
5707 #define FDCAN_NDAT2_ND50_Pos      (18U)
5708 #define FDCAN_NDAT2_ND50_Msk      (0x1U << FDCAN_NDAT2_ND50_Pos)               /*!< 0x00040000 */
5709 #define FDCAN_NDAT2_ND50          FDCAN_NDAT2_ND50_Msk                         /*!<New Data flag of Rx Buffer 50             */
5710 #define FDCAN_NDAT2_ND51_Pos      (19U)
5711 #define FDCAN_NDAT2_ND51_Msk      (0x1U << FDCAN_NDAT2_ND51_Pos)               /*!< 0x00080000 */
5712 #define FDCAN_NDAT2_ND51          FDCAN_NDAT2_ND51_Msk                         /*!<New Data flag of Rx Buffer 51             */
5713 #define FDCAN_NDAT2_ND52_Pos      (20U)
5714 #define FDCAN_NDAT2_ND52_Msk      (0x1U << FDCAN_NDAT2_ND52_Pos)               /*!< 0x00100000 */
5715 #define FDCAN_NDAT2_ND52          FDCAN_NDAT2_ND52_Msk                         /*!<New Data flag of Rx Buffer 52             */
5716 #define FDCAN_NDAT2_ND53_Pos      (21U)
5717 #define FDCAN_NDAT2_ND53_Msk      (0x1U << FDCAN_NDAT2_ND53_Pos)               /*!< 0x00200000 */
5718 #define FDCAN_NDAT2_ND53          FDCAN_NDAT2_ND53_Msk                         /*!<New Data flag of Rx Buffer 53             */
5719 #define FDCAN_NDAT2_ND54_Pos      (22U)
5720 #define FDCAN_NDAT2_ND54_Msk      (0x1U << FDCAN_NDAT2_ND54_Pos)               /*!< 0x00400000 */
5721 #define FDCAN_NDAT2_ND54          FDCAN_NDAT2_ND54_Msk                         /*!<New Data flag of Rx Buffer 54             */
5722 #define FDCAN_NDAT2_ND55_Pos      (23U)
5723 #define FDCAN_NDAT2_ND55_Msk      (0x1U << FDCAN_NDAT2_ND55_Pos)               /*!< 0x00800000 */
5724 #define FDCAN_NDAT2_ND55          FDCAN_NDAT2_ND55_Msk                         /*!<New Data flag of Rx Buffer 55             */
5725 #define FDCAN_NDAT2_ND56_Pos      (24U)
5726 #define FDCAN_NDAT2_ND56_Msk      (0x1U << FDCAN_NDAT2_ND56_Pos)               /*!< 0x01000000 */
5727 #define FDCAN_NDAT2_ND56          FDCAN_NDAT2_ND56_Msk                         /*!<New Data flag of Rx Buffer 56             */
5728 #define FDCAN_NDAT2_ND57_Pos      (25U)
5729 #define FDCAN_NDAT2_ND57_Msk      (0x1U << FDCAN_NDAT2_ND57_Pos)               /*!< 0x02000000 */
5730 #define FDCAN_NDAT2_ND57          FDCAN_NDAT2_ND57_Msk                         /*!<New Data flag of Rx Buffer 57             */
5731 #define FDCAN_NDAT2_ND58_Pos      (26U)
5732 #define FDCAN_NDAT2_ND58_Msk      (0x1U << FDCAN_NDAT2_ND58_Pos)               /*!< 0x04000000 */
5733 #define FDCAN_NDAT2_ND58          FDCAN_NDAT2_ND58_Msk                         /*!<New Data flag of Rx Buffer 58             */
5734 #define FDCAN_NDAT2_ND59_Pos      (27U)
5735 #define FDCAN_NDAT2_ND59_Msk      (0x1U << FDCAN_NDAT2_ND59_Pos)               /*!< 0x08000000 */
5736 #define FDCAN_NDAT2_ND59          FDCAN_NDAT2_ND59_Msk                         /*!<New Data flag of Rx Buffer 59             */
5737 #define FDCAN_NDAT2_ND60_Pos      (28U)
5738 #define FDCAN_NDAT2_ND60_Msk      (0x1U << FDCAN_NDAT2_ND60_Pos)               /*!< 0x10000000 */
5739 #define FDCAN_NDAT2_ND60          FDCAN_NDAT2_ND60_Msk                         /*!<New Data flag of Rx Buffer 60             */
5740 #define FDCAN_NDAT2_ND61_Pos      (29U)
5741 #define FDCAN_NDAT2_ND61_Msk      (0x1U << FDCAN_NDAT2_ND61_Pos)               /*!< 0x20000000 */
5742 #define FDCAN_NDAT2_ND61          FDCAN_NDAT2_ND61_Msk                         /*!<New Data flag of Rx Buffer 61             */
5743 #define FDCAN_NDAT2_ND62_Pos      (30U)
5744 #define FDCAN_NDAT2_ND62_Msk      (0x1U << FDCAN_NDAT2_ND62_Pos)               /*!< 0x40000000 */
5745 #define FDCAN_NDAT2_ND62          FDCAN_NDAT2_ND62_Msk                         /*!<New Data flag of Rx Buffer 62             */
5746 #define FDCAN_NDAT2_ND63_Pos      (31U)
5747 #define FDCAN_NDAT2_ND63_Msk      (0x1U << FDCAN_NDAT2_ND63_Pos)               /*!< 0x80000000 */
5748 #define FDCAN_NDAT2_ND63          FDCAN_NDAT2_ND63_Msk                         /*!<New Data flag of Rx Buffer 63             */
5749 
5750 /*****************  Bit definition for FDCAN_RXF0C register  ********************/
5751 #define FDCAN_RXF0C_F0SA_Pos      (2U)
5752 #define FDCAN_RXF0C_F0SA_Msk      (0x3FFFU << FDCAN_RXF0C_F0SA_Pos)            /*!< 0x0000FFFC */
5753 #define FDCAN_RXF0C_F0SA          FDCAN_RXF0C_F0SA_Msk                         /*!<Rx FIFO 0 Start Address                   */
5754 #define FDCAN_RXF0C_F0S_Pos       (16U)
5755 #define FDCAN_RXF0C_F0S_Msk       (0x7FU << FDCAN_RXF0C_F0S_Pos)               /*!< 0x007F0000 */
5756 #define FDCAN_RXF0C_F0S           FDCAN_RXF0C_F0S_Msk                          /*!<Number of Rx FIFO 0 elements              */
5757 #define FDCAN_RXF0C_F0WM_Pos      (24U)
5758 #define FDCAN_RXF0C_F0WM_Msk      (0x7FU << FDCAN_RXF0C_F0WM_Pos)              /*!< 0x7F000000 */
5759 #define FDCAN_RXF0C_F0WM          FDCAN_RXF0C_F0WM_Msk                         /*!<FIFO 0 Watermark                          */
5760 #define FDCAN_RXF0C_F0OM_Pos      (31U)
5761 #define FDCAN_RXF0C_F0OM_Msk      (0x1U << FDCAN_RXF0C_F0OM_Pos)               /*!< 0x80000000 */
5762 #define FDCAN_RXF0C_F0OM          FDCAN_RXF0C_F0OM_Msk                         /*!<FIFO 0 Operation Mode                     */
5763 
5764 /*****************  Bit definition for FDCAN_RXF0S register  ********************/
5765 #define FDCAN_RXF0S_F0FL_Pos      (0U)
5766 #define FDCAN_RXF0S_F0FL_Msk      (0x7FU << FDCAN_RXF0S_F0FL_Pos)              /*!< 0x0000007F */
5767 #define FDCAN_RXF0S_F0FL          FDCAN_RXF0S_F0FL_Msk                         /*!<Rx FIFO 0 Fill Level                      */
5768 #define FDCAN_RXF0S_F0GI_Pos      (8U)
5769 #define FDCAN_RXF0S_F0GI_Msk      (0x3FU << FDCAN_RXF0S_F0GI_Pos)              /*!< 0x00003F00 */
5770 #define FDCAN_RXF0S_F0GI          FDCAN_RXF0S_F0GI_Msk                         /*!<Rx FIFO 0 Get Index                       */
5771 #define FDCAN_RXF0S_F0PI_Pos      (16U)
5772 #define FDCAN_RXF0S_F0PI_Msk      (0x3FU << FDCAN_RXF0S_F0PI_Pos)              /*!< 0x003F0000 */
5773 #define FDCAN_RXF0S_F0PI          FDCAN_RXF0S_F0PI_Msk                         /*!<Rx FIFO 0 Put Index                       */
5774 #define FDCAN_RXF0S_F0F_Pos       (24U)
5775 #define FDCAN_RXF0S_F0F_Msk       (0x1U << FDCAN_RXF0S_F0F_Pos)                /*!< 0x01000000 */
5776 #define FDCAN_RXF0S_F0F           FDCAN_RXF0S_F0F_Msk                          /*!<Rx FIFO 0 Full                            */
5777 #define FDCAN_RXF0S_RF0L_Pos      (25U)
5778 #define FDCAN_RXF0S_RF0L_Msk      (0x1U << FDCAN_RXF0S_RF0L_Pos)               /*!< 0x02000000 */
5779 #define FDCAN_RXF0S_RF0L          FDCAN_RXF0S_RF0L_Msk                         /*!<Rx FIFO 0 Message Lost                    */
5780 
5781 /*****************  Bit definition for FDCAN_RXF0A register  ********************/
5782 #define FDCAN_RXF0A_F0AI_Pos      (0U)
5783 #define FDCAN_RXF0A_F0AI_Msk      (0x3FU << FDCAN_RXF0A_F0AI_Pos)              /*!< 0x0000003F */
5784 #define FDCAN_RXF0A_F0AI          FDCAN_RXF0A_F0AI_Msk                         /*!<Rx FIFO 0 Acknowledge Index               */
5785 
5786 /*****************  Bit definition for FDCAN_RXBC register  ********************/
5787 #define FDCAN_RXBC_RBSA_Pos       (2U)
5788 #define FDCAN_RXBC_RBSA_Msk       (0x3FFFU << FDCAN_RXBC_RBSA_Pos)             /*!< 0x0000FFFC */
5789 #define FDCAN_RXBC_RBSA           FDCAN_RXBC_RBSA_Msk                          /*!<Rx Buffer Start Address                   */
5790 
5791 /*****************  Bit definition for FDCAN_RXF1C register  ********************/
5792 #define FDCAN_RXF1C_F1SA_Pos      (2U)
5793 #define FDCAN_RXF1C_F1SA_Msk      (0x3FFFU << FDCAN_RXF1C_F1SA_Pos)            /*!< 0x0000FFFC */
5794 #define FDCAN_RXF1C_F1SA          FDCAN_RXF1C_F1SA_Msk                         /*!<Rx FIFO 1 Start Address                   */
5795 #define FDCAN_RXF1C_F1S_Pos       (16U)
5796 #define FDCAN_RXF1C_F1S_Msk       (0x7FU << FDCAN_RXF1C_F1S_Pos)               /*!< 0x007F0000 */
5797 #define FDCAN_RXF1C_F1S           FDCAN_RXF1C_F1S_Msk                          /*!<Number of Rx FIFO 1 elements              */
5798 #define FDCAN_RXF1C_F1WM_Pos      (24U)
5799 #define FDCAN_RXF1C_F1WM_Msk      (0x7FU << FDCAN_RXF1C_F1WM_Pos)              /*!< 0x7F000000 */
5800 #define FDCAN_RXF1C_F1WM          FDCAN_RXF1C_F1WM_Msk                         /*!<Rx FIFO 1 Watermark                       */
5801 #define FDCAN_RXF1C_F1OM_Pos      (31U)
5802 #define FDCAN_RXF1C_F1OM_Msk      (0x1U << FDCAN_RXF1C_F1OM_Pos)               /*!< 0x80000000 */
5803 #define FDCAN_RXF1C_F1OM          FDCAN_RXF1C_F1OM_Msk                         /*!<FIFO 1 Operation Mode                     */
5804 
5805 /*****************  Bit definition for FDCAN_RXF1S register  ********************/
5806 #define FDCAN_RXF1S_F1FL_Pos      (0U)
5807 #define FDCAN_RXF1S_F1FL_Msk      (0x7FU << FDCAN_RXF1S_F1FL_Pos)              /*!< 0x0000007F */
5808 #define FDCAN_RXF1S_F1FL          FDCAN_RXF1S_F1FL_Msk                         /*!<Rx FIFO 1 Fill Level                      */
5809 #define FDCAN_RXF1S_F1GI_Pos      (8U)
5810 #define FDCAN_RXF1S_F1GI_Msk      (0x3FU << FDCAN_RXF1S_F1GI_Pos)              /*!< 0x00003F00 */
5811 #define FDCAN_RXF1S_F1GI          FDCAN_RXF1S_F1GI_Msk                         /*!<Rx FIFO 1 Get Index                       */
5812 #define FDCAN_RXF1S_F1PI_Pos      (16U)
5813 #define FDCAN_RXF1S_F1PI_Msk      (0x3FU << FDCAN_RXF1S_F1PI_Pos)              /*!< 0x003F0000 */
5814 #define FDCAN_RXF1S_F1PI          FDCAN_RXF1S_F1PI_Msk                         /*!<Rx FIFO 1 Put Index                       */
5815 #define FDCAN_RXF1S_F1F_Pos       (24U)
5816 #define FDCAN_RXF1S_F1F_Msk       (0x1U << FDCAN_RXF1S_F1F_Pos)                /*!< 0x01000000 */
5817 #define FDCAN_RXF1S_F1F           FDCAN_RXF1S_F1F_Msk                          /*!<Rx FIFO 1 Full                            */
5818 #define FDCAN_RXF1S_RF1L_Pos      (25U)
5819 #define FDCAN_RXF1S_RF1L_Msk      (0x1U << FDCAN_RXF1S_RF1L_Pos)               /*!< 0x02000000 */
5820 #define FDCAN_RXF1S_RF1L          FDCAN_RXF1S_RF1L_Msk                         /*!<Rx FIFO 1 Message Lost                    */
5821 #define FDCAN_RXF1S_DMS_Pos       (30U)
5822 #define FDCAN_RXF1S_DMS_Msk       (0x3U << FDCAN_RXF1S_DMS_Pos)                /*!< 0xC0000000 */
5823 #define FDCAN_RXF1S_DMS           FDCAN_RXF1S_DMS_Msk                          /*!<Debug Message Status                      */
5824 
5825 /*****************  Bit definition for FDCAN_RXF1A register  ********************/
5826 #define FDCAN_RXF1A_F1AI_Pos      (0U)
5827 #define FDCAN_RXF1A_F1AI_Msk      (0x3FU << FDCAN_RXF1A_F1AI_Pos)              /*!< 0x0000003F */
5828 #define FDCAN_RXF1A_F1AI          FDCAN_RXF1A_F1AI_Msk                         /*!<Rx FIFO 1 Acknowledge Index               */
5829 
5830 /*****************  Bit definition for FDCAN_RXESC register  ********************/
5831 #define FDCAN_RXESC_F0DS_Pos      (0U)
5832 #define FDCAN_RXESC_F0DS_Msk      (0x7U << FDCAN_RXESC_F0DS_Pos)               /*!< 0x00000007 */
5833 #define FDCAN_RXESC_F0DS          FDCAN_RXESC_F0DS_Msk                         /*!<Rx FIFO 1 Data Field Size                 */
5834 #define FDCAN_RXESC_F1DS_Pos      (4U)
5835 #define FDCAN_RXESC_F1DS_Msk      (0x7U << FDCAN_RXESC_F1DS_Pos)               /*!< 0x00000070 */
5836 #define FDCAN_RXESC_F1DS          FDCAN_RXESC_F1DS_Msk                         /*!<Rx FIFO 0 Data Field Size                 */
5837 #define FDCAN_RXESC_RBDS_Pos      (8U)
5838 #define FDCAN_RXESC_RBDS_Msk      (0x7U << FDCAN_RXESC_RBDS_Pos)               /*!< 0x00000700 */
5839 #define FDCAN_RXESC_RBDS          FDCAN_RXESC_RBDS_Msk                         /*!<Rx Buffer Data Field Size                 */
5840 
5841 /*****************  Bit definition for FDCAN_TXBC register  *********************/
5842 #define FDCAN_TXBC_TBSA_Pos       (2U)
5843 #define FDCAN_TXBC_TBSA_Msk       (0x3FFFU << FDCAN_TXBC_TBSA_Pos)             /*!< 0x000000FC */
5844 #define FDCAN_TXBC_TBSA           FDCAN_TXBC_TBSA_Msk                          /*!<Tx Buffers Start Address                  */
5845 #define FDCAN_TXBC_NDTB_Pos       (16U)
5846 #define FDCAN_TXBC_NDTB_Msk       (0x3FU << FDCAN_TXBC_NDTB_Pos)               /*!< 0x003F0000 */
5847 #define FDCAN_TXBC_NDTB           FDCAN_TXBC_NDTB_Msk                          /*!<Number of Dedicated Transmit Buffers      */
5848 #define FDCAN_TXBC_TFQS_Pos       (24U)
5849 #define FDCAN_TXBC_TFQS_Msk       (0x3FU << FDCAN_TXBC_TFQS_Pos)               /*!< 0x3F000000 */
5850 #define FDCAN_TXBC_TFQS           FDCAN_TXBC_TFQS_Msk                          /*!<Transmit FIFO/Queue Size                  */
5851 #define FDCAN_TXBC_TFQM_Pos       (30U)
5852 #define FDCAN_TXBC_TFQM_Msk       (0x1U << FDCAN_TXBC_TFQM_Pos)                /*!< 0x40000000 */
5853 #define FDCAN_TXBC_TFQM           FDCAN_TXBC_TFQM_Msk                          /*!<Tx FIFO/Queue Mode                        */
5854 
5855 /*****************  Bit definition for FDCAN_TXFQS register  *********************/
5856 #define FDCAN_TXFQS_TFFL_Pos      (0U)
5857 #define FDCAN_TXFQS_TFFL_Msk      (0x3FU << FDCAN_TXFQS_TFFL_Pos)              /*!< 0x0000003F */
5858 #define FDCAN_TXFQS_TFFL          FDCAN_TXFQS_TFFL_Msk                         /*!<Tx FIFO Free Level                        */
5859 #define FDCAN_TXFQS_TFGI_Pos      (8U)
5860 #define FDCAN_TXFQS_TFGI_Msk      (0x1FU << FDCAN_TXFQS_TFGI_Pos)              /*!< 0x00001F00 */
5861 #define FDCAN_TXFQS_TFGI          FDCAN_TXFQS_TFGI_Msk                         /*!<Tx FIFO Get Index                         */
5862 #define FDCAN_TXFQS_TFQPI_Pos     (16U)
5863 #define FDCAN_TXFQS_TFQPI_Msk     (0x1FU << FDCAN_TXFQS_TFQPI_Pos)             /*!< 0x001F0000 */
5864 #define FDCAN_TXFQS_TFQPI         FDCAN_TXFQS_TFQPI_Msk                        /*!<Tx FIFO/Queue Put Index                   */
5865 #define FDCAN_TXFQS_TFQF_Pos      (21U)
5866 #define FDCAN_TXFQS_TFQF_Msk      (0x1U << FDCAN_TXFQS_TFQF_Pos)               /*!< 0x00200000 */
5867 #define FDCAN_TXFQS_TFQF          FDCAN_TXFQS_TFQF_Msk                         /*!<Tx FIFO/Queue Full                        */
5868 
5869 /*****************  Bit definition for FDCAN_TXESC register  *********************/
5870 #define FDCAN_TXESC_TBDS_Pos      (0U)
5871 #define FDCAN_TXESC_TBDS_Msk      (0x7U << FDCAN_TXESC_TBDS_Pos)               /*!< 0x00000007 */
5872 #define FDCAN_TXESC_TBDS          FDCAN_TXESC_TBDS_Msk                         /*!<Tx Buffer Data Field Size                 */
5873 
5874 /*****************  Bit definition for FDCAN_TXBRP register  *********************/
5875 #define FDCAN_TXBRP_TRP_Pos       (0U)
5876 #define FDCAN_TXBRP_TRP_Msk       (0xFFFFFFFFU << FDCAN_TXBRP_TRP_Pos)         /*!< 0xFFFFFFFF */
5877 #define FDCAN_TXBRP_TRP           FDCAN_TXBRP_TRP_Msk                          /*!<Transmission Request Pending              */
5878 
5879 /*****************  Bit definition for FDCAN_TXBAR register  *********************/
5880 #define FDCAN_TXBAR_AR_Pos        (0U)
5881 #define FDCAN_TXBAR_AR_Msk        (0xFFFFFFFFU << FDCAN_TXBAR_AR_Pos)          /*!< 0xFFFFFFFF */
5882 #define FDCAN_TXBAR_AR            FDCAN_TXBAR_AR_Msk                           /*!<Add Request                               */
5883 
5884 /*****************  Bit definition for FDCAN_TXBCR register  *********************/
5885 #define FDCAN_TXBCR_CR_Pos        (0U)
5886 #define FDCAN_TXBCR_CR_Msk        (0xFFFFFFFFU << FDCAN_TXBCR_CR_Pos)          /*!< 0xFFFFFFFF */
5887 #define FDCAN_TXBCR_CR            FDCAN_TXBCR_CR_Msk                           /*!<Cancellation Request                      */
5888 
5889 /*****************  Bit definition for FDCAN_TXBTO register  *********************/
5890 #define FDCAN_TXBTO_TO_Pos        (0U)
5891 #define FDCAN_TXBTO_TO_Msk        (0xFFFFFFFFU << FDCAN_TXBTO_TO_Pos)          /*!< 0xFFFFFFFF */
5892 #define FDCAN_TXBTO_TO            FDCAN_TXBTO_TO_Msk                           /*!<Transmission Occurred                     */
5893 
5894 /*****************  Bit definition for FDCAN_TXBCF register  *********************/
5895 #define FDCAN_TXBCF_CF_Pos        (0U)
5896 #define FDCAN_TXBCF_CF_Msk        (0xFFFFFFFFU << FDCAN_TXBCF_CF_Pos)          /*!< 0xFFFFFFFF */
5897 #define FDCAN_TXBCF_CF            FDCAN_TXBCF_CF_Msk                           /*!<Cancellation Finished                     */
5898 
5899 /*****************  Bit definition for FDCAN_TXBTIE register  ********************/
5900 #define FDCAN_TXBTIE_TIE_Pos      (0U)
5901 #define FDCAN_TXBTIE_TIE_Msk      (0xFFFFFFFFU << FDCAN_TXBTIE_TIE_Pos)        /*!< 0xFFFFFFFF */
5902 #define FDCAN_TXBTIE_TIE          FDCAN_TXBTIE_TIE_Msk                         /*!<Transmission Interrupt Enable             */
5903 
5904 /*****************  Bit definition for FDCAN_ TXBCIE register  *******************/
5905 #define FDCAN_TXBCIE_CF_Pos       (0U)
5906 #define FDCAN_TXBCIE_CF_Msk       (0xFFFFFFFFU << FDCAN_TXBCIE_CF_Pos)         /*!< 0xFFFFFFFF */
5907 #define FDCAN_TXBCIE_CF           FDCAN_TXBCIE_CF_Msk                          /*!<Cancellation Finished Interrupt Enable    */
5908 
5909 /*****************  Bit definition for FDCAN_TXEFC register  *********************/
5910 #define FDCAN_TXEFC_EFSA_Pos      (2U)
5911 #define FDCAN_TXEFC_EFSA_Msk      (0x3FFFU << FDCAN_TXEFC_EFSA_Pos)            /*!< 0x0000FFFC */
5912 #define FDCAN_TXEFC_EFSA          FDCAN_TXEFC_EFSA_Msk                         /*!<Event FIFO Start Address                  */
5913 #define FDCAN_TXEFC_EFS_Pos       (16U)
5914 #define FDCAN_TXEFC_EFS_Msk       (0x3FU << FDCAN_TXEFC_EFS_Pos)               /*!< 0x003F0000 */
5915 #define FDCAN_TXEFC_EFS           FDCAN_TXEFC_EFS_Msk                          /*!<Event FIFO Size                           */
5916 #define FDCAN_TXEFC_EFWM_Pos      (24U)
5917 #define FDCAN_TXEFC_EFWM_Msk      (0x3FU << FDCAN_TXEFC_EFWM_Pos)              /*!< 0x3F000000 */
5918 #define FDCAN_TXEFC_EFWM          FDCAN_TXEFC_EFWM_Msk                         /*!<Event FIFO Watermark                      */
5919 
5920 /*****************  Bit definition for FDCAN_TXEFS register  *********************/
5921 #define FDCAN_TXEFS_EFFL_Pos      (0U)
5922 #define FDCAN_TXEFS_EFFL_Msk      (0x3FU << FDCAN_TXEFS_EFFL_Pos)              /*!< 0x0000003F */
5923 #define FDCAN_TXEFS_EFFL          FDCAN_TXEFS_EFFL_Msk                         /*!<Event FIFO Fill Level                     */
5924 #define FDCAN_TXEFS_EFGI_Pos      (8U)
5925 #define FDCAN_TXEFS_EFGI_Msk      (0x1FU << FDCAN_TXEFS_EFGI_Pos)              /*!< 0x00001F00 */
5926 #define FDCAN_TXEFS_EFGI          FDCAN_TXEFS_EFGI_Msk                         /*!<Event FIFO Get Index                      */
5927 #define FDCAN_TXEFS_EFPI_Pos      (16U)
5928 #define FDCAN_TXEFS_EFPI_Msk      (0x1FU << FDCAN_TXEFS_EFPI_Pos)              /*!< 0x001F0000 */
5929 #define FDCAN_TXEFS_EFPI          FDCAN_TXEFS_EFPI_Msk                         /*!<Event FIFO Put Index                      */
5930 #define FDCAN_TXEFS_EFF_Pos       (24U)
5931 #define FDCAN_TXEFS_EFF_Msk       (0x1U << FDCAN_TXEFS_EFF_Pos)                /*!< 0x01000000 */
5932 #define FDCAN_TXEFS_EFF           FDCAN_TXEFS_EFF_Msk                          /*!<Event FIFO Full                           */
5933 #define FDCAN_TXEFS_TEFL_Pos      (25U)
5934 #define FDCAN_TXEFS_TEFL_Msk      (0x1U << FDCAN_TXEFS_TEFL_Pos)               /*!< 0x02000000 */
5935 #define FDCAN_TXEFS_TEFL          FDCAN_TXEFS_TEFL_Msk                         /*!<Tx Event FIFO Element Lost                */
5936 
5937 /*****************  Bit definition for FDCAN_TXEFA register  *********************/
5938 #define FDCAN_TXEFA_EFAI_Pos      (0U)
5939 #define FDCAN_TXEFA_EFAI_Msk      (0x1FU << FDCAN_TXEFA_EFAI_Pos)              /*!< 0x0000001F */
5940 #define FDCAN_TXEFA_EFAI          FDCAN_TXEFA_EFAI_Msk                         /*!<Event FIFO Acknowledge Index              */
5941 
5942 /*****************  Bit definition for FDCAN_TTTMC register  *********************/
5943 #define FDCAN_TTTMC_TMSA_Pos      (2U)
5944 #define FDCAN_TTTMC_TMSA_Msk      (0x3FFFU << FDCAN_TTTMC_TMSA_Pos)            /*!< 0x0000FFFC */
5945 #define FDCAN_TTTMC_TMSA          FDCAN_TTTMC_TMSA_Msk                         /*!<Trigger Memory Start Address              */
5946 #define FDCAN_TTTMC_TME_Pos       (16U)
5947 #define FDCAN_TTTMC_TME_Msk       (0x7FU << FDCAN_TTTMC_TME_Pos)               /*!< 0x007F0000 */
5948 #define FDCAN_TTTMC_TME           FDCAN_TTTMC_TME_Msk                          /*!<Trigger Memory Elements                   */
5949 
5950 /*****************  Bit definition for FDCAN_TTRMC register  *********************/
5951 #define FDCAN_TTRMC_RID_Pos       (0U)
5952 #define FDCAN_TTRMC_RID_Msk       (0x1FFFFFFFU << FDCAN_TTRMC_RID_Pos)         /*!< 0x1FFFFFFF */
5953 #define FDCAN_TTRMC_RID           FDCAN_TTRMC_RID_Msk                          /*!<Reference Identifier                      */
5954 #define FDCAN_TTRMC_XTD_Pos       (30U)
5955 #define FDCAN_TTRMC_XTD_Msk       (0x1U << FDCAN_TTRMC_XTD_Pos)                /*!< 0x40000000 */
5956 #define FDCAN_TTRMC_XTD           FDCAN_TTRMC_XTD_Msk                          /*!< Extended Identifier                      */
5957 #define FDCAN_TTRMC_RMPS_Pos      (31U)
5958 #define FDCAN_TTRMC_RMPS_Msk      (0x1U << FDCAN_TTRMC_RMPS_Pos)               /*!< 0x80000000 */
5959 #define FDCAN_TTRMC_RMPS          FDCAN_TTRMC_RMPS_Msk                         /*!<Reference Message Payload Select          */
5960 
5961 /*****************  Bit definition for FDCAN_TTOCF register  *********************/
5962 #define FDCAN_TTOCF_OM_Pos        (0U)
5963 #define FDCAN_TTOCF_OM_Msk        (0x3U << FDCAN_TTOCF_OM_Pos)                 /*!< 0x00000003 */
5964 #define FDCAN_TTOCF_OM            FDCAN_TTOCF_OM_Msk                           /*!<Operation Mode                            */
5965 #define FDCAN_TTOCF_GEN_Pos       (3U)
5966 #define FDCAN_TTOCF_GEN_Msk       (0x1U << FDCAN_TTOCF_GEN_Pos)                /*!< 0x00000008 */
5967 #define FDCAN_TTOCF_GEN           FDCAN_TTOCF_GEN_Msk                          /*!<Gap Enable                                */
5968 #define FDCAN_TTOCF_TM_Pos        (4U)
5969 #define FDCAN_TTOCF_TM_Msk        (0x1U << FDCAN_TTOCF_TM_Pos)                 /*!< 0x00000010 */
5970 #define FDCAN_TTOCF_TM            FDCAN_TTOCF_TM_Msk                           /*!<Time Master                               */
5971 #define FDCAN_TTOCF_LDSDL_Pos     (5U)
5972 #define FDCAN_TTOCF_LDSDL_Msk     (0x7U << FDCAN_TTOCF_LDSDL_Pos)              /*!< 0x000000E0 */
5973 #define FDCAN_TTOCF_LDSDL         FDCAN_TTOCF_LDSDL_Msk                        /*!<LD of Synchronization Deviation Limit     */
5974 #define FDCAN_TTOCF_IRTO_Pos      (8U)
5975 #define FDCAN_TTOCF_IRTO_Msk      (0x7FU << FDCAN_TTOCF_IRTO_Pos)              /*!< 0x00007F00 */
5976 #define FDCAN_TTOCF_IRTO          FDCAN_TTOCF_IRTO_Msk                         /*!<Initial Reference Trigger Offset          */
5977 #define FDCAN_TTOCF_EECS_Pos      (15U)
5978 #define FDCAN_TTOCF_EECS_Msk      (0x1U << FDCAN_TTOCF_EECS_Pos)               /*!< 0x00008000 */
5979 #define FDCAN_TTOCF_EECS          FDCAN_TTOCF_EECS_Msk                         /*!<Enable External Clock Synchronization     */
5980 #define FDCAN_TTOCF_AWL_Pos       (16U)
5981 #define FDCAN_TTOCF_AWL_Msk       (0xFFU << FDCAN_TTOCF_AWL_Pos)               /*!< 0x00FF0000 */
5982 #define FDCAN_TTOCF_AWL           FDCAN_TTOCF_AWL_Msk                          /*!<Application Watchdog Limit                */
5983 #define FDCAN_TTOCF_EGTF_Pos      (24U)
5984 #define FDCAN_TTOCF_EGTF_Msk      (0x1U << FDCAN_TTOCF_EGTF_Pos)               /*!< 0x01000000 */
5985 #define FDCAN_TTOCF_EGTF          FDCAN_TTOCF_EGTF_Msk                         /*!<Enable Global Time Filtering              */
5986 #define FDCAN_TTOCF_ECC_Pos       (25U)
5987 #define FDCAN_TTOCF_ECC_Msk       (0x1U << FDCAN_TTOCF_ECC_Pos)                /*!< 0x02000000 */
5988 #define FDCAN_TTOCF_ECC           FDCAN_TTOCF_ECC_Msk                          /*!<Enable Clock Calibration                  */
5989 #define FDCAN_TTOCF_EVTP_Pos      (26U)
5990 #define FDCAN_TTOCF_EVTP_Msk      (0x1U << FDCAN_TTOCF_EVTP_Pos)               /*!< 0x04000000 */
5991 #define FDCAN_TTOCF_EVTP          FDCAN_TTOCF_EVTP_Msk                         /*!<Event Trigger Polarity                    */
5992 
5993 /*****************  Bit definition for FDCAN_TTMLM register  *********************/
5994 #define FDCAN_TTMLM_CCM_Pos       (0U)
5995 #define FDCAN_TTMLM_CCM_Msk       (0x3FU << FDCAN_TTMLM_CCM_Pos)               /*!< 0x0000003F */
5996 #define FDCAN_TTMLM_CCM           FDCAN_TTMLM_CCM_Msk                          /*!<Cycle Count Max                           */
5997 #define FDCAN_TTMLM_CSS_Pos       (6U)
5998 #define FDCAN_TTMLM_CSS_Msk       (0x3U << FDCAN_TTMLM_CSS_Pos)                /*!< 0x000000C0 */
5999 #define FDCAN_TTMLM_CSS           FDCAN_TTMLM_CSS_Msk                          /*!<Cycle Start Synchronization               */
6000 #define FDCAN_TTMLM_TXEW_Pos      (8U)
6001 #define FDCAN_TTMLM_TXEW_Msk      (0xFU << FDCAN_TTMLM_TXEW_Pos)               /*!< 0x00000F00 */
6002 #define FDCAN_TTMLM_TXEW          FDCAN_TTMLM_TXEW_Msk                         /*!<Tx Enable Window                          */
6003 #define FDCAN_TTMLM_ENTT_Pos      (16U)
6004 #define FDCAN_TTMLM_ENTT_Msk      (0xFFFU << FDCAN_TTMLM_ENTT_Pos)             /*!< 0x0FFF0000 */
6005 #define FDCAN_TTMLM_ENTT          FDCAN_TTMLM_ENTT_Msk                         /*!<Expected Number of Tx Triggers            */
6006 
6007 /*****************  Bit definition for FDCAN_TURCF register  *********************/
6008 #define FDCAN_TURCF_NCL_Pos       (0U)
6009 #define FDCAN_TURCF_NCL_Msk       (0xFFFFU << FDCAN_TURCF_NCL_Pos)             /*!< 0x0000FFFF */
6010 #define FDCAN_TURCF_NCL           FDCAN_TURCF_NCL_Msk                          /*!<Numerator Configuration Low               */
6011 #define FDCAN_TURCF_DC_Pos        (16U)
6012 #define FDCAN_TURCF_DC_Msk        (0x3FFFU << FDCAN_TURCF_DC_Pos)              /*!< 0x3FFF0000 */
6013 #define FDCAN_TURCF_DC            FDCAN_TURCF_DC_Msk                           /*!<Denominator Configuration                 */
6014 #define FDCAN_TURCF_ELT_Pos       (31U)
6015 #define FDCAN_TURCF_ELT_Msk       (0x1U << FDCAN_TURCF_ELT_Pos)                /*!< 0x80000000 */
6016 #define FDCAN_TURCF_ELT           FDCAN_TURCF_ELT_Msk                          /*!<Enable Local Time                         */
6017 
6018 /*****************  Bit definition for FDCAN_TTOCN register  ********************/
6019 #define FDCAN_TTOCN_SGT_Pos       (0U)
6020 #define FDCAN_TTOCN_SGT_Msk       (0x1U << FDCAN_TTOCN_SGT_Pos)                /*!< 0x00000001 */
6021 #define FDCAN_TTOCN_SGT           FDCAN_TTOCN_SGT_Msk                          /*!<Set Global time                           */
6022 #define FDCAN_TTOCN_ECS_Pos       (1U)
6023 #define FDCAN_TTOCN_ECS_Msk       (0x1U << FDCAN_TTOCN_ECS_Pos)                /*!< 0x00000002 */
6024 #define FDCAN_TTOCN_ECS           FDCAN_TTOCN_ECS_Msk                          /*!<External Clock Synchronization            */
6025 #define FDCAN_TTOCN_SWP_Pos       (2U)
6026 #define FDCAN_TTOCN_SWP_Msk       (0x1U << FDCAN_TTOCN_SWP_Pos)                /*!< 0x00000004 */
6027 #define FDCAN_TTOCN_SWP           FDCAN_TTOCN_SWP_Msk                          /*!<Stop Watch Polarity                       */
6028 #define FDCAN_TTOCN_SWS_Pos       (3U)
6029 #define FDCAN_TTOCN_SWS_Msk       (0x3U << FDCAN_TTOCN_SWS_Pos)                /*!< 0x00000018 */
6030 #define FDCAN_TTOCN_SWS           FDCAN_TTOCN_SWS_Msk                          /*!<Stop Watch Source                         */
6031 #define FDCAN_TTOCN_RTIE_Pos      (5U)
6032 #define FDCAN_TTOCN_RTIE_Msk      (0x1U << FDCAN_TTOCN_RTIE_Pos)               /*!< 0x00000020 */
6033 #define FDCAN_TTOCN_RTIE          FDCAN_TTOCN_RTIE_Msk                         /*!<Register Time Mark Interrupt Pulse Enable */
6034 #define FDCAN_TTOCN_TMC_Pos       (6U)
6035 #define FDCAN_TTOCN_TMC_Msk       (0x3U << FDCAN_TTOCN_TMC_Pos)                /*!< 0x000000C0 */
6036 #define FDCAN_TTOCN_TMC           FDCAN_TTOCN_TMC_Msk                          /*!<Register Time Mark Compare                */
6037 #define FDCAN_TTOCN_TTIE_Pos      (8U)
6038 #define FDCAN_TTOCN_TTIE_Msk      (0x1U << FDCAN_TTOCN_TTIE_Pos)               /*!< 0x00000100 */
6039 #define FDCAN_TTOCN_TTIE          FDCAN_TTOCN_TTIE_Msk                         /*!<Trigger Time Mark Interrupt Pulse Enable  */
6040 #define FDCAN_TTOCN_GCS_Pos       (9U)
6041 #define FDCAN_TTOCN_GCS_Msk       (0x1U << FDCAN_TTOCN_GCS_Pos)                /*!< 0x00000200 */
6042 #define FDCAN_TTOCN_GCS           FDCAN_TTOCN_GCS_Msk                          /*!<Gap Control Select                        */
6043 #define FDCAN_TTOCN_FGP_Pos       (10U)
6044 #define FDCAN_TTOCN_FGP_Msk       (0x1U << FDCAN_TTOCN_FGP_Pos)                /*!< 0x00000400 */
6045 #define FDCAN_TTOCN_FGP           FDCAN_TTOCN_FGP_Msk                          /*!<Finish Gap                                */
6046 #define FDCAN_TTOCN_TMG_Pos       (11U)
6047 #define FDCAN_TTOCN_TMG_Msk       (0x1U << FDCAN_TTOCN_TMG_Pos)                /*!< 0x00000800 */
6048 #define FDCAN_TTOCN_TMG           FDCAN_TTOCN_TMG_Msk                          /*!<Time Mark Gap                             */
6049 #define FDCAN_TTOCN_NIG_Pos       (12U)
6050 #define FDCAN_TTOCN_NIG_Msk       (0x1U << FDCAN_TTOCN_NIG_Pos)                /*!< 0x00001000 */
6051 #define FDCAN_TTOCN_NIG           FDCAN_TTOCN_NIG_Msk                          /*!<Next is Gap                               */
6052 #define FDCAN_TTOCN_ESCN_Pos      (13U)
6053 #define FDCAN_TTOCN_ESCN_Msk      (0x1U << FDCAN_TTOCN_ESCN_Pos)               /*!< 0x00002000 */
6054 #define FDCAN_TTOCN_ESCN          FDCAN_TTOCN_ESCN_Msk                         /*!<External Synchronization Control          */
6055 #define FDCAN_TTOCN_LCKC_Pos      (15U)
6056 #define FDCAN_TTOCN_LCKC_Msk      (0x1U << FDCAN_TTOCN_LCKC_Pos)               /*!< 0x00008000 */
6057 #define FDCAN_TTOCN_LCKC          FDCAN_TTOCN_LCKC_Msk                         /*!<TT Operation Control Register Locked      */
6058 
6059 /*****************  Bit definition for FDCAN_TTGTP register  ********************/
6060 #define FDCAN_TTGTP_TP_Pos        (0U)
6061 #define FDCAN_TTGTP_TP_Msk        (0xFFFFU << FDCAN_TTGTP_TP_Pos)              /*!< 0x0000FFFF */
6062 #define FDCAN_TTGTP_TP            FDCAN_TTGTP_TP_Msk                           /*!<Time Preset                               */
6063 #define FDCAN_TTGTP_CTP_Pos       (16U)
6064 #define FDCAN_TTGTP_CTP_Msk       (0xFFFFU << FDCAN_TTGTP_CTP_Pos)             /*!< 0xFFFF0000 */
6065 #define FDCAN_TTGTP_CTP           FDCAN_TTGTP_CTP_Msk                          /*!<Cycle Time Target Phase                   */
6066 
6067 /*****************  Bit definition for FDCAN_TTTMK register  ********************/
6068 #define FDCAN_TTTMK_TM_Pos        (0U)
6069 #define FDCAN_TTTMK_TM_Msk        (0xFFFFU << FDCAN_TTTMK_TM_Pos)              /*!< 0x0000FFFF */
6070 #define FDCAN_TTTMK_TM            FDCAN_TTTMK_TM_Msk                           /*!<Time Mark                                 */
6071 #define FDCAN_TTTMK_TICC_Pos      (16U)
6072 #define FDCAN_TTTMK_TICC_Msk      (0x7FU << FDCAN_TTTMK_TICC_Pos)              /*!< 0x007F0000 */
6073 #define FDCAN_TTTMK_TICC          FDCAN_TTTMK_TICC_Msk                         /*!<Time Mark Cycle Code                      */
6074 #define FDCAN_TTTMK_LCKM_Pos      (31U)
6075 #define FDCAN_TTTMK_LCKM_Msk      (0x1U << FDCAN_TTTMK_LCKM_Pos)               /*!< 0x80000000 */
6076 #define FDCAN_TTTMK_LCKM          FDCAN_TTTMK_LCKM_Msk                         /*!<TT Time Mark Register Locked              */
6077 
6078 /*****************  Bit definition for FDCAN_TTIR register  ********************/
6079 #define FDCAN_TTIR_SBC_Pos        (0U)
6080 #define FDCAN_TTIR_SBC_Msk        (0x1U << FDCAN_TTIR_SBC_Pos)                 /*!< 0x00000001 */
6081 #define FDCAN_TTIR_SBC            FDCAN_TTIR_SBC_Msk                           /*!<Start of Basic Cycle                      */
6082 #define FDCAN_TTIR_SMC_Pos        (1U)
6083 #define FDCAN_TTIR_SMC_Msk        (0x1U << FDCAN_TTIR_SMC_Pos)                 /*!< 0x00000002 */
6084 #define FDCAN_TTIR_SMC            FDCAN_TTIR_SMC_Msk                           /*!<Start of Matrix Cycle                     */
6085 #define FDCAN_TTIR_CSM_Pos        (2U)
6086 #define FDCAN_TTIR_CSM_Msk        (0x1U << FDCAN_TTIR_CSM_Pos)                 /*!< 0x00000004 */
6087 #define FDCAN_TTIR_CSM            FDCAN_TTIR_CSM_Msk                           /*!<Change of Synchronization Mode            */
6088 #define FDCAN_TTIR_SOG_Pos        (3U)
6089 #define FDCAN_TTIR_SOG_Msk        (0x1U << FDCAN_TTIR_SOG_Pos)                 /*!< 0x00000008 */
6090 #define FDCAN_TTIR_SOG            FDCAN_TTIR_SOG_Msk                           /*!<Start of Gap                              */
6091 #define FDCAN_TTIR_RTMI_Pos       (4U)
6092 #define FDCAN_TTIR_RTMI_Msk       (0x1U << FDCAN_TTIR_RTMI_Pos)                /*!< 0x00000010 */
6093 #define FDCAN_TTIR_RTMI           FDCAN_TTIR_RTMI_Msk                          /*!<Register Time Mark Interrupt              */
6094 #define FDCAN_TTIR_TTMI_Pos       (5U)
6095 #define FDCAN_TTIR_TTMI_Msk       (0x1U << FDCAN_TTIR_TTMI_Pos)                /*!< 0x00000020 */
6096 #define FDCAN_TTIR_TTMI           FDCAN_TTIR_TTMI_Msk                          /*!<Trigger Time Mark Event Internal          */
6097 #define FDCAN_TTIR_SWE_Pos        (6U)
6098 #define FDCAN_TTIR_SWE_Msk        (0x1U << FDCAN_TTIR_SWE_Pos)                 /*!< 0x00000040 */
6099 #define FDCAN_TTIR_SWE            FDCAN_TTIR_SWE_Msk                           /*!<Stop Watch Event                          */
6100 #define FDCAN_TTIR_GTW_Pos        (7U)
6101 #define FDCAN_TTIR_GTW_Msk        (0x1U << FDCAN_TTIR_GTW_Pos)                 /*!< 0x00000080 */
6102 #define FDCAN_TTIR_GTW            FDCAN_TTIR_GTW_Msk                           /*!<Global Time Wrap                          */
6103 #define FDCAN_TTIR_GTD_Pos        (8U)
6104 #define FDCAN_TTIR_GTD_Msk        (0x1U << FDCAN_TTIR_GTD_Pos)                 /*!< 0x00000100 */
6105 #define FDCAN_TTIR_GTD            FDCAN_TTIR_GTD_Msk                           /*!<Global Time Discontinuity                 */
6106 #define FDCAN_TTIR_GTE_Pos        (9U)
6107 #define FDCAN_TTIR_GTE_Msk        (0x1U << FDCAN_TTIR_GTE_Pos)                 /*!< 0x00000200 */
6108 #define FDCAN_TTIR_GTE            FDCAN_TTIR_GTE_Msk                           /*!<Global Time Error                         */
6109 #define FDCAN_TTIR_TXU_Pos        (10U)
6110 #define FDCAN_TTIR_TXU_Msk        (0x1U << FDCAN_TTIR_TXU_Pos)                 /*!< 0x00000400 */
6111 #define FDCAN_TTIR_TXU            FDCAN_TTIR_TXU_Msk                           /*!<Tx Count Underflow                        */
6112 #define FDCAN_TTIR_TXO_Pos        (11U)
6113 #define FDCAN_TTIR_TXO_Msk        (0x1U << FDCAN_TTIR_TXO_Pos)                 /*!< 0x00000800 */
6114 #define FDCAN_TTIR_TXO            FDCAN_TTIR_TXO_Msk                           /*!<Tx Count Overflow                         */
6115 #define FDCAN_TTIR_SE1_Pos        (12U)
6116 #define FDCAN_TTIR_SE1_Msk        (0x1U << FDCAN_TTIR_SE1_Pos)                 /*!< 0x00001000 */
6117 #define FDCAN_TTIR_SE1            FDCAN_TTIR_SE1_Msk                           /*!<Scheduling Error 1                        */
6118 #define FDCAN_TTIR_SE2_Pos        (13U)
6119 #define FDCAN_TTIR_SE2_Msk        (0x1U << FDCAN_TTIR_SE2_Pos)                 /*!< 0x00002000 */
6120 #define FDCAN_TTIR_SE2            FDCAN_TTIR_SE2_Msk                           /*!<Scheduling Error 2                        */
6121 #define FDCAN_TTIR_ELC_Pos        (14U)
6122 #define FDCAN_TTIR_ELC_Msk        (0x1U << FDCAN_TTIR_ELC_Pos)                 /*!< 0x00004000 */
6123 #define FDCAN_TTIR_ELC            FDCAN_TTIR_ELC_Msk                           /*!<Error Level Changed                       */
6124 #define FDCAN_TTIR_IWT_Pos        (15U)
6125 #define FDCAN_TTIR_IWT_Msk        (0x1U << FDCAN_TTIR_IWT_Pos)                 /*!< 0x00008000 */
6126 #define FDCAN_TTIR_IWT            FDCAN_TTIR_IWT_Msk                           /*!<Initialization Watch Trigger              */
6127 #define FDCAN_TTIR_WT_Pos         (16U)
6128 #define FDCAN_TTIR_WT_Msk         (0x1U << FDCAN_TTIR_WT_Pos)                  /*!< 0x00010000 */
6129 #define FDCAN_TTIR_WT             FDCAN_TTIR_WT_Msk                            /*!<Watch Trigger                             */
6130 #define FDCAN_TTIR_AW_Pos         (17U)
6131 #define FDCAN_TTIR_AW_Msk         (0x1U << FDCAN_TTIR_AW_Pos)                  /*!< 0x00020000 */
6132 #define FDCAN_TTIR_AW             FDCAN_TTIR_AW_Msk                            /*!<Application Watchdog                      */
6133 #define FDCAN_TTIR_CER_Pos        (18U)
6134 #define FDCAN_TTIR_CER_Msk        (0x1U << FDCAN_TTIR_CER_Pos)                 /*!< 0x00040000 */
6135 #define FDCAN_TTIR_CER            FDCAN_TTIR_CER_Msk                           /*!<Configuration Error                       */
6136 
6137 /*****************  Bit definition for FDCAN_TTIE register  ********************/
6138 #define FDCAN_TTIE_SBCE_Pos       (0U)
6139 #define FDCAN_TTIE_SBCE_Msk       (0x1U << FDCAN_TTIE_SBCE_Pos)                /*!< 0x00000001 */
6140 #define FDCAN_TTIE_SBCE           FDCAN_TTIE_SBCE_Msk                          /*!<Start of Basic Cycle Interrupt Enable             */
6141 #define FDCAN_TTIE_SMCE_Pos       (1U)
6142 #define FDCAN_TTIE_SMCE_Msk       (0x1U << FDCAN_TTIE_SMCE_Pos)                /*!< 0x00000002 */
6143 #define FDCAN_TTIE_SMCE           FDCAN_TTIE_SMCE_Msk                          /*!<Start of Matrix Cycle Interrupt Enable            */
6144 #define FDCAN_TTIE_CSME_Pos       (2U)
6145 #define FDCAN_TTIE_CSME_Msk       (0x1U << FDCAN_TTIE_CSME_Pos)                /*!< 0x00000004 */
6146 #define FDCAN_TTIE_CSME           FDCAN_TTIE_CSME_Msk                          /*!<Change of Synchronization Mode Interrupt Enable   */
6147 #define FDCAN_TTIE_SOGE_Pos       (3U)
6148 #define FDCAN_TTIE_SOGE_Msk       (0x1U << FDCAN_TTIE_SOGE_Pos)                /*!< 0x00000008 */
6149 #define FDCAN_TTIE_SOGE           FDCAN_TTIE_SOGE_Msk                          /*!<Start of Gap Interrupt Enable                     */
6150 #define FDCAN_TTIE_RTMIE_Pos      (4U)
6151 #define FDCAN_TTIE_RTMIE_Msk      (0x1U << FDCAN_TTIE_RTMIE_Pos)               /*!< 0x00000010 */
6152 #define FDCAN_TTIE_RTMIE          FDCAN_TTIE_RTMIE_Msk                         /*!<Register Time Mark Interrupt Interrupt Enable     */
6153 #define FDCAN_TTIE_TTMIE_Pos      (5U)
6154 #define FDCAN_TTIE_TTMIE_Msk      (0x1U << FDCAN_TTIE_TTMIE_Pos)               /*!< 0x00000020 */
6155 #define FDCAN_TTIE_TTMIE          FDCAN_TTIE_TTMIE_Msk                         /*!<Trigger Time Mark Event Internal Interrupt Enable */
6156 #define FDCAN_TTIE_SWEE_Pos       (6U)
6157 #define FDCAN_TTIE_SWEE_Msk       (0x1U << FDCAN_TTIE_SWEE_Pos)                /*!< 0x00000040 */
6158 #define FDCAN_TTIE_SWEE           FDCAN_TTIE_SWEE_Msk                          /*!<Stop Watch Event Interrupt Enable                 */
6159 #define FDCAN_TTIE_GTWE_Pos       (7U)
6160 #define FDCAN_TTIE_GTWE_Msk       (0x1U << FDCAN_TTIE_GTWE_Pos)                /*!< 0x00000080 */
6161 #define FDCAN_TTIE_GTWE           FDCAN_TTIE_GTWE_Msk                          /*!<Global Time Wrap Interrupt Enable                 */
6162 #define FDCAN_TTIE_GTDE_Pos       (8U)
6163 #define FDCAN_TTIE_GTDE_Msk       (0x1U << FDCAN_TTIE_GTDE_Pos)                /*!< 0x00000100 */
6164 #define FDCAN_TTIE_GTDE           FDCAN_TTIE_GTDE_Msk                          /*!<Global Time Discontinuity Interrupt Enable        */
6165 #define FDCAN_TTIE_GTEE_Pos       (9U)
6166 #define FDCAN_TTIE_GTEE_Msk       (0x1U << FDCAN_TTIE_GTEE_Pos)                /*!< 0x00000200 */
6167 #define FDCAN_TTIE_GTEE           FDCAN_TTIE_GTEE_Msk                          /*!<Global Time Error Interrupt Enable                */
6168 #define FDCAN_TTIE_TXUE_Pos       (10U)
6169 #define FDCAN_TTIE_TXUE_Msk       (0x1U << FDCAN_TTIE_TXUE_Pos)                /*!< 0x00000400 */
6170 #define FDCAN_TTIE_TXUE           FDCAN_TTIE_TXUE_Msk                          /*!<Tx Count Underflow Interrupt Enable               */
6171 #define FDCAN_TTIE_TXOE_Pos       (11U)
6172 #define FDCAN_TTIE_TXOE_Msk       (0x1U << FDCAN_TTIE_TXOE_Pos)                /*!< 0x00000800 */
6173 #define FDCAN_TTIE_TXOE           FDCAN_TTIE_TXOE_Msk                          /*!<Tx Count Overflow Interrupt Enable                */
6174 #define FDCAN_TTIE_SE1E_Pos       (12U)
6175 #define FDCAN_TTIE_SE1E_Msk       (0x1U << FDCAN_TTIE_SE1E_Pos)                /*!< 0x00001000 */
6176 #define FDCAN_TTIE_SE1E           FDCAN_TTIE_SE1E_Msk                          /*!<Scheduling Error 1 Interrupt Enable               */
6177 #define FDCAN_TTIE_SE2E_Pos       (13U)
6178 #define FDCAN_TTIE_SE2E_Msk       (0x1U << FDCAN_TTIE_SE2E_Pos)                /*!< 0x00002000 */
6179 #define FDCAN_TTIE_SE2E           FDCAN_TTIE_SE2E_Msk                          /*!<Scheduling Error 2 Interrupt Enable               */
6180 #define FDCAN_TTIE_ELCE_Pos       (14U)
6181 #define FDCAN_TTIE_ELCE_Msk       (0x1U << FDCAN_TTIE_ELCE_Pos)                /*!< 0x00004000 */
6182 #define FDCAN_TTIE_ELCE           FDCAN_TTIE_ELCE_Msk                          /*!<Error Level Changed Interrupt Enable              */
6183 #define FDCAN_TTIE_IWTE_Pos       (15U)
6184 #define FDCAN_TTIE_IWTE_Msk       (0x1U << FDCAN_TTIE_IWTE_Pos)                /*!< 0x00008000 */
6185 #define FDCAN_TTIE_IWTE           FDCAN_TTIE_IWTE_Msk                          /*!<Initialization Watch Trigger Interrupt Enable     */
6186 #define FDCAN_TTIE_WTE_Pos        (16U)
6187 #define FDCAN_TTIE_WTE_Msk        (0x1U << FDCAN_TTIE_WTE_Pos)                 /*!< 0x00010000 */
6188 #define FDCAN_TTIE_WTE            FDCAN_TTIE_WTE_Msk                           /*!<Watch Trigger Interrupt Enable                    */
6189 #define FDCAN_TTIE_AWE_Pos        (17U)
6190 #define FDCAN_TTIE_AWE_Msk        (0x1U << FDCAN_TTIE_AWE_Pos)                 /*!< 0x00020000 */
6191 #define FDCAN_TTIE_AWE            FDCAN_TTIE_AWE_Msk                           /*!<Application Watchdog Interrupt Enable             */
6192 #define FDCAN_TTIE_CERE_Pos       (18U)
6193 #define FDCAN_TTIE_CERE_Msk       (0x1U << FDCAN_TTIE_CERE_Pos)                /*!< 0x00040000 */
6194 #define FDCAN_TTIE_CERE           FDCAN_TTIE_CERE_Msk                          /*!<Configuration Error Interrupt Enable              */
6195 
6196 /*****************  Bit definition for FDCAN_TTILS register  ********************/
6197 #define FDCAN_TTILS_SBCS_Pos      (0U)
6198 #define FDCAN_TTILS_SBCS_Msk      (0x1U << FDCAN_TTILS_SBCS_Pos)               /*!< 0x00000001 */
6199 #define FDCAN_TTILS_SBCS          FDCAN_TTILS_SBCS_Msk                         /*!<Start of Basic Cycle Interrupt Line               */
6200 #define FDCAN_TTILS_SMCS_Pos      (1U)
6201 #define FDCAN_TTILS_SMCS_Msk      (0x1U << FDCAN_TTILS_SMCS_Pos)               /*!< 0x00000002 */
6202 #define FDCAN_TTILS_SMCS          FDCAN_TTILS_SMCS_Msk                         /*!<Start of Matrix Cycle Interrupt Line              */
6203 #define FDCAN_TTILS_CSMS_Pos      (2U)
6204 #define FDCAN_TTILS_CSMS_Msk      (0x1U << FDCAN_TTILS_CSMS_Pos)               /*!< 0x00000004 */
6205 #define FDCAN_TTILS_CSMS          FDCAN_TTILS_CSMS_Msk                         /*!<Change of Synchronization Mode Interrupt Line     */
6206 #define FDCAN_TTILS_SOGS_Pos      (3U)
6207 #define FDCAN_TTILS_SOGS_Msk      (0x1U << FDCAN_TTILS_SOGS_Pos)               /*!< 0x00000008 */
6208 #define FDCAN_TTILS_SOGS          FDCAN_TTILS_SOGS_Msk                         /*!<Start of Gap Interrupt Line                       */
6209 #define FDCAN_TTILS_RTMIS_Pos     (4U)
6210 #define FDCAN_TTILS_RTMIS_Msk     (0x1U << FDCAN_TTILS_RTMIS_Pos)              /*!< 0x00000010 */
6211 #define FDCAN_TTILS_RTMIS         FDCAN_TTILS_RTMIS_Msk                        /*!<Register Time Mark Interrupt Interrupt Line       */
6212 #define FDCAN_TTILS_TTMIS_Pos     (5U)
6213 #define FDCAN_TTILS_TTMIS_Msk     (0x1U << FDCAN_TTILS_TTMIS_Pos)              /*!< 0x00000020 */
6214 #define FDCAN_TTILS_TTMIS         FDCAN_TTILS_TTMIS_Msk                        /*!<Trigger Time Mark Event Internal Interrupt Line   */
6215 #define FDCAN_TTILS_SWES_Pos      (6U)
6216 #define FDCAN_TTILS_SWES_Msk      (0x1U << FDCAN_TTILS_SWES_Pos)               /*!< 0x00000040 */
6217 #define FDCAN_TTILS_SWES          FDCAN_TTILS_SWES_Msk                         /*!<Stop Watch Event Interrupt Line                   */
6218 #define FDCAN_TTILS_GTWS_Pos      (7U)
6219 #define FDCAN_TTILS_GTWS_Msk      (0x1U << FDCAN_TTILS_GTWS_Pos)               /*!< 0x00000080 */
6220 #define FDCAN_TTILS_GTWS          FDCAN_TTILS_GTWS_Msk                         /*!<Global Time Wrap Interrupt Line                   */
6221 #define FDCAN_TTILS_GTDS_Pos      (8U)
6222 #define FDCAN_TTILS_GTDS_Msk      (0x1U << FDCAN_TTILS_GTDS_Pos)               /*!< 0x00000100 */
6223 #define FDCAN_TTILS_GTDS          FDCAN_TTILS_GTDS_Msk                         /*!<Global Time Discontinuity Interrupt Line          */
6224 #define FDCAN_TTILS_GTES_Pos      (9U)
6225 #define FDCAN_TTILS_GTES_Msk      (0x1U << FDCAN_TTILS_GTES_Pos)               /*!< 0x00000200 */
6226 #define FDCAN_TTILS_GTES          FDCAN_TTILS_GTES_Msk                         /*!<Global Time Error Interrupt Line                  */
6227 #define FDCAN_TTILS_TXUS_Pos      (10U)
6228 #define FDCAN_TTILS_TXUS_Msk      (0x1U << FDCAN_TTILS_TXUS_Pos)               /*!< 0x00000400 */
6229 #define FDCAN_TTILS_TXUS          FDCAN_TTILS_TXUS_Msk                         /*!<Tx Count Underflow Interrupt Line                 */
6230 #define FDCAN_TTILS_TXOS_Pos      (11U)
6231 #define FDCAN_TTILS_TXOS_Msk      (0x1U << FDCAN_TTILS_TXOS_Pos)               /*!< 0x00000800 */
6232 #define FDCAN_TTILS_TXOS          FDCAN_TTILS_TXOS_Msk                         /*!<Tx Count Overflow Interrupt Line                  */
6233 #define FDCAN_TTILS_SE1S_Pos      (12U)
6234 #define FDCAN_TTILS_SE1S_Msk      (0x1U << FDCAN_TTILS_SE1S_Pos)               /*!< 0x00001000 */
6235 #define FDCAN_TTILS_SE1S          FDCAN_TTILS_SE1S_Msk                         /*!<Scheduling Error 1 Interrupt Line                 */
6236 #define FDCAN_TTILS_SE2S_Pos      (13U)
6237 #define FDCAN_TTILS_SE2S_Msk      (0x1U << FDCAN_TTILS_SE2S_Pos)               /*!< 0x00002000 */
6238 #define FDCAN_TTILS_SE2S          FDCAN_TTILS_SE2S_Msk                         /*!<Scheduling Error 2 Interrupt Line                 */
6239 #define FDCAN_TTILS_ELCS_Pos      (14U)
6240 #define FDCAN_TTILS_ELCS_Msk      (0x1U << FDCAN_TTILS_ELCS_Pos)               /*!< 0x00004000 */
6241 #define FDCAN_TTILS_ELCS          FDCAN_TTILS_ELCS_Msk                         /*!<Error Level Changed Interrupt Line                */
6242 #define FDCAN_TTILS_IWTS_Pos      (15U)
6243 #define FDCAN_TTILS_IWTS_Msk      (0x1U << FDCAN_TTILS_IWTS_Pos)               /*!< 0x00008000 */
6244 #define FDCAN_TTILS_IWTS          FDCAN_TTILS_IWTS_Msk                         /*!<Initialization Watch Trigger Interrupt Line       */
6245 #define FDCAN_TTILS_WTS_Pos       (16U)
6246 #define FDCAN_TTILS_WTS_Msk       (0x1U << FDCAN_TTILS_WTS_Pos)                /*!< 0x00010000 */
6247 #define FDCAN_TTILS_WTS           FDCAN_TTILS_WTS_Msk                          /*!<Watch Trigger Interrupt Line                      */
6248 #define FDCAN_TTILS_AWS_Pos       (17U)
6249 #define FDCAN_TTILS_AWS_Msk       (0x1U << FDCAN_TTILS_AWS_Pos)                /*!< 0x00020000 */
6250 #define FDCAN_TTILS_AWS           FDCAN_TTILS_AWS_Msk                          /*!<Application Watchdog Interrupt Line               */
6251 #define FDCAN_TTILS_CERS_Pos      (18U)
6252 #define FDCAN_TTILS_CERS_Msk      (0x1U << FDCAN_TTILS_CERS_Pos)               /*!< 0x00040000 */
6253 #define FDCAN_TTILS_CERS          FDCAN_TTILS_CERS_Msk                         /*!<Configuration Error Interrupt Line                */
6254 
6255 /*****************  Bit definition for FDCAN_TTOST register  ********************/
6256 #define FDCAN_TTOST_EL_Pos        (0U)
6257 #define FDCAN_TTOST_EL_Msk        (0x3U << FDCAN_TTOST_EL_Pos)                 /*!< 0x00000003 */
6258 #define FDCAN_TTOST_EL            FDCAN_TTOST_EL_Msk                           /*!<Error Level                              */
6259 #define FDCAN_TTOST_MS_Pos        (2U)
6260 #define FDCAN_TTOST_MS_Msk        (0x3U << FDCAN_TTOST_MS_Pos)                 /*!< 0x0000000C */
6261 #define FDCAN_TTOST_MS            FDCAN_TTOST_MS_Msk                           /*!<Master State                             */
6262 #define FDCAN_TTOST_SYS_Pos       (4U)
6263 #define FDCAN_TTOST_SYS_Msk       (0x3U << FDCAN_TTOST_SYS_Pos)                /*!< 0x00000030 */
6264 #define FDCAN_TTOST_SYS           FDCAN_TTOST_SYS_Msk                          /*!<Synchronization State                    */
6265 #define FDCAN_TTOST_QGTP_Pos      (6U)
6266 #define FDCAN_TTOST_QGTP_Msk      (0x1U << FDCAN_TTOST_QGTP_Pos)               /*!< 0x00000040 */
6267 #define FDCAN_TTOST_QGTP          FDCAN_TTOST_QGTP_Msk                         /*!<Quality of Global Time Phase             */
6268 #define FDCAN_TTOST_QCS_Pos       (7U)
6269 #define FDCAN_TTOST_QCS_Msk       (0x1U << FDCAN_TTOST_QCS_Pos)                /*!< 0x00000080 */
6270 #define FDCAN_TTOST_QCS           FDCAN_TTOST_QCS_Msk                          /*!<Quality of Clock Speed                   */
6271 #define FDCAN_TTOST_RTO_Pos       (8U)
6272 #define FDCAN_TTOST_RTO_Msk       (0xFFU << FDCAN_TTOST_RTO_Pos)               /*!< 0x0000FF00 */
6273 #define FDCAN_TTOST_RTO           FDCAN_TTOST_RTO_Msk                          /*!<Reference Trigger Offset                 */
6274 #define FDCAN_TTOST_WGTD_Pos      (22U)
6275 #define FDCAN_TTOST_WGTD_Msk      (0x1U << FDCAN_TTOST_WGTD_Pos)               /*!< 0x00400000 */
6276 #define FDCAN_TTOST_WGTD          FDCAN_TTOST_WGTD_Msk                         /*!<Wait for Global Time Discontinuity       */
6277 #define FDCAN_TTOST_GFI_Pos       (23U)
6278 #define FDCAN_TTOST_GFI_Msk       (0x1U << FDCAN_TTOST_GFI_Pos)                /*!< 0x00800000 */
6279 #define FDCAN_TTOST_GFI           FDCAN_TTOST_GFI_Msk                          /*!<Gap Finished Indicator                   */
6280 #define FDCAN_TTOST_TMP_Pos       (24U)
6281 #define FDCAN_TTOST_TMP_Msk       (0x7U << FDCAN_TTOST_TMP_Pos)                /*!< 0x07000000 */
6282 #define FDCAN_TTOST_TMP           FDCAN_TTOST_TMP_Msk                          /*!<Time Master Priority                     */
6283 #define FDCAN_TTOST_GSI_Pos       (27U)
6284 #define FDCAN_TTOST_GSI_Msk       (0x1U << FDCAN_TTOST_GSI_Pos)                /*!< 0x08000000 */
6285 #define FDCAN_TTOST_GSI           FDCAN_TTOST_GSI_Msk                          /*!<Gap Started Indicator                    */
6286 #define FDCAN_TTOST_WFE_Pos       (28U)
6287 #define FDCAN_TTOST_WFE_Msk       (0x1U << FDCAN_TTOST_WFE_Pos)                /*!< 0x10000000 */
6288 #define FDCAN_TTOST_WFE           FDCAN_TTOST_WFE_Msk                          /*!<Wait for Event                           */
6289 #define FDCAN_TTOST_AWE_Pos       (29U)
6290 #define FDCAN_TTOST_AWE_Msk       (0x1U << FDCAN_TTOST_AWE_Pos)                /*!< 0x20000000 */
6291 #define FDCAN_TTOST_AWE           FDCAN_TTOST_AWE_Msk                          /*!<Application Watchdog Event               */
6292 #define FDCAN_TTOST_WECS_Pos      (30U)
6293 #define FDCAN_TTOST_WECS_Msk      (0x1U << FDCAN_TTOST_WECS_Pos)               /*!< 0x40000000 */
6294 #define FDCAN_TTOST_WECS          FDCAN_TTOST_WECS_Msk                         /*!<Wait for External Clock Synchronization  */
6295 #define FDCAN_TTOST_SPL_Pos       (31U)
6296 #define FDCAN_TTOST_SPL_Msk       (0x1U << FDCAN_TTOST_SPL_Pos)                /*!< 0x80000000 */
6297 #define FDCAN_TTOST_SPL           FDCAN_TTOST_SPL_Msk                          /*!<Schedule Phase Lock                      */
6298 
6299 /*****************  Bit definition for FDCAN_TURNA register  ********************/
6300 #define FDCAN_TURNA_NAV_Pos       (0U)
6301 #define FDCAN_TURNA_NAV_Msk       (0x3FFFFU << FDCAN_TURNA_NAV_Pos)            /*!< 0x0003FFFF */
6302 #define FDCAN_TURNA_NAV           FDCAN_TURNA_NAV_Msk                          /*!<Numerator Actual Value                   */
6303 
6304 /*****************  Bit definition for FDCAN_TTLGT register  ********************/
6305 #define FDCAN_TTLGT_LT_Pos        (0U)
6306 #define FDCAN_TTLGT_LT_Msk        (0xFFFFU << FDCAN_TTLGT_LT_Pos)              /*!< 0x0000FFFF */
6307 #define FDCAN_TTLGT_LT            FDCAN_TTLGT_LT_Msk                           /*!<Local Time                               */
6308 #define FDCAN_TTLGT_GT_Pos        (16U)
6309 #define FDCAN_TTLGT_GT_Msk        (0xFFFFU << FDCAN_TTLGT_GT_Pos)              /*!< 0xFFFF0000 */
6310 #define FDCAN_TTLGT_GT            FDCAN_TTLGT_GT_Msk                           /*!<Global Time                              */
6311 
6312 /*****************  Bit definition for FDCAN_TTCTC register  ********************/
6313 #define FDCAN_TTCTC_CT_Pos        (0U)
6314 #define FDCAN_TTCTC_CT_Msk        (0xFFFFU << FDCAN_TTCTC_CT_Pos)              /*!< 0x0000FFFF */
6315 #define FDCAN_TTCTC_CT            FDCAN_TTCTC_CT_Msk                           /*!<Cycle Time                               */
6316 #define FDCAN_TTCTC_CC_Pos        (16U)
6317 #define FDCAN_TTCTC_CC_Msk        (0x3FU << FDCAN_TTCTC_CC_Pos)                /*!< 0x003F0000 */
6318 #define FDCAN_TTCTC_CC            FDCAN_TTCTC_CC_Msk                           /*!<Cycle Count                              */
6319 
6320 /*****************  Bit definition for FDCAN_TTCPT register  ********************/
6321 #define FDCAN_TTCPT_CCV_Pos       (0U)
6322 #define FDCAN_TTCPT_CCV_Msk       (0x3FU << FDCAN_TTCPT_CCV_Pos)               /*!< 0x0000003F */
6323 #define FDCAN_TTCPT_CCV           FDCAN_TTCPT_CCV_Msk                          /*!<Cycle Count Value                        */
6324 #define FDCAN_TTCPT_SWV_Pos       (16U)
6325 #define FDCAN_TTCPT_SWV_Msk       (0xFFFFU << FDCAN_TTCPT_SWV_Pos)             /*!< 0xFFFF0000 */
6326 #define FDCAN_TTCPT_SWV           FDCAN_TTCPT_SWV_Msk                          /*!<Stop Watch Value                         */
6327 
6328 /*****************  Bit definition for FDCAN_TTCSM register  ********************/
6329 #define FDCAN_TTCSM_CSM_Pos       (0U)
6330 #define FDCAN_TTCSM_CSM_Msk       (0xFFFFU << FDCAN_TTCSM_CSM_Pos)             /*!< 0x0000FFFF */
6331 #define FDCAN_TTCSM_CSM           FDCAN_TTCSM_CSM_Msk                          /*!<Cycle Sync Mark                          */
6332 
6333 /*****************  Bit definition for FDCAN_TTTS register  *********************/
6334 #define FDCAN_TTTS_SWTSEL_Pos     (0U)
6335 #define FDCAN_TTTS_SWTSEL_Msk     (0x3U << FDCAN_TTTS_SWTSEL_Pos)              /*!< 0x00000003 */
6336 #define FDCAN_TTTS_SWTSEL         FDCAN_TTTS_SWTSEL_Msk                        /*!<Stop watch trigger input selection       */
6337 #define FDCAN_TTTS_EVTSEL_Pos     (4U)
6338 #define FDCAN_TTTS_EVTSEL_Msk     (0x3U << FDCAN_TTTS_EVTSEL_Pos)              /*!< 0x00000030 */
6339 #define FDCAN_TTTS_EVTSEL         FDCAN_TTTS_EVTSEL_Msk                        /*!<Event trigger input selection            */
6340 
6341 /********************************************************************************/
6342 /*                                                                              */
6343 /*                      FDCANCCU (Clock Calibration unit)                       */
6344 /*                                                                              */
6345 /********************************************************************************/
6346 
6347 /*****************  Bit definition for FDCANCCU_CREL register  ******************/
6348 #define FDCANCCU_CREL_DAY_Pos        (0U)
6349 #define FDCANCCU_CREL_DAY_Msk        (0xFFU << FDCANCCU_CREL_DAY_Pos)          /*!< 0x000000FF */
6350 #define FDCANCCU_CREL_DAY            FDCANCCU_CREL_DAY_Msk                     /*!<Timestamp Day                           */
6351 #define FDCANCCU_CREL_MON_Pos        (8U)
6352 #define FDCANCCU_CREL_MON_Msk        (0xFFU << FDCANCCU_CREL_MON_Pos)          /*!< 0x0000FF00 */
6353 #define FDCANCCU_CREL_MON            FDCANCCU_CREL_MON_Msk                     /*!<Timestamp Month                         */
6354 #define FDCANCCU_CREL_YEAR_Pos       (16U)
6355 #define FDCANCCU_CREL_YEAR_Msk       (0xFU << FDCANCCU_CREL_YEAR_Pos)          /*!< 0x000F0000 */
6356 #define FDCANCCU_CREL_YEAR           FDCANCCU_CREL_YEAR_Msk                    /*!<Timestamp Year                          */
6357 #define FDCANCCU_CREL_SUBSTEP_Pos    (20U)
6358 #define FDCANCCU_CREL_SUBSTEP_Msk    (0xFU << FDCANCCU_CREL_SUBSTEP_Pos)       /*!< 0x00F00000 */
6359 #define FDCANCCU_CREL_SUBSTEP        FDCANCCU_CREL_SUBSTEP_Msk                 /*!<Sub-step of Core release                */
6360 #define FDCANCCU_CREL_STEP_Pos       (24U)
6361 #define FDCANCCU_CREL_STEP_Msk       (0xFU << FDCANCCU_CREL_STEP_Pos)          /*!< 0x0F000000 */
6362 #define FDCANCCU_CREL_STEP           FDCANCCU_CREL_STEP_Msk                    /*!<Step of Core release                    */
6363 #define FDCANCCU_CREL_REL_Pos        (28U)
6364 #define FDCANCCU_CREL_REL_Msk        (0xFU << FDCANCCU_CREL_REL_Pos)           /*!< 0xF0000000 */
6365 #define FDCANCCU_CREL_REL            FDCANCCU_CREL_REL_Msk                     /*!<Core release                            */
6366 
6367 /*****************  Bit definition for FDCANCCU_CCFG register  ******************/
6368 #define FDCANCCU_CCFG_TQBT_Pos       (0U)
6369 #define FDCANCCU_CCFG_TQBT_Msk       (0x1FU << FDCANCCU_CCFG_TQBT_Pos)         /*!< 0x0000001F */
6370 #define FDCANCCU_CCFG_TQBT           FDCANCCU_CCFG_TQBT_Msk                    /*!<Time Quanta per Bit Time                */
6371 #define FDCANCCU_CCFG_BCC_Pos        (6U)
6372 #define FDCANCCU_CCFG_BCC_Msk        (0x1U << FDCANCCU_CCFG_BCC_Pos)           /*!< 0x00000040 */
6373 #define FDCANCCU_CCFG_BCC            FDCANCCU_CCFG_BCC_Msk                     /*!<Bypass Clock Calibration                */
6374 #define FDCANCCU_CCFG_CFL_Pos        (7U)
6375 #define FDCANCCU_CCFG_CFL_Msk        (0x1U << FDCANCCU_CCFG_CFL_Pos)           /*!< 0x00000080 */
6376 #define FDCANCCU_CCFG_CFL            FDCANCCU_CCFG_CFL_Msk                     /*!<Calibration Field Length                */
6377 #define FDCANCCU_CCFG_OCPM_Pos       (8U)
6378 #define FDCANCCU_CCFG_OCPM_Msk       (0xFFU << FDCANCCU_CCFG_OCPM_Pos)         /*!< 0x0000FF00 */
6379 #define FDCANCCU_CCFG_OCPM           FDCANCCU_CCFG_OCPM_Msk                    /*!<Oscillator Clock Periods Minimum        */
6380 #define FDCANCCU_CCFG_CDIV_Pos       (16U)
6381 #define FDCANCCU_CCFG_CDIV_Msk       (0xFU << FDCANCCU_CCFG_CDIV_Pos)          /*!< 0x000F0000 */
6382 #define FDCANCCU_CCFG_CDIV           FDCANCCU_CCFG_CDIV_Msk                    /*!<Clock Divider                           */
6383 #define FDCANCCU_CCFG_SWR_Pos        (31U)
6384 #define FDCANCCU_CCFG_SWR_Msk        (0x1U << FDCANCCU_CCFG_SWR_Pos)           /*!< 0x80000000 */
6385 #define FDCANCCU_CCFG_SWR            FDCANCCU_CCFG_SWR_Msk                     /*!<Software Reset                          */
6386 
6387 /*****************  Bit definition for FDCANCCU_CSTAT register  *****************/
6388 #define FDCANCCU_CSTAT_OCPC_Pos      (0U)
6389 #define FDCANCCU_CSTAT_OCPC_Msk      (0x3FFFFU << FDCANCCU_CSTAT_OCPC_Pos)     /*!< 0x0003FFFF */
6390 #define FDCANCCU_CSTAT_OCPC          FDCANCCU_CSTAT_OCPC_Msk                   /*!<Oscillator Clock Period Counter        */
6391 #define FDCANCCU_CSTAT_TQC_Pos       (18U)
6392 #define FDCANCCU_CSTAT_TQC_Msk       (0x7FFU << FDCANCCU_CSTAT_TQC_Pos)        /*!< 0x1FFC0000 */
6393 #define FDCANCCU_CSTAT_TQC           FDCANCCU_CSTAT_TQC_Msk                    /*!<Time Quanta Counter                    */
6394 #define FDCANCCU_CSTAT_CALS_Pos      (30U)
6395 #define FDCANCCU_CSTAT_CALS_Msk      (0x3U << FDCANCCU_CSTAT_CALS_Pos)         /*!< 0xC0000000 */
6396 #define FDCANCCU_CSTAT_CALS          FDCANCCU_CSTAT_CALS_Msk                   /*!<Calibration State                      */
6397 
6398 /******************  Bit definition for FDCANCCU_CWD register  ******************/
6399 #define FDCANCCU_CWD_WDC_Pos         (0U)
6400 #define FDCANCCU_CWD_WDC_Msk         (0xFFFFU << FDCANCCU_CWD_WDC_Pos)         /*!< 0x0000FFFF */
6401 #define FDCANCCU_CWD_WDC             FDCANCCU_CWD_WDC_Msk                      /*!<Watchdog Configuration                 */
6402 #define FDCANCCU_CWD_WDV_Pos         (16U)
6403 #define FDCANCCU_CWD_WDV_Msk         (0xFFFFU << FDCANCCU_CWD_WDV_Pos)         /*!< 0xFFFF0000 */
6404 #define FDCANCCU_CWD_WDV             FDCANCCU_CWD_WDV_Msk                      /*!<Watchdog Value                         */
6405 
6406 /******************  Bit definition for FDCANCCU_IR register  *******************/
6407 #define FDCANCCU_IR_CWE_Pos          (0U)
6408 #define FDCANCCU_IR_CWE_Msk          (0x1U << FDCANCCU_IR_CWE_Pos)             /*!< 0x00000001 */
6409 #define FDCANCCU_IR_CWE              FDCANCCU_IR_CWE_Msk                       /*!<Calibration Watchdog Event             */
6410 #define FDCANCCU_IR_CSC_Pos          (1U)
6411 #define FDCANCCU_IR_CSC_Msk          (0x1U << FDCANCCU_IR_CSC_Pos)             /*!< 0x00000002 */
6412 #define FDCANCCU_IR_CSC              FDCANCCU_IR_CSC_Msk                       /*!<Calibration State Changed              */
6413 
6414 /******************  Bit definition for FDCANCCU_IE register  *******************/
6415 #define FDCANCCU_IE_CWEE_Pos         (0U)
6416 #define FDCANCCU_IE_CWEE_Msk         (0x1U << FDCANCCU_IE_CWEE_Pos)            /*!< 0x00000001 */
6417 #define FDCANCCU_IE_CWEE             FDCANCCU_IE_CWEE_Msk                      /*!<Calibration Watchdog Event Enable      */
6418 #define FDCANCCU_IE_CSCE_Pos         (1U)
6419 #define FDCANCCU_IE_CSCE_Msk         (0x1U << FDCANCCU_IE_CSCE_Pos)            /*!< 0x00000002 */
6420 #define FDCANCCU_IE_CSCE             FDCANCCU_IE_CSCE_Msk                      /*!<Calibration State Changed Enable       */
6421 
6422 /******************************************************************************/
6423 /*                                                                            */
6424 /*                          HDMI-CEC (CEC)                                    */
6425 /*                                                                            */
6426 /******************************************************************************/
6427 
6428 /*******************  Bit definition for CEC_CR register  *********************/
6429 #define CEC_CR_CECEN_Pos         (0U)
6430 #define CEC_CR_CECEN_Msk         (0x1U << CEC_CR_CECEN_Pos)                    /*!< 0x00000001 */
6431 #define CEC_CR_CECEN             CEC_CR_CECEN_Msk                              /*!< CEC Enable                                */
6432 #define CEC_CR_TXSOM_Pos         (1U)
6433 #define CEC_CR_TXSOM_Msk         (0x1U << CEC_CR_TXSOM_Pos)                    /*!< 0x00000002 */
6434 #define CEC_CR_TXSOM             CEC_CR_TXSOM_Msk                              /*!< CEC Tx Start Of Message                   */
6435 #define CEC_CR_TXEOM_Pos         (2U)
6436 #define CEC_CR_TXEOM_Msk         (0x1U << CEC_CR_TXEOM_Pos)                    /*!< 0x00000004 */
6437 #define CEC_CR_TXEOM             CEC_CR_TXEOM_Msk                              /*!< CEC Tx End Of Message                     */
6438 
6439 /*******************  Bit definition for CEC_CFGR register  *******************/
6440 #define CEC_CFGR_SFT_Pos         (0U)
6441 #define CEC_CFGR_SFT_Msk         (0x7U << CEC_CFGR_SFT_Pos)                    /*!< 0x00000007 */
6442 #define CEC_CFGR_SFT             CEC_CFGR_SFT_Msk                              /*!< CEC Signal Free Time                      */
6443 #define CEC_CFGR_RXTOL_Pos       (3U)
6444 #define CEC_CFGR_RXTOL_Msk       (0x1U << CEC_CFGR_RXTOL_Pos)                  /*!< 0x00000008 */
6445 #define CEC_CFGR_RXTOL           CEC_CFGR_RXTOL_Msk                            /*!< CEC Tolerance                             */
6446 #define CEC_CFGR_BRESTP_Pos      (4U)
6447 #define CEC_CFGR_BRESTP_Msk      (0x1U << CEC_CFGR_BRESTP_Pos)                 /*!< 0x00000010 */
6448 #define CEC_CFGR_BRESTP          CEC_CFGR_BRESTP_Msk                           /*!< CEC Rx Stop                               */
6449 #define CEC_CFGR_BREGEN_Pos      (5U)
6450 #define CEC_CFGR_BREGEN_Msk      (0x1U << CEC_CFGR_BREGEN_Pos)                 /*!< 0x00000020 */
6451 #define CEC_CFGR_BREGEN          CEC_CFGR_BREGEN_Msk                           /*!< CEC Bit Rising Error generation           */
6452 #define CEC_CFGR_LBPEGEN_Pos     (6U)
6453 #define CEC_CFGR_LBPEGEN_Msk     (0x1U << CEC_CFGR_LBPEGEN_Pos)                /*!< 0x00000040 */
6454 #define CEC_CFGR_LBPEGEN         CEC_CFGR_LBPEGEN_Msk                          /*!< CEC Long Bit Period Error generation      */
6455 #define CEC_CFGR_SFTOPT_Pos      (8U)
6456 #define CEC_CFGR_SFTOPT_Msk      (0x1U << CEC_CFGR_SFTOPT_Pos)                 /*!< 0x00000100 */
6457 #define CEC_CFGR_SFTOPT          CEC_CFGR_SFTOPT_Msk                           /*!< CEC Signal Free Time optional             */
6458 #define CEC_CFGR_BRDNOGEN_Pos    (7U)
6459 #define CEC_CFGR_BRDNOGEN_Msk    (0x1U << CEC_CFGR_BRDNOGEN_Pos)               /*!< 0x00000080 */
6460 #define CEC_CFGR_BRDNOGEN        CEC_CFGR_BRDNOGEN_Msk                         /*!< CEC Broadcast No error generation         */
6461 #define CEC_CFGR_OAR_Pos         (16U)
6462 #define CEC_CFGR_OAR_Msk         (0x7FFFU << CEC_CFGR_OAR_Pos)                 /*!< 0x7FFF0000 */
6463 #define CEC_CFGR_OAR             CEC_CFGR_OAR_Msk                              /*!< CEC Own Address                           */
6464 #define CEC_CFGR_LSTN_Pos        (31U)
6465 #define CEC_CFGR_LSTN_Msk        (0x1U << CEC_CFGR_LSTN_Pos)                   /*!< 0x80000000 */
6466 #define CEC_CFGR_LSTN            CEC_CFGR_LSTN_Msk                             /*!< CEC Listen mode                           */
6467 
6468 /*******************  Bit definition for CEC_TXDR register  *******************/
6469 #define CEC_TXDR_TXD_Pos         (0U)
6470 #define CEC_TXDR_TXD_Msk         (0xFFU << CEC_TXDR_TXD_Pos)                   /*!< 0x000000FF */
6471 #define CEC_TXDR_TXD             CEC_TXDR_TXD_Msk                              /*!< CEC Tx Data                               */
6472 
6473 /*******************  Bit definition for CEC_RXDR register  *******************/
6474 #define CEC_TXDR_RXD_Pos         (0U)
6475 #define CEC_TXDR_RXD_Msk         (0xFFU << CEC_TXDR_RXD_Pos)                   /*!< 0x000000FF */
6476 #define CEC_TXDR_RXD             CEC_TXDR_RXD_Msk                              /*!< CEC Rx Data                               */
6477 
6478 /*******************  Bit definition for CEC_ISR register  ********************/
6479 #define CEC_ISR_RXBR_Pos         (0U)
6480 #define CEC_ISR_RXBR_Msk         (0x1U << CEC_ISR_RXBR_Pos)                    /*!< 0x00000001 */
6481 #define CEC_ISR_RXBR             CEC_ISR_RXBR_Msk                              /*!< CEC Rx-Byte Received                      */
6482 #define CEC_ISR_RXEND_Pos        (1U)
6483 #define CEC_ISR_RXEND_Msk        (0x1U << CEC_ISR_RXEND_Pos)                   /*!< 0x00000002 */
6484 #define CEC_ISR_RXEND            CEC_ISR_RXEND_Msk                             /*!< CEC End Of Reception                      */
6485 #define CEC_ISR_RXOVR_Pos        (2U)
6486 #define CEC_ISR_RXOVR_Msk        (0x1U << CEC_ISR_RXOVR_Pos)                   /*!< 0x00000004 */
6487 #define CEC_ISR_RXOVR            CEC_ISR_RXOVR_Msk                             /*!< CEC Rx-Overrun                            */
6488 #define CEC_ISR_BRE_Pos          (3U)
6489 #define CEC_ISR_BRE_Msk          (0x1U << CEC_ISR_BRE_Pos)                     /*!< 0x00000008 */
6490 #define CEC_ISR_BRE              CEC_ISR_BRE_Msk                               /*!< CEC Rx Bit Rising Error                   */
6491 #define CEC_ISR_SBPE_Pos         (4U)
6492 #define CEC_ISR_SBPE_Msk         (0x1U << CEC_ISR_SBPE_Pos)                    /*!< 0x00000010 */
6493 #define CEC_ISR_SBPE             CEC_ISR_SBPE_Msk                              /*!< CEC Rx Short Bit period Error             */
6494 #define CEC_ISR_LBPE_Pos         (5U)
6495 #define CEC_ISR_LBPE_Msk         (0x1U << CEC_ISR_LBPE_Pos)                    /*!< 0x00000020 */
6496 #define CEC_ISR_LBPE             CEC_ISR_LBPE_Msk                              /*!< CEC Rx Long Bit period Error              */
6497 #define CEC_ISR_RXACKE_Pos       (6U)
6498 #define CEC_ISR_RXACKE_Msk       (0x1U << CEC_ISR_RXACKE_Pos)                  /*!< 0x00000040 */
6499 #define CEC_ISR_RXACKE           CEC_ISR_RXACKE_Msk                            /*!< CEC Rx Missing Acknowledge                */
6500 #define CEC_ISR_ARBLST_Pos       (7U)
6501 #define CEC_ISR_ARBLST_Msk       (0x1U << CEC_ISR_ARBLST_Pos)                  /*!< 0x00000080 */
6502 #define CEC_ISR_ARBLST           CEC_ISR_ARBLST_Msk                            /*!< CEC Arbitration Lost                      */
6503 #define CEC_ISR_TXBR_Pos         (8U)
6504 #define CEC_ISR_TXBR_Msk         (0x1U << CEC_ISR_TXBR_Pos)                    /*!< 0x00000100 */
6505 #define CEC_ISR_TXBR             CEC_ISR_TXBR_Msk                              /*!< CEC Tx Byte Request                       */
6506 #define CEC_ISR_TXEND_Pos        (9U)
6507 #define CEC_ISR_TXEND_Msk        (0x1U << CEC_ISR_TXEND_Pos)                   /*!< 0x00000200 */
6508 #define CEC_ISR_TXEND            CEC_ISR_TXEND_Msk                             /*!< CEC End of Transmission                   */
6509 #define CEC_ISR_TXUDR_Pos        (10U)
6510 #define CEC_ISR_TXUDR_Msk        (0x1U << CEC_ISR_TXUDR_Pos)                   /*!< 0x00000400 */
6511 #define CEC_ISR_TXUDR            CEC_ISR_TXUDR_Msk                             /*!< CEC Tx-Buffer Underrun                    */
6512 #define CEC_ISR_TXERR_Pos        (11U)
6513 #define CEC_ISR_TXERR_Msk        (0x1U << CEC_ISR_TXERR_Pos)                   /*!< 0x00000800 */
6514 #define CEC_ISR_TXERR            CEC_ISR_TXERR_Msk                             /*!< CEC Tx-Error                              */
6515 #define CEC_ISR_TXACKE_Pos       (12U)
6516 #define CEC_ISR_TXACKE_Msk       (0x1U << CEC_ISR_TXACKE_Pos)                  /*!< 0x00001000 */
6517 #define CEC_ISR_TXACKE           CEC_ISR_TXACKE_Msk                            /*!< CEC Tx Missing Acknowledge                */
6518 
6519 /*******************  Bit definition for CEC_IER register  ********************/
6520 #define CEC_IER_RXBRIE_Pos       (0U)
6521 #define CEC_IER_RXBRIE_Msk       (0x1U << CEC_IER_RXBRIE_Pos)                  /*!< 0x00000001 */
6522 #define CEC_IER_RXBRIE           CEC_IER_RXBRIE_Msk                            /*!< CEC Rx-Byte Received IT Enable            */
6523 #define CEC_IER_RXENDIE_Pos      (1U)
6524 #define CEC_IER_RXENDIE_Msk      (0x1U << CEC_IER_RXENDIE_Pos)                 /*!< 0x00000002 */
6525 #define CEC_IER_RXENDIE          CEC_IER_RXENDIE_Msk                           /*!< CEC End Of Reception IT Enable            */
6526 #define CEC_IER_RXOVRIE_Pos      (2U)
6527 #define CEC_IER_RXOVRIE_Msk      (0x1U << CEC_IER_RXOVRIE_Pos)                 /*!< 0x00000004 */
6528 #define CEC_IER_RXOVRIE          CEC_IER_RXOVRIE_Msk                           /*!< CEC Rx-Overrun IT Enable                  */
6529 #define CEC_IER_BREIE_Pos        (3U)
6530 #define CEC_IER_BREIE_Msk        (0x1U << CEC_IER_BREIE_Pos)                   /*!< 0x00000008 */
6531 #define CEC_IER_BREIE            CEC_IER_BREIE_Msk                             /*!< CEC Rx Bit Rising Error IT Enable         */
6532 #define CEC_IER_SBPEIE_Pos       (4U)
6533 #define CEC_IER_SBPEIE_Msk       (0x1U << CEC_IER_SBPEIE_Pos)                  /*!< 0x00000010 */
6534 #define CEC_IER_SBPEIE           CEC_IER_SBPEIE_Msk                            /*!< CEC Rx Short Bit period Error IT Enable   */
6535 #define CEC_IER_LBPEIE_Pos       (5U)
6536 #define CEC_IER_LBPEIE_Msk       (0x1U << CEC_IER_LBPEIE_Pos)                  /*!< 0x00000020 */
6537 #define CEC_IER_LBPEIE           CEC_IER_LBPEIE_Msk                            /*!< CEC Rx Long Bit period Error IT Enable    */
6538 #define CEC_IER_RXACKEIE_Pos     (6U)
6539 #define CEC_IER_RXACKEIE_Msk     (0x1U << CEC_IER_RXACKEIE_Pos)                /*!< 0x00000040 */
6540 #define CEC_IER_RXACKEIE         CEC_IER_RXACKEIE_Msk                          /*!< CEC Rx Missing Acknowledge IT Enable      */
6541 #define CEC_IER_ARBLSTIE_Pos     (7U)
6542 #define CEC_IER_ARBLSTIE_Msk     (0x1U << CEC_IER_ARBLSTIE_Pos)                /*!< 0x00000080 */
6543 #define CEC_IER_ARBLSTIE         CEC_IER_ARBLSTIE_Msk                          /*!< CEC Arbitration Lost IT Enable            */
6544 #define CEC_IER_TXBRIE_Pos       (8U)
6545 #define CEC_IER_TXBRIE_Msk       (0x1U << CEC_IER_TXBRIE_Pos)                  /*!< 0x00000100 */
6546 #define CEC_IER_TXBRIE           CEC_IER_TXBRIE_Msk                            /*!< CEC Tx Byte Request  IT Enable            */
6547 #define CEC_IER_TXENDIE_Pos      (9U)
6548 #define CEC_IER_TXENDIE_Msk      (0x1U << CEC_IER_TXENDIE_Pos)                 /*!< 0x00000200 */
6549 #define CEC_IER_TXENDIE          CEC_IER_TXENDIE_Msk                           /*!< CEC End of Transmission IT Enable         */
6550 #define CEC_IER_TXUDRIE_Pos      (10U)
6551 #define CEC_IER_TXUDRIE_Msk      (0x1U << CEC_IER_TXUDRIE_Pos)                 /*!< 0x00000400 */
6552 #define CEC_IER_TXUDRIE          CEC_IER_TXUDRIE_Msk                           /*!< CEC Tx-Buffer Underrun IT Enable          */
6553 #define CEC_IER_TXERRIE_Pos      (11U)
6554 #define CEC_IER_TXERRIE_Msk      (0x1U << CEC_IER_TXERRIE_Pos)                 /*!< 0x00000800 */
6555 #define CEC_IER_TXERRIE          CEC_IER_TXERRIE_Msk                           /*!< CEC Tx-Error IT Enable                    */
6556 #define CEC_IER_TXACKEIE_Pos     (12U)
6557 #define CEC_IER_TXACKEIE_Msk     (0x1U << CEC_IER_TXACKEIE_Pos)                /*!< 0x00001000 */
6558 #define CEC_IER_TXACKEIE         CEC_IER_TXACKEIE_Msk                          /*!< CEC Tx Missing Acknowledge IT Enable      */
6559 
6560 /******************************************************************************/
6561 /*                                                                            */
6562 /*                          CRC calculation unit                              */
6563 /*                                                                            */
6564 /******************************************************************************/
6565 /*******************  Bit definition for CRC_DR register  *********************/
6566 #define CRC_DR_DR_Pos            (0U)
6567 #define CRC_DR_DR_Msk            (0xFFFFFFFFU << CRC_DR_DR_Pos)                /*!< 0xFFFFFFFF */
6568 #define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
6569 
6570 /*******************  Bit definition for CRC_IDR register  ********************/
6571 #define CRC_IDR_IDR_Pos          (0U)
6572 #define CRC_IDR_IDR_Msk          (0xFFFFFFFFU << CRC_IDR_IDR_Pos)              /*!< 0xFFFFFFFF */
6573 #define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 32-bit data register bits */
6574 
6575 /********************  Bit definition for CRC_CR register  ********************/
6576 #define CRC_CR_RESET_Pos         (0U)
6577 #define CRC_CR_RESET_Msk         (0x1U << CRC_CR_RESET_Pos)                    /*!< 0x00000001 */
6578 #define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
6579 #define CRC_CR_POLYSIZE_Pos      (3U)
6580 #define CRC_CR_POLYSIZE_Msk      (0x3U << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000018 */
6581 #define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
6582 #define CRC_CR_POLYSIZE_0        (0x1U << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */
6583 #define CRC_CR_POLYSIZE_1        (0x2U << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */
6584 #define CRC_CR_REV_IN_Pos        (5U)
6585 #define CRC_CR_REV_IN_Msk        (0x3U << CRC_CR_REV_IN_Pos)                   /*!< 0x00000060 */
6586 #define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
6587 #define CRC_CR_REV_IN_0          (0x1U << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
6588 #define CRC_CR_REV_IN_1          (0x2U << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
6589 #define CRC_CR_REV_OUT_Pos       (7U)
6590 #define CRC_CR_REV_OUT_Msk       (0x1U << CRC_CR_REV_OUT_Pos)                  /*!< 0x00000080 */
6591 #define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
6592 
6593 /*******************  Bit definition for CRC_INIT register  *******************/
6594 #define CRC_INIT_INIT_Pos        (0U)
6595 #define CRC_INIT_INIT_Msk        (0xFFFFFFFFU << CRC_INIT_INIT_Pos)            /*!< 0xFFFFFFFF */
6596 #define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
6597 
6598 /*******************  Bit definition for CRC_POL register  ********************/
6599 #define CRC_POL_POL_Pos          (0U)
6600 #define CRC_POL_POL_Msk          (0xFFFFFFFFU << CRC_POL_POL_Pos)              /*!< 0xFFFFFFFF */
6601 #define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
6602 
6603 /******************************************************************************/
6604 /*                                                                            */
6605 /*                          CRS Clock Recovery System                         */
6606 /******************************************************************************/
6607 
6608 /*******************  Bit definition for CRS_CR register  *********************/
6609 #define CRS_CR_SYNCOKIE_Pos       (0U)
6610 #define CRS_CR_SYNCOKIE_Msk       (0x1U << CRS_CR_SYNCOKIE_Pos)                /*!< 0x00000001 */
6611 #define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /*!< SYNC event OK interrupt enable */
6612 #define CRS_CR_SYNCWARNIE_Pos     (1U)
6613 #define CRS_CR_SYNCWARNIE_Msk     (0x1U << CRS_CR_SYNCWARNIE_Pos)              /*!< 0x00000002 */
6614 #define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /*!< SYNC warning interrupt enable */
6615 #define CRS_CR_ERRIE_Pos          (2U)
6616 #define CRS_CR_ERRIE_Msk          (0x1U << CRS_CR_ERRIE_Pos)                   /*!< 0x00000004 */
6617 #define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /*!< SYNC error or trimming error interrupt enable */
6618 #define CRS_CR_ESYNCIE_Pos        (3U)
6619 #define CRS_CR_ESYNCIE_Msk        (0x1U << CRS_CR_ESYNCIE_Pos)                 /*!< 0x00000008 */
6620 #define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /*!< Expected SYNC interrupt enable */
6621 #define CRS_CR_CEN_Pos            (5U)
6622 #define CRS_CR_CEN_Msk            (0x1U << CRS_CR_CEN_Pos)                     /*!< 0x00000020 */
6623 #define CRS_CR_CEN                CRS_CR_CEN_Msk                               /*!< Frequency error counter enable */
6624 #define CRS_CR_AUTOTRIMEN_Pos     (6U)
6625 #define CRS_CR_AUTOTRIMEN_Msk     (0x1U << CRS_CR_AUTOTRIMEN_Pos)              /*!< 0x00000040 */
6626 #define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /*!< Automatic trimming enable */
6627 #define CRS_CR_SWSYNC_Pos         (7U)
6628 #define CRS_CR_SWSYNC_Msk         (0x1U << CRS_CR_SWSYNC_Pos)                  /*!< 0x00000080 */
6629 #define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /*!< Generate software SYNC event */
6630 #define CRS_CR_TRIM_Pos           (8U)
6631 #define CRS_CR_TRIM_Msk           (0x3FU << CRS_CR_TRIM_Pos)                   /*!< 0x00003F00 */
6632 #define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /*!< HSI48 oscillator smooth trimming */
6633 
6634 /*******************  Bit definition for CRS_CFGR register  *********************/
6635 #define CRS_CFGR_RELOAD_Pos       (0U)
6636 #define CRS_CFGR_RELOAD_Msk       (0xFFFFU << CRS_CFGR_RELOAD_Pos)             /*!< 0x0000FFFF */
6637 #define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /*!< Counter reload value */
6638 #define CRS_CFGR_FELIM_Pos        (16U)
6639 #define CRS_CFGR_FELIM_Msk        (0xFFU << CRS_CFGR_FELIM_Pos)                /*!< 0x00FF0000 */
6640 #define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /*!< Frequency error limit */
6641 
6642 #define CRS_CFGR_SYNCDIV_Pos      (24U)
6643 #define CRS_CFGR_SYNCDIV_Msk      (0x7U << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x07000000 */
6644 #define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /*!< SYNC divider */
6645 #define CRS_CFGR_SYNCDIV_0        (0x1U << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x01000000 */
6646 #define CRS_CFGR_SYNCDIV_1        (0x2U << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x02000000 */
6647 #define CRS_CFGR_SYNCDIV_2        (0x4U << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x04000000 */
6648 
6649 #define CRS_CFGR_SYNCSRC_Pos      (28U)
6650 #define CRS_CFGR_SYNCSRC_Msk      (0x3U << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x30000000 */
6651 #define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /*!< SYNC signal source selection */
6652 #define CRS_CFGR_SYNCSRC_0        (0x1U << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x10000000 */
6653 #define CRS_CFGR_SYNCSRC_1        (0x2U << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x20000000 */
6654 
6655 #define CRS_CFGR_SYNCPOL_Pos      (31U)
6656 #define CRS_CFGR_SYNCPOL_Msk      (0x1U << CRS_CFGR_SYNCPOL_Pos)               /*!< 0x80000000 */
6657 #define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /*!< SYNC polarity selection */
6658 
6659 /*******************  Bit definition for CRS_ISR register  *********************/
6660 #define CRS_ISR_SYNCOKF_Pos       (0U)
6661 #define CRS_ISR_SYNCOKF_Msk       (0x1U << CRS_ISR_SYNCOKF_Pos)                /*!< 0x00000001 */
6662 #define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /*!< SYNC event OK flag */
6663 #define CRS_ISR_SYNCWARNF_Pos     (1U)
6664 #define CRS_ISR_SYNCWARNF_Msk     (0x1U << CRS_ISR_SYNCWARNF_Pos)              /*!< 0x00000002 */
6665 #define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /*!< SYNC warning flag */
6666 #define CRS_ISR_ERRF_Pos          (2U)
6667 #define CRS_ISR_ERRF_Msk          (0x1U << CRS_ISR_ERRF_Pos)                   /*!< 0x00000004 */
6668 #define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /*!< Error flag */
6669 #define CRS_ISR_ESYNCF_Pos        (3U)
6670 #define CRS_ISR_ESYNCF_Msk        (0x1U << CRS_ISR_ESYNCF_Pos)                 /*!< 0x00000008 */
6671 #define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /*!< Expected SYNC flag */
6672 #define CRS_ISR_SYNCERR_Pos       (8U)
6673 #define CRS_ISR_SYNCERR_Msk       (0x1U << CRS_ISR_SYNCERR_Pos)                /*!< 0x00000100 */
6674 #define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /*!< SYNC error */
6675 #define CRS_ISR_SYNCMISS_Pos      (9U)
6676 #define CRS_ISR_SYNCMISS_Msk      (0x1U << CRS_ISR_SYNCMISS_Pos)               /*!< 0x00000200 */
6677 #define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /*!< SYNC missed */
6678 #define CRS_ISR_TRIMOVF_Pos       (10U)
6679 #define CRS_ISR_TRIMOVF_Msk       (0x1U << CRS_ISR_TRIMOVF_Pos)                /*!< 0x00000400 */
6680 #define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /*!< Trimming overflow or underflow */
6681 #define CRS_ISR_FEDIR_Pos         (15U)
6682 #define CRS_ISR_FEDIR_Msk         (0x1U << CRS_ISR_FEDIR_Pos)                  /*!< 0x00008000 */
6683 #define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /*!< Frequency error direction */
6684 #define CRS_ISR_FECAP_Pos         (16U)
6685 #define CRS_ISR_FECAP_Msk         (0xFFFFU << CRS_ISR_FECAP_Pos)               /*!< 0xFFFF0000 */
6686 #define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /*!< Frequency error capture */
6687 
6688 /*******************  Bit definition for CRS_ICR register  *********************/
6689 #define CRS_ICR_SYNCOKC_Pos       (0U)
6690 #define CRS_ICR_SYNCOKC_Msk       (0x1U << CRS_ICR_SYNCOKC_Pos)                /*!< 0x00000001 */
6691 #define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /*!< SYNC event OK clear flag */
6692 #define CRS_ICR_SYNCWARNC_Pos     (1U)
6693 #define CRS_ICR_SYNCWARNC_Msk     (0x1U << CRS_ICR_SYNCWARNC_Pos)              /*!< 0x00000002 */
6694 #define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /*!< SYNC warning clear flag */
6695 #define CRS_ICR_ERRC_Pos          (2U)
6696 #define CRS_ICR_ERRC_Msk          (0x1U << CRS_ICR_ERRC_Pos)                   /*!< 0x00000004 */
6697 #define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /*!< Error clear flag */
6698 #define CRS_ICR_ESYNCC_Pos        (3U)
6699 #define CRS_ICR_ESYNCC_Msk        (0x1U << CRS_ICR_ESYNCC_Pos)                 /*!< 0x00000008 */
6700 #define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /*!< Expected SYNC clear flag */
6701 
6702 
6703 /******************************************************************************/
6704 /*                                                                            */
6705 /*                      Digital to Analog Converter                           */
6706 /*                                                                            */
6707 /******************************************************************************/
6708 /********************  Bit definition for DAC_CR register  ********************/
6709 #define DAC_CR_EN1_Pos              (0U)
6710 #define DAC_CR_EN1_Msk              (0x1U << DAC_CR_EN1_Pos)                   /*!< 0x00000001 */
6711 #define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */
6712 #define DAC_CR_TEN1_Pos             (1U)
6713 #define DAC_CR_TEN1_Msk             (0x1U << DAC_CR_TEN1_Pos)                  /*!< 0x00000002 */
6714 #define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */
6715 
6716 #define DAC_CR_TSEL1_Pos            (2U)
6717 #define DAC_CR_TSEL1_Msk            (0xFU << DAC_CR_TSEL1_Pos)                 /*!< 0x0000003C */
6718 #define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
6719 #define DAC_CR_TSEL1_0              (0x1U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000004 */
6720 #define DAC_CR_TSEL1_1              (0x2U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */
6721 #define DAC_CR_TSEL1_2              (0x4U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */
6722 #define DAC_CR_TSEL1_3              (0x8U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */
6723 
6724 
6725 #define DAC_CR_WAVE1_Pos            (6U)
6726 #define DAC_CR_WAVE1_Msk            (0x3U << DAC_CR_WAVE1_Pos)                 /*!< 0x000000C0 */
6727 #define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
6728 #define DAC_CR_WAVE1_0              (0x1U << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */
6729 #define DAC_CR_WAVE1_1              (0x2U << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */
6730 
6731 #define DAC_CR_MAMP1_Pos            (8U)
6732 #define DAC_CR_MAMP1_Msk            (0xFU << DAC_CR_MAMP1_Pos)                 /*!< 0x00000F00 */
6733 #define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
6734 #define DAC_CR_MAMP1_0              (0x1U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */
6735 #define DAC_CR_MAMP1_1              (0x2U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */
6736 #define DAC_CR_MAMP1_2              (0x4U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */
6737 #define DAC_CR_MAMP1_3              (0x8U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */
6738 
6739 #define DAC_CR_DMAEN1_Pos           (12U)
6740 #define DAC_CR_DMAEN1_Msk           (0x1U << DAC_CR_DMAEN1_Pos)                /*!< 0x00001000 */
6741 #define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */
6742 #define DAC_CR_DMAUDRIE1_Pos        (13U)
6743 #define DAC_CR_DMAUDRIE1_Msk        (0x1U << DAC_CR_DMAUDRIE1_Pos)             /*!< 0x00002000 */
6744 #define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/
6745 #define DAC_CR_CEN1_Pos             (14U)
6746 #define DAC_CR_CEN1_Msk             (0x1U << DAC_CR_CEN1_Pos)                  /*!< 0x00004000 */
6747 #define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/
6748 #define DAC_CR_HFSEL_Pos            (15U)
6749 #define DAC_CR_HFSEL_Msk            (0x1U << DAC_CR_HFSEL_Pos)                  /*!< 0x00008000 */
6750 #define DAC_CR_HFSEL                DAC_CR_HFSEL_Msk                            /*!<High frequency interface mode enable >*/
6751 
6752 #define DAC_CR_EN2_Pos              (16U)
6753 #define DAC_CR_EN2_Msk              (0x1U << DAC_CR_EN2_Pos)                   /*!< 0x00010000 */
6754 #define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */
6755 #define DAC_CR_TEN2_Pos             (17U)
6756 #define DAC_CR_TEN2_Msk             (0x1U << DAC_CR_TEN2_Pos)                  /*!< 0x00020000 */
6757 #define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */
6758 
6759 #define DAC_CR_TSEL2_Pos            (18U)
6760 #define DAC_CR_TSEL2_Msk            (0xFU << DAC_CR_TSEL2_Pos)                 /*!< 0x003C0000 */
6761 #define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
6762 #define DAC_CR_TSEL2_0              (0x1U << DAC_CR_TSEL2_Pos)                 /*!< 0x00040000 */
6763 #define DAC_CR_TSEL2_1              (0x2U << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */
6764 #define DAC_CR_TSEL2_2              (0x4U << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */
6765 #define DAC_CR_TSEL2_3              (0x8U << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */
6766 
6767 
6768 #define DAC_CR_WAVE2_Pos            (22U)
6769 #define DAC_CR_WAVE2_Msk            (0x3U << DAC_CR_WAVE2_Pos)                 /*!< 0x00C00000 */
6770 #define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
6771 #define DAC_CR_WAVE2_0              (0x1U << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */
6772 #define DAC_CR_WAVE2_1              (0x2U << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */
6773 
6774 #define DAC_CR_MAMP2_Pos            (24U)
6775 #define DAC_CR_MAMP2_Msk            (0xFU << DAC_CR_MAMP2_Pos)                 /*!< 0x0F000000 */
6776 #define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
6777 #define DAC_CR_MAMP2_0              (0x1U << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */
6778 #define DAC_CR_MAMP2_1              (0x2U << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */
6779 #define DAC_CR_MAMP2_2              (0x4U << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */
6780 #define DAC_CR_MAMP2_3              (0x8U << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */
6781 
6782 #define DAC_CR_DMAEN2_Pos           (28U)
6783 #define DAC_CR_DMAEN2_Msk           (0x1U << DAC_CR_DMAEN2_Pos)                /*!< 0x10000000 */
6784 #define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */
6785 #define DAC_CR_DMAUDRIE2_Pos        (29U)
6786 #define DAC_CR_DMAUDRIE2_Msk        (0x1U << DAC_CR_DMAUDRIE2_Pos)             /*!< 0x20000000 */
6787 #define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable  >*/
6788 #define DAC_CR_CEN2_Pos             (30U)
6789 #define DAC_CR_CEN2_Msk             (0x1U << DAC_CR_CEN2_Pos)                  /*!< 0x40000000 */
6790 #define DAC_CR_CEN2                 DAC_CR_CEN2_Msk                            /*!<DAC channel2 calibration enable >*/
6791 
6792 /*****************  Bit definition for DAC_SWTRIGR register  ******************/
6793 #define DAC_SWTRIGR_SWTRIG1         ((uint8_t)0x01)                            /*!<DAC channel1 software trigger */
6794 #define DAC_SWTRIGR_SWTRIG2         ((uint8_t)0x02)                            /*!<DAC channel2 software trigger */
6795 
6796 /*****************  Bit definition for DAC_DHR12R1 register  ******************/
6797 #define DAC_DHR12R1_DACC1DHR        ((uint16_t)0x0FFF)                         /*!<DAC channel1 12-bit Right aligned data */
6798 
6799 /*****************  Bit definition for DAC_DHR12L1 register  ******************/
6800 #define DAC_DHR12L1_DACC1DHR        ((uint16_t)0xFFF0)                         /*!<DAC channel1 12-bit Left aligned data */
6801 
6802 /******************  Bit definition for DAC_DHR8R1 register  ******************/
6803 #define DAC_DHR8R1_DACC1DHR         ((uint8_t)0xFF)                            /*!<DAC channel1 8-bit Right aligned data */
6804 
6805 /*****************  Bit definition for DAC_DHR12R2 register  ******************/
6806 #define DAC_DHR12R2_DACC2DHR        ((uint16_t)0x0FFF)                         /*!<DAC channel2 12-bit Right aligned data */
6807 
6808 /*****************  Bit definition for DAC_DHR12L2 register  ******************/
6809 #define DAC_DHR12L2_DACC2DHR        ((uint16_t)0xFFF0)                         /*!<DAC channel2 12-bit Left aligned data */
6810 
6811 /******************  Bit definition for DAC_DHR8R2 register  ******************/
6812 #define DAC_DHR8R2_DACC2DHR         ((uint8_t)0xFF)                            /*!<DAC channel2 8-bit Right aligned data */
6813 
6814 /*****************  Bit definition for DAC_DHR12RD register  ******************/
6815 #define DAC_DHR12RD_DACC1DHR_Pos    (0U)
6816 #define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos)       /*!< 0x00000FFF */
6817 #define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
6818 #define DAC_DHR12RD_DACC2DHR_Pos    (16U)
6819 #define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos)       /*!< 0x0FFF0000 */
6820 #define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
6821 
6822 /*****************  Bit definition for DAC_DHR12LD register  ******************/
6823 #define DAC_DHR12LD_DACC1DHR_Pos    (4U)
6824 #define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
6825 #define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
6826 #define DAC_DHR12LD_DACC2DHR_Pos    (20U)
6827 #define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos)       /*!< 0xFFF00000 */
6828 #define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
6829 
6830 /******************  Bit definition for DAC_DHR8RD register  ******************/
6831 #define DAC_DHR8RD_DACC1DHR_Pos     (0U)
6832 #define DAC_DHR8RD_DACC1DHR_Msk     (0xFFU << DAC_DHR8RD_DACC1DHR_Pos)         /*!< 0x000000FF */
6833 #define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
6834 #define DAC_DHR8RD_DACC2DHR_Pos     (0U)
6835 #define DAC_DHR8RD_DACC2DHR_Msk     (0xFFU << DAC_DHR8RD_DACC2DHR_Pos)         /*!< 0x000000FF */
6836 #define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
6837 
6838 /*******************  Bit definition for DAC_DOR1 register  *******************/
6839 #define DAC_DOR1_DACC1DOR           ((uint16_t)0x0FFF)                         /*!<DAC channel1 data output */
6840 
6841 /*******************  Bit definition for DAC_DOR2 register  *******************/
6842 #define DAC_DOR2_DACC2DOR           ((uint16_t)0x0FFF)                         /*!<DAC channel2 data output */
6843 
6844 /********************  Bit definition for DAC_SR register  ********************/
6845 #define DAC_SR_DMAUDR1_Pos          (13U)
6846 #define DAC_SR_DMAUDR1_Msk          (0x1U << DAC_SR_DMAUDR1_Pos)               /*!< 0x00002000 */
6847 #define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */
6848 #define DAC_SR_CAL_FLAG1_Pos        (14U)
6849 #define DAC_SR_CAL_FLAG1_Msk        (0x1U << DAC_SR_CAL_FLAG1_Pos)             /*!< 0x00004000 */
6850 #define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */
6851 #define DAC_SR_BWST1_Pos            (15U)
6852 #define DAC_SR_BWST1_Msk            (0x4001U << DAC_SR_BWST1_Pos)              /*!< 0x20008000 */
6853 #define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */
6854 
6855 #define DAC_SR_DMAUDR2_Pos          (29U)
6856 #define DAC_SR_DMAUDR2_Msk          (0x1U << DAC_SR_DMAUDR2_Pos)               /*!< 0x20000000 */
6857 #define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */
6858 #define DAC_SR_CAL_FLAG2_Pos        (30U)
6859 #define DAC_SR_CAL_FLAG2_Msk        (0x1U << DAC_SR_CAL_FLAG2_Pos)             /*!< 0x40000000 */
6860 #define DAC_SR_CAL_FLAG2            DAC_SR_CAL_FLAG2_Msk                       /*!<DAC channel2 calibration offset status */
6861 #define DAC_SR_BWST2_Pos            (31U)
6862 #define DAC_SR_BWST2_Msk            (0x1U << DAC_SR_BWST2_Pos)                 /*!< 0x80000000 */
6863 #define DAC_SR_BWST2                DAC_SR_BWST2_Msk                           /*!<DAC channel2 busy writing sample time flag */
6864 
6865 /*******************  Bit definition for DAC_CCR register  ********************/
6866 #define DAC_CCR_OTRIM1_Pos          (0U)
6867 #define DAC_CCR_OTRIM1_Msk          (0x1FU << DAC_CCR_OTRIM1_Pos)              /*!< 0x0000001F */
6868 #define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */
6869 #define DAC_CCR_OTRIM2_Pos          (16U)
6870 #define DAC_CCR_OTRIM2_Msk          (0x1FU << DAC_CCR_OTRIM2_Pos)              /*!< 0x001F0000 */
6871 #define DAC_CCR_OTRIM2              DAC_CCR_OTRIM2_Msk                         /*!<DAC channel2 offset trimming value */
6872 
6873 /*******************  Bit definition for DAC_MCR register  *******************/
6874 #define DAC_MCR_MODE1_Pos           (0U)
6875 #define DAC_MCR_MODE1_Msk           (0x7U << DAC_MCR_MODE1_Pos)                /*!< 0x00000007 */
6876 #define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */
6877 #define DAC_MCR_MODE1_0             (0x1U << DAC_MCR_MODE1_Pos)                /*!< 0x00000001 */
6878 #define DAC_MCR_MODE1_1             (0x2U << DAC_MCR_MODE1_Pos)                /*!< 0x00000002 */
6879 #define DAC_MCR_MODE1_2             (0x4U << DAC_MCR_MODE1_Pos)                /*!< 0x00000004 */
6880 
6881 #define DAC_MCR_MODE2_Pos           (16U)
6882 #define DAC_MCR_MODE2_Msk           (0x7U << DAC_MCR_MODE2_Pos)                /*!< 0x00070000 */
6883 #define DAC_MCR_MODE2               DAC_MCR_MODE2_Msk                          /*!<MODE2[2:0] (DAC channel2 mode) */
6884 #define DAC_MCR_MODE2_0             (0x1U << DAC_MCR_MODE2_Pos)                /*!< 0x00010000 */
6885 #define DAC_MCR_MODE2_1             (0x2U << DAC_MCR_MODE2_Pos)                /*!< 0x00020000 */
6886 #define DAC_MCR_MODE2_2             (0x4U << DAC_MCR_MODE2_Pos)                /*!< 0x00040000 */
6887 
6888 /******************  Bit definition for DAC_SHSR1 register  ******************/
6889 #define DAC_SHSR1_TSAMPLE1_Pos      (0U)
6890 #define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFU << DAC_SHSR1_TSAMPLE1_Pos)         /*!< 0x000003FF */
6891 #define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */
6892 
6893 /******************  Bit definition for DAC_SHSR2 register  ******************/
6894 #define DAC_SHSR1_TSAMPLE2_Pos      (0U)
6895 #define DAC_SHSR1_TSAMPLE2_Msk      (0x3FFU << DAC_SHSR1_TSAMPLE2_Pos)         /*!< 0x000003FF */
6896 #define DAC_SHSR1_TSAMPLE2          DAC_SHSR1_TSAMPLE2_Msk                     /*!<DAC channel2 sample time */
6897 
6898 /******************  Bit definition for DAC_SHHR register  ******************/
6899 #define DAC_SHHR_THOLD1_Pos         (0U)
6900 #define DAC_SHHR_THOLD1_Msk         (0x3FFU << DAC_SHHR_THOLD1_Pos)            /*!< 0x000003FF */
6901 #define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */
6902 #define DAC_SHHR_THOLD2_Pos         (16U)
6903 #define DAC_SHHR_THOLD2_Msk         (0x3FFU << DAC_SHHR_THOLD2_Pos)            /*!< 0x03FF0000 */
6904 #define DAC_SHHR_THOLD2             DAC_SHHR_THOLD2_Msk                        /*!<DAC channel2 hold time */
6905 
6906 /******************  Bit definition for DAC_SHRR register  ******************/
6907 #define DAC_SHRR_TREFRESH1_Pos      (0U)
6908 #define DAC_SHRR_TREFRESH1_Msk      (0xFFU << DAC_SHRR_TREFRESH1_Pos)          /*!< 0x000000FF */
6909 #define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */
6910 #define DAC_SHRR_TREFRESH2_Pos      (16U)
6911 #define DAC_SHRR_TREFRESH2_Msk      (0xFFU << DAC_SHRR_TREFRESH2_Pos)          /*!< 0x00FF0000 */
6912 #define DAC_SHRR_TREFRESH2          DAC_SHRR_TREFRESH2_Msk                     /*!<DAC channel2 refresh time */
6913 
6914 /**********************  Bit definition for DAC_HWCFGR0 register  ***************/
6915 #define DAC_HWCFGR0_DUAL_Pos      (0U)
6916 #define DAC_HWCFGR0_DUAL_Msk      (0xFF << DAC_HWCFGR0_DUAL_Pos)               /*!< 0x0000000F */
6917 #define DAC_HWCFGR0_DUAL          DAC_HWCFGR0_DUAL_Msk                         /*!< Dual DAC capability */
6918 #define DAC_HWCFGR0_LFSR_Pos      (4U)
6919 #define DAC_HWCFGR0_LFSR_Msk      (0xFU << DAC_HWCFGR0_LFSR_Pos)               /*!< 0x000000F0 */
6920 #define DAC_HWCFGR0_LFSR          DAC_HWCFGR0_LFSR_Msk                         /*!< Pseudonoise wave generation capability */
6921 #define DAC_HWCFGR0_TRIANGLE_Pos  (8U)
6922 #define DAC_HWCFGR0_TRIANGLE_Msk  (0xFU << DAC_HWCFGR0_TRIANGLE_Pos)           /*!< 0x00000F00 */
6923 #define DAC_HWCFGR0_TRIANGLE      DAC_HWCFGR0_TRIANGLE_Msk                     /*!< Triangle wave generation capability */
6924 #define DAC_HWCFGR0_SAMPLE_Pos    (12U)
6925 #define DAC_HWCFGR0_SAMPLE_Msk    (0xFU << DAC_HWCFGR0_SAMPLE_Pos)             /*!< 0x0000F000 */
6926 #define DAC_HWCFGR0_SAMPLE        DAC_HWCFGR0_SAMPLE_Msk                       /*!< Sample and Hold mode capability */
6927 #define DAC_HWCFGR0_OR_CFG_Pos    (16U)
6928 #define DAC_HWCFGR0_OR_CFG_Msk    (0xFFU << DAC_HWCFGR0_OR_CFG_Pos)            /*!< 0x00FF0000 */
6929 #define DAC_HWCFGR0_OR_CFG        DAC_HWCFGR0_OR_CFG_Msk                       /*!< option register bit width */
6930 
6931 /********************  Bit definition for DAC_VERR register********************/
6932 #define DAC_VERR_MINREV_Pos        (0U)
6933 #define DAC_VERR_MINREV_Msk        (0xFU << DAC_VERR_MINREV_Pos)           /*!< 0x0000000F */
6934 #define DAC_VERR_MINREV            DAC_VERR_MINREV_Msk                     /*!< MAJREV[3:0] bits (Minor revision) */
6935 #define DAC_VERR_MAJREV_Pos        (4U)
6936 #define DAC_VERR_MAJREV_Msk        (0xFU << DAC_VERR_MAJREV_Pos)           /*!< 0x000000F0 */
6937 #define DAC_VERR_MAJREV            DAC_VERR_MAJREV_Msk                     /*!< MINREV[3:0] bits (Major revision) */
6938 
6939 /**********************  Bit definition for DAC_IPIDR register  ****************/
6940 #define DAC_IPIDR_IPID_Pos       (0U)
6941 #define DAC_IPIDR_IPID_Msk       (0xFFFFFFFFU << DAC_IPIDR_IPID_Pos)         /*!< 0xFFFFFFFF */
6942 #define DAC_IPIDR_IPID           DAC_IPIDR_IPID_Msk                          /*!< IP Identification */
6943 
6944 /**********************  Bit definition for DAC_SIDR register  *****************/
6945 #define DAC_SIDR_SID_Pos         (0U)
6946 #define DAC_SIDR_SID_Msk         (0xFFFFFFFFU << DAC_SIDR_SID_Pos)           /*!< 0xFFFFFFFF */
6947 #define DAC_SIDR_SID             DAC_SIDR_SID_Msk                            /*!< IP size identification */
6948 
6949 /******************************************************************************/
6950 /*                                                                            */
6951 /*                                DBG                                         */
6952 /*                                                                            */
6953 /******************************************************************************/
6954 
6955 /********************  Bit definition for DBGMCU_IDCODE register  *************/
6956 #define DBGMCU_IDCODE_DEV_ID_Pos              (0U)
6957 #define DBGMCU_IDCODE_DEV_ID_Msk              (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
6958 #define DBGMCU_IDCODE_DEV_ID                  DBGMCU_IDCODE_DEV_ID_Msk
6959 #define DBGMCU_IDCODE_REV_ID_Pos              (16U)
6960 #define DBGMCU_IDCODE_REV_ID_Msk              (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
6961 #define DBGMCU_IDCODE_REV_ID                  DBGMCU_IDCODE_REV_ID_Msk
6962 
6963 /********************  Bit definition for DBGMCU_CR register  *****************/
6964 #define DBGMCU_CR_DBG_SLEEP_Pos               (0U)
6965 #define DBGMCU_CR_DBG_SLEEP_Msk               (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
6966 #define DBGMCU_CR_DBG_SLEEP                   DBGMCU_CR_DBG_SLEEP_Msk
6967 #define DBGMCU_CR_DBG_STOP_Pos                (1U)
6968 #define DBGMCU_CR_DBG_STOP_Msk                (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
6969 #define DBGMCU_CR_DBG_STOP                    DBGMCU_CR_DBG_STOP_Msk
6970 #define DBGMCU_CR_DBG_STANDBY_Pos             (2U)
6971 #define DBGMCU_CR_DBG_STANDBY_Msk             (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
6972 #define DBGMCU_CR_DBG_STANDBY                 DBGMCU_CR_DBG_STANDBY_Msk
6973 #define DBGMCU_CR_DBG_WDFZCTL_Pos             (24U)
6974 #define DBGMCU_CR_DBG_WDFZCTL_Msk             (0x1U << DBGMCU_CR_DBG_WDFZCTL_Pos) /*!< 0x01000000 */
6975 #define DBGMCU_CR_DBG_WDFZCTL                 DBGMCU_CR_DBG_WDFZCTL_Msk
6976 #define DBGMCU_CR_DBG_TRGOEN_Pos              (28U)
6977 #define DBGMCU_CR_DBG_TRGOEN_Msk              (0x1U << DBGMCU_CR_DBG_TRGOEN_Pos) /*!< 0x10000000 */
6978 #define DBGMCU_CR_DBG_TRGOEN                  DBGMCU_CR_DBG_TRGOEN_Msk
6979 
6980 /********************  Bit definition for APB4FZ register  ************/
6981 #define DBGMCU_APB4_FZ_DBG_IWDG2_STOP_Pos     (2U)
6982 #define DBGMCU_APB4_FZ_DBG_IWDG2_STOP_Msk     (0x1U << DBGMCU_APB4_FZ_DBG_IWDG2_STOP_Pos) /*!< 0x00000004 */
6983 #define DBGMCU_APB4_FZ_DBG_IWDG2_STOP         DBGMCU_APB4_FZ_DBG_IWDG2_STOP_Msk
6984 
6985 /********************  Bit definition for APB1FZ register  ************/
6986 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos      (0U)
6987 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk      (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
6988 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP          DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
6989 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos      (1U)
6990 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk      (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
6991 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP          DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
6992 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos      (2U)
6993 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk      (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
6994 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP          DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
6995 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos      (3U)
6996 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk      (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
6997 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP          DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
6998 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos      (4U)
6999 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk      (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
7000 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP          DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
7001 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos      (5U)
7002 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk      (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
7003 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP          DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
7004 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos     (6U)
7005 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk     (0x1U << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
7006 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP         DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
7007 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos     (7U)
7008 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk     (0x1U << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
7009 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP         DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
7010 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos     (8U)
7011 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk     (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
7012 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP         DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
7013 #define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Pos    (9U)
7014 #define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Msk    (0x1U << DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Pos) /*!< 0x00000200 */
7015 #define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP        DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Msk
7016 #define DBGMCU_APB1_FZ_DBG_WWDG1_STOP_Pos     (10U)
7017 #define DBGMCU_APB1_FZ_DBG_WWDG1_STOP_Msk     (0x1U << DBGMCU_APB1_FZ_DBG_WWDG1_STOP_Pos) /*!< 0x00000400 */
7018 #define DBGMCU_APB1_FZ_DBG_WWDG1_STOP         DBGMCU_APB1_FZ_DBG_WWDG1_STOP_Msk
7019 #define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos      (18U)
7020 #define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk      (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00040000 */
7021 #define DBGMCU_APB1_FZ_DBG_I2C1_STOP          DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk
7022 #define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos      (19U)
7023 #define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk      (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos) /*!< 0x00080000 */
7024 #define DBGMCU_APB1_FZ_DBG_I2C2_STOP          DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk
7025 #define DBGMCU_APB1_FZ_DBG_I2C3_STOP_Pos      (20U)
7026 #define DBGMCU_APB1_FZ_DBG_I2C3_STOP_Msk      (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_STOP_Pos) /*!< 0x00100000 */
7027 #define DBGMCU_APB1_FZ_DBG_I2C3_STOP          DBGMCU_APB1_FZ_DBG_I2C3_STOP_Msk
7028 #define DBGMCU_APB1_FZ_DBG_I2C5_STOP_Pos      (21U)
7029 #define DBGMCU_APB1_FZ_DBG_I2C5_STOP_Msk      (0x1U << DBGMCU_APB1_FZ_DBG_I2C5_STOP_Pos) /*!< 0x00200000 */
7030 #define DBGMCU_APB1_FZ_DBG_I2C5_STOP          DBGMCU_APB1_FZ_DBG_I2C5_STOP_Msk
7031 
7032 /********************  Bit definition for APB2FZ register  ************/
7033 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos      (0U)
7034 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk      (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
7035 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP          DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
7036 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos      (1U)
7037 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk      (0x1U << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
7038 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP          DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
7039 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos     (6U)
7040 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk     (0x1U << DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos) /*!< 0x00000040 */
7041 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP         DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk
7042 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos     (7U)
7043 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk     (0x1U << DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos) /*!< 0x00000080 */
7044 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP         DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk
7045 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos     (8U)
7046 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk     (0x1U << DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos) /*!< 0x00000100 */
7047 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP         DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk
7048 #define DBGMCU_APB2_FZ_DBG_FDCAN_STOP_Pos     (15U)
7049 #define DBGMCU_APB2_FZ_DBG_FDCAN_STOP_Msk     (0x1U << DBGMCU_APB2_FZ_DBG_FDCAN_STOP_Pos) /*!< 0x00008000 */
7050 #define DBGMCU_APB2_FZ_DBG_FDCAN_STOP         DBGMCU_APB2_FZ_DBG_FDCAN_STOP_Msk
7051 
7052 /********************  Bit definition for APB3FZ register  ************/
7053 #define DBGMCU_APB3_FZ_DBG_LPTIM2_STOP_Pos    (1U)
7054 #define DBGMCU_APB3_FZ_DBG_LPTIM2_STOP_Msk    (0x1U << DBGMCU_APB3_FZ_DBG_LPTIM2_STOP_Pos) /*!< 0x00000002 */
7055 #define DBGMCU_APB3_FZ_DBG_LPTIM2_STOP        DBGMCU_APB3_FZ_DBG_LPTIM2_STOP_Msk
7056 #define DBGMCU_APB3_FZ_DBG_LPTIM3_STOP_Pos    (2U)
7057 #define DBGMCU_APB3_FZ_DBG_LPTIM3_STOP_Msk    (0x1U << DBGMCU_APB3_FZ_DBG_LPTIM3_STOP_Pos) /*!< 0x00000004 */
7058 #define DBGMCU_APB3_FZ_DBG_LPTIM3_STOP        DBGMCU_APB3_FZ_DBG_LPTIM3_STOP_Msk
7059 #define DBGMCU_APB3_FZ_DBG_LPTIM4_STOP_Pos    (3U)
7060 #define DBGMCU_APB3_FZ_DBG_LPTIM4_STOP_Msk    (0x1U << DBGMCU_APB3_FZ_DBG_LPTIM4_STOP_Pos) /*!< 0x00000008 */
7061 #define DBGMCU_APB3_FZ_DBG_LPTIM4_STOP        DBGMCU_APB3_FZ_DBG_LPTIM4_STOP_Msk
7062 #define DBGMCU_APB3_FZ_DBG_LPTIM5_STOP_Pos    (4U)
7063 #define DBGMCU_APB3_FZ_DBG_LPTIM5_STOP_Msk    (0x1U << DBGMCU_APB3_FZ_DBG_LPTIM5_STOP_Pos) /*!< 0x00000010 */
7064 #define DBGMCU_APB3_FZ_DBG_LPTIM5_STOP        DBGMCU_APB3_FZ_DBG_LPTIM5_STOP_Msk
7065 
7066 /********************  Bit definition for APB5FZ register  ************/
7067 #define DBGMCU_APB5_FZ_DBG_I2C4_STOP_Pos      (2U)
7068 #define DBGMCU_APB5_FZ_DBG_I2C4_STOP_Msk      (0x1U << DBGMCU_APB5_FZ_DBG_I2C4_STOP_Pos) /*!< 0x00000004 */
7069 #define DBGMCU_APB5_FZ_DBG_I2C4_STOP          DBGMCU_APB5_FZ_DBG_I2C4_STOP_Msk
7070 #define DBGMCU_APB5_FZ_DBG_IWDG1_STOP_Pos     (3U)
7071 #define DBGMCU_APB5_FZ_DBG_IWDG1_STOP_Msk     (0x1U << DBGMCU_APB5_FZ_DBG_IWDG1_STOP_Pos) /*!< 0x00000008 */
7072 #define DBGMCU_APB5_FZ_DBG_IWDG1_STOP         DBGMCU_APB5_FZ_DBG_IWDG1_STOP_Msk
7073 #define DBGMCU_APB5_FZ_DBG_RTC_STOP_Pos       (4U)
7074 #define DBGMCU_APB5_FZ_DBG_RTC_STOP_Msk       (0x1U << DBGMCU_APB5_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000010 */
7075 #define DBGMCU_APB5_FZ_DBG_RTC_STOP           DBGMCU_APB5_FZ_DBG_RTC_STOP_Msk
7076 #define DBGMCU_APB5_FZ_DBG_I2C6_STOP_Pos      (9U)
7077 #define DBGMCU_APB5_FZ_DBG_I2C6_STOP_Msk      (0x1U << DBGMCU_APB5_FZ_DBG_I2C6_STOP_Pos) /*!< 0x00000200 */
7078 #define DBGMCU_APB5_FZ_DBG_I2C6_STOP          DBGMCU_APB5_FZ_DBG_I2C6_STOP_Msk
7079 
7080 /******************************************************************************/
7081 /*                                                                            */
7082 /*                                    DCMI                                    */
7083 /*                                                                            */
7084 /******************************************************************************/
7085 /********************  Bits definition for DCMI_CR register  ******************/
7086 #define DCMI_CR_CAPTURE_Pos        (0U)
7087 #define DCMI_CR_CAPTURE_Msk        (0x1UL << DCMI_CR_CAPTURE_Pos)              /*!< 0x00000001 */
7088 #define DCMI_CR_CAPTURE            DCMI_CR_CAPTURE_Msk
7089 #define DCMI_CR_CM_Pos             (1U)
7090 #define DCMI_CR_CM_Msk             (0x1UL << DCMI_CR_CM_Pos)                   /*!< 0x00000002 */
7091 #define DCMI_CR_CM                 DCMI_CR_CM_Msk
7092 #define DCMI_CR_CROP_Pos           (2U)
7093 #define DCMI_CR_CROP_Msk           (0x1UL << DCMI_CR_CROP_Pos)                 /*!< 0x00000004 */
7094 #define DCMI_CR_CROP               DCMI_CR_CROP_Msk
7095 #define DCMI_CR_JPEG_Pos           (3U)
7096 #define DCMI_CR_JPEG_Msk           (0x1UL << DCMI_CR_JPEG_Pos)                 /*!< 0x00000008 */
7097 #define DCMI_CR_JPEG               DCMI_CR_JPEG_Msk
7098 #define DCMI_CR_ESS_Pos            (4U)
7099 #define DCMI_CR_ESS_Msk            (0x1UL << DCMI_CR_ESS_Pos)                  /*!< 0x00000010 */
7100 #define DCMI_CR_ESS                DCMI_CR_ESS_Msk
7101 #define DCMI_CR_PCKPOL_Pos         (5U)
7102 #define DCMI_CR_PCKPOL_Msk         (0x1UL << DCMI_CR_PCKPOL_Pos)               /*!< 0x00000020 */
7103 #define DCMI_CR_PCKPOL             DCMI_CR_PCKPOL_Msk
7104 #define DCMI_CR_HSPOL_Pos          (6U)
7105 #define DCMI_CR_HSPOL_Msk          (0x1UL << DCMI_CR_HSPOL_Pos)                /*!< 0x00000040 */
7106 #define DCMI_CR_HSPOL              DCMI_CR_HSPOL_Msk
7107 #define DCMI_CR_VSPOL_Pos          (7U)
7108 #define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                /*!< 0x00000080 */
7109 #define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk
7110 #define DCMI_CR_FCRC_0             ((uint32_t)0x00000100U)
7111 #define DCMI_CR_FCRC_1             ((uint32_t)0x00000200U)
7112 #define DCMI_CR_EDM_0              ((uint32_t)0x00000400U)
7113 #define DCMI_CR_EDM_1              ((uint32_t)0x00000800U)
7114 #define DCMI_CR_CRE_Pos            (12U)
7115 #define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                  /*!< 0x00001000 */
7116 #define DCMI_CR_CRE                DCMI_CR_CRE_Msk
7117 #define DCMI_CR_ENABLE_Pos         (14U)
7118 #define DCMI_CR_ENABLE_Msk         (0x1UL << DCMI_CR_ENABLE_Pos)               /*!< 0x00004000 */
7119 #define DCMI_CR_ENABLE             DCMI_CR_ENABLE_Msk
7120 #define DCMI_CR_BSM_Pos            (16U)
7121 #define DCMI_CR_BSM_Msk            (0x3UL << DCMI_CR_BSM_Pos)                  /*!< 0x00030000 */
7122 #define DCMI_CR_BSM                DCMI_CR_BSM_Msk
7123 #define DCMI_CR_BSM_0              (0x1U << DCMI_CR_BSM_Pos)                   /*!< 0x00010000 */
7124 #define DCMI_CR_BSM_1              (0x2U << DCMI_CR_BSM_Pos)                   /*!< 0x00020000 */
7125 #define DCMI_CR_OEBS_Pos           (18U)
7126 #define DCMI_CR_OEBS_Msk           (0x1UL << DCMI_CR_OEBS_Pos)                 /*!< 0x00040000 */
7127 #define DCMI_CR_OEBS               DCMI_CR_OEBS_Msk
7128 #define DCMI_CR_LSM_Pos            (19U)
7129 #define DCMI_CR_LSM_Msk            (0x1UL << DCMI_CR_LSM_Pos)                  /*!< 0x00080000 */
7130 #define DCMI_CR_LSM                DCMI_CR_LSM_Msk
7131 #define DCMI_CR_OELS_Pos           (20U)
7132 #define DCMI_CR_OELS_Msk           (0x1UL << DCMI_CR_OELS_Pos)                 /*!< 0x00100000 */
7133 #define DCMI_CR_OELS               DCMI_CR_OELS_Msk
7134 
7135 /********************  Bits definition for DCMI_SR register  ******************/
7136 #define DCMI_SR_HSYNC_Pos          (0U)
7137 #define DCMI_SR_HSYNC_Msk          (0x1UL << DCMI_SR_HSYNC_Pos)                /*!< 0x00000001 */
7138 #define DCMI_SR_HSYNC              DCMI_SR_HSYNC_Msk
7139 #define DCMI_SR_VSYNC_Pos          (1U)
7140 #define DCMI_SR_VSYNC_Msk          (0x1UL << DCMI_SR_VSYNC_Pos)                /*!< 0x00000002 */
7141 #define DCMI_SR_VSYNC              DCMI_SR_VSYNC_Msk
7142 #define DCMI_SR_FNE_Pos            (2U)
7143 #define DCMI_SR_FNE_Msk            (0x1UL << DCMI_SR_FNE_Pos)                  /*!< 0x00000004 */
7144 #define DCMI_SR_FNE                DCMI_SR_FNE_Msk
7145 
7146 /********************  Bits definition for DCMI_RIS register   ****************/
7147 #define DCMI_RIS_FRAME_RIS_Pos     (0U)
7148 #define DCMI_RIS_FRAME_RIS_Msk     (0x1UL << DCMI_RIS_FRAME_RIS_Pos)           /*!< 0x00000001 */
7149 #define DCMI_RIS_FRAME_RIS         DCMI_RIS_FRAME_RIS_Msk
7150 #define DCMI_RIS_OVR_RIS_Pos       (1U)
7151 #define DCMI_RIS_OVR_RIS_Msk       (0x1UL << DCMI_RIS_OVR_RIS_Pos)             /*!< 0x00000002 */
7152 #define DCMI_RIS_OVR_RIS           DCMI_RIS_OVR_RIS_Msk
7153 #define DCMI_RIS_ERR_RIS_Pos       (2U)
7154 #define DCMI_RIS_ERR_RIS_Msk       (0x1UL << DCMI_RIS_ERR_RIS_Pos)             /*!< 0x00000004 */
7155 #define DCMI_RIS_ERR_RIS           DCMI_RIS_ERR_RIS_Msk
7156 #define DCMI_RIS_VSYNC_RIS_Pos     (3U)
7157 #define DCMI_RIS_VSYNC_RIS_Msk     (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)           /*!< 0x00000008 */
7158 #define DCMI_RIS_VSYNC_RIS         DCMI_RIS_VSYNC_RIS_Msk
7159 #define DCMI_RIS_LINE_RIS_Pos      (4U)
7160 #define DCMI_RIS_LINE_RIS_Msk      (0x1UL << DCMI_RIS_LINE_RIS_Pos)            /*!< 0x00000010 */
7161 #define DCMI_RIS_LINE_RIS          DCMI_RIS_LINE_RIS_Msk
7162 
7163 /********************  Bits definition for DCMI_IER register  *****************/
7164 #define DCMI_IER_FRAME_IE_Pos      (0U)
7165 #define DCMI_IER_FRAME_IE_Msk      (0x1UL << DCMI_IER_FRAME_IE_Pos)            /*!< 0x00000001 */
7166 #define DCMI_IER_FRAME_IE          DCMI_IER_FRAME_IE_Msk
7167 #define DCMI_IER_OVR_IE_Pos        (1U)
7168 #define DCMI_IER_OVR_IE_Msk        (0x1UL << DCMI_IER_OVR_IE_Pos)              /*!< 0x00000002 */
7169 #define DCMI_IER_OVR_IE            DCMI_IER_OVR_IE_Msk
7170 #define DCMI_IER_ERR_IE_Pos        (2U)
7171 #define DCMI_IER_ERR_IE_Msk        (0x1UL << DCMI_IER_ERR_IE_Pos)              /*!< 0x00000004 */
7172 #define DCMI_IER_ERR_IE            DCMI_IER_ERR_IE_Msk
7173 #define DCMI_IER_VSYNC_IE_Pos      (3U)
7174 #define DCMI_IER_VSYNC_IE_Msk      (0x1UL << DCMI_IER_VSYNC_IE_Pos)            /*!< 0x00000008 */
7175 #define DCMI_IER_VSYNC_IE          DCMI_IER_VSYNC_IE_Msk
7176 #define DCMI_IER_LINE_IE_Pos       (4U)
7177 #define DCMI_IER_LINE_IE_Msk       (0x1UL << DCMI_IER_LINE_IE_Pos)             /*!< 0x00000010 */
7178 #define DCMI_IER_LINE_IE           DCMI_IER_LINE_IE_Msk
7179 
7180 
7181 /********************  Bits definition for DCMI_MIS register  *****************/
7182 #define DCMI_MIS_FRAME_MIS_Pos     (0U)
7183 #define DCMI_MIS_FRAME_MIS_Msk     (0x1UL << DCMI_MIS_FRAME_MIS_Pos)           /*!< 0x00000001 */
7184 #define DCMI_MIS_FRAME_MIS         DCMI_MIS_FRAME_MIS_Msk
7185 #define DCMI_MIS_OVR_MIS_Pos       (1U)
7186 #define DCMI_MIS_OVR_MIS_Msk       (0x1UL << DCMI_MIS_OVR_MIS_Pos)             /*!< 0x00000002 */
7187 #define DCMI_MIS_OVR_MIS           DCMI_MIS_OVR_MIS_Msk
7188 #define DCMI_MIS_ERR_MIS_Pos       (2U)
7189 #define DCMI_MIS_ERR_MIS_Msk       (0x1UL << DCMI_MIS_ERR_MIS_Pos)             /*!< 0x00000004 */
7190 #define DCMI_MIS_ERR_MIS           DCMI_MIS_ERR_MIS_Msk
7191 #define DCMI_MIS_VSYNC_MIS_Pos     (3U)
7192 #define DCMI_MIS_VSYNC_MIS_Msk     (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)           /*!< 0x00000008 */
7193 #define DCMI_MIS_VSYNC_MIS         DCMI_MIS_VSYNC_MIS_Msk
7194 #define DCMI_MIS_LINE_MIS_Pos      (4U)
7195 #define DCMI_MIS_LINE_MIS_Msk      (0x1UL << DCMI_MIS_LINE_MIS_Pos)            /*!< 0x00000010 */
7196 #define DCMI_MIS_LINE_MIS          DCMI_MIS_LINE_MIS_Msk
7197 
7198 
7199 /********************  Bits definition for DCMI_ICR register  *****************/
7200 #define DCMI_ICR_FRAME_ISC_Pos     (0U)
7201 #define DCMI_ICR_FRAME_ISC_Msk     (0x1UL << DCMI_ICR_FRAME_ISC_Pos)           /*!< 0x00000001 */
7202 #define DCMI_ICR_FRAME_ISC         DCMI_ICR_FRAME_ISC_Msk
7203 #define DCMI_ICR_OVR_ISC_Pos       (1U)
7204 #define DCMI_ICR_OVR_ISC_Msk       (0x1UL << DCMI_ICR_OVR_ISC_Pos)             /*!< 0x00000002 */
7205 #define DCMI_ICR_OVR_ISC           DCMI_ICR_OVR_ISC_Msk
7206 #define DCMI_ICR_ERR_ISC_Pos       (2U)
7207 #define DCMI_ICR_ERR_ISC_Msk       (0x1UL << DCMI_ICR_ERR_ISC_Pos)             /*!< 0x00000004 */
7208 #define DCMI_ICR_ERR_ISC           DCMI_ICR_ERR_ISC_Msk
7209 #define DCMI_ICR_VSYNC_ISC_Pos     (3U)
7210 #define DCMI_ICR_VSYNC_ISC_Msk     (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)           /*!< 0x00000008 */
7211 #define DCMI_ICR_VSYNC_ISC         DCMI_ICR_VSYNC_ISC_Msk
7212 #define DCMI_ICR_LINE_ISC_Pos      (4U)
7213 #define DCMI_ICR_LINE_ISC_Msk      (0x1UL << DCMI_ICR_LINE_ISC_Pos)            /*!< 0x00000010 */
7214 #define DCMI_ICR_LINE_ISC          DCMI_ICR_LINE_ISC_Msk
7215 
7216 
7217 /********************  Bits definition for DCMI_ESCR register  ******************/
7218 #define DCMI_ESCR_FSC_Pos          (0U)
7219 #define DCMI_ESCR_FSC_Msk          (0xFFUL << DCMI_ESCR_FSC_Pos)               /*!< 0x000000FF */
7220 #define DCMI_ESCR_FSC              DCMI_ESCR_FSC_Msk
7221 #define DCMI_ESCR_LSC_Pos          (8U)
7222 #define DCMI_ESCR_LSC_Msk          (0xFFUL << DCMI_ESCR_LSC_Pos)               /*!< 0x0000FF00 */
7223 #define DCMI_ESCR_LSC              DCMI_ESCR_LSC_Msk
7224 #define DCMI_ESCR_LEC_Pos          (16U)
7225 #define DCMI_ESCR_LEC_Msk          (0xFFUL << DCMI_ESCR_LEC_Pos)               /*!< 0x00FF0000 */
7226 #define DCMI_ESCR_LEC              DCMI_ESCR_LEC_Msk
7227 #define DCMI_ESCR_FEC_Pos          (24U)
7228 #define DCMI_ESCR_FEC_Msk          (0xFFUL << DCMI_ESCR_FEC_Pos)               /*!< 0xFF000000 */
7229 #define DCMI_ESCR_FEC              DCMI_ESCR_FEC_Msk
7230 
7231 /********************  Bits definition for DCMI_ESUR register  ******************/
7232 #define DCMI_ESUR_FSU_Pos          (0U)
7233 #define DCMI_ESUR_FSU_Msk          (0xFFUL << DCMI_ESUR_FSU_Pos)               /*!< 0x000000FF */
7234 #define DCMI_ESUR_FSU              DCMI_ESUR_FSU_Msk
7235 #define DCMI_ESUR_LSU_Pos          (8U)
7236 #define DCMI_ESUR_LSU_Msk          (0xFFUL << DCMI_ESUR_LSU_Pos)               /*!< 0x0000FF00 */
7237 #define DCMI_ESUR_LSU              DCMI_ESUR_LSU_Msk
7238 #define DCMI_ESUR_LEU_Pos          (16U)
7239 #define DCMI_ESUR_LEU_Msk          (0xFFUL << DCMI_ESUR_LEU_Pos)               /*!< 0x00FF0000 */
7240 #define DCMI_ESUR_LEU              DCMI_ESUR_LEU_Msk
7241 #define DCMI_ESUR_FEU_Pos          (24U)
7242 #define DCMI_ESUR_FEU_Msk          (0xFFUL << DCMI_ESUR_FEU_Pos)               /*!< 0xFF000000 */
7243 #define DCMI_ESUR_FEU              DCMI_ESUR_FEU_Msk
7244 
7245 /********************  Bits definition for DCMI_CWSTRT register  ******************/
7246 #define DCMI_CWSTRT_HOFFCNT_Pos    (0U)
7247 #define DCMI_CWSTRT_HOFFCNT_Msk    (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)       /*!< 0x00003FFF */
7248 #define DCMI_CWSTRT_HOFFCNT        DCMI_CWSTRT_HOFFCNT_Msk
7249 #define DCMI_CWSTRT_VST_Pos        (16U)
7250 #define DCMI_CWSTRT_VST_Msk        (0x1FFFUL << DCMI_CWSTRT_VST_Pos)           /*!< 0x1FFF0000 */
7251 #define DCMI_CWSTRT_VST            DCMI_CWSTRT_VST_Msk
7252 
7253 /********************  Bits definition for DCMI_CWSIZE register  ******************/
7254 #define DCMI_CWSIZE_CAPCNT_Pos     (0U)
7255 #define DCMI_CWSIZE_CAPCNT_Msk     (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)        /*!< 0x00003FFF */
7256 #define DCMI_CWSIZE_CAPCNT         DCMI_CWSIZE_CAPCNT_Msk
7257 #define DCMI_CWSIZE_VLINE_Pos      (16U)
7258 #define DCMI_CWSIZE_VLINE_Msk      (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)         /*!< 0x3FFF0000 */
7259 #define DCMI_CWSIZE_VLINE          DCMI_CWSIZE_VLINE_Msk
7260 
7261 /********************  Bits definition for DCMI_DR register  ******************/
7262 #define DCMI_DR_BYTE0_Pos          (0U)
7263 #define DCMI_DR_BYTE0_Msk          (0xFFUL << DCMI_DR_BYTE0_Pos)               /*!< 0x000000FF */
7264 #define DCMI_DR_BYTE0              DCMI_DR_BYTE0_Msk
7265 #define DCMI_DR_BYTE1_Pos          (8U)
7266 #define DCMI_DR_BYTE1_Msk          (0xFFUL << DCMI_DR_BYTE1_Pos)               /*!< 0x0000FF00 */
7267 #define DCMI_DR_BYTE1              DCMI_DR_BYTE1_Msk
7268 #define DCMI_DR_BYTE2_Pos          (16U)
7269 #define DCMI_DR_BYTE2_Msk          (0xFFUL << DCMI_DR_BYTE2_Pos)               /*!< 0x00FF0000 */
7270 #define DCMI_DR_BYTE2              DCMI_DR_BYTE2_Msk
7271 #define DCMI_DR_BYTE3_Pos          (24U)
7272 #define DCMI_DR_BYTE3_Msk          (0xFFUL << DCMI_DR_BYTE3_Pos)               /*!< 0xFF000000 */
7273 #define DCMI_DR_BYTE3              DCMI_DR_BYTE3_Msk
7274 
7275 /******************************************************************************/
7276 /*                                                                            */
7277 /*                 Digital Filter for Sigma Delta Modulators                  */
7278 /*                                                                            */
7279 /******************************************************************************/
7280 
7281 /****************   DFSDM channel configuration registers  ********************/
7282 
7283 /***************  Bit definition for DFSDM_CHCFGR1 register  ******************/
7284 #define DFSDM_CHCFGR1_DFSDMEN_Pos       (31U)
7285 #define DFSDM_CHCFGR1_DFSDMEN_Msk       (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos)   /*!< 0x80000000 */
7286 #define DFSDM_CHCFGR1_DFSDMEN           DFSDM_CHCFGR1_DFSDMEN_Msk              /*!< Global enable for DFSDM interface */
7287 #define DFSDM_CHCFGR1_CKOUTSRC_Pos      (30U)
7288 #define DFSDM_CHCFGR1_CKOUTSRC_Msk      (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos)  /*!< 0x40000000 */
7289 #define DFSDM_CHCFGR1_CKOUTSRC          DFSDM_CHCFGR1_CKOUTSRC_Msk             /*!< Output serial clock source selection */
7290 #define DFSDM_CHCFGR1_CKOUTDIV_Pos      (16U)
7291 #define DFSDM_CHCFGR1_CKOUTDIV_Msk      (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */
7292 #define DFSDM_CHCFGR1_CKOUTDIV          DFSDM_CHCFGR1_CKOUTDIV_Msk             /*!< CKOUTDIV[7:0] output serial clock divider */
7293 #define DFSDM_CHCFGR1_DATPACK_Pos       (14U)
7294 #define DFSDM_CHCFGR1_DATPACK_Msk       (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos)   /*!< 0x0000C000 */
7295 #define DFSDM_CHCFGR1_DATPACK           DFSDM_CHCFGR1_DATPACK_Msk              /*!< DATPACK[1:0] Data packing mode */
7296 #define DFSDM_CHCFGR1_DATPACK_1         (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos)   /*!< 0x00008000 */
7297 #define DFSDM_CHCFGR1_DATPACK_0         (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos)   /*!< 0x00004000 */
7298 #define DFSDM_CHCFGR1_DATMPX_Pos        (12U)
7299 #define DFSDM_CHCFGR1_DATMPX_Msk        (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos)    /*!< 0x00003000 */
7300 #define DFSDM_CHCFGR1_DATMPX            DFSDM_CHCFGR1_DATMPX_Msk               /*!< DATMPX[1:0] Input data multiplexer for channel y */
7301 #define DFSDM_CHCFGR1_DATMPX_1          (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos)    /*!< 0x00002000 */
7302 #define DFSDM_CHCFGR1_DATMPX_0          (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos)    /*!< 0x00001000 */
7303 #define DFSDM_CHCFGR1_CHINSEL_Pos       (8U)
7304 #define DFSDM_CHCFGR1_CHINSEL_Msk       (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos)   /*!< 0x00000100 */
7305 #define DFSDM_CHCFGR1_CHINSEL           DFSDM_CHCFGR1_CHINSEL_Msk              /*!< Serial inputs selection for channel y */
7306 #define DFSDM_CHCFGR1_CHEN_Pos          (7U)
7307 #define DFSDM_CHCFGR1_CHEN_Msk          (0x1UL << DFSDM_CHCFGR1_CHEN_Pos)      /*!< 0x00000080 */
7308 #define DFSDM_CHCFGR1_CHEN              DFSDM_CHCFGR1_CHEN_Msk                 /*!< Channel y enable */
7309 #define DFSDM_CHCFGR1_CKABEN_Pos        (6U)
7310 #define DFSDM_CHCFGR1_CKABEN_Msk        (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos)    /*!< 0x00000040 */
7311 #define DFSDM_CHCFGR1_CKABEN            DFSDM_CHCFGR1_CKABEN_Msk               /*!< Clock absence detector enable on channel y */
7312 #define DFSDM_CHCFGR1_SCDEN_Pos         (5U)
7313 #define DFSDM_CHCFGR1_SCDEN_Msk         (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos)     /*!< 0x00000020 */
7314 #define DFSDM_CHCFGR1_SCDEN             DFSDM_CHCFGR1_SCDEN_Msk                /*!< Short circuit detector enable on channel y */
7315 #define DFSDM_CHCFGR1_SPICKSEL_Pos      (2U)
7316 #define DFSDM_CHCFGR1_SPICKSEL_Msk      (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos)  /*!< 0x0000000C */
7317 #define DFSDM_CHCFGR1_SPICKSEL          DFSDM_CHCFGR1_SPICKSEL_Msk             /*!< SPICKSEL[1:0] SPI clock select for channel y */
7318 #define DFSDM_CHCFGR1_SPICKSEL_1        (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos)  /*!< 0x00000008 */
7319 #define DFSDM_CHCFGR1_SPICKSEL_0        (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos)  /*!< 0x00000004 */
7320 #define DFSDM_CHCFGR1_SITP_Pos          (0U)
7321 #define DFSDM_CHCFGR1_SITP_Msk          (0x3UL << DFSDM_CHCFGR1_SITP_Pos)      /*!< 0x00000003 */
7322 #define DFSDM_CHCFGR1_SITP              DFSDM_CHCFGR1_SITP_Msk                 /*!< SITP[1:0] Serial interface type for channel y */
7323 #define DFSDM_CHCFGR1_SITP_1            (0x2UL << DFSDM_CHCFGR1_SITP_Pos)      /*!< 0x00000002 */
7324 #define DFSDM_CHCFGR1_SITP_0            (0x1UL << DFSDM_CHCFGR1_SITP_Pos)      /*!< 0x00000001 */
7325 
7326 /***************  Bit definition for DFSDM_CHCFGR2 register  ******************/
7327 #define DFSDM_CHCFGR2_OFFSET_Pos        (8U)
7328 #define DFSDM_CHCFGR2_OFFSET_Msk        (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos)/*!< 0xFFFFFF00 */
7329 #define DFSDM_CHCFGR2_OFFSET            DFSDM_CHCFGR2_OFFSET_Msk               /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
7330 #define DFSDM_CHCFGR2_DTRBS_Pos         (3U)
7331 #define DFSDM_CHCFGR2_DTRBS_Msk         (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos)    /*!< 0x000000F8 */
7332 #define DFSDM_CHCFGR2_DTRBS             DFSDM_CHCFGR2_DTRBS_Msk                /*!< DTRBS[4:0] Data right bit-shift for channel y */
7333 
7334 /****************  Bit definition for DFSDM_CHAWSCDR register *****************/
7335 #define DFSDM_CHAWSCDR_AWFORD_Pos       (22U)
7336 #define DFSDM_CHAWSCDR_AWFORD_Msk       (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos)   /*!< 0x00C00000 */
7337 #define DFSDM_CHAWSCDR_AWFORD           DFSDM_CHAWSCDR_AWFORD_Msk              /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
7338 #define DFSDM_CHAWSCDR_AWFORD_1         (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos)   /*!< 0x00800000 */
7339 #define DFSDM_CHAWSCDR_AWFORD_0         (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos)   /*!< 0x00400000 */
7340 #define DFSDM_CHAWSCDR_AWFOSR_Pos       (16U)
7341 #define DFSDM_CHAWSCDR_AWFOSR_Msk       (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos)  /*!< 0x001F0000 */
7342 #define DFSDM_CHAWSCDR_AWFOSR           DFSDM_CHAWSCDR_AWFOSR_Msk              /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
7343 #define DFSDM_CHAWSCDR_BKSCD_Pos        (12U)
7344 #define DFSDM_CHAWSCDR_BKSCD_Msk        (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos)    /*!< 0x0000F000 */
7345 #define DFSDM_CHAWSCDR_BKSCD            DFSDM_CHAWSCDR_BKSCD_Msk               /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
7346 #define DFSDM_CHAWSCDR_SCDT_Pos         (0U)
7347 #define DFSDM_CHAWSCDR_SCDT_Msk         (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos)    /*!< 0x000000FF */
7348 #define DFSDM_CHAWSCDR_SCDT             DFSDM_CHAWSCDR_SCDT_Msk                /*!< SCDT[7:0] Short circuit detector threshold for channel y */
7349 
7350 /****************  Bit definition for DFSDM_CHWDATR register *******************/
7351 #define DFSDM_CHWDATR_WDATA_Pos         (0U)
7352 #define DFSDM_CHWDATR_WDATA_Msk         (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos)  /*!< 0x0000FFFF */
7353 #define DFSDM_CHWDATR_WDATA             DFSDM_CHWDATR_WDATA_Msk                /*!< WDATA[15:0] Input channel y watchdog data */
7354 
7355 /****************  Bit definition for DFSDM_CHDATINR register *****************/
7356 #define DFSDM_CHDATINR_INDAT0_Pos       (0U)
7357 #define DFSDM_CHDATINR_INDAT0_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos)/*!< 0x0000FFFF */
7358 #define DFSDM_CHDATINR_INDAT0           DFSDM_CHDATINR_INDAT0_Msk              /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
7359 #define DFSDM_CHDATINR_INDAT1_Pos       (16U)
7360 #define DFSDM_CHDATINR_INDAT1_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos)/*!< 0xFFFF0000 */
7361 #define DFSDM_CHDATINR_INDAT1           DFSDM_CHDATINR_INDAT1_Msk              /*!< INDAT0[15:0] Input data for channel y */
7362 
7363 /****************  Bit definition for DFSDM_CHDLYR register *******************/
7364 #define DFSDM_CHDLYR_PLSSKP_Pos         (0U)
7365 #define DFSDM_CHDLYR_PLSSKP_Msk         (0x3FUL << DFSDM_CHDLYR_PLSSKP_Pos)    /*!< 0x0000003F */
7366 #define DFSDM_CHDLYR_PLSSKP             DFSDM_CHDLYR_PLSSKP_Msk                /*!< PLSSKP[5:0] Number of input serial samples that will be skipped */
7367 
7368 /************************   DFSDM module registers  ****************************/
7369 
7370 /*****************  Bit definition for DFSDM_FLTCR1 register *******************/
7371 #define DFSDM_FLTCR1_AWFSEL_Pos         (30U)
7372 #define DFSDM_FLTCR1_AWFSEL_Msk         (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos)     /*!< 0x40000000 */
7373 #define DFSDM_FLTCR1_AWFSEL             DFSDM_FLTCR1_AWFSEL_Msk                /*!< Analog watchdog fast mode select */
7374 #define DFSDM_FLTCR1_FAST_Pos           (29U)
7375 #define DFSDM_FLTCR1_FAST_Msk           (0x1UL << DFSDM_FLTCR1_FAST_Pos)       /*!< 0x20000000 */
7376 #define DFSDM_FLTCR1_FAST               DFSDM_FLTCR1_FAST_Msk                  /*!< Fast conversion mode selection */
7377 #define DFSDM_FLTCR1_RCH_Pos            (24U)
7378 #define DFSDM_FLTCR1_RCH_Msk            (0x7UL << DFSDM_FLTCR1_RCH_Pos)        /*!< 0x07000000 */
7379 #define DFSDM_FLTCR1_RCH                DFSDM_FLTCR1_RCH_Msk                   /*!< RCH[2:0] Regular channel selection */
7380 #define DFSDM_FLTCR1_RDMAEN_Pos         (21U)
7381 #define DFSDM_FLTCR1_RDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos)     /*!< 0x00200000 */
7382 #define DFSDM_FLTCR1_RDMAEN             DFSDM_FLTCR1_RDMAEN_Msk                /*!< DMA channel enabled to read data for the regular conversion */
7383 #define DFSDM_FLTCR1_RSYNC_Pos          (19U)
7384 #define DFSDM_FLTCR1_RSYNC_Msk          (0x1UL << DFSDM_FLTCR1_RSYNC_Pos)      /*!< 0x00080000 */
7385 #define DFSDM_FLTCR1_RSYNC              DFSDM_FLTCR1_RSYNC_Msk                 /*!< Launch regular conversion synchronously with DFSDMx */
7386 #define DFSDM_FLTCR1_RCONT_Pos          (18U)
7387 #define DFSDM_FLTCR1_RCONT_Msk          (0x1UL << DFSDM_FLTCR1_RCONT_Pos)      /*!< 0x00040000 */
7388 #define DFSDM_FLTCR1_RCONT              DFSDM_FLTCR1_RCONT_Msk                 /*!< Continuous mode selection for regular conversions */
7389 #define DFSDM_FLTCR1_RSWSTART_Pos       (17U)
7390 #define DFSDM_FLTCR1_RSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos)   /*!< 0x00020000 */
7391 #define DFSDM_FLTCR1_RSWSTART           DFSDM_FLTCR1_RSWSTART_Msk              /*!< Software start of a conversion on the regular channel */
7392 #define DFSDM_FLTCR1_JEXTEN_Pos         (13U)
7393 #define DFSDM_FLTCR1_JEXTEN_Msk         (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos)     /*!< 0x00006000 */
7394 #define DFSDM_FLTCR1_JEXTEN             DFSDM_FLTCR1_JEXTEN_Msk                /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
7395 #define DFSDM_FLTCR1_JEXTEN_1           (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos)     /*!< 0x00004000 */
7396 #define DFSDM_FLTCR1_JEXTEN_0           (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos)     /*!< 0x00002000 */
7397 #define DFSDM_FLTCR1_JEXTSEL_Pos        (8U)
7398 #define DFSDM_FLTCR1_JEXTSEL_Msk        (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos)   /*!< 0x00001F00 */
7399 #define DFSDM_FLTCR1_JEXTSEL            DFSDM_FLTCR1_JEXTSEL_Msk               /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */
7400 #define DFSDM_FLTCR1_JEXTSEL_4          (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos)   /*!< 0x00001000 */
7401 #define DFSDM_FLTCR1_JEXTSEL_3          (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos)   /*!< 0x00000800 */
7402 #define DFSDM_FLTCR1_JEXTSEL_2          (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos)   /*!< 0x00000400 */
7403 #define DFSDM_FLTCR1_JEXTSEL_1          (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos)   /*!< 0x00000200 */
7404 #define DFSDM_FLTCR1_JEXTSEL_0          (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos)   /*!< 0x00000100 */
7405 #define DFSDM_FLTCR1_JDMAEN_Pos         (5U)
7406 #define DFSDM_FLTCR1_JDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos)     /*!< 0x00000020 */
7407 #define DFSDM_FLTCR1_JDMAEN             DFSDM_FLTCR1_JDMAEN_Msk                /*!< DMA channel enabled to read data for the injected channel group */
7408 #define DFSDM_FLTCR1_JSCAN_Pos          (4U)
7409 #define DFSDM_FLTCR1_JSCAN_Msk          (0x1UL << DFSDM_FLTCR1_JSCAN_Pos)      /*!< 0x00000010 */
7410 #define DFSDM_FLTCR1_JSCAN              DFSDM_FLTCR1_JSCAN_Msk                 /*!< Scanning conversion in continuous mode selection for injected conversions */
7411 #define DFSDM_FLTCR1_JSYNC_Pos          (3U)
7412 #define DFSDM_FLTCR1_JSYNC_Msk          (0x1UL << DFSDM_FLTCR1_JSYNC_Pos)      /*!< 0x00000008 */
7413 #define DFSDM_FLTCR1_JSYNC              DFSDM_FLTCR1_JSYNC_Msk                 /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger  */
7414 #define DFSDM_FLTCR1_JSWSTART_Pos       (1U)
7415 #define DFSDM_FLTCR1_JSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos)   /*!< 0x00000002 */
7416 #define DFSDM_FLTCR1_JSWSTART           DFSDM_FLTCR1_JSWSTART_Msk              /*!< Start the conversion of the injected group of channels */
7417 #define DFSDM_FLTCR1_DFEN_Pos           (0U)
7418 #define DFSDM_FLTCR1_DFEN_Msk           (0x1UL << DFSDM_FLTCR1_DFEN_Pos)       /*!< 0x00000001 */
7419 #define DFSDM_FLTCR1_DFEN               DFSDM_FLTCR1_DFEN_Msk                  /*!< DFSDM enable */
7420 
7421 /*****************  Bit definition for DFSDM_FLTCR2 register *******************/
7422 #define DFSDM_FLTCR2_AWDCH_Pos          (16U)
7423 #define DFSDM_FLTCR2_AWDCH_Msk          (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos)     /*!< 0x00FF0000 */
7424 #define DFSDM_FLTCR2_AWDCH              DFSDM_FLTCR2_AWDCH_Msk                 /*!< AWDCH[7:0] Analog watchdog channel selection */
7425 #define DFSDM_FLTCR2_EXCH_Pos           (8U)
7426 #define DFSDM_FLTCR2_EXCH_Msk           (0xFFUL << DFSDM_FLTCR2_EXCH_Pos)      /*!< 0x0000FF00 */
7427 #define DFSDM_FLTCR2_EXCH               DFSDM_FLTCR2_EXCH_Msk                  /*!< EXCH[7:0] Extreme detector channel selection */
7428 #define DFSDM_FLTCR2_CKABIE_Pos         (6U)
7429 #define DFSDM_FLTCR2_CKABIE_Msk         (0x1UL << DFSDM_FLTCR2_CKABIE_Pos)     /*!< 0x00000040 */
7430 #define DFSDM_FLTCR2_CKABIE             DFSDM_FLTCR2_CKABIE_Msk                /*!< Clock absence interrupt enable */
7431 #define DFSDM_FLTCR2_SCDIE_Pos          (5U)
7432 #define DFSDM_FLTCR2_SCDIE_Msk          (0x1UL << DFSDM_FLTCR2_SCDIE_Pos)      /*!< 0x00000020 */
7433 #define DFSDM_FLTCR2_SCDIE              DFSDM_FLTCR2_SCDIE_Msk                 /*!< Short circuit detector interrupt enable */
7434 #define DFSDM_FLTCR2_AWDIE_Pos          (4U)
7435 #define DFSDM_FLTCR2_AWDIE_Msk          (0x1UL << DFSDM_FLTCR2_AWDIE_Pos)      /*!< 0x00000010 */
7436 #define DFSDM_FLTCR2_AWDIE              DFSDM_FLTCR2_AWDIE_Msk                 /*!< Analog watchdog interrupt enable */
7437 #define DFSDM_FLTCR2_ROVRIE_Pos         (3U)
7438 #define DFSDM_FLTCR2_ROVRIE_Msk         (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos)     /*!< 0x00000008 */
7439 #define DFSDM_FLTCR2_ROVRIE             DFSDM_FLTCR2_ROVRIE_Msk                /*!< Regular data overrun interrupt enable */
7440 #define DFSDM_FLTCR2_JOVRIE_Pos         (2U)
7441 #define DFSDM_FLTCR2_JOVRIE_Msk         (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos)     /*!< 0x00000004 */
7442 #define DFSDM_FLTCR2_JOVRIE             DFSDM_FLTCR2_JOVRIE_Msk                /*!< Injected data overrun interrupt enable */
7443 #define DFSDM_FLTCR2_REOCIE_Pos         (1U)
7444 #define DFSDM_FLTCR2_REOCIE_Msk         (0x1UL << DFSDM_FLTCR2_REOCIE_Pos)     /*!< 0x00000002 */
7445 #define DFSDM_FLTCR2_REOCIE             DFSDM_FLTCR2_REOCIE_Msk                /*!< Regular end of conversion interrupt enable */
7446 #define DFSDM_FLTCR2_JEOCIE_Pos         (0U)
7447 #define DFSDM_FLTCR2_JEOCIE_Msk         (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos)     /*!< 0x00000001 */
7448 #define DFSDM_FLTCR2_JEOCIE             DFSDM_FLTCR2_JEOCIE_Msk                /*!< Injected end of conversion interrupt enable */
7449 
7450 /*****************  Bit definition for DFSDM_FLTISR register *******************/
7451 #define DFSDM_FLTISR_SCDF_Pos           (24U)
7452 #define DFSDM_FLTISR_SCDF_Msk           (0xFFUL << DFSDM_FLTISR_SCDF_Pos)      /*!< 0xFF000000 */
7453 #define DFSDM_FLTISR_SCDF               DFSDM_FLTISR_SCDF_Msk                  /*!< SCDF[7:0] Short circuit detector flag */
7454 #define DFSDM_FLTISR_CKABF_Pos          (16U)
7455 #define DFSDM_FLTISR_CKABF_Msk          (0xFFUL << DFSDM_FLTISR_CKABF_Pos)     /*!< 0x00FF0000 */
7456 #define DFSDM_FLTISR_CKABF              DFSDM_FLTISR_CKABF_Msk                 /*!< CKABF[7:0] Clock absence flag */
7457 #define DFSDM_FLTISR_RCIP_Pos           (14U)
7458 #define DFSDM_FLTISR_RCIP_Msk           (0x1UL << DFSDM_FLTISR_RCIP_Pos)       /*!< 0x00004000 */
7459 #define DFSDM_FLTISR_RCIP               DFSDM_FLTISR_RCIP_Msk                  /*!< Regular conversion in progress status */
7460 #define DFSDM_FLTISR_JCIP_Pos           (13U)
7461 #define DFSDM_FLTISR_JCIP_Msk           (0x1UL << DFSDM_FLTISR_JCIP_Pos)       /*!< 0x00002000 */
7462 #define DFSDM_FLTISR_JCIP               DFSDM_FLTISR_JCIP_Msk                  /*!< Injected conversion in progress status */
7463 #define DFSDM_FLTISR_AWDF_Pos           (4U)
7464 #define DFSDM_FLTISR_AWDF_Msk           (0x1UL << DFSDM_FLTISR_AWDF_Pos)       /*!< 0x00000010 */
7465 #define DFSDM_FLTISR_AWDF               DFSDM_FLTISR_AWDF_Msk                  /*!< Analog watchdog */
7466 #define DFSDM_FLTISR_ROVRF_Pos          (3U)
7467 #define DFSDM_FLTISR_ROVRF_Msk          (0x1UL << DFSDM_FLTISR_ROVRF_Pos)      /*!< 0x00000008 */
7468 #define DFSDM_FLTISR_ROVRF              DFSDM_FLTISR_ROVRF_Msk                 /*!< Regular conversion overrun flag */
7469 #define DFSDM_FLTISR_JOVRF_Pos          (2U)
7470 #define DFSDM_FLTISR_JOVRF_Msk          (0x1UL << DFSDM_FLTISR_JOVRF_Pos)      /*!< 0x00000004 */
7471 #define DFSDM_FLTISR_JOVRF              DFSDM_FLTISR_JOVRF_Msk                 /*!< Injected conversion overrun flag */
7472 #define DFSDM_FLTISR_REOCF_Pos          (1U)
7473 #define DFSDM_FLTISR_REOCF_Msk          (0x1UL << DFSDM_FLTISR_REOCF_Pos)      /*!< 0x00000002 */
7474 #define DFSDM_FLTISR_REOCF              DFSDM_FLTISR_REOCF_Msk                 /*!< End of regular conversion flag */
7475 #define DFSDM_FLTISR_JEOCF_Pos          (0U)
7476 #define DFSDM_FLTISR_JEOCF_Msk          (0x1UL << DFSDM_FLTISR_JEOCF_Pos)      /*!< 0x00000001 */
7477 #define DFSDM_FLTISR_JEOCF              DFSDM_FLTISR_JEOCF_Msk                 /*!< End of injected conversion flag */
7478 
7479 /*****************  Bit definition for DFSDM_FLTICR register *******************/
7480 #define DFSDM_FLTICR_CLRSCDF_Pos        (24U)
7481 #define DFSDM_FLTICR_CLRSCDF_Msk        (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos)   /*!< 0xFF000000 */
7482 #define DFSDM_FLTICR_CLRSCDF            DFSDM_FLTICR_CLRSCDF_Msk               /*!< CLRSCDF[7:0] Clear the short circuit detector flag */
7483 #define DFSDM_FLTICR_CLRCKABF_Pos       (16U)
7484 #define DFSDM_FLTICR_CLRCKABF_Msk       (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos)  /*!< 0x00FF0000 */
7485 #define DFSDM_FLTICR_CLRCKABF           DFSDM_FLTICR_CLRCKABF_Msk              /*!< CLRCKABF[7:0] Clear the clock absence flag */
7486 #define DFSDM_FLTICR_CLRROVRF_Pos       (3U)
7487 #define DFSDM_FLTICR_CLRROVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos)   /*!< 0x00000008 */
7488 #define DFSDM_FLTICR_CLRROVRF           DFSDM_FLTICR_CLRROVRF_Msk              /*!< Clear the regular conversion overrun flag */
7489 #define DFSDM_FLTICR_CLRJOVRF_Pos       (2U)
7490 #define DFSDM_FLTICR_CLRJOVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos)   /*!< 0x00000004 */
7491 #define DFSDM_FLTICR_CLRJOVRF           DFSDM_FLTICR_CLRJOVRF_Msk              /*!< Clear the injected conversion overrun flag */
7492 
7493 /****************  Bit definition for DFSDM_FLTJCHGR register ******************/
7494 #define DFSDM_FLTJCHGR_JCHG_Pos         (0U)
7495 #define DFSDM_FLTJCHGR_JCHG_Msk         (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos)    /*!< 0x000000FF */
7496 #define DFSDM_FLTJCHGR_JCHG             DFSDM_FLTJCHGR_JCHG_Msk                /*!< JCHG[7:0] Injected channel group selection */
7497 
7498 /*****************  Bit definition for DFSDM_FLTFCR register *******************/
7499 #define DFSDM_FLTFCR_FORD_Pos           (29U)
7500 #define DFSDM_FLTFCR_FORD_Msk           (0x7UL << DFSDM_FLTFCR_FORD_Pos)       /*!< 0xE0000000 */
7501 #define DFSDM_FLTFCR_FORD               DFSDM_FLTFCR_FORD_Msk                  /*!< FORD[2:0] Sinc filter order */
7502 #define DFSDM_FLTFCR_FORD_2             (0x4UL << DFSDM_FLTFCR_FORD_Pos)       /*!< 0x80000000 */
7503 #define DFSDM_FLTFCR_FORD_1             (0x2UL << DFSDM_FLTFCR_FORD_Pos)       /*!< 0x40000000 */
7504 #define DFSDM_FLTFCR_FORD_0             (0x1UL << DFSDM_FLTFCR_FORD_Pos)       /*!< 0x20000000 */
7505 #define DFSDM_FLTFCR_FOSR_Pos           (16U)
7506 #define DFSDM_FLTFCR_FOSR_Msk           (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos)     /*!< 0x03FF0000 */
7507 #define DFSDM_FLTFCR_FOSR               DFSDM_FLTFCR_FOSR_Msk                  /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
7508 #define DFSDM_FLTFCR_IOSR_Pos           (0U)
7509 #define DFSDM_FLTFCR_IOSR_Msk           (0xFFUL << DFSDM_FLTFCR_IOSR_Pos)      /*!< 0x000000FF */
7510 #define DFSDM_FLTFCR_IOSR               DFSDM_FLTFCR_IOSR_Msk                  /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
7511 
7512 /***************  Bit definition for DFSDM_FLTJDATAR register *****************/
7513 #define DFSDM_FLTJDATAR_JDATA_Pos       (8U)
7514 #define DFSDM_FLTJDATAR_JDATA_Msk       (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos)/*!< 0xFFFFFF00 */
7515 #define DFSDM_FLTJDATAR_JDATA           DFSDM_FLTJDATAR_JDATA_Msk              /*!< JDATA[23:0] Injected group conversion data */
7516 #define DFSDM_FLTJDATAR_JDATACH_Pos     (0U)
7517 #define DFSDM_FLTJDATAR_JDATACH_Msk     (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */
7518 #define DFSDM_FLTJDATAR_JDATACH         DFSDM_FLTJDATAR_JDATACH_Msk            /*!< JDATACH[2:0] Injected channel most recently converted */
7519 
7520 /***************  Bit definition for DFSDM_FLTRDATAR register *****************/
7521 #define DFSDM_FLTRDATAR_RDATA_Pos       (8U)
7522 #define DFSDM_FLTRDATAR_RDATA_Msk       (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos)/*!< 0xFFFFFF00 */
7523 #define DFSDM_FLTRDATAR_RDATA           DFSDM_FLTRDATAR_RDATA_Msk              /*!< RDATA[23:0] Regular channel conversion data */
7524 #define DFSDM_FLTRDATAR_RPEND_Pos       (4U)
7525 #define DFSDM_FLTRDATAR_RPEND_Msk       (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos)   /*!< 0x00000010 */
7526 #define DFSDM_FLTRDATAR_RPEND           DFSDM_FLTRDATAR_RPEND_Msk              /*!< RPEND Regular channel pending data */
7527 #define DFSDM_FLTRDATAR_RDATACH_Pos     (0U)
7528 #define DFSDM_FLTRDATAR_RDATACH_Msk     (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */
7529 #define DFSDM_FLTRDATAR_RDATACH         DFSDM_FLTRDATAR_RDATACH_Msk            /*!< RDATACH[2:0] Regular channel most recently converted */
7530 
7531 /***************  Bit definition for DFSDM_FLTAWHTR register ******************/
7532 #define DFSDM_FLTAWHTR_AWHT_Pos         (8U)
7533 #define DFSDM_FLTAWHTR_AWHT_Msk         (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos)/*!< 0xFFFFFF00 */
7534 #define DFSDM_FLTAWHTR_AWHT             DFSDM_FLTAWHTR_AWHT_Msk                /*!< AWHT[23:0] Analog watchdog high threshold */
7535 #define DFSDM_FLTAWHTR_BKAWH_Pos        (0U)
7536 #define DFSDM_FLTAWHTR_BKAWH_Msk        (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos)    /*!< 0x0000000F */
7537 #define DFSDM_FLTAWHTR_BKAWH            DFSDM_FLTAWHTR_BKAWH_Msk               /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
7538 
7539 /***************  Bit definition for DFSDM_FLTAWLTR register ******************/
7540 #define DFSDM_FLTAWLTR_AWLT_Pos         (8U)
7541 #define DFSDM_FLTAWLTR_AWLT_Msk         (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos)/*!< 0xFFFFFF00 */
7542 #define DFSDM_FLTAWLTR_AWLT             DFSDM_FLTAWLTR_AWLT_Msk                /*!< AWLT[23:0] Analog watchdog low threshold */
7543 #define DFSDM_FLTAWLTR_BKAWL_Pos        (0U)
7544 #define DFSDM_FLTAWLTR_BKAWL_Msk        (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos)    /*!< 0x0000000F */
7545 #define DFSDM_FLTAWLTR_BKAWL            DFSDM_FLTAWLTR_BKAWL_Msk               /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
7546 
7547 /***************  Bit definition for DFSDM_FLTAWSR register *******************/
7548 #define DFSDM_FLTAWSR_AWHTF_Pos         (8U)
7549 #define DFSDM_FLTAWSR_AWHTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos)    /*!< 0x0000FF00 */
7550 #define DFSDM_FLTAWSR_AWHTF             DFSDM_FLTAWSR_AWHTF_Msk                /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
7551 #define DFSDM_FLTAWSR_AWLTF_Pos         (0U)
7552 #define DFSDM_FLTAWSR_AWLTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos)    /*!< 0x000000FF */
7553 #define DFSDM_FLTAWSR_AWLTF             DFSDM_FLTAWSR_AWLTF_Msk                /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
7554 
7555 /***************  Bit definition for DFSDM_FLTAWCFR register ******************/
7556 #define DFSDM_FLTAWCFR_CLRAWHTF_Pos     (8U)
7557 #define DFSDM_FLTAWCFR_CLRAWHTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos)/*!< 0x0000FF00 */
7558 #define DFSDM_FLTAWCFR_CLRAWHTF         DFSDM_FLTAWCFR_CLRAWHTF_Msk            /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
7559 #define DFSDM_FLTAWCFR_CLRAWLTF_Pos     (0U)
7560 #define DFSDM_FLTAWCFR_CLRAWLTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos)/*!< 0x000000FF */
7561 #define DFSDM_FLTAWCFR_CLRAWLTF         DFSDM_FLTAWCFR_CLRAWLTF_Msk            /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
7562 
7563 /***************  Bit definition for DFSDM_FLTEXMAX register ******************/
7564 #define DFSDM_FLTEXMAX_EXMAX_Pos        (8U)
7565 #define DFSDM_FLTEXMAX_EXMAX_Msk        (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos)/*!< 0xFFFFFF00 */
7566 #define DFSDM_FLTEXMAX_EXMAX            DFSDM_FLTEXMAX_EXMAX_Msk               /*!< EXMAX[23:0] Extreme detector maximum value */
7567 #define DFSDM_FLTEXMAX_EXMAXCH_Pos      (0U)
7568 #define DFSDM_FLTEXMAX_EXMAXCH_Msk      (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos)  /*!< 0x00000007 */
7569 #define DFSDM_FLTEXMAX_EXMAXCH          DFSDM_FLTEXMAX_EXMAXCH_Msk             /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
7570 
7571 /***************  Bit definition for DFSDM_FLTEXMIN register ******************/
7572 #define DFSDM_FLTEXMIN_EXMIN_Pos        (8U)
7573 #define DFSDM_FLTEXMIN_EXMIN_Msk        (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos)/*!< 0xFFFFFF00 */
7574 #define DFSDM_FLTEXMIN_EXMIN            DFSDM_FLTEXMIN_EXMIN_Msk               /*!< EXMIN[23:0] Extreme detector minimum value */
7575 #define DFSDM_FLTEXMIN_EXMINCH_Pos      (0U)
7576 #define DFSDM_FLTEXMIN_EXMINCH_Msk      (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos)  /*!< 0x00000007 */
7577 #define DFSDM_FLTEXMIN_EXMINCH          DFSDM_FLTEXMIN_EXMINCH_Msk             /*!< EXMINCH[2:0] Extreme detector minimum data channel */
7578 
7579 /***************  Bit definition for DFSDM_FLTCNVTIMR register ****************/
7580 #define DFSDM_FLTCNVTIMR_CNVCNT_Pos     (4U)
7581 #define DFSDM_FLTCNVTIMR_CNVCNT_Msk     (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos)/*!< 0xFFFFFFF0 */
7582 #define DFSDM_FLTCNVTIMR_CNVCNT         DFSDM_FLTCNVTIMR_CNVCNT_Msk            /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
7583 
7584 /**********************  Bit definition for DFSDM_HWCFGR register  ***************/
7585 #define DFSDM_HWCFGR_NBT_Pos  (0U)
7586 #define DFSDM_HWCFGR_NBT_Msk  (0xFFU << DFSDM_HWCFGR_NBT_Pos)          /*!< 0x000000FF */
7587 #define DFSDM_HWCFGR_NBT      DFSDM_HWCFGR_NBT_Msk                     /*!< Number of implemented transceivers */
7588 #define DFSDM_HWCFGR_NBF_Pos  (8U)
7589 #define DFSDM_HWCFGR_NBF_Msk  (0xFFU << DFSDM_HWCFGR_NBF_Pos)          /*!< 0x0000FF00 */
7590 #define DFSDM_HWCFGR_NBF      DFSDM_HWCFGR_NBF_Msk                     /*!< NNumber of implemented filters */
7591 
7592 /**********************  Bit definition for DFSDM_VERR register  *****************/
7593 #define DFSDM_VERR_MINREV_Pos      (0U)
7594 #define DFSDM_VERR_MINREV_Msk      (0xFU << DFSDM_VERR_MINREV_Pos)               /*!< 0x0000000F */
7595 #define DFSDM_VERR_MINREV          DFSDM_VERR_MINREV_Msk                         /*!< Minor Revision number */
7596 #define DFSDM_VERR_MAJREV_Pos      (4U)
7597 #define DFSDM_VERR_MAJREV_Msk      (0xFU << DFSDM_VERR_MAJREV_Pos)               /*!< 0x000000F0 */
7598 #define DFSDM_VERR_MAJREV          DFSDM_VERR_MAJREV_Msk                         /*!< Major Revision number */
7599 
7600 /**********************  Bit definition for DFSDM_IPIDR register  ****************/
7601 #define DFSDM_IPIDR_IPID_Pos       (0U)
7602 #define DFSDM_IPIDR_IPID_Msk       (0xFFFFFFFFU << DFSDM_IPIDR_IPID_Pos)         /*!< 0xFFFFFFFF */
7603 #define DFSDM_IPIDR_IPID           DFSDM_IPIDR_IPID_Msk                          /*!< IP Identification */
7604 
7605 /**********************  Bit definition for DFSDM_SIDR register  *****************/
7606 #define DFSDM_SIDR_SID_Pos         (0U)
7607 #define DFSDM_SIDR_SID_Msk         (0xFFFFFFFFU << DFSDM_SIDR_SID_Pos)           /*!< 0xFFFFFFFF */
7608 #define DFSDM_SIDR_SID             DFSDM_SIDR_SID_Msk                            /*!< IP size identification */
7609 
7610 /******************************************************************************/
7611 /*                                                                            */
7612 /*                Ethernet MAC Registers bits definitions                     */
7613 /*                                                                            */
7614 /******************************************************************************/
7615 /***************  Bit definition for ETH_MACCR register  ***************/
7616 #define ETH_MACCR_RE_Pos                    (0U)
7617 #define ETH_MACCR_RE_Msk                    (0x1U << ETH_MACCR_RE_Pos)                          /*!< 0x00000001 */
7618 #define ETH_MACCR_RE                        ETH_MACCR_RE_Msk                                    /*!< Receiver Enable */
7619 #define ETH_MACCR_TE_Pos                    (1U)
7620 #define ETH_MACCR_TE_Msk                    (0x1U << ETH_MACCR_TE_Pos)                          /*!< 0x00000002 */
7621 #define ETH_MACCR_TE                        ETH_MACCR_TE_Msk                                    /*!< Transmitter Enable */
7622 #define ETH_MACCR_PRELEN_Pos                (2U)
7623 #define ETH_MACCR_PRELEN_Msk                (0x3U << ETH_MACCR_PRELEN_Pos)                      /*!< 0x0000000C */
7624 #define ETH_MACCR_PRELEN                    ETH_MACCR_PRELEN_Msk                                /*!< Preamble Length for Transmit packets */
7625 #define ETH_MACCR_PRELEN_0                  (0x1U << ETH_MACCR_PRELEN_Pos)                      /*!< 0x00000004 */
7626 #define ETH_MACCR_PRELEN_1                  (0x2U << ETH_MACCR_PRELEN_Pos)                      /*!< 0x00000008 */
7627 #define ETH_MACCR_DC_Pos                    (4U)
7628 #define ETH_MACCR_DC_Msk                    (0x1U << ETH_MACCR_DC_Pos)                          /*!< 0x00000010 */
7629 #define ETH_MACCR_DC                        ETH_MACCR_DC_Msk                                    /*!< Deferral Check */
7630 #define ETH_MACCR_BL_Pos                    (5U)
7631 #define ETH_MACCR_BL_Msk                    (0x3U << ETH_MACCR_BL_Pos)                          /*!< 0x00000060 */
7632 #define ETH_MACCR_BL                        ETH_MACCR_BL_Msk                                    /*!< Back-Off Limit */
7633 #define ETH_MACCR_BL_0                      (0x1U << ETH_MACCR_BL_Pos)                         /*!< 0x00000020 */
7634 #define ETH_MACCR_BL_1                      (0x2U << ETH_MACCR_BL_Pos)                         /*!< 0x00000040 */
7635 #define ETH_MACCR_DR_Pos                    (8U)
7636 #define ETH_MACCR_DR_Msk                    (0x1U << ETH_MACCR_DR_Pos)                          /*!< 0x00000100 */
7637 #define ETH_MACCR_DR                        ETH_MACCR_DR_Msk                                    /*!< Disable Retry */
7638 #define ETH_MACCR_DCRS_Pos                  (9U)
7639 #define ETH_MACCR_DCRS_Msk                  (0x1U << ETH_MACCR_DCRS_Pos)                        /*!< 0x00000200 */
7640 #define ETH_MACCR_DCRS                      ETH_MACCR_DCRS_Msk                                  /*!< Disable Carrier Sense During Transmission */
7641 #define ETH_MACCR_DO_Pos                    (10U)
7642 #define ETH_MACCR_DO_Msk                    (0x1U << ETH_MACCR_DO_Pos)                          /*!< 0x00000400 */
7643 #define ETH_MACCR_DO                        ETH_MACCR_DO_Msk                                    /*!< Disable Receive Own */
7644 #define ETH_MACCR_ECRSFD_Pos                (11U)
7645 #define ETH_MACCR_ECRSFD_Msk                (0x1U << ETH_MACCR_ECRSFD_Pos)                      /*!< 0x00000800 */
7646 #define ETH_MACCR_ECRSFD                    ETH_MACCR_ECRSFD_Msk                                /*!< Enable Carrier Sense Before Transmission in Full-Duplex Mode */
7647 #define ETH_MACCR_LM_Pos                    (12U)
7648 #define ETH_MACCR_LM_Msk                    (0x1U << ETH_MACCR_LM_Pos)                          /*!< 0x00001000 */
7649 #define ETH_MACCR_LM                        ETH_MACCR_LM_Msk                                    /*!< Loopback Mode */
7650 #define ETH_MACCR_DM_Pos                    (13U)
7651 #define ETH_MACCR_DM_Msk                    (0x1U << ETH_MACCR_DM_Pos)                          /*!< 0x00002000 */
7652 #define ETH_MACCR_DM                        ETH_MACCR_DM_Msk                                    /*!< Duplex Mode */
7653 #define ETH_MACCR_FES_Pos                   (14U)
7654 #define ETH_MACCR_FES_Msk                   (0x1U << ETH_MACCR_FES_Pos)                         /*!< 0x00004000 */
7655 #define ETH_MACCR_FES                       ETH_MACCR_FES_Msk                                   /*!< MAC Speed */
7656 #define ETH_MACCR_PS_Pos                    (15U)
7657 #define ETH_MACCR_PS_Msk                    (0x1U << ETH_MACCR_PS_Pos)                          /*!< 0x00008000 */
7658 #define ETH_MACCR_PS                        ETH_MACCR_PS_Msk                                    /*!< Port Select */
7659 #define ETH_MACCR_JE_Pos                    (16U)
7660 #define ETH_MACCR_JE_Msk                    (0x1U << ETH_MACCR_JE_Pos)                          /*!< 0x00010000 */
7661 #define ETH_MACCR_JE                        ETH_MACCR_JE_Msk                                    /*!< Jumbo Packet Enable */
7662 #define ETH_MACCR_JD_Pos                    (17U)
7663 #define ETH_MACCR_JD_Msk                    (0x1U << ETH_MACCR_JD_Pos)                          /*!< 0x00020000 */
7664 #define ETH_MACCR_JD                        ETH_MACCR_JD_Msk                                    /*!< Jabber Disable */
7665 #define ETH_MACCR_BE_Pos                    (18U)
7666 #define ETH_MACCR_BE_Msk                    (0x1U << ETH_MACCR_BE_Pos)                          /*!< 0x00040000 */
7667 #define ETH_MACCR_BE                        ETH_MACCR_BE_Msk                                    /*!< Packet Burst Enable */
7668 #define ETH_MACCR_WD_Pos                    (19U)
7669 #define ETH_MACCR_WD_Msk                    (0x1U << ETH_MACCR_WD_Pos)                          /*!< 0x00080000 */
7670 #define ETH_MACCR_WD                        ETH_MACCR_WD_Msk                                    /*!< Watchdog Disable */
7671 #define ETH_MACCR_ACS_Pos                   (20U)
7672 #define ETH_MACCR_ACS_Msk                   (0x1U << ETH_MACCR_ACS_Pos)                         /*!< 0x00100000 */
7673 #define ETH_MACCR_ACS                       ETH_MACCR_ACS_Msk                                   /*!< Automatic Pad or CRC Stripping */
7674 #define ETH_MACCR_CST_Pos                   (21U)
7675 #define ETH_MACCR_CST_Msk                   (0x1U << ETH_MACCR_CST_Pos)                         /*!< 0x00200000 */
7676 #define ETH_MACCR_CST                       ETH_MACCR_CST_Msk                                   /*!< CRC stripping for Type packets */
7677 #define ETH_MACCR_S2KP_Pos                  (22U)
7678 #define ETH_MACCR_S2KP_Msk                  (0x1U << ETH_MACCR_S2KP_Pos)                        /*!< 0x00400000 */
7679 #define ETH_MACCR_S2KP                      ETH_MACCR_S2KP_Msk                                  /*!< IEEE 802.3as Support for 2K Packets */
7680 #define ETH_MACCR_GPSLCE_Pos                (23U)
7681 #define ETH_MACCR_GPSLCE_Msk                (0x1U << ETH_MACCR_GPSLCE_Pos)                      /*!< 0x00800000 */
7682 #define ETH_MACCR_GPSLCE                    ETH_MACCR_GPSLCE_Msk                                /*!< Giant Packet Size Limit Control Enable */
7683 #define ETH_MACCR_IPG_Pos                   (24U)
7684 #define ETH_MACCR_IPG_Msk                   (0x7U << ETH_MACCR_IPG_Pos)                         /*!< 0x07000000 */
7685 #define ETH_MACCR_IPG                       ETH_MACCR_IPG_Msk                                   /*!< Inter-Packet Gap */
7686 #define ETH_MACCR_IPG_0                     (0x1U << ETH_MACCR_IPG_Pos)                   /*!< 0x01000000 */
7687 #define ETH_MACCR_IPG_1                     (0x2U << ETH_MACCR_IPG_Pos)                   /*!< 0x02000000 */
7688 #define ETH_MACCR_IPG_2                     (0x4U << ETH_MACCR_IPG_Pos)                   /*!< 0x04000000 */
7689 #define ETH_MACCR_IPC_Pos                   (27U)
7690 #define ETH_MACCR_IPC_Msk                   (0x1U << ETH_MACCR_IPC_Pos)                         /*!< 0x08000000 */
7691 #define ETH_MACCR_IPC                       ETH_MACCR_IPC_Msk                                   /*!< Checksum Offload */
7692 #define ETH_MACCR_SARC_Pos                  (28U)
7693 #define ETH_MACCR_SARC_Msk                  (0x7U << ETH_MACCR_SARC_Pos)                        /*!< 0x70000000 */
7694 #define ETH_MACCR_SARC                      ETH_MACCR_SARC_Msk                                  /*!< Source Address Insertion or Replacement Control */
7695 #define ETH_MACCR_SARC_0                    (0x1U << ETH_MACCR_SARC_Pos)                 /*!< 0x10000000 */
7696 #define ETH_MACCR_SARC_1                    (0x2U << ETH_MACCR_SARC_Pos)                 /*!< 0x20000000 */
7697 #define ETH_MACCR_SARC_2                    (0x4U << ETH_MACCR_SARC_Pos)                 /*!< 0x40000000 */
7698 #define ETH_MACCR_ARPEN_Pos                 (31U)
7699 #define ETH_MACCR_ARPEN_Msk                 (0x1U << ETH_MACCR_ARPEN_Pos)                       /*!< 0x80000000 */
7700 #define ETH_MACCR_ARPEN                     ETH_MACCR_ARPEN_Msk                                 /*!< ARP Offload Enable */
7701 
7702 /**************  Bit definition for ETH_MACECR register  ***************/
7703 #define ETH_MACECR_GPSL_Pos                 (0U)
7704 #define ETH_MACECR_GPSL_Msk                 (0x3FFFU << ETH_MACECR_GPSL_Pos)                    /*!< 0x00003FFF */
7705 #define ETH_MACECR_GPSL                     ETH_MACECR_GPSL_Msk                                 /*!< Giant Packet Size Limit */
7706 #define ETH_MACECR_GPSL_0                   (0x1U << ETH_MACECR_GPSL_Pos)                       /*!< 0x00000001 */
7707 #define ETH_MACECR_GPSL_1                   (0x2U << ETH_MACECR_GPSL_Pos)                       /*!< 0x00000002 */
7708 #define ETH_MACECR_GPSL_2                   (0x4U << ETH_MACECR_GPSL_Pos)                       /*!< 0x00000004 */
7709 #define ETH_MACECR_GPSL_3                   (0x8U << ETH_MACECR_GPSL_Pos)                       /*!< 0x00000008 */
7710 #define ETH_MACECR_GPSL_4                   (0x10U << ETH_MACECR_GPSL_Pos)                      /*!< 0x00000010 */
7711 #define ETH_MACECR_GPSL_5                   (0x20U << ETH_MACECR_GPSL_Pos)                      /*!< 0x00000020 */
7712 #define ETH_MACECR_GPSL_6                   (0x40U << ETH_MACECR_GPSL_Pos)                      /*!< 0x00000040 */
7713 #define ETH_MACECR_GPSL_7                   (0x80U << ETH_MACECR_GPSL_Pos)                      /*!< 0x00000080 */
7714 #define ETH_MACECR_GPSL_8                   (0x100U << ETH_MACECR_GPSL_Pos)                     /*!< 0x00000100 */
7715 #define ETH_MACECR_GPSL_9                   (0x200U << ETH_MACECR_GPSL_Pos)                     /*!< 0x00000200 */
7716 #define ETH_MACECR_GPSL_10                  (0x400U << ETH_MACECR_GPSL_Pos)                     /*!< 0x00000400 */
7717 #define ETH_MACECR_GPSL_11                  (0x800U << ETH_MACECR_GPSL_Pos)                     /*!< 0x00000800 */
7718 #define ETH_MACECR_GPSL_12                  (0x1000U << ETH_MACECR_GPSL_Pos)                    /*!< 0x00001000 */
7719 #define ETH_MACECR_GPSL_13                  (0x2000U << ETH_MACECR_GPSL_Pos)                    /*!< 0x00002000 */
7720 #define ETH_MACECR_DCRCC_Pos                (16U)
7721 #define ETH_MACECR_DCRCC_Msk                (0x1U << ETH_MACECR_DCRCC_Pos)                      /*!< 0x00010000 */
7722 #define ETH_MACECR_DCRCC                    ETH_MACECR_DCRCC_Msk                                /*!< Disable CRC Checking for Received Packets */
7723 #define ETH_MACECR_SPEN_Pos                 (17U)
7724 #define ETH_MACECR_SPEN_Msk                 (0x1U << ETH_MACECR_SPEN_Pos)                       /*!< 0x00020000 */
7725 #define ETH_MACECR_SPEN                     ETH_MACECR_SPEN_Msk                                 /*!< Slow Protocol Detection Enable */
7726 #define ETH_MACECR_USP_Pos                  (18U)
7727 #define ETH_MACECR_USP_Msk                  (0x1U << ETH_MACECR_USP_Pos)                        /*!< 0x00040000 */
7728 #define ETH_MACECR_USP                      ETH_MACECR_USP_Msk                                  /*!< Unicast Slow Protocol Packet Detect */
7729 #define ETH_MACECR_EIPGEN_Pos               (24U)
7730 #define ETH_MACECR_EIPGEN_Msk               (0x1U << ETH_MACECR_EIPGEN_Pos)                     /*!< 0x01000000 */
7731 #define ETH_MACECR_EIPGEN                   ETH_MACECR_EIPGEN_Msk                               /*!< Extended Inter-Packet Gap Enable */
7732 #define ETH_MACECR_EIPG_Pos                 (25U)
7733 #define ETH_MACECR_EIPG_Msk                 (0x1FU << ETH_MACECR_EIPG_Pos)                      /*!< 0x3E000000 */
7734 #define ETH_MACECR_EIPG                     ETH_MACECR_EIPG_Msk                                 /*!< Extended Inter-Packet Gap */
7735 #define ETH_MACECR_EIPG_0                   (0x1U << ETH_MACECR_EIPG_Pos)                 /*!< 0x02000000 */
7736 #define ETH_MACECR_EIPG_1                   (0x2U << ETH_MACECR_EIPG_Pos)                 /*!< 0x04000000 */
7737 #define ETH_MACECR_EIPG_2                   (0x4U << ETH_MACECR_EIPG_Pos)                 /*!< 0x08000000 */
7738 #define ETH_MACECR_EIPG_3                   (0x8U << ETH_MACECR_EIPG_Pos)                /*!< 0x10000000 */
7739 #define ETH_MACECR_EIPG_4                   (0x10U << ETH_MACECR_EIPG_Pos)                /*!< 0x20000000 */
7740 
7741 /**************  Bit definition for ETH_MACPFR register  ***************/
7742 #define ETH_MACPFR_PR_Pos                   (0U)
7743 #define ETH_MACPFR_PR_Msk                   (0x1U << ETH_MACPFR_PR_Pos)                         /*!< 0x00000001 */
7744 #define ETH_MACPFR_PR                       ETH_MACPFR_PR_Msk                                   /*!< Promiscuous Mode */
7745 #define ETH_MACPFR_HUC_Pos                  (1U)
7746 #define ETH_MACPFR_HUC_Msk                  (0x1U << ETH_MACPFR_HUC_Pos)                        /*!< 0x00000002 */
7747 #define ETH_MACPFR_HUC                      ETH_MACPFR_HUC_Msk                                  /*!< Hash Unicast */
7748 #define ETH_MACPFR_HMC_Pos                  (2U)
7749 #define ETH_MACPFR_HMC_Msk                  (0x1U << ETH_MACPFR_HMC_Pos)                        /*!< 0x00000004 */
7750 #define ETH_MACPFR_HMC                      ETH_MACPFR_HMC_Msk                                  /*!< Hash Multicast */
7751 #define ETH_MACPFR_DAIF_Pos                 (3U)
7752 #define ETH_MACPFR_DAIF_Msk                 (0x1U << ETH_MACPFR_DAIF_Pos)                       /*!< 0x00000008 */
7753 #define ETH_MACPFR_DAIF                     ETH_MACPFR_DAIF_Msk                                 /*!< DA Inverse Filtering */
7754 #define ETH_MACPFR_PM_Pos                   (4U)
7755 #define ETH_MACPFR_PM_Msk                   (0x1U << ETH_MACPFR_PM_Pos)                         /*!< 0x00000010 */
7756 #define ETH_MACPFR_PM                       ETH_MACPFR_PM_Msk                                   /*!< Pass All Multicast */
7757 #define ETH_MACPFR_DBF_Pos                  (5U)
7758 #define ETH_MACPFR_DBF_Msk                  (0x1U << ETH_MACPFR_DBF_Pos)                        /*!< 0x00000020 */
7759 #define ETH_MACPFR_DBF                      ETH_MACPFR_DBF_Msk                                  /*!< Disable Broadcast Packets */
7760 #define ETH_MACPFR_PCF_Pos                  (6U)
7761 #define ETH_MACPFR_PCF_Msk                  (0x3U << ETH_MACPFR_PCF_Pos)                        /*!< 0x000000C0 */
7762 #define ETH_MACPFR_PCF                      ETH_MACPFR_PCF_Msk                                  /*!< Pass Control Packets */
7763 #define ETH_MACPFR_PCF_0                    (0x1U << ETH_MACPFR_PCF_Pos)                       /*!< 0x00000040 */
7764 #define ETH_MACPFR_PCF_1                    (0x2U << ETH_MACPFR_PCF_Pos)                       /*!< 0x00000080 */
7765 #define ETH_MACPFR_SAIF_Pos                 (8U)
7766 #define ETH_MACPFR_SAIF_Msk                 (0x1U << ETH_MACPFR_SAIF_Pos)                       /*!< 0x00000100 */
7767 #define ETH_MACPFR_SAIF                     ETH_MACPFR_SAIF_Msk                                 /*!< SA Inverse Filtering */
7768 #define ETH_MACPFR_SAF_Pos                  (9U)
7769 #define ETH_MACPFR_SAF_Msk                  (0x1U << ETH_MACPFR_SAF_Pos)                        /*!< 0x00000200 */
7770 #define ETH_MACPFR_SAF                      ETH_MACPFR_SAF_Msk                                  /*!< Source Address Filter Enable */
7771 #define ETH_MACPFR_HPF_Pos                  (10U)
7772 #define ETH_MACPFR_HPF_Msk                  (0x1U << ETH_MACPFR_HPF_Pos)                        /*!< 0x00000400 */
7773 #define ETH_MACPFR_HPF                      ETH_MACPFR_HPF_Msk                                  /*!< Hash or Perfect Filter */
7774 #define ETH_MACPFR_VTFE_Pos                 (16U)
7775 #define ETH_MACPFR_VTFE_Msk                 (0x1U << ETH_MACPFR_VTFE_Pos)                       /*!< 0x00010000 */
7776 #define ETH_MACPFR_VTFE                     ETH_MACPFR_VTFE_Msk                                 /*!< VLAN Tag Filter Enable */
7777 #define ETH_MACPFR_IPFE_Pos                 (20U)
7778 #define ETH_MACPFR_IPFE_Msk                 (0x1U << ETH_MACPFR_IPFE_Pos)                       /*!< 0x00100000 */
7779 #define ETH_MACPFR_IPFE                     ETH_MACPFR_IPFE_Msk                                 /*!< Layer 3 and Layer 4 Filter Enable */
7780 #define ETH_MACPFR_DNTU_Pos                 (21U)
7781 #define ETH_MACPFR_DNTU_Msk                 (0x1U << ETH_MACPFR_DNTU_Pos)                       /*!< 0x00200000 */
7782 #define ETH_MACPFR_DNTU                     ETH_MACPFR_DNTU_Msk                                 /*!< Drop Non-TCP/UDP over IP Packets */
7783 #define ETH_MACPFR_RA_Pos                   (31U)
7784 #define ETH_MACPFR_RA_Msk                   (0x1U << ETH_MACPFR_RA_Pos)                         /*!< 0x80000000 */
7785 #define ETH_MACPFR_RA                       ETH_MACPFR_RA_Msk                                   /*!< Receive All */
7786 
7787 /**************  Bit definition for ETH_MACWTR register  ***************/
7788 #define ETH_MACWTR_WTO_Pos                  (0U)
7789 #define ETH_MACWTR_WTO_Msk                  (0xFU << ETH_MACWTR_WTO_Pos)                        /*!< 0x0000000F */
7790 #define ETH_MACWTR_WTO                      ETH_MACWTR_WTO_Msk                                  /*!< Watchdog Timeout */
7791 #define ETH_MACWTR_WTO_0                    (0x1U << ETH_MACWTR_WTO_Pos)                        /*!< 0x00000001 */
7792 #define ETH_MACWTR_WTO_1                    (0x2U << ETH_MACWTR_WTO_Pos)                        /*!< 0x00000002 */
7793 #define ETH_MACWTR_WTO_2                    (0x4U << ETH_MACWTR_WTO_Pos)                        /*!< 0x00000004 */
7794 #define ETH_MACWTR_WTO_3                    (0x8U << ETH_MACWTR_WTO_Pos)                        /*!< 0x00000008 */
7795 #define ETH_MACWTR_PWE_Pos                  (8U)
7796 #define ETH_MACWTR_PWE_Msk                  (0x1U << ETH_MACWTR_PWE_Pos)                        /*!< 0x00000100 */
7797 #define ETH_MACWTR_PWE                      ETH_MACWTR_PWE_Msk                                  /*!< Programmable Watchdog Enable */
7798 
7799 /**************  Bit definition for ETH_MACHT0R register  **************/
7800 #define ETH_MACHT0R_HT31T0_Pos              (0U)
7801 #define ETH_MACHT0R_HT31T0_Msk              (0xFFFFFFFFU << ETH_MACHT0R_HT31T0_Pos)             /*!< 0xFFFFFFFF */
7802 #define ETH_MACHT0R_HT31T0                  ETH_MACHT0R_HT31T0_Msk                              /*!< MAC Hash Table First 32 Bits */
7803 #define ETH_MACHT0R_HT31T0_0                (0x1U << ETH_MACHT0R_HT31T0_Pos)                    /*!< 0x00000001 */
7804 #define ETH_MACHT0R_HT31T0_1                (0x2U << ETH_MACHT0R_HT31T0_Pos)                    /*!< 0x00000002 */
7805 #define ETH_MACHT0R_HT31T0_2                (0x4U << ETH_MACHT0R_HT31T0_Pos)                    /*!< 0x00000004 */
7806 #define ETH_MACHT0R_HT31T0_3                (0x8U << ETH_MACHT0R_HT31T0_Pos)                    /*!< 0x00000008 */
7807 #define ETH_MACHT0R_HT31T0_4                (0x10U << ETH_MACHT0R_HT31T0_Pos)                   /*!< 0x00000010 */
7808 #define ETH_MACHT0R_HT31T0_5                (0x20U << ETH_MACHT0R_HT31T0_Pos)                   /*!< 0x00000020 */
7809 #define ETH_MACHT0R_HT31T0_6                (0x40U << ETH_MACHT0R_HT31T0_Pos)                   /*!< 0x00000040 */
7810 #define ETH_MACHT0R_HT31T0_7                (0x80U << ETH_MACHT0R_HT31T0_Pos)                   /*!< 0x00000080 */
7811 #define ETH_MACHT0R_HT31T0_8                (0x100U << ETH_MACHT0R_HT31T0_Pos)                  /*!< 0x00000100 */
7812 #define ETH_MACHT0R_HT31T0_9                (0x200U << ETH_MACHT0R_HT31T0_Pos)                  /*!< 0x00000200 */
7813 #define ETH_MACHT0R_HT31T0_10               (0x400U << ETH_MACHT0R_HT31T0_Pos)                  /*!< 0x00000400 */
7814 #define ETH_MACHT0R_HT31T0_11               (0x800U << ETH_MACHT0R_HT31T0_Pos)                  /*!< 0x00000800 */
7815 #define ETH_MACHT0R_HT31T0_12               (0x1000U << ETH_MACHT0R_HT31T0_Pos)                 /*!< 0x00001000 */
7816 #define ETH_MACHT0R_HT31T0_13               (0x2000U << ETH_MACHT0R_HT31T0_Pos)                 /*!< 0x00002000 */
7817 #define ETH_MACHT0R_HT31T0_14               (0x4000U << ETH_MACHT0R_HT31T0_Pos)                 /*!< 0x00004000 */
7818 #define ETH_MACHT0R_HT31T0_15               (0x8000U << ETH_MACHT0R_HT31T0_Pos)                 /*!< 0x00008000 */
7819 #define ETH_MACHT0R_HT31T0_16               (0x10000U << ETH_MACHT0R_HT31T0_Pos)                /*!< 0x00010000 */
7820 #define ETH_MACHT0R_HT31T0_17               (0x20000U << ETH_MACHT0R_HT31T0_Pos)                /*!< 0x00020000 */
7821 #define ETH_MACHT0R_HT31T0_18               (0x40000U << ETH_MACHT0R_HT31T0_Pos)                /*!< 0x00040000 */
7822 #define ETH_MACHT0R_HT31T0_19               (0x80000U << ETH_MACHT0R_HT31T0_Pos)                /*!< 0x00080000 */
7823 #define ETH_MACHT0R_HT31T0_20               (0x100000U << ETH_MACHT0R_HT31T0_Pos)               /*!< 0x00100000 */
7824 #define ETH_MACHT0R_HT31T0_21               (0x200000U << ETH_MACHT0R_HT31T0_Pos)               /*!< 0x00200000 */
7825 #define ETH_MACHT0R_HT31T0_22               (0x400000U << ETH_MACHT0R_HT31T0_Pos)               /*!< 0x00400000 */
7826 #define ETH_MACHT0R_HT31T0_23               (0x800000U << ETH_MACHT0R_HT31T0_Pos)               /*!< 0x00800000 */
7827 #define ETH_MACHT0R_HT31T0_24               (0x1000000U << ETH_MACHT0R_HT31T0_Pos)              /*!< 0x01000000 */
7828 #define ETH_MACHT0R_HT31T0_25               (0x2000000U << ETH_MACHT0R_HT31T0_Pos)              /*!< 0x02000000 */
7829 #define ETH_MACHT0R_HT31T0_26               (0x4000000U << ETH_MACHT0R_HT31T0_Pos)              /*!< 0x04000000 */
7830 #define ETH_MACHT0R_HT31T0_27               (0x8000000U << ETH_MACHT0R_HT31T0_Pos)              /*!< 0x08000000 */
7831 #define ETH_MACHT0R_HT31T0_28               (0x10000000U << ETH_MACHT0R_HT31T0_Pos)             /*!< 0x10000000 */
7832 #define ETH_MACHT0R_HT31T0_29               (0x20000000U << ETH_MACHT0R_HT31T0_Pos)             /*!< 0x20000000 */
7833 #define ETH_MACHT0R_HT31T0_30               (0x40000000U << ETH_MACHT0R_HT31T0_Pos)             /*!< 0x40000000 */
7834 #define ETH_MACHT0R_HT31T0_31               (0x80000000U << ETH_MACHT0R_HT31T0_Pos)             /*!< 0x80000000 */
7835 
7836 /**************  Bit definition for ETH_MACHT1R register  **************/
7837 #define ETH_MACHT1R_HT63T32_Pos             (0U)
7838 #define ETH_MACHT1R_HT63T32_Msk             (0xFFFFFFFFU << ETH_MACHT1R_HT63T32_Pos)            /*!< 0xFFFFFFFF */
7839 #define ETH_MACHT1R_HT63T32                 ETH_MACHT1R_HT63T32_Msk                             /*!< MAC Hash Table Second 32 Bits */
7840 #define ETH_MACHT1R_HT63T32_0               (0x1U << ETH_MACHT1R_HT63T32_Pos)                   /*!< 0x00000001 */
7841 #define ETH_MACHT1R_HT63T32_1               (0x2U << ETH_MACHT1R_HT63T32_Pos)                   /*!< 0x00000002 */
7842 #define ETH_MACHT1R_HT63T32_2               (0x4U << ETH_MACHT1R_HT63T32_Pos)                   /*!< 0x00000004 */
7843 #define ETH_MACHT1R_HT63T32_3               (0x8U << ETH_MACHT1R_HT63T32_Pos)                   /*!< 0x00000008 */
7844 #define ETH_MACHT1R_HT63T32_4               (0x10U << ETH_MACHT1R_HT63T32_Pos)                  /*!< 0x00000010 */
7845 #define ETH_MACHT1R_HT63T32_5               (0x20U << ETH_MACHT1R_HT63T32_Pos)                  /*!< 0x00000020 */
7846 #define ETH_MACHT1R_HT63T32_6               (0x40U << ETH_MACHT1R_HT63T32_Pos)                  /*!< 0x00000040 */
7847 #define ETH_MACHT1R_HT63T32_7               (0x80U << ETH_MACHT1R_HT63T32_Pos)                  /*!< 0x00000080 */
7848 #define ETH_MACHT1R_HT63T32_8               (0x100U << ETH_MACHT1R_HT63T32_Pos)                 /*!< 0x00000100 */
7849 #define ETH_MACHT1R_HT63T32_9               (0x200U << ETH_MACHT1R_HT63T32_Pos)                 /*!< 0x00000200 */
7850 #define ETH_MACHT1R_HT63T32_10              (0x400U << ETH_MACHT1R_HT63T32_Pos)                 /*!< 0x00000400 */
7851 #define ETH_MACHT1R_HT63T32_11              (0x800U << ETH_MACHT1R_HT63T32_Pos)                 /*!< 0x00000800 */
7852 #define ETH_MACHT1R_HT63T32_12              (0x1000U << ETH_MACHT1R_HT63T32_Pos)                /*!< 0x00001000 */
7853 #define ETH_MACHT1R_HT63T32_13              (0x2000U << ETH_MACHT1R_HT63T32_Pos)                /*!< 0x00002000 */
7854 #define ETH_MACHT1R_HT63T32_14              (0x4000U << ETH_MACHT1R_HT63T32_Pos)                /*!< 0x00004000 */
7855 #define ETH_MACHT1R_HT63T32_15              (0x8000U << ETH_MACHT1R_HT63T32_Pos)                /*!< 0x00008000 */
7856 #define ETH_MACHT1R_HT63T32_16              (0x10000U << ETH_MACHT1R_HT63T32_Pos)               /*!< 0x00010000 */
7857 #define ETH_MACHT1R_HT63T32_17              (0x20000U << ETH_MACHT1R_HT63T32_Pos)               /*!< 0x00020000 */
7858 #define ETH_MACHT1R_HT63T32_18              (0x40000U << ETH_MACHT1R_HT63T32_Pos)               /*!< 0x00040000 */
7859 #define ETH_MACHT1R_HT63T32_19              (0x80000U << ETH_MACHT1R_HT63T32_Pos)               /*!< 0x00080000 */
7860 #define ETH_MACHT1R_HT63T32_20              (0x100000U << ETH_MACHT1R_HT63T32_Pos)              /*!< 0x00100000 */
7861 #define ETH_MACHT1R_HT63T32_21              (0x200000U << ETH_MACHT1R_HT63T32_Pos)              /*!< 0x00200000 */
7862 #define ETH_MACHT1R_HT63T32_22              (0x400000U << ETH_MACHT1R_HT63T32_Pos)              /*!< 0x00400000 */
7863 #define ETH_MACHT1R_HT63T32_23              (0x800000U << ETH_MACHT1R_HT63T32_Pos)              /*!< 0x00800000 */
7864 #define ETH_MACHT1R_HT63T32_24              (0x1000000U << ETH_MACHT1R_HT63T32_Pos)             /*!< 0x01000000 */
7865 #define ETH_MACHT1R_HT63T32_25              (0x2000000U << ETH_MACHT1R_HT63T32_Pos)             /*!< 0x02000000 */
7866 #define ETH_MACHT1R_HT63T32_26              (0x4000000U << ETH_MACHT1R_HT63T32_Pos)             /*!< 0x04000000 */
7867 #define ETH_MACHT1R_HT63T32_27              (0x8000000U << ETH_MACHT1R_HT63T32_Pos)             /*!< 0x08000000 */
7868 #define ETH_MACHT1R_HT63T32_28              (0x10000000U << ETH_MACHT1R_HT63T32_Pos)            /*!< 0x10000000 */
7869 #define ETH_MACHT1R_HT63T32_29              (0x20000000U << ETH_MACHT1R_HT63T32_Pos)            /*!< 0x20000000 */
7870 #define ETH_MACHT1R_HT63T32_30              (0x40000000U << ETH_MACHT1R_HT63T32_Pos)            /*!< 0x40000000 */
7871 #define ETH_MACHT1R_HT63T32_31              (0x80000000U << ETH_MACHT1R_HT63T32_Pos)            /*!< 0x80000000 */
7872 
7873 /**************  Bit definition for ETH_MACVTR register  ***************/
7874 #define ETH_MACVTR_VL_Pos                   (0U)
7875 #define ETH_MACVTR_VL_Msk                   (0xFFFFU << ETH_MACVTR_VL_Pos)                      /*!< 0x0000FFFF */
7876 #define ETH_MACVTR_VL                       ETH_MACVTR_VL_Msk                                   /*!< VLAN Tag Identifier for Receive Packets */
7877 #define ETH_MACVTR_VL_0                     (0x1U << ETH_MACVTR_VL_Pos)                         /*!< 0x00000001 */
7878 #define ETH_MACVTR_VL_1                     (0x2U << ETH_MACVTR_VL_Pos)                         /*!< 0x00000002 */
7879 #define ETH_MACVTR_VL_2                     (0x4U << ETH_MACVTR_VL_Pos)                         /*!< 0x00000004 */
7880 #define ETH_MACVTR_VL_3                     (0x8U << ETH_MACVTR_VL_Pos)                         /*!< 0x00000008 */
7881 #define ETH_MACVTR_VL_4                     (0x10U << ETH_MACVTR_VL_Pos)                        /*!< 0x00000010 */
7882 #define ETH_MACVTR_VL_5                     (0x20U << ETH_MACVTR_VL_Pos)                        /*!< 0x00000020 */
7883 #define ETH_MACVTR_VL_6                     (0x40U << ETH_MACVTR_VL_Pos)                        /*!< 0x00000040 */
7884 #define ETH_MACVTR_VL_7                     (0x80U << ETH_MACVTR_VL_Pos)                        /*!< 0x00000080 */
7885 #define ETH_MACVTR_VL_8                     (0x100U << ETH_MACVTR_VL_Pos)                       /*!< 0x00000100 */
7886 #define ETH_MACVTR_VL_9                     (0x200U << ETH_MACVTR_VL_Pos)                       /*!< 0x00000200 */
7887 #define ETH_MACVTR_VL_10                    (0x400U << ETH_MACVTR_VL_Pos)                       /*!< 0x00000400 */
7888 #define ETH_MACVTR_VL_11                    (0x800U << ETH_MACVTR_VL_Pos)                       /*!< 0x00000800 */
7889 #define ETH_MACVTR_VL_12                    (0x1000U << ETH_MACVTR_VL_Pos)                      /*!< 0x00001000 */
7890 #define ETH_MACVTR_VL_13                    (0x2000U << ETH_MACVTR_VL_Pos)                      /*!< 0x00002000 */
7891 #define ETH_MACVTR_VL_14                    (0x4000U << ETH_MACVTR_VL_Pos)                      /*!< 0x00004000 */
7892 #define ETH_MACVTR_VL_15                    (0x8000U << ETH_MACVTR_VL_Pos)                      /*!< 0x00008000 */
7893 #define ETH_MACVTR_ETV_Pos                  (16U)
7894 #define ETH_MACVTR_ETV_Msk                  (0x1U << ETH_MACVTR_ETV_Pos)                        /*!< 0x00010000 */
7895 #define ETH_MACVTR_ETV                      ETH_MACVTR_ETV_Msk                                  /*!< Enable 12-Bit VLAN Tag Comparison */
7896 #define ETH_MACVTR_VTIM_Pos                 (17U)
7897 #define ETH_MACVTR_VTIM_Msk                 (0x1U << ETH_MACVTR_VTIM_Pos)                       /*!< 0x00020000 */
7898 #define ETH_MACVTR_VTIM                     ETH_MACVTR_VTIM_Msk                                 /*!< VLAN Tag Inverse Match Enable */
7899 #define ETH_MACVTR_ESVL_Pos                 (18U)
7900 #define ETH_MACVTR_ESVL_Msk                 (0x1U << ETH_MACVTR_ESVL_Pos)                       /*!< 0x00040000 */
7901 #define ETH_MACVTR_ESVL                     ETH_MACVTR_ESVL_Msk                                 /*!< Enable S-VLAN */
7902 #define ETH_MACVTR_ERSVLM_Pos               (19U)
7903 #define ETH_MACVTR_ERSVLM_Msk               (0x1U << ETH_MACVTR_ERSVLM_Pos)                     /*!< 0x00080000 */
7904 #define ETH_MACVTR_ERSVLM                   ETH_MACVTR_ERSVLM_Msk                               /*!< Enable Receive S-VLAN Match */
7905 #define ETH_MACVTR_DOVLTC_Pos               (20U)
7906 #define ETH_MACVTR_DOVLTC_Msk               (0x1U << ETH_MACVTR_DOVLTC_Pos)                     /*!< 0x00100000 */
7907 #define ETH_MACVTR_DOVLTC                   ETH_MACVTR_DOVLTC_Msk                               /*!< Disable VLAN Type Check */
7908 #define ETH_MACVTR_EVLS_Pos                 (21U)
7909 #define ETH_MACVTR_EVLS_Msk                 (0x3U << ETH_MACVTR_EVLS_Pos)                       /*!< 0x00600000 */
7910 #define ETH_MACVTR_EVLS                     ETH_MACVTR_EVLS_Msk                                 /*!< Enable VLAN Tag Stripping on Receive */
7911 #define ETH_MACVTR_EVLS_0                   (0x1U << ETH_MACVTR_EVLS_Pos)                  /*!< 0x00200000 */
7912 #define ETH_MACVTR_EVLS_1                   (0x2U << ETH_MACVTR_EVLS_Pos)                  /*!< 0x00400000 */
7913 #define ETH_MACVTR_EVLRXS_Pos               (24U)
7914 #define ETH_MACVTR_EVLRXS_Msk               (0x1U << ETH_MACVTR_EVLRXS_Pos)                     /*!< 0x01000000 */
7915 #define ETH_MACVTR_EVLRXS                   ETH_MACVTR_EVLRXS_Msk                               /*!< Enable VLAN Tag in Rx status */
7916 #define ETH_MACVTR_VTHM_Pos                 (25U)
7917 #define ETH_MACVTR_VTHM_Msk                 (0x1U << ETH_MACVTR_VTHM_Pos)                       /*!< 0x02000000 */
7918 #define ETH_MACVTR_VTHM                     ETH_MACVTR_VTHM_Msk                                 /*!< VLAN Tag Hash Table Match Enable */
7919 #define ETH_MACVTR_EDVLP_Pos                (26U)
7920 #define ETH_MACVTR_EDVLP_Msk                (0x1U << ETH_MACVTR_EDVLP_Pos)                      /*!< 0x04000000 */
7921 #define ETH_MACVTR_EDVLP                    ETH_MACVTR_EDVLP_Msk                                /*!< Enable Double VLAN Processing */
7922 #define ETH_MACVTR_ERIVLT_Pos               (27U)
7923 #define ETH_MACVTR_ERIVLT_Msk               (0x1U << ETH_MACVTR_ERIVLT_Pos)                     /*!< 0x08000000 */
7924 #define ETH_MACVTR_ERIVLT                   ETH_MACVTR_ERIVLT_Msk                               /*!< Enable Inner VLAN Tag */
7925 #define ETH_MACVTR_EIVLS_Pos                (28U)
7926 #define ETH_MACVTR_EIVLS_Msk                (0x3U << ETH_MACVTR_EIVLS_Pos)                      /*!< 0x30000000 */
7927 #define ETH_MACVTR_EIVLS                    ETH_MACVTR_EIVLS_Msk                                /*!< Enable Inner VLAN Tag Stripping on Receive */
7928 #define ETH_MACVTR_EIVLS_0                  (0x1U << ETH_MACVTR_EIVLS_Pos)               /*!< 0x10000000 */
7929 #define ETH_MACVTR_EIVLS_1                  (0x2U << ETH_MACVTR_EIVLS_Pos)               /*!< 0x20000000 */
7930 #define ETH_MACVTR_EIVLRXS_Pos              (31U)
7931 #define ETH_MACVTR_EIVLRXS_Msk              (0x1U << ETH_MACVTR_EIVLRXS_Pos)                    /*!< 0x80000000 */
7932 #define ETH_MACVTR_EIVLRXS                  ETH_MACVTR_EIVLRXS_Msk                              /*!< Enable Inner VLAN Tag in Rx Status */
7933 
7934 /**************  Bit definition for ETH_MACVHTR register  **************/
7935 #define ETH_MACVHTR_VLHT_Pos                (0U)
7936 #define ETH_MACVHTR_VLHT_Msk                (0xFFFFU << ETH_MACVHTR_VLHT_Pos)                   /*!< 0x0000FFFF */
7937 #define ETH_MACVHTR_VLHT                    ETH_MACVHTR_VLHT_Msk                                /*!< VLAN Hash Table */
7938 #define ETH_MACVHTR_VLHT_0                  (0x1U << ETH_MACVHTR_VLHT_Pos)                      /*!< 0x00000001 */
7939 #define ETH_MACVHTR_VLHT_1                  (0x2U << ETH_MACVHTR_VLHT_Pos)                      /*!< 0x00000002 */
7940 #define ETH_MACVHTR_VLHT_2                  (0x4U << ETH_MACVHTR_VLHT_Pos)                      /*!< 0x00000004 */
7941 #define ETH_MACVHTR_VLHT_3                  (0x8U << ETH_MACVHTR_VLHT_Pos)                      /*!< 0x00000008 */
7942 #define ETH_MACVHTR_VLHT_4                  (0x10U << ETH_MACVHTR_VLHT_Pos)                     /*!< 0x00000010 */
7943 #define ETH_MACVHTR_VLHT_5                  (0x20U << ETH_MACVHTR_VLHT_Pos)                     /*!< 0x00000020 */
7944 #define ETH_MACVHTR_VLHT_6                  (0x40U << ETH_MACVHTR_VLHT_Pos)                     /*!< 0x00000040 */
7945 #define ETH_MACVHTR_VLHT_7                  (0x80U << ETH_MACVHTR_VLHT_Pos)                     /*!< 0x00000080 */
7946 #define ETH_MACVHTR_VLHT_8                  (0x100U << ETH_MACVHTR_VLHT_Pos)                    /*!< 0x00000100 */
7947 #define ETH_MACVHTR_VLHT_9                  (0x200U << ETH_MACVHTR_VLHT_Pos)                    /*!< 0x00000200 */
7948 #define ETH_MACVHTR_VLHT_10                 (0x400U << ETH_MACVHTR_VLHT_Pos)                    /*!< 0x00000400 */
7949 #define ETH_MACVHTR_VLHT_11                 (0x800U << ETH_MACVHTR_VLHT_Pos)                    /*!< 0x00000800 */
7950 #define ETH_MACVHTR_VLHT_12                 (0x1000U << ETH_MACVHTR_VLHT_Pos)                   /*!< 0x00001000 */
7951 #define ETH_MACVHTR_VLHT_13                 (0x2000U << ETH_MACVHTR_VLHT_Pos)                   /*!< 0x00002000 */
7952 #define ETH_MACVHTR_VLHT_14                 (0x4000U << ETH_MACVHTR_VLHT_Pos)                   /*!< 0x00004000 */
7953 #define ETH_MACVHTR_VLHT_15                 (0x8000U << ETH_MACVHTR_VLHT_Pos)                   /*!< 0x00008000 */
7954 
7955 /**************  Bit definition for ETH_MACVIR register  ***************/
7956 #define ETH_MACVIR_VLT_Pos                  (0U)
7957 #define ETH_MACVIR_VLT_Msk                  (0xFFFFU << ETH_MACVIR_VLT_Pos)                     /*!< 0x0000FFFF */
7958 #define ETH_MACVIR_VLT                      ETH_MACVIR_VLT_Msk                                  /*!< VLAN Tag for Transmit Packets */
7959 #define ETH_MACVIR_VLT_0                    (0x1U << ETH_MACVIR_VLT_Pos)                        /*!< 0x00000001 */
7960 #define ETH_MACVIR_VLT_1                    (0x2U << ETH_MACVIR_VLT_Pos)                        /*!< 0x00000002 */
7961 #define ETH_MACVIR_VLT_2                    (0x4U << ETH_MACVIR_VLT_Pos)                        /*!< 0x00000004 */
7962 #define ETH_MACVIR_VLT_3                    (0x8U << ETH_MACVIR_VLT_Pos)                        /*!< 0x00000008 */
7963 #define ETH_MACVIR_VLT_4                    (0x10U << ETH_MACVIR_VLT_Pos)                       /*!< 0x00000010 */
7964 #define ETH_MACVIR_VLT_5                    (0x20U << ETH_MACVIR_VLT_Pos)                       /*!< 0x00000020 */
7965 #define ETH_MACVIR_VLT_6                    (0x40U << ETH_MACVIR_VLT_Pos)                       /*!< 0x00000040 */
7966 #define ETH_MACVIR_VLT_7                    (0x80U << ETH_MACVIR_VLT_Pos)                       /*!< 0x00000080 */
7967 #define ETH_MACVIR_VLT_8                    (0x100U << ETH_MACVIR_VLT_Pos)                      /*!< 0x00000100 */
7968 #define ETH_MACVIR_VLT_9                    (0x200U << ETH_MACVIR_VLT_Pos)                      /*!< 0x00000200 */
7969 #define ETH_MACVIR_VLT_10                   (0x400U << ETH_MACVIR_VLT_Pos)                      /*!< 0x00000400 */
7970 #define ETH_MACVIR_VLT_11                   (0x800U << ETH_MACVIR_VLT_Pos)                      /*!< 0x00000800 */
7971 #define ETH_MACVIR_VLT_12                   (0x1000U << ETH_MACVIR_VLT_Pos)                     /*!< 0x00001000 */
7972 #define ETH_MACVIR_VLT_13                   (0x2000U << ETH_MACVIR_VLT_Pos)                     /*!< 0x00002000 */
7973 #define ETH_MACVIR_VLT_14                   (0x4000U << ETH_MACVIR_VLT_Pos)                     /*!< 0x00004000 */
7974 #define ETH_MACVIR_VLT_15                   (0x8000U << ETH_MACVIR_VLT_Pos)                     /*!< 0x00008000 */
7975 #define ETH_MACVIR_VLC_Pos                  (16U)
7976 #define ETH_MACVIR_VLC_Msk                  (0x3U << ETH_MACVIR_VLC_Pos)                        /*!< 0x00030000 */
7977 #define ETH_MACVIR_VLC                      ETH_MACVIR_VLC_Msk                                  /*!< VLAN Tag Control in Transmit Packets */
7978 #define ETH_MACVIR_VLC_0                    (0x1U << ETH_MACVIR_VLC_Pos)                    /*!< 0x00010000 */
7979 #define ETH_MACVIR_VLC_1                    (0x2U << ETH_MACVIR_VLC_Pos)                    /*!< 0x00020000 */
7980 #define ETH_MACVIR_VLP_Pos                  (18U)
7981 #define ETH_MACVIR_VLP_Msk                  (0x1U << ETH_MACVIR_VLP_Pos)                        /*!< 0x00040000 */
7982 #define ETH_MACVIR_VLP                      ETH_MACVIR_VLP_Msk                                  /*!< VLAN Priority Control */
7983 #define ETH_MACVIR_CSVL_Pos                 (19U)
7984 #define ETH_MACVIR_CSVL_Msk                 (0x1U << ETH_MACVIR_CSVL_Pos)                       /*!< 0x00080000 */
7985 #define ETH_MACVIR_CSVL                     ETH_MACVIR_CSVL_Msk                                 /*!< C-VLAN or S-VLAN */
7986 #define ETH_MACVIR_VLTI_Pos                 (20U)
7987 #define ETH_MACVIR_VLTI_Msk                 (0x1U << ETH_MACVIR_VLTI_Pos)                       /*!< 0x00100000 */
7988 #define ETH_MACVIR_VLTI                     ETH_MACVIR_VLTI_Msk                                 /*!< VLAN Tag Input */
7989 
7990 /**************  Bit definition for ETH_MACIVIR register  **************/
7991 #define ETH_MACIVIR_VLT_Pos                 (0U)
7992 #define ETH_MACIVIR_VLT_Msk                 (0xFFFFU << ETH_MACIVIR_VLT_Pos)                    /*!< 0x0000FFFF */
7993 #define ETH_MACIVIR_VLT                     ETH_MACIVIR_VLT_Msk                                 /*!< VLAN Tag for Transmit Packets */
7994 #define ETH_MACIVIR_VLT_0                   (0x1U << ETH_MACIVIR_VLT_Pos)                       /*!< 0x00000001 */
7995 #define ETH_MACIVIR_VLT_1                   (0x2U << ETH_MACIVIR_VLT_Pos)                       /*!< 0x00000002 */
7996 #define ETH_MACIVIR_VLT_2                   (0x4U << ETH_MACIVIR_VLT_Pos)                       /*!< 0x00000004 */
7997 #define ETH_MACIVIR_VLT_3                   (0x8U << ETH_MACIVIR_VLT_Pos)                       /*!< 0x00000008 */
7998 #define ETH_MACIVIR_VLT_4                   (0x10U << ETH_MACIVIR_VLT_Pos)                      /*!< 0x00000010 */
7999 #define ETH_MACIVIR_VLT_5                   (0x20U << ETH_MACIVIR_VLT_Pos)                      /*!< 0x00000020 */
8000 #define ETH_MACIVIR_VLT_6                   (0x40U << ETH_MACIVIR_VLT_Pos)                      /*!< 0x00000040 */
8001 #define ETH_MACIVIR_VLT_7                   (0x80U << ETH_MACIVIR_VLT_Pos)                      /*!< 0x00000080 */
8002 #define ETH_MACIVIR_VLT_8                   (0x100U << ETH_MACIVIR_VLT_Pos)                     /*!< 0x00000100 */
8003 #define ETH_MACIVIR_VLT_9                   (0x200U << ETH_MACIVIR_VLT_Pos)                     /*!< 0x00000200 */
8004 #define ETH_MACIVIR_VLT_10                  (0x400U << ETH_MACIVIR_VLT_Pos)                     /*!< 0x00000400 */
8005 #define ETH_MACIVIR_VLT_11                  (0x800U << ETH_MACIVIR_VLT_Pos)                     /*!< 0x00000800 */
8006 #define ETH_MACIVIR_VLT_12                  (0x1000U << ETH_MACIVIR_VLT_Pos)                    /*!< 0x00001000 */
8007 #define ETH_MACIVIR_VLT_13                  (0x2000U << ETH_MACIVIR_VLT_Pos)                    /*!< 0x00002000 */
8008 #define ETH_MACIVIR_VLT_14                  (0x4000U << ETH_MACIVIR_VLT_Pos)                    /*!< 0x00004000 */
8009 #define ETH_MACIVIR_VLT_15                  (0x8000U << ETH_MACIVIR_VLT_Pos)                    /*!< 0x00008000 */
8010 #define ETH_MACIVIR_VLC_Pos                 (16U)
8011 #define ETH_MACIVIR_VLC_Msk                 (0x3U << ETH_MACIVIR_VLC_Pos)                       /*!< 0x00030000 */
8012 #define ETH_MACIVIR_VLC                     ETH_MACIVIR_VLC_Msk                                 /*!< VLAN Tag Control in Transmit Packets */
8013 #define ETH_MACIVIR_VLC_0                   (0x1U << ETH_MACIVIR_VLC_Pos)                   /*!< 0x00010000 */
8014 #define ETH_MACIVIR_VLC_1                   (0x2U << ETH_MACIVIR_VLC_Pos)                   /*!< 0x00020000 */
8015 #define ETH_MACIVIR_VLP_Pos                 (18U)
8016 #define ETH_MACIVIR_VLP_Msk                 (0x1U << ETH_MACIVIR_VLP_Pos)                       /*!< 0x00040000 */
8017 #define ETH_MACIVIR_VLP                     ETH_MACIVIR_VLP_Msk                                 /*!< VLAN Priority Control */
8018 #define ETH_MACIVIR_CSVL_Pos                (19U)
8019 #define ETH_MACIVIR_CSVL_Msk                (0x1U << ETH_MACIVIR_CSVL_Pos)                      /*!< 0x00080000 */
8020 #define ETH_MACIVIR_CSVL                    ETH_MACIVIR_CSVL_Msk                                /*!< C-VLAN or S-VLAN */
8021 #define ETH_MACIVIR_VLTI_Pos                (20U)
8022 #define ETH_MACIVIR_VLTI_Msk                (0x1U << ETH_MACIVIR_VLTI_Pos)                      /*!< 0x00100000 */
8023 #define ETH_MACIVIR_VLTI                    ETH_MACIVIR_VLTI_Msk                                /*!< VLAN Tag Input */
8024 
8025 /************  Bit definition for ETH_MACQ0TXFCR register  *************/
8026 #define ETH_MACQ0TXFCR_FCB_BPA_Pos          (0U)
8027 #define ETH_MACQ0TXFCR_FCB_BPA_Msk          (0x1U << ETH_MACQ0TXFCR_FCB_BPA_Pos)                /*!< 0x00000001 */
8028 #define ETH_MACQ0TXFCR_FCB_BPA              ETH_MACQ0TXFCR_FCB_BPA_Msk                          /*!< Flow Control Busy or Backpressure Activate */
8029 #define ETH_MACQ0TXFCR_TFE_Pos              (1U)
8030 #define ETH_MACQ0TXFCR_TFE_Msk              (0x1U << ETH_MACQ0TXFCR_TFE_Pos)                    /*!< 0x00000002 */
8031 #define ETH_MACQ0TXFCR_TFE                  ETH_MACQ0TXFCR_TFE_Msk                              /*!< Transmit Flow Control Enable */
8032 #define ETH_MACQ0TXFCR_PLT_Pos              (4U)
8033 #define ETH_MACQ0TXFCR_PLT_Msk              (0x7U << ETH_MACQ0TXFCR_PLT_Pos)                    /*!< 0x00000070 */
8034 #define ETH_MACQ0TXFCR_PLT                  ETH_MACQ0TXFCR_PLT_Msk                              /*!< Pause Low Threshold */
8035 #define ETH_MACQ0TXFCR_PLT_0                (0x1U << ETH_MACQ0TXFCR_PLT_Pos)                   /*!< 0x00000010 */
8036 #define ETH_MACQ0TXFCR_PLT_1                (0x2U << ETH_MACQ0TXFCR_PLT_Pos)                   /*!< 0x00000020 */
8037 #define ETH_MACQ0TXFCR_PLT_2                (0x4U << ETH_MACQ0TXFCR_PLT_Pos)                   /*!< 0x00000040 */
8038 #define ETH_MACQ0TXFCR_DZPQ_Pos             (7U)
8039 #define ETH_MACQ0TXFCR_DZPQ_Msk             (0x1U << ETH_MACQ0TXFCR_DZPQ_Pos)                   /*!< 0x00000080 */
8040 #define ETH_MACQ0TXFCR_DZPQ                 ETH_MACQ0TXFCR_DZPQ_Msk                             /*!< Disable Zero-Quanta Pause */
8041 #define ETH_MACQ0TXFCR_PT_Pos               (16U)
8042 #define ETH_MACQ0TXFCR_PT_Msk               (0xFFFFU << ETH_MACQ0TXFCR_PT_Pos)                  /*!< 0xFFFF0000 */
8043 #define ETH_MACQ0TXFCR_PT                   ETH_MACQ0TXFCR_PT_Msk                               /*!< Pause Time */
8044 #define ETH_MACQ0TXFCR_PT_0                 (0x1U << ETH_MACQ0TXFCR_PT_Pos)                 /*!< 0x00010000 */
8045 #define ETH_MACQ0TXFCR_PT_1                 (0x2U << ETH_MACQ0TXFCR_PT_Pos)                 /*!< 0x00020000 */
8046 #define ETH_MACQ0TXFCR_PT_2                 (0x4U << ETH_MACQ0TXFCR_PT_Pos)                 /*!< 0x00040000 */
8047 #define ETH_MACQ0TXFCR_PT_3                 (0x8U << ETH_MACQ0TXFCR_PT_Pos)                 /*!< 0x00080000 */
8048 #define ETH_MACQ0TXFCR_PT_4                 (0x10U << ETH_MACQ0TXFCR_PT_Pos)                /*!< 0x00100000 */
8049 #define ETH_MACQ0TXFCR_PT_5                 (0x20U << ETH_MACQ0TXFCR_PT_Pos)                /*!< 0x00200000 */
8050 #define ETH_MACQ0TXFCR_PT_6                 (0x40U << ETH_MACQ0TXFCR_PT_Pos)                /*!< 0x00400000 */
8051 #define ETH_MACQ0TXFCR_PT_7                 (0x80U << ETH_MACQ0TXFCR_PT_Pos)                /*!< 0x00800000 */
8052 #define ETH_MACQ0TXFCR_PT_8                 (0x100U << ETH_MACQ0TXFCR_PT_Pos)               /*!< 0x01000000 */
8053 #define ETH_MACQ0TXFCR_PT_9                 (0x200U << ETH_MACQ0TXFCR_PT_Pos)               /*!< 0x02000000 */
8054 #define ETH_MACQ0TXFCR_PT_10                (0x400U << ETH_MACQ0TXFCR_PT_Pos)               /*!< 0x04000000 */
8055 #define ETH_MACQ0TXFCR_PT_11                (0x800U << ETH_MACQ0TXFCR_PT_Pos)               /*!< 0x08000000 */
8056 #define ETH_MACQ0TXFCR_PT_12                (0x1000U << ETH_MACQ0TXFCR_PT_Pos)              /*!< 0x10000000 */
8057 #define ETH_MACQ0TXFCR_PT_13                (0x2000U << ETH_MACQ0TXFCR_PT_Pos)              /*!< 0x20000000 */
8058 #define ETH_MACQ0TXFCR_PT_14                (0x4000U << ETH_MACQ0TXFCR_PT_Pos)              /*!< 0x40000000 */
8059 #define ETH_MACQ0TXFCR_PT_15                (0x8000U << ETH_MACQ0TXFCR_PT_Pos)              /*!< 0x80000000 */
8060 
8061 /*************  Bit definition for ETH_MACRXFCR register  **************/
8062 #define ETH_MACRXFCR_RFE_Pos                (0U)
8063 #define ETH_MACRXFCR_RFE_Msk                (0x1U << ETH_MACRXFCR_RFE_Pos)                      /*!< 0x00000001 */
8064 #define ETH_MACRXFCR_RFE                    ETH_MACRXFCR_RFE_Msk                                /*!< Receive Flow Control Enable */
8065 #define ETH_MACRXFCR_UP_Pos                 (1U)
8066 #define ETH_MACRXFCR_UP_Msk                 (0x1U << ETH_MACRXFCR_UP_Pos)                       /*!< 0x00000002 */
8067 #define ETH_MACRXFCR_UP                     ETH_MACRXFCR_UP_Msk                                 /*!< Unicast Pause Packet Detect */
8068 
8069 /*************  Bit definition for ETH_MACTXQPMR register  *************/
8070 #define ETH_MACTXQPMR_PSTQ0_Pos             (0U)
8071 #define ETH_MACTXQPMR_PSTQ0_Msk             (0xFFU << ETH_MACTXQPMR_PSTQ0_Pos)                  /*!< 0x000000FF */
8072 #define ETH_MACTXQPMR_PSTQ0                 ETH_MACTXQPMR_PSTQ0_Msk                             /*!< Priorities Selected in Transmit Queue 0 */
8073 #define ETH_MACTXQPMR_PSTQ0_0               (0x1U << ETH_MACTXQPMR_PSTQ0_Pos)                   /*!< 0x00000001 */
8074 #define ETH_MACTXQPMR_PSTQ0_1               (0x2U << ETH_MACTXQPMR_PSTQ0_Pos)                   /*!< 0x00000002 */
8075 #define ETH_MACTXQPMR_PSTQ0_2               (0x4U << ETH_MACTXQPMR_PSTQ0_Pos)                   /*!< 0x00000004 */
8076 #define ETH_MACTXQPMR_PSTQ0_3               (0x8U << ETH_MACTXQPMR_PSTQ0_Pos)                   /*!< 0x00000008 */
8077 #define ETH_MACTXQPMR_PSTQ0_4               (0x10U << ETH_MACTXQPMR_PSTQ0_Pos)                  /*!< 0x00000010 */
8078 #define ETH_MACTXQPMR_PSTQ0_5               (0x20U << ETH_MACTXQPMR_PSTQ0_Pos)                  /*!< 0x00000020 */
8079 #define ETH_MACTXQPMR_PSTQ0_6               (0x40U << ETH_MACTXQPMR_PSTQ0_Pos)                  /*!< 0x00000040 */
8080 #define ETH_MACTXQPMR_PSTQ0_7               (0x80U << ETH_MACTXQPMR_PSTQ0_Pos)                  /*!< 0x00000080 */
8081 #define ETH_MACTXQPMR_PSTQ1_Pos             (8U)
8082 #define ETH_MACTXQPMR_PSTQ1_Msk             (0xFFU << ETH_MACTXQPMR_PSTQ1_Pos)                  /*!< 0x0000FF00 */
8083 #define ETH_MACTXQPMR_PSTQ1                 ETH_MACTXQPMR_PSTQ1_Msk                             /*!< Priorities Selected in Transmit Queue 1 */
8084 #define ETH_MACTXQPMR_PSTQ1_0               (0x1U << ETH_MACTXQPMR_PSTQ1_Pos)                 /*!< 0x00000100 */
8085 #define ETH_MACTXQPMR_PSTQ1_1               (0x2U << ETH_MACTXQPMR_PSTQ1_Pos)                 /*!< 0x00000200 */
8086 #define ETH_MACTXQPMR_PSTQ1_2               (0x4U << ETH_MACTXQPMR_PSTQ1_Pos)                 /*!< 0x00000400 */
8087 #define ETH_MACTXQPMR_PSTQ1_3               (0x8U << ETH_MACTXQPMR_PSTQ1_Pos)                 /*!< 0x00000800 */
8088 #define ETH_MACTXQPMR_PSTQ1_4               (0x10U << ETH_MACTXQPMR_PSTQ1_Pos)                /*!< 0x00001000 */
8089 #define ETH_MACTXQPMR_PSTQ1_5               (0x20U << ETH_MACTXQPMR_PSTQ1_Pos)                /*!< 0x00002000 */
8090 #define ETH_MACTXQPMR_PSTQ1_6               (0x40U << ETH_MACTXQPMR_PSTQ1_Pos)                /*!< 0x00004000 */
8091 #define ETH_MACTXQPMR_PSTQ1_7               (0x80U << ETH_MACTXQPMR_PSTQ1_Pos)                /*!< 0x00008000 */
8092 
8093 /*************  Bit definition for ETH_MACRXQC0R register  *************/
8094 #define ETH_MACRXQC0R_RXQ0EN_Pos            (0U)
8095 #define ETH_MACRXQC0R_RXQ0EN_Msk            (0x3U << ETH_MACRXQC0R_RXQ0EN_Pos)                  /*!< 0x00000003 */
8096 #define ETH_MACRXQC0R_RXQ0EN                ETH_MACRXQC0R_RXQ0EN_Msk                            /*!< Receive Queue 0 Enable */
8097 #define ETH_MACRXQC0R_RXQ0EN_0              (0x1U << ETH_MACRXQC0R_RXQ0EN_Pos)                  /*!< 0x00000001 */
8098 #define ETH_MACRXQC0R_RXQ0EN_1              (0x2U << ETH_MACRXQC0R_RXQ0EN_Pos)                  /*!< 0x00000002 */
8099 #define ETH_MACRXQC0R_RXQ1EN_Pos            (2U)
8100 #define ETH_MACRXQC0R_RXQ1EN_Msk            (0x3U << ETH_MACRXQC0R_RXQ1EN_Pos)                  /*!< 0x0000000C */
8101 #define ETH_MACRXQC0R_RXQ1EN                ETH_MACRXQC0R_RXQ1EN_Msk                            /*!< Receive Queue 1 Enable */
8102 #define ETH_MACRXQC0R_RXQ1EN_0              (0x1U << ETH_MACRXQC0R_RXQ1EN_Pos)                  /*!< 0x00000004 */
8103 #define ETH_MACRXQC0R_RXQ1EN_1              (0x2U << ETH_MACRXQC0R_RXQ1EN_Pos)                  /*!< 0x00000008 */
8104 
8105 /*************  Bit definition for ETH_MACRXQC1R register  *************/
8106 #define ETH_MACRXQC1R_AVCPQ_Pos             (0U)
8107 #define ETH_MACRXQC1R_AVCPQ_Msk             (0x7U << ETH_MACRXQC1R_AVCPQ_Pos)                   /*!< 0x00000007 */
8108 #define ETH_MACRXQC1R_AVCPQ                 ETH_MACRXQC1R_AVCPQ_Msk                             /*!< AV Untagged Control Packets Queue */
8109 #define ETH_MACRXQC1R_AVCPQ_0               (0x1U << ETH_MACRXQC1R_AVCPQ_Pos)                   /*!< 0x00000001 */
8110 #define ETH_MACRXQC1R_AVCPQ_1               (0x2U << ETH_MACRXQC1R_AVCPQ_Pos)                   /*!< 0x00000002 */
8111 #define ETH_MACRXQC1R_AVCPQ_2               (0x4U << ETH_MACRXQC1R_AVCPQ_Pos)                   /*!< 0x00000004 */
8112 #define ETH_MACRXQC1R_AVPTPQ_Pos            (4U)
8113 #define ETH_MACRXQC1R_AVPTPQ_Msk            (0x7U << ETH_MACRXQC1R_AVPTPQ_Pos)                  /*!< 0x00000070 */
8114 #define ETH_MACRXQC1R_AVPTPQ                ETH_MACRXQC1R_AVPTPQ_Msk                            /*!< AV PTP Packets Queue */
8115 #define ETH_MACRXQC1R_AVPTPQ_0              (0x1U << ETH_MACRXQC1R_AVPTPQ_Pos)                 /*!< 0x00000010 */
8116 #define ETH_MACRXQC1R_AVPTPQ_1              (0x2U << ETH_MACRXQC1R_AVPTPQ_Pos)                 /*!< 0x00000020 */
8117 #define ETH_MACRXQC1R_AVPTPQ_2              (0x4U << ETH_MACRXQC1R_AVPTPQ_Pos)                 /*!< 0x00000040 */
8118 #define ETH_MACRXQC1R_UPQ_Pos               (12U)
8119 #define ETH_MACRXQC1R_UPQ_Msk               (0x7U << ETH_MACRXQC1R_UPQ_Pos)                     /*!< 0x00007000 */
8120 #define ETH_MACRXQC1R_UPQ                   ETH_MACRXQC1R_UPQ_Msk                               /*!< Untagged Packet Queue */
8121 #define ETH_MACRXQC1R_UPQ_0                 (0x1U << ETH_MACRXQC1R_UPQ_Pos)                  /*!< 0x00001000 */
8122 #define ETH_MACRXQC1R_UPQ_1                 (0x2U << ETH_MACRXQC1R_UPQ_Pos)                  /*!< 0x00002000 */
8123 #define ETH_MACRXQC1R_UPQ_2                 (0x4U << ETH_MACRXQC1R_UPQ_Pos)                  /*!< 0x00004000 */
8124 #define ETH_MACRXQC1R_MCBCQ_Pos             (16U)
8125 #define ETH_MACRXQC1R_MCBCQ_Msk             (0x7U << ETH_MACRXQC1R_MCBCQ_Pos)                   /*!< 0x00070000 */
8126 #define ETH_MACRXQC1R_MCBCQ                 ETH_MACRXQC1R_MCBCQ_Msk                             /*!< Multicast and Broadcast Queue */
8127 #define ETH_MACRXQC1R_MCBCQ_0               (0x1U << ETH_MACRXQC1R_MCBCQ_Pos)               /*!< 0x00010000 */
8128 #define ETH_MACRXQC1R_MCBCQ_1               (0x2U << ETH_MACRXQC1R_MCBCQ_Pos)               /*!< 0x00020000 */
8129 #define ETH_MACRXQC1R_MCBCQ_2               (0x4U << ETH_MACRXQC1R_MCBCQ_Pos)               /*!< 0x00040000 */
8130 #define ETH_MACRXQC1R_MCBCQEN_Pos           (20U)
8131 #define ETH_MACRXQC1R_MCBCQEN_Msk           (0x1U << ETH_MACRXQC1R_MCBCQEN_Pos)                 /*!< 0x00100000 */
8132 #define ETH_MACRXQC1R_MCBCQEN               ETH_MACRXQC1R_MCBCQEN_Msk                           /*!< Multicast and Broadcast Queue Enable */
8133 #define ETH_MACRXQC1R_TACPQE_Pos            (21U)
8134 #define ETH_MACRXQC1R_TACPQE_Msk            (0x1U << ETH_MACRXQC1R_TACPQE_Pos)                  /*!< 0x00200000 */
8135 #define ETH_MACRXQC1R_TACPQE                ETH_MACRXQC1R_TACPQE_Msk                            /*!< Tagged AV Control Packets Queuing Enable. */
8136 
8137 /*************  Bit definition for ETH_MACRXQC2R register  *************/
8138 #define ETH_MACRXQC2R_PSRQ0_Pos             (0U)
8139 #define ETH_MACRXQC2R_PSRQ0_Msk             (0xFFU << ETH_MACRXQC2R_PSRQ0_Pos)                  /*!< 0x000000FF */
8140 #define ETH_MACRXQC2R_PSRQ0                 ETH_MACRXQC2R_PSRQ0_Msk                             /*!< Priorities Selected in the Receive Queue 0 */
8141 #define ETH_MACRXQC2R_PSRQ0_0               (0x1U << ETH_MACRXQC2R_PSRQ0_Pos)                   /*!< 0x00000001 */
8142 #define ETH_MACRXQC2R_PSRQ0_1               (0x2U << ETH_MACRXQC2R_PSRQ0_Pos)                   /*!< 0x00000002 */
8143 #define ETH_MACRXQC2R_PSRQ0_2               (0x4U << ETH_MACRXQC2R_PSRQ0_Pos)                   /*!< 0x00000004 */
8144 #define ETH_MACRXQC2R_PSRQ0_3               (0x8U << ETH_MACRXQC2R_PSRQ0_Pos)                   /*!< 0x00000008 */
8145 #define ETH_MACRXQC2R_PSRQ0_4               (0x10U << ETH_MACRXQC2R_PSRQ0_Pos)                  /*!< 0x00000010 */
8146 #define ETH_MACRXQC2R_PSRQ0_5               (0x20U << ETH_MACRXQC2R_PSRQ0_Pos)                  /*!< 0x00000020 */
8147 #define ETH_MACRXQC2R_PSRQ0_6               (0x40U << ETH_MACRXQC2R_PSRQ0_Pos)                  /*!< 0x00000040 */
8148 #define ETH_MACRXQC2R_PSRQ0_7               (0x80U << ETH_MACRXQC2R_PSRQ0_Pos)                  /*!< 0x00000080 */
8149 #define ETH_MACRXQC2R_PSRQ1_Pos             (8U)
8150 #define ETH_MACRXQC2R_PSRQ1_Msk             (0xFFU << ETH_MACRXQC2R_PSRQ1_Pos)                  /*!< 0x0000FF00 */
8151 #define ETH_MACRXQC2R_PSRQ1                 ETH_MACRXQC2R_PSRQ1_Msk                             /*!< Priorities Selected in the Receive Queue 1 */
8152 #define ETH_MACRXQC2R_PSRQ1_0               (0x1U << ETH_MACRXQC2R_PSRQ1_Pos)                 /*!< 0x00000100 */
8153 #define ETH_MACRXQC2R_PSRQ1_1               (0x2U << ETH_MACRXQC2R_PSRQ1_Pos)                 /*!< 0x00000200 */
8154 #define ETH_MACRXQC2R_PSRQ1_2               (0x4U << ETH_MACRXQC2R_PSRQ1_Pos)                 /*!< 0x00000400 */
8155 #define ETH_MACRXQC2R_PSRQ1_3               (0x8U << ETH_MACRXQC2R_PSRQ1_Pos)                 /*!< 0x00000800 */
8156 #define ETH_MACRXQC2R_PSRQ1_4               (0x10U << ETH_MACRXQC2R_PSRQ1_Pos)                /*!< 0x00001000 */
8157 #define ETH_MACRXQC2R_PSRQ1_5               (0x20U << ETH_MACRXQC2R_PSRQ1_Pos)                /*!< 0x00002000 */
8158 #define ETH_MACRXQC2R_PSRQ1_6               (0x40U << ETH_MACRXQC2R_PSRQ1_Pos)                /*!< 0x00004000 */
8159 #define ETH_MACRXQC2R_PSRQ1_7               (0x80U << ETH_MACRXQC2R_PSRQ1_Pos)                /*!< 0x00008000 */
8160 
8161 /**************  Bit definition for ETH_MACISR register  ***************/
8162 #define ETH_MACISR_RGSMIIIS_Pos             (0U)
8163 #define ETH_MACISR_RGSMIIIS_Msk             (0x1U << ETH_MACISR_RGSMIIIS_Pos)                   /*!< 0x00000001 */
8164 #define ETH_MACISR_RGSMIIIS                 ETH_MACISR_RGSMIIIS_Msk                             /*!< RGMII or SMII Interrupt Status */
8165 #define ETH_MACISR_PHYIS_Pos                (3U)
8166 #define ETH_MACISR_PHYIS_Msk                (0x1U << ETH_MACISR_PHYIS_Pos)                      /*!< 0x00000008 */
8167 #define ETH_MACISR_PHYIS                    ETH_MACISR_PHYIS_Msk                                /*!< PHY Interrupt */
8168 #define ETH_MACISR_PMTIS_Pos                (4U)
8169 #define ETH_MACISR_PMTIS_Msk                (0x1U << ETH_MACISR_PMTIS_Pos)                      /*!< 0x00000010 */
8170 #define ETH_MACISR_PMTIS                    ETH_MACISR_PMTIS_Msk                                /*!< PMT Interrupt Status */
8171 #define ETH_MACISR_LPIIS_Pos                (5U)
8172 #define ETH_MACISR_LPIIS_Msk                (0x1U << ETH_MACISR_LPIIS_Pos)                      /*!< 0x00000020 */
8173 #define ETH_MACISR_LPIIS                    ETH_MACISR_LPIIS_Msk                                /*!< LPI Interrupt Status */
8174 #define ETH_MACISR_MMCIS_Pos                (8U)
8175 #define ETH_MACISR_MMCIS_Msk                (0x1U << ETH_MACISR_MMCIS_Pos)                      /*!< 0x00000100 */
8176 #define ETH_MACISR_MMCIS                    ETH_MACISR_MMCIS_Msk                                /*!< MMC Interrupt Status */
8177 #define ETH_MACISR_MMCRXIS_Pos              (9U)
8178 #define ETH_MACISR_MMCRXIS_Msk              (0x1U << ETH_MACISR_MMCRXIS_Pos)                    /*!< 0x00000200 */
8179 #define ETH_MACISR_MMCRXIS                  ETH_MACISR_MMCRXIS_Msk                              /*!< MMC Receive Interrupt Status */
8180 #define ETH_MACISR_MMCTXIS_Pos              (10U)
8181 #define ETH_MACISR_MMCTXIS_Msk              (0x1U << ETH_MACISR_MMCTXIS_Pos)                    /*!< 0x00000400 */
8182 #define ETH_MACISR_MMCTXIS                  ETH_MACISR_MMCTXIS_Msk                              /*!< MMC Transmit Interrupt Status */
8183 #define ETH_MACISR_TSIS_Pos                 (12U)
8184 #define ETH_MACISR_TSIS_Msk                 (0x1U << ETH_MACISR_TSIS_Pos)                       /*!< 0x00001000 */
8185 #define ETH_MACISR_TSIS                     ETH_MACISR_TSIS_Msk                                 /*!< Timestamp Interrupt Status */
8186 #define ETH_MACISR_TXSTSIS_Pos              (13U)
8187 #define ETH_MACISR_TXSTSIS_Msk              (0x1U << ETH_MACISR_TXSTSIS_Pos)                    /*!< 0x00002000 */
8188 #define ETH_MACISR_TXSTSIS                  ETH_MACISR_TXSTSIS_Msk                              /*!< Transmit Status Interrupt */
8189 #define ETH_MACISR_RXSTSIS_Pos              (14U)
8190 #define ETH_MACISR_RXSTSIS_Msk              (0x1U << ETH_MACISR_RXSTSIS_Pos)                    /*!< 0x00004000 */
8191 #define ETH_MACISR_RXSTSIS                  ETH_MACISR_RXSTSIS_Msk                              /*!< Receive Status Interrupt */
8192 
8193 /**************  Bit definition for ETH_MACIER register  ***************/
8194 #define ETH_MACIER_RGSMIIIE_Pos             (0U)
8195 #define ETH_MACIER_RGSMIIIE_Msk             (0x1U << ETH_MACIER_RGSMIIIE_Pos)                   /*!< 0x00000001 */
8196 #define ETH_MACIER_RGSMIIIE                 ETH_MACIER_RGSMIIIE_Msk                             /*!< RGMII or SMII Interrupt Enable */
8197 #define ETH_MACIER_PHYIE_Pos                (3U)
8198 #define ETH_MACIER_PHYIE_Msk                (0x1U << ETH_MACIER_PHYIE_Pos)                      /*!< 0x00000008 */
8199 #define ETH_MACIER_PHYIE                    ETH_MACIER_PHYIE_Msk                                /*!< PHY Interrupt Enable */
8200 #define ETH_MACIER_PMTIE_Pos                (4U)
8201 #define ETH_MACIER_PMTIE_Msk                (0x1U << ETH_MACIER_PMTIE_Pos)                      /*!< 0x00000010 */
8202 #define ETH_MACIER_PMTIE                    ETH_MACIER_PMTIE_Msk                                /*!< PMT Interrupt Enable */
8203 #define ETH_MACIER_LPIIE_Pos                (5U)
8204 #define ETH_MACIER_LPIIE_Msk                (0x1U << ETH_MACIER_LPIIE_Pos)                      /*!< 0x00000020 */
8205 #define ETH_MACIER_LPIIE                    ETH_MACIER_LPIIE_Msk                                /*!< LPI Interrupt Enable */
8206 #define ETH_MACIER_TSIE_Pos                 (12U)
8207 #define ETH_MACIER_TSIE_Msk                 (0x1U << ETH_MACIER_TSIE_Pos)                       /*!< 0x00001000 */
8208 #define ETH_MACIER_TSIE                     ETH_MACIER_TSIE_Msk                                 /*!< Timestamp Interrupt Enable */
8209 #define ETH_MACIER_TXSTSIE_Pos              (13U)
8210 #define ETH_MACIER_TXSTSIE_Msk              (0x1U << ETH_MACIER_TXSTSIE_Pos)                    /*!< 0x00002000 */
8211 #define ETH_MACIER_TXSTSIE                  ETH_MACIER_TXSTSIE_Msk                              /*!< Transmit Status Interrupt Enable */
8212 #define ETH_MACIER_RXSTSIE_Pos              (14U)
8213 #define ETH_MACIER_RXSTSIE_Msk              (0x1U << ETH_MACIER_RXSTSIE_Pos)                    /*!< 0x00004000 */
8214 #define ETH_MACIER_RXSTSIE                  ETH_MACIER_RXSTSIE_Msk                              /*!< Receive Status Interrupt Enable */
8215 
8216 /*************  Bit definition for ETH_MACRXTXSR register  *************/
8217 #define ETH_MACRXTXSR_TJT_Pos               (0U)
8218 #define ETH_MACRXTXSR_TJT_Msk               (0x1U << ETH_MACRXTXSR_TJT_Pos)                     /*!< 0x00000001 */
8219 #define ETH_MACRXTXSR_TJT                   ETH_MACRXTXSR_TJT_Msk                               /*!< Transmit Jabber Timeout */
8220 #define ETH_MACRXTXSR_NCARR_Pos             (1U)
8221 #define ETH_MACRXTXSR_NCARR_Msk             (0x1U << ETH_MACRXTXSR_NCARR_Pos)                   /*!< 0x00000002 */
8222 #define ETH_MACRXTXSR_NCARR                 ETH_MACRXTXSR_NCARR_Msk                             /*!< No Carrier */
8223 #define ETH_MACRXTXSR_LCARR_Pos             (2U)
8224 #define ETH_MACRXTXSR_LCARR_Msk             (0x1U << ETH_MACRXTXSR_LCARR_Pos)                   /*!< 0x00000004 */
8225 #define ETH_MACRXTXSR_LCARR                 ETH_MACRXTXSR_LCARR_Msk                             /*!< Loss of Carrier */
8226 #define ETH_MACRXTXSR_EXDEF_Pos             (3U)
8227 #define ETH_MACRXTXSR_EXDEF_Msk             (0x1U << ETH_MACRXTXSR_EXDEF_Pos)                   /*!< 0x00000008 */
8228 #define ETH_MACRXTXSR_EXDEF                 ETH_MACRXTXSR_EXDEF_Msk                             /*!< Excessive Deferral */
8229 #define ETH_MACRXTXSR_LCOL_Pos              (4U)
8230 #define ETH_MACRXTXSR_LCOL_Msk              (0x1U << ETH_MACRXTXSR_LCOL_Pos)                    /*!< 0x00000010 */
8231 #define ETH_MACRXTXSR_LCOL                  ETH_MACRXTXSR_LCOL_Msk                              /*!< Late Collision */
8232 #define ETH_MACRXTXSR_EXCOL_Pos             (5U)
8233 #define ETH_MACRXTXSR_EXCOL_Msk             (0x1U << ETH_MACRXTXSR_EXCOL_Pos)                   /*!< 0x00000020 */
8234 #define ETH_MACRXTXSR_EXCOL                 ETH_MACRXTXSR_EXCOL_Msk                             /*!< Excessive Collisions */
8235 #define ETH_MACRXTXSR_RWT_Pos               (8U)
8236 #define ETH_MACRXTXSR_RWT_Msk               (0x1U << ETH_MACRXTXSR_RWT_Pos)                     /*!< 0x00000100 */
8237 #define ETH_MACRXTXSR_RWT                   ETH_MACRXTXSR_RWT_Msk                               /*!< Receive Watchdog Timeout */
8238 
8239 /**************  Bit definition for ETH_MACPCSR register  **************/
8240 #define ETH_MACPCSR_PWRDWN_Pos              (0U)
8241 #define ETH_MACPCSR_PWRDWN_Msk              (0x1U << ETH_MACPCSR_PWRDWN_Pos)                    /*!< 0x00000001 */
8242 #define ETH_MACPCSR_PWRDWN                  ETH_MACPCSR_PWRDWN_Msk                              /*!< Power Down */
8243 #define ETH_MACPCSR_MGKPKTEN_Pos            (1U)
8244 #define ETH_MACPCSR_MGKPKTEN_Msk            (0x1U << ETH_MACPCSR_MGKPKTEN_Pos)                  /*!< 0x00000002 */
8245 #define ETH_MACPCSR_MGKPKTEN                ETH_MACPCSR_MGKPKTEN_Msk                            /*!< Magic Packet Enable */
8246 #define ETH_MACPCSR_RWKPKTEN_Pos            (2U)
8247 #define ETH_MACPCSR_RWKPKTEN_Msk            (0x1U << ETH_MACPCSR_RWKPKTEN_Pos)                  /*!< 0x00000004 */
8248 #define ETH_MACPCSR_RWKPKTEN                ETH_MACPCSR_RWKPKTEN_Msk                            /*!< Remote wakeup Packet Enable */
8249 #define ETH_MACPCSR_MGKPRCVD_Pos            (5U)
8250 #define ETH_MACPCSR_MGKPRCVD_Msk            (0x1U << ETH_MACPCSR_MGKPRCVD_Pos)                  /*!< 0x00000020 */
8251 #define ETH_MACPCSR_MGKPRCVD                ETH_MACPCSR_MGKPRCVD_Msk                            /*!< Magic Packet Received */
8252 #define ETH_MACPCSR_RWKPRCVD_Pos            (6U)
8253 #define ETH_MACPCSR_RWKPRCVD_Msk            (0x1U << ETH_MACPCSR_RWKPRCVD_Pos)                  /*!< 0x00000040 */
8254 #define ETH_MACPCSR_RWKPRCVD                ETH_MACPCSR_RWKPRCVD_Msk                            /*!< Remote wakeup Packet Received */
8255 #define ETH_MACPCSR_GLBLUCAST_Pos           (9U)
8256 #define ETH_MACPCSR_GLBLUCAST_Msk           (0x1U << ETH_MACPCSR_GLBLUCAST_Pos)                 /*!< 0x00000200 */
8257 #define ETH_MACPCSR_GLBLUCAST               ETH_MACPCSR_GLBLUCAST_Msk                           /*!< Global Unicast */
8258 #define ETH_MACPCSR_RWKPFE_Pos              (10U)
8259 #define ETH_MACPCSR_RWKPFE_Msk              (0x1U << ETH_MACPCSR_RWKPFE_Pos)                    /*!< 0x00000400 */
8260 #define ETH_MACPCSR_RWKPFE                  ETH_MACPCSR_RWKPFE_Msk                              /*!< Remote wakeup Packet Forwarding Enable */
8261 #define ETH_MACPCSR_RWKPTR_Pos              (24U)
8262 #define ETH_MACPCSR_RWKPTR_Msk              (0x1FU << ETH_MACPCSR_RWKPTR_Pos)                   /*!< 0x1F000000 */
8263 #define ETH_MACPCSR_RWKPTR                  ETH_MACPCSR_RWKPTR_Msk                              /*!< Remote wakeup FIFO Pointer */
8264 #define ETH_MACPCSR_RWKPTR_0                (0x1U << ETH_MACPCSR_RWKPTR_Pos)              /*!< 0x01000000 */
8265 #define ETH_MACPCSR_RWKPTR_1                (0x2U << ETH_MACPCSR_RWKPTR_Pos)              /*!< 0x02000000 */
8266 #define ETH_MACPCSR_RWKPTR_2                (0x4U << ETH_MACPCSR_RWKPTR_Pos)              /*!< 0x04000000 */
8267 #define ETH_MACPCSR_RWKPTR_3                (0x8U << ETH_MACPCSR_RWKPTR_Pos)              /*!< 0x08000000 */
8268 #define ETH_MACPCSR_RWKPTR_4                (0x10U << ETH_MACPCSR_RWKPTR_Pos)             /*!< 0x10000000 */
8269 #define ETH_MACPCSR_RWKFILTRST_Pos          (31U)
8270 #define ETH_MACPCSR_RWKFILTRST_Msk          (0x1U << ETH_MACPCSR_RWKFILTRST_Pos)                /*!< 0x80000000 */
8271 #define ETH_MACPCSR_RWKFILTRST              ETH_MACPCSR_RWKFILTRST_Msk                          /*!< Remote wakeup Packet Filter Register Pointer Reset */
8272 
8273 /*************  Bit definition for ETH_MACRWKPFR register  *************/
8274 #define ETH_MACRWKPFR_MACRWKPFR_Pos         (0U)
8275 #define ETH_MACRWKPFR_MACRWKPFR_Msk         (0xFFFFFFFFU << ETH_MACRWKPFR_MACRWKPFR_Pos)        /*!< 0xFFFFFFFF */
8276 #define ETH_MACRWKPFR_MACRWKPFR             ETH_MACRWKPFR_MACRWKPFR_Msk                         /*!< Remote wakeup packet filter */
8277 #define ETH_MACRWKPFR_MACRWKPFR_0           (0x1U << ETH_MACRWKPFR_MACRWKPFR_Pos)               /*!< 0x00000001 */
8278 #define ETH_MACRWKPFR_MACRWKPFR_1           (0x2U << ETH_MACRWKPFR_MACRWKPFR_Pos)               /*!< 0x00000002 */
8279 #define ETH_MACRWKPFR_MACRWKPFR_2           (0x4U << ETH_MACRWKPFR_MACRWKPFR_Pos)               /*!< 0x00000004 */
8280 #define ETH_MACRWKPFR_MACRWKPFR_3           (0x8U << ETH_MACRWKPFR_MACRWKPFR_Pos)               /*!< 0x00000008 */
8281 #define ETH_MACRWKPFR_MACRWKPFR_4           (0x10U << ETH_MACRWKPFR_MACRWKPFR_Pos)              /*!< 0x00000010 */
8282 #define ETH_MACRWKPFR_MACRWKPFR_5           (0x20U << ETH_MACRWKPFR_MACRWKPFR_Pos)              /*!< 0x00000020 */
8283 #define ETH_MACRWKPFR_MACRWKPFR_6           (0x40U << ETH_MACRWKPFR_MACRWKPFR_Pos)              /*!< 0x00000040 */
8284 #define ETH_MACRWKPFR_MACRWKPFR_7           (0x80U << ETH_MACRWKPFR_MACRWKPFR_Pos)              /*!< 0x00000080 */
8285 #define ETH_MACRWKPFR_MACRWKPFR_8           (0x100U << ETH_MACRWKPFR_MACRWKPFR_Pos)             /*!< 0x00000100 */
8286 #define ETH_MACRWKPFR_MACRWKPFR_9           (0x200U << ETH_MACRWKPFR_MACRWKPFR_Pos)             /*!< 0x00000200 */
8287 #define ETH_MACRWKPFR_MACRWKPFR_10          (0x400U << ETH_MACRWKPFR_MACRWKPFR_Pos)             /*!< 0x00000400 */
8288 #define ETH_MACRWKPFR_MACRWKPFR_11          (0x800U << ETH_MACRWKPFR_MACRWKPFR_Pos)             /*!< 0x00000800 */
8289 #define ETH_MACRWKPFR_MACRWKPFR_12          (0x1000U << ETH_MACRWKPFR_MACRWKPFR_Pos)            /*!< 0x00001000 */
8290 #define ETH_MACRWKPFR_MACRWKPFR_13          (0x2000U << ETH_MACRWKPFR_MACRWKPFR_Pos)            /*!< 0x00002000 */
8291 #define ETH_MACRWKPFR_MACRWKPFR_14          (0x4000U << ETH_MACRWKPFR_MACRWKPFR_Pos)            /*!< 0x00004000 */
8292 #define ETH_MACRWKPFR_MACRWKPFR_15          (0x8000U << ETH_MACRWKPFR_MACRWKPFR_Pos)            /*!< 0x00008000 */
8293 #define ETH_MACRWKPFR_MACRWKPFR_16          (0x10000U << ETH_MACRWKPFR_MACRWKPFR_Pos)           /*!< 0x00010000 */
8294 #define ETH_MACRWKPFR_MACRWKPFR_17          (0x20000U << ETH_MACRWKPFR_MACRWKPFR_Pos)           /*!< 0x00020000 */
8295 #define ETH_MACRWKPFR_MACRWKPFR_18          (0x40000U << ETH_MACRWKPFR_MACRWKPFR_Pos)           /*!< 0x00040000 */
8296 #define ETH_MACRWKPFR_MACRWKPFR_19          (0x80000U << ETH_MACRWKPFR_MACRWKPFR_Pos)           /*!< 0x00080000 */
8297 #define ETH_MACRWKPFR_MACRWKPFR_20          (0x100000U << ETH_MACRWKPFR_MACRWKPFR_Pos)          /*!< 0x00100000 */
8298 #define ETH_MACRWKPFR_MACRWKPFR_21          (0x200000U << ETH_MACRWKPFR_MACRWKPFR_Pos)          /*!< 0x00200000 */
8299 #define ETH_MACRWKPFR_MACRWKPFR_22          (0x400000U << ETH_MACRWKPFR_MACRWKPFR_Pos)          /*!< 0x00400000 */
8300 #define ETH_MACRWKPFR_MACRWKPFR_23          (0x800000U << ETH_MACRWKPFR_MACRWKPFR_Pos)          /*!< 0x00800000 */
8301 #define ETH_MACRWKPFR_MACRWKPFR_24          (0x1000000U << ETH_MACRWKPFR_MACRWKPFR_Pos)         /*!< 0x01000000 */
8302 #define ETH_MACRWKPFR_MACRWKPFR_25          (0x2000000U << ETH_MACRWKPFR_MACRWKPFR_Pos)         /*!< 0x02000000 */
8303 #define ETH_MACRWKPFR_MACRWKPFR_26          (0x4000000U << ETH_MACRWKPFR_MACRWKPFR_Pos)         /*!< 0x04000000 */
8304 #define ETH_MACRWKPFR_MACRWKPFR_27          (0x8000000U << ETH_MACRWKPFR_MACRWKPFR_Pos)         /*!< 0x08000000 */
8305 #define ETH_MACRWKPFR_MACRWKPFR_28          (0x10000000U << ETH_MACRWKPFR_MACRWKPFR_Pos)        /*!< 0x10000000 */
8306 #define ETH_MACRWKPFR_MACRWKPFR_29          (0x20000000U << ETH_MACRWKPFR_MACRWKPFR_Pos)        /*!< 0x20000000 */
8307 #define ETH_MACRWKPFR_MACRWKPFR_30          (0x40000000U << ETH_MACRWKPFR_MACRWKPFR_Pos)        /*!< 0x40000000 */
8308 #define ETH_MACRWKPFR_MACRWKPFR_31          (0x80000000U << ETH_MACRWKPFR_MACRWKPFR_Pos)        /*!< 0x80000000 */
8309 
8310 /**************  Bit definition for ETH_MACLCSR register  **************/
8311 #define ETH_MACLCSR_TLPIEN_Pos              (0U)
8312 #define ETH_MACLCSR_TLPIEN_Msk              (0x1U << ETH_MACLCSR_TLPIEN_Pos)                    /*!< 0x00000001 */
8313 #define ETH_MACLCSR_TLPIEN                  ETH_MACLCSR_TLPIEN_Msk                              /*!< Transmit LPI Entry */
8314 #define ETH_MACLCSR_TLPIEX_Pos              (1U)
8315 #define ETH_MACLCSR_TLPIEX_Msk              (0x1U << ETH_MACLCSR_TLPIEX_Pos)                    /*!< 0x00000002 */
8316 #define ETH_MACLCSR_TLPIEX                  ETH_MACLCSR_TLPIEX_Msk                              /*!< Transmit LPI Exit */
8317 #define ETH_MACLCSR_RLPIEN_Pos              (2U)
8318 #define ETH_MACLCSR_RLPIEN_Msk              (0x1U << ETH_MACLCSR_RLPIEN_Pos)                    /*!< 0x00000004 */
8319 #define ETH_MACLCSR_RLPIEN                  ETH_MACLCSR_RLPIEN_Msk                              /*!< Receive LPI Entry */
8320 #define ETH_MACLCSR_RLPIEX_Pos              (3U)
8321 #define ETH_MACLCSR_RLPIEX_Msk              (0x1U << ETH_MACLCSR_RLPIEX_Pos)                    /*!< 0x00000008 */
8322 #define ETH_MACLCSR_RLPIEX                  ETH_MACLCSR_RLPIEX_Msk                              /*!< Receive LPI Exit */
8323 #define ETH_MACLCSR_TLPIST_Pos              (8U)
8324 #define ETH_MACLCSR_TLPIST_Msk              (0x1U << ETH_MACLCSR_TLPIST_Pos)                    /*!< 0x00000100 */
8325 #define ETH_MACLCSR_TLPIST                  ETH_MACLCSR_TLPIST_Msk                              /*!< Transmit LPI State */
8326 #define ETH_MACLCSR_RLPIST_Pos              (9U)
8327 #define ETH_MACLCSR_RLPIST_Msk              (0x1U << ETH_MACLCSR_RLPIST_Pos)                    /*!< 0x00000200 */
8328 #define ETH_MACLCSR_RLPIST                  ETH_MACLCSR_RLPIST_Msk                              /*!< Receive LPI State */
8329 #define ETH_MACLCSR_LPIEN_Pos               (16U)
8330 #define ETH_MACLCSR_LPIEN_Msk               (0x1U << ETH_MACLCSR_LPIEN_Pos)                     /*!< 0x00010000 */
8331 #define ETH_MACLCSR_LPIEN                   ETH_MACLCSR_LPIEN_Msk                               /*!< LPI Enable */
8332 #define ETH_MACLCSR_PLS_Pos                 (17U)
8333 #define ETH_MACLCSR_PLS_Msk                 (0x1U << ETH_MACLCSR_PLS_Pos)                       /*!< 0x00020000 */
8334 #define ETH_MACLCSR_PLS                     ETH_MACLCSR_PLS_Msk                                 /*!< PHY Link Status */
8335 #define ETH_MACLCSR_PLSEN_Pos               (18U)
8336 #define ETH_MACLCSR_PLSEN_Msk               (0x1U << ETH_MACLCSR_PLSEN_Pos)                     /*!< 0x00040000 */
8337 #define ETH_MACLCSR_PLSEN                   ETH_MACLCSR_PLSEN_Msk                               /*!< PHY Link Status Enable */
8338 #define ETH_MACLCSR_LPITXA_Pos              (19U)
8339 #define ETH_MACLCSR_LPITXA_Msk              (0x1U << ETH_MACLCSR_LPITXA_Pos)                    /*!< 0x00080000 */
8340 #define ETH_MACLCSR_LPITXA                  ETH_MACLCSR_LPITXA_Msk                              /*!< LPI Tx Automate */
8341 #define ETH_MACLCSR_LPITE_Pos               (20U)
8342 #define ETH_MACLCSR_LPITE_Msk               (0x1U << ETH_MACLCSR_LPITE_Pos)                     /*!< 0x00100000 */
8343 #define ETH_MACLCSR_LPITE                   ETH_MACLCSR_LPITE_Msk                               /*!< LPI Timer Enable */
8344 
8345 /**************  Bit definition for ETH_MACLTCR register  **************/
8346 #define ETH_MACLTCR_TWT_Pos                 (0U)
8347 #define ETH_MACLTCR_TWT_Msk                 (0xFFFFU << ETH_MACLTCR_TWT_Pos)                    /*!< 0x0000FFFF */
8348 #define ETH_MACLTCR_TWT                     ETH_MACLTCR_TWT_Msk                                 /*!< LPI TW Timer */
8349 #define ETH_MACLTCR_TWT_0                   (0x1U << ETH_MACLTCR_TWT_Pos)                       /*!< 0x00000001 */
8350 #define ETH_MACLTCR_TWT_1                   (0x2U << ETH_MACLTCR_TWT_Pos)                       /*!< 0x00000002 */
8351 #define ETH_MACLTCR_TWT_2                   (0x4U << ETH_MACLTCR_TWT_Pos)                       /*!< 0x00000004 */
8352 #define ETH_MACLTCR_TWT_3                   (0x8U << ETH_MACLTCR_TWT_Pos)                       /*!< 0x00000008 */
8353 #define ETH_MACLTCR_TWT_4                   (0x10U << ETH_MACLTCR_TWT_Pos)                      /*!< 0x00000010 */
8354 #define ETH_MACLTCR_TWT_5                   (0x20U << ETH_MACLTCR_TWT_Pos)                      /*!< 0x00000020 */
8355 #define ETH_MACLTCR_TWT_6                   (0x40U << ETH_MACLTCR_TWT_Pos)                      /*!< 0x00000040 */
8356 #define ETH_MACLTCR_TWT_7                   (0x80U << ETH_MACLTCR_TWT_Pos)                      /*!< 0x00000080 */
8357 #define ETH_MACLTCR_TWT_8                   (0x100U << ETH_MACLTCR_TWT_Pos)                     /*!< 0x00000100 */
8358 #define ETH_MACLTCR_TWT_9                   (0x200U << ETH_MACLTCR_TWT_Pos)                     /*!< 0x00000200 */
8359 #define ETH_MACLTCR_TWT_10                  (0x400U << ETH_MACLTCR_TWT_Pos)                     /*!< 0x00000400 */
8360 #define ETH_MACLTCR_TWT_11                  (0x800U << ETH_MACLTCR_TWT_Pos)                     /*!< 0x00000800 */
8361 #define ETH_MACLTCR_TWT_12                  (0x1000U << ETH_MACLTCR_TWT_Pos)                    /*!< 0x00001000 */
8362 #define ETH_MACLTCR_TWT_13                  (0x2000U << ETH_MACLTCR_TWT_Pos)                    /*!< 0x00002000 */
8363 #define ETH_MACLTCR_TWT_14                  (0x4000U << ETH_MACLTCR_TWT_Pos)                    /*!< 0x00004000 */
8364 #define ETH_MACLTCR_TWT_15                  (0x8000U << ETH_MACLTCR_TWT_Pos)                    /*!< 0x00008000 */
8365 #define ETH_MACLTCR_LST_Pos                 (16U)
8366 #define ETH_MACLTCR_LST_Msk                 (0x3FFU << ETH_MACLTCR_LST_Pos)                     /*!< 0x03FF0000 */
8367 #define ETH_MACLTCR_LST                     ETH_MACLTCR_LST_Msk                                 /*!< LPI LS Timer */
8368 #define ETH_MACLTCR_LST_0                   (0x1U << ETH_MACLTCR_LST_Pos)                   /*!< 0x00010000 */
8369 #define ETH_MACLTCR_LST_1                   (0x2U << ETH_MACLTCR_LST_Pos)                   /*!< 0x00020000 */
8370 #define ETH_MACLTCR_LST_2                   (0x4U << ETH_MACLTCR_LST_Pos)                   /*!< 0x00040000 */
8371 #define ETH_MACLTCR_LST_3                   (0x8U << ETH_MACLTCR_LST_Pos)                   /*!< 0x00080000 */
8372 #define ETH_MACLTCR_LST_4                   (0x10U << ETH_MACLTCR_LST_Pos)                  /*!< 0x00100000 */
8373 #define ETH_MACLTCR_LST_5                   (0x20U << ETH_MACLTCR_LST_Pos)                  /*!< 0x00200000 */
8374 #define ETH_MACLTCR_LST_6                   (0x40U << ETH_MACLTCR_LST_Pos)                  /*!< 0x00400000 */
8375 #define ETH_MACLTCR_LST_7                   (0x80U << ETH_MACLTCR_LST_Pos)                  /*!< 0x00800000 */
8376 #define ETH_MACLTCR_LST_8                   (0x100U << ETH_MACLTCR_LST_Pos)                 /*!< 0x01000000 */
8377 #define ETH_MACLTCR_LST_9                   (0x200U << ETH_MACLTCR_LST_Pos)                 /*!< 0x02000000 */
8378 
8379 /**************  Bit definition for ETH_MACLETR register  **************/
8380 #define ETH_MACLETR_LPIET_Pos               (3U)
8381 #define ETH_MACLETR_LPIET_Msk               (0x1FFFFU << ETH_MACLETR_LPIET_Pos)                 /*!< 0x000FFFF8 */
8382 #define ETH_MACLETR_LPIET                   ETH_MACLETR_LPIET_Msk                               /*!< LPI Entry Timer */
8383 #define ETH_MACLETR_LPIET_0                 (0x1U << ETH_MACLETR_LPIET_Pos)                     /*!< 0x00000008 */
8384 #define ETH_MACLETR_LPIET_1                 (0x2U << ETH_MACLETR_LPIET_Pos)                    /*!< 0x00000010 */
8385 #define ETH_MACLETR_LPIET_2                 (0x4U << ETH_MACLETR_LPIET_Pos)                    /*!< 0x00000020 */
8386 #define ETH_MACLETR_LPIET_3                 (0x8U << ETH_MACLETR_LPIET_Pos)                    /*!< 0x00000040 */
8387 #define ETH_MACLETR_LPIET_4                 (0x10U << ETH_MACLETR_LPIET_Pos)                    /*!< 0x00000080 */
8388 #define ETH_MACLETR_LPIET_5                 (0x20U << ETH_MACLETR_LPIET_Pos)                   /*!< 0x00000100 */
8389 #define ETH_MACLETR_LPIET_6                 (0x40U << ETH_MACLETR_LPIET_Pos)                   /*!< 0x00000200 */
8390 #define ETH_MACLETR_LPIET_7                 (0x80U << ETH_MACLETR_LPIET_Pos)                   /*!< 0x00000400 */
8391 #define ETH_MACLETR_LPIET_8                 (0x100U << ETH_MACLETR_LPIET_Pos)                   /*!< 0x00000800 */
8392 #define ETH_MACLETR_LPIET_9                 (0x200U << ETH_MACLETR_LPIET_Pos)                  /*!< 0x00001000 */
8393 #define ETH_MACLETR_LPIET_10                (0x400U << ETH_MACLETR_LPIET_Pos)                  /*!< 0x00002000 */
8394 #define ETH_MACLETR_LPIET_11                (0x800U << ETH_MACLETR_LPIET_Pos)                  /*!< 0x00004000 */
8395 #define ETH_MACLETR_LPIET_12                (0x1000U << ETH_MACLETR_LPIET_Pos)                  /*!< 0x00008000 */
8396 #define ETH_MACLETR_LPIET_13                (0x2000U << ETH_MACLETR_LPIET_Pos)                 /*!< 0x00010000 */
8397 #define ETH_MACLETR_LPIET_14                (0x4000U << ETH_MACLETR_LPIET_Pos)                 /*!< 0x00020000 */
8398 #define ETH_MACLETR_LPIET_15                (0x8000U << ETH_MACLETR_LPIET_Pos)                 /*!< 0x00040000 */
8399 #define ETH_MACLETR_LPIET_16                (0x10000U << ETH_MACLETR_LPIET_Pos)                 /*!< 0x00080000 */
8400 
8401 /*************  Bit definition for ETH_MAC1USTCR register  *************/
8402 #define ETH_MAC1USTCR_TIC_1US_CNTR_Pos      (0U)
8403 #define ETH_MAC1USTCR_TIC_1US_CNTR_Msk      (0xFFFU << ETH_MAC1USTCR_TIC_1US_CNTR_Pos)          /*!< 0x00000FFF */
8404 #define ETH_MAC1USTCR_TIC_1US_CNTR          ETH_MAC1USTCR_TIC_1US_CNTR_Msk                      /*!< 1 µs tick Counter */
8405 #define ETH_MAC1USTCR_TIC_1US_CNTR_0        (0x1U << ETH_MAC1USTCR_TIC_1US_CNTR_Pos)            /*!< 0x00000001 */
8406 #define ETH_MAC1USTCR_TIC_1US_CNTR_1        (0x2U << ETH_MAC1USTCR_TIC_1US_CNTR_Pos)            /*!< 0x00000002 */
8407 #define ETH_MAC1USTCR_TIC_1US_CNTR_2        (0x4U << ETH_MAC1USTCR_TIC_1US_CNTR_Pos)            /*!< 0x00000004 */
8408 #define ETH_MAC1USTCR_TIC_1US_CNTR_3        (0x8U << ETH_MAC1USTCR_TIC_1US_CNTR_Pos)            /*!< 0x00000008 */
8409 #define ETH_MAC1USTCR_TIC_1US_CNTR_4        (0x10U << ETH_MAC1USTCR_TIC_1US_CNTR_Pos)           /*!< 0x00000010 */
8410 #define ETH_MAC1USTCR_TIC_1US_CNTR_5        (0x20U << ETH_MAC1USTCR_TIC_1US_CNTR_Pos)           /*!< 0x00000020 */
8411 #define ETH_MAC1USTCR_TIC_1US_CNTR_6        (0x40U << ETH_MAC1USTCR_TIC_1US_CNTR_Pos)           /*!< 0x00000040 */
8412 #define ETH_MAC1USTCR_TIC_1US_CNTR_7        (0x80U << ETH_MAC1USTCR_TIC_1US_CNTR_Pos)           /*!< 0x00000080 */
8413 #define ETH_MAC1USTCR_TIC_1US_CNTR_8        (0x100U << ETH_MAC1USTCR_TIC_1US_CNTR_Pos)          /*!< 0x00000100 */
8414 #define ETH_MAC1USTCR_TIC_1US_CNTR_9        (0x200U << ETH_MAC1USTCR_TIC_1US_CNTR_Pos)          /*!< 0x00000200 */
8415 #define ETH_MAC1USTCR_TIC_1US_CNTR_10       (0x400U << ETH_MAC1USTCR_TIC_1US_CNTR_Pos)          /*!< 0x00000400 */
8416 #define ETH_MAC1USTCR_TIC_1US_CNTR_11       (0x800U << ETH_MAC1USTCR_TIC_1US_CNTR_Pos)          /*!< 0x00000800 */
8417 
8418 /*************  Bit definition for ETH_MACPHYCSR register  *************/
8419 #define ETH_MACPHYCSR_TC_Pos                (0U)
8420 #define ETH_MACPHYCSR_TC_Msk                (0x1U << ETH_MACPHYCSR_TC_Pos)                      /*!< 0x00000001 */
8421 #define ETH_MACPHYCSR_TC                    ETH_MACPHYCSR_TC_Msk                                /*!< Transmit Configuration in RGMII, SGMII, or SMII */
8422 #define ETH_MACPHYCSR_LUD_Pos               (1U)
8423 #define ETH_MACPHYCSR_LUD_Msk               (0x1U << ETH_MACPHYCSR_LUD_Pos)                     /*!< 0x00000002 */
8424 #define ETH_MACPHYCSR_LUD                   ETH_MACPHYCSR_LUD_Msk                               /*!< Link Up or Down */
8425 #define ETH_MACPHYCSR_LNKMOD_Pos            (16U)
8426 #define ETH_MACPHYCSR_LNKMOD_Msk            (0x1U << ETH_MACPHYCSR_LNKMOD_Pos)                  /*!< 0x00010000 */
8427 #define ETH_MACPHYCSR_LNKMOD                ETH_MACPHYCSR_LNKMOD_Msk                            /*!< Link Mode */
8428 #define ETH_MACPHYCSR_LNKSPEED_Pos          (17U)
8429 #define ETH_MACPHYCSR_LNKSPEED_Msk          (0x3U << ETH_MACPHYCSR_LNKSPEED_Pos)                /*!< 0x00060000 */
8430 #define ETH_MACPHYCSR_LNKSPEED              ETH_MACPHYCSR_LNKSPEED_Msk                          /*!< Link Speed */
8431 #define ETH_MACPHYCSR_LNKSPEED_0            (0x1U << ETH_MACPHYCSR_LNKSPEED_Pos)            /*!< 0x00020000 */
8432 #define ETH_MACPHYCSR_LNKSPEED_1            (0x2U << ETH_MACPHYCSR_LNKSPEED_Pos)            /*!< 0x00040000 */
8433 #define ETH_MACPHYCSR_LNKSTS_Pos            (19U)
8434 #define ETH_MACPHYCSR_LNKSTS_Msk            (0x1U << ETH_MACPHYCSR_LNKSTS_Pos)                  /*!< 0x00080000 */
8435 #define ETH_MACPHYCSR_LNKSTS                ETH_MACPHYCSR_LNKSTS_Msk                            /*!< Link Status */
8436 #define ETH_MACPHYCSR_JABTO_Pos             (20U)
8437 #define ETH_MACPHYCSR_JABTO_Msk             (0x1U << ETH_MACPHYCSR_JABTO_Pos)                   /*!< 0x00100000 */
8438 #define ETH_MACPHYCSR_JABTO                 ETH_MACPHYCSR_JABTO_Msk                             /*!< Jabber Timeout */
8439 #define ETH_MACPHYCSR_FALSCARDET_Pos        (21U)
8440 #define ETH_MACPHYCSR_FALSCARDET_Msk        (0x1U << ETH_MACPHYCSR_FALSCARDET_Pos)              /*!< 0x00200000 */
8441 #define ETH_MACPHYCSR_FALSCARDET            ETH_MACPHYCSR_FALSCARDET_Msk                        /*!< False Carrier Detected */
8442 
8443 /***************  Bit definition for ETH_MACVR register  ***************/
8444 #define ETH_MACVR_SNPSVER_Pos               (0U)
8445 #define ETH_MACVR_SNPSVER_Msk               (0xFFU << ETH_MACVR_SNPSVER_Pos)                    /*!< 0x000000FF */
8446 #define ETH_MACVR_SNPSVER                   ETH_MACVR_SNPSVER_Msk                               /*!< IP version */
8447 #define ETH_MACVR_SNPSVER_0                 (0x1U << ETH_MACVR_SNPSVER_Pos)                     /*!< 0x00000001 */
8448 #define ETH_MACVR_SNPSVER_1                 (0x2U << ETH_MACVR_SNPSVER_Pos)                     /*!< 0x00000002 */
8449 #define ETH_MACVR_SNPSVER_2                 (0x4U << ETH_MACVR_SNPSVER_Pos)                     /*!< 0x00000004 */
8450 #define ETH_MACVR_SNPSVER_3                 (0x8U << ETH_MACVR_SNPSVER_Pos)                     /*!< 0x00000008 */
8451 #define ETH_MACVR_SNPSVER_4                 (0x10U << ETH_MACVR_SNPSVER_Pos)                    /*!< 0x00000010 */
8452 #define ETH_MACVR_SNPSVER_5                 (0x20U << ETH_MACVR_SNPSVER_Pos)                    /*!< 0x00000020 */
8453 #define ETH_MACVR_SNPSVER_6                 (0x40U << ETH_MACVR_SNPSVER_Pos)                    /*!< 0x00000040 */
8454 #define ETH_MACVR_SNPSVER_7                 (0x80U << ETH_MACVR_SNPSVER_Pos)                    /*!< 0x00000080 */
8455 #define ETH_MACVR_USERVER_Pos               (8U)
8456 #define ETH_MACVR_USERVER_Msk               (0xFFU << ETH_MACVR_USERVER_Pos)                    /*!< 0x0000FF00 */
8457 #define ETH_MACVR_USERVER                   ETH_MACVR_USERVER_Msk                               /*!< ST-defined version */
8458 #define ETH_MACVR_USERVER_0                 (0x1U << ETH_MACVR_USERVER_Pos)                   /*!< 0x00000100 */
8459 #define ETH_MACVR_USERVER_1                 (0x2U << ETH_MACVR_USERVER_Pos)                   /*!< 0x00000200 */
8460 #define ETH_MACVR_USERVER_2                 (0x4U << ETH_MACVR_USERVER_Pos)                   /*!< 0x00000400 */
8461 #define ETH_MACVR_USERVER_3                 (0x8U << ETH_MACVR_USERVER_Pos)                   /*!< 0x00000800 */
8462 #define ETH_MACVR_USERVER_4                 (0x10U << ETH_MACVR_USERVER_Pos)                  /*!< 0x00001000 */
8463 #define ETH_MACVR_USERVER_5                 (0x20U << ETH_MACVR_USERVER_Pos)                  /*!< 0x00002000 */
8464 #define ETH_MACVR_USERVER_6                 (0x40U << ETH_MACVR_USERVER_Pos)                  /*!< 0x00004000 */
8465 #define ETH_MACVR_USERVER_7                 (0x80U << ETH_MACVR_USERVER_Pos)                  /*!< 0x00008000 */
8466 
8467 /***************  Bit definition for ETH_MACDR register  ***************/
8468 #define ETH_MACDR_RPESTS_Pos                (0U)
8469 #define ETH_MACDR_RPESTS_Msk                (0x1U << ETH_MACDR_RPESTS_Pos)                      /*!< 0x00000001 */
8470 #define ETH_MACDR_RPESTS                    ETH_MACDR_RPESTS_Msk                                /*!< MAC GMII or MII Receive Protocol Engine Status */
8471 #define ETH_MACDR_RFCFCSTS_Pos              (1U)
8472 #define ETH_MACDR_RFCFCSTS_Msk              (0x3U << ETH_MACDR_RFCFCSTS_Pos)                    /*!< 0x00000006 */
8473 #define ETH_MACDR_RFCFCSTS                  ETH_MACDR_RFCFCSTS_Msk                              /*!< MAC Receive Packet Controller FIFO Status */
8474 #define ETH_MACDR_RFCFCSTS_0                (0x1U << ETH_MACDR_RFCFCSTS_Pos)                    /*!< 0x00000002 */
8475 #define ETH_MACDR_RFCFCSTS_1                (0x2U << ETH_MACDR_RFCFCSTS_Pos)                    /*!< 0x00000004 */
8476 #define ETH_MACDR_TPESTS_Pos                (16U)
8477 #define ETH_MACDR_TPESTS_Msk                (0x1U << ETH_MACDR_TPESTS_Pos)                      /*!< 0x00010000 */
8478 #define ETH_MACDR_TPESTS                    ETH_MACDR_TPESTS_Msk                                /*!< MAC GMII or MII Transmit Protocol Engine Status */
8479 #define ETH_MACDR_TFCSTS_Pos                (17U)
8480 #define ETH_MACDR_TFCSTS_Msk                (0x3U << ETH_MACDR_TFCSTS_Pos)                      /*!< 0x00060000 */
8481 #define ETH_MACDR_TFCSTS                    ETH_MACDR_TFCSTS_Msk                                /*!< MAC Transmit Packet Controller Status */
8482 #define ETH_MACDR_TFCSTS_0                  (0x1U << ETH_MACDR_TFCSTS_Pos)                  /*!< 0x00020000 */
8483 #define ETH_MACDR_TFCSTS_1                  (0x2U << ETH_MACDR_TFCSTS_Pos)                  /*!< 0x00040000 */
8484 
8485 /*************  Bit definition for ETH_MACHWF1R register  **************/
8486 #define ETH_MACHWF1R_RXFIFOSIZE_Pos         (0U)
8487 #define ETH_MACHWF1R_RXFIFOSIZE_Msk         (0x1FU << ETH_MACHWF1R_RXFIFOSIZE_Pos)              /*!< 0x0000001F */
8488 #define ETH_MACHWF1R_RXFIFOSIZE             ETH_MACHWF1R_RXFIFOSIZE_Msk                         /*!< MTL Receive FIFO Size */
8489 #define ETH_MACHWF1R_RXFIFOSIZE_0           (0x1U << ETH_MACHWF1R_RXFIFOSIZE_Pos)               /*!< 0x00000001 */
8490 #define ETH_MACHWF1R_RXFIFOSIZE_1           (0x2U << ETH_MACHWF1R_RXFIFOSIZE_Pos)               /*!< 0x00000002 */
8491 #define ETH_MACHWF1R_RXFIFOSIZE_2           (0x4U << ETH_MACHWF1R_RXFIFOSIZE_Pos)               /*!< 0x00000004 */
8492 #define ETH_MACHWF1R_RXFIFOSIZE_3           (0x8U << ETH_MACHWF1R_RXFIFOSIZE_Pos)               /*!< 0x00000008 */
8493 #define ETH_MACHWF1R_RXFIFOSIZE_4           (0x10U << ETH_MACHWF1R_RXFIFOSIZE_Pos)              /*!< 0x00000010 */
8494 #define ETH_MACHWF1R_TXFIFOSIZE_Pos         (6U)
8495 #define ETH_MACHWF1R_TXFIFOSIZE_Msk         (0x1FU << ETH_MACHWF1R_TXFIFOSIZE_Pos)              /*!< 0x000007C0 */
8496 #define ETH_MACHWF1R_TXFIFOSIZE             ETH_MACHWF1R_TXFIFOSIZE_Msk                         /*!< MTL Transmit FIFO Size */
8497 #define ETH_MACHWF1R_TXFIFOSIZE_0           (0x1U << ETH_MACHWF1R_TXFIFOSIZE_Pos)              /*!< 0x00000040 */
8498 #define ETH_MACHWF1R_TXFIFOSIZE_1           (0x2U << ETH_MACHWF1R_TXFIFOSIZE_Pos)              /*!< 0x00000080 */
8499 #define ETH_MACHWF1R_TXFIFOSIZE_2           (0x4U << ETH_MACHWF1R_TXFIFOSIZE_Pos)             /*!< 0x00000100 */
8500 #define ETH_MACHWF1R_TXFIFOSIZE_3           (0x8U << ETH_MACHWF1R_TXFIFOSIZE_Pos)             /*!< 0x00000200 */
8501 #define ETH_MACHWF1R_TXFIFOSIZE_4           (0x10U << ETH_MACHWF1R_TXFIFOSIZE_Pos)             /*!< 0x00000400 */
8502 #define ETH_MACHWF1R_OSTEN_Pos              (11U)
8503 #define ETH_MACHWF1R_OSTEN_Msk              (0x1U << ETH_MACHWF1R_OSTEN_Pos)                    /*!< 0x00000800 */
8504 #define ETH_MACHWF1R_OSTEN                  ETH_MACHWF1R_OSTEN_Msk                              /*!< One-Step Timestamping Enable */
8505 #define ETH_MACHWF1R_PTOEN_Pos              (12U)
8506 #define ETH_MACHWF1R_PTOEN_Msk              (0x1U << ETH_MACHWF1R_PTOEN_Pos)                    /*!< 0x00001000 */
8507 #define ETH_MACHWF1R_PTOEN                  ETH_MACHWF1R_PTOEN_Msk                              /*!< PTP Offload Enable */
8508 #define ETH_MACHWF1R_ADVTHWORD_Pos          (13U)
8509 #define ETH_MACHWF1R_ADVTHWORD_Msk          (0x1U << ETH_MACHWF1R_ADVTHWORD_Pos)                /*!< 0x00002000 */
8510 #define ETH_MACHWF1R_ADVTHWORD              ETH_MACHWF1R_ADVTHWORD_Msk                          /*!< IEEE 1588 High Word Register Enable */
8511 #define ETH_MACHWF1R_ADDR64_Pos             (14U)
8512 #define ETH_MACHWF1R_ADDR64_Msk             (0x3U << ETH_MACHWF1R_ADDR64_Pos)                   /*!< 0x0000C000 */
8513 #define ETH_MACHWF1R_ADDR64                 ETH_MACHWF1R_ADDR64_Msk                             /*!< Address width */
8514 #define ETH_MACHWF1R_ADDR64_0               (0x1U << ETH_MACHWF1R_ADDR64_Pos)                /*!< 0x00004000 */
8515 #define ETH_MACHWF1R_ADDR64_1               (0x2U << ETH_MACHWF1R_ADDR64_Pos)                /*!< 0x00008000 */
8516 #define ETH_MACHWF1R_DCBEN_Pos              (16U)
8517 #define ETH_MACHWF1R_DCBEN_Msk              (0x1U << ETH_MACHWF1R_DCBEN_Pos)                    /*!< 0x00010000 */
8518 #define ETH_MACHWF1R_DCBEN                  ETH_MACHWF1R_DCBEN_Msk                              /*!< DCB Feature Enable */
8519 #define ETH_MACHWF1R_SPHEN_Pos              (17U)
8520 #define ETH_MACHWF1R_SPHEN_Msk              (0x1U << ETH_MACHWF1R_SPHEN_Pos)                    /*!< 0x00020000 */
8521 #define ETH_MACHWF1R_SPHEN                  ETH_MACHWF1R_SPHEN_Msk                              /*!< Split Header Feature Enable */
8522 #define ETH_MACHWF1R_TSOEN_Pos              (18U)
8523 #define ETH_MACHWF1R_TSOEN_Msk              (0x1U << ETH_MACHWF1R_TSOEN_Pos)                    /*!< 0x00040000 */
8524 #define ETH_MACHWF1R_TSOEN                  ETH_MACHWF1R_TSOEN_Msk                              /*!< TCP Segmentation Offload Enable */
8525 #define ETH_MACHWF1R_DBGMEMA_Pos            (19U)
8526 #define ETH_MACHWF1R_DBGMEMA_Msk            (0x1U << ETH_MACHWF1R_DBGMEMA_Pos)                  /*!< 0x00080000 */
8527 #define ETH_MACHWF1R_DBGMEMA                ETH_MACHWF1R_DBGMEMA_Msk                            /*!< DMA Debug Registers Enable */
8528 #define ETH_MACHWF1R_AVSEL_Pos              (20U)
8529 #define ETH_MACHWF1R_AVSEL_Msk              (0x1U << ETH_MACHWF1R_AVSEL_Pos)                    /*!< 0x00100000 */
8530 #define ETH_MACHWF1R_AVSEL                  ETH_MACHWF1R_AVSEL_Msk                              /*!< AV Feature Enable */
8531 #define ETH_MACHWF1R_HASHTBLSZ_Pos          (24U)
8532 #define ETH_MACHWF1R_HASHTBLSZ_Msk          (0x3U << ETH_MACHWF1R_HASHTBLSZ_Pos)                /*!< 0x03000000 */
8533 #define ETH_MACHWF1R_HASHTBLSZ              ETH_MACHWF1R_HASHTBLSZ_Msk                          /*!< Hash Table Size */
8534 #define ETH_MACHWF1R_HASHTBLSZ_0            (0x1U << ETH_MACHWF1R_HASHTBLSZ_Pos)          /*!< 0x01000000 */
8535 #define ETH_MACHWF1R_HASHTBLSZ_1            (0x2U << ETH_MACHWF1R_HASHTBLSZ_Pos)          /*!< 0x02000000 */
8536 #define ETH_MACHWF1R_L3L4FNUM_Pos           (27U)
8537 #define ETH_MACHWF1R_L3L4FNUM_Msk           (0xFU << ETH_MACHWF1R_L3L4FNUM_Pos)                 /*!< 0x78000000 */
8538 #define ETH_MACHWF1R_L3L4FNUM               ETH_MACHWF1R_L3L4FNUM_Msk                           /*!< Total number of L3 or L4 Filters */
8539 #define ETH_MACHWF1R_L3L4FNUM_0             (0x1U << ETH_MACHWF1R_L3L4FNUM_Pos)           /*!< 0x08000000 */
8540 #define ETH_MACHWF1R_L3L4FNUM_1             (0x2U << ETH_MACHWF1R_L3L4FNUM_Pos)          /*!< 0x10000000 */
8541 #define ETH_MACHWF1R_L3L4FNUM_2             (0x4U << ETH_MACHWF1R_L3L4FNUM_Pos)          /*!< 0x20000000 */
8542 #define ETH_MACHWF1R_L3L4FNUM_3             (0x8U << ETH_MACHWF1R_L3L4FNUM_Pos)          /*!< 0x40000000 */
8543 
8544 /*************  Bit definition for ETH_MACHWF2R register  **************/
8545 #define ETH_MACHWF2R_RXQCNT_Pos             (0U)
8546 #define ETH_MACHWF2R_RXQCNT_Msk             (0xFU << ETH_MACHWF2R_RXQCNT_Pos)                   /*!< 0x0000000F */
8547 #define ETH_MACHWF2R_RXQCNT                 ETH_MACHWF2R_RXQCNT_Msk                             /*!< Number of MTL Receive Queues */
8548 #define ETH_MACHWF2R_RXQCNT_0               (0x1U << ETH_MACHWF2R_RXQCNT_Pos)                   /*!< 0x00000001 */
8549 #define ETH_MACHWF2R_RXQCNT_1               (0x2U << ETH_MACHWF2R_RXQCNT_Pos)                   /*!< 0x00000002 */
8550 #define ETH_MACHWF2R_RXQCNT_2               (0x4U << ETH_MACHWF2R_RXQCNT_Pos)                   /*!< 0x00000004 */
8551 #define ETH_MACHWF2R_RXQCNT_3               (0x8U << ETH_MACHWF2R_RXQCNT_Pos)                   /*!< 0x00000008 */
8552 #define ETH_MACHWF2R_TXQCNT_Pos             (6U)
8553 #define ETH_MACHWF2R_TXQCNT_Msk             (0xFU << ETH_MACHWF2R_TXQCNT_Pos)                   /*!< 0x000003C0 */
8554 #define ETH_MACHWF2R_TXQCNT                 ETH_MACHWF2R_TXQCNT_Msk                             /*!< Number of MTL Transmit Queues */
8555 #define ETH_MACHWF2R_TXQCNT_0               (0x1U << ETH_MACHWF2R_TXQCNT_Pos)                  /*!< 0x00000040 */
8556 #define ETH_MACHWF2R_TXQCNT_1               (0x2U << ETH_MACHWF2R_TXQCNT_Pos)                  /*!< 0x00000080 */
8557 #define ETH_MACHWF2R_TXQCNT_2               (0x4U << ETH_MACHWF2R_TXQCNT_Pos)                 /*!< 0x00000100 */
8558 #define ETH_MACHWF2R_TXQCNT_3               (0x8U << ETH_MACHWF2R_TXQCNT_Pos)                 /*!< 0x00000200 */
8559 #define ETH_MACHWF2R_RXCHCNT_Pos            (12U)
8560 #define ETH_MACHWF2R_RXCHCNT_Msk            (0xFU << ETH_MACHWF2R_RXCHCNT_Pos)                  /*!< 0x0000F000 */
8561 #define ETH_MACHWF2R_RXCHCNT                ETH_MACHWF2R_RXCHCNT_Msk                            /*!< Number of DMA Receive Channels */
8562 #define ETH_MACHWF2R_RXCHCNT_0              (0x1U << ETH_MACHWF2R_RXCHCNT_Pos)               /*!< 0x00001000 */
8563 #define ETH_MACHWF2R_RXCHCNT_1              (0x2U << ETH_MACHWF2R_RXCHCNT_Pos)               /*!< 0x00002000 */
8564 #define ETH_MACHWF2R_RXCHCNT_2              (0x4U << ETH_MACHWF2R_RXCHCNT_Pos)               /*!< 0x00004000 */
8565 #define ETH_MACHWF2R_RXCHCNT_3              (0x8U << ETH_MACHWF2R_RXCHCNT_Pos)               /*!< 0x00008000 */
8566 #define ETH_MACHWF2R_TXCHCNT_Pos            (18U)
8567 #define ETH_MACHWF2R_TXCHCNT_Msk            (0xFU << ETH_MACHWF2R_TXCHCNT_Pos)                  /*!< 0x003C0000 */
8568 #define ETH_MACHWF2R_TXCHCNT                ETH_MACHWF2R_TXCHCNT_Msk                            /*!< Number of DMA Transmit Channels */
8569 #define ETH_MACHWF2R_TXCHCNT_0              (0x1U << ETH_MACHWF2R_TXCHCNT_Pos)              /*!< 0x00040000 */
8570 #define ETH_MACHWF2R_TXCHCNT_1              (0x2U << ETH_MACHWF2R_TXCHCNT_Pos)              /*!< 0x00080000 */
8571 #define ETH_MACHWF2R_TXCHCNT_2              (0x4U << ETH_MACHWF2R_TXCHCNT_Pos)             /*!< 0x00100000 */
8572 #define ETH_MACHWF2R_TXCHCNT_3              (0x8U << ETH_MACHWF2R_TXCHCNT_Pos)             /*!< 0x00200000 */
8573 #define ETH_MACHWF2R_PPSOUTNUM_Pos          (24U)
8574 #define ETH_MACHWF2R_PPSOUTNUM_Msk          (0x7U << ETH_MACHWF2R_PPSOUTNUM_Pos)                /*!< 0x07000000 */
8575 #define ETH_MACHWF2R_PPSOUTNUM              ETH_MACHWF2R_PPSOUTNUM_Msk                          /*!< Number of PPS Outputs */
8576 #define ETH_MACHWF2R_PPSOUTNUM_0            (0x1U << ETH_MACHWF2R_PPSOUTNUM_Pos)          /*!< 0x01000000 */
8577 #define ETH_MACHWF2R_PPSOUTNUM_1            (0x2U << ETH_MACHWF2R_PPSOUTNUM_Pos)          /*!< 0x02000000 */
8578 #define ETH_MACHWF2R_PPSOUTNUM_2            (0x4U << ETH_MACHWF2R_PPSOUTNUM_Pos)          /*!< 0x04000000 */
8579 #define ETH_MACHWF2R_AUXSNAPNUM_Pos         (28U)
8580 #define ETH_MACHWF2R_AUXSNAPNUM_Msk         (0x7U << ETH_MACHWF2R_AUXSNAPNUM_Pos)               /*!< 0x70000000 */
8581 #define ETH_MACHWF2R_AUXSNAPNUM             ETH_MACHWF2R_AUXSNAPNUM_Msk                         /*!< Number of Auxiliary Snapshot Inputs */
8582 #define ETH_MACHWF2R_AUXSNAPNUM_0           (0x1U << ETH_MACHWF2R_AUXSNAPNUM_Pos)        /*!< 0x10000000 */
8583 #define ETH_MACHWF2R_AUXSNAPNUM_1           (0x2U << ETH_MACHWF2R_AUXSNAPNUM_Pos)        /*!< 0x20000000 */
8584 #define ETH_MACHWF2R_AUXSNAPNUM_2           (0x4U << ETH_MACHWF2R_AUXSNAPNUM_Pos)        /*!< 0x40000000 */
8585 
8586 /*************  Bit definition for ETH_MACMDIOAR register  *************/
8587 #define ETH_MACMDIOAR_GB_Pos                (0U)
8588 #define ETH_MACMDIOAR_GB_Msk                (0x1U << ETH_MACMDIOAR_GB_Pos)                      /*!< 0x00000001 */
8589 #define ETH_MACMDIOAR_GB                    ETH_MACMDIOAR_GB_Msk                                /*!< GMII Busy */
8590 #define ETH_MACMDIOAR_C45E_Pos              (1U)
8591 #define ETH_MACMDIOAR_C45E_Msk              (0x1U << ETH_MACMDIOAR_C45E_Pos)                    /*!< 0x00000002 */
8592 #define ETH_MACMDIOAR_C45E                  ETH_MACMDIOAR_C45E_Msk                              /*!< Clause 45 PHY Enable */
8593 #define ETH_MACMDIOAR_GOC_Pos               (2U)
8594 #define ETH_MACMDIOAR_GOC_Msk               (0x3U << ETH_MACMDIOAR_GOC_Pos)                     /*!< 0x0000000C */
8595 #define ETH_MACMDIOAR_GOC                   ETH_MACMDIOAR_GOC_Msk                               /*!< GMII Operation Command */
8596 #define ETH_MACMDIOAR_GOC_0                 (0x1U << ETH_MACMDIOAR_GOC_Pos)                     /*!< 0x00000004 */
8597 #define ETH_MACMDIOAR_GOC_1                 (0x2U << ETH_MACMDIOAR_GOC_Pos)                     /*!< 0x00000008 */
8598 #define ETH_MACMDIOAR_SKAP_Pos              (4U)
8599 #define ETH_MACMDIOAR_SKAP_Msk              (0x1U << ETH_MACMDIOAR_SKAP_Pos)                    /*!< 0x00000010 */
8600 #define ETH_MACMDIOAR_SKAP                  ETH_MACMDIOAR_SKAP_Msk                              /*!< Skip Address Packet */
8601 #define ETH_MACMDIOAR_CR_Pos                (8U)
8602 #define ETH_MACMDIOAR_CR_Msk                (0xFU << ETH_MACMDIOAR_CR_Pos)                      /*!< 0x00000F00 */
8603 #define ETH_MACMDIOAR_CR                    ETH_MACMDIOAR_CR_Msk                                /*!< CSR Clock Range */
8604 #define ETH_MACMDIOAR_CR_0                  (0x1U << ETH_MACMDIOAR_CR_Pos)                    /*!< 0x00000100 */
8605 #define ETH_MACMDIOAR_CR_1                  (0x2U << ETH_MACMDIOAR_CR_Pos)                    /*!< 0x00000200 */
8606 #define ETH_MACMDIOAR_CR_2                  (0x4U << ETH_MACMDIOAR_CR_Pos)                    /*!< 0x00000400 */
8607 #define ETH_MACMDIOAR_CR_3                  (0x8U << ETH_MACMDIOAR_CR_Pos)                    /*!< 0x00000800 */
8608 #define ETH_MACMDIOAR_NTC_Pos               (12U)
8609 #define ETH_MACMDIOAR_NTC_Msk               (0x7U << ETH_MACMDIOAR_NTC_Pos)                     /*!< 0x00007000 */
8610 #define ETH_MACMDIOAR_NTC                   ETH_MACMDIOAR_NTC_Msk                               /*!< Number of Training Clocks */
8611 #define ETH_MACMDIOAR_NTC_0                 (0x1U << ETH_MACMDIOAR_NTC_Pos)                  /*!< 0x00001000 */
8612 #define ETH_MACMDIOAR_NTC_1                 (0x2U << ETH_MACMDIOAR_NTC_Pos)                  /*!< 0x00002000 */
8613 #define ETH_MACMDIOAR_NTC_2                 (0x4U << ETH_MACMDIOAR_NTC_Pos)                  /*!< 0x00004000 */
8614 #define ETH_MACMDIOAR_RDA_Pos               (16U)
8615 #define ETH_MACMDIOAR_RDA_Msk               (0x1FU << ETH_MACMDIOAR_RDA_Pos)                    /*!< 0x001F0000 */
8616 #define ETH_MACMDIOAR_RDA                   ETH_MACMDIOAR_RDA_Msk                               /*!< Register/Device Address */
8617 #define ETH_MACMDIOAR_RDA_0                 (0x1U << ETH_MACMDIOAR_RDA_Pos)                 /*!< 0x00010000 */
8618 #define ETH_MACMDIOAR_RDA_1                 (0x2U << ETH_MACMDIOAR_RDA_Pos)                 /*!< 0x00020000 */
8619 #define ETH_MACMDIOAR_RDA_2                 (0x4U << ETH_MACMDIOAR_RDA_Pos)                 /*!< 0x00040000 */
8620 #define ETH_MACMDIOAR_RDA_3                 (0x8U << ETH_MACMDIOAR_RDA_Pos)                 /*!< 0x00080000 */
8621 #define ETH_MACMDIOAR_RDA_4                 (0x10U << ETH_MACMDIOAR_RDA_Pos)                /*!< 0x00100000 */
8622 #define ETH_MACMDIOAR_PA_Pos                (21U)
8623 #define ETH_MACMDIOAR_PA_Msk                (0x1FU << ETH_MACMDIOAR_PA_Pos)                     /*!< 0x03E00000 */
8624 #define ETH_MACMDIOAR_PA                    ETH_MACMDIOAR_PA_Msk                                /*!< Physical Layer Address */
8625 #define ETH_MACMDIOAR_PA_0                  (0x1U << ETH_MACMDIOAR_PA_Pos)                 /*!< 0x00200000 */
8626 #define ETH_MACMDIOAR_PA_1                  (0x2U << ETH_MACMDIOAR_PA_Pos)                 /*!< 0x00400000 */
8627 #define ETH_MACMDIOAR_PA_2                  (0x4U << ETH_MACMDIOAR_PA_Pos)                 /*!< 0x00800000 */
8628 #define ETH_MACMDIOAR_PA_3                  (0x8U << ETH_MACMDIOAR_PA_Pos)                /*!< 0x01000000 */
8629 #define ETH_MACMDIOAR_PA_4                  (0x10U << ETH_MACMDIOAR_PA_Pos)                /*!< 0x02000000 */
8630 #define ETH_MACMDIOAR_BTB_Pos               (26U)
8631 #define ETH_MACMDIOAR_BTB_Msk               (0x1U << ETH_MACMDIOAR_BTB_Pos)                     /*!< 0x04000000 */
8632 #define ETH_MACMDIOAR_BTB                   ETH_MACMDIOAR_BTB_Msk                               /*!< Back to Back transactions */
8633 #define ETH_MACMDIOAR_PSE_Pos               (27U)
8634 #define ETH_MACMDIOAR_PSE_Msk               (0x1U << ETH_MACMDIOAR_PSE_Pos)                     /*!< 0x08000000 */
8635 #define ETH_MACMDIOAR_PSE                   ETH_MACMDIOAR_PSE_Msk                               /*!< Preamble Suppression Enable */
8636 
8637 /*************  Bit definition for ETH_MACMDIODR register  *************/
8638 #define ETH_MACMDIODR_GD_Pos                (0U)
8639 #define ETH_MACMDIODR_GD_Msk                (0xFFFFU << ETH_MACMDIODR_GD_Pos)                   /*!< 0x0000FFFF */
8640 #define ETH_MACMDIODR_GD                    ETH_MACMDIODR_GD_Msk                                /*!< GMII Data */
8641 #define ETH_MACMDIODR_GD_0                  (0x1U << ETH_MACMDIODR_GD_Pos)                      /*!< 0x00000001 */
8642 #define ETH_MACMDIODR_GD_1                  (0x2U << ETH_MACMDIODR_GD_Pos)                      /*!< 0x00000002 */
8643 #define ETH_MACMDIODR_GD_2                  (0x4U << ETH_MACMDIODR_GD_Pos)                      /*!< 0x00000004 */
8644 #define ETH_MACMDIODR_GD_3                  (0x8U << ETH_MACMDIODR_GD_Pos)                      /*!< 0x00000008 */
8645 #define ETH_MACMDIODR_GD_4                  (0x10U << ETH_MACMDIODR_GD_Pos)                     /*!< 0x00000010 */
8646 #define ETH_MACMDIODR_GD_5                  (0x20U << ETH_MACMDIODR_GD_Pos)                     /*!< 0x00000020 */
8647 #define ETH_MACMDIODR_GD_6                  (0x40U << ETH_MACMDIODR_GD_Pos)                     /*!< 0x00000040 */
8648 #define ETH_MACMDIODR_GD_7                  (0x80U << ETH_MACMDIODR_GD_Pos)                     /*!< 0x00000080 */
8649 #define ETH_MACMDIODR_GD_8                  (0x100U << ETH_MACMDIODR_GD_Pos)                    /*!< 0x00000100 */
8650 #define ETH_MACMDIODR_GD_9                  (0x200U << ETH_MACMDIODR_GD_Pos)                    /*!< 0x00000200 */
8651 #define ETH_MACMDIODR_GD_10                 (0x400U << ETH_MACMDIODR_GD_Pos)                    /*!< 0x00000400 */
8652 #define ETH_MACMDIODR_GD_11                 (0x800U << ETH_MACMDIODR_GD_Pos)                    /*!< 0x00000800 */
8653 #define ETH_MACMDIODR_GD_12                 (0x1000U << ETH_MACMDIODR_GD_Pos)                   /*!< 0x00001000 */
8654 #define ETH_MACMDIODR_GD_13                 (0x2000U << ETH_MACMDIODR_GD_Pos)                   /*!< 0x00002000 */
8655 #define ETH_MACMDIODR_GD_14                 (0x4000U << ETH_MACMDIODR_GD_Pos)                   /*!< 0x00004000 */
8656 #define ETH_MACMDIODR_GD_15                 (0x8000U << ETH_MACMDIODR_GD_Pos)                   /*!< 0x00008000 */
8657 #define ETH_MACMDIODR_RA_Pos                (16U)
8658 #define ETH_MACMDIODR_RA_Msk                (0xFFFFU << ETH_MACMDIODR_RA_Pos)                   /*!< 0xFFFF0000 */
8659 #define ETH_MACMDIODR_RA                    ETH_MACMDIODR_RA_Msk                                /*!< Register Address */
8660 #define ETH_MACMDIODR_RA_0                  (0x1U << ETH_MACMDIODR_RA_Pos)                  /*!< 0x00010000 */
8661 #define ETH_MACMDIODR_RA_1                  (0x2U << ETH_MACMDIODR_RA_Pos)                  /*!< 0x00020000 */
8662 #define ETH_MACMDIODR_RA_2                  (0x4U << ETH_MACMDIODR_RA_Pos)                  /*!< 0x00040000 */
8663 #define ETH_MACMDIODR_RA_3                  (0x8U << ETH_MACMDIODR_RA_Pos)                  /*!< 0x00080000 */
8664 #define ETH_MACMDIODR_RA_4                  (0x10U << ETH_MACMDIODR_RA_Pos)                 /*!< 0x00100000 */
8665 #define ETH_MACMDIODR_RA_5                  (0x20U << ETH_MACMDIODR_RA_Pos)                 /*!< 0x00200000 */
8666 #define ETH_MACMDIODR_RA_6                  (0x40U << ETH_MACMDIODR_RA_Pos)                 /*!< 0x00400000 */
8667 #define ETH_MACMDIODR_RA_7                  (0x80U << ETH_MACMDIODR_RA_Pos)                 /*!< 0x00800000 */
8668 #define ETH_MACMDIODR_RA_8                  (0x100U << ETH_MACMDIODR_RA_Pos)                /*!< 0x01000000 */
8669 #define ETH_MACMDIODR_RA_9                  (0x200U << ETH_MACMDIODR_RA_Pos)                /*!< 0x02000000 */
8670 #define ETH_MACMDIODR_RA_10                 (0x400U << ETH_MACMDIODR_RA_Pos)                /*!< 0x04000000 */
8671 #define ETH_MACMDIODR_RA_11                 (0x800U << ETH_MACMDIODR_RA_Pos)                /*!< 0x08000000 */
8672 #define ETH_MACMDIODR_RA_12                 (0x1000U << ETH_MACMDIODR_RA_Pos)               /*!< 0x10000000 */
8673 #define ETH_MACMDIODR_RA_13                 (0x2000U << ETH_MACMDIODR_RA_Pos)               /*!< 0x20000000 */
8674 #define ETH_MACMDIODR_RA_14                 (0x4000U << ETH_MACMDIODR_RA_Pos)               /*!< 0x40000000 */
8675 #define ETH_MACMDIODR_RA_15                 (0x8000U << ETH_MACMDIODR_RA_Pos)               /*!< 0x80000000 */
8676 
8677 /**************  Bit definition for ETH_MACA0HR register  **************/
8678 #define ETH_MACA0HR_ADDRHI_Pos              (0U)
8679 #define ETH_MACA0HR_ADDRHI_Msk              (0xFFFFU << ETH_MACA0HR_ADDRHI_Pos)                 /*!< 0x0000FFFF */
8680 #define ETH_MACA0HR_ADDRHI                  ETH_MACA0HR_ADDRHI_Msk                              /*!< MAC Address0[47:32] */
8681 #define ETH_MACA0HR_ADDRHI_0                (0x1U << ETH_MACA0HR_ADDRHI_Pos)                    /*!< 0x00000001 */
8682 #define ETH_MACA0HR_ADDRHI_1                (0x2U << ETH_MACA0HR_ADDRHI_Pos)                    /*!< 0x00000002 */
8683 #define ETH_MACA0HR_ADDRHI_2                (0x4U << ETH_MACA0HR_ADDRHI_Pos)                    /*!< 0x00000004 */
8684 #define ETH_MACA0HR_ADDRHI_3                (0x8U << ETH_MACA0HR_ADDRHI_Pos)                    /*!< 0x00000008 */
8685 #define ETH_MACA0HR_ADDRHI_4                (0x10U << ETH_MACA0HR_ADDRHI_Pos)                   /*!< 0x00000010 */
8686 #define ETH_MACA0HR_ADDRHI_5                (0x20U << ETH_MACA0HR_ADDRHI_Pos)                   /*!< 0x00000020 */
8687 #define ETH_MACA0HR_ADDRHI_6                (0x40U << ETH_MACA0HR_ADDRHI_Pos)                   /*!< 0x00000040 */
8688 #define ETH_MACA0HR_ADDRHI_7                (0x80U << ETH_MACA0HR_ADDRHI_Pos)                   /*!< 0x00000080 */
8689 #define ETH_MACA0HR_ADDRHI_8                (0x100U << ETH_MACA0HR_ADDRHI_Pos)                  /*!< 0x00000100 */
8690 #define ETH_MACA0HR_ADDRHI_9                (0x200U << ETH_MACA0HR_ADDRHI_Pos)                  /*!< 0x00000200 */
8691 #define ETH_MACA0HR_ADDRHI_10               (0x400U << ETH_MACA0HR_ADDRHI_Pos)                  /*!< 0x00000400 */
8692 #define ETH_MACA0HR_ADDRHI_11               (0x800U << ETH_MACA0HR_ADDRHI_Pos)                  /*!< 0x00000800 */
8693 #define ETH_MACA0HR_ADDRHI_12               (0x1000U << ETH_MACA0HR_ADDRHI_Pos)                 /*!< 0x00001000 */
8694 #define ETH_MACA0HR_ADDRHI_13               (0x2000U << ETH_MACA0HR_ADDRHI_Pos)                 /*!< 0x00002000 */
8695 #define ETH_MACA0HR_ADDRHI_14               (0x4000U << ETH_MACA0HR_ADDRHI_Pos)                 /*!< 0x00004000 */
8696 #define ETH_MACA0HR_ADDRHI_15               (0x8000U << ETH_MACA0HR_ADDRHI_Pos)                 /*!< 0x00008000 */
8697 #define ETH_MACA0HR_AE_Pos                  (31U)
8698 #define ETH_MACA0HR_AE_Msk                  (0x1U << ETH_MACA0HR_AE_Pos)                        /*!< 0x80000000 */
8699 #define ETH_MACA0HR_AE                      ETH_MACA0HR_AE_Msk                                  /*!< Address Enable */
8700 
8701 /**************  Bit definition for ETH_MACA0LR register  **************/
8702 #define ETH_MACA0LR_ADDRLO_Pos              (0U)
8703 #define ETH_MACA0LR_ADDRLO_Msk              (0xFFFFFFFFU << ETH_MACA0LR_ADDRLO_Pos)             /*!< 0xFFFFFFFF */
8704 #define ETH_MACA0LR_ADDRLO                  ETH_MACA0LR_ADDRLO_Msk                              /*!< MAC Address x [31:0] (x = 0 to 3) */
8705 #define ETH_MACA0LR_ADDRLO_0                (0x1U << ETH_MACA0LR_ADDRLO_Pos)                    /*!< 0x00000001 */
8706 #define ETH_MACA0LR_ADDRLO_1                (0x2U << ETH_MACA0LR_ADDRLO_Pos)                    /*!< 0x00000002 */
8707 #define ETH_MACA0LR_ADDRLO_2                (0x4U << ETH_MACA0LR_ADDRLO_Pos)                    /*!< 0x00000004 */
8708 #define ETH_MACA0LR_ADDRLO_3                (0x8U << ETH_MACA0LR_ADDRLO_Pos)                    /*!< 0x00000008 */
8709 #define ETH_MACA0LR_ADDRLO_4                (0x10U << ETH_MACA0LR_ADDRLO_Pos)                   /*!< 0x00000010 */
8710 #define ETH_MACA0LR_ADDRLO_5                (0x20U << ETH_MACA0LR_ADDRLO_Pos)                   /*!< 0x00000020 */
8711 #define ETH_MACA0LR_ADDRLO_6                (0x40U << ETH_MACA0LR_ADDRLO_Pos)                   /*!< 0x00000040 */
8712 #define ETH_MACA0LR_ADDRLO_7                (0x80U << ETH_MACA0LR_ADDRLO_Pos)                   /*!< 0x00000080 */
8713 #define ETH_MACA0LR_ADDRLO_8                (0x100U << ETH_MACA0LR_ADDRLO_Pos)                  /*!< 0x00000100 */
8714 #define ETH_MACA0LR_ADDRLO_9                (0x200U << ETH_MACA0LR_ADDRLO_Pos)                  /*!< 0x00000200 */
8715 #define ETH_MACA0LR_ADDRLO_10               (0x400U << ETH_MACA0LR_ADDRLO_Pos)                  /*!< 0x00000400 */
8716 #define ETH_MACA0LR_ADDRLO_11               (0x800U << ETH_MACA0LR_ADDRLO_Pos)                  /*!< 0x00000800 */
8717 #define ETH_MACA0LR_ADDRLO_12               (0x1000U << ETH_MACA0LR_ADDRLO_Pos)                 /*!< 0x00001000 */
8718 #define ETH_MACA0LR_ADDRLO_13               (0x2000U << ETH_MACA0LR_ADDRLO_Pos)                 /*!< 0x00002000 */
8719 #define ETH_MACA0LR_ADDRLO_14               (0x4000U << ETH_MACA0LR_ADDRLO_Pos)                 /*!< 0x00004000 */
8720 #define ETH_MACA0LR_ADDRLO_15               (0x8000U << ETH_MACA0LR_ADDRLO_Pos)                 /*!< 0x00008000 */
8721 #define ETH_MACA0LR_ADDRLO_16               (0x10000U << ETH_MACA0LR_ADDRLO_Pos)                /*!< 0x00010000 */
8722 #define ETH_MACA0LR_ADDRLO_17               (0x20000U << ETH_MACA0LR_ADDRLO_Pos)                /*!< 0x00020000 */
8723 #define ETH_MACA0LR_ADDRLO_18               (0x40000U << ETH_MACA0LR_ADDRLO_Pos)                /*!< 0x00040000 */
8724 #define ETH_MACA0LR_ADDRLO_19               (0x80000U << ETH_MACA0LR_ADDRLO_Pos)                /*!< 0x00080000 */
8725 #define ETH_MACA0LR_ADDRLO_20               (0x100000U << ETH_MACA0LR_ADDRLO_Pos)               /*!< 0x00100000 */
8726 #define ETH_MACA0LR_ADDRLO_21               (0x200000U << ETH_MACA0LR_ADDRLO_Pos)               /*!< 0x00200000 */
8727 #define ETH_MACA0LR_ADDRLO_22               (0x400000U << ETH_MACA0LR_ADDRLO_Pos)               /*!< 0x00400000 */
8728 #define ETH_MACA0LR_ADDRLO_23               (0x800000U << ETH_MACA0LR_ADDRLO_Pos)               /*!< 0x00800000 */
8729 #define ETH_MACA0LR_ADDRLO_24               (0x1000000U << ETH_MACA0LR_ADDRLO_Pos)              /*!< 0x01000000 */
8730 #define ETH_MACA0LR_ADDRLO_25               (0x2000000U << ETH_MACA0LR_ADDRLO_Pos)              /*!< 0x02000000 */
8731 #define ETH_MACA0LR_ADDRLO_26               (0x4000000U << ETH_MACA0LR_ADDRLO_Pos)              /*!< 0x04000000 */
8732 #define ETH_MACA0LR_ADDRLO_27               (0x8000000U << ETH_MACA0LR_ADDRLO_Pos)              /*!< 0x08000000 */
8733 #define ETH_MACA0LR_ADDRLO_28               (0x10000000U << ETH_MACA0LR_ADDRLO_Pos)             /*!< 0x10000000 */
8734 #define ETH_MACA0LR_ADDRLO_29               (0x20000000U << ETH_MACA0LR_ADDRLO_Pos)             /*!< 0x20000000 */
8735 #define ETH_MACA0LR_ADDRLO_30               (0x40000000U << ETH_MACA0LR_ADDRLO_Pos)             /*!< 0x40000000 */
8736 #define ETH_MACA0LR_ADDRLO_31               (0x80000000U << ETH_MACA0LR_ADDRLO_Pos)             /*!< 0x80000000 */
8737 
8738 /**************  Bit definition for ETH_MACA1HR register  **************/
8739 #define ETH_MACA1HR_ADDRHI_Pos              (0U)
8740 #define ETH_MACA1HR_ADDRHI_Msk              (0xFFFFU << ETH_MACA1HR_ADDRHI_Pos)                 /*!< 0x0000FFFF */
8741 #define ETH_MACA1HR_ADDRHI                  ETH_MACA1HR_ADDRHI_Msk                              /*!< MAC Address1 [47:32] */
8742 #define ETH_MACA1HR_ADDRHI_0                (0x1U << ETH_MACA1HR_ADDRHI_Pos)                    /*!< 0x00000001 */
8743 #define ETH_MACA1HR_ADDRHI_1                (0x2U << ETH_MACA1HR_ADDRHI_Pos)                    /*!< 0x00000002 */
8744 #define ETH_MACA1HR_ADDRHI_2                (0x4U << ETH_MACA1HR_ADDRHI_Pos)                    /*!< 0x00000004 */
8745 #define ETH_MACA1HR_ADDRHI_3                (0x8U << ETH_MACA1HR_ADDRHI_Pos)                    /*!< 0x00000008 */
8746 #define ETH_MACA1HR_ADDRHI_4                (0x10U << ETH_MACA1HR_ADDRHI_Pos)                   /*!< 0x00000010 */
8747 #define ETH_MACA1HR_ADDRHI_5                (0x20U << ETH_MACA1HR_ADDRHI_Pos)                   /*!< 0x00000020 */
8748 #define ETH_MACA1HR_ADDRHI_6                (0x40U << ETH_MACA1HR_ADDRHI_Pos)                   /*!< 0x00000040 */
8749 #define ETH_MACA1HR_ADDRHI_7                (0x80U << ETH_MACA1HR_ADDRHI_Pos)                   /*!< 0x00000080 */
8750 #define ETH_MACA1HR_ADDRHI_8                (0x100U << ETH_MACA1HR_ADDRHI_Pos)                  /*!< 0x00000100 */
8751 #define ETH_MACA1HR_ADDRHI_9                (0x200U << ETH_MACA1HR_ADDRHI_Pos)                  /*!< 0x00000200 */
8752 #define ETH_MACA1HR_ADDRHI_10               (0x400U << ETH_MACA1HR_ADDRHI_Pos)                  /*!< 0x00000400 */
8753 #define ETH_MACA1HR_ADDRHI_11               (0x800U << ETH_MACA1HR_ADDRHI_Pos)                  /*!< 0x00000800 */
8754 #define ETH_MACA1HR_ADDRHI_12               (0x1000U << ETH_MACA1HR_ADDRHI_Pos)                 /*!< 0x00001000 */
8755 #define ETH_MACA1HR_ADDRHI_13               (0x2000U << ETH_MACA1HR_ADDRHI_Pos)                 /*!< 0x00002000 */
8756 #define ETH_MACA1HR_ADDRHI_14               (0x4000U << ETH_MACA1HR_ADDRHI_Pos)                 /*!< 0x00004000 */
8757 #define ETH_MACA1HR_ADDRHI_15               (0x8000U << ETH_MACA1HR_ADDRHI_Pos)                 /*!< 0x00008000 */
8758 #define ETH_MACA1HR_MBC_Pos                 (24U)
8759 #define ETH_MACA1HR_MBC_Msk                 (0x3FU << ETH_MACA1HR_MBC_Pos)                      /*!< 0x3F000000 */
8760 #define ETH_MACA1HR_MBC                     ETH_MACA1HR_MBC_Msk                                 /*!< Mask Byte Control */
8761 #define ETH_MACA1HR_MBC_0                   (0x1U << ETH_MACA1HR_MBC_Pos)                 /*!< 0x01000000 */
8762 #define ETH_MACA1HR_MBC_1                   (0x2U << ETH_MACA1HR_MBC_Pos)                 /*!< 0x02000000 */
8763 #define ETH_MACA1HR_MBC_2                   (0x4U << ETH_MACA1HR_MBC_Pos)                 /*!< 0x04000000 */
8764 #define ETH_MACA1HR_MBC_3                   (0x8U << ETH_MACA1HR_MBC_Pos)                 /*!< 0x08000000 */
8765 #define ETH_MACA1HR_MBC_4                   (0x10U << ETH_MACA1HR_MBC_Pos)                /*!< 0x10000000 */
8766 #define ETH_MACA1HR_MBC_5                   (0x20U << ETH_MACA1HR_MBC_Pos)                /*!< 0x20000000 */
8767 #define ETH_MACA1HR_SA_Pos                  (30U)
8768 #define ETH_MACA1HR_SA_Msk                  (0x1U << ETH_MACA1HR_SA_Pos)                        /*!< 0x40000000 */
8769 #define ETH_MACA1HR_SA                      ETH_MACA1HR_SA_Msk                                  /*!< Source Address */
8770 #define ETH_MACA1HR_AE_Pos                  (31U)
8771 #define ETH_MACA1HR_AE_Msk                  (0x1U << ETH_MACA1HR_AE_Pos)                        /*!< 0x80000000 */
8772 #define ETH_MACA1HR_AE                      ETH_MACA1HR_AE_Msk                                  /*!< Address Enable */
8773 
8774 /**************  Bit definition for ETH_MACA1LR register  **************/
8775 #define ETH_MACA1LR_ADDRLO_Pos              (0U)
8776 #define ETH_MACA1LR_ADDRLO_Msk              (0xFFFFFFFFU << ETH_MACA1LR_ADDRLO_Pos)             /*!< 0xFFFFFFFF */
8777 #define ETH_MACA1LR_ADDRLO                  ETH_MACA1LR_ADDRLO_Msk                              /*!< MAC Address x [31:0] (x = 0 to 3) */
8778 #define ETH_MACA1LR_ADDRLO_0                (0x1U << ETH_MACA1LR_ADDRLO_Pos)                    /*!< 0x00000001 */
8779 #define ETH_MACA1LR_ADDRLO_1                (0x2U << ETH_MACA1LR_ADDRLO_Pos)                    /*!< 0x00000002 */
8780 #define ETH_MACA1LR_ADDRLO_2                (0x4U << ETH_MACA1LR_ADDRLO_Pos)                    /*!< 0x00000004 */
8781 #define ETH_MACA1LR_ADDRLO_3                (0x8U << ETH_MACA1LR_ADDRLO_Pos)                    /*!< 0x00000008 */
8782 #define ETH_MACA1LR_ADDRLO_4                (0x10U << ETH_MACA1LR_ADDRLO_Pos)                   /*!< 0x00000010 */
8783 #define ETH_MACA1LR_ADDRLO_5                (0x20U << ETH_MACA1LR_ADDRLO_Pos)                   /*!< 0x00000020 */
8784 #define ETH_MACA1LR_ADDRLO_6                (0x40U << ETH_MACA1LR_ADDRLO_Pos)                   /*!< 0x00000040 */
8785 #define ETH_MACA1LR_ADDRLO_7                (0x80U << ETH_MACA1LR_ADDRLO_Pos)                   /*!< 0x00000080 */
8786 #define ETH_MACA1LR_ADDRLO_8                (0x100U << ETH_MACA1LR_ADDRLO_Pos)                  /*!< 0x00000100 */
8787 #define ETH_MACA1LR_ADDRLO_9                (0x200U << ETH_MACA1LR_ADDRLO_Pos)                  /*!< 0x00000200 */
8788 #define ETH_MACA1LR_ADDRLO_10               (0x400U << ETH_MACA1LR_ADDRLO_Pos)                  /*!< 0x00000400 */
8789 #define ETH_MACA1LR_ADDRLO_11               (0x800U << ETH_MACA1LR_ADDRLO_Pos)                  /*!< 0x00000800 */
8790 #define ETH_MACA1LR_ADDRLO_12               (0x1000U << ETH_MACA1LR_ADDRLO_Pos)                 /*!< 0x00001000 */
8791 #define ETH_MACA1LR_ADDRLO_13               (0x2000U << ETH_MACA1LR_ADDRLO_Pos)                 /*!< 0x00002000 */
8792 #define ETH_MACA1LR_ADDRLO_14               (0x4000U << ETH_MACA1LR_ADDRLO_Pos)                 /*!< 0x00004000 */
8793 #define ETH_MACA1LR_ADDRLO_15               (0x8000U << ETH_MACA1LR_ADDRLO_Pos)                 /*!< 0x00008000 */
8794 #define ETH_MACA1LR_ADDRLO_16               (0x10000U << ETH_MACA1LR_ADDRLO_Pos)                /*!< 0x00010000 */
8795 #define ETH_MACA1LR_ADDRLO_17               (0x20000U << ETH_MACA1LR_ADDRLO_Pos)                /*!< 0x00020000 */
8796 #define ETH_MACA1LR_ADDRLO_18               (0x40000U << ETH_MACA1LR_ADDRLO_Pos)                /*!< 0x00040000 */
8797 #define ETH_MACA1LR_ADDRLO_19               (0x80000U << ETH_MACA1LR_ADDRLO_Pos)                /*!< 0x00080000 */
8798 #define ETH_MACA1LR_ADDRLO_20               (0x100000U << ETH_MACA1LR_ADDRLO_Pos)               /*!< 0x00100000 */
8799 #define ETH_MACA1LR_ADDRLO_21               (0x200000U << ETH_MACA1LR_ADDRLO_Pos)               /*!< 0x00200000 */
8800 #define ETH_MACA1LR_ADDRLO_22               (0x400000U << ETH_MACA1LR_ADDRLO_Pos)               /*!< 0x00400000 */
8801 #define ETH_MACA1LR_ADDRLO_23               (0x800000U << ETH_MACA1LR_ADDRLO_Pos)               /*!< 0x00800000 */
8802 #define ETH_MACA1LR_ADDRLO_24               (0x1000000U << ETH_MACA1LR_ADDRLO_Pos)              /*!< 0x01000000 */
8803 #define ETH_MACA1LR_ADDRLO_25               (0x2000000U << ETH_MACA1LR_ADDRLO_Pos)              /*!< 0x02000000 */
8804 #define ETH_MACA1LR_ADDRLO_26               (0x4000000U << ETH_MACA1LR_ADDRLO_Pos)              /*!< 0x04000000 */
8805 #define ETH_MACA1LR_ADDRLO_27               (0x8000000U << ETH_MACA1LR_ADDRLO_Pos)              /*!< 0x08000000 */
8806 #define ETH_MACA1LR_ADDRLO_28               (0x10000000U << ETH_MACA1LR_ADDRLO_Pos)             /*!< 0x10000000 */
8807 #define ETH_MACA1LR_ADDRLO_29               (0x20000000U << ETH_MACA1LR_ADDRLO_Pos)             /*!< 0x20000000 */
8808 #define ETH_MACA1LR_ADDRLO_30               (0x40000000U << ETH_MACA1LR_ADDRLO_Pos)             /*!< 0x40000000 */
8809 #define ETH_MACA1LR_ADDRLO_31               (0x80000000U << ETH_MACA1LR_ADDRLO_Pos)             /*!< 0x80000000 */
8810 
8811 /**************  Bit definition for ETH_MACA2HR register  **************/
8812 #define ETH_MACA2HR_ADDRHI_Pos              (0U)
8813 #define ETH_MACA2HR_ADDRHI_Msk              (0xFFFFU << ETH_MACA2HR_ADDRHI_Pos)                 /*!< 0x0000FFFF */
8814 #define ETH_MACA2HR_ADDRHI                  ETH_MACA2HR_ADDRHI_Msk                              /*!< MAC Address1 [47:32] */
8815 #define ETH_MACA2HR_ADDRHI_0                (0x1U << ETH_MACA2HR_ADDRHI_Pos)                    /*!< 0x00000001 */
8816 #define ETH_MACA2HR_ADDRHI_1                (0x2U << ETH_MACA2HR_ADDRHI_Pos)                    /*!< 0x00000002 */
8817 #define ETH_MACA2HR_ADDRHI_2                (0x4U << ETH_MACA2HR_ADDRHI_Pos)                    /*!< 0x00000004 */
8818 #define ETH_MACA2HR_ADDRHI_3                (0x8U << ETH_MACA2HR_ADDRHI_Pos)                    /*!< 0x00000008 */
8819 #define ETH_MACA2HR_ADDRHI_4                (0x10U << ETH_MACA2HR_ADDRHI_Pos)                   /*!< 0x00000010 */
8820 #define ETH_MACA2HR_ADDRHI_5                (0x20U << ETH_MACA2HR_ADDRHI_Pos)                   /*!< 0x00000020 */
8821 #define ETH_MACA2HR_ADDRHI_6                (0x40U << ETH_MACA2HR_ADDRHI_Pos)                   /*!< 0x00000040 */
8822 #define ETH_MACA2HR_ADDRHI_7                (0x80U << ETH_MACA2HR_ADDRHI_Pos)                   /*!< 0x00000080 */
8823 #define ETH_MACA2HR_ADDRHI_8                (0x100U << ETH_MACA2HR_ADDRHI_Pos)                  /*!< 0x00000100 */
8824 #define ETH_MACA2HR_ADDRHI_9                (0x200U << ETH_MACA2HR_ADDRHI_Pos)                  /*!< 0x00000200 */
8825 #define ETH_MACA2HR_ADDRHI_10               (0x400U << ETH_MACA2HR_ADDRHI_Pos)                  /*!< 0x00000400 */
8826 #define ETH_MACA2HR_ADDRHI_11               (0x800U << ETH_MACA2HR_ADDRHI_Pos)                  /*!< 0x00000800 */
8827 #define ETH_MACA2HR_ADDRHI_12               (0x1000U << ETH_MACA2HR_ADDRHI_Pos)                 /*!< 0x00001000 */
8828 #define ETH_MACA2HR_ADDRHI_13               (0x2000U << ETH_MACA2HR_ADDRHI_Pos)                 /*!< 0x00002000 */
8829 #define ETH_MACA2HR_ADDRHI_14               (0x4000U << ETH_MACA2HR_ADDRHI_Pos)                 /*!< 0x00004000 */
8830 #define ETH_MACA2HR_ADDRHI_15               (0x8000U << ETH_MACA2HR_ADDRHI_Pos)                 /*!< 0x00008000 */
8831 #define ETH_MACA2HR_MBC_Pos                 (24U)
8832 #define ETH_MACA2HR_MBC_Msk                 (0x3FU << ETH_MACA2HR_MBC_Pos)                      /*!< 0x3F000000 */
8833 #define ETH_MACA2HR_MBC                     ETH_MACA2HR_MBC_Msk                                 /*!< Mask Byte Control */
8834 #define ETH_MACA2HR_MBC_0                   (0x1U << ETH_MACA2HR_MBC_Pos)                 /*!< 0x01000000 */
8835 #define ETH_MACA2HR_MBC_1                   (0x2U << ETH_MACA2HR_MBC_Pos)                 /*!< 0x02000000 */
8836 #define ETH_MACA2HR_MBC_2                   (0x4U << ETH_MACA2HR_MBC_Pos)                 /*!< 0x04000000 */
8837 #define ETH_MACA2HR_MBC_3                   (0x8U << ETH_MACA2HR_MBC_Pos)                 /*!< 0x08000000 */
8838 #define ETH_MACA2HR_MBC_4                   (0x10U << ETH_MACA2HR_MBC_Pos)                /*!< 0x10000000 */
8839 #define ETH_MACA2HR_MBC_5                   (0x20U << ETH_MACA2HR_MBC_Pos)                /*!< 0x20000000 */
8840 #define ETH_MACA2HR_SA_Pos                  (30U)
8841 #define ETH_MACA2HR_SA_Msk                  (0x1U << ETH_MACA2HR_SA_Pos)                        /*!< 0x40000000 */
8842 #define ETH_MACA2HR_SA                      ETH_MACA2HR_SA_Msk                                  /*!< Source Address */
8843 #define ETH_MACA2HR_AE_Pos                  (31U)
8844 #define ETH_MACA2HR_AE_Msk                  (0x1U << ETH_MACA2HR_AE_Pos)                        /*!< 0x80000000 */
8845 #define ETH_MACA2HR_AE                      ETH_MACA2HR_AE_Msk                                  /*!< Address Enable */
8846 
8847 /**************  Bit definition for ETH_MACA2LR register  **************/
8848 #define ETH_MACA2LR_ADDRLO_Pos              (0U)
8849 #define ETH_MACA2LR_ADDRLO_Msk              (0xFFFFFFFFU << ETH_MACA2LR_ADDRLO_Pos)             /*!< 0xFFFFFFFF */
8850 #define ETH_MACA2LR_ADDRLO                  ETH_MACA2LR_ADDRLO_Msk                              /*!< MAC Address x [31:0] (x = 0 to 3) */
8851 #define ETH_MACA2LR_ADDRLO_0                (0x1U << ETH_MACA2LR_ADDRLO_Pos)                    /*!< 0x00000001 */
8852 #define ETH_MACA2LR_ADDRLO_1                (0x2U << ETH_MACA2LR_ADDRLO_Pos)                    /*!< 0x00000002 */
8853 #define ETH_MACA2LR_ADDRLO_2                (0x4U << ETH_MACA2LR_ADDRLO_Pos)                    /*!< 0x00000004 */
8854 #define ETH_MACA2LR_ADDRLO_3                (0x8U << ETH_MACA2LR_ADDRLO_Pos)                    /*!< 0x00000008 */
8855 #define ETH_MACA2LR_ADDRLO_4                (0x10U << ETH_MACA2LR_ADDRLO_Pos)                   /*!< 0x00000010 */
8856 #define ETH_MACA2LR_ADDRLO_5                (0x20U << ETH_MACA2LR_ADDRLO_Pos)                   /*!< 0x00000020 */
8857 #define ETH_MACA2LR_ADDRLO_6                (0x40U << ETH_MACA2LR_ADDRLO_Pos)                   /*!< 0x00000040 */
8858 #define ETH_MACA2LR_ADDRLO_7                (0x80U << ETH_MACA2LR_ADDRLO_Pos)                   /*!< 0x00000080 */
8859 #define ETH_MACA2LR_ADDRLO_8                (0x100U << ETH_MACA2LR_ADDRLO_Pos)                  /*!< 0x00000100 */
8860 #define ETH_MACA2LR_ADDRLO_9                (0x200U << ETH_MACA2LR_ADDRLO_Pos)                  /*!< 0x00000200 */
8861 #define ETH_MACA2LR_ADDRLO_10               (0x400U << ETH_MACA2LR_ADDRLO_Pos)                  /*!< 0x00000400 */
8862 #define ETH_MACA2LR_ADDRLO_11               (0x800U << ETH_MACA2LR_ADDRLO_Pos)                  /*!< 0x00000800 */
8863 #define ETH_MACA2LR_ADDRLO_12               (0x1000U << ETH_MACA2LR_ADDRLO_Pos)                 /*!< 0x00001000 */
8864 #define ETH_MACA2LR_ADDRLO_13               (0x2000U << ETH_MACA2LR_ADDRLO_Pos)                 /*!< 0x00002000 */
8865 #define ETH_MACA2LR_ADDRLO_14               (0x4000U << ETH_MACA2LR_ADDRLO_Pos)                 /*!< 0x00004000 */
8866 #define ETH_MACA2LR_ADDRLO_15               (0x8000U << ETH_MACA2LR_ADDRLO_Pos)                 /*!< 0x00008000 */
8867 #define ETH_MACA2LR_ADDRLO_16               (0x10000U << ETH_MACA2LR_ADDRLO_Pos)                /*!< 0x00010000 */
8868 #define ETH_MACA2LR_ADDRLO_17               (0x20000U << ETH_MACA2LR_ADDRLO_Pos)                /*!< 0x00020000 */
8869 #define ETH_MACA2LR_ADDRLO_18               (0x40000U << ETH_MACA2LR_ADDRLO_Pos)                /*!< 0x00040000 */
8870 #define ETH_MACA2LR_ADDRLO_19               (0x80000U << ETH_MACA2LR_ADDRLO_Pos)                /*!< 0x00080000 */
8871 #define ETH_MACA2LR_ADDRLO_20               (0x100000U << ETH_MACA2LR_ADDRLO_Pos)               /*!< 0x00100000 */
8872 #define ETH_MACA2LR_ADDRLO_21               (0x200000U << ETH_MACA2LR_ADDRLO_Pos)               /*!< 0x00200000 */
8873 #define ETH_MACA2LR_ADDRLO_22               (0x400000U << ETH_MACA2LR_ADDRLO_Pos)               /*!< 0x00400000 */
8874 #define ETH_MACA2LR_ADDRLO_23               (0x800000U << ETH_MACA2LR_ADDRLO_Pos)               /*!< 0x00800000 */
8875 #define ETH_MACA2LR_ADDRLO_24               (0x1000000U << ETH_MACA2LR_ADDRLO_Pos)              /*!< 0x01000000 */
8876 #define ETH_MACA2LR_ADDRLO_25               (0x2000000U << ETH_MACA2LR_ADDRLO_Pos)              /*!< 0x02000000 */
8877 #define ETH_MACA2LR_ADDRLO_26               (0x4000000U << ETH_MACA2LR_ADDRLO_Pos)              /*!< 0x04000000 */
8878 #define ETH_MACA2LR_ADDRLO_27               (0x8000000U << ETH_MACA2LR_ADDRLO_Pos)              /*!< 0x08000000 */
8879 #define ETH_MACA2LR_ADDRLO_28               (0x10000000U << ETH_MACA2LR_ADDRLO_Pos)             /*!< 0x10000000 */
8880 #define ETH_MACA2LR_ADDRLO_29               (0x20000000U << ETH_MACA2LR_ADDRLO_Pos)             /*!< 0x20000000 */
8881 #define ETH_MACA2LR_ADDRLO_30               (0x40000000U << ETH_MACA2LR_ADDRLO_Pos)             /*!< 0x40000000 */
8882 #define ETH_MACA2LR_ADDRLO_31               (0x80000000U << ETH_MACA2LR_ADDRLO_Pos)             /*!< 0x80000000 */
8883 
8884 /**************  Bit definition for ETH_MACA3HR register  **************/
8885 #define ETH_MACA3HR_ADDRHI_Pos              (0U)
8886 #define ETH_MACA3HR_ADDRHI_Msk              (0xFFFFU << ETH_MACA3HR_ADDRHI_Pos)                 /*!< 0x0000FFFF */
8887 #define ETH_MACA3HR_ADDRHI                  ETH_MACA3HR_ADDRHI_Msk                              /*!< MAC Address1 [47:32] */
8888 #define ETH_MACA3HR_ADDRHI_0                (0x1U << ETH_MACA3HR_ADDRHI_Pos)                    /*!< 0x00000001 */
8889 #define ETH_MACA3HR_ADDRHI_1                (0x2U << ETH_MACA3HR_ADDRHI_Pos)                    /*!< 0x00000002 */
8890 #define ETH_MACA3HR_ADDRHI_2                (0x4U << ETH_MACA3HR_ADDRHI_Pos)                    /*!< 0x00000004 */
8891 #define ETH_MACA3HR_ADDRHI_3                (0x8U << ETH_MACA3HR_ADDRHI_Pos)                    /*!< 0x00000008 */
8892 #define ETH_MACA3HR_ADDRHI_4                (0x10U << ETH_MACA3HR_ADDRHI_Pos)                   /*!< 0x00000010 */
8893 #define ETH_MACA3HR_ADDRHI_5                (0x20U << ETH_MACA3HR_ADDRHI_Pos)                   /*!< 0x00000020 */
8894 #define ETH_MACA3HR_ADDRHI_6                (0x40U << ETH_MACA3HR_ADDRHI_Pos)                   /*!< 0x00000040 */
8895 #define ETH_MACA3HR_ADDRHI_7                (0x80U << ETH_MACA3HR_ADDRHI_Pos)                   /*!< 0x00000080 */
8896 #define ETH_MACA3HR_ADDRHI_8                (0x100U << ETH_MACA3HR_ADDRHI_Pos)                  /*!< 0x00000100 */
8897 #define ETH_MACA3HR_ADDRHI_9                (0x200U << ETH_MACA3HR_ADDRHI_Pos)                  /*!< 0x00000200 */
8898 #define ETH_MACA3HR_ADDRHI_10               (0x400U << ETH_MACA3HR_ADDRHI_Pos)                  /*!< 0x00000400 */
8899 #define ETH_MACA3HR_ADDRHI_11               (0x800U << ETH_MACA3HR_ADDRHI_Pos)                  /*!< 0x00000800 */
8900 #define ETH_MACA3HR_ADDRHI_12               (0x1000U << ETH_MACA3HR_ADDRHI_Pos)                 /*!< 0x00001000 */
8901 #define ETH_MACA3HR_ADDRHI_13               (0x2000U << ETH_MACA3HR_ADDRHI_Pos)                 /*!< 0x00002000 */
8902 #define ETH_MACA3HR_ADDRHI_14               (0x4000U << ETH_MACA3HR_ADDRHI_Pos)                 /*!< 0x00004000 */
8903 #define ETH_MACA3HR_ADDRHI_15               (0x8000U << ETH_MACA3HR_ADDRHI_Pos)                 /*!< 0x00008000 */
8904 #define ETH_MACA3HR_MBC_Pos                 (24U)
8905 #define ETH_MACA3HR_MBC_Msk                 (0x3FU << ETH_MACA3HR_MBC_Pos)                      /*!< 0x3F000000 */
8906 #define ETH_MACA3HR_MBC                     ETH_MACA3HR_MBC_Msk                                 /*!< Mask Byte Control */
8907 #define ETH_MACA3HR_MBC_0                   (0x1U << ETH_MACA3HR_MBC_Pos)                 /*!< 0x01000000 */
8908 #define ETH_MACA3HR_MBC_1                   (0x2U << ETH_MACA3HR_MBC_Pos)                 /*!< 0x02000000 */
8909 #define ETH_MACA3HR_MBC_2                   (0x4U << ETH_MACA3HR_MBC_Pos)                 /*!< 0x04000000 */
8910 #define ETH_MACA3HR_MBC_3                   (0x8U << ETH_MACA3HR_MBC_Pos)                 /*!< 0x08000000 */
8911 #define ETH_MACA3HR_MBC_4                   (0x10U << ETH_MACA3HR_MBC_Pos)                /*!< 0x10000000 */
8912 #define ETH_MACA3HR_MBC_5                   (0x20U << ETH_MACA3HR_MBC_Pos)                /*!< 0x20000000 */
8913 #define ETH_MACA3HR_SA_Pos                  (30U)
8914 #define ETH_MACA3HR_SA_Msk                  (0x1U << ETH_MACA3HR_SA_Pos)                        /*!< 0x40000000 */
8915 #define ETH_MACA3HR_SA                      ETH_MACA3HR_SA_Msk                                  /*!< Source Address */
8916 #define ETH_MACA3HR_AE_Pos                  (31U)
8917 #define ETH_MACA3HR_AE_Msk                  (0x1U << ETH_MACA3HR_AE_Pos)                        /*!< 0x80000000 */
8918 #define ETH_MACA3HR_AE                      ETH_MACA3HR_AE_Msk                                  /*!< Address Enable */
8919 
8920 /**************  Bit definition for ETH_MACA3LR register  **************/
8921 #define ETH_MACA3LR_ADDRLO_Pos              (0U)
8922 #define ETH_MACA3LR_ADDRLO_Msk              (0xFFFFFFFFU << ETH_MACA3LR_ADDRLO_Pos)             /*!< 0xFFFFFFFF */
8923 #define ETH_MACA3LR_ADDRLO                  ETH_MACA3LR_ADDRLO_Msk                              /*!< MAC Address x [31:0] (x = 0 to 3) */
8924 #define ETH_MACA3LR_ADDRLO_0                (0x1U << ETH_MACA3LR_ADDRLO_Pos)                    /*!< 0x00000001 */
8925 #define ETH_MACA3LR_ADDRLO_1                (0x2U << ETH_MACA3LR_ADDRLO_Pos)                    /*!< 0x00000002 */
8926 #define ETH_MACA3LR_ADDRLO_2                (0x4U << ETH_MACA3LR_ADDRLO_Pos)                    /*!< 0x00000004 */
8927 #define ETH_MACA3LR_ADDRLO_3                (0x8U << ETH_MACA3LR_ADDRLO_Pos)                    /*!< 0x00000008 */
8928 #define ETH_MACA3LR_ADDRLO_4                (0x10U << ETH_MACA3LR_ADDRLO_Pos)                   /*!< 0x00000010 */
8929 #define ETH_MACA3LR_ADDRLO_5                (0x20U << ETH_MACA3LR_ADDRLO_Pos)                   /*!< 0x00000020 */
8930 #define ETH_MACA3LR_ADDRLO_6                (0x40U << ETH_MACA3LR_ADDRLO_Pos)                   /*!< 0x00000040 */
8931 #define ETH_MACA3LR_ADDRLO_7                (0x80U << ETH_MACA3LR_ADDRLO_Pos)                   /*!< 0x00000080 */
8932 #define ETH_MACA3LR_ADDRLO_8                (0x100U << ETH_MACA3LR_ADDRLO_Pos)                  /*!< 0x00000100 */
8933 #define ETH_MACA3LR_ADDRLO_9                (0x200U << ETH_MACA3LR_ADDRLO_Pos)                  /*!< 0x00000200 */
8934 #define ETH_MACA3LR_ADDRLO_10               (0x400U << ETH_MACA3LR_ADDRLO_Pos)                  /*!< 0x00000400 */
8935 #define ETH_MACA3LR_ADDRLO_11               (0x800U << ETH_MACA3LR_ADDRLO_Pos)                  /*!< 0x00000800 */
8936 #define ETH_MACA3LR_ADDRLO_12               (0x1000U << ETH_MACA3LR_ADDRLO_Pos)                 /*!< 0x00001000 */
8937 #define ETH_MACA3LR_ADDRLO_13               (0x2000U << ETH_MACA3LR_ADDRLO_Pos)                 /*!< 0x00002000 */
8938 #define ETH_MACA3LR_ADDRLO_14               (0x4000U << ETH_MACA3LR_ADDRLO_Pos)                 /*!< 0x00004000 */
8939 #define ETH_MACA3LR_ADDRLO_15               (0x8000U << ETH_MACA3LR_ADDRLO_Pos)                 /*!< 0x00008000 */
8940 #define ETH_MACA3LR_ADDRLO_16               (0x10000U << ETH_MACA3LR_ADDRLO_Pos)                /*!< 0x00010000 */
8941 #define ETH_MACA3LR_ADDRLO_17               (0x20000U << ETH_MACA3LR_ADDRLO_Pos)                /*!< 0x00020000 */
8942 #define ETH_MACA3LR_ADDRLO_18               (0x40000U << ETH_MACA3LR_ADDRLO_Pos)                /*!< 0x00040000 */
8943 #define ETH_MACA3LR_ADDRLO_19               (0x80000U << ETH_MACA3LR_ADDRLO_Pos)                /*!< 0x00080000 */
8944 #define ETH_MACA3LR_ADDRLO_20               (0x100000U << ETH_MACA3LR_ADDRLO_Pos)               /*!< 0x00100000 */
8945 #define ETH_MACA3LR_ADDRLO_21               (0x200000U << ETH_MACA3LR_ADDRLO_Pos)               /*!< 0x00200000 */
8946 #define ETH_MACA3LR_ADDRLO_22               (0x400000U << ETH_MACA3LR_ADDRLO_Pos)               /*!< 0x00400000 */
8947 #define ETH_MACA3LR_ADDRLO_23               (0x800000U << ETH_MACA3LR_ADDRLO_Pos)               /*!< 0x00800000 */
8948 #define ETH_MACA3LR_ADDRLO_24               (0x1000000U << ETH_MACA3LR_ADDRLO_Pos)              /*!< 0x01000000 */
8949 #define ETH_MACA3LR_ADDRLO_25               (0x2000000U << ETH_MACA3LR_ADDRLO_Pos)              /*!< 0x02000000 */
8950 #define ETH_MACA3LR_ADDRLO_26               (0x4000000U << ETH_MACA3LR_ADDRLO_Pos)              /*!< 0x04000000 */
8951 #define ETH_MACA3LR_ADDRLO_27               (0x8000000U << ETH_MACA3LR_ADDRLO_Pos)              /*!< 0x08000000 */
8952 #define ETH_MACA3LR_ADDRLO_28               (0x10000000U << ETH_MACA3LR_ADDRLO_Pos)             /*!< 0x10000000 */
8953 #define ETH_MACA3LR_ADDRLO_29               (0x20000000U << ETH_MACA3LR_ADDRLO_Pos)             /*!< 0x20000000 */
8954 #define ETH_MACA3LR_ADDRLO_30               (0x40000000U << ETH_MACA3LR_ADDRLO_Pos)             /*!< 0x40000000 */
8955 #define ETH_MACA3LR_ADDRLO_31               (0x80000000U << ETH_MACA3LR_ADDRLO_Pos)             /*!< 0x80000000 */
8956 
8957 /************  Bit definition for ETH_MMC_CONTROL register  ************/
8958 #define ETH_MMCCR_CNTRST_Pos                (0U)
8959 #define ETH_MMCCR_CNTRST_Msk                (0x1U << ETH_MMCCR_CNTRST_Pos)                /*!< 0x00000001 */
8960 #define ETH_MMCCR_CNTRST                    ETH_MMCCR_CNTRST_Msk                          /*!< Counters Reset */
8961 #define ETH_MMCCR_CNTSTOPRO_Pos             (1U)
8962 #define ETH_MMCCR_CNTSTOPRO_Msk             (0x1U << ETH_MMCCR_CNTSTOPRO_Pos)             /*!< 0x00000002 */
8963 #define ETH_MMCCR_CNTSTOPRO                 ETH_MMCCR_CNTSTOPRO_Msk                       /*!< Counter Stop Rollover */
8964 #define ETH_MMCCR_RSTONRD_Pos               (2U)
8965 #define ETH_MMCCR_RSTONRD_Msk               (0x1U << ETH_MMCCR_RSTONRD_Pos)               /*!< 0x00000004 */
8966 #define ETH_MMCCR_RSTONRD                   ETH_MMCCR_RSTONRD_Msk                         /*!< Reset on Read */
8967 #define ETH_MMCCR_CNTFREEZ_Pos              (3U)
8968 #define ETH_MMCCR_CNTFREEZ_Msk              (0x1U << ETH_MMCCR_CNTFREEZ_Pos)              /*!< 0x00000008 */
8969 #define ETH_MMCCR_CNTFREEZ                  ETH_MMCCR_CNTFREEZ_Msk                        /*!< MMC Counter Freeze */
8970 #define ETH_MMCCR_CNTPRST_Pos               (4U)
8971 #define ETH_MMCCR_CNTPRST_Msk               (0x1U << ETH_MMCCR_CNTPRST_Pos)               /*!< 0x00000010 */
8972 #define ETH_MMCCR_CNTPRST                   ETH_MMCCR_CNTPRST_Msk                         /*!< Counters Preset */
8973 #define ETH_MMCCR_CNTPRSTLVL_Pos            (5U)
8974 #define ETH_MMCCR_CNTPRSTLVL_Msk            (0x1U << ETH_MMCCR_CNTPRSTLVL_Pos)            /*!< 0x00000020 */
8975 #define ETH_MMCCR_CNTPRSTLVL                ETH_MMCCR_CNTPRSTLVL_Msk                      /*!< Full-Half Preset */
8976 #define ETH_MMCCR_UCDBC_Pos                 (8U)
8977 #define ETH_MMCCR_UCDBC_Msk                 (0x1U << ETH_MMCCR_UCDBC_Pos)                 /*!< 0x00000100 */
8978 #define ETH_MMCCR_UCDBC                     ETH_MMCCR_UCDBC_Msk                           /*!< Update MMC Counters for Dropped Broadcast Packets */
8979 
8980 /***********  Bit definition for ETH_MMC_RX_INTERRUPT register  ************/
8981 #define ETH_MMCRXIR_RXCRCERPIS_Pos          (5U)
8982 #define ETH_MMCRXIR_RXCRCERPIS_Msk          (0x1U << ETH_MMCRXIR_RXCRCERPIS_Pos)         /*!< 0x00000020 */
8983 #define ETH_MMCRXIR_RXCRCERPIS              ETH_MMCRXIR_RXCRCERPIS_Msk                   /*!< MMC Receive CRC Error Packet Counter Interrupt Status */
8984 #define ETH_MMCRXIR_RXALGNERPIS_Pos         (6U)
8985 #define ETH_MMCRXIR_RXALGNERPIS_Msk         (0x1U << ETH_MMCRXIR_RXALGNERPIS_Pos)        /*!< 0x00000040 */
8986 #define ETH_MMCRXIR_RXALGNERPIS             ETH_MMCRXIR_RXALGNERPIS_Msk                  /*!< MMC Receive Alignment Error Packet Counter Interrupt Status */
8987 #define ETH_MMCRXIR_RXUCGPIS_Pos            (17U)
8988 #define ETH_MMCRXIR_RXUCGPIS_Msk            (0x1U << ETH_MMCRXIR_RXUCGPIS_Pos)           /*!< 0x00020000 */
8989 #define ETH_MMCRXIR_RXUCGPIS                ETH_MMCRXIR_RXUCGPIS_Msk                     /*!< MMC Receive Unicast Good Packet Counter Interrupt Status */
8990 #define ETH_MMCRXIR_RXLPIUSCIS_Pos          (26U)
8991 #define ETH_MMCRXIR_RXLPIUSCIS_Msk          (0x1U << ETH_MMCRXIR_RXLPIUSCIS_Pos)         /*!< 0x04000000 */
8992 #define ETH_MMCRXIR_RXLPIUSCIS              ETH_MMCRXIR_RXLPIUSCIS_Msk                   /*!< MMC Receive LPI microsecond counter interrupt status */
8993 #define ETH_MMCRXIR_RXLPITRCIS_Pos          (27U)
8994 #define ETH_MMCRXIR_RXLPITRCIS_Msk          (0x1U << ETH_MMCRXIR_RXLPITRCIS_Pos)         /*!< 0x08000000 */
8995 #define ETH_MMCRXIR_RXLPITRCIS              ETH_MMCRXIR_RXLPITRCIS_Msk                   /*!< MMC Receive LPI transition counter interrupt status */
8996 
8997 /***********  Bit definition for ETH_MMC_TX_INTERRUPT register  ************/
8998 #define ETH_MMCTXIR_TXSCOLGPIS_Pos          (14U)
8999 #define ETH_MMCTXIR_TXSCOLGPIS_Msk          (0x1U << ETH_MMCTXIR_TXSCOLGPIS_Pos)         /*!< 0x00004000 */
9000 #define ETH_MMCTXIR_TXSCOLGPIS              ETH_MMCTXIR_TXSCOLGPIS_Msk                   /*!< MMC Transmit Single Collision Good Packet Counter Interrupt Status */
9001 #define ETH_MMCTXIR_TXMCOLGPIS_Pos          (15U)
9002 #define ETH_MMCTXIR_TXMCOLGPIS_Msk          (0x1U << ETH_MMCTXIR_TXMCOLGPIS_Pos)         /*!< 0x00008000 */
9003 #define ETH_MMCTXIR_TXMCOLGPIS              ETH_MMCTXIR_TXMCOLGPIS_Msk                   /*!< MMC Transmit Multiple Collision Good Packet Counter Interrupt Status */
9004 #define ETH_MMCTXIR_TXGPKTIS_Pos            (21U)
9005 #define ETH_MMCTXIR_TXGPKTIS_Msk            (0x1U << ETH_MMCTXIR_TXGPKTIS_Pos)           /*!< 0x00200000 */
9006 #define ETH_MMCTXIR_TXGPKTIS                ETH_MMCTXIR_TXGPKTIS_Msk                     /*!< MMC Transmit Good Packet Counter Interrupt Status */
9007 #define ETH_MMCTXIR_TXLPIUSCIS_Pos          (26U)
9008 #define ETH_MMCTXIR_TXLPIUSCIS_Msk          (0x1U << ETH_MMCTXIR_TXLPIUSCIS_Pos)         /*!< 0x04000000 */
9009 #define ETH_MMCTXIR_TXLPIUSCIS              ETH_MMCTXIR_TXLPIUSCIS_Msk                   /*!< MMC Transmit LPI microsecond counter interrupt status */
9010 #define ETH_MMCTXIR_TXLPITRCIS_Pos          (27U)
9011 #define ETH_MMCTXIR_TXLPITRCIS_Msk          (0x1U << ETH_MMCTXIR_TXLPITRCIS_Pos)         /*!< 0x08000000 */
9012 #define ETH_MMCTXIR_TXLPITRCIS              ETH_MMCTXIR_TXLPITRCIS_Msk                   /*!< MMC Transmit LPI transition counter interrupt status */
9013 
9014 /**********  Bit definition for ETH_MMC_RX_INTERRUPT_MASK register  ***********/
9015 #define ETH_MMCRXIMR_RXCRCERPIM_Pos         (5U)
9016 #define ETH_MMCRXIMR_RXCRCERPIM_Msk         (0x1U << ETH_MMCRXIMR_RXCRCERPIM_Pos)         /*!< 0x00000020 */
9017 #define ETH_MMCRXIMR_RXCRCERPIM             ETH_MMCRXIMR_RXCRCERPIM_Msk                   /*!< MMC Receive CRC Error Packet Counter Interrupt Mask */
9018 #define ETH_MMCRXIMR_RXALGNERPIM_Pos        (6U)
9019 #define ETH_MMCRXIMR_RXALGNERPIM_Msk        (0x1U << ETH_MMCRXIMR_RXALGNERPIM_Pos)        /*!< 0x00000040 */
9020 #define ETH_MMCRXIMR_RXALGNERPIM            ETH_MMCRXIMR_RXALGNERPIM_Msk                  /*!< MMC Receive Alignment Error Packet Counter Interrupt Mask */
9021 #define ETH_MMCRXIMR_RXUCGPIM_Pos           (17U)
9022 #define ETH_MMCRXIMR_RXUCGPIM_Msk           (0x1U << ETH_MMCRXIMR_RXUCGPIM_Pos)           /*!< 0x00020000 */
9023 #define ETH_MMCRXIMR_RXUCGPIM               ETH_MMCRXIMR_RXUCGPIM_Msk                     /*!< MMC Receive Unicast Good Packet Counter Interrupt Mask */
9024 #define ETH_MMCRXIMR_RXLPIUSCIM_Pos         (26U)
9025 #define ETH_MMCRXIMR_RXLPIUSCIM_Msk         (0x1U << ETH_MMCRXIMR_RXLPIUSCIM_Pos)         /*!< 0x04000000 */
9026 #define ETH_MMCRXIMR_RXLPIUSCIM             ETH_MMCRXIMR_RXLPIUSCIM_Msk                   /*!< MMC Receive LPI microsecond counter interrupt Mask */
9027 #define ETH_MMCRXIMR_RXLPITRCIM_Pos         (27U)
9028 #define ETH_MMCRXIMR_RXLPITRCIM_Msk         (0x1U << ETH_MMCRXIMR_RXLPITRCIM_Pos)         /*!< 0x08000000 */
9029 #define ETH_MMCRXIMR_RXLPITRCIM             ETH_MMCRXIMR_RXLPITRCIM_Msk                   /*!< MMC Receive LPI transition counter interrupt Mask */
9030 
9031 /**********  Bit definition for ETH_MMC_TX_INTERRUPT_MASK register  ***********/
9032 #define ETH_MMCTXIMR_TXSCOLGPIM_Pos         (14U)
9033 #define ETH_MMCTXIMR_TXSCOLGPIM_Msk         (0x1U << ETH_MMCTXIMR_TXSCOLGPIM_Pos)        /*!< 0x00004000 */
9034 #define ETH_MMCTXIMR_TXSCOLGPIM             ETH_MMCTXIMR_TXSCOLGPIM_Msk                  /*!< MMC Transmit Single Collision Good Packet Counter Interrupt Mask */
9035 #define ETH_MMCTXIMR_TXMCOLGPIM_Pos         (15U)
9036 #define ETH_MMCTXIMR_TXMCOLGPIM_Msk         (0x1U << ETH_MMCTXIMR_TXMCOLGPIM_Pos)        /*!< 0x00008000 */
9037 #define ETH_MMCTXIMR_TXMCOLGPIM             ETH_MMCTXIMR_TXMCOLGPIM_Msk                  /*!< MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask */
9038 #define ETH_MMCTXIMR_TXGPKTIM_Pos           (21U)
9039 #define ETH_MMCTXIMR_TXGPKTIM_Msk           (0x1U << ETH_MMCTXIMR_TXGPKTIM_Pos)          /*!< 0x00200000 */
9040 #define ETH_MMCTXIMR_TXGPKTIM               ETH_MMCTXIMR_TXGPKTIM_Msk                    /*!< MMC Transmit Good Packet Counter Interrupt Mask */
9041 #define ETH_MMCTXIMR_TXLPIUSCIM_Pos         (26U)
9042 #define ETH_MMCTXIMR_TXLPIUSCIM_Msk         (0x1U << ETH_MMCTXIMR_TXLPIUSCIM_Pos)        /*!< 0x04000000 */
9043 #define ETH_MMCTXIMR_TXLPIUSCIM             ETH_MMCTXIMR_TXLPIUSCIM_Msk                  /*!< MMC Transmit LPI microsecond counter interrupt Mask */
9044 #define ETH_MMCTXIMR_TXLPITRCIM_Pos         (27U)
9045 #define ETH_MMCTXIMR_TXLPITRCIM_Msk         (0x1U << ETH_MMCTXIMR_TXLPITRCIM_Pos)        /*!< 0x08000000 */
9046 #define ETH_MMCTXIMR_TXLPITRCIM             ETH_MMC_INTERRUPT_MASK_TXLPITRCIM_Msk                  /*!< MMC Transmit LPI transition counter interrupt Mask */
9047 
9048 /***********  Bit definition for ETH_MMC_TX_SINGLE_COLLISION_GOOD_PACKETS register  ************/
9049 #define ETH_MMCTXSCGPR_TXSNGLCOLG_Pos       (0U)
9050 #define ETH_MMCTXSCGPR_TXSNGLCOLG_Msk       (0xFFFFFFFFU << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0xFFFFFFFF */
9051 #define ETH_MMCTXSCGPR_TXSNGLCOLG           ETH_MMCTXSCGPR_TXSNGLCOLG_Msk                  /*!< Tx Single Collision Good Packets */
9052 #define ETH_MMCTXSCGPR_TXSNGLCOLG_0         (0x1U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos)        /*!< 0x00000001 */
9053 #define ETH_MMCTXSCGPR_TXSNGLCOLG_1         (0x2U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos)        /*!< 0x00000002 */
9054 #define ETH_MMCTXSCGPR_TXSNGLCOLG_2         (0x4U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos)        /*!< 0x00000004 */
9055 #define ETH_MMCTXSCGPR_TXSNGLCOLG_3         (0x8U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos)        /*!< 0x00000008 */
9056 #define ETH_MMCTXSCGPR_TXSNGLCOLG_4         (0x10U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos)       /*!< 0x00000010 */
9057 #define ETH_MMCTXSCGPR_TXSNGLCOLG_5         (0x20U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos)       /*!< 0x00000020 */
9058 #define ETH_MMCTXSCGPR_TXSNGLCOLG_6         (0x40U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos)       /*!< 0x00000040 */
9059 #define ETH_MMCTXSCGPR_TXSNGLCOLG_7         (0x80U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos)       /*!< 0x00000080 */
9060 #define ETH_MMCTXSCGPR_TXSNGLCOLG_8         (0x100U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos)      /*!< 0x00000100 */
9061 #define ETH_MMCTXSCGPR_TXSNGLCOLG_9         (0x200U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos)      /*!< 0x00000200 */
9062 #define ETH_MMCTXSCGPR_TXSNGLCOLG_10        (0x400U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos)      /*!< 0x00000400 */
9063 #define ETH_MMCTXSCGPR_TXSNGLCOLG_11        (0x800U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos)      /*!< 0x00000800 */
9064 #define ETH_MMCTXSCGPR_TXSNGLCOLG_12        (0x1000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos)     /*!< 0x00001000 */
9065 #define ETH_MMCTXSCGPR_TXSNGLCOLG_13        (0x2000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos)     /*!< 0x00002000 */
9066 #define ETH_MMCTXSCGPR_TXSNGLCOLG_14        (0x4000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos)     /*!< 0x00004000 */
9067 #define ETH_MMCTXSCGPR_TXSNGLCOLG_15        (0x8000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos)     /*!< 0x00008000 */
9068 #define ETH_MMCTXSCGPR_TXSNGLCOLG_16        (0x10000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos)    /*!< 0x00010000 */
9069 #define ETH_MMCTXSCGPR_TXSNGLCOLG_17        (0x20000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos)    /*!< 0x00020000 */
9070 #define ETH_MMCTXSCGPR_TXSNGLCOLG_18        (0x40000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos)    /*!< 0x00040000 */
9071 #define ETH_MMCTXSCGPR_TXSNGLCOLG_19        (0x80000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos)    /*!< 0x00080000 */
9072 #define ETH_MMCTXSCGPR_TXSNGLCOLG_20        (0x100000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos)   /*!< 0x00100000 */
9073 #define ETH_MMCTXSCGPR_TXSNGLCOLG_21        (0x200000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos)   /*!< 0x00200000 */
9074 #define ETH_MMCTXSCGPR_TXSNGLCOLG_22        (0x400000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos)   /*!< 0x00400000 */
9075 #define ETH_MMCTXSCGPR_TXSNGLCOLG_23        (0x800000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos)   /*!< 0x00800000 */
9076 #define ETH_MMCTXSCGPR_TXSNGLCOLG_24        (0x1000000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos)  /*!< 0x01000000 */
9077 #define ETH_MMCTXSCGPR_TXSNGLCOLG_25        (0x2000000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos)  /*!< 0x02000000 */
9078 #define ETH_MMCTXSCGPR_TXSNGLCOLG_26        (0x4000000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos)  /*!< 0x04000000 */
9079 #define ETH_MMCTXSCGPR_TXSNGLCOLG_27        (0x8000000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos)  /*!< 0x08000000 */
9080 #define ETH_MMCTXSCGPR_TXSNGLCOLG_28        (0x10000000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x10000000 */
9081 #define ETH_MMCTXSCGPR_TXSNGLCOLG_29        (0x20000000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x20000000 */
9082 #define ETH_MMCTXSCGPR_TXSNGLCOLG_30        (0x40000000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x40000000 */
9083 #define ETH_MMCTXSCGPR_TXSNGLCOLG_31        (0x80000000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x80000000 */
9084 
9085 /***********  Bit definition for ETH_MMC_TX_MULTIPLE_COLLISION_GOOD_PACKETS register  ************/
9086 #define ETH_MMCTXMCGPR_TXMULTCOLG_Pos       (0U)
9087 #define ETH_MMCTXMCGPR_TXMULTCOLG_Msk       (0xFFFFFFFFU << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0xFFFFFFFF */
9088 #define ETH_MMCTXMCGPR_TXMULTCOLG           ETH_MMCTXMCGPR_TXMULTCOLG_Msk                  /*!< Tx Multiple Collision Good Packets */
9089 #define ETH_MMCTXMCGPR_TXMULTCOLG_0         (0x1U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos)        /*!< 0x00000001 */
9090 #define ETH_MMCTXMCGPR_TXMULTCOLG_1         (0x2U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos)        /*!< 0x00000002 */
9091 #define ETH_MMCTXMCGPR_TXMULTCOLG_2         (0x4U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos)        /*!< 0x00000004 */
9092 #define ETH_MMCTXMCGPR_TXMULTCOLG_3         (0x8U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos)        /*!< 0x00000008 */
9093 #define ETH_MMCTXMCGPR_TXMULTCOLG_4         (0x10U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos)       /*!< 0x00000010 */
9094 #define ETH_MMCTXMCGPR_TXMULTCOLG_5         (0x20U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos)       /*!< 0x00000020 */
9095 #define ETH_MMCTXMCGPR_TXMULTCOLG_6         (0x40U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos)       /*!< 0x00000040 */
9096 #define ETH_MMCTXMCGPR_TXMULTCOLG_7         (0x80U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos)       /*!< 0x00000080 */
9097 #define ETH_MMCTXMCGPR_TXMULTCOLG_8         (0x100U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos)      /*!< 0x00000100 */
9098 #define ETH_MMCTXMCGPR_TXMULTCOLG_9         (0x200U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos)      /*!< 0x00000200 */
9099 #define ETH_MMCTXMCGPR_TXMULTCOLG_10        (0x400U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos)      /*!< 0x00000400 */
9100 #define ETH_MMCTXMCGPR_TXMULTCOLG_11        (0x800U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos)      /*!< 0x00000800 */
9101 #define ETH_MMCTXMCGPR_TXMULTCOLG_12        (0x1000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos)     /*!< 0x00001000 */
9102 #define ETH_MMCTXMCGPR_TXMULTCOLG_13        (0x2000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos)     /*!< 0x00002000 */
9103 #define ETH_MMCTXMCGPR_TXMULTCOLG_14        (0x4000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos)     /*!< 0x00004000 */
9104 #define ETH_MMCTXMCGPR_TXMULTCOLG_15        (0x8000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos)     /*!< 0x00008000 */
9105 #define ETH_MMCTXMCGPR_TXMULTCOLG_16        (0x10000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos)    /*!< 0x00010000 */
9106 #define ETH_MMCTXMCGPR_TXMULTCOLG_17        (0x20000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos)    /*!< 0x00020000 */
9107 #define ETH_MMCTXMCGPR_TXMULTCOLG_18        (0x40000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos)    /*!< 0x00040000 */
9108 #define ETH_MMCTXMCGPR_TXMULTCOLG_19        (0x80000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos)    /*!< 0x00080000 */
9109 #define ETH_MMCTXMCGPR_TXMULTCOLG_20        (0x100000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos)   /*!< 0x00100000 */
9110 #define ETH_MMCTXMCGPR_TXMULTCOLG_21        (0x200000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos)   /*!< 0x00200000 */
9111 #define ETH_MMCTXMCGPR_TXMULTCOLG_22        (0x400000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos)   /*!< 0x00400000 */
9112 #define ETH_MMCTXMCGPR_TXMULTCOLG_23        (0x800000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos)   /*!< 0x00800000 */
9113 #define ETH_MMCTXMCGPR_TXMULTCOLG_24        (0x1000000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos)  /*!< 0x01000000 */
9114 #define ETH_MMCTXMCGPR_TXMULTCOLG_25        (0x2000000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos)  /*!< 0x02000000 */
9115 #define ETH_MMCTXMCGPR_TXMULTCOLG_26        (0x4000000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos)  /*!< 0x04000000 */
9116 #define ETH_MMCTXMCGPR_TXMULTCOLG_27        (0x8000000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos)  /*!< 0x08000000 */
9117 #define ETH_MMCTXMCGPR_TXMULTCOLG_28        (0x10000000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x10000000 */
9118 #define ETH_MMCTXMCGPR_TXMULTCOLG_29        (0x20000000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x20000000 */
9119 #define ETH_MMCTXMCGPR_TXMULTCOLG_30        (0x40000000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x40000000 */
9120 #define ETH_MMCTXMCGPR_TXMULTCOLG_31        (0x80000000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x80000000 */
9121 
9122 /************  Bit definition for ETH_MMC_TX_PACKET_COUNT_GOOD register  *************/
9123 #define ETH_MMCTXPCGR_TXPKTG_Pos            (0U)
9124 #define ETH_MMCTXPCGR_TXPKTG_Msk            (0xFFFFFFFFU << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0xFFFFFFFF */
9125 #define ETH_MMCTXPCGR_TXPKTG                ETH_MMCTXPCGR_TXPKTG_Msk                  /*!< Tx Packet Count Good */
9126 #define ETH_MMCTXPCGR_TXPKTG_0              (0x1U << ETH_MMCTXPCGR_TXPKTG_Pos)        /*!< 0x00000001 */
9127 #define ETH_MMCTXPCGR_TXPKTG_1              (0x2U << ETH_MMCTXPCGR_TXPKTG_Pos)        /*!< 0x00000002 */
9128 #define ETH_MMCTXPCGR_TXPKTG_2              (0x4U << ETH_MMCTXPCGR_TXPKTG_Pos)        /*!< 0x00000004 */
9129 #define ETH_MMCTXPCGR_TXPKTG_3              (0x8U << ETH_MMCTXPCGR_TXPKTG_Pos)        /*!< 0x00000008 */
9130 #define ETH_MMCTXPCGR_TXPKTG_4              (0x10U << ETH_MMCTXPCGR_TXPKTG_Pos)       /*!< 0x00000010 */
9131 #define ETH_MMCTXPCGR_TXPKTG_5              (0x20U << ETH_MMCTXPCGR_TXPKTG_Pos)       /*!< 0x00000020 */
9132 #define ETH_MMCTXPCGR_TXPKTG_6              (0x40U << ETH_MMCTXPCGR_TXPKTG_Pos)       /*!< 0x00000040 */
9133 #define ETH_MMCTXPCGR_TXPKTG_7              (0x80U << ETH_MMCTXPCGR_TXPKTG_Pos)       /*!< 0x00000080 */
9134 #define ETH_MMCTXPCGR_TXPKTG_8              (0x100U << ETH_MMCTXPCGR_TXPKTG_Pos)      /*!< 0x00000100 */
9135 #define ETH_MMCTXPCGR_TXPKTG_9              (0x200U << ETH_MMCTXPCGR_TXPKTG_Pos)      /*!< 0x00000200 */
9136 #define ETH_MMCTXPCGR_TXPKTG_10             (0x400U << ETH_MMCTXPCGR_TXPKTG_Pos)      /*!< 0x00000400 */
9137 #define ETH_MMCTXPCGR_TXPKTG_11             (0x800U << ETH_MMCTXPCGR_TXPKTG_Pos)      /*!< 0x00000800 */
9138 #define ETH_MMCTXPCGR_TXPKTG_12             (0x1000U << ETH_MMCTXPCGR_TXPKTG_Pos)     /*!< 0x00001000 */
9139 #define ETH_MMCTXPCGR_TXPKTG_13             (0x2000U << ETH_MMCTXPCGR_TXPKTG_Pos)     /*!< 0x00002000 */
9140 #define ETH_MMCTXPCGR_TXPKTG_14             (0x4000U << ETH_MMCTXPCGR_TXPKTG_Pos)     /*!< 0x00004000 */
9141 #define ETH_MMCTXPCGR_TXPKTG_15             (0x8000U << ETH_MMCTXPCGR_TXPKTG_Pos)     /*!< 0x00008000 */
9142 #define ETH_MMCTXPCGR_TXPKTG_16             (0x10000U << ETH_MMCTXPCGR_TXPKTG_Pos)    /*!< 0x00010000 */
9143 #define ETH_MMCTXPCGR_TXPKTG_17             (0x20000U << ETH_MMCTXPCGR_TXPKTG_Pos)    /*!< 0x00020000 */
9144 #define ETH_MMCTXPCGR_TXPKTG_18             (0x40000U << ETH_MMCTXPCGR_TXPKTG_Pos)    /*!< 0x00040000 */
9145 #define ETH_MMCTXPCGR_TXPKTG_19             (0x80000U << ETH_MMCTXPCGR_TXPKTG_Pos)    /*!< 0x00080000 */
9146 #define ETH_MMCTXPCGR_TXPKTG_20             (0x100000U << ETH_MMCTXPCGR_TXPKTG_Pos)   /*!< 0x00100000 */
9147 #define ETH_MMCTXPCGR_TXPKTG_21             (0x200000U << ETH_MMCTXPCGR_TXPKTG_Pos)   /*!< 0x00200000 */
9148 #define ETH_MMCTXPCGR_TXPKTG_22             (0x400000U << ETH_MMCTXPCGR_TXPKTG_Pos)   /*!< 0x00400000 */
9149 #define ETH_MMCTXPCGR_TXPKTG_23             (0x800000U << ETH_MMCTXPCGR_TXPKTG_Pos)   /*!< 0x00800000 */
9150 #define ETH_MMCTXPCGR_TXPKTG_24             (0x1000000U << ETH_MMCTXPCGR_TXPKTG_Pos)  /*!< 0x01000000 */
9151 #define ETH_MMCTXPCGR_TXPKTG_25             (0x2000000U << ETH_MMCTXPCGR_TXPKTG_Pos)  /*!< 0x02000000 */
9152 #define ETH_MMCTXPCGR_TXPKTG_26             (0x4000000U << ETH_MMCTXPCGR_TXPKTG_Pos)  /*!< 0x04000000 */
9153 #define ETH_MMCTXPCGR_TXPKTG_27             (0x8000000U << ETH_MMCTXPCGR_TXPKTG_Pos)  /*!< 0x08000000 */
9154 #define ETH_MMCTXPCGR_TXPKTG_28             (0x10000000U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x10000000 */
9155 #define ETH_MMCTXPCGR_TXPKTG_29             (0x20000000U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x20000000 */
9156 #define ETH_MMCTXPCGR_TXPKTG_30             (0x40000000U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x40000000 */
9157 #define ETH_MMCTXPCGR_TXPKTG_31             (0x80000000U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x80000000 */
9158 
9159 /***********  Bit definition for ETH_MMC_RX_CRC_ERROR_PACKETS register  ***********/
9160 #define ETH_MMCRXCRCEPR_RXCRCERR_Pos        (0U)
9161 #define ETH_MMCRXCRCEPR_RXCRCERR_Msk        (0xFFFFFFFFU << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0xFFFFFFFF */
9162 #define ETH_MMCRXCRCEPR_RXCRCERR            ETH_MMCRXCRCEPR_RXCRCERR_Msk                  /*!< Rx CRC Error Packets */
9163 #define ETH_MMCRXCRCEPR_RXCRCERR_0          (0x1U << ETH_MMCRXCRCEPR_RXCRCERR_Pos)        /*!< 0x00000001 */
9164 #define ETH_MMCRXCRCEPR_RXCRCERR_1          (0x2U << ETH_MMCRXCRCEPR_RXCRCERR_Pos)        /*!< 0x00000002 */
9165 #define ETH_MMCRXCRCEPR_RXCRCERR_2          (0x4U << ETH_MMCRXCRCEPR_RXCRCERR_Pos)        /*!< 0x00000004 */
9166 #define ETH_MMCRXCRCEPR_RXCRCERR_3          (0x8U << ETH_MMCRXCRCEPR_RXCRCERR_Pos)        /*!< 0x00000008 */
9167 #define ETH_MMCRXCRCEPR_RXCRCERR_4          (0x10U << ETH_MMCRXCRCEPR_RXCRCERR_Pos)       /*!< 0x00000010 */
9168 #define ETH_MMCRXCRCEPR_RXCRCERR_5          (0x20U << ETH_MMCRXCRCEPR_RXCRCERR_Pos)       /*!< 0x00000020 */
9169 #define ETH_MMCRXCRCEPR_RXCRCERR_6          (0x40U << ETH_MMCRXCRCEPR_RXCRCERR_Pos)       /*!< 0x00000040 */
9170 #define ETH_MMCRXCRCEPR_RXCRCERR_7          (0x80U << ETH_MMCRXCRCEPR_RXCRCERR_Pos)       /*!< 0x00000080 */
9171 #define ETH_MMCRXCRCEPR_RXCRCERR_8          (0x100U << ETH_MMCRXCRCEPR_RXCRCERR_Pos)      /*!< 0x00000100 */
9172 #define ETH_MMCRXCRCEPR_RXCRCERR_9          (0x200U << ETH_MMCRXCRCEPR_RXCRCERR_Pos)      /*!< 0x00000200 */
9173 #define ETH_MMCRXCRCEPR_RXCRCERR_10         (0x400U << ETH_MMCRXCRCEPR_RXCRCERR_Pos)      /*!< 0x00000400 */
9174 #define ETH_MMCRXCRCEPR_RXCRCERR_11         (0x800U << ETH_MMCRXCRCEPR_RXCRCERR_Pos)      /*!< 0x00000800 */
9175 #define ETH_MMCRXCRCEPR_RXCRCERR_12         (0x1000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos)     /*!< 0x00001000 */
9176 #define ETH_MMCRXCRCEPR_RXCRCERR_13         (0x2000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos)     /*!< 0x00002000 */
9177 #define ETH_MMCRXCRCEPR_RXCRCERR_14         (0x4000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos)     /*!< 0x00004000 */
9178 #define ETH_MMCRXCRCEPR_RXCRCERR_15         (0x8000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos)     /*!< 0x00008000 */
9179 #define ETH_MMCRXCRCEPR_RXCRCERR_16         (0x10000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos)    /*!< 0x00010000 */
9180 #define ETH_MMCRXCRCEPR_RXCRCERR_17         (0x20000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos)    /*!< 0x00020000 */
9181 #define ETH_MMCRXCRCEPR_RXCRCERR_18         (0x40000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos)    /*!< 0x00040000 */
9182 #define ETH_MMCRXCRCEPR_RXCRCERR_19         (0x80000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos)    /*!< 0x00080000 */
9183 #define ETH_MMCRXCRCEPR_RXCRCERR_20         (0x100000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos)   /*!< 0x00100000 */
9184 #define ETH_MMCRXCRCEPR_RXCRCERR_21         (0x200000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos)   /*!< 0x00200000 */
9185 #define ETH_MMCRXCRCEPR_RXCRCERR_22         (0x400000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos)   /*!< 0x00400000 */
9186 #define ETH_MMCRXCRCEPR_RXCRCERR_23         (0x800000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos)   /*!< 0x00800000 */
9187 #define ETH_MMCRXCRCEPR_RXCRCERR_24         (0x1000000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos)  /*!< 0x01000000 */
9188 #define ETH_MMCRXCRCEPR_RXCRCERR_25         (0x2000000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos)  /*!< 0x02000000 */
9189 #define ETH_MMCRXCRCEPR_RXCRCERR_26         (0x4000000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos)  /*!< 0x04000000 */
9190 #define ETH_MMCRXCRCEPR_RXCRCERR_27         (0x8000000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos)  /*!< 0x08000000 */
9191 #define ETH_MMCRXCRCEPR_RXCRCERR_28         (0x10000000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x10000000 */
9192 #define ETH_MMCRXCRCEPR_RXCRCERR_29         (0x20000000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x20000000 */
9193 #define ETH_MMCRXCRCEPR_RXCRCERR_30         (0x40000000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x40000000 */
9194 #define ETH_MMCRXCRCEPR_RXCRCERR_31         (0x80000000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x80000000 */
9195 
9196 /***********  Bit definition for ETH_MMC_RX_ALIGNMENT_ERROR_PACKETS register  ***********/
9197 #define ETH_MMCRXAEPR_RXALGNERR_Pos         (0U)
9198 #define ETH_MMCRXAEPR_RXALGNERR_Msk         (0xFFFFFFFFU << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0xFFFFFFFF */
9199 #define ETH_MMCRXAEPR_RXALGNERR             ETH_MMCRXAEPR_RXALGNERR_Msk                  /*!< Rx Alignment Error Packets */
9200 #define ETH_MMCRXAEPR_RXALGNERR_0           (0x1U << ETH_MMCRXAEPR_RXALGNERR_Pos)        /*!< 0x00000001 */
9201 #define ETH_MMCRXAEPR_RXALGNERR_1           (0x2U << ETH_MMCRXAEPR_RXALGNERR_Pos)        /*!< 0x00000002 */
9202 #define ETH_MMCRXAEPR_RXALGNERR_2           (0x4U << ETH_MMCRXAEPR_RXALGNERR_Pos)        /*!< 0x00000004 */
9203 #define ETH_MMCRXAEPR_RXALGNERR_3           (0x8U << ETH_MMCRXAEPR_RXALGNERR_Pos)        /*!< 0x00000008 */
9204 #define ETH_MMCRXAEPR_RXALGNERR_4           (0x10U << ETH_MMCRXAEPR_RXALGNERR_Pos)       /*!< 0x00000010 */
9205 #define ETH_MMCRXAEPR_RXALGNERR_5           (0x20U << ETH_MMCRXAEPR_RXALGNERR_Pos)       /*!< 0x00000020 */
9206 #define ETH_MMCRXAEPR_RXALGNERR_6           (0x40U << ETH_MMCRXAEPR_RXALGNERR_Pos)       /*!< 0x00000040 */
9207 #define ETH_MMCRXAEPR_RXALGNERR_7           (0x80U << ETH_MMCRXAEPR_RXALGNERR_Pos)       /*!< 0x00000080 */
9208 #define ETH_MMCRXAEPR_RXALGNERR_8           (0x100U << ETH_MMCRXAEPR_RXALGNERR_Pos)      /*!< 0x00000100 */
9209 #define ETH_MMCRXAEPR_RXALGNERR_9           (0x200U << ETH_MMCRXAEPR_RXALGNERR_Pos)      /*!< 0x00000200 */
9210 #define ETH_MMCRXAEPR_RXALGNERR_10          (0x400U << ETH_MMCRXAEPR_RXALGNERR_Pos)      /*!< 0x00000400 */
9211 #define ETH_MMCRXAEPR_RXALGNERR_11          (0x800U << ETH_MMCRXAEPR_RXALGNERR_Pos)      /*!< 0x00000800 */
9212 #define ETH_MMCRXAEPR_RXALGNERR_12          (0x1000U << ETH_MMCRXAEPR_RXALGNERR_Pos)     /*!< 0x00001000 */
9213 #define ETH_MMCRXAEPR_RXALGNERR_13          (0x2000U << ETH_MMCRXAEPR_RXALGNERR_Pos)     /*!< 0x00002000 */
9214 #define ETH_MMCRXAEPR_RXALGNERR_14          (0x4000U << ETH_MMCRXAEPR_RXALGNERR_Pos)     /*!< 0x00004000 */
9215 #define ETH_MMCRXAEPR_RXALGNERR_15          (0x8000U << ETH_MMCRXAEPR_RXALGNERR_Pos)     /*!< 0x00008000 */
9216 #define ETH_MMCRXAEPR_RXALGNERR_16          (0x10000U << ETH_MMCRXAEPR_RXALGNERR_Pos)    /*!< 0x00010000 */
9217 #define ETH_MMCRXAEPR_RXALGNERR_17          (0x20000U << ETH_MMCRXAEPR_RXALGNERR_Pos)    /*!< 0x00020000 */
9218 #define ETH_MMCRXAEPR_RXALGNERR_18          (0x40000U << ETH_MMCRXAEPR_RXALGNERR_Pos)    /*!< 0x00040000 */
9219 #define ETH_MMCRXAEPR_RXALGNERR_19          (0x80000U << ETH_MMCRXAEPR_RXALGNERR_Pos)    /*!< 0x00080000 */
9220 #define ETH_MMCRXAEPR_RXALGNERR_20          (0x100000U << ETH_MMCRXAEPR_RXALGNERR_Pos)   /*!< 0x00100000 */
9221 #define ETH_MMCRXAEPR_RXALGNERR_21          (0x200000U << ETH_MMCRXAEPR_RXALGNERR_Pos)   /*!< 0x00200000 */
9222 #define ETH_MMCRXAEPR_RXALGNERR_22          (0x400000U << ETH_MMCRXAEPR_RXALGNERR_Pos)   /*!< 0x00400000 */
9223 #define ETH_MMCRXAEPR_RXALGNERR_23          (0x800000U << ETH_MMCRXAEPR_RXALGNERR_Pos)   /*!< 0x00800000 */
9224 #define ETH_MMCRXAEPR_RXALGNERR_24          (0x1000000U << ETH_MMCRXAEPR_RXALGNERR_Pos)  /*!< 0x01000000 */
9225 #define ETH_MMCRXAEPR_RXALGNERR_25          (0x2000000U << ETH_MMCRXAEPR_RXALGNERR_Pos)  /*!< 0x02000000 */
9226 #define ETH_MMCRXAEPR_RXALGNERR_26          (0x4000000U << ETH_MMCRXAEPR_RXALGNERR_Pos)  /*!< 0x04000000 */
9227 #define ETH_MMCRXAEPR_RXALGNERR_27          (0x8000000U << ETH_MMCRXAEPR_RXALGNERR_Pos)  /*!< 0x08000000 */
9228 #define ETH_MMCRXAEPR_RXALGNERR_28          (0x10000000U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x10000000 */
9229 #define ETH_MMCRXAEPR_RXALGNERR_29          (0x20000000U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x20000000 */
9230 #define ETH_MMCRXAEPR_RXALGNERR_30          (0x40000000U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x40000000 */
9231 #define ETH_MMCRXAEPR_RXALGNERR_31          (0x80000000U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x80000000 */
9232 
9233 /***********  Bit definition for ETH_MMC_RX_UNICAST_PACKETS_GOOD register  ************/
9234 #define ETH_MMCRXUPGR_RXUCASTG_Pos          (0U)
9235 #define ETH_MMCRXUPGR_RXUCASTG_Msk          (0xFFFFFFFFU << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0xFFFFFFFF */
9236 #define ETH_MMCRXUPGR_RXUCASTG              ETH_MMCRXUPGR_RXUCASTG_Msk                  /*!< Rx Unicast Packets Good */
9237 #define ETH_MMCRXUPGR_RXUCASTG_0            (0x1U << ETH_MMCRXUPGR_RXUCASTG_Pos)        /*!< 0x00000001 */
9238 #define ETH_MMCRXUPGR_RXUCASTG_1            (0x2U << ETH_MMCRXUPGR_RXUCASTG_Pos)        /*!< 0x00000002 */
9239 #define ETH_MMCRXUPGR_RXUCASTG_2            (0x4U << ETH_MMCRXUPGR_RXUCASTG_Pos)        /*!< 0x00000004 */
9240 #define ETH_MMCRXUPGR_RXUCASTG_3            (0x8U << ETH_MMCRXUPGR_RXUCASTG_Pos)        /*!< 0x00000008 */
9241 #define ETH_MMCRXUPGR_RXUCASTG_4            (0x10U << ETH_MMCRXUPGR_RXUCASTG_Pos)       /*!< 0x00000010 */
9242 #define ETH_MMCRXUPGR_RXUCASTG_5            (0x20U << ETH_MMCRXUPGR_RXUCASTG_Pos)       /*!< 0x00000020 */
9243 #define ETH_MMCRXUPGR_RXUCASTG_6            (0x40U << ETH_MMCRXUPGR_RXUCASTG_Pos)       /*!< 0x00000040 */
9244 #define ETH_MMCRXUPGR_RXUCASTG_7            (0x80U << ETH_MMCRXUPGR_RXUCASTG_Pos)       /*!< 0x00000080 */
9245 #define ETH_MMCRXUPGR_RXUCASTG_8            (0x100U << ETH_MMCRXUPGR_RXUCASTG_Pos)      /*!< 0x00000100 */
9246 #define ETH_MMCRXUPGR_RXUCASTG_9            (0x200U << ETH_MMCRXUPGR_RXUCASTG_Pos)      /*!< 0x00000200 */
9247 #define ETH_MMCRXUPGR_RXUCASTG_10           (0x400U << ETH_MMCRXUPGR_RXUCASTG_Pos)      /*!< 0x00000400 */
9248 #define ETH_MMCRXUPGR_RXUCASTG_11           (0x800U << ETH_MMCRXUPGR_RXUCASTG_Pos)      /*!< 0x00000800 */
9249 #define ETH_MMCRXUPGR_RXUCASTG_12           (0x1000U << ETH_MMCRXUPGR_RXUCASTG_Pos)     /*!< 0x00001000 */
9250 #define ETH_MMCRXUPGR_RXUCASTG_13           (0x2000U << ETH_MMCRXUPGR_RXUCASTG_Pos)     /*!< 0x00002000 */
9251 #define ETH_MMCRXUPGR_RXUCASTG_14           (0x4000U << ETH_MMCRXUPGR_RXUCASTG_Pos)     /*!< 0x00004000 */
9252 #define ETH_MMCRXUPGR_RXUCASTG_15           (0x8000U << ETH_MMCRXUPGR_RXUCASTG_Pos)     /*!< 0x00008000 */
9253 #define ETH_MMCRXUPGR_RXUCASTG_16           (0x10000U << ETH_MMCRXUPGR_RXUCASTG_Pos)    /*!< 0x00010000 */
9254 #define ETH_MMCRXUPGR_RXUCASTG_17           (0x20000U << ETH_MMCRXUPGR_RXUCASTG_Pos)    /*!< 0x00020000 */
9255 #define ETH_MMCRXUPGR_RXUCASTG_18           (0x40000U << ETH_MMCRXUPGR_RXUCASTG_Pos)    /*!< 0x00040000 */
9256 #define ETH_MMCRXUPGR_RXUCASTG_19           (0x80000U << ETH_MMCRXUPGR_RXUCASTG_Pos)    /*!< 0x00080000 */
9257 #define ETH_MMCRXUPGR_RXUCASTG_20           (0x100000U << ETH_MMCRXUPGR_RXUCASTG_Pos)   /*!< 0x00100000 */
9258 #define ETH_MMCRXUPGR_RXUCASTG_21           (0x200000U << ETH_MMCRXUPGR_RXUCASTG_Pos)   /*!< 0x00200000 */
9259 #define ETH_MMCRXUPGR_RXUCASTG_22           (0x400000U << ETH_MMCRXUPGR_RXUCASTG_Pos)   /*!< 0x00400000 */
9260 #define ETH_MMCRXUPGR_RXUCASTG_23           (0x800000U << ETH_MMCRXUPGR_RXUCASTG_Pos)   /*!< 0x00800000 */
9261 #define ETH_MMCRXUPGR_RXUCASTG_24           (0x1000000U << ETH_MMCRXUPGR_RXUCASTG_Pos)  /*!< 0x01000000 */
9262 #define ETH_MMCRXUPGR_RXUCASTG_25           (0x2000000U << ETH_MMCRXUPGR_RXUCASTG_Pos)  /*!< 0x02000000 */
9263 #define ETH_MMCRXUPGR_RXUCASTG_26           (0x4000000U << ETH_MMCRXUPGR_RXUCASTG_Pos)  /*!< 0x04000000 */
9264 #define ETH_MMCRXUPGR_RXUCASTG_27           (0x8000000U << ETH_MMCRXUPGR_RXUCASTG_Pos)  /*!< 0x08000000 */
9265 #define ETH_MMCRXUPGR_RXUCASTG_28           (0x10000000U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x10000000 */
9266 #define ETH_MMCRXUPGR_RXUCASTG_29           (0x20000000U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x20000000 */
9267 #define ETH_MMCRXUPGR_RXUCASTG_30           (0x40000000U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x40000000 */
9268 #define ETH_MMCRXUPGR_RXUCASTG_31           (0x80000000U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x80000000 */
9269 
9270 /*************  Bit definition for ETH_MMC_TX_LPI_USEC_CNTR register  *************/
9271 #define ETH_MMCTXLPIMSTR_TXLPIUSC_Pos       (0U)
9272 #define ETH_MMCTXLPIMSTR_TXLPIUSC_Msk       (0xFFFFFFFFU << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0xFFFFFFFF */
9273 #define ETH_MMCTXLPIMSTR_TXLPIUSC           ETH_MMCTXLPIMSTR_TXLPIUSC_Msk                  /*!< Tx LPI Microseconds Counter */
9274 #define ETH_MMCTXLPIMSTR_TXLPIUSC_0         (0x1U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos)        /*!< 0x00000001 */
9275 #define ETH_MMCTXLPIMSTR_TXLPIUSC_1         (0x2U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos)        /*!< 0x00000002 */
9276 #define ETH_MMCTXLPIMSTR_TXLPIUSC_2         (0x4U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos)        /*!< 0x00000004 */
9277 #define ETH_MMCTXLPIMSTR_TXLPIUSC_3         (0x8U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos)        /*!< 0x00000008 */
9278 #define ETH_MMCTXLPIMSTR_TXLPIUSC_4         (0x10U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos)       /*!< 0x00000010 */
9279 #define ETH_MMCTXLPIMSTR_TXLPIUSC_5         (0x20U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos)       /*!< 0x00000020 */
9280 #define ETH_MMCTXLPIMSTR_TXLPIUSC_6         (0x40U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos)       /*!< 0x00000040 */
9281 #define ETH_MMCTXLPIMSTR_TXLPIUSC_7         (0x80U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos)       /*!< 0x00000080 */
9282 #define ETH_MMCTXLPIMSTR_TXLPIUSC_8         (0x100U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos)      /*!< 0x00000100 */
9283 #define ETH_MMCTXLPIMSTR_TXLPIUSC_9         (0x200U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos)      /*!< 0x00000200 */
9284 #define ETH_MMCTXLPIMSTR_TXLPIUSC_10        (0x400U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos)      /*!< 0x00000400 */
9285 #define ETH_MMCTXLPIMSTR_TXLPIUSC_11        (0x800U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos)      /*!< 0x00000800 */
9286 #define ETH_MMCTXLPIMSTR_TXLPIUSC_12        (0x1000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos)     /*!< 0x00001000 */
9287 #define ETH_MMCTXLPIMSTR_TXLPIUSC_13        (0x2000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos)     /*!< 0x00002000 */
9288 #define ETH_MMCTXLPIMSTR_TXLPIUSC_14        (0x4000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos)     /*!< 0x00004000 */
9289 #define ETH_MMCTXLPIMSTR_TXLPIUSC_15        (0x8000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos)     /*!< 0x00008000 */
9290 #define ETH_MMCTXLPIMSTR_TXLPIUSC_16        (0x10000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos)    /*!< 0x00010000 */
9291 #define ETH_MMCTXLPIMSTR_TXLPIUSC_17        (0x20000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos)    /*!< 0x00020000 */
9292 #define ETH_MMCTXLPIMSTR_TXLPIUSC_18        (0x40000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos)    /*!< 0x00040000 */
9293 #define ETH_MMCTXLPIMSTR_TXLPIUSC_19        (0x80000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos)    /*!< 0x00080000 */
9294 #define ETH_MMCTXLPIMSTR_TXLPIUSC_20        (0x100000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos)   /*!< 0x00100000 */
9295 #define ETH_MMCTXLPIMSTR_TXLPIUSC_21        (0x200000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos)   /*!< 0x00200000 */
9296 #define ETH_MMCTXLPIMSTR_TXLPIUSC_22        (0x400000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos)   /*!< 0x00400000 */
9297 #define ETH_MMCTXLPIMSTR_TXLPIUSC_23        (0x800000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos)   /*!< 0x00800000 */
9298 #define ETH_MMCTXLPIMSTR_TXLPIUSC_24        (0x1000000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos)  /*!< 0x01000000 */
9299 #define ETH_MMCTXLPIMSTR_TXLPIUSC_25        (0x2000000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos)  /*!< 0x02000000 */
9300 #define ETH_MMCTXLPIMSTR_TXLPIUSC_26        (0x4000000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos)  /*!< 0x04000000 */
9301 #define ETH_MMCTXLPIMSTR_TXLPIUSC_27        (0x8000000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos)  /*!< 0x08000000 */
9302 #define ETH_MMCTXLPIMSTR_TXLPIUSC_28        (0x10000000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x10000000 */
9303 #define ETH_MMCTXLPIMSTR_TXLPIUSC_29        (0x20000000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x20000000 */
9304 #define ETH_MMCTXLPIMSTR_TXLPIUSC_30        (0x40000000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x40000000 */
9305 #define ETH_MMCTXLPIMSTR_TXLPIUSC_31        (0x80000000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x80000000 */
9306 
9307 /*************  Bit definition for ETH_MMC_TX_LPI_TRAN_CNTR register  *************/
9308 #define ETH_MMCTXLPITCR_TXLPITRC_Pos        (0U)
9309 #define ETH_MMCTXLPITCR_TXLPITRC_Msk        (0xFFFFFFFFU << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0xFFFFFFFF */
9310 #define ETH_MMCTXLPITCR_TXLPITRC            ETH_MMCTXLPITCR_TXLPITRC_Msk                  /*!< Tx LPI Transition counter */
9311 #define ETH_MMCTXLPITCR_TXLPITRC_0          (0x1U << ETH_MMCTXLPITCR_TXLPITRC_Pos)        /*!< 0x00000001 */
9312 #define ETH_MMCTXLPITCR_TXLPITRC_1          (0x2U << ETH_MMCTXLPITCR_TXLPITRC_Pos)        /*!< 0x00000002 */
9313 #define ETH_MMCTXLPITCR_TXLPITRC_2          (0x4U << ETH_MMCTXLPITCR_TXLPITRC_Pos)        /*!< 0x00000004 */
9314 #define ETH_MMCTXLPITCR_TXLPITRC_3          (0x8U << ETH_MMCTXLPITCR_TXLPITRC_Pos)        /*!< 0x00000008 */
9315 #define ETH_MMCTXLPITCR_TXLPITRC_4          (0x10U << ETH_MMCTXLPITCR_TXLPITRC_Pos)       /*!< 0x00000010 */
9316 #define ETH_MMCTXLPITCR_TXLPITRC_5          (0x20U << ETH_MMCTXLPITCR_TXLPITRC_Pos)       /*!< 0x00000020 */
9317 #define ETH_MMCTXLPITCR_TXLPITRC_6          (0x40U << ETH_MMCTXLPITCR_TXLPITRC_Pos)       /*!< 0x00000040 */
9318 #define ETH_MMCTXLPITCR_TXLPITRC_7          (0x80U << ETH_MMCTXLPITCR_TXLPITRC_Pos)       /*!< 0x00000080 */
9319 #define ETH_MMCTXLPITCR_TXLPITRC_8          (0x100U << ETH_MMCTXLPITCR_TXLPITRC_Pos)      /*!< 0x00000100 */
9320 #define ETH_MMCTXLPITCR_TXLPITRC_9          (0x200U << ETH_MMCTXLPITCR_TXLPITRC_Pos)      /*!< 0x00000200 */
9321 #define ETH_MMCTXLPITCR_TXLPITRC_10         (0x400U << ETH_MMCTXLPITCR_TXLPITRC_Pos)      /*!< 0x00000400 */
9322 #define ETH_MMCTXLPITCR_TXLPITRC_11         (0x800U << ETH_MMCTXLPITCR_TXLPITRC_Pos)      /*!< 0x00000800 */
9323 #define ETH_MMCTXLPITCR_TXLPITRC_12         (0x1000U << ETH_MMCTXLPITCR_TXLPITRC_Pos)     /*!< 0x00001000 */
9324 #define ETH_MMCTXLPITCR_TXLPITRC_13         (0x2000U << ETH_MMCTXLPITCR_TXLPITRC_Pos)     /*!< 0x00002000 */
9325 #define ETH_MMCTXLPITCR_TXLPITRC_14         (0x4000U << ETH_MMCTXLPITCR_TXLPITRC_Pos)     /*!< 0x00004000 */
9326 #define ETH_MMCTXLPITCR_TXLPITRC_15         (0x8000U << ETH_MMCTXLPITCR_TXLPITRC_Pos)     /*!< 0x00008000 */
9327 #define ETH_MMCTXLPITCR_TXLPITRC_16         (0x10000U << ETH_MMCTXLPITCR_TXLPITRC_Pos)    /*!< 0x00010000 */
9328 #define ETH_MMCTXLPITCR_TXLPITRC_17         (0x20000U << ETH_MMCTXLPITCR_TXLPITRC_Pos)    /*!< 0x00020000 */
9329 #define ETH_MMCTXLPITCR_TXLPITRC_18         (0x40000U << ETH_MMCTXLPITCR_TXLPITRC_Pos)    /*!< 0x00040000 */
9330 #define ETH_MMCTXLPITCR_TXLPITRC_19         (0x80000U << ETH_MMCTXLPITCR_TXLPITRC_Pos)    /*!< 0x00080000 */
9331 #define ETH_MMCTXLPITCR_TXLPITRC_20         (0x100000U << ETH_MMCTXLPITCR_TXLPITRC_Pos)   /*!< 0x00100000 */
9332 #define ETH_MMCTXLPITCR_TXLPITRC_21         (0x200000U << ETH_MMCTXLPITCR_TXLPITRC_Pos)   /*!< 0x00200000 */
9333 #define ETH_MMCTXLPITCR_TXLPITRC_22         (0x400000U << ETH_MMCTXLPITCR_TXLPITRC_Pos)   /*!< 0x00400000 */
9334 #define ETH_MMCTXLPITCR_TXLPITRC_23         (0x800000U << ETH_MMCTXLPITCR_TXLPITRC_Pos)   /*!< 0x00800000 */
9335 #define ETH_MMCTXLPITCR_TXLPITRC_24         (0x1000000U << ETH_MMCTXLPITCR_TXLPITRC_Pos)  /*!< 0x01000000 */
9336 #define ETH_MMCTXLPITCR_TXLPITRC_25         (0x2000000U << ETH_MMCTXLPITCR_TXLPITRC_Pos)  /*!< 0x02000000 */
9337 #define ETH_MMCTXLPITCR_TXLPITRC_26         (0x4000000U << ETH_MMCTXLPITCR_TXLPITRC_Pos)  /*!< 0x04000000 */
9338 #define ETH_MMCTXLPITCR_TXLPITRC_27         (0x8000000U << ETH_MMCTXLPITCR_TXLPITRC_Pos)  /*!< 0x08000000 */
9339 #define ETH_MMCTXLPITCR_TXLPITRC_28         (0x10000000U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x10000000 */
9340 #define ETH_MMCTXLPITCR_TXLPITRC_29         (0x20000000U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x20000000 */
9341 #define ETH_MMCTXLPITCR_TXLPITRC_30         (0x40000000U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x40000000 */
9342 #define ETH_MMCTXLPITCR_TXLPITRC_31         (0x80000000U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x80000000 */
9343 
9344 /*************  Bit definition for ETH_MMC_RX_LPI_USEC_CNTR register  *************/
9345 #define ETH_MMCRXLPIMSTR_RXLPIUSC_Pos       (0U)
9346 #define ETH_MMCRXLPIMSTR_RXLPIUSC_Msk       (0xFFFFFFFFU << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0xFFFFFFFF */
9347 #define ETH_MMCRXLPIMSTR_RXLPIUSC           ETH_MMCRXLPIMSTR_RXLPIUSC_Msk                  /*!< Rx LPI Microseconds Counter */
9348 #define ETH_MMCRXLPIMSTR_RXLPIUSC_0         (0x1U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos)        /*!< 0x00000001 */
9349 #define ETH_MMCRXLPIMSTR_RXLPIUSC_1         (0x2U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos)        /*!< 0x00000002 */
9350 #define ETH_MMCRXLPIMSTR_RXLPIUSC_2         (0x4U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos)        /*!< 0x00000004 */
9351 #define ETH_MMCRXLPIMSTR_RXLPIUSC_3         (0x8U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos)        /*!< 0x00000008 */
9352 #define ETH_MMCRXLPIMSTR_RXLPIUSC_4         (0x10U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos)       /*!< 0x00000010 */
9353 #define ETH_MMCRXLPIMSTR_RXLPIUSC_5         (0x20U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos)       /*!< 0x00000020 */
9354 #define ETH_MMCRXLPIMSTR_RXLPIUSC_6         (0x40U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos)       /*!< 0x00000040 */
9355 #define ETH_MMCRXLPIMSTR_RXLPIUSC_7         (0x80U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos)       /*!< 0x00000080 */
9356 #define ETH_MMCRXLPIMSTR_RXLPIUSC_8         (0x100U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos)      /*!< 0x00000100 */
9357 #define ETH_MMCRXLPIMSTR_RXLPIUSC_9         (0x200U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos)      /*!< 0x00000200 */
9358 #define ETH_MMCRXLPIMSTR_RXLPIUSC_10        (0x400U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos)      /*!< 0x00000400 */
9359 #define ETH_MMCRXLPIMSTR_RXLPIUSC_11        (0x800U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos)      /*!< 0x00000800 */
9360 #define ETH_MMCRXLPIMSTR_RXLPIUSC_12        (0x1000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos)     /*!< 0x00001000 */
9361 #define ETH_MMCRXLPIMSTR_RXLPIUSC_13        (0x2000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos)     /*!< 0x00002000 */
9362 #define ETH_MMCRXLPIMSTR_RXLPIUSC_14        (0x4000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos)     /*!< 0x00004000 */
9363 #define ETH_MMCRXLPIMSTR_RXLPIUSC_15        (0x8000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos)     /*!< 0x00008000 */
9364 #define ETH_MMCRXLPIMSTR_RXLPIUSC_16        (0x10000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos)    /*!< 0x00010000 */
9365 #define ETH_MMCRXLPIMSTR_RXLPIUSC_17        (0x20000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos)    /*!< 0x00020000 */
9366 #define ETH_MMCRXLPIMSTR_RXLPIUSC_18        (0x40000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos)    /*!< 0x00040000 */
9367 #define ETH_MMCRXLPIMSTR_RXLPIUSC_19        (0x80000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos)    /*!< 0x00080000 */
9368 #define ETH_MMCRXLPIMSTR_RXLPIUSC_20        (0x100000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos)   /*!< 0x00100000 */
9369 #define ETH_MMCRXLPIMSTR_RXLPIUSC_21        (0x200000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos)   /*!< 0x00200000 */
9370 #define ETH_MMCRXLPIMSTR_RXLPIUSC_22        (0x400000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos)   /*!< 0x00400000 */
9371 #define ETH_MMCRXLPIMSTR_RXLPIUSC_23        (0x800000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos)   /*!< 0x00800000 */
9372 #define ETH_MMCRXLPIMSTR_RXLPIUSC_24        (0x1000000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos)  /*!< 0x01000000 */
9373 #define ETH_MMCRXLPIMSTR_RXLPIUSC_25        (0x2000000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos)  /*!< 0x02000000 */
9374 #define ETH_MMCRXLPIMSTR_RXLPIUSC_26        (0x4000000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos)  /*!< 0x04000000 */
9375 #define ETH_MMCRXLPIMSTR_RXLPIUSC_27        (0x8000000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos)  /*!< 0x08000000 */
9376 #define ETH_MMCRXLPIMSTR_RXLPIUSC_28        (0x10000000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x10000000 */
9377 #define ETH_MMCRXLPIMSTR_RXLPIUSC_29        (0x20000000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x20000000 */
9378 #define ETH_MMCRXLPIMSTR_RXLPIUSC_30        (0x40000000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x40000000 */
9379 #define ETH_MMCRXLPIMSTR_RXLPIUSC_31        (0x80000000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x80000000 */
9380 
9381 /*************  Bit definition for ETH_MMC_RX_LPI_TRAN_CNTR register  *************/
9382 #define ETH_MMCRXLPITCR_RXLPITRC_Pos        (0U)
9383 #define ETH_MMCRXLPITCR_RXLPITRC_Msk        (0xFFFFFFFFU << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0xFFFFFFFF */
9384 #define ETH_MMCRXLPITCR_RXLPITRC            ETH_MMCRXLPITCR_RXLPITRC_Msk                  /*!< Rx LPI Transition counter */
9385 #define ETH_MMCRXLPITCR_RXLPITRC_0          (0x1U << ETH_MMCRXLPITCR_RXLPITRC_Pos)        /*!< 0x00000001 */
9386 #define ETH_MMCRXLPITCR_RXLPITRC_1          (0x2U << ETH_MMCRXLPITCR_RXLPITRC_Pos)        /*!< 0x00000002 */
9387 #define ETH_MMCRXLPITCR_RXLPITRC_2          (0x4U << ETH_MMCRXLPITCR_RXLPITRC_Pos)        /*!< 0x00000004 */
9388 #define ETH_MMCRXLPITCR_RXLPITRC_3          (0x8U << ETH_MMCRXLPITCR_RXLPITRC_Pos)        /*!< 0x00000008 */
9389 #define ETH_MMCRXLPITCR_RXLPITRC_4          (0x10U << ETH_MMCRXLPITCR_RXLPITRC_Pos)       /*!< 0x00000010 */
9390 #define ETH_MMCRXLPITCR_RXLPITRC_5          (0x20U << ETH_MMCRXLPITCR_RXLPITRC_Pos)       /*!< 0x00000020 */
9391 #define ETH_MMCRXLPITCR_RXLPITRC_6          (0x40U << ETH_MMCRXLPITCR_RXLPITRC_Pos)       /*!< 0x00000040 */
9392 #define ETH_MMCRXLPITCR_RXLPITRC_7          (0x80U << ETH_MMCRXLPITCR_RXLPITRC_Pos)       /*!< 0x00000080 */
9393 #define ETH_MMCRXLPITCR_RXLPITRC_8          (0x100U << ETH_MMCRXLPITCR_RXLPITRC_Pos)      /*!< 0x00000100 */
9394 #define ETH_MMCRXLPITCR_RXLPITRC_9          (0x200U << ETH_MMCRXLPITCR_RXLPITRC_Pos)      /*!< 0x00000200 */
9395 #define ETH_MMCRXLPITCR_RXLPITRC_10         (0x400U << ETH_MMCRXLPITCR_RXLPITRC_Pos)      /*!< 0x00000400 */
9396 #define ETH_MMCRXLPITCR_RXLPITRC_11         (0x800U << ETH_MMCRXLPITCR_RXLPITRC_Pos)      /*!< 0x00000800 */
9397 #define ETH_MMCRXLPITCR_RXLPITRC_12         (0x1000U << ETH_MMCRXLPITCR_RXLPITRC_Pos)     /*!< 0x00001000 */
9398 #define ETH_MMCRXLPITCR_RXLPITRC_13         (0x2000U << ETH_MMCRXLPITCR_RXLPITRC_Pos)     /*!< 0x00002000 */
9399 #define ETH_MMCRXLPITCR_RXLPITRC_14         (0x4000U << ETH_MMCRXLPITCR_RXLPITRC_Pos)     /*!< 0x00004000 */
9400 #define ETH_MMCRXLPITCR_RXLPITRC_15         (0x8000U << ETH_MMCRXLPITCR_RXLPITRC_Pos)     /*!< 0x00008000 */
9401 #define ETH_MMCRXLPITCR_RXLPITRC_16         (0x10000U << ETH_MMCRXLPITCR_RXLPITRC_Pos)    /*!< 0x00010000 */
9402 #define ETH_MMCRXLPITCR_RXLPITRC_17         (0x20000U << ETH_MMCRXLPITCR_RXLPITRC_Pos)    /*!< 0x00020000 */
9403 #define ETH_MMCRXLPITCR_RXLPITRC_18         (0x40000U << ETH_MMCRXLPITCR_RXLPITRC_Pos)    /*!< 0x00040000 */
9404 #define ETH_MMCRXLPITCR_RXLPITRC_19         (0x80000U << ETH_MMCRXLPITCR_RXLPITRC_Pos)    /*!< 0x00080000 */
9405 #define ETH_MMCRXLPITCR_RXLPITRC_20         (0x100000U << ETH_MMCRXLPITCR_RXLPITRC_Pos)   /*!< 0x00100000 */
9406 #define ETH_MMCRXLPITCR_RXLPITRC_21         (0x200000U << ETH_MMCRXLPITCR_RXLPITRC_Pos)   /*!< 0x00200000 */
9407 #define ETH_MMCRXLPITCR_RXLPITRC_22         (0x400000U << ETH_MMCRXLPITCR_RXLPITRC_Pos)   /*!< 0x00400000 */
9408 #define ETH_MMCRXLPITCR_RXLPITRC_23         (0x800000U << ETH_MMCRXLPITCR_RXLPITRC_Pos)   /*!< 0x00800000 */
9409 #define ETH_MMCRXLPITCR_RXLPITRC_24         (0x1000000U << ETH_MMCRXLPITCR_RXLPITRC_Pos)  /*!< 0x01000000 */
9410 #define ETH_MMCRXLPITCR_RXLPITRC_25         (0x2000000U << ETH_MMCRXLPITCR_RXLPITRC_Pos)  /*!< 0x02000000 */
9411 #define ETH_MMCRXLPITCR_RXLPITRC_26         (0x4000000U << ETH_MMCRXLPITCR_RXLPITRC_Pos)  /*!< 0x04000000 */
9412 #define ETH_MMCRXLPITCR_RXLPITRC_27         (0x8000000U << ETH_MMCRXLPITCR_RXLPITRC_Pos)  /*!< 0x08000000 */
9413 #define ETH_MMCRXLPITCR_RXLPITRC_28         (0x10000000U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x10000000 */
9414 #define ETH_MMCRXLPITCR_RXLPITRC_29         (0x20000000U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x20000000 */
9415 #define ETH_MMCRXLPITCR_RXLPITRC_30         (0x40000000U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x40000000 */
9416 #define ETH_MMCRXLPITCR_RXLPITRC_31         (0x80000000U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x80000000 */
9417 
9418 /************  Bit definition for ETH_MACL3L4C0R register  *************/
9419 #define ETH_MACL3L4C0R_L3PEN0_Pos           (0U)
9420 #define ETH_MACL3L4C0R_L3PEN0_Msk           (0x1U << ETH_MACL3L4C0R_L3PEN0_Pos)                 /*!< 0x00000001 */
9421 #define ETH_MACL3L4C0R_L3PEN0               ETH_MACL3L4C0R_L3PEN0_Msk                           /*!< Layer 3 Protocol Enable */
9422 #define ETH_MACL3L4C0R_L3SAM0_Pos           (2U)
9423 #define ETH_MACL3L4C0R_L3SAM0_Msk           (0x1U << ETH_MACL3L4C0R_L3SAM0_Pos)                 /*!< 0x00000004 */
9424 #define ETH_MACL3L4C0R_L3SAM0               ETH_MACL3L4C0R_L3SAM0_Msk                           /*!< Layer 3 IP SA Match Enable */
9425 #define ETH_MACL3L4C0R_L3SAIM0_Pos          (3U)
9426 #define ETH_MACL3L4C0R_L3SAIM0_Msk          (0x1U << ETH_MACL3L4C0R_L3SAIM0_Pos)                /*!< 0x00000008 */
9427 #define ETH_MACL3L4C0R_L3SAIM0              ETH_MACL3L4C0R_L3SAIM0_Msk                          /*!< Layer 3 IP SA Inverse Match Enable */
9428 #define ETH_MACL3L4C0R_L3DAM0_Pos           (4U)
9429 #define ETH_MACL3L4C0R_L3DAM0_Msk           (0x1U << ETH_MACL3L4C0R_L3DAM0_Pos)                 /*!< 0x00000010 */
9430 #define ETH_MACL3L4C0R_L3DAM0               ETH_MACL3L4C0R_L3DAM0_Msk                           /*!< Layer 3 IP DA Match Enable */
9431 #define ETH_MACL3L4C0R_L3DAIM0_Pos          (5U)
9432 #define ETH_MACL3L4C0R_L3DAIM0_Msk          (0x1U << ETH_MACL3L4C0R_L3DAIM0_Pos)                /*!< 0x00000020 */
9433 #define ETH_MACL3L4C0R_L3DAIM0              ETH_MACL3L4C0R_L3DAIM0_Msk                          /*!< Layer 3 IP DA Inverse Match Enable */
9434 #define ETH_MACL3L4C0R_L3HSBM0_Pos          (6U)
9435 #define ETH_MACL3L4C0R_L3HSBM0_Msk          (0x1FU << ETH_MACL3L4C0R_L3HSBM0_Pos)               /*!< 0x000007C0 */
9436 #define ETH_MACL3L4C0R_L3HSBM0              ETH_MACL3L4C0R_L3HSBM0_Msk                          /*!< Layer 3 IP SA Higher Bits Match */
9437 #define ETH_MACL3L4C0R_L3HSBM0_0            (0x1U << ETH_MACL3L4C0R_L3HSBM0_Pos)               /*!< 0x00000040 */
9438 #define ETH_MACL3L4C0R_L3HSBM0_1            (0x2U << ETH_MACL3L4C0R_L3HSBM0_Pos)               /*!< 0x00000080 */
9439 #define ETH_MACL3L4C0R_L3HSBM0_2            (0x4U << ETH_MACL3L4C0R_L3HSBM0_Pos)              /*!< 0x00000100 */
9440 #define ETH_MACL3L4C0R_L3HSBM0_3            (0x8U << ETH_MACL3L4C0R_L3HSBM0_Pos)              /*!< 0x00000200 */
9441 #define ETH_MACL3L4C0R_L3HSBM0_4            (0x10U << ETH_MACL3L4C0R_L3HSBM0_Pos)              /*!< 0x00000400 */
9442 #define ETH_MACL3L4C0R_L3HDBM0_Pos          (11U)
9443 #define ETH_MACL3L4C0R_L3HDBM0_Msk          (0x1FU << ETH_MACL3L4C0R_L3HDBM0_Pos)               /*!< 0x0000F800 */
9444 #define ETH_MACL3L4C0R_L3HDBM0              ETH_MACL3L4C0R_L3HDBM0_Msk                          /*!< Layer 3 IP DA Higher Bits Match */
9445 #define ETH_MACL3L4C0R_L3HDBM0_0            (0x1U << ETH_MACL3L4C0R_L3HDBM0_Pos)              /*!< 0x00000800 */
9446 #define ETH_MACL3L4C0R_L3HDBM0_1            (0x2U << ETH_MACL3L4C0R_L3HDBM0_Pos)             /*!< 0x00001000 */
9447 #define ETH_MACL3L4C0R_L3HDBM0_2            (0x4U << ETH_MACL3L4C0R_L3HDBM0_Pos)             /*!< 0x00002000 */
9448 #define ETH_MACL3L4C0R_L3HDBM0_3            (0x8U << ETH_MACL3L4C0R_L3HDBM0_Pos)             /*!< 0x00004000 */
9449 #define ETH_MACL3L4C0R_L3HDBM0_4            (0x10U << ETH_MACL3L4C0R_L3HDBM0_Pos)             /*!< 0x00008000 */
9450 #define ETH_MACL3L4C0R_L4PEN0_Pos           (16U)
9451 #define ETH_MACL3L4C0R_L4PEN0_Msk           (0x1U << ETH_MACL3L4C0R_L4PEN0_Pos)                 /*!< 0x00010000 */
9452 #define ETH_MACL3L4C0R_L4PEN0               ETH_MACL3L4C0R_L4PEN0_Msk                           /*!< Layer 4 Protocol Enable */
9453 #define ETH_MACL3L4C0R_L4SPM0_Pos           (18U)
9454 #define ETH_MACL3L4C0R_L4SPM0_Msk           (0x1U << ETH_MACL3L4C0R_L4SPM0_Pos)                 /*!< 0x00040000 */
9455 #define ETH_MACL3L4C0R_L4SPM0               ETH_MACL3L4C0R_L4SPM0_Msk                           /*!< Layer 4 Source Port Match Enable */
9456 #define ETH_MACL3L4C0R_L4SPIM0_Pos          (19U)
9457 #define ETH_MACL3L4C0R_L4SPIM0_Msk          (0x1U << ETH_MACL3L4C0R_L4SPIM0_Pos)                /*!< 0x00080000 */
9458 #define ETH_MACL3L4C0R_L4SPIM0              ETH_MACL3L4C0R_L4SPIM0_Msk                          /*!< Layer 4 Source Port Inverse Match Enable */
9459 #define ETH_MACL3L4C0R_L4DPM0_Pos           (20U)
9460 #define ETH_MACL3L4C0R_L4DPM0_Msk           (0x1U << ETH_MACL3L4C0R_L4DPM0_Pos)                 /*!< 0x00100000 */
9461 #define ETH_MACL3L4C0R_L4DPM0               ETH_MACL3L4C0R_L4DPM0_Msk                           /*!< Layer 4 Destination Port Match Enable */
9462 #define ETH_MACL3L4C0R_L4DPIM0_Pos          (21U)
9463 #define ETH_MACL3L4C0R_L4DPIM0_Msk          (0x1U << ETH_MACL3L4C0R_L4DPIM0_Pos)                /*!< 0x00200000 */
9464 #define ETH_MACL3L4C0R_L4DPIM0              ETH_MACL3L4C0R_L4DPIM0_Msk                          /*!< Layer 4 Destination Port Inverse Match Enable */
9465 
9466 /*************  Bit definition for ETH_MACL4A0R register  **************/
9467 #define ETH_MACL4A0R_L4SP0_Pos              (0U)
9468 #define ETH_MACL4A0R_L4SP0_Msk              (0xFFFFU << ETH_MACL4A0R_L4SP0_Pos)                 /*!< 0x0000FFFF */
9469 #define ETH_MACL4A0R_L4SP0                  ETH_MACL4A0R_L4SP0_Msk                              /*!< Layer 4 Source Port Number Field */
9470 #define ETH_MACL4A0R_L4SP0_0                (0x1U << ETH_MACL4A0R_L4SP0_Pos)                    /*!< 0x00000001 */
9471 #define ETH_MACL4A0R_L4SP0_1                (0x2U << ETH_MACL4A0R_L4SP0_Pos)                    /*!< 0x00000002 */
9472 #define ETH_MACL4A0R_L4SP0_2                (0x4U << ETH_MACL4A0R_L4SP0_Pos)                    /*!< 0x00000004 */
9473 #define ETH_MACL4A0R_L4SP0_3                (0x8U << ETH_MACL4A0R_L4SP0_Pos)                    /*!< 0x00000008 */
9474 #define ETH_MACL4A0R_L4SP0_4                (0x10U << ETH_MACL4A0R_L4SP0_Pos)                   /*!< 0x00000010 */
9475 #define ETH_MACL4A0R_L4SP0_5                (0x20U << ETH_MACL4A0R_L4SP0_Pos)                   /*!< 0x00000020 */
9476 #define ETH_MACL4A0R_L4SP0_6                (0x40U << ETH_MACL4A0R_L4SP0_Pos)                   /*!< 0x00000040 */
9477 #define ETH_MACL4A0R_L4SP0_7                (0x80U << ETH_MACL4A0R_L4SP0_Pos)                   /*!< 0x00000080 */
9478 #define ETH_MACL4A0R_L4SP0_8                (0x100U << ETH_MACL4A0R_L4SP0_Pos)                  /*!< 0x00000100 */
9479 #define ETH_MACL4A0R_L4SP0_9                (0x200U << ETH_MACL4A0R_L4SP0_Pos)                  /*!< 0x00000200 */
9480 #define ETH_MACL4A0R_L4SP0_10               (0x400U << ETH_MACL4A0R_L4SP0_Pos)                  /*!< 0x00000400 */
9481 #define ETH_MACL4A0R_L4SP0_11               (0x800U << ETH_MACL4A0R_L4SP0_Pos)                  /*!< 0x00000800 */
9482 #define ETH_MACL4A0R_L4SP0_12               (0x1000U << ETH_MACL4A0R_L4SP0_Pos)                 /*!< 0x00001000 */
9483 #define ETH_MACL4A0R_L4SP0_13               (0x2000U << ETH_MACL4A0R_L4SP0_Pos)                 /*!< 0x00002000 */
9484 #define ETH_MACL4A0R_L4SP0_14               (0x4000U << ETH_MACL4A0R_L4SP0_Pos)                 /*!< 0x00004000 */
9485 #define ETH_MACL4A0R_L4SP0_15               (0x8000U << ETH_MACL4A0R_L4SP0_Pos)                 /*!< 0x00008000 */
9486 #define ETH_MACL4A0R_L4DP0_Pos              (16U)
9487 #define ETH_MACL4A0R_L4DP0_Msk              (0xFFFFU << ETH_MACL4A0R_L4DP0_Pos)                 /*!< 0xFFFF0000 */
9488 #define ETH_MACL4A0R_L4DP0                  ETH_MACL4A0R_L4DP0_Msk                              /*!< Layer 4 Destination Port Number Field */
9489 #define ETH_MACL4A0R_L4DP0_0                (0x1U << ETH_MACL4A0R_L4DP0_Pos)                /*!< 0x00010000 */
9490 #define ETH_MACL4A0R_L4DP0_1                (0x2U << ETH_MACL4A0R_L4DP0_Pos)                /*!< 0x00020000 */
9491 #define ETH_MACL4A0R_L4DP0_2                (0x4U << ETH_MACL4A0R_L4DP0_Pos)                /*!< 0x00040000 */
9492 #define ETH_MACL4A0R_L4DP0_3                (0x8U << ETH_MACL4A0R_L4DP0_Pos)                /*!< 0x00080000 */
9493 #define ETH_MACL4A0R_L4DP0_4                (0x10U << ETH_MACL4A0R_L4DP0_Pos)               /*!< 0x00100000 */
9494 #define ETH_MACL4A0R_L4DP0_5                (0x20U << ETH_MACL4A0R_L4DP0_Pos)               /*!< 0x00200000 */
9495 #define ETH_MACL4A0R_L4DP0_6                (0x40U << ETH_MACL4A0R_L4DP0_Pos)               /*!< 0x00400000 */
9496 #define ETH_MACL4A0R_L4DP0_7                (0x80U << ETH_MACL4A0R_L4DP0_Pos)               /*!< 0x00800000 */
9497 #define ETH_MACL4A0R_L4DP0_8                (0x100U << ETH_MACL4A0R_L4DP0_Pos)              /*!< 0x01000000 */
9498 #define ETH_MACL4A0R_L4DP0_9                (0x200U << ETH_MACL4A0R_L4DP0_Pos)              /*!< 0x02000000 */
9499 #define ETH_MACL4A0R_L4DP0_10               (0x400U << ETH_MACL4A0R_L4DP0_Pos)              /*!< 0x04000000 */
9500 #define ETH_MACL4A0R_L4DP0_11               (0x800U << ETH_MACL4A0R_L4DP0_Pos)              /*!< 0x08000000 */
9501 #define ETH_MACL4A0R_L4DP0_12               (0x1000U << ETH_MACL4A0R_L4DP0_Pos)             /*!< 0x10000000 */
9502 #define ETH_MACL4A0R_L4DP0_13               (0x2000U << ETH_MACL4A0R_L4DP0_Pos)             /*!< 0x20000000 */
9503 #define ETH_MACL4A0R_L4DP0_14               (0x4000U << ETH_MACL4A0R_L4DP0_Pos)             /*!< 0x40000000 */
9504 #define ETH_MACL4A0R_L4DP0_15               (0x8000U << ETH_MACL4A0R_L4DP0_Pos)             /*!< 0x80000000 */
9505 
9506 /*************  Bit definition for ETH_MACL3A00R register  *************/
9507 #define ETH_MACL3A00R_L3A00_Pos             (0U)
9508 #define ETH_MACL3A00R_L3A00_Msk             (0xFFFFFFFFU << ETH_MACL3A00R_L3A00_Pos)            /*!< 0xFFFFFFFF */
9509 #define ETH_MACL3A00R_L3A00                 ETH_MACL3A00R_L3A00_Msk                             /*!< Layer 3 Address 0 Field */
9510 #define ETH_MACL3A00R_L3A00_0               (0x1U << ETH_MACL3A00R_L3A00_Pos)                   /*!< 0x00000001 */
9511 #define ETH_MACL3A00R_L3A00_1               (0x2U << ETH_MACL3A00R_L3A00_Pos)                   /*!< 0x00000002 */
9512 #define ETH_MACL3A00R_L3A00_2               (0x4U << ETH_MACL3A00R_L3A00_Pos)                   /*!< 0x00000004 */
9513 #define ETH_MACL3A00R_L3A00_3               (0x8U << ETH_MACL3A00R_L3A00_Pos)                   /*!< 0x00000008 */
9514 #define ETH_MACL3A00R_L3A00_4               (0x10U << ETH_MACL3A00R_L3A00_Pos)                  /*!< 0x00000010 */
9515 #define ETH_MACL3A00R_L3A00_5               (0x20U << ETH_MACL3A00R_L3A00_Pos)                  /*!< 0x00000020 */
9516 #define ETH_MACL3A00R_L3A00_6               (0x40U << ETH_MACL3A00R_L3A00_Pos)                  /*!< 0x00000040 */
9517 #define ETH_MACL3A00R_L3A00_7               (0x80U << ETH_MACL3A00R_L3A00_Pos)                  /*!< 0x00000080 */
9518 #define ETH_MACL3A00R_L3A00_8               (0x100U << ETH_MACL3A00R_L3A00_Pos)                 /*!< 0x00000100 */
9519 #define ETH_MACL3A00R_L3A00_9               (0x200U << ETH_MACL3A00R_L3A00_Pos)                 /*!< 0x00000200 */
9520 #define ETH_MACL3A00R_L3A00_10              (0x400U << ETH_MACL3A00R_L3A00_Pos)                 /*!< 0x00000400 */
9521 #define ETH_MACL3A00R_L3A00_11              (0x800U << ETH_MACL3A00R_L3A00_Pos)                 /*!< 0x00000800 */
9522 #define ETH_MACL3A00R_L3A00_12              (0x1000U << ETH_MACL3A00R_L3A00_Pos)                /*!< 0x00001000 */
9523 #define ETH_MACL3A00R_L3A00_13              (0x2000U << ETH_MACL3A00R_L3A00_Pos)                /*!< 0x00002000 */
9524 #define ETH_MACL3A00R_L3A00_14              (0x4000U << ETH_MACL3A00R_L3A00_Pos)                /*!< 0x00004000 */
9525 #define ETH_MACL3A00R_L3A00_15              (0x8000U << ETH_MACL3A00R_L3A00_Pos)                /*!< 0x00008000 */
9526 #define ETH_MACL3A00R_L3A00_16              (0x10000U << ETH_MACL3A00R_L3A00_Pos)               /*!< 0x00010000 */
9527 #define ETH_MACL3A00R_L3A00_17              (0x20000U << ETH_MACL3A00R_L3A00_Pos)               /*!< 0x00020000 */
9528 #define ETH_MACL3A00R_L3A00_18              (0x40000U << ETH_MACL3A00R_L3A00_Pos)               /*!< 0x00040000 */
9529 #define ETH_MACL3A00R_L3A00_19              (0x80000U << ETH_MACL3A00R_L3A00_Pos)               /*!< 0x00080000 */
9530 #define ETH_MACL3A00R_L3A00_20              (0x100000U << ETH_MACL3A00R_L3A00_Pos)              /*!< 0x00100000 */
9531 #define ETH_MACL3A00R_L3A00_21              (0x200000U << ETH_MACL3A00R_L3A00_Pos)              /*!< 0x00200000 */
9532 #define ETH_MACL3A00R_L3A00_22              (0x400000U << ETH_MACL3A00R_L3A00_Pos)              /*!< 0x00400000 */
9533 #define ETH_MACL3A00R_L3A00_23              (0x800000U << ETH_MACL3A00R_L3A00_Pos)              /*!< 0x00800000 */
9534 #define ETH_MACL3A00R_L3A00_24              (0x1000000U << ETH_MACL3A00R_L3A00_Pos)             /*!< 0x01000000 */
9535 #define ETH_MACL3A00R_L3A00_25              (0x2000000U << ETH_MACL3A00R_L3A00_Pos)             /*!< 0x02000000 */
9536 #define ETH_MACL3A00R_L3A00_26              (0x4000000U << ETH_MACL3A00R_L3A00_Pos)             /*!< 0x04000000 */
9537 #define ETH_MACL3A00R_L3A00_27              (0x8000000U << ETH_MACL3A00R_L3A00_Pos)             /*!< 0x08000000 */
9538 #define ETH_MACL3A00R_L3A00_28              (0x10000000U << ETH_MACL3A00R_L3A00_Pos)            /*!< 0x10000000 */
9539 #define ETH_MACL3A00R_L3A00_29              (0x20000000U << ETH_MACL3A00R_L3A00_Pos)            /*!< 0x20000000 */
9540 #define ETH_MACL3A00R_L3A00_30              (0x40000000U << ETH_MACL3A00R_L3A00_Pos)            /*!< 0x40000000 */
9541 #define ETH_MACL3A00R_L3A00_31              (0x80000000U << ETH_MACL3A00R_L3A00_Pos)            /*!< 0x80000000 */
9542 
9543 /*************  Bit definition for ETH_MACL3A10R register  *************/
9544 #define ETH_MACL3A10R_L3A10_Pos             (0U)
9545 #define ETH_MACL3A10R_L3A10_Msk             (0xFFFFFFFFU << ETH_MACL3A10R_L3A10_Pos)            /*!< 0xFFFFFFFF */
9546 #define ETH_MACL3A10R_L3A10                 ETH_MACL3A10R_L3A10_Msk                             /*!< Layer 3 Address 1 Field */
9547 #define ETH_MACL3A10R_L3A10_0               (0x1U << ETH_MACL3A10R_L3A10_Pos)                   /*!< 0x00000001 */
9548 #define ETH_MACL3A10R_L3A10_1               (0x2U << ETH_MACL3A10R_L3A10_Pos)                   /*!< 0x00000002 */
9549 #define ETH_MACL3A10R_L3A10_2               (0x4U << ETH_MACL3A10R_L3A10_Pos)                   /*!< 0x00000004 */
9550 #define ETH_MACL3A10R_L3A10_3               (0x8U << ETH_MACL3A10R_L3A10_Pos)                   /*!< 0x00000008 */
9551 #define ETH_MACL3A10R_L3A10_4               (0x10U << ETH_MACL3A10R_L3A10_Pos)                  /*!< 0x00000010 */
9552 #define ETH_MACL3A10R_L3A10_5               (0x20U << ETH_MACL3A10R_L3A10_Pos)                  /*!< 0x00000020 */
9553 #define ETH_MACL3A10R_L3A10_6               (0x40U << ETH_MACL3A10R_L3A10_Pos)                  /*!< 0x00000040 */
9554 #define ETH_MACL3A10R_L3A10_7               (0x80U << ETH_MACL3A10R_L3A10_Pos)                  /*!< 0x00000080 */
9555 #define ETH_MACL3A10R_L3A10_8               (0x100U << ETH_MACL3A10R_L3A10_Pos)                 /*!< 0x00000100 */
9556 #define ETH_MACL3A10R_L3A10_9               (0x200U << ETH_MACL3A10R_L3A10_Pos)                 /*!< 0x00000200 */
9557 #define ETH_MACL3A10R_L3A10_10              (0x400U << ETH_MACL3A10R_L3A10_Pos)                 /*!< 0x00000400 */
9558 #define ETH_MACL3A10R_L3A10_11              (0x800U << ETH_MACL3A10R_L3A10_Pos)                 /*!< 0x00000800 */
9559 #define ETH_MACL3A10R_L3A10_12              (0x1000U << ETH_MACL3A10R_L3A10_Pos)                /*!< 0x00001000 */
9560 #define ETH_MACL3A10R_L3A10_13              (0x2000U << ETH_MACL3A10R_L3A10_Pos)                /*!< 0x00002000 */
9561 #define ETH_MACL3A10R_L3A10_14              (0x4000U << ETH_MACL3A10R_L3A10_Pos)                /*!< 0x00004000 */
9562 #define ETH_MACL3A10R_L3A10_15              (0x8000U << ETH_MACL3A10R_L3A10_Pos)                /*!< 0x00008000 */
9563 #define ETH_MACL3A10R_L3A10_16              (0x10000U << ETH_MACL3A10R_L3A10_Pos)               /*!< 0x00010000 */
9564 #define ETH_MACL3A10R_L3A10_17              (0x20000U << ETH_MACL3A10R_L3A10_Pos)               /*!< 0x00020000 */
9565 #define ETH_MACL3A10R_L3A10_18              (0x40000U << ETH_MACL3A10R_L3A10_Pos)               /*!< 0x00040000 */
9566 #define ETH_MACL3A10R_L3A10_19              (0x80000U << ETH_MACL3A10R_L3A10_Pos)               /*!< 0x00080000 */
9567 #define ETH_MACL3A10R_L3A10_20              (0x100000U << ETH_MACL3A10R_L3A10_Pos)              /*!< 0x00100000 */
9568 #define ETH_MACL3A10R_L3A10_21              (0x200000U << ETH_MACL3A10R_L3A10_Pos)              /*!< 0x00200000 */
9569 #define ETH_MACL3A10R_L3A10_22              (0x400000U << ETH_MACL3A10R_L3A10_Pos)              /*!< 0x00400000 */
9570 #define ETH_MACL3A10R_L3A10_23              (0x800000U << ETH_MACL3A10R_L3A10_Pos)              /*!< 0x00800000 */
9571 #define ETH_MACL3A10R_L3A10_24              (0x1000000U << ETH_MACL3A10R_L3A10_Pos)             /*!< 0x01000000 */
9572 #define ETH_MACL3A10R_L3A10_25              (0x2000000U << ETH_MACL3A10R_L3A10_Pos)             /*!< 0x02000000 */
9573 #define ETH_MACL3A10R_L3A10_26              (0x4000000U << ETH_MACL3A10R_L3A10_Pos)             /*!< 0x04000000 */
9574 #define ETH_MACL3A10R_L3A10_27              (0x8000000U << ETH_MACL3A10R_L3A10_Pos)             /*!< 0x08000000 */
9575 #define ETH_MACL3A10R_L3A10_28              (0x10000000U << ETH_MACL3A10R_L3A10_Pos)            /*!< 0x10000000 */
9576 #define ETH_MACL3A10R_L3A10_29              (0x20000000U << ETH_MACL3A10R_L3A10_Pos)            /*!< 0x20000000 */
9577 #define ETH_MACL3A10R_L3A10_30              (0x40000000U << ETH_MACL3A10R_L3A10_Pos)            /*!< 0x40000000 */
9578 #define ETH_MACL3A10R_L3A10_31              (0x80000000U << ETH_MACL3A10R_L3A10_Pos)            /*!< 0x80000000 */
9579 
9580 /*************  Bit definition for ETH_MACL3A20 register  **************/
9581 #define ETH_MACL3A20_L3A20_Pos              (0U)
9582 #define ETH_MACL3A20_L3A20_Msk              (0xFFFFFFFFU << ETH_MACL3A20_L3A20_Pos)             /*!< 0xFFFFFFFF */
9583 #define ETH_MACL3A20_L3A20                  ETH_MACL3A20_L3A20_Msk                              /*!< Layer 3 Address 2 Field */
9584 #define ETH_MACL3A20_L3A20_0                (0x1U << ETH_MACL3A20_L3A20_Pos)                    /*!< 0x00000001 */
9585 #define ETH_MACL3A20_L3A20_1                (0x2U << ETH_MACL3A20_L3A20_Pos)                    /*!< 0x00000002 */
9586 #define ETH_MACL3A20_L3A20_2                (0x4U << ETH_MACL3A20_L3A20_Pos)                    /*!< 0x00000004 */
9587 #define ETH_MACL3A20_L3A20_3                (0x8U << ETH_MACL3A20_L3A20_Pos)                    /*!< 0x00000008 */
9588 #define ETH_MACL3A20_L3A20_4                (0x10U << ETH_MACL3A20_L3A20_Pos)                   /*!< 0x00000010 */
9589 #define ETH_MACL3A20_L3A20_5                (0x20U << ETH_MACL3A20_L3A20_Pos)                   /*!< 0x00000020 */
9590 #define ETH_MACL3A20_L3A20_6                (0x40U << ETH_MACL3A20_L3A20_Pos)                   /*!< 0x00000040 */
9591 #define ETH_MACL3A20_L3A20_7                (0x80U << ETH_MACL3A20_L3A20_Pos)                   /*!< 0x00000080 */
9592 #define ETH_MACL3A20_L3A20_8                (0x100U << ETH_MACL3A20_L3A20_Pos)                  /*!< 0x00000100 */
9593 #define ETH_MACL3A20_L3A20_9                (0x200U << ETH_MACL3A20_L3A20_Pos)                  /*!< 0x00000200 */
9594 #define ETH_MACL3A20_L3A20_10               (0x400U << ETH_MACL3A20_L3A20_Pos)                  /*!< 0x00000400 */
9595 #define ETH_MACL3A20_L3A20_11               (0x800U << ETH_MACL3A20_L3A20_Pos)                  /*!< 0x00000800 */
9596 #define ETH_MACL3A20_L3A20_12               (0x1000U << ETH_MACL3A20_L3A20_Pos)                 /*!< 0x00001000 */
9597 #define ETH_MACL3A20_L3A20_13               (0x2000U << ETH_MACL3A20_L3A20_Pos)                 /*!< 0x00002000 */
9598 #define ETH_MACL3A20_L3A20_14               (0x4000U << ETH_MACL3A20_L3A20_Pos)                 /*!< 0x00004000 */
9599 #define ETH_MACL3A20_L3A20_15               (0x8000U << ETH_MACL3A20_L3A20_Pos)                 /*!< 0x00008000 */
9600 #define ETH_MACL3A20_L3A20_16               (0x10000U << ETH_MACL3A20_L3A20_Pos)                /*!< 0x00010000 */
9601 #define ETH_MACL3A20_L3A20_17               (0x20000U << ETH_MACL3A20_L3A20_Pos)                /*!< 0x00020000 */
9602 #define ETH_MACL3A20_L3A20_18               (0x40000U << ETH_MACL3A20_L3A20_Pos)                /*!< 0x00040000 */
9603 #define ETH_MACL3A20_L3A20_19               (0x80000U << ETH_MACL3A20_L3A20_Pos)                /*!< 0x00080000 */
9604 #define ETH_MACL3A20_L3A20_20               (0x100000U << ETH_MACL3A20_L3A20_Pos)               /*!< 0x00100000 */
9605 #define ETH_MACL3A20_L3A20_21               (0x200000U << ETH_MACL3A20_L3A20_Pos)               /*!< 0x00200000 */
9606 #define ETH_MACL3A20_L3A20_22               (0x400000U << ETH_MACL3A20_L3A20_Pos)               /*!< 0x00400000 */
9607 #define ETH_MACL3A20_L3A20_23               (0x800000U << ETH_MACL3A20_L3A20_Pos)               /*!< 0x00800000 */
9608 #define ETH_MACL3A20_L3A20_24               (0x1000000U << ETH_MACL3A20_L3A20_Pos)              /*!< 0x01000000 */
9609 #define ETH_MACL3A20_L3A20_25               (0x2000000U << ETH_MACL3A20_L3A20_Pos)              /*!< 0x02000000 */
9610 #define ETH_MACL3A20_L3A20_26               (0x4000000U << ETH_MACL3A20_L3A20_Pos)              /*!< 0x04000000 */
9611 #define ETH_MACL3A20_L3A20_27               (0x8000000U << ETH_MACL3A20_L3A20_Pos)              /*!< 0x08000000 */
9612 #define ETH_MACL3A20_L3A20_28               (0x10000000U << ETH_MACL3A20_L3A20_Pos)             /*!< 0x10000000 */
9613 #define ETH_MACL3A20_L3A20_29               (0x20000000U << ETH_MACL3A20_L3A20_Pos)             /*!< 0x20000000 */
9614 #define ETH_MACL3A20_L3A20_30               (0x40000000U << ETH_MACL3A20_L3A20_Pos)             /*!< 0x40000000 */
9615 #define ETH_MACL3A20_L3A20_31               (0x80000000U << ETH_MACL3A20_L3A20_Pos)             /*!< 0x80000000 */
9616 
9617 /*************  Bit definition for ETH_MACL3A30 register  **************/
9618 #define ETH_MACL3A30_L3A30_Pos              (0U)
9619 #define ETH_MACL3A30_L3A30_Msk              (0xFFFFFFFFU << ETH_MACL3A30_L3A30_Pos)             /*!< 0xFFFFFFFF */
9620 #define ETH_MACL3A30_L3A30                  ETH_MACL3A30_L3A30_Msk                              /*!< Layer 3 Address 3 Field */
9621 #define ETH_MACL3A30_L3A30_0                (0x1U << ETH_MACL3A30_L3A30_Pos)                    /*!< 0x00000001 */
9622 #define ETH_MACL3A30_L3A30_1                (0x2U << ETH_MACL3A30_L3A30_Pos)                    /*!< 0x00000002 */
9623 #define ETH_MACL3A30_L3A30_2                (0x4U << ETH_MACL3A30_L3A30_Pos)                    /*!< 0x00000004 */
9624 #define ETH_MACL3A30_L3A30_3                (0x8U << ETH_MACL3A30_L3A30_Pos)                    /*!< 0x00000008 */
9625 #define ETH_MACL3A30_L3A30_4                (0x10U << ETH_MACL3A30_L3A30_Pos)                   /*!< 0x00000010 */
9626 #define ETH_MACL3A30_L3A30_5                (0x20U << ETH_MACL3A30_L3A30_Pos)                   /*!< 0x00000020 */
9627 #define ETH_MACL3A30_L3A30_6                (0x40U << ETH_MACL3A30_L3A30_Pos)                   /*!< 0x00000040 */
9628 #define ETH_MACL3A30_L3A30_7                (0x80U << ETH_MACL3A30_L3A30_Pos)                   /*!< 0x00000080 */
9629 #define ETH_MACL3A30_L3A30_8                (0x100U << ETH_MACL3A30_L3A30_Pos)                  /*!< 0x00000100 */
9630 #define ETH_MACL3A30_L3A30_9                (0x200U << ETH_MACL3A30_L3A30_Pos)                  /*!< 0x00000200 */
9631 #define ETH_MACL3A30_L3A30_10               (0x400U << ETH_MACL3A30_L3A30_Pos)                  /*!< 0x00000400 */
9632 #define ETH_MACL3A30_L3A30_11               (0x800U << ETH_MACL3A30_L3A30_Pos)                  /*!< 0x00000800 */
9633 #define ETH_MACL3A30_L3A30_12               (0x1000U << ETH_MACL3A30_L3A30_Pos)                 /*!< 0x00001000 */
9634 #define ETH_MACL3A30_L3A30_13               (0x2000U << ETH_MACL3A30_L3A30_Pos)                 /*!< 0x00002000 */
9635 #define ETH_MACL3A30_L3A30_14               (0x4000U << ETH_MACL3A30_L3A30_Pos)                 /*!< 0x00004000 */
9636 #define ETH_MACL3A30_L3A30_15               (0x8000U << ETH_MACL3A30_L3A30_Pos)                 /*!< 0x00008000 */
9637 #define ETH_MACL3A30_L3A30_16               (0x10000U << ETH_MACL3A30_L3A30_Pos)                /*!< 0x00010000 */
9638 #define ETH_MACL3A30_L3A30_17               (0x20000U << ETH_MACL3A30_L3A30_Pos)                /*!< 0x00020000 */
9639 #define ETH_MACL3A30_L3A30_18               (0x40000U << ETH_MACL3A30_L3A30_Pos)                /*!< 0x00040000 */
9640 #define ETH_MACL3A30_L3A30_19               (0x80000U << ETH_MACL3A30_L3A30_Pos)                /*!< 0x00080000 */
9641 #define ETH_MACL3A30_L3A30_20               (0x100000U << ETH_MACL3A30_L3A30_Pos)               /*!< 0x00100000 */
9642 #define ETH_MACL3A30_L3A30_21               (0x200000U << ETH_MACL3A30_L3A30_Pos)               /*!< 0x00200000 */
9643 #define ETH_MACL3A30_L3A30_22               (0x400000U << ETH_MACL3A30_L3A30_Pos)               /*!< 0x00400000 */
9644 #define ETH_MACL3A30_L3A30_23               (0x800000U << ETH_MACL3A30_L3A30_Pos)               /*!< 0x00800000 */
9645 #define ETH_MACL3A30_L3A30_24               (0x1000000U << ETH_MACL3A30_L3A30_Pos)              /*!< 0x01000000 */
9646 #define ETH_MACL3A30_L3A30_25               (0x2000000U << ETH_MACL3A30_L3A30_Pos)              /*!< 0x02000000 */
9647 #define ETH_MACL3A30_L3A30_26               (0x4000000U << ETH_MACL3A30_L3A30_Pos)              /*!< 0x04000000 */
9648 #define ETH_MACL3A30_L3A30_27               (0x8000000U << ETH_MACL3A30_L3A30_Pos)              /*!< 0x08000000 */
9649 #define ETH_MACL3A30_L3A30_28               (0x10000000U << ETH_MACL3A30_L3A30_Pos)             /*!< 0x10000000 */
9650 #define ETH_MACL3A30_L3A30_29               (0x20000000U << ETH_MACL3A30_L3A30_Pos)             /*!< 0x20000000 */
9651 #define ETH_MACL3A30_L3A30_30               (0x40000000U << ETH_MACL3A30_L3A30_Pos)             /*!< 0x40000000 */
9652 #define ETH_MACL3A30_L3A30_31               (0x80000000U << ETH_MACL3A30_L3A30_Pos)             /*!< 0x80000000 */
9653 
9654 /************  Bit definition for ETH_MACL3L4C1R register  *************/
9655 #define ETH_MACL3L4C1R_L3PEN1_Pos           (0U)
9656 #define ETH_MACL3L4C1R_L3PEN1_Msk           (0x1U << ETH_MACL3L4C1R_L3PEN1_Pos)                 /*!< 0x00000001 */
9657 #define ETH_MACL3L4C1R_L3PEN1               ETH_MACL3L4C1R_L3PEN1_Msk                           /*!< Layer 3 Protocol Enable */
9658 #define ETH_MACL3L4C1R_L3SAM1_Pos           (2U)
9659 #define ETH_MACL3L4C1R_L3SAM1_Msk           (0x1U << ETH_MACL3L4C1R_L3SAM1_Pos)                 /*!< 0x00000004 */
9660 #define ETH_MACL3L4C1R_L3SAM1               ETH_MACL3L4C1R_L3SAM1_Msk                           /*!< Layer 3 IP SA Match Enable */
9661 #define ETH_MACL3L4C1R_L3SAIM1_Pos          (3U)
9662 #define ETH_MACL3L4C1R_L3SAIM1_Msk          (0x1U << ETH_MACL3L4C1R_L3SAIM1_Pos)                /*!< 0x00000008 */
9663 #define ETH_MACL3L4C1R_L3SAIM1              ETH_MACL3L4C1R_L3SAIM1_Msk                          /*!< Layer 3 IP SA Inverse Match Enable */
9664 #define ETH_MACL3L4C1R_L3DAM1_Pos           (4U)
9665 #define ETH_MACL3L4C1R_L3DAM1_Msk           (0x1U << ETH_MACL3L4C1R_L3DAM1_Pos)                 /*!< 0x00000010 */
9666 #define ETH_MACL3L4C1R_L3DAM1               ETH_MACL3L4C1R_L3DAM1_Msk                           /*!< Layer 3 IP DA Match Enable */
9667 #define ETH_MACL3L4C1R_L3DAIM1_Pos          (5U)
9668 #define ETH_MACL3L4C1R_L3DAIM1_Msk          (0x1U << ETH_MACL3L4C1R_L3DAIM1_Pos)                /*!< 0x00000020 */
9669 #define ETH_MACL3L4C1R_L3DAIM1              ETH_MACL3L4C1R_L3DAIM1_Msk                          /*!< Layer 3 IP DA Inverse Match Enable */
9670 #define ETH_MACL3L4C1R_L3HSBM1_Pos          (6U)
9671 #define ETH_MACL3L4C1R_L3HSBM1_Msk          (0x1FU << ETH_MACL3L4C1R_L3HSBM1_Pos)               /*!< 0x000007C0 */
9672 #define ETH_MACL3L4C1R_L3HSBM1              ETH_MACL3L4C1R_L3HSBM1_Msk                          /*!< Layer 3 IP SA Higher Bits Match */
9673 #define ETH_MACL3L4C1R_L3HSBM1_0            (0x1U << ETH_MACL3L4C1R_L3HSBM1_Pos)               /*!< 0x00000040 */
9674 #define ETH_MACL3L4C1R_L3HSBM1_1            (0x2U << ETH_MACL3L4C1R_L3HSBM1_Pos)               /*!< 0x00000080 */
9675 #define ETH_MACL3L4C1R_L3HSBM1_2            (0x4U << ETH_MACL3L4C1R_L3HSBM1_Pos)              /*!< 0x00000100 */
9676 #define ETH_MACL3L4C1R_L3HSBM1_3            (0x8U << ETH_MACL3L4C1R_L3HSBM1_Pos)              /*!< 0x00000200 */
9677 #define ETH_MACL3L4C1R_L3HSBM1_4            (0x10U << ETH_MACL3L4C1R_L3HSBM1_Pos)              /*!< 0x00000400 */
9678 #define ETH_MACL3L4C1R_L3HDBM1_Pos          (11U)
9679 #define ETH_MACL3L4C1R_L3HDBM1_Msk          (0x1FU << ETH_MACL3L4C1R_L3HDBM1_Pos)               /*!< 0x0000F800 */
9680 #define ETH_MACL3L4C1R_L3HDBM1              ETH_MACL3L4C1R_L3HDBM1_Msk                          /*!< Layer 3 IP DA Higher Bits Match */
9681 #define ETH_MACL3L4C1R_L3HDBM1_0            (0x1U << ETH_MACL3L4C1R_L3HDBM1_Pos)              /*!< 0x00000800 */
9682 #define ETH_MACL3L4C1R_L3HDBM1_1            (0x2U << ETH_MACL3L4C1R_L3HDBM1_Pos)             /*!< 0x00001000 */
9683 #define ETH_MACL3L4C1R_L3HDBM1_2            (0x4U << ETH_MACL3L4C1R_L3HDBM1_Pos)             /*!< 0x00002000 */
9684 #define ETH_MACL3L4C1R_L3HDBM1_3            (0x8U << ETH_MACL3L4C1R_L3HDBM1_Pos)             /*!< 0x00004000 */
9685 #define ETH_MACL3L4C1R_L3HDBM1_4            (0x10U << ETH_MACL3L4C1R_L3HDBM1_Pos)             /*!< 0x00008000 */
9686 #define ETH_MACL3L4C1R_L4PEN1_Pos           (16U)
9687 #define ETH_MACL3L4C1R_L4PEN1_Msk           (0x1U << ETH_MACL3L4C1R_L4PEN1_Pos)                 /*!< 0x00010000 */
9688 #define ETH_MACL3L4C1R_L4PEN1               ETH_MACL3L4C1R_L4PEN1_Msk                           /*!< Layer 4 Protocol Enable */
9689 #define ETH_MACL3L4C1R_L4SPM1_Pos           (18U)
9690 #define ETH_MACL3L4C1R_L4SPM1_Msk           (0x1U << ETH_MACL3L4C1R_L4SPM1_Pos)                 /*!< 0x00040000 */
9691 #define ETH_MACL3L4C1R_L4SPM1               ETH_MACL3L4C1R_L4SPM1_Msk                           /*!< Layer 4 Source Port Match Enable */
9692 #define ETH_MACL3L4C1R_L4SPIM1_Pos          (19U)
9693 #define ETH_MACL3L4C1R_L4SPIM1_Msk          (0x1U << ETH_MACL3L4C1R_L4SPIM1_Pos)                /*!< 0x00080000 */
9694 #define ETH_MACL3L4C1R_L4SPIM1              ETH_MACL3L4C1R_L4SPIM1_Msk                          /*!< Layer 4 Source Port Inverse Match Enable */
9695 #define ETH_MACL3L4C1R_L4DPM1_Pos           (20U)
9696 #define ETH_MACL3L4C1R_L4DPM1_Msk           (0x1U << ETH_MACL3L4C1R_L4DPM1_Pos)                 /*!< 0x00100000 */
9697 #define ETH_MACL3L4C1R_L4DPM1               ETH_MACL3L4C1R_L4DPM1_Msk                           /*!< Layer 4 Destination Port Match Enable */
9698 #define ETH_MACL3L4C1R_L4DPIM1_Pos          (21U)
9699 #define ETH_MACL3L4C1R_L4DPIM1_Msk          (0x1U << ETH_MACL3L4C1R_L4DPIM1_Pos)                /*!< 0x00200000 */
9700 #define ETH_MACL3L4C1R_L4DPIM1              ETH_MACL3L4C1R_L4DPIM1_Msk                          /*!< Layer 4 Destination Port Inverse Match Enable */
9701 
9702 /*************  Bit definition for ETH_MACL4A1R register  **************/
9703 #define ETH_MACL4A1R_L4SP1_Pos              (0U)
9704 #define ETH_MACL4A1R_L4SP1_Msk              (0xFFFFU << ETH_MACL4A1R_L4SP1_Pos)                 /*!< 0x0000FFFF */
9705 #define ETH_MACL4A1R_L4SP1                  ETH_MACL4A1R_L4SP1_Msk                              /*!< Layer 4 Source Port Number Field */
9706 #define ETH_MACL4A1R_L4SP1_0                (0x1U << ETH_MACL4A1R_L4SP1_Pos)                    /*!< 0x00000001 */
9707 #define ETH_MACL4A1R_L4SP1_1                (0x2U << ETH_MACL4A1R_L4SP1_Pos)                    /*!< 0x00000002 */
9708 #define ETH_MACL4A1R_L4SP1_2                (0x4U << ETH_MACL4A1R_L4SP1_Pos)                    /*!< 0x00000004 */
9709 #define ETH_MACL4A1R_L4SP1_3                (0x8U << ETH_MACL4A1R_L4SP1_Pos)                    /*!< 0x00000008 */
9710 #define ETH_MACL4A1R_L4SP1_4                (0x10U << ETH_MACL4A1R_L4SP1_Pos)                   /*!< 0x00000010 */
9711 #define ETH_MACL4A1R_L4SP1_5                (0x20U << ETH_MACL4A1R_L4SP1_Pos)                   /*!< 0x00000020 */
9712 #define ETH_MACL4A1R_L4SP1_6                (0x40U << ETH_MACL4A1R_L4SP1_Pos)                   /*!< 0x00000040 */
9713 #define ETH_MACL4A1R_L4SP1_7                (0x80U << ETH_MACL4A1R_L4SP1_Pos)                   /*!< 0x00000080 */
9714 #define ETH_MACL4A1R_L4SP1_8                (0x100U << ETH_MACL4A1R_L4SP1_Pos)                  /*!< 0x00000100 */
9715 #define ETH_MACL4A1R_L4SP1_9                (0x200U << ETH_MACL4A1R_L4SP1_Pos)                  /*!< 0x00000200 */
9716 #define ETH_MACL4A1R_L4SP1_10               (0x400U << ETH_MACL4A1R_L4SP1_Pos)                  /*!< 0x00000400 */
9717 #define ETH_MACL4A1R_L4SP1_11               (0x800U << ETH_MACL4A1R_L4SP1_Pos)                  /*!< 0x00000800 */
9718 #define ETH_MACL4A1R_L4SP1_12               (0x1000U << ETH_MACL4A1R_L4SP1_Pos)                 /*!< 0x00001000 */
9719 #define ETH_MACL4A1R_L4SP1_13               (0x2000U << ETH_MACL4A1R_L4SP1_Pos)                 /*!< 0x00002000 */
9720 #define ETH_MACL4A1R_L4SP1_14               (0x4000U << ETH_MACL4A1R_L4SP1_Pos)                 /*!< 0x00004000 */
9721 #define ETH_MACL4A1R_L4SP1_15               (0x8000U << ETH_MACL4A1R_L4SP1_Pos)                 /*!< 0x00008000 */
9722 #define ETH_MACL4A1R_L4DP1_Pos              (16U)
9723 #define ETH_MACL4A1R_L4DP1_Msk              (0xFFFFU << ETH_MACL4A1R_L4DP1_Pos)                 /*!< 0xFFFF0000 */
9724 #define ETH_MACL4A1R_L4DP1                  ETH_MACL4A1R_L4DP1_Msk                              /*!< Layer 4 Destination Port Number Field */
9725 #define ETH_MACL4A1R_L4DP1_0                (0x1U << ETH_MACL4A1R_L4DP1_Pos)                /*!< 0x00010000 */
9726 #define ETH_MACL4A1R_L4DP1_1                (0x2U << ETH_MACL4A1R_L4DP1_Pos)                /*!< 0x00020000 */
9727 #define ETH_MACL4A1R_L4DP1_2                (0x4U << ETH_MACL4A1R_L4DP1_Pos)                /*!< 0x00040000 */
9728 #define ETH_MACL4A1R_L4DP1_3                (0x8U << ETH_MACL4A1R_L4DP1_Pos)                /*!< 0x00080000 */
9729 #define ETH_MACL4A1R_L4DP1_4                (0x10U << ETH_MACL4A1R_L4DP1_Pos)               /*!< 0x00100000 */
9730 #define ETH_MACL4A1R_L4DP1_5                (0x20U << ETH_MACL4A1R_L4DP1_Pos)               /*!< 0x00200000 */
9731 #define ETH_MACL4A1R_L4DP1_6                (0x40U << ETH_MACL4A1R_L4DP1_Pos)               /*!< 0x00400000 */
9732 #define ETH_MACL4A1R_L4DP1_7                (0x80U << ETH_MACL4A1R_L4DP1_Pos)               /*!< 0x00800000 */
9733 #define ETH_MACL4A1R_L4DP1_8                (0x100U << ETH_MACL4A1R_L4DP1_Pos)              /*!< 0x01000000 */
9734 #define ETH_MACL4A1R_L4DP1_9                (0x200U << ETH_MACL4A1R_L4DP1_Pos)              /*!< 0x02000000 */
9735 #define ETH_MACL4A1R_L4DP1_10               (0x400U << ETH_MACL4A1R_L4DP1_Pos)              /*!< 0x04000000 */
9736 #define ETH_MACL4A1R_L4DP1_11               (0x800U << ETH_MACL4A1R_L4DP1_Pos)              /*!< 0x08000000 */
9737 #define ETH_MACL4A1R_L4DP1_12               (0x1000U << ETH_MACL4A1R_L4DP1_Pos)             /*!< 0x10000000 */
9738 #define ETH_MACL4A1R_L4DP1_13               (0x2000U << ETH_MACL4A1R_L4DP1_Pos)             /*!< 0x20000000 */
9739 #define ETH_MACL4A1R_L4DP1_14               (0x4000U << ETH_MACL4A1R_L4DP1_Pos)             /*!< 0x40000000 */
9740 #define ETH_MACL4A1R_L4DP1_15               (0x8000U << ETH_MACL4A1R_L4DP1_Pos)             /*!< 0x80000000 */
9741 
9742 /*************  Bit definition for ETH_MACL3A01R register  *************/
9743 #define ETH_MACL3A01R_L3A01_Pos             (0U)
9744 #define ETH_MACL3A01R_L3A01_Msk             (0xFFFFFFFFU << ETH_MACL3A01R_L3A01_Pos)            /*!< 0xFFFFFFFF */
9745 #define ETH_MACL3A01R_L3A01                 ETH_MACL3A01R_L3A01_Msk                             /*!< Layer 3 Address 0 Field */
9746 #define ETH_MACL3A01R_L3A01_0               (0x1U << ETH_MACL3A01R_L3A01_Pos)                   /*!< 0x00000001 */
9747 #define ETH_MACL3A01R_L3A01_1               (0x2U << ETH_MACL3A01R_L3A01_Pos)                   /*!< 0x00000002 */
9748 #define ETH_MACL3A01R_L3A01_2               (0x4U << ETH_MACL3A01R_L3A01_Pos)                   /*!< 0x00000004 */
9749 #define ETH_MACL3A01R_L3A01_3               (0x8U << ETH_MACL3A01R_L3A01_Pos)                   /*!< 0x00000008 */
9750 #define ETH_MACL3A01R_L3A01_4               (0x10U << ETH_MACL3A01R_L3A01_Pos)                  /*!< 0x00000010 */
9751 #define ETH_MACL3A01R_L3A01_5               (0x20U << ETH_MACL3A01R_L3A01_Pos)                  /*!< 0x00000020 */
9752 #define ETH_MACL3A01R_L3A01_6               (0x40U << ETH_MACL3A01R_L3A01_Pos)                  /*!< 0x00000040 */
9753 #define ETH_MACL3A01R_L3A01_7               (0x80U << ETH_MACL3A01R_L3A01_Pos)                  /*!< 0x00000080 */
9754 #define ETH_MACL3A01R_L3A01_8               (0x100U << ETH_MACL3A01R_L3A01_Pos)                 /*!< 0x00000100 */
9755 #define ETH_MACL3A01R_L3A01_9               (0x200U << ETH_MACL3A01R_L3A01_Pos)                 /*!< 0x00000200 */
9756 #define ETH_MACL3A01R_L3A01_10              (0x400U << ETH_MACL3A01R_L3A01_Pos)                 /*!< 0x00000400 */
9757 #define ETH_MACL3A01R_L3A01_11              (0x800U << ETH_MACL3A01R_L3A01_Pos)                 /*!< 0x00000800 */
9758 #define ETH_MACL3A01R_L3A01_12              (0x1000U << ETH_MACL3A01R_L3A01_Pos)                /*!< 0x00001000 */
9759 #define ETH_MACL3A01R_L3A01_13              (0x2000U << ETH_MACL3A01R_L3A01_Pos)                /*!< 0x00002000 */
9760 #define ETH_MACL3A01R_L3A01_14              (0x4000U << ETH_MACL3A01R_L3A01_Pos)                /*!< 0x00004000 */
9761 #define ETH_MACL3A01R_L3A01_15              (0x8000U << ETH_MACL3A01R_L3A01_Pos)                /*!< 0x00008000 */
9762 #define ETH_MACL3A01R_L3A01_16              (0x10000U << ETH_MACL3A01R_L3A01_Pos)               /*!< 0x00010000 */
9763 #define ETH_MACL3A01R_L3A01_17              (0x20000U << ETH_MACL3A01R_L3A01_Pos)               /*!< 0x00020000 */
9764 #define ETH_MACL3A01R_L3A01_18              (0x40000U << ETH_MACL3A01R_L3A01_Pos)               /*!< 0x00040000 */
9765 #define ETH_MACL3A01R_L3A01_19              (0x80000U << ETH_MACL3A01R_L3A01_Pos)               /*!< 0x00080000 */
9766 #define ETH_MACL3A01R_L3A01_20              (0x100000U << ETH_MACL3A01R_L3A01_Pos)              /*!< 0x00100000 */
9767 #define ETH_MACL3A01R_L3A01_21              (0x200000U << ETH_MACL3A01R_L3A01_Pos)              /*!< 0x00200000 */
9768 #define ETH_MACL3A01R_L3A01_22              (0x400000U << ETH_MACL3A01R_L3A01_Pos)              /*!< 0x00400000 */
9769 #define ETH_MACL3A01R_L3A01_23              (0x800000U << ETH_MACL3A01R_L3A01_Pos)              /*!< 0x00800000 */
9770 #define ETH_MACL3A01R_L3A01_24              (0x1000000U << ETH_MACL3A01R_L3A01_Pos)             /*!< 0x01000000 */
9771 #define ETH_MACL3A01R_L3A01_25              (0x2000000U << ETH_MACL3A01R_L3A01_Pos)             /*!< 0x02000000 */
9772 #define ETH_MACL3A01R_L3A01_26              (0x4000000U << ETH_MACL3A01R_L3A01_Pos)             /*!< 0x04000000 */
9773 #define ETH_MACL3A01R_L3A01_27              (0x8000000U << ETH_MACL3A01R_L3A01_Pos)             /*!< 0x08000000 */
9774 #define ETH_MACL3A01R_L3A01_28              (0x10000000U << ETH_MACL3A01R_L3A01_Pos)            /*!< 0x10000000 */
9775 #define ETH_MACL3A01R_L3A01_29              (0x20000000U << ETH_MACL3A01R_L3A01_Pos)            /*!< 0x20000000 */
9776 #define ETH_MACL3A01R_L3A01_30              (0x40000000U << ETH_MACL3A01R_L3A01_Pos)            /*!< 0x40000000 */
9777 #define ETH_MACL3A01R_L3A01_31              (0x80000000U << ETH_MACL3A01R_L3A01_Pos)            /*!< 0x80000000 */
9778 
9779 /*************  Bit definition for ETH_MACL3A11R register  *************/
9780 #define ETH_MACL3A11R_L3A11_Pos             (0U)
9781 #define ETH_MACL3A11R_L3A11_Msk             (0xFFFFFFFFU << ETH_MACL3A11R_L3A11_Pos)            /*!< 0xFFFFFFFF */
9782 #define ETH_MACL3A11R_L3A11                 ETH_MACL3A11R_L3A11_Msk                             /*!< Layer 3 Address 1 Field */
9783 #define ETH_MACL3A11R_L3A11_0               (0x1U << ETH_MACL3A11R_L3A11_Pos)                   /*!< 0x00000001 */
9784 #define ETH_MACL3A11R_L3A11_1               (0x2U << ETH_MACL3A11R_L3A11_Pos)                   /*!< 0x00000002 */
9785 #define ETH_MACL3A11R_L3A11_2               (0x4U << ETH_MACL3A11R_L3A11_Pos)                   /*!< 0x00000004 */
9786 #define ETH_MACL3A11R_L3A11_3               (0x8U << ETH_MACL3A11R_L3A11_Pos)                   /*!< 0x00000008 */
9787 #define ETH_MACL3A11R_L3A11_4               (0x10U << ETH_MACL3A11R_L3A11_Pos)                  /*!< 0x00000010 */
9788 #define ETH_MACL3A11R_L3A11_5               (0x20U << ETH_MACL3A11R_L3A11_Pos)                  /*!< 0x00000020 */
9789 #define ETH_MACL3A11R_L3A11_6               (0x40U << ETH_MACL3A11R_L3A11_Pos)                  /*!< 0x00000040 */
9790 #define ETH_MACL3A11R_L3A11_7               (0x80U << ETH_MACL3A11R_L3A11_Pos)                  /*!< 0x00000080 */
9791 #define ETH_MACL3A11R_L3A11_8               (0x100U << ETH_MACL3A11R_L3A11_Pos)                 /*!< 0x00000100 */
9792 #define ETH_MACL3A11R_L3A11_9               (0x200U << ETH_MACL3A11R_L3A11_Pos)                 /*!< 0x00000200 */
9793 #define ETH_MACL3A11R_L3A11_10              (0x400U << ETH_MACL3A11R_L3A11_Pos)                 /*!< 0x00000400 */
9794 #define ETH_MACL3A11R_L3A11_11              (0x800U << ETH_MACL3A11R_L3A11_Pos)                 /*!< 0x00000800 */
9795 #define ETH_MACL3A11R_L3A11_12              (0x1000U << ETH_MACL3A11R_L3A11_Pos)                /*!< 0x00001000 */
9796 #define ETH_MACL3A11R_L3A11_13              (0x2000U << ETH_MACL3A11R_L3A11_Pos)                /*!< 0x00002000 */
9797 #define ETH_MACL3A11R_L3A11_14              (0x4000U << ETH_MACL3A11R_L3A11_Pos)                /*!< 0x00004000 */
9798 #define ETH_MACL3A11R_L3A11_15              (0x8000U << ETH_MACL3A11R_L3A11_Pos)                /*!< 0x00008000 */
9799 #define ETH_MACL3A11R_L3A11_16              (0x10000U << ETH_MACL3A11R_L3A11_Pos)               /*!< 0x00010000 */
9800 #define ETH_MACL3A11R_L3A11_17              (0x20000U << ETH_MACL3A11R_L3A11_Pos)               /*!< 0x00020000 */
9801 #define ETH_MACL3A11R_L3A11_18              (0x40000U << ETH_MACL3A11R_L3A11_Pos)               /*!< 0x00040000 */
9802 #define ETH_MACL3A11R_L3A11_19              (0x80000U << ETH_MACL3A11R_L3A11_Pos)               /*!< 0x00080000 */
9803 #define ETH_MACL3A11R_L3A11_20              (0x100000U << ETH_MACL3A11R_L3A11_Pos)              /*!< 0x00100000 */
9804 #define ETH_MACL3A11R_L3A11_21              (0x200000U << ETH_MACL3A11R_L3A11_Pos)              /*!< 0x00200000 */
9805 #define ETH_MACL3A11R_L3A11_22              (0x400000U << ETH_MACL3A11R_L3A11_Pos)              /*!< 0x00400000 */
9806 #define ETH_MACL3A11R_L3A11_23              (0x800000U << ETH_MACL3A11R_L3A11_Pos)              /*!< 0x00800000 */
9807 #define ETH_MACL3A11R_L3A11_24              (0x1000000U << ETH_MACL3A11R_L3A11_Pos)             /*!< 0x01000000 */
9808 #define ETH_MACL3A11R_L3A11_25              (0x2000000U << ETH_MACL3A11R_L3A11_Pos)             /*!< 0x02000000 */
9809 #define ETH_MACL3A11R_L3A11_26              (0x4000000U << ETH_MACL3A11R_L3A11_Pos)             /*!< 0x04000000 */
9810 #define ETH_MACL3A11R_L3A11_27              (0x8000000U << ETH_MACL3A11R_L3A11_Pos)             /*!< 0x08000000 */
9811 #define ETH_MACL3A11R_L3A11_28              (0x10000000U << ETH_MACL3A11R_L3A11_Pos)            /*!< 0x10000000 */
9812 #define ETH_MACL3A11R_L3A11_29              (0x20000000U << ETH_MACL3A11R_L3A11_Pos)            /*!< 0x20000000 */
9813 #define ETH_MACL3A11R_L3A11_30              (0x40000000U << ETH_MACL3A11R_L3A11_Pos)            /*!< 0x40000000 */
9814 #define ETH_MACL3A11R_L3A11_31              (0x80000000U << ETH_MACL3A11R_L3A11_Pos)            /*!< 0x80000000 */
9815 
9816 /*************  Bit definition for ETH_MACL3A21R register  *************/
9817 #define ETH_MACL3A21R_L3A21_Pos             (0U)
9818 #define ETH_MACL3A21R_L3A21_Msk             (0xFFFFFFFFU << ETH_MACL3A21R_L3A21_Pos)            /*!< 0xFFFFFFFF */
9819 #define ETH_MACL3A21R_L3A21                 ETH_MACL3A21R_L3A21_Msk                             /*!< Layer 3 Address 2 Field */
9820 #define ETH_MACL3A21R_L3A21_0               (0x1U << ETH_MACL3A21R_L3A21_Pos)                   /*!< 0x00000001 */
9821 #define ETH_MACL3A21R_L3A21_1               (0x2U << ETH_MACL3A21R_L3A21_Pos)                   /*!< 0x00000002 */
9822 #define ETH_MACL3A21R_L3A21_2               (0x4U << ETH_MACL3A21R_L3A21_Pos)                   /*!< 0x00000004 */
9823 #define ETH_MACL3A21R_L3A21_3               (0x8U << ETH_MACL3A21R_L3A21_Pos)                   /*!< 0x00000008 */
9824 #define ETH_MACL3A21R_L3A21_4               (0x10U << ETH_MACL3A21R_L3A21_Pos)                  /*!< 0x00000010 */
9825 #define ETH_MACL3A21R_L3A21_5               (0x20U << ETH_MACL3A21R_L3A21_Pos)                  /*!< 0x00000020 */
9826 #define ETH_MACL3A21R_L3A21_6               (0x40U << ETH_MACL3A21R_L3A21_Pos)                  /*!< 0x00000040 */
9827 #define ETH_MACL3A21R_L3A21_7               (0x80U << ETH_MACL3A21R_L3A21_Pos)                  /*!< 0x00000080 */
9828 #define ETH_MACL3A21R_L3A21_8               (0x100U << ETH_MACL3A21R_L3A21_Pos)                 /*!< 0x00000100 */
9829 #define ETH_MACL3A21R_L3A21_9               (0x200U << ETH_MACL3A21R_L3A21_Pos)                 /*!< 0x00000200 */
9830 #define ETH_MACL3A21R_L3A21_10              (0x400U << ETH_MACL3A21R_L3A21_Pos)                 /*!< 0x00000400 */
9831 #define ETH_MACL3A21R_L3A21_11              (0x800U << ETH_MACL3A21R_L3A21_Pos)                 /*!< 0x00000800 */
9832 #define ETH_MACL3A21R_L3A21_12              (0x1000U << ETH_MACL3A21R_L3A21_Pos)                /*!< 0x00001000 */
9833 #define ETH_MACL3A21R_L3A21_13              (0x2000U << ETH_MACL3A21R_L3A21_Pos)                /*!< 0x00002000 */
9834 #define ETH_MACL3A21R_L3A21_14              (0x4000U << ETH_MACL3A21R_L3A21_Pos)                /*!< 0x00004000 */
9835 #define ETH_MACL3A21R_L3A21_15              (0x8000U << ETH_MACL3A21R_L3A21_Pos)                /*!< 0x00008000 */
9836 #define ETH_MACL3A21R_L3A21_16              (0x10000U << ETH_MACL3A21R_L3A21_Pos)               /*!< 0x00010000 */
9837 #define ETH_MACL3A21R_L3A21_17              (0x20000U << ETH_MACL3A21R_L3A21_Pos)               /*!< 0x00020000 */
9838 #define ETH_MACL3A21R_L3A21_18              (0x40000U << ETH_MACL3A21R_L3A21_Pos)               /*!< 0x00040000 */
9839 #define ETH_MACL3A21R_L3A21_19              (0x80000U << ETH_MACL3A21R_L3A21_Pos)               /*!< 0x00080000 */
9840 #define ETH_MACL3A21R_L3A21_20              (0x100000U << ETH_MACL3A21R_L3A21_Pos)              /*!< 0x00100000 */
9841 #define ETH_MACL3A21R_L3A21_21              (0x200000U << ETH_MACL3A21R_L3A21_Pos)              /*!< 0x00200000 */
9842 #define ETH_MACL3A21R_L3A21_22              (0x400000U << ETH_MACL3A21R_L3A21_Pos)              /*!< 0x00400000 */
9843 #define ETH_MACL3A21R_L3A21_23              (0x800000U << ETH_MACL3A21R_L3A21_Pos)              /*!< 0x00800000 */
9844 #define ETH_MACL3A21R_L3A21_24              (0x1000000U << ETH_MACL3A21R_L3A21_Pos)             /*!< 0x01000000 */
9845 #define ETH_MACL3A21R_L3A21_25              (0x2000000U << ETH_MACL3A21R_L3A21_Pos)             /*!< 0x02000000 */
9846 #define ETH_MACL3A21R_L3A21_26              (0x4000000U << ETH_MACL3A21R_L3A21_Pos)             /*!< 0x04000000 */
9847 #define ETH_MACL3A21R_L3A21_27              (0x8000000U << ETH_MACL3A21R_L3A21_Pos)             /*!< 0x08000000 */
9848 #define ETH_MACL3A21R_L3A21_28              (0x10000000U << ETH_MACL3A21R_L3A21_Pos)            /*!< 0x10000000 */
9849 #define ETH_MACL3A21R_L3A21_29              (0x20000000U << ETH_MACL3A21R_L3A21_Pos)            /*!< 0x20000000 */
9850 #define ETH_MACL3A21R_L3A21_30              (0x40000000U << ETH_MACL3A21R_L3A21_Pos)            /*!< 0x40000000 */
9851 #define ETH_MACL3A21R_L3A21_31              (0x80000000U << ETH_MACL3A21R_L3A21_Pos)            /*!< 0x80000000 */
9852 
9853 /*************  Bit definition for ETH_MACL3A31R register  *************/
9854 #define ETH_MACL3A31R_L3A31_Pos             (0U)
9855 #define ETH_MACL3A31R_L3A31_Msk             (0xFFFFFFFFU << ETH_MACL3A31R_L3A31_Pos)            /*!< 0xFFFFFFFF */
9856 #define ETH_MACL3A31R_L3A31                 ETH_MACL3A31R_L3A31_Msk                             /*!< Layer 3 Address 3 Field */
9857 #define ETH_MACL3A31R_L3A31_0               (0x1U << ETH_MACL3A31R_L3A31_Pos)                   /*!< 0x00000001 */
9858 #define ETH_MACL3A31R_L3A31_1               (0x2U << ETH_MACL3A31R_L3A31_Pos)                   /*!< 0x00000002 */
9859 #define ETH_MACL3A31R_L3A31_2               (0x4U << ETH_MACL3A31R_L3A31_Pos)                   /*!< 0x00000004 */
9860 #define ETH_MACL3A31R_L3A31_3               (0x8U << ETH_MACL3A31R_L3A31_Pos)                   /*!< 0x00000008 */
9861 #define ETH_MACL3A31R_L3A31_4               (0x10U << ETH_MACL3A31R_L3A31_Pos)                  /*!< 0x00000010 */
9862 #define ETH_MACL3A31R_L3A31_5               (0x20U << ETH_MACL3A31R_L3A31_Pos)                  /*!< 0x00000020 */
9863 #define ETH_MACL3A31R_L3A31_6               (0x40U << ETH_MACL3A31R_L3A31_Pos)                  /*!< 0x00000040 */
9864 #define ETH_MACL3A31R_L3A31_7               (0x80U << ETH_MACL3A31R_L3A31_Pos)                  /*!< 0x00000080 */
9865 #define ETH_MACL3A31R_L3A31_8               (0x100U << ETH_MACL3A31R_L3A31_Pos)                 /*!< 0x00000100 */
9866 #define ETH_MACL3A31R_L3A31_9               (0x200U << ETH_MACL3A31R_L3A31_Pos)                 /*!< 0x00000200 */
9867 #define ETH_MACL3A31R_L3A31_10              (0x400U << ETH_MACL3A31R_L3A31_Pos)                 /*!< 0x00000400 */
9868 #define ETH_MACL3A31R_L3A31_11              (0x800U << ETH_MACL3A31R_L3A31_Pos)                 /*!< 0x00000800 */
9869 #define ETH_MACL3A31R_L3A31_12              (0x1000U << ETH_MACL3A31R_L3A31_Pos)                /*!< 0x00001000 */
9870 #define ETH_MACL3A31R_L3A31_13              (0x2000U << ETH_MACL3A31R_L3A31_Pos)                /*!< 0x00002000 */
9871 #define ETH_MACL3A31R_L3A31_14              (0x4000U << ETH_MACL3A31R_L3A31_Pos)                /*!< 0x00004000 */
9872 #define ETH_MACL3A31R_L3A31_15              (0x8000U << ETH_MACL3A31R_L3A31_Pos)                /*!< 0x00008000 */
9873 #define ETH_MACL3A31R_L3A31_16              (0x10000U << ETH_MACL3A31R_L3A31_Pos)               /*!< 0x00010000 */
9874 #define ETH_MACL3A31R_L3A31_17              (0x20000U << ETH_MACL3A31R_L3A31_Pos)               /*!< 0x00020000 */
9875 #define ETH_MACL3A31R_L3A31_18              (0x40000U << ETH_MACL3A31R_L3A31_Pos)               /*!< 0x00040000 */
9876 #define ETH_MACL3A31R_L3A31_19              (0x80000U << ETH_MACL3A31R_L3A31_Pos)               /*!< 0x00080000 */
9877 #define ETH_MACL3A31R_L3A31_20              (0x100000U << ETH_MACL3A31R_L3A31_Pos)              /*!< 0x00100000 */
9878 #define ETH_MACL3A31R_L3A31_21              (0x200000U << ETH_MACL3A31R_L3A31_Pos)              /*!< 0x00200000 */
9879 #define ETH_MACL3A31R_L3A31_22              (0x400000U << ETH_MACL3A31R_L3A31_Pos)              /*!< 0x00400000 */
9880 #define ETH_MACL3A31R_L3A31_23              (0x800000U << ETH_MACL3A31R_L3A31_Pos)              /*!< 0x00800000 */
9881 #define ETH_MACL3A31R_L3A31_24              (0x1000000U << ETH_MACL3A31R_L3A31_Pos)             /*!< 0x01000000 */
9882 #define ETH_MACL3A31R_L3A31_25              (0x2000000U << ETH_MACL3A31R_L3A31_Pos)             /*!< 0x02000000 */
9883 #define ETH_MACL3A31R_L3A31_26              (0x4000000U << ETH_MACL3A31R_L3A31_Pos)             /*!< 0x04000000 */
9884 #define ETH_MACL3A31R_L3A31_27              (0x8000000U << ETH_MACL3A31R_L3A31_Pos)             /*!< 0x08000000 */
9885 #define ETH_MACL3A31R_L3A31_28              (0x10000000U << ETH_MACL3A31R_L3A31_Pos)            /*!< 0x10000000 */
9886 #define ETH_MACL3A31R_L3A31_29              (0x20000000U << ETH_MACL3A31R_L3A31_Pos)            /*!< 0x20000000 */
9887 #define ETH_MACL3A31R_L3A31_30              (0x40000000U << ETH_MACL3A31R_L3A31_Pos)            /*!< 0x40000000 */
9888 #define ETH_MACL3A31R_L3A31_31              (0x80000000U << ETH_MACL3A31R_L3A31_Pos)            /*!< 0x80000000 */
9889 
9890 /*************  Bit definition for ETH_MACARPAR register  **************/
9891 #define ETH_MACARPAR_ARPPA_Pos              (0U)
9892 #define ETH_MACARPAR_ARPPA_Msk              (0xFFFFFFFFU << ETH_MACARPAR_ARPPA_Pos)             /*!< 0xFFFFFFFF */
9893 #define ETH_MACARPAR_ARPPA                  ETH_MACARPAR_ARPPA_Msk                              /*!< ARP Protocol Address */
9894 #define ETH_MACARPAR_ARPPA_0                (0x1U << ETH_MACARPAR_ARPPA_Pos)                    /*!< 0x00000001 */
9895 #define ETH_MACARPAR_ARPPA_1                (0x2U << ETH_MACARPAR_ARPPA_Pos)                    /*!< 0x00000002 */
9896 #define ETH_MACARPAR_ARPPA_2                (0x4U << ETH_MACARPAR_ARPPA_Pos)                    /*!< 0x00000004 */
9897 #define ETH_MACARPAR_ARPPA_3                (0x8U << ETH_MACARPAR_ARPPA_Pos)                    /*!< 0x00000008 */
9898 #define ETH_MACARPAR_ARPPA_4                (0x10U << ETH_MACARPAR_ARPPA_Pos)                   /*!< 0x00000010 */
9899 #define ETH_MACARPAR_ARPPA_5                (0x20U << ETH_MACARPAR_ARPPA_Pos)                   /*!< 0x00000020 */
9900 #define ETH_MACARPAR_ARPPA_6                (0x40U << ETH_MACARPAR_ARPPA_Pos)                   /*!< 0x00000040 */
9901 #define ETH_MACARPAR_ARPPA_7                (0x80U << ETH_MACARPAR_ARPPA_Pos)                   /*!< 0x00000080 */
9902 #define ETH_MACARPAR_ARPPA_8                (0x100U << ETH_MACARPAR_ARPPA_Pos)                  /*!< 0x00000100 */
9903 #define ETH_MACARPAR_ARPPA_9                (0x200U << ETH_MACARPAR_ARPPA_Pos)                  /*!< 0x00000200 */
9904 #define ETH_MACARPAR_ARPPA_10               (0x400U << ETH_MACARPAR_ARPPA_Pos)                  /*!< 0x00000400 */
9905 #define ETH_MACARPAR_ARPPA_11               (0x800U << ETH_MACARPAR_ARPPA_Pos)                  /*!< 0x00000800 */
9906 #define ETH_MACARPAR_ARPPA_12               (0x1000U << ETH_MACARPAR_ARPPA_Pos)                 /*!< 0x00001000 */
9907 #define ETH_MACARPAR_ARPPA_13               (0x2000U << ETH_MACARPAR_ARPPA_Pos)                 /*!< 0x00002000 */
9908 #define ETH_MACARPAR_ARPPA_14               (0x4000U << ETH_MACARPAR_ARPPA_Pos)                 /*!< 0x00004000 */
9909 #define ETH_MACARPAR_ARPPA_15               (0x8000U << ETH_MACARPAR_ARPPA_Pos)                 /*!< 0x00008000 */
9910 #define ETH_MACARPAR_ARPPA_16               (0x10000U << ETH_MACARPAR_ARPPA_Pos)                /*!< 0x00010000 */
9911 #define ETH_MACARPAR_ARPPA_17               (0x20000U << ETH_MACARPAR_ARPPA_Pos)                /*!< 0x00020000 */
9912 #define ETH_MACARPAR_ARPPA_18               (0x40000U << ETH_MACARPAR_ARPPA_Pos)                /*!< 0x00040000 */
9913 #define ETH_MACARPAR_ARPPA_19               (0x80000U << ETH_MACARPAR_ARPPA_Pos)                /*!< 0x00080000 */
9914 #define ETH_MACARPAR_ARPPA_20               (0x100000U << ETH_MACARPAR_ARPPA_Pos)               /*!< 0x00100000 */
9915 #define ETH_MACARPAR_ARPPA_21               (0x200000U << ETH_MACARPAR_ARPPA_Pos)               /*!< 0x00200000 */
9916 #define ETH_MACARPAR_ARPPA_22               (0x400000U << ETH_MACARPAR_ARPPA_Pos)               /*!< 0x00400000 */
9917 #define ETH_MACARPAR_ARPPA_23               (0x800000U << ETH_MACARPAR_ARPPA_Pos)               /*!< 0x00800000 */
9918 #define ETH_MACARPAR_ARPPA_24               (0x1000000U << ETH_MACARPAR_ARPPA_Pos)              /*!< 0x01000000 */
9919 #define ETH_MACARPAR_ARPPA_25               (0x2000000U << ETH_MACARPAR_ARPPA_Pos)              /*!< 0x02000000 */
9920 #define ETH_MACARPAR_ARPPA_26               (0x4000000U << ETH_MACARPAR_ARPPA_Pos)              /*!< 0x04000000 */
9921 #define ETH_MACARPAR_ARPPA_27               (0x8000000U << ETH_MACARPAR_ARPPA_Pos)              /*!< 0x08000000 */
9922 #define ETH_MACARPAR_ARPPA_28               (0x10000000U << ETH_MACARPAR_ARPPA_Pos)             /*!< 0x10000000 */
9923 #define ETH_MACARPAR_ARPPA_29               (0x20000000U << ETH_MACARPAR_ARPPA_Pos)             /*!< 0x20000000 */
9924 #define ETH_MACARPAR_ARPPA_30               (0x40000000U << ETH_MACARPAR_ARPPA_Pos)             /*!< 0x40000000 */
9925 #define ETH_MACARPAR_ARPPA_31               (0x80000000U << ETH_MACARPAR_ARPPA_Pos)             /*!< 0x80000000 */
9926 
9927 /**************  Bit definition for ETH_MACTSCR register  **************/
9928 #define ETH_MACTSCR_TSENA_Pos               (0U)
9929 #define ETH_MACTSCR_TSENA_Msk               (0x1U << ETH_MACTSCR_TSENA_Pos)                     /*!< 0x00000001 */
9930 #define ETH_MACTSCR_TSENA                   ETH_MACTSCR_TSENA_Msk                               /*!< Enable Timestamp */
9931 #define ETH_MACTSCR_TSCFUPDT_Pos            (1U)
9932 #define ETH_MACTSCR_TSCFUPDT_Msk            (0x1U << ETH_MACTSCR_TSCFUPDT_Pos)                  /*!< 0x00000002 */
9933 #define ETH_MACTSCR_TSCFUPDT                ETH_MACTSCR_TSCFUPDT_Msk                            /*!< Fine or Coarse Timestamp Update */
9934 #define ETH_MACTSCR_TSINIT_Pos              (2U)
9935 #define ETH_MACTSCR_TSINIT_Msk              (0x1U << ETH_MACTSCR_TSINIT_Pos)                    /*!< 0x00000004 */
9936 #define ETH_MACTSCR_TSINIT                  ETH_MACTSCR_TSINIT_Msk                              /*!< Initialize Timestamp */
9937 #define ETH_MACTSCR_TSUPDT_Pos              (3U)
9938 #define ETH_MACTSCR_TSUPDT_Msk              (0x1U << ETH_MACTSCR_TSUPDT_Pos)                    /*!< 0x00000008 */
9939 #define ETH_MACTSCR_TSUPDT                  ETH_MACTSCR_TSUPDT_Msk                              /*!< Update Timestamp */
9940 #define ETH_MACTSCR_TSADDREG_Pos            (5U)
9941 #define ETH_MACTSCR_TSADDREG_Msk            (0x1U << ETH_MACTSCR_TSADDREG_Pos)                  /*!< 0x00000020 */
9942 #define ETH_MACTSCR_TSADDREG                ETH_MACTSCR_TSADDREG_Msk                            /*!< Update Addend Register */
9943 #define ETH_MACTSCR_TSENALL_Pos             (8U)
9944 #define ETH_MACTSCR_TSENALL_Msk             (0x1U << ETH_MACTSCR_TSENALL_Pos)                   /*!< 0x00000100 */
9945 #define ETH_MACTSCR_TSENALL                 ETH_MACTSCR_TSENALL_Msk                             /*!< Enable Timestamp for All Packets */
9946 #define ETH_MACTSCR_TSCTRLSSR_Pos           (9U)
9947 #define ETH_MACTSCR_TSCTRLSSR_Msk           (0x1U << ETH_MACTSCR_TSCTRLSSR_Pos)                 /*!< 0x00000200 */
9948 #define ETH_MACTSCR_TSCTRLSSR               ETH_MACTSCR_TSCTRLSSR_Msk                           /*!< Timestamp Digital or Binary Rollover Control */
9949 #define ETH_MACTSCR_TSVER2ENA_Pos           (10U)
9950 #define ETH_MACTSCR_TSVER2ENA_Msk           (0x1U << ETH_MACTSCR_TSVER2ENA_Pos)                 /*!< 0x00000400 */
9951 #define ETH_MACTSCR_TSVER2ENA               ETH_MACTSCR_TSVER2ENA_Msk                           /*!< Enable PTP Packet Processing for Version 2 Format */
9952 #define ETH_MACTSCR_TSIPENA_Pos             (11U)
9953 #define ETH_MACTSCR_TSIPENA_Msk             (0x1U << ETH_MACTSCR_TSIPENA_Pos)                   /*!< 0x00000800 */
9954 #define ETH_MACTSCR_TSIPENA                 ETH_MACTSCR_TSIPENA_Msk                             /*!< Enable Processing of PTP over Ethernet Packets */
9955 #define ETH_MACTSCR_TSIPV6ENA_Pos           (12U)
9956 #define ETH_MACTSCR_TSIPV6ENA_Msk           (0x1U << ETH_MACTSCR_TSIPV6ENA_Pos)                 /*!< 0x00001000 */
9957 #define ETH_MACTSCR_TSIPV6ENA               ETH_MACTSCR_TSIPV6ENA_Msk                           /*!< Enable Processing of PTP Packets Sent over IPv6-UDP */
9958 #define ETH_MACTSCR_TSIPV4ENA_Pos           (13U)
9959 #define ETH_MACTSCR_TSIPV4ENA_Msk           (0x1U << ETH_MACTSCR_TSIPV4ENA_Pos)                 /*!< 0x00002000 */
9960 #define ETH_MACTSCR_TSIPV4ENA               ETH_MACTSCR_TSIPV4ENA_Msk                           /*!< Enable Processing of PTP Packets Sent over IPv4-UDP */
9961 #define ETH_MACTSCR_TSEVNTENA_Pos           (14U)
9962 #define ETH_MACTSCR_TSEVNTENA_Msk           (0x1U << ETH_MACTSCR_TSEVNTENA_Pos)                 /*!< 0x00004000 */
9963 #define ETH_MACTSCR_TSEVNTENA               ETH_MACTSCR_TSEVNTENA_Msk                           /*!< Enable Timestamp Snapshot for Event Messages */
9964 #define ETH_MACTSCR_TSMSTRENA_Pos           (15U)
9965 #define ETH_MACTSCR_TSMSTRENA_Msk           (0x1U << ETH_MACTSCR_TSMSTRENA_Pos)                 /*!< 0x00008000 */
9966 #define ETH_MACTSCR_TSMSTRENA               ETH_MACTSCR_TSMSTRENA_Msk                           /*!< Enable Snapshot for Messages Relevant to Master */
9967 #define ETH_MACTSCR_SNAPTYPSEL_Pos          (16U)
9968 #define ETH_MACTSCR_SNAPTYPSEL_Msk          (0x3U << ETH_MACTSCR_SNAPTYPSEL_Pos)                /*!< 0x00030000 */
9969 #define ETH_MACTSCR_SNAPTYPSEL              ETH_MACTSCR_SNAPTYPSEL_Msk                          /*!< Select PTP packets for Taking Snapshots */
9970 #define ETH_MACTSCR_SNAPTYPSEL_0            (0x1U << ETH_MACTSCR_SNAPTYPSEL_Pos)            /*!< 0x00010000 */
9971 #define ETH_MACTSCR_SNAPTYPSEL_1            (0x2U << ETH_MACTSCR_SNAPTYPSEL_Pos)            /*!< 0x00020000 */
9972 #define ETH_MACTSCR_TSENMACADDR_Pos         (18U)
9973 #define ETH_MACTSCR_TSENMACADDR_Msk         (0x1U << ETH_MACTSCR_TSENMACADDR_Pos)               /*!< 0x00040000 */
9974 #define ETH_MACTSCR_TSENMACADDR             ETH_MACTSCR_TSENMACADDR_Msk                         /*!< Enable MAC Address for PTP Packet Filtering */
9975 #define ETH_MACTSCR_CSC_Pos                 (19U)
9976 #define ETH_MACTSCR_CSC_Msk                 (0x1U << ETH_MACTSCR_CSC_Pos)                       /*!< 0x00080000 */
9977 #define ETH_MACTSCR_CSC                     ETH_MACTSCR_CSC_Msk                                 /*!< Enable checksum correction during OST for PTP over UDP/IPv4 packets */
9978 #define ETH_MACTSCR_TXTSSTSM_Pos            (24U)
9979 #define ETH_MACTSCR_TXTSSTSM_Msk            (0x1U << ETH_MACTSCR_TXTSSTSM_Pos)                  /*!< 0x01000000 */
9980 #define ETH_MACTSCR_TXTSSTSM                ETH_MACTSCR_TXTSSTSM_Msk                            /*!< Transmit Timestamp Status Mode */
9981 #define ETH_MACTSCR_AV8021ASMEN_Pos         (28U)
9982 #define ETH_MACTSCR_AV8021ASMEN_Msk         (0x1U << ETH_MACTSCR_AV8021ASMEN_Pos)               /*!< 0x10000000 */
9983 #define ETH_MACTSCR_AV8021ASMEN             ETH_MACTSCR_AV8021ASMEN_Msk                         /*!< AV 802.1AS Mode Enable */
9984 
9985 /**************  Bit definition for ETH_MACSSIR register  **************/
9986 #define ETH_MACSSIR_SNSINC_Pos              (8U)
9987 #define ETH_MACSSIR_SNSINC_Msk              (0xFFU << ETH_MACSSIR_SNSINC_Pos)                   /*!< 0x0000FF00 */
9988 #define ETH_MACSSIR_SNSINC                  ETH_MACSSIR_SNSINC_Msk                              /*!< Sub-nanosecond Increment Value */
9989 #define ETH_MACSSIR_SNSINC_0                (0x1U << ETH_MACSSIR_SNSINC_Pos)                  /*!< 0x00000100 */
9990 #define ETH_MACSSIR_SNSINC_1                (0x2U << ETH_MACSSIR_SNSINC_Pos)                  /*!< 0x00000200 */
9991 #define ETH_MACSSIR_SNSINC_2                (0x4U << ETH_MACSSIR_SNSINC_Pos)                  /*!< 0x00000400 */
9992 #define ETH_MACSSIR_SNSINC_3                (0x8U << ETH_MACSSIR_SNSINC_Pos)                  /*!< 0x00000800 */
9993 #define ETH_MACSSIR_SNSINC_4                (0x10U << ETH_MACSSIR_SNSINC_Pos)                 /*!< 0x00001000 */
9994 #define ETH_MACSSIR_SNSINC_5                (0x20U << ETH_MACSSIR_SNSINC_Pos)                 /*!< 0x00002000 */
9995 #define ETH_MACSSIR_SNSINC_6                (0x40U << ETH_MACSSIR_SNSINC_Pos)                 /*!< 0x00004000 */
9996 #define ETH_MACSSIR_SNSINC_7                (0x80U << ETH_MACSSIR_SNSINC_Pos)                 /*!< 0x00008000 */
9997 #define ETH_MACSSIR_SSINC_Pos               (16U)
9998 #define ETH_MACSSIR_SSINC_Msk               (0xFFU << ETH_MACSSIR_SSINC_Pos)                    /*!< 0x00FF0000 */
9999 #define ETH_MACSSIR_SSINC                   ETH_MACSSIR_SSINC_Msk                               /*!< Sub-second Increment Value */
10000 #define ETH_MACSSIR_SSINC_0                 (0x1U << ETH_MACSSIR_SSINC_Pos)                 /*!< 0x00010000 */
10001 #define ETH_MACSSIR_SSINC_1                 (0x2U << ETH_MACSSIR_SSINC_Pos)                 /*!< 0x00020000 */
10002 #define ETH_MACSSIR_SSINC_2                 (0x4U << ETH_MACSSIR_SSINC_Pos)                 /*!< 0x00040000 */
10003 #define ETH_MACSSIR_SSINC_3                 (0x8U << ETH_MACSSIR_SSINC_Pos)                 /*!< 0x00080000 */
10004 #define ETH_MACSSIR_SSINC_4                 (0x10U << ETH_MACSSIR_SSINC_Pos)                /*!< 0x00100000 */
10005 #define ETH_MACSSIR_SSINC_5                 (0x20U << ETH_MACSSIR_SSINC_Pos)                /*!< 0x00200000 */
10006 #define ETH_MACSSIR_SSINC_6                 (0x40U << ETH_MACSSIR_SSINC_Pos)                /*!< 0x00400000 */
10007 #define ETH_MACSSIR_SSINC_7                 (0x80U << ETH_MACSSIR_SSINC_Pos)                /*!< 0x00800000 */
10008 
10009 /**************  Bit definition for ETH_MACSTSR register  **************/
10010 #define ETH_MACSTSR_TSS_Pos                 (0U)
10011 #define ETH_MACSTSR_TSS_Msk                 (0xFFFFFFFFU << ETH_MACSTSR_TSS_Pos)                /*!< 0xFFFFFFFF */
10012 #define ETH_MACSTSR_TSS                     ETH_MACSTSR_TSS_Msk                                 /*!< Timestamp Second */
10013 #define ETH_MACSTSR_TSS_0                   (0x1U << ETH_MACSTSR_TSS_Pos)                       /*!< 0x00000001 */
10014 #define ETH_MACSTSR_TSS_1                   (0x2U << ETH_MACSTSR_TSS_Pos)                       /*!< 0x00000002 */
10015 #define ETH_MACSTSR_TSS_2                   (0x4U << ETH_MACSTSR_TSS_Pos)                       /*!< 0x00000004 */
10016 #define ETH_MACSTSR_TSS_3                   (0x8U << ETH_MACSTSR_TSS_Pos)                       /*!< 0x00000008 */
10017 #define ETH_MACSTSR_TSS_4                   (0x10U << ETH_MACSTSR_TSS_Pos)                      /*!< 0x00000010 */
10018 #define ETH_MACSTSR_TSS_5                   (0x20U << ETH_MACSTSR_TSS_Pos)                      /*!< 0x00000020 */
10019 #define ETH_MACSTSR_TSS_6                   (0x40U << ETH_MACSTSR_TSS_Pos)                      /*!< 0x00000040 */
10020 #define ETH_MACSTSR_TSS_7                   (0x80U << ETH_MACSTSR_TSS_Pos)                      /*!< 0x00000080 */
10021 #define ETH_MACSTSR_TSS_8                   (0x100U << ETH_MACSTSR_TSS_Pos)                     /*!< 0x00000100 */
10022 #define ETH_MACSTSR_TSS_9                   (0x200U << ETH_MACSTSR_TSS_Pos)                     /*!< 0x00000200 */
10023 #define ETH_MACSTSR_TSS_10                  (0x400U << ETH_MACSTSR_TSS_Pos)                     /*!< 0x00000400 */
10024 #define ETH_MACSTSR_TSS_11                  (0x800U << ETH_MACSTSR_TSS_Pos)                     /*!< 0x00000800 */
10025 #define ETH_MACSTSR_TSS_12                  (0x1000U << ETH_MACSTSR_TSS_Pos)                    /*!< 0x00001000 */
10026 #define ETH_MACSTSR_TSS_13                  (0x2000U << ETH_MACSTSR_TSS_Pos)                    /*!< 0x00002000 */
10027 #define ETH_MACSTSR_TSS_14                  (0x4000U << ETH_MACSTSR_TSS_Pos)                    /*!< 0x00004000 */
10028 #define ETH_MACSTSR_TSS_15                  (0x8000U << ETH_MACSTSR_TSS_Pos)                    /*!< 0x00008000 */
10029 #define ETH_MACSTSR_TSS_16                  (0x10000U << ETH_MACSTSR_TSS_Pos)                   /*!< 0x00010000 */
10030 #define ETH_MACSTSR_TSS_17                  (0x20000U << ETH_MACSTSR_TSS_Pos)                   /*!< 0x00020000 */
10031 #define ETH_MACSTSR_TSS_18                  (0x40000U << ETH_MACSTSR_TSS_Pos)                   /*!< 0x00040000 */
10032 #define ETH_MACSTSR_TSS_19                  (0x80000U << ETH_MACSTSR_TSS_Pos)                   /*!< 0x00080000 */
10033 #define ETH_MACSTSR_TSS_20                  (0x100000U << ETH_MACSTSR_TSS_Pos)                  /*!< 0x00100000 */
10034 #define ETH_MACSTSR_TSS_21                  (0x200000U << ETH_MACSTSR_TSS_Pos)                  /*!< 0x00200000 */
10035 #define ETH_MACSTSR_TSS_22                  (0x400000U << ETH_MACSTSR_TSS_Pos)                  /*!< 0x00400000 */
10036 #define ETH_MACSTSR_TSS_23                  (0x800000U << ETH_MACSTSR_TSS_Pos)                  /*!< 0x00800000 */
10037 #define ETH_MACSTSR_TSS_24                  (0x1000000U << ETH_MACSTSR_TSS_Pos)                 /*!< 0x01000000 */
10038 #define ETH_MACSTSR_TSS_25                  (0x2000000U << ETH_MACSTSR_TSS_Pos)                 /*!< 0x02000000 */
10039 #define ETH_MACSTSR_TSS_26                  (0x4000000U << ETH_MACSTSR_TSS_Pos)                 /*!< 0x04000000 */
10040 #define ETH_MACSTSR_TSS_27                  (0x8000000U << ETH_MACSTSR_TSS_Pos)                 /*!< 0x08000000 */
10041 #define ETH_MACSTSR_TSS_28                  (0x10000000U << ETH_MACSTSR_TSS_Pos)                /*!< 0x10000000 */
10042 #define ETH_MACSTSR_TSS_29                  (0x20000000U << ETH_MACSTSR_TSS_Pos)                /*!< 0x20000000 */
10043 #define ETH_MACSTSR_TSS_30                  (0x40000000U << ETH_MACSTSR_TSS_Pos)                /*!< 0x40000000 */
10044 #define ETH_MACSTSR_TSS_31                  (0x80000000U << ETH_MACSTSR_TSS_Pos)                /*!< 0x80000000 */
10045 
10046 /**************  Bit definition for ETH_MACSTNR register  **************/
10047 #define ETH_MACSTNR_TSSS_Pos                (0U)
10048 #define ETH_MACSTNR_TSSS_Msk                (0x7FFFFFFFU << ETH_MACSTNR_TSSS_Pos)               /*!< 0x7FFFFFFF */
10049 #define ETH_MACSTNR_TSSS                    ETH_MACSTNR_TSSS_Msk                                /*!< Timestamp Sub-seconds */
10050 #define ETH_MACSTNR_TSSS_0                  (0x1U << ETH_MACSTNR_TSSS_Pos)                      /*!< 0x00000001 */
10051 #define ETH_MACSTNR_TSSS_1                  (0x2U << ETH_MACSTNR_TSSS_Pos)                      /*!< 0x00000002 */
10052 #define ETH_MACSTNR_TSSS_2                  (0x4U << ETH_MACSTNR_TSSS_Pos)                      /*!< 0x00000004 */
10053 #define ETH_MACSTNR_TSSS_3                  (0x8U << ETH_MACSTNR_TSSS_Pos)                      /*!< 0x00000008 */
10054 #define ETH_MACSTNR_TSSS_4                  (0x10U << ETH_MACSTNR_TSSS_Pos)                     /*!< 0x00000010 */
10055 #define ETH_MACSTNR_TSSS_5                  (0x20U << ETH_MACSTNR_TSSS_Pos)                     /*!< 0x00000020 */
10056 #define ETH_MACSTNR_TSSS_6                  (0x40U << ETH_MACSTNR_TSSS_Pos)                     /*!< 0x00000040 */
10057 #define ETH_MACSTNR_TSSS_7                  (0x80U << ETH_MACSTNR_TSSS_Pos)                     /*!< 0x00000080 */
10058 #define ETH_MACSTNR_TSSS_8                  (0x100U << ETH_MACSTNR_TSSS_Pos)                    /*!< 0x00000100 */
10059 #define ETH_MACSTNR_TSSS_9                  (0x200U << ETH_MACSTNR_TSSS_Pos)                    /*!< 0x00000200 */
10060 #define ETH_MACSTNR_TSSS_10                 (0x400U << ETH_MACSTNR_TSSS_Pos)                    /*!< 0x00000400 */
10061 #define ETH_MACSTNR_TSSS_11                 (0x800U << ETH_MACSTNR_TSSS_Pos)                    /*!< 0x00000800 */
10062 #define ETH_MACSTNR_TSSS_12                 (0x1000U << ETH_MACSTNR_TSSS_Pos)                   /*!< 0x00001000 */
10063 #define ETH_MACSTNR_TSSS_13                 (0x2000U << ETH_MACSTNR_TSSS_Pos)                   /*!< 0x00002000 */
10064 #define ETH_MACSTNR_TSSS_14                 (0x4000U << ETH_MACSTNR_TSSS_Pos)                   /*!< 0x00004000 */
10065 #define ETH_MACSTNR_TSSS_15                 (0x8000U << ETH_MACSTNR_TSSS_Pos)                   /*!< 0x00008000 */
10066 #define ETH_MACSTNR_TSSS_16                 (0x10000U << ETH_MACSTNR_TSSS_Pos)                  /*!< 0x00010000 */
10067 #define ETH_MACSTNR_TSSS_17                 (0x20000U << ETH_MACSTNR_TSSS_Pos)                  /*!< 0x00020000 */
10068 #define ETH_MACSTNR_TSSS_18                 (0x40000U << ETH_MACSTNR_TSSS_Pos)                  /*!< 0x00040000 */
10069 #define ETH_MACSTNR_TSSS_19                 (0x80000U << ETH_MACSTNR_TSSS_Pos)                  /*!< 0x00080000 */
10070 #define ETH_MACSTNR_TSSS_20                 (0x100000U << ETH_MACSTNR_TSSS_Pos)                 /*!< 0x00100000 */
10071 #define ETH_MACSTNR_TSSS_21                 (0x200000U << ETH_MACSTNR_TSSS_Pos)                 /*!< 0x00200000 */
10072 #define ETH_MACSTNR_TSSS_22                 (0x400000U << ETH_MACSTNR_TSSS_Pos)                 /*!< 0x00400000 */
10073 #define ETH_MACSTNR_TSSS_23                 (0x800000U << ETH_MACSTNR_TSSS_Pos)                 /*!< 0x00800000 */
10074 #define ETH_MACSTNR_TSSS_24                 (0x1000000U << ETH_MACSTNR_TSSS_Pos)                /*!< 0x01000000 */
10075 #define ETH_MACSTNR_TSSS_25                 (0x2000000U << ETH_MACSTNR_TSSS_Pos)                /*!< 0x02000000 */
10076 #define ETH_MACSTNR_TSSS_26                 (0x4000000U << ETH_MACSTNR_TSSS_Pos)                /*!< 0x04000000 */
10077 #define ETH_MACSTNR_TSSS_27                 (0x8000000U << ETH_MACSTNR_TSSS_Pos)                /*!< 0x08000000 */
10078 #define ETH_MACSTNR_TSSS_28                 (0x10000000U << ETH_MACSTNR_TSSS_Pos)               /*!< 0x10000000 */
10079 #define ETH_MACSTNR_TSSS_29                 (0x20000000U << ETH_MACSTNR_TSSS_Pos)               /*!< 0x20000000 */
10080 #define ETH_MACSTNR_TSSS_30                 (0x40000000U << ETH_MACSTNR_TSSS_Pos)               /*!< 0x40000000 */
10081 
10082 /*************  Bit definition for ETH_MACSTSUR register  **************/
10083 #define ETH_MACSTSUR_TSS_Pos                (0U)
10084 #define ETH_MACSTSUR_TSS_Msk                (0xFFFFFFFFU << ETH_MACSTSUR_TSS_Pos)               /*!< 0xFFFFFFFF */
10085 #define ETH_MACSTSUR_TSS                    ETH_MACSTSUR_TSS_Msk                                /*!< Timestamp Seconds */
10086 #define ETH_MACSTSUR_TSS_0                  (0x1U << ETH_MACSTSUR_TSS_Pos)                      /*!< 0x00000001 */
10087 #define ETH_MACSTSUR_TSS_1                  (0x2U << ETH_MACSTSUR_TSS_Pos)                      /*!< 0x00000002 */
10088 #define ETH_MACSTSUR_TSS_2                  (0x4U << ETH_MACSTSUR_TSS_Pos)                      /*!< 0x00000004 */
10089 #define ETH_MACSTSUR_TSS_3                  (0x8U << ETH_MACSTSUR_TSS_Pos)                      /*!< 0x00000008 */
10090 #define ETH_MACSTSUR_TSS_4                  (0x10U << ETH_MACSTSUR_TSS_Pos)                     /*!< 0x00000010 */
10091 #define ETH_MACSTSUR_TSS_5                  (0x20U << ETH_MACSTSUR_TSS_Pos)                     /*!< 0x00000020 */
10092 #define ETH_MACSTSUR_TSS_6                  (0x40U << ETH_MACSTSUR_TSS_Pos)                     /*!< 0x00000040 */
10093 #define ETH_MACSTSUR_TSS_7                  (0x80U << ETH_MACSTSUR_TSS_Pos)                     /*!< 0x00000080 */
10094 #define ETH_MACSTSUR_TSS_8                  (0x100U << ETH_MACSTSUR_TSS_Pos)                    /*!< 0x00000100 */
10095 #define ETH_MACSTSUR_TSS_9                  (0x200U << ETH_MACSTSUR_TSS_Pos)                    /*!< 0x00000200 */
10096 #define ETH_MACSTSUR_TSS_10                 (0x400U << ETH_MACSTSUR_TSS_Pos)                    /*!< 0x00000400 */
10097 #define ETH_MACSTSUR_TSS_11                 (0x800U << ETH_MACSTSUR_TSS_Pos)                    /*!< 0x00000800 */
10098 #define ETH_MACSTSUR_TSS_12                 (0x1000U << ETH_MACSTSUR_TSS_Pos)                   /*!< 0x00001000 */
10099 #define ETH_MACSTSUR_TSS_13                 (0x2000U << ETH_MACSTSUR_TSS_Pos)                   /*!< 0x00002000 */
10100 #define ETH_MACSTSUR_TSS_14                 (0x4000U << ETH_MACSTSUR_TSS_Pos)                   /*!< 0x00004000 */
10101 #define ETH_MACSTSUR_TSS_15                 (0x8000U << ETH_MACSTSUR_TSS_Pos)                   /*!< 0x00008000 */
10102 #define ETH_MACSTSUR_TSS_16                 (0x10000U << ETH_MACSTSUR_TSS_Pos)                  /*!< 0x00010000 */
10103 #define ETH_MACSTSUR_TSS_17                 (0x20000U << ETH_MACSTSUR_TSS_Pos)                  /*!< 0x00020000 */
10104 #define ETH_MACSTSUR_TSS_18                 (0x40000U << ETH_MACSTSUR_TSS_Pos)                  /*!< 0x00040000 */
10105 #define ETH_MACSTSUR_TSS_19                 (0x80000U << ETH_MACSTSUR_TSS_Pos)                  /*!< 0x00080000 */
10106 #define ETH_MACSTSUR_TSS_20                 (0x100000U << ETH_MACSTSUR_TSS_Pos)                 /*!< 0x00100000 */
10107 #define ETH_MACSTSUR_TSS_21                 (0x200000U << ETH_MACSTSUR_TSS_Pos)                 /*!< 0x00200000 */
10108 #define ETH_MACSTSUR_TSS_22                 (0x400000U << ETH_MACSTSUR_TSS_Pos)                 /*!< 0x00400000 */
10109 #define ETH_MACSTSUR_TSS_23                 (0x800000U << ETH_MACSTSUR_TSS_Pos)                 /*!< 0x00800000 */
10110 #define ETH_MACSTSUR_TSS_24                 (0x1000000U << ETH_MACSTSUR_TSS_Pos)                /*!< 0x01000000 */
10111 #define ETH_MACSTSUR_TSS_25                 (0x2000000U << ETH_MACSTSUR_TSS_Pos)                /*!< 0x02000000 */
10112 #define ETH_MACSTSUR_TSS_26                 (0x4000000U << ETH_MACSTSUR_TSS_Pos)                /*!< 0x04000000 */
10113 #define ETH_MACSTSUR_TSS_27                 (0x8000000U << ETH_MACSTSUR_TSS_Pos)                /*!< 0x08000000 */
10114 #define ETH_MACSTSUR_TSS_28                 (0x10000000U << ETH_MACSTSUR_TSS_Pos)               /*!< 0x10000000 */
10115 #define ETH_MACSTSUR_TSS_29                 (0x20000000U << ETH_MACSTSUR_TSS_Pos)               /*!< 0x20000000 */
10116 #define ETH_MACSTSUR_TSS_30                 (0x40000000U << ETH_MACSTSUR_TSS_Pos)               /*!< 0x40000000 */
10117 #define ETH_MACSTSUR_TSS_31                 (0x80000000U << ETH_MACSTSUR_TSS_Pos)               /*!< 0x80000000 */
10118 
10119 /*************  Bit definition for ETH_MACSTNUR register  **************/
10120 #define ETH_MACSTNUR_TSSS_Pos               (0U)
10121 #define ETH_MACSTNUR_TSSS_Msk               (0x7FFFFFFFU << ETH_MACSTNUR_TSSS_Pos)              /*!< 0x7FFFFFFF */
10122 #define ETH_MACSTNUR_TSSS                   ETH_MACSTNUR_TSSS_Msk                               /*!< Timestamp Sub-seconds */
10123 #define ETH_MACSTNUR_TSSS_0                 (0x1U << ETH_MACSTNUR_TSSS_Pos)                     /*!< 0x00000001 */
10124 #define ETH_MACSTNUR_TSSS_1                 (0x2U << ETH_MACSTNUR_TSSS_Pos)                     /*!< 0x00000002 */
10125 #define ETH_MACSTNUR_TSSS_2                 (0x4U << ETH_MACSTNUR_TSSS_Pos)                     /*!< 0x00000004 */
10126 #define ETH_MACSTNUR_TSSS_3                 (0x8U << ETH_MACSTNUR_TSSS_Pos)                     /*!< 0x00000008 */
10127 #define ETH_MACSTNUR_TSSS_4                 (0x10U << ETH_MACSTNUR_TSSS_Pos)                    /*!< 0x00000010 */
10128 #define ETH_MACSTNUR_TSSS_5                 (0x20U << ETH_MACSTNUR_TSSS_Pos)                    /*!< 0x00000020 */
10129 #define ETH_MACSTNUR_TSSS_6                 (0x40U << ETH_MACSTNUR_TSSS_Pos)                    /*!< 0x00000040 */
10130 #define ETH_MACSTNUR_TSSS_7                 (0x80U << ETH_MACSTNUR_TSSS_Pos)                    /*!< 0x00000080 */
10131 #define ETH_MACSTNUR_TSSS_8                 (0x100U << ETH_MACSTNUR_TSSS_Pos)                   /*!< 0x00000100 */
10132 #define ETH_MACSTNUR_TSSS_9                 (0x200U << ETH_MACSTNUR_TSSS_Pos)                   /*!< 0x00000200 */
10133 #define ETH_MACSTNUR_TSSS_10                (0x400U << ETH_MACSTNUR_TSSS_Pos)                   /*!< 0x00000400 */
10134 #define ETH_MACSTNUR_TSSS_11                (0x800U << ETH_MACSTNUR_TSSS_Pos)                   /*!< 0x00000800 */
10135 #define ETH_MACSTNUR_TSSS_12                (0x1000U << ETH_MACSTNUR_TSSS_Pos)                  /*!< 0x00001000 */
10136 #define ETH_MACSTNUR_TSSS_13                (0x2000U << ETH_MACSTNUR_TSSS_Pos)                  /*!< 0x00002000 */
10137 #define ETH_MACSTNUR_TSSS_14                (0x4000U << ETH_MACSTNUR_TSSS_Pos)                  /*!< 0x00004000 */
10138 #define ETH_MACSTNUR_TSSS_15                (0x8000U << ETH_MACSTNUR_TSSS_Pos)                  /*!< 0x00008000 */
10139 #define ETH_MACSTNUR_TSSS_16                (0x10000U << ETH_MACSTNUR_TSSS_Pos)                 /*!< 0x00010000 */
10140 #define ETH_MACSTNUR_TSSS_17                (0x20000U << ETH_MACSTNUR_TSSS_Pos)                 /*!< 0x00020000 */
10141 #define ETH_MACSTNUR_TSSS_18                (0x40000U << ETH_MACSTNUR_TSSS_Pos)                 /*!< 0x00040000 */
10142 #define ETH_MACSTNUR_TSSS_19                (0x80000U << ETH_MACSTNUR_TSSS_Pos)                 /*!< 0x00080000 */
10143 #define ETH_MACSTNUR_TSSS_20                (0x100000U << ETH_MACSTNUR_TSSS_Pos)                /*!< 0x00100000 */
10144 #define ETH_MACSTNUR_TSSS_21                (0x200000U << ETH_MACSTNUR_TSSS_Pos)                /*!< 0x00200000 */
10145 #define ETH_MACSTNUR_TSSS_22                (0x400000U << ETH_MACSTNUR_TSSS_Pos)                /*!< 0x00400000 */
10146 #define ETH_MACSTNUR_TSSS_23                (0x800000U << ETH_MACSTNUR_TSSS_Pos)                /*!< 0x00800000 */
10147 #define ETH_MACSTNUR_TSSS_24                (0x1000000U << ETH_MACSTNUR_TSSS_Pos)               /*!< 0x01000000 */
10148 #define ETH_MACSTNUR_TSSS_25                (0x2000000U << ETH_MACSTNUR_TSSS_Pos)               /*!< 0x02000000 */
10149 #define ETH_MACSTNUR_TSSS_26                (0x4000000U << ETH_MACSTNUR_TSSS_Pos)               /*!< 0x04000000 */
10150 #define ETH_MACSTNUR_TSSS_27                (0x8000000U << ETH_MACSTNUR_TSSS_Pos)               /*!< 0x08000000 */
10151 #define ETH_MACSTNUR_TSSS_28                (0x10000000U << ETH_MACSTNUR_TSSS_Pos)              /*!< 0x10000000 */
10152 #define ETH_MACSTNUR_TSSS_29                (0x20000000U << ETH_MACSTNUR_TSSS_Pos)              /*!< 0x20000000 */
10153 #define ETH_MACSTNUR_TSSS_30                (0x40000000U << ETH_MACSTNUR_TSSS_Pos)              /*!< 0x40000000 */
10154 #define ETH_MACSTNUR_ADDSUB_Pos             (31U)
10155 #define ETH_MACSTNUR_ADDSUB_Msk             (0x1U << ETH_MACSTNUR_ADDSUB_Pos)                   /*!< 0x80000000 */
10156 #define ETH_MACSTNUR_ADDSUB                 ETH_MACSTNUR_ADDSUB_Msk                             /*!< Add or Subtract Time */
10157 
10158 /**************  Bit definition for ETH_MACTSAR register  **************/
10159 #define ETH_MACTSAR_TSAR_Pos                (0U)
10160 #define ETH_MACTSAR_TSAR_Msk                (0xFFFFFFFFU << ETH_MACTSAR_TSAR_Pos)               /*!< 0xFFFFFFFF */
10161 #define ETH_MACTSAR_TSAR                    ETH_MACTSAR_TSAR_Msk                                /*!< Timestamp Addend Register */
10162 #define ETH_MACTSAR_TSAR_0                  (0x1U << ETH_MACTSAR_TSAR_Pos)                      /*!< 0x00000001 */
10163 #define ETH_MACTSAR_TSAR_1                  (0x2U << ETH_MACTSAR_TSAR_Pos)                      /*!< 0x00000002 */
10164 #define ETH_MACTSAR_TSAR_2                  (0x4U << ETH_MACTSAR_TSAR_Pos)                      /*!< 0x00000004 */
10165 #define ETH_MACTSAR_TSAR_3                  (0x8U << ETH_MACTSAR_TSAR_Pos)                      /*!< 0x00000008 */
10166 #define ETH_MACTSAR_TSAR_4                  (0x10U << ETH_MACTSAR_TSAR_Pos)                     /*!< 0x00000010 */
10167 #define ETH_MACTSAR_TSAR_5                  (0x20U << ETH_MACTSAR_TSAR_Pos)                     /*!< 0x00000020 */
10168 #define ETH_MACTSAR_TSAR_6                  (0x40U << ETH_MACTSAR_TSAR_Pos)                     /*!< 0x00000040 */
10169 #define ETH_MACTSAR_TSAR_7                  (0x80U << ETH_MACTSAR_TSAR_Pos)                     /*!< 0x00000080 */
10170 #define ETH_MACTSAR_TSAR_8                  (0x100U << ETH_MACTSAR_TSAR_Pos)                    /*!< 0x00000100 */
10171 #define ETH_MACTSAR_TSAR_9                  (0x200U << ETH_MACTSAR_TSAR_Pos)                    /*!< 0x00000200 */
10172 #define ETH_MACTSAR_TSAR_10                 (0x400U << ETH_MACTSAR_TSAR_Pos)                    /*!< 0x00000400 */
10173 #define ETH_MACTSAR_TSAR_11                 (0x800U << ETH_MACTSAR_TSAR_Pos)                    /*!< 0x00000800 */
10174 #define ETH_MACTSAR_TSAR_12                 (0x1000U << ETH_MACTSAR_TSAR_Pos)                   /*!< 0x00001000 */
10175 #define ETH_MACTSAR_TSAR_13                 (0x2000U << ETH_MACTSAR_TSAR_Pos)                   /*!< 0x00002000 */
10176 #define ETH_MACTSAR_TSAR_14                 (0x4000U << ETH_MACTSAR_TSAR_Pos)                   /*!< 0x00004000 */
10177 #define ETH_MACTSAR_TSAR_15                 (0x8000U << ETH_MACTSAR_TSAR_Pos)                   /*!< 0x00008000 */
10178 #define ETH_MACTSAR_TSAR_16                 (0x10000U << ETH_MACTSAR_TSAR_Pos)                  /*!< 0x00010000 */
10179 #define ETH_MACTSAR_TSAR_17                 (0x20000U << ETH_MACTSAR_TSAR_Pos)                  /*!< 0x00020000 */
10180 #define ETH_MACTSAR_TSAR_18                 (0x40000U << ETH_MACTSAR_TSAR_Pos)                  /*!< 0x00040000 */
10181 #define ETH_MACTSAR_TSAR_19                 (0x80000U << ETH_MACTSAR_TSAR_Pos)                  /*!< 0x00080000 */
10182 #define ETH_MACTSAR_TSAR_20                 (0x100000U << ETH_MACTSAR_TSAR_Pos)                 /*!< 0x00100000 */
10183 #define ETH_MACTSAR_TSAR_21                 (0x200000U << ETH_MACTSAR_TSAR_Pos)                 /*!< 0x00200000 */
10184 #define ETH_MACTSAR_TSAR_22                 (0x400000U << ETH_MACTSAR_TSAR_Pos)                 /*!< 0x00400000 */
10185 #define ETH_MACTSAR_TSAR_23                 (0x800000U << ETH_MACTSAR_TSAR_Pos)                 /*!< 0x00800000 */
10186 #define ETH_MACTSAR_TSAR_24                 (0x1000000U << ETH_MACTSAR_TSAR_Pos)                /*!< 0x01000000 */
10187 #define ETH_MACTSAR_TSAR_25                 (0x2000000U << ETH_MACTSAR_TSAR_Pos)                /*!< 0x02000000 */
10188 #define ETH_MACTSAR_TSAR_26                 (0x4000000U << ETH_MACTSAR_TSAR_Pos)                /*!< 0x04000000 */
10189 #define ETH_MACTSAR_TSAR_27                 (0x8000000U << ETH_MACTSAR_TSAR_Pos)                /*!< 0x08000000 */
10190 #define ETH_MACTSAR_TSAR_28                 (0x10000000U << ETH_MACTSAR_TSAR_Pos)               /*!< 0x10000000 */
10191 #define ETH_MACTSAR_TSAR_29                 (0x20000000U << ETH_MACTSAR_TSAR_Pos)               /*!< 0x20000000 */
10192 #define ETH_MACTSAR_TSAR_30                 (0x40000000U << ETH_MACTSAR_TSAR_Pos)               /*!< 0x40000000 */
10193 #define ETH_MACTSAR_TSAR_31                 (0x80000000U << ETH_MACTSAR_TSAR_Pos)               /*!< 0x80000000 */
10194 
10195 /**************  Bit definition for ETH_MACTSSR register  **************/
10196 #define ETH_MACTSSR_TSSOVF_Pos              (0U)
10197 #define ETH_MACTSSR_TSSOVF_Msk              (0x1U << ETH_MACTSSR_TSSOVF_Pos)                    /*!< 0x00000001 */
10198 #define ETH_MACTSSR_TSSOVF                  ETH_MACTSSR_TSSOVF_Msk                              /*!< Timestamp Seconds Overflow */
10199 #define ETH_MACTSSR_TSTARGT0_Pos            (1U)
10200 #define ETH_MACTSSR_TSTARGT0_Msk            (0x1U << ETH_MACTSSR_TSTARGT0_Pos)                  /*!< 0x00000002 */
10201 #define ETH_MACTSSR_TSTARGT0                ETH_MACTSSR_TSTARGT0_Msk                            /*!< Timestamp Target Time Reached */
10202 #define ETH_MACTSSR_AUXTSTRIG_Pos           (2U)
10203 #define ETH_MACTSSR_AUXTSTRIG_Msk           (0x1U << ETH_MACTSSR_AUXTSTRIG_Pos)                 /*!< 0x00000004 */
10204 #define ETH_MACTSSR_AUXTSTRIG               ETH_MACTSSR_AUXTSTRIG_Msk                           /*!< Auxiliary Timestamp Trigger Snapshot */
10205 #define ETH_MACTSSR_TSTRGTERR0_Pos          (3U)
10206 #define ETH_MACTSSR_TSTRGTERR0_Msk          (0x1U << ETH_MACTSSR_TSTRGTERR0_Pos)                /*!< 0x00000008 */
10207 #define ETH_MACTSSR_TSTRGTERR0              ETH_MACTSSR_TSTRGTERR0_Msk                          /*!< Timestamp Target Time Error */
10208 #define ETH_MACTSSR_TXTSSIS_Pos             (15U)
10209 #define ETH_MACTSSR_TXTSSIS_Msk             (0x1U << ETH_MACTSSR_TXTSSIS_Pos)                   /*!< 0x00008000 */
10210 #define ETH_MACTSSR_TXTSSIS                 ETH_MACTSSR_TXTSSIS_Msk                             /*!< Tx Timestamp Status Interrupt Status */
10211 #define ETH_MACTSSR_ATSSTN_Pos              (16U)
10212 #define ETH_MACTSSR_ATSSTN_Msk              (0xFU << ETH_MACTSSR_ATSSTN_Pos)                    /*!< 0x000F0000 */
10213 #define ETH_MACTSSR_ATSSTN                  ETH_MACTSSR_ATSSTN_Msk                              /*!< Auxiliary Timestamp Snapshot Trigger Identifier */
10214 #define ETH_MACTSSR_ATSSTN_0                (0x1U << ETH_MACTSSR_ATSSTN_Pos)                /*!< 0x00010000 */
10215 #define ETH_MACTSSR_ATSSTN_1                (0x2U << ETH_MACTSSR_ATSSTN_Pos)                /*!< 0x00020000 */
10216 #define ETH_MACTSSR_ATSSTN_2                (0x4U << ETH_MACTSSR_ATSSTN_Pos)                /*!< 0x00040000 */
10217 #define ETH_MACTSSR_ATSSTN_3                (0x8U << ETH_MACTSSR_ATSSTN_Pos)                /*!< 0x00080000 */
10218 #define ETH_MACTSSR_ATSSTM_Pos              (24U)
10219 #define ETH_MACTSSR_ATSSTM_Msk              (0x1U << ETH_MACTSSR_ATSSTM_Pos)                    /*!< 0x01000000 */
10220 #define ETH_MACTSSR_ATSSTM                  ETH_MACTSSR_ATSSTM_Msk                              /*!< Auxiliary Timestamp Snapshot Trigger Missed */
10221 #define ETH_MACTSSR_ATSNS_Pos               (25U)
10222 #define ETH_MACTSSR_ATSNS_Msk               (0x1FU << ETH_MACTSSR_ATSNS_Pos)                    /*!< 0x3E000000 */
10223 #define ETH_MACTSSR_ATSNS                   ETH_MACTSSR_ATSNS_Msk                               /*!< Number of Auxiliary Timestamp Snapshots */
10224 #define ETH_MACTSSR_ATSNS_0                 (0x1U << ETH_MACTSSR_ATSNS_Pos)               /*!< 0x02000000 */
10225 #define ETH_MACTSSR_ATSNS_1                 (0x2U << ETH_MACTSSR_ATSNS_Pos)               /*!< 0x04000000 */
10226 #define ETH_MACTSSR_ATSNS_2                 (0x4U << ETH_MACTSSR_ATSNS_Pos)               /*!< 0x08000000 */
10227 #define ETH_MACTSSR_ATSNS_3                 (0x8U << ETH_MACTSSR_ATSNS_Pos)              /*!< 0x10000000 */
10228 #define ETH_MACTSSR_ATSNS_4                 (0x10U << ETH_MACTSSR_ATSNS_Pos)              /*!< 0x20000000 */
10229 
10230 /************  Bit definition for ETH_MACTXTSSNR register  *************/
10231 #define ETH_MACTXTSSNR_TXTSSLO_Pos          (0U)
10232 #define ETH_MACTXTSSNR_TXTSSLO_Msk          (0x7FFFFFFFU << ETH_MACTXTSSNR_TXTSSLO_Pos)         /*!< 0x7FFFFFFF */
10233 #define ETH_MACTXTSSNR_TXTSSLO              ETH_MACTXTSSNR_TXTSSLO_Msk                          /*!< Transmit Timestamp Status Low */
10234 #define ETH_MACTXTSSNR_TXTSSLO_0            (0x1U << ETH_MACTXTSSNR_TXTSSLO_Pos)                /*!< 0x00000001 */
10235 #define ETH_MACTXTSSNR_TXTSSLO_1            (0x2U << ETH_MACTXTSSNR_TXTSSLO_Pos)                /*!< 0x00000002 */
10236 #define ETH_MACTXTSSNR_TXTSSLO_2            (0x4U << ETH_MACTXTSSNR_TXTSSLO_Pos)                /*!< 0x00000004 */
10237 #define ETH_MACTXTSSNR_TXTSSLO_3            (0x8U << ETH_MACTXTSSNR_TXTSSLO_Pos)                /*!< 0x00000008 */
10238 #define ETH_MACTXTSSNR_TXTSSLO_4            (0x10U << ETH_MACTXTSSNR_TXTSSLO_Pos)               /*!< 0x00000010 */
10239 #define ETH_MACTXTSSNR_TXTSSLO_5            (0x20U << ETH_MACTXTSSNR_TXTSSLO_Pos)               /*!< 0x00000020 */
10240 #define ETH_MACTXTSSNR_TXTSSLO_6            (0x40U << ETH_MACTXTSSNR_TXTSSLO_Pos)               /*!< 0x00000040 */
10241 #define ETH_MACTXTSSNR_TXTSSLO_7            (0x80U << ETH_MACTXTSSNR_TXTSSLO_Pos)               /*!< 0x00000080 */
10242 #define ETH_MACTXTSSNR_TXTSSLO_8            (0x100U << ETH_MACTXTSSNR_TXTSSLO_Pos)              /*!< 0x00000100 */
10243 #define ETH_MACTXTSSNR_TXTSSLO_9            (0x200U << ETH_MACTXTSSNR_TXTSSLO_Pos)              /*!< 0x00000200 */
10244 #define ETH_MACTXTSSNR_TXTSSLO_10           (0x400U << ETH_MACTXTSSNR_TXTSSLO_Pos)              /*!< 0x00000400 */
10245 #define ETH_MACTXTSSNR_TXTSSLO_11           (0x800U << ETH_MACTXTSSNR_TXTSSLO_Pos)              /*!< 0x00000800 */
10246 #define ETH_MACTXTSSNR_TXTSSLO_12           (0x1000U << ETH_MACTXTSSNR_TXTSSLO_Pos)             /*!< 0x00001000 */
10247 #define ETH_MACTXTSSNR_TXTSSLO_13           (0x2000U << ETH_MACTXTSSNR_TXTSSLO_Pos)             /*!< 0x00002000 */
10248 #define ETH_MACTXTSSNR_TXTSSLO_14           (0x4000U << ETH_MACTXTSSNR_TXTSSLO_Pos)             /*!< 0x00004000 */
10249 #define ETH_MACTXTSSNR_TXTSSLO_15           (0x8000U << ETH_MACTXTSSNR_TXTSSLO_Pos)             /*!< 0x00008000 */
10250 #define ETH_MACTXTSSNR_TXTSSLO_16           (0x10000U << ETH_MACTXTSSNR_TXTSSLO_Pos)            /*!< 0x00010000 */
10251 #define ETH_MACTXTSSNR_TXTSSLO_17           (0x20000U << ETH_MACTXTSSNR_TXTSSLO_Pos)            /*!< 0x00020000 */
10252 #define ETH_MACTXTSSNR_TXTSSLO_18           (0x40000U << ETH_MACTXTSSNR_TXTSSLO_Pos)            /*!< 0x00040000 */
10253 #define ETH_MACTXTSSNR_TXTSSLO_19           (0x80000U << ETH_MACTXTSSNR_TXTSSLO_Pos)            /*!< 0x00080000 */
10254 #define ETH_MACTXTSSNR_TXTSSLO_20           (0x100000U << ETH_MACTXTSSNR_TXTSSLO_Pos)           /*!< 0x00100000 */
10255 #define ETH_MACTXTSSNR_TXTSSLO_21           (0x200000U << ETH_MACTXTSSNR_TXTSSLO_Pos)           /*!< 0x00200000 */
10256 #define ETH_MACTXTSSNR_TXTSSLO_22           (0x400000U << ETH_MACTXTSSNR_TXTSSLO_Pos)           /*!< 0x00400000 */
10257 #define ETH_MACTXTSSNR_TXTSSLO_23           (0x800000U << ETH_MACTXTSSNR_TXTSSLO_Pos)           /*!< 0x00800000 */
10258 #define ETH_MACTXTSSNR_TXTSSLO_24           (0x1000000U << ETH_MACTXTSSNR_TXTSSLO_Pos)          /*!< 0x01000000 */
10259 #define ETH_MACTXTSSNR_TXTSSLO_25           (0x2000000U << ETH_MACTXTSSNR_TXTSSLO_Pos)          /*!< 0x02000000 */
10260 #define ETH_MACTXTSSNR_TXTSSLO_26           (0x4000000U << ETH_MACTXTSSNR_TXTSSLO_Pos)          /*!< 0x04000000 */
10261 #define ETH_MACTXTSSNR_TXTSSLO_27           (0x8000000U << ETH_MACTXTSSNR_TXTSSLO_Pos)          /*!< 0x08000000 */
10262 #define ETH_MACTXTSSNR_TXTSSLO_28           (0x10000000U << ETH_MACTXTSSNR_TXTSSLO_Pos)         /*!< 0x10000000 */
10263 #define ETH_MACTXTSSNR_TXTSSLO_29           (0x20000000U << ETH_MACTXTSSNR_TXTSSLO_Pos)         /*!< 0x20000000 */
10264 #define ETH_MACTXTSSNR_TXTSSLO_30           (0x40000000U << ETH_MACTXTSSNR_TXTSSLO_Pos)         /*!< 0x40000000 */
10265 #define ETH_MACTXTSSNR_TXTSSMIS_Pos         (31U)
10266 #define ETH_MACTXTSSNR_TXTSSMIS_Msk         (0x1U << ETH_MACTXTSSNR_TXTSSMIS_Pos)               /*!< 0x80000000 */
10267 #define ETH_MACTXTSSNR_TXTSSMIS             ETH_MACTXTSSNR_TXTSSMIS_Msk                         /*!< Transmit Timestamp Status Missed */
10268 
10269 /************  Bit definition for ETH_MACTXTSSSR register  *************/
10270 #define ETH_MACTXTSSSR_TXTSSHI_Pos          (0U)
10271 #define ETH_MACTXTSSSR_TXTSSHI_Msk          (0xFFFFFFFFU << ETH_MACTXTSSSR_TXTSSHI_Pos)         /*!< 0xFFFFFFFF */
10272 #define ETH_MACTXTSSSR_TXTSSHI              ETH_MACTXTSSSR_TXTSSHI_Msk                          /*!< Transmit Timestamp Status High */
10273 #define ETH_MACTXTSSSR_TXTSSHI_0            (0x1U << ETH_MACTXTSSSR_TXTSSHI_Pos)                /*!< 0x00000001 */
10274 #define ETH_MACTXTSSSR_TXTSSHI_1            (0x2U << ETH_MACTXTSSSR_TXTSSHI_Pos)                /*!< 0x00000002 */
10275 #define ETH_MACTXTSSSR_TXTSSHI_2            (0x4U << ETH_MACTXTSSSR_TXTSSHI_Pos)                /*!< 0x00000004 */
10276 #define ETH_MACTXTSSSR_TXTSSHI_3            (0x8U << ETH_MACTXTSSSR_TXTSSHI_Pos)                /*!< 0x00000008 */
10277 #define ETH_MACTXTSSSR_TXTSSHI_4            (0x10U << ETH_MACTXTSSSR_TXTSSHI_Pos)               /*!< 0x00000010 */
10278 #define ETH_MACTXTSSSR_TXTSSHI_5            (0x20U << ETH_MACTXTSSSR_TXTSSHI_Pos)               /*!< 0x00000020 */
10279 #define ETH_MACTXTSSSR_TXTSSHI_6            (0x40U << ETH_MACTXTSSSR_TXTSSHI_Pos)               /*!< 0x00000040 */
10280 #define ETH_MACTXTSSSR_TXTSSHI_7            (0x80U << ETH_MACTXTSSSR_TXTSSHI_Pos)               /*!< 0x00000080 */
10281 #define ETH_MACTXTSSSR_TXTSSHI_8            (0x100U << ETH_MACTXTSSSR_TXTSSHI_Pos)              /*!< 0x00000100 */
10282 #define ETH_MACTXTSSSR_TXTSSHI_9            (0x200U << ETH_MACTXTSSSR_TXTSSHI_Pos)              /*!< 0x00000200 */
10283 #define ETH_MACTXTSSSR_TXTSSHI_10           (0x400U << ETH_MACTXTSSSR_TXTSSHI_Pos)              /*!< 0x00000400 */
10284 #define ETH_MACTXTSSSR_TXTSSHI_11           (0x800U << ETH_MACTXTSSSR_TXTSSHI_Pos)              /*!< 0x00000800 */
10285 #define ETH_MACTXTSSSR_TXTSSHI_12           (0x1000U << ETH_MACTXTSSSR_TXTSSHI_Pos)             /*!< 0x00001000 */
10286 #define ETH_MACTXTSSSR_TXTSSHI_13           (0x2000U << ETH_MACTXTSSSR_TXTSSHI_Pos)             /*!< 0x00002000 */
10287 #define ETH_MACTXTSSSR_TXTSSHI_14           (0x4000U << ETH_MACTXTSSSR_TXTSSHI_Pos)             /*!< 0x00004000 */
10288 #define ETH_MACTXTSSSR_TXTSSHI_15           (0x8000U << ETH_MACTXTSSSR_TXTSSHI_Pos)             /*!< 0x00008000 */
10289 #define ETH_MACTXTSSSR_TXTSSHI_16           (0x10000U << ETH_MACTXTSSSR_TXTSSHI_Pos)            /*!< 0x00010000 */
10290 #define ETH_MACTXTSSSR_TXTSSHI_17           (0x20000U << ETH_MACTXTSSSR_TXTSSHI_Pos)            /*!< 0x00020000 */
10291 #define ETH_MACTXTSSSR_TXTSSHI_18           (0x40000U << ETH_MACTXTSSSR_TXTSSHI_Pos)            /*!< 0x00040000 */
10292 #define ETH_MACTXTSSSR_TXTSSHI_19           (0x80000U << ETH_MACTXTSSSR_TXTSSHI_Pos)            /*!< 0x00080000 */
10293 #define ETH_MACTXTSSSR_TXTSSHI_20           (0x100000U << ETH_MACTXTSSSR_TXTSSHI_Pos)           /*!< 0x00100000 */
10294 #define ETH_MACTXTSSSR_TXTSSHI_21           (0x200000U << ETH_MACTXTSSSR_TXTSSHI_Pos)           /*!< 0x00200000 */
10295 #define ETH_MACTXTSSSR_TXTSSHI_22           (0x400000U << ETH_MACTXTSSSR_TXTSSHI_Pos)           /*!< 0x00400000 */
10296 #define ETH_MACTXTSSSR_TXTSSHI_23           (0x800000U << ETH_MACTXTSSSR_TXTSSHI_Pos)           /*!< 0x00800000 */
10297 #define ETH_MACTXTSSSR_TXTSSHI_24           (0x1000000U << ETH_MACTXTSSSR_TXTSSHI_Pos)          /*!< 0x01000000 */
10298 #define ETH_MACTXTSSSR_TXTSSHI_25           (0x2000000U << ETH_MACTXTSSSR_TXTSSHI_Pos)          /*!< 0x02000000 */
10299 #define ETH_MACTXTSSSR_TXTSSHI_26           (0x4000000U << ETH_MACTXTSSSR_TXTSSHI_Pos)          /*!< 0x04000000 */
10300 #define ETH_MACTXTSSSR_TXTSSHI_27           (0x8000000U << ETH_MACTXTSSSR_TXTSSHI_Pos)          /*!< 0x08000000 */
10301 #define ETH_MACTXTSSSR_TXTSSHI_28           (0x10000000U << ETH_MACTXTSSSR_TXTSSHI_Pos)         /*!< 0x10000000 */
10302 #define ETH_MACTXTSSSR_TXTSSHI_29           (0x20000000U << ETH_MACTXTSSSR_TXTSSHI_Pos)         /*!< 0x20000000 */
10303 #define ETH_MACTXTSSSR_TXTSSHI_30           (0x40000000U << ETH_MACTXTSSSR_TXTSSHI_Pos)         /*!< 0x40000000 */
10304 #define ETH_MACTXTSSSR_TXTSSHI_31           (0x80000000U << ETH_MACTXTSSSR_TXTSSHI_Pos)         /*!< 0x80000000 */
10305 
10306 /**************  Bit definition for ETH_MACACR register  ***************/
10307 #define ETH_MACACR_ATSFC_Pos                (0U)
10308 #define ETH_MACACR_ATSFC_Msk                (0x1U << ETH_MACACR_ATSFC_Pos)                      /*!< 0x00000001 */
10309 #define ETH_MACACR_ATSFC                    ETH_MACACR_ATSFC_Msk                                /*!< Auxiliary Snapshot FIFO Clear */
10310 #define ETH_MACACR_ATSEN0_Pos               (4U)
10311 #define ETH_MACACR_ATSEN0_Msk               (0x1U << ETH_MACACR_ATSEN0_Pos)                     /*!< 0x00000010 */
10312 #define ETH_MACACR_ATSEN0                   ETH_MACACR_ATSEN0_Msk                               /*!< Auxiliary Snapshot 0 Enable */
10313 #define ETH_MACACR_ATSEN1_Pos               (5U)
10314 #define ETH_MACACR_ATSEN1_Msk               (0x1U << ETH_MACACR_ATSEN1_Pos)                     /*!< 0x00000020 */
10315 #define ETH_MACACR_ATSEN1                   ETH_MACACR_ATSEN1_Msk                               /*!< Auxiliary Snapshot 1 Enable */
10316 #define ETH_MACACR_ATSEN2_Pos               (6U)
10317 #define ETH_MACACR_ATSEN2_Msk               (0x1U << ETH_MACACR_ATSEN2_Pos)                     /*!< 0x00000040 */
10318 #define ETH_MACACR_ATSEN2                   ETH_MACACR_ATSEN2_Msk                               /*!< Auxiliary Snapshot 2 Enable */
10319 #define ETH_MACACR_ATSEN3_Pos               (7U)
10320 #define ETH_MACACR_ATSEN3_Msk               (0x1U << ETH_MACACR_ATSEN3_Pos)                     /*!< 0x00000080 */
10321 #define ETH_MACACR_ATSEN3                   ETH_MACACR_ATSEN3_Msk                               /*!< Auxiliary Snapshot 3 Enable */
10322 
10323 /*************  Bit definition for ETH_MACATSNR register  **************/
10324 #define ETH_MACATSNR_AUXTSLO_Pos            (0U)
10325 #define ETH_MACATSNR_AUXTSLO_Msk            (0x7FFFFFFFU << ETH_MACATSNR_AUXTSLO_Pos)           /*!< 0x7FFFFFFF */
10326 #define ETH_MACATSNR_AUXTSLO                ETH_MACATSNR_AUXTSLO_Msk                            /*!< Auxiliary Timestamp */
10327 #define ETH_MACATSNR_AUXTSLO_0              (0x1U << ETH_MACATSNR_AUXTSLO_Pos)                  /*!< 0x00000001 */
10328 #define ETH_MACATSNR_AUXTSLO_1              (0x2U << ETH_MACATSNR_AUXTSLO_Pos)                  /*!< 0x00000002 */
10329 #define ETH_MACATSNR_AUXTSLO_2              (0x4U << ETH_MACATSNR_AUXTSLO_Pos)                  /*!< 0x00000004 */
10330 #define ETH_MACATSNR_AUXTSLO_3              (0x8U << ETH_MACATSNR_AUXTSLO_Pos)                  /*!< 0x00000008 */
10331 #define ETH_MACATSNR_AUXTSLO_4              (0x10U << ETH_MACATSNR_AUXTSLO_Pos)                 /*!< 0x00000010 */
10332 #define ETH_MACATSNR_AUXTSLO_5              (0x20U << ETH_MACATSNR_AUXTSLO_Pos)                 /*!< 0x00000020 */
10333 #define ETH_MACATSNR_AUXTSLO_6              (0x40U << ETH_MACATSNR_AUXTSLO_Pos)                 /*!< 0x00000040 */
10334 #define ETH_MACATSNR_AUXTSLO_7              (0x80U << ETH_MACATSNR_AUXTSLO_Pos)                 /*!< 0x00000080 */
10335 #define ETH_MACATSNR_AUXTSLO_8              (0x100U << ETH_MACATSNR_AUXTSLO_Pos)                /*!< 0x00000100 */
10336 #define ETH_MACATSNR_AUXTSLO_9              (0x200U << ETH_MACATSNR_AUXTSLO_Pos)                /*!< 0x00000200 */
10337 #define ETH_MACATSNR_AUXTSLO_10             (0x400U << ETH_MACATSNR_AUXTSLO_Pos)                /*!< 0x00000400 */
10338 #define ETH_MACATSNR_AUXTSLO_11             (0x800U << ETH_MACATSNR_AUXTSLO_Pos)                /*!< 0x00000800 */
10339 #define ETH_MACATSNR_AUXTSLO_12             (0x1000U << ETH_MACATSNR_AUXTSLO_Pos)               /*!< 0x00001000 */
10340 #define ETH_MACATSNR_AUXTSLO_13             (0x2000U << ETH_MACATSNR_AUXTSLO_Pos)               /*!< 0x00002000 */
10341 #define ETH_MACATSNR_AUXTSLO_14             (0x4000U << ETH_MACATSNR_AUXTSLO_Pos)               /*!< 0x00004000 */
10342 #define ETH_MACATSNR_AUXTSLO_15             (0x8000U << ETH_MACATSNR_AUXTSLO_Pos)               /*!< 0x00008000 */
10343 #define ETH_MACATSNR_AUXTSLO_16             (0x10000U << ETH_MACATSNR_AUXTSLO_Pos)              /*!< 0x00010000 */
10344 #define ETH_MACATSNR_AUXTSLO_17             (0x20000U << ETH_MACATSNR_AUXTSLO_Pos)              /*!< 0x00020000 */
10345 #define ETH_MACATSNR_AUXTSLO_18             (0x40000U << ETH_MACATSNR_AUXTSLO_Pos)              /*!< 0x00040000 */
10346 #define ETH_MACATSNR_AUXTSLO_19             (0x80000U << ETH_MACATSNR_AUXTSLO_Pos)              /*!< 0x00080000 */
10347 #define ETH_MACATSNR_AUXTSLO_20             (0x100000U << ETH_MACATSNR_AUXTSLO_Pos)             /*!< 0x00100000 */
10348 #define ETH_MACATSNR_AUXTSLO_21             (0x200000U << ETH_MACATSNR_AUXTSLO_Pos)             /*!< 0x00200000 */
10349 #define ETH_MACATSNR_AUXTSLO_22             (0x400000U << ETH_MACATSNR_AUXTSLO_Pos)             /*!< 0x00400000 */
10350 #define ETH_MACATSNR_AUXTSLO_23             (0x800000U << ETH_MACATSNR_AUXTSLO_Pos)             /*!< 0x00800000 */
10351 #define ETH_MACATSNR_AUXTSLO_24             (0x1000000U << ETH_MACATSNR_AUXTSLO_Pos)            /*!< 0x01000000 */
10352 #define ETH_MACATSNR_AUXTSLO_25             (0x2000000U << ETH_MACATSNR_AUXTSLO_Pos)            /*!< 0x02000000 */
10353 #define ETH_MACATSNR_AUXTSLO_26             (0x4000000U << ETH_MACATSNR_AUXTSLO_Pos)            /*!< 0x04000000 */
10354 #define ETH_MACATSNR_AUXTSLO_27             (0x8000000U << ETH_MACATSNR_AUXTSLO_Pos)            /*!< 0x08000000 */
10355 #define ETH_MACATSNR_AUXTSLO_28             (0x10000000U << ETH_MACATSNR_AUXTSLO_Pos)           /*!< 0x10000000 */
10356 #define ETH_MACATSNR_AUXTSLO_29             (0x20000000U << ETH_MACATSNR_AUXTSLO_Pos)           /*!< 0x20000000 */
10357 #define ETH_MACATSNR_AUXTSLO_30             (0x40000000U << ETH_MACATSNR_AUXTSLO_Pos)           /*!< 0x40000000 */
10358 
10359 /*************  Bit definition for ETH_MACATSSR register  **************/
10360 #define ETH_MACATSSR_AUXTSHI_Pos            (0U)
10361 #define ETH_MACATSSR_AUXTSHI_Msk            (0xFFFFFFFFU << ETH_MACATSSR_AUXTSHI_Pos)           /*!< 0xFFFFFFFF */
10362 #define ETH_MACATSSR_AUXTSHI                ETH_MACATSSR_AUXTSHI_Msk                            /*!< Auxiliary Timestamp */
10363 #define ETH_MACATSSR_AUXTSHI_0              (0x1U << ETH_MACATSSR_AUXTSHI_Pos)                  /*!< 0x00000001 */
10364 #define ETH_MACATSSR_AUXTSHI_1              (0x2U << ETH_MACATSSR_AUXTSHI_Pos)                  /*!< 0x00000002 */
10365 #define ETH_MACATSSR_AUXTSHI_2              (0x4U << ETH_MACATSSR_AUXTSHI_Pos)                  /*!< 0x00000004 */
10366 #define ETH_MACATSSR_AUXTSHI_3              (0x8U << ETH_MACATSSR_AUXTSHI_Pos)                  /*!< 0x00000008 */
10367 #define ETH_MACATSSR_AUXTSHI_4              (0x10U << ETH_MACATSSR_AUXTSHI_Pos)                 /*!< 0x00000010 */
10368 #define ETH_MACATSSR_AUXTSHI_5              (0x20U << ETH_MACATSSR_AUXTSHI_Pos)                 /*!< 0x00000020 */
10369 #define ETH_MACATSSR_AUXTSHI_6              (0x40U << ETH_MACATSSR_AUXTSHI_Pos)                 /*!< 0x00000040 */
10370 #define ETH_MACATSSR_AUXTSHI_7              (0x80U << ETH_MACATSSR_AUXTSHI_Pos)                 /*!< 0x00000080 */
10371 #define ETH_MACATSSR_AUXTSHI_8              (0x100U << ETH_MACATSSR_AUXTSHI_Pos)                /*!< 0x00000100 */
10372 #define ETH_MACATSSR_AUXTSHI_9              (0x200U << ETH_MACATSSR_AUXTSHI_Pos)                /*!< 0x00000200 */
10373 #define ETH_MACATSSR_AUXTSHI_10             (0x400U << ETH_MACATSSR_AUXTSHI_Pos)                /*!< 0x00000400 */
10374 #define ETH_MACATSSR_AUXTSHI_11             (0x800U << ETH_MACATSSR_AUXTSHI_Pos)                /*!< 0x00000800 */
10375 #define ETH_MACATSSR_AUXTSHI_12             (0x1000U << ETH_MACATSSR_AUXTSHI_Pos)               /*!< 0x00001000 */
10376 #define ETH_MACATSSR_AUXTSHI_13             (0x2000U << ETH_MACATSSR_AUXTSHI_Pos)               /*!< 0x00002000 */
10377 #define ETH_MACATSSR_AUXTSHI_14             (0x4000U << ETH_MACATSSR_AUXTSHI_Pos)               /*!< 0x00004000 */
10378 #define ETH_MACATSSR_AUXTSHI_15             (0x8000U << ETH_MACATSSR_AUXTSHI_Pos)               /*!< 0x00008000 */
10379 #define ETH_MACATSSR_AUXTSHI_16             (0x10000U << ETH_MACATSSR_AUXTSHI_Pos)              /*!< 0x00010000 */
10380 #define ETH_MACATSSR_AUXTSHI_17             (0x20000U << ETH_MACATSSR_AUXTSHI_Pos)              /*!< 0x00020000 */
10381 #define ETH_MACATSSR_AUXTSHI_18             (0x40000U << ETH_MACATSSR_AUXTSHI_Pos)              /*!< 0x00040000 */
10382 #define ETH_MACATSSR_AUXTSHI_19             (0x80000U << ETH_MACATSSR_AUXTSHI_Pos)              /*!< 0x00080000 */
10383 #define ETH_MACATSSR_AUXTSHI_20             (0x100000U << ETH_MACATSSR_AUXTSHI_Pos)             /*!< 0x00100000 */
10384 #define ETH_MACATSSR_AUXTSHI_21             (0x200000U << ETH_MACATSSR_AUXTSHI_Pos)             /*!< 0x00200000 */
10385 #define ETH_MACATSSR_AUXTSHI_22             (0x400000U << ETH_MACATSSR_AUXTSHI_Pos)             /*!< 0x00400000 */
10386 #define ETH_MACATSSR_AUXTSHI_23             (0x800000U << ETH_MACATSSR_AUXTSHI_Pos)             /*!< 0x00800000 */
10387 #define ETH_MACATSSR_AUXTSHI_24             (0x1000000U << ETH_MACATSSR_AUXTSHI_Pos)            /*!< 0x01000000 */
10388 #define ETH_MACATSSR_AUXTSHI_25             (0x2000000U << ETH_MACATSSR_AUXTSHI_Pos)            /*!< 0x02000000 */
10389 #define ETH_MACATSSR_AUXTSHI_26             (0x4000000U << ETH_MACATSSR_AUXTSHI_Pos)            /*!< 0x04000000 */
10390 #define ETH_MACATSSR_AUXTSHI_27             (0x8000000U << ETH_MACATSSR_AUXTSHI_Pos)            /*!< 0x08000000 */
10391 #define ETH_MACATSSR_AUXTSHI_28             (0x10000000U << ETH_MACATSSR_AUXTSHI_Pos)           /*!< 0x10000000 */
10392 #define ETH_MACATSSR_AUXTSHI_29             (0x20000000U << ETH_MACATSSR_AUXTSHI_Pos)           /*!< 0x20000000 */
10393 #define ETH_MACATSSR_AUXTSHI_30             (0x40000000U << ETH_MACATSSR_AUXTSHI_Pos)           /*!< 0x40000000 */
10394 #define ETH_MACATSSR_AUXTSHI_31             (0x80000000U << ETH_MACATSSR_AUXTSHI_Pos)           /*!< 0x80000000 */
10395 
10396 /*************  Bit definition for ETH_MACTSIACR register  *************/
10397 #define ETH_MACTSIACR_OSTIAC_Pos            (0U)
10398 #define ETH_MACTSIACR_OSTIAC_Msk            (0xFFFFFFFFU << ETH_MACTSIACR_OSTIAC_Pos)           /*!< 0xFFFFFFFF */
10399 #define ETH_MACTSIACR_OSTIAC                ETH_MACTSIACR_OSTIAC_Msk                            /*!< One-Step Timestamp Ingress Asymmetry Correction */
10400 #define ETH_MACTSIACR_OSTIAC_0              (0x1U << ETH_MACTSIACR_OSTIAC_Pos)                  /*!< 0x00000001 */
10401 #define ETH_MACTSIACR_OSTIAC_1              (0x2U << ETH_MACTSIACR_OSTIAC_Pos)                  /*!< 0x00000002 */
10402 #define ETH_MACTSIACR_OSTIAC_2              (0x4U << ETH_MACTSIACR_OSTIAC_Pos)                  /*!< 0x00000004 */
10403 #define ETH_MACTSIACR_OSTIAC_3              (0x8U << ETH_MACTSIACR_OSTIAC_Pos)                  /*!< 0x00000008 */
10404 #define ETH_MACTSIACR_OSTIAC_4              (0x10U << ETH_MACTSIACR_OSTIAC_Pos)                 /*!< 0x00000010 */
10405 #define ETH_MACTSIACR_OSTIAC_5              (0x20U << ETH_MACTSIACR_OSTIAC_Pos)                 /*!< 0x00000020 */
10406 #define ETH_MACTSIACR_OSTIAC_6              (0x40U << ETH_MACTSIACR_OSTIAC_Pos)                 /*!< 0x00000040 */
10407 #define ETH_MACTSIACR_OSTIAC_7              (0x80U << ETH_MACTSIACR_OSTIAC_Pos)                 /*!< 0x00000080 */
10408 #define ETH_MACTSIACR_OSTIAC_8              (0x100U << ETH_MACTSIACR_OSTIAC_Pos)                /*!< 0x00000100 */
10409 #define ETH_MACTSIACR_OSTIAC_9              (0x200U << ETH_MACTSIACR_OSTIAC_Pos)                /*!< 0x00000200 */
10410 #define ETH_MACTSIACR_OSTIAC_10             (0x400U << ETH_MACTSIACR_OSTIAC_Pos)                /*!< 0x00000400 */
10411 #define ETH_MACTSIACR_OSTIAC_11             (0x800U << ETH_MACTSIACR_OSTIAC_Pos)                /*!< 0x00000800 */
10412 #define ETH_MACTSIACR_OSTIAC_12             (0x1000U << ETH_MACTSIACR_OSTIAC_Pos)               /*!< 0x00001000 */
10413 #define ETH_MACTSIACR_OSTIAC_13             (0x2000U << ETH_MACTSIACR_OSTIAC_Pos)               /*!< 0x00002000 */
10414 #define ETH_MACTSIACR_OSTIAC_14             (0x4000U << ETH_MACTSIACR_OSTIAC_Pos)               /*!< 0x00004000 */
10415 #define ETH_MACTSIACR_OSTIAC_15             (0x8000U << ETH_MACTSIACR_OSTIAC_Pos)               /*!< 0x00008000 */
10416 #define ETH_MACTSIACR_OSTIAC_16             (0x10000U << ETH_MACTSIACR_OSTIAC_Pos)              /*!< 0x00010000 */
10417 #define ETH_MACTSIACR_OSTIAC_17             (0x20000U << ETH_MACTSIACR_OSTIAC_Pos)              /*!< 0x00020000 */
10418 #define ETH_MACTSIACR_OSTIAC_18             (0x40000U << ETH_MACTSIACR_OSTIAC_Pos)              /*!< 0x00040000 */
10419 #define ETH_MACTSIACR_OSTIAC_19             (0x80000U << ETH_MACTSIACR_OSTIAC_Pos)              /*!< 0x00080000 */
10420 #define ETH_MACTSIACR_OSTIAC_20             (0x100000U << ETH_MACTSIACR_OSTIAC_Pos)             /*!< 0x00100000 */
10421 #define ETH_MACTSIACR_OSTIAC_21             (0x200000U << ETH_MACTSIACR_OSTIAC_Pos)             /*!< 0x00200000 */
10422 #define ETH_MACTSIACR_OSTIAC_22             (0x400000U << ETH_MACTSIACR_OSTIAC_Pos)             /*!< 0x00400000 */
10423 #define ETH_MACTSIACR_OSTIAC_23             (0x800000U << ETH_MACTSIACR_OSTIAC_Pos)             /*!< 0x00800000 */
10424 #define ETH_MACTSIACR_OSTIAC_24             (0x1000000U << ETH_MACTSIACR_OSTIAC_Pos)            /*!< 0x01000000 */
10425 #define ETH_MACTSIACR_OSTIAC_25             (0x2000000U << ETH_MACTSIACR_OSTIAC_Pos)            /*!< 0x02000000 */
10426 #define ETH_MACTSIACR_OSTIAC_26             (0x4000000U << ETH_MACTSIACR_OSTIAC_Pos)            /*!< 0x04000000 */
10427 #define ETH_MACTSIACR_OSTIAC_27             (0x8000000U << ETH_MACTSIACR_OSTIAC_Pos)            /*!< 0x08000000 */
10428 #define ETH_MACTSIACR_OSTIAC_28             (0x10000000U << ETH_MACTSIACR_OSTIAC_Pos)           /*!< 0x10000000 */
10429 #define ETH_MACTSIACR_OSTIAC_29             (0x20000000U << ETH_MACTSIACR_OSTIAC_Pos)           /*!< 0x20000000 */
10430 #define ETH_MACTSIACR_OSTIAC_30             (0x40000000U << ETH_MACTSIACR_OSTIAC_Pos)           /*!< 0x40000000 */
10431 #define ETH_MACTSIACR_OSTIAC_31             (0x80000000U << ETH_MACTSIACR_OSTIAC_Pos)           /*!< 0x80000000 */
10432 
10433 /*************  Bit definition for ETH_MACTSEACR register  *************/
10434 #define ETH_MACTSEACR_OSTEAC_Pos            (0U)
10435 #define ETH_MACTSEACR_OSTEAC_Msk            (0xFFFFFFFFU << ETH_MACTSEACR_OSTEAC_Pos)           /*!< 0xFFFFFFFF */
10436 #define ETH_MACTSEACR_OSTEAC                ETH_MACTSEACR_OSTEAC_Msk                            /*!< One-Step Timestamp Egress Asymmetry Correction */
10437 #define ETH_MACTSEACR_OSTEAC_0              (0x1U << ETH_MACTSEACR_OSTEAC_Pos)                  /*!< 0x00000001 */
10438 #define ETH_MACTSEACR_OSTEAC_1              (0x2U << ETH_MACTSEACR_OSTEAC_Pos)                  /*!< 0x00000002 */
10439 #define ETH_MACTSEACR_OSTEAC_2              (0x4U << ETH_MACTSEACR_OSTEAC_Pos)                  /*!< 0x00000004 */
10440 #define ETH_MACTSEACR_OSTEAC_3              (0x8U << ETH_MACTSEACR_OSTEAC_Pos)                  /*!< 0x00000008 */
10441 #define ETH_MACTSEACR_OSTEAC_4              (0x10U << ETH_MACTSEACR_OSTEAC_Pos)                 /*!< 0x00000010 */
10442 #define ETH_MACTSEACR_OSTEAC_5              (0x20U << ETH_MACTSEACR_OSTEAC_Pos)                 /*!< 0x00000020 */
10443 #define ETH_MACTSEACR_OSTEAC_6              (0x40U << ETH_MACTSEACR_OSTEAC_Pos)                 /*!< 0x00000040 */
10444 #define ETH_MACTSEACR_OSTEAC_7              (0x80U << ETH_MACTSEACR_OSTEAC_Pos)                 /*!< 0x00000080 */
10445 #define ETH_MACTSEACR_OSTEAC_8              (0x100U << ETH_MACTSEACR_OSTEAC_Pos)                /*!< 0x00000100 */
10446 #define ETH_MACTSEACR_OSTEAC_9              (0x200U << ETH_MACTSEACR_OSTEAC_Pos)                /*!< 0x00000200 */
10447 #define ETH_MACTSEACR_OSTEAC_10             (0x400U << ETH_MACTSEACR_OSTEAC_Pos)                /*!< 0x00000400 */
10448 #define ETH_MACTSEACR_OSTEAC_11             (0x800U << ETH_MACTSEACR_OSTEAC_Pos)                /*!< 0x00000800 */
10449 #define ETH_MACTSEACR_OSTEAC_12             (0x1000U << ETH_MACTSEACR_OSTEAC_Pos)               /*!< 0x00001000 */
10450 #define ETH_MACTSEACR_OSTEAC_13             (0x2000U << ETH_MACTSEACR_OSTEAC_Pos)               /*!< 0x00002000 */
10451 #define ETH_MACTSEACR_OSTEAC_14             (0x4000U << ETH_MACTSEACR_OSTEAC_Pos)               /*!< 0x00004000 */
10452 #define ETH_MACTSEACR_OSTEAC_15             (0x8000U << ETH_MACTSEACR_OSTEAC_Pos)               /*!< 0x00008000 */
10453 #define ETH_MACTSEACR_OSTEAC_16             (0x10000U << ETH_MACTSEACR_OSTEAC_Pos)              /*!< 0x00010000 */
10454 #define ETH_MACTSEACR_OSTEAC_17             (0x20000U << ETH_MACTSEACR_OSTEAC_Pos)              /*!< 0x00020000 */
10455 #define ETH_MACTSEACR_OSTEAC_18             (0x40000U << ETH_MACTSEACR_OSTEAC_Pos)              /*!< 0x00040000 */
10456 #define ETH_MACTSEACR_OSTEAC_19             (0x80000U << ETH_MACTSEACR_OSTEAC_Pos)              /*!< 0x00080000 */
10457 #define ETH_MACTSEACR_OSTEAC_20             (0x100000U << ETH_MACTSEACR_OSTEAC_Pos)             /*!< 0x00100000 */
10458 #define ETH_MACTSEACR_OSTEAC_21             (0x200000U << ETH_MACTSEACR_OSTEAC_Pos)             /*!< 0x00200000 */
10459 #define ETH_MACTSEACR_OSTEAC_22             (0x400000U << ETH_MACTSEACR_OSTEAC_Pos)             /*!< 0x00400000 */
10460 #define ETH_MACTSEACR_OSTEAC_23             (0x800000U << ETH_MACTSEACR_OSTEAC_Pos)             /*!< 0x00800000 */
10461 #define ETH_MACTSEACR_OSTEAC_24             (0x1000000U << ETH_MACTSEACR_OSTEAC_Pos)            /*!< 0x01000000 */
10462 #define ETH_MACTSEACR_OSTEAC_25             (0x2000000U << ETH_MACTSEACR_OSTEAC_Pos)            /*!< 0x02000000 */
10463 #define ETH_MACTSEACR_OSTEAC_26             (0x4000000U << ETH_MACTSEACR_OSTEAC_Pos)            /*!< 0x04000000 */
10464 #define ETH_MACTSEACR_OSTEAC_27             (0x8000000U << ETH_MACTSEACR_OSTEAC_Pos)            /*!< 0x08000000 */
10465 #define ETH_MACTSEACR_OSTEAC_28             (0x10000000U << ETH_MACTSEACR_OSTEAC_Pos)           /*!< 0x10000000 */
10466 #define ETH_MACTSEACR_OSTEAC_29             (0x20000000U << ETH_MACTSEACR_OSTEAC_Pos)           /*!< 0x20000000 */
10467 #define ETH_MACTSEACR_OSTEAC_30             (0x40000000U << ETH_MACTSEACR_OSTEAC_Pos)           /*!< 0x40000000 */
10468 #define ETH_MACTSEACR_OSTEAC_31             (0x80000000U << ETH_MACTSEACR_OSTEAC_Pos)           /*!< 0x80000000 */
10469 
10470 /*************  Bit definition for ETH_MACTSICNR register  *************/
10471 #define ETH_MACTSICNR_TSIC_Pos              (0U)
10472 #define ETH_MACTSICNR_TSIC_Msk              (0xFFFFFFFFU << ETH_MACTSICNR_TSIC_Pos)             /*!< 0xFFFFFFFF */
10473 #define ETH_MACTSICNR_TSIC                  ETH_MACTSICNR_TSIC_Msk                              /*!< Timestamp Ingress Correction */
10474 #define ETH_MACTSICNR_TSIC_0                (0x1U << ETH_MACTSICNR_TSIC_Pos)                    /*!< 0x00000001 */
10475 #define ETH_MACTSICNR_TSIC_1                (0x2U << ETH_MACTSICNR_TSIC_Pos)                    /*!< 0x00000002 */
10476 #define ETH_MACTSICNR_TSIC_2                (0x4U << ETH_MACTSICNR_TSIC_Pos)                    /*!< 0x00000004 */
10477 #define ETH_MACTSICNR_TSIC_3                (0x8U << ETH_MACTSICNR_TSIC_Pos)                    /*!< 0x00000008 */
10478 #define ETH_MACTSICNR_TSIC_4                (0x10U << ETH_MACTSICNR_TSIC_Pos)                   /*!< 0x00000010 */
10479 #define ETH_MACTSICNR_TSIC_5                (0x20U << ETH_MACTSICNR_TSIC_Pos)                   /*!< 0x00000020 */
10480 #define ETH_MACTSICNR_TSIC_6                (0x40U << ETH_MACTSICNR_TSIC_Pos)                   /*!< 0x00000040 */
10481 #define ETH_MACTSICNR_TSIC_7                (0x80U << ETH_MACTSICNR_TSIC_Pos)                   /*!< 0x00000080 */
10482 #define ETH_MACTSICNR_TSIC_8                (0x100U << ETH_MACTSICNR_TSIC_Pos)                  /*!< 0x00000100 */
10483 #define ETH_MACTSICNR_TSIC_9                (0x200U << ETH_MACTSICNR_TSIC_Pos)                  /*!< 0x00000200 */
10484 #define ETH_MACTSICNR_TSIC_10               (0x400U << ETH_MACTSICNR_TSIC_Pos)                  /*!< 0x00000400 */
10485 #define ETH_MACTSICNR_TSIC_11               (0x800U << ETH_MACTSICNR_TSIC_Pos)                  /*!< 0x00000800 */
10486 #define ETH_MACTSICNR_TSIC_12               (0x1000U << ETH_MACTSICNR_TSIC_Pos)                 /*!< 0x00001000 */
10487 #define ETH_MACTSICNR_TSIC_13               (0x2000U << ETH_MACTSICNR_TSIC_Pos)                 /*!< 0x00002000 */
10488 #define ETH_MACTSICNR_TSIC_14               (0x4000U << ETH_MACTSICNR_TSIC_Pos)                 /*!< 0x00004000 */
10489 #define ETH_MACTSICNR_TSIC_15               (0x8000U << ETH_MACTSICNR_TSIC_Pos)                 /*!< 0x00008000 */
10490 #define ETH_MACTSICNR_TSIC_16               (0x10000U << ETH_MACTSICNR_TSIC_Pos)                /*!< 0x00010000 */
10491 #define ETH_MACTSICNR_TSIC_17               (0x20000U << ETH_MACTSICNR_TSIC_Pos)                /*!< 0x00020000 */
10492 #define ETH_MACTSICNR_TSIC_18               (0x40000U << ETH_MACTSICNR_TSIC_Pos)                /*!< 0x00040000 */
10493 #define ETH_MACTSICNR_TSIC_19               (0x80000U << ETH_MACTSICNR_TSIC_Pos)                /*!< 0x00080000 */
10494 #define ETH_MACTSICNR_TSIC_20               (0x100000U << ETH_MACTSICNR_TSIC_Pos)               /*!< 0x00100000 */
10495 #define ETH_MACTSICNR_TSIC_21               (0x200000U << ETH_MACTSICNR_TSIC_Pos)               /*!< 0x00200000 */
10496 #define ETH_MACTSICNR_TSIC_22               (0x400000U << ETH_MACTSICNR_TSIC_Pos)               /*!< 0x00400000 */
10497 #define ETH_MACTSICNR_TSIC_23               (0x800000U << ETH_MACTSICNR_TSIC_Pos)               /*!< 0x00800000 */
10498 #define ETH_MACTSICNR_TSIC_24               (0x1000000U << ETH_MACTSICNR_TSIC_Pos)              /*!< 0x01000000 */
10499 #define ETH_MACTSICNR_TSIC_25               (0x2000000U << ETH_MACTSICNR_TSIC_Pos)              /*!< 0x02000000 */
10500 #define ETH_MACTSICNR_TSIC_26               (0x4000000U << ETH_MACTSICNR_TSIC_Pos)              /*!< 0x04000000 */
10501 #define ETH_MACTSICNR_TSIC_27               (0x8000000U << ETH_MACTSICNR_TSIC_Pos)              /*!< 0x08000000 */
10502 #define ETH_MACTSICNR_TSIC_28               (0x10000000U << ETH_MACTSICNR_TSIC_Pos)             /*!< 0x10000000 */
10503 #define ETH_MACTSICNR_TSIC_29               (0x20000000U << ETH_MACTSICNR_TSIC_Pos)             /*!< 0x20000000 */
10504 #define ETH_MACTSICNR_TSIC_30               (0x40000000U << ETH_MACTSICNR_TSIC_Pos)             /*!< 0x40000000 */
10505 #define ETH_MACTSICNR_TSIC_31               (0x80000000U << ETH_MACTSICNR_TSIC_Pos)             /*!< 0x80000000 */
10506 
10507 /*************  Bit definition for ETH_MACTSECNR register  *************/
10508 #define ETH_MACTSECNR_TSEC_Pos              (0U)
10509 #define ETH_MACTSECNR_TSEC_Msk              (0xFFFFFFFFU << ETH_MACTSECNR_TSEC_Pos)             /*!< 0xFFFFFFFF */
10510 #define ETH_MACTSECNR_TSEC                  ETH_MACTSECNR_TSEC_Msk                              /*!< Timestamp Egress Correction */
10511 #define ETH_MACTSECNR_TSEC_0                (0x1U << ETH_MACTSECNR_TSEC_Pos)                    /*!< 0x00000001 */
10512 #define ETH_MACTSECNR_TSEC_1                (0x2U << ETH_MACTSECNR_TSEC_Pos)                    /*!< 0x00000002 */
10513 #define ETH_MACTSECNR_TSEC_2                (0x4U << ETH_MACTSECNR_TSEC_Pos)                    /*!< 0x00000004 */
10514 #define ETH_MACTSECNR_TSEC_3                (0x8U << ETH_MACTSECNR_TSEC_Pos)                    /*!< 0x00000008 */
10515 #define ETH_MACTSECNR_TSEC_4                (0x10U << ETH_MACTSECNR_TSEC_Pos)                   /*!< 0x00000010 */
10516 #define ETH_MACTSECNR_TSEC_5                (0x20U << ETH_MACTSECNR_TSEC_Pos)                   /*!< 0x00000020 */
10517 #define ETH_MACTSECNR_TSEC_6                (0x40U << ETH_MACTSECNR_TSEC_Pos)                   /*!< 0x00000040 */
10518 #define ETH_MACTSECNR_TSEC_7                (0x80U << ETH_MACTSECNR_TSEC_Pos)                   /*!< 0x00000080 */
10519 #define ETH_MACTSECNR_TSEC_8                (0x100U << ETH_MACTSECNR_TSEC_Pos)                  /*!< 0x00000100 */
10520 #define ETH_MACTSECNR_TSEC_9                (0x200U << ETH_MACTSECNR_TSEC_Pos)                  /*!< 0x00000200 */
10521 #define ETH_MACTSECNR_TSEC_10               (0x400U << ETH_MACTSECNR_TSEC_Pos)                  /*!< 0x00000400 */
10522 #define ETH_MACTSECNR_TSEC_11               (0x800U << ETH_MACTSECNR_TSEC_Pos)                  /*!< 0x00000800 */
10523 #define ETH_MACTSECNR_TSEC_12               (0x1000U << ETH_MACTSECNR_TSEC_Pos)                 /*!< 0x00001000 */
10524 #define ETH_MACTSECNR_TSEC_13               (0x2000U << ETH_MACTSECNR_TSEC_Pos)                 /*!< 0x00002000 */
10525 #define ETH_MACTSECNR_TSEC_14               (0x4000U << ETH_MACTSECNR_TSEC_Pos)                 /*!< 0x00004000 */
10526 #define ETH_MACTSECNR_TSEC_15               (0x8000U << ETH_MACTSECNR_TSEC_Pos)                 /*!< 0x00008000 */
10527 #define ETH_MACTSECNR_TSEC_16               (0x10000U << ETH_MACTSECNR_TSEC_Pos)                /*!< 0x00010000 */
10528 #define ETH_MACTSECNR_TSEC_17               (0x20000U << ETH_MACTSECNR_TSEC_Pos)                /*!< 0x00020000 */
10529 #define ETH_MACTSECNR_TSEC_18               (0x40000U << ETH_MACTSECNR_TSEC_Pos)                /*!< 0x00040000 */
10530 #define ETH_MACTSECNR_TSEC_19               (0x80000U << ETH_MACTSECNR_TSEC_Pos)                /*!< 0x00080000 */
10531 #define ETH_MACTSECNR_TSEC_20               (0x100000U << ETH_MACTSECNR_TSEC_Pos)               /*!< 0x00100000 */
10532 #define ETH_MACTSECNR_TSEC_21               (0x200000U << ETH_MACTSECNR_TSEC_Pos)               /*!< 0x00200000 */
10533 #define ETH_MACTSECNR_TSEC_22               (0x400000U << ETH_MACTSECNR_TSEC_Pos)               /*!< 0x00400000 */
10534 #define ETH_MACTSECNR_TSEC_23               (0x800000U << ETH_MACTSECNR_TSEC_Pos)               /*!< 0x00800000 */
10535 #define ETH_MACTSECNR_TSEC_24               (0x1000000U << ETH_MACTSECNR_TSEC_Pos)              /*!< 0x01000000 */
10536 #define ETH_MACTSECNR_TSEC_25               (0x2000000U << ETH_MACTSECNR_TSEC_Pos)              /*!< 0x02000000 */
10537 #define ETH_MACTSECNR_TSEC_26               (0x4000000U << ETH_MACTSECNR_TSEC_Pos)              /*!< 0x04000000 */
10538 #define ETH_MACTSECNR_TSEC_27               (0x8000000U << ETH_MACTSECNR_TSEC_Pos)              /*!< 0x08000000 */
10539 #define ETH_MACTSECNR_TSEC_28               (0x10000000U << ETH_MACTSECNR_TSEC_Pos)             /*!< 0x10000000 */
10540 #define ETH_MACTSECNR_TSEC_29               (0x20000000U << ETH_MACTSECNR_TSEC_Pos)             /*!< 0x20000000 */
10541 #define ETH_MACTSECNR_TSEC_30               (0x40000000U << ETH_MACTSECNR_TSEC_Pos)             /*!< 0x40000000 */
10542 #define ETH_MACTSECNR_TSEC_31               (0x80000000U << ETH_MACTSECNR_TSEC_Pos)             /*!< 0x80000000 */
10543 
10544 /*************  Bit definition for ETH_MACPPSCR register  **************/
10545 #define ETH_MACPPSCR_PPSCTRL_Pos            (0U)
10546 #define ETH_MACPPSCR_PPSCTRL_Msk            (0xFU << ETH_MACPPSCR_PPSCTRL_Pos)                  /*!< 0x0000000F */
10547 #define ETH_MACPPSCR_PPSCTRL                ETH_MACPPSCR_PPSCTRL_Msk                            /*!< PPS Output Frequency Control */
10548 #define ETH_MACPPSCR_PPSCTRL_0              (0x1U << ETH_MACPPSCR_PPSCTRL_Pos)                  /*!< 0x00000001 */
10549 #define ETH_MACPPSCR_PPSCTRL_1              (0x2U << ETH_MACPPSCR_PPSCTRL_Pos)                  /*!< 0x00000002 */
10550 #define ETH_MACPPSCR_PPSCTRL_2              (0x4U << ETH_MACPPSCR_PPSCTRL_Pos)                  /*!< 0x00000004 */
10551 #define ETH_MACPPSCR_PPSCTRL_3              (0x8U << ETH_MACPPSCR_PPSCTRL_Pos)                  /*!< 0x00000008 */
10552 #define ETH_MACPPSCR_PPSEN0_Pos             (4U)
10553 #define ETH_MACPPSCR_PPSEN0_Msk             (0x1U << ETH_MACPPSCR_PPSEN0_Pos)                   /*!< 0x00000010 */
10554 #define ETH_MACPPSCR_PPSEN0                 ETH_MACPPSCR_PPSEN0_Msk                             /*!< Flexible PPS Output Mode Enable */
10555 #define ETH_MACPPSCR_TRGTMODSEL0_Pos        (5U)
10556 #define ETH_MACPPSCR_TRGTMODSEL0_Msk        (0x3U << ETH_MACPPSCR_TRGTMODSEL0_Pos)              /*!< 0x00000060 */
10557 #define ETH_MACPPSCR_TRGTMODSEL0            ETH_MACPPSCR_TRGTMODSEL0_Msk                        /*!< Target Time Register Mode for PPS Output */
10558 #define ETH_MACPPSCR_TRGTMODSEL0_0          (0x1U << ETH_MACPPSCR_TRGTMODSEL0_Pos)             /*!< 0x00000020 */
10559 #define ETH_MACPPSCR_TRGTMODSEL0_1          (0x2U << ETH_MACPPSCR_TRGTMODSEL0_Pos)             /*!< 0x00000040 */
10560 #define ETH_MACPPSCR_PPSCMD_Pos             (0U)
10561 #define ETH_MACPPSCR_PPSCMD_Msk             (0xFU << ETH_MACPPSCR_PPSCMD_Pos)                   /*!< 0x0000000F */
10562 #define ETH_MACPPSCR_PPSCMD                 ETH_MACPPSCR_PPSCMD_Msk                             /*!< Flexible PPS Output (ptp_pps_o[0]) Control */
10563 #define ETH_MACPPSCR_PPSCMD_0               (0x1U << ETH_MACPPSCR_PPSCMD_Pos)                   /*!< 0x00000001 */
10564 #define ETH_MACPPSCR_PPSCMD_1               (0x2U << ETH_MACPPSCR_PPSCMD_Pos)                   /*!< 0x00000002 */
10565 #define ETH_MACPPSCR_PPSCMD_2               (0x4U << ETH_MACPPSCR_PPSCMD_Pos)                   /*!< 0x00000004 */
10566 #define ETH_MACPPSCR_PPSCMD_3               (0x8U << ETH_MACPPSCR_PPSCMD_Pos)                   /*!< 0x00000008 */
10567 #define ETH_MACPPSCR_PPSEN0_Pos             (4U)
10568 #define ETH_MACPPSCR_PPSEN0_Msk             (0x1U << ETH_MACPPSCR_PPSEN0_Pos)                   /*!< 0x00000010 */
10569 #define ETH_MACPPSCR_PPSEN0                 ETH_MACPPSCR_PPSEN0_Msk                             /*!< Flexible PPS Output Mode Enable */
10570 #define ETH_MACPPSCR_TRGTMODSEL0_Pos        (5U)
10571 #define ETH_MACPPSCR_TRGTMODSEL0_Msk        (0x3U << ETH_MACPPSCR_TRGTMODSEL0_Pos)              /*!< 0x00000060 */
10572 #define ETH_MACPPSCR_TRGTMODSEL0            ETH_MACPPSCR_TRGTMODSEL0_Msk                        /*!< Target Time Register Mode for PPS Output */
10573 #define ETH_MACPPSCR_TRGTMODSEL0_0          (0x1U << ETH_MACPPSCR_TRGTMODSEL0_Pos)             /*!< 0x00000020 */
10574 #define ETH_MACPPSCR_TRGTMODSEL0_1          (0x2U << ETH_MACPPSCR_TRGTMODSEL0_Pos)             /*!< 0x00000040 */
10575 
10576 /************  Bit definition for ETH_MACPPSTTSR register  *************/
10577 #define ETH_MACPPSTTSR_TSTRH0_Pos           (0U)
10578 #define ETH_MACPPSTTSR_TSTRH0_Msk           (0xFFFFFFFFU << ETH_MACPPSTTSR_TSTRH0_Pos)          /*!< 0xFFFFFFFF */
10579 #define ETH_MACPPSTTSR_TSTRH0               ETH_MACPPSTTSR_TSTRH0_Msk                           /*!< PPS Target Time Seconds Register */
10580 #define ETH_MACPPSTTSR_TSTRH0_0             (0x1U << ETH_MACPPSTTSR_TSTRH0_Pos)                 /*!< 0x00000001 */
10581 #define ETH_MACPPSTTSR_TSTRH0_1             (0x2U << ETH_MACPPSTTSR_TSTRH0_Pos)                 /*!< 0x00000002 */
10582 #define ETH_MACPPSTTSR_TSTRH0_2             (0x4U << ETH_MACPPSTTSR_TSTRH0_Pos)                 /*!< 0x00000004 */
10583 #define ETH_MACPPSTTSR_TSTRH0_3             (0x8U << ETH_MACPPSTTSR_TSTRH0_Pos)                 /*!< 0x00000008 */
10584 #define ETH_MACPPSTTSR_TSTRH0_4             (0x10U << ETH_MACPPSTTSR_TSTRH0_Pos)                /*!< 0x00000010 */
10585 #define ETH_MACPPSTTSR_TSTRH0_5             (0x20U << ETH_MACPPSTTSR_TSTRH0_Pos)                /*!< 0x00000020 */
10586 #define ETH_MACPPSTTSR_TSTRH0_6             (0x40U << ETH_MACPPSTTSR_TSTRH0_Pos)                /*!< 0x00000040 */
10587 #define ETH_MACPPSTTSR_TSTRH0_7             (0x80U << ETH_MACPPSTTSR_TSTRH0_Pos)                /*!< 0x00000080 */
10588 #define ETH_MACPPSTTSR_TSTRH0_8             (0x100U << ETH_MACPPSTTSR_TSTRH0_Pos)               /*!< 0x00000100 */
10589 #define ETH_MACPPSTTSR_TSTRH0_9             (0x200U << ETH_MACPPSTTSR_TSTRH0_Pos)               /*!< 0x00000200 */
10590 #define ETH_MACPPSTTSR_TSTRH0_10            (0x400U << ETH_MACPPSTTSR_TSTRH0_Pos)               /*!< 0x00000400 */
10591 #define ETH_MACPPSTTSR_TSTRH0_11            (0x800U << ETH_MACPPSTTSR_TSTRH0_Pos)               /*!< 0x00000800 */
10592 #define ETH_MACPPSTTSR_TSTRH0_12            (0x1000U << ETH_MACPPSTTSR_TSTRH0_Pos)              /*!< 0x00001000 */
10593 #define ETH_MACPPSTTSR_TSTRH0_13            (0x2000U << ETH_MACPPSTTSR_TSTRH0_Pos)              /*!< 0x00002000 */
10594 #define ETH_MACPPSTTSR_TSTRH0_14            (0x4000U << ETH_MACPPSTTSR_TSTRH0_Pos)              /*!< 0x00004000 */
10595 #define ETH_MACPPSTTSR_TSTRH0_15            (0x8000U << ETH_MACPPSTTSR_TSTRH0_Pos)              /*!< 0x00008000 */
10596 #define ETH_MACPPSTTSR_TSTRH0_16            (0x10000U << ETH_MACPPSTTSR_TSTRH0_Pos)             /*!< 0x00010000 */
10597 #define ETH_MACPPSTTSR_TSTRH0_17            (0x20000U << ETH_MACPPSTTSR_TSTRH0_Pos)             /*!< 0x00020000 */
10598 #define ETH_MACPPSTTSR_TSTRH0_18            (0x40000U << ETH_MACPPSTTSR_TSTRH0_Pos)             /*!< 0x00040000 */
10599 #define ETH_MACPPSTTSR_TSTRH0_19            (0x80000U << ETH_MACPPSTTSR_TSTRH0_Pos)             /*!< 0x00080000 */
10600 #define ETH_MACPPSTTSR_TSTRH0_20            (0x100000U << ETH_MACPPSTTSR_TSTRH0_Pos)            /*!< 0x00100000 */
10601 #define ETH_MACPPSTTSR_TSTRH0_21            (0x200000U << ETH_MACPPSTTSR_TSTRH0_Pos)            /*!< 0x00200000 */
10602 #define ETH_MACPPSTTSR_TSTRH0_22            (0x400000U << ETH_MACPPSTTSR_TSTRH0_Pos)            /*!< 0x00400000 */
10603 #define ETH_MACPPSTTSR_TSTRH0_23            (0x800000U << ETH_MACPPSTTSR_TSTRH0_Pos)            /*!< 0x00800000 */
10604 #define ETH_MACPPSTTSR_TSTRH0_24            (0x1000000U << ETH_MACPPSTTSR_TSTRH0_Pos)           /*!< 0x01000000 */
10605 #define ETH_MACPPSTTSR_TSTRH0_25            (0x2000000U << ETH_MACPPSTTSR_TSTRH0_Pos)           /*!< 0x02000000 */
10606 #define ETH_MACPPSTTSR_TSTRH0_26            (0x4000000U << ETH_MACPPSTTSR_TSTRH0_Pos)           /*!< 0x04000000 */
10607 #define ETH_MACPPSTTSR_TSTRH0_27            (0x8000000U << ETH_MACPPSTTSR_TSTRH0_Pos)           /*!< 0x08000000 */
10608 #define ETH_MACPPSTTSR_TSTRH0_28            (0x10000000U << ETH_MACPPSTTSR_TSTRH0_Pos)          /*!< 0x10000000 */
10609 #define ETH_MACPPSTTSR_TSTRH0_29            (0x20000000U << ETH_MACPPSTTSR_TSTRH0_Pos)          /*!< 0x20000000 */
10610 #define ETH_MACPPSTTSR_TSTRH0_30            (0x40000000U << ETH_MACPPSTTSR_TSTRH0_Pos)          /*!< 0x40000000 */
10611 #define ETH_MACPPSTTSR_TSTRH0_31            (0x80000000U << ETH_MACPPSTTSR_TSTRH0_Pos)          /*!< 0x80000000 */
10612 
10613 /************  Bit definition for ETH_MACPPSTTNR register  *************/
10614 #define ETH_MACPPSTTNR_TTSL0_Pos            (0U)
10615 #define ETH_MACPPSTTNR_TTSL0_Msk            (0x7FFFFFFFU << ETH_MACPPSTTNR_TTSL0_Pos)           /*!< 0x7FFFFFFF */
10616 #define ETH_MACPPSTTNR_TTSL0                ETH_MACPPSTTNR_TTSL0_Msk                            /*!< Target Time Low for PPS Register */
10617 #define ETH_MACPPSTTNR_TTSL0_0              (0x1U << ETH_MACPPSTTNR_TTSL0_Pos)                  /*!< 0x00000001 */
10618 #define ETH_MACPPSTTNR_TTSL0_1              (0x2U << ETH_MACPPSTTNR_TTSL0_Pos)                  /*!< 0x00000002 */
10619 #define ETH_MACPPSTTNR_TTSL0_2              (0x4U << ETH_MACPPSTTNR_TTSL0_Pos)                  /*!< 0x00000004 */
10620 #define ETH_MACPPSTTNR_TTSL0_3              (0x8U << ETH_MACPPSTTNR_TTSL0_Pos)                  /*!< 0x00000008 */
10621 #define ETH_MACPPSTTNR_TTSL0_4              (0x10U << ETH_MACPPSTTNR_TTSL0_Pos)                 /*!< 0x00000010 */
10622 #define ETH_MACPPSTTNR_TTSL0_5              (0x20U << ETH_MACPPSTTNR_TTSL0_Pos)                 /*!< 0x00000020 */
10623 #define ETH_MACPPSTTNR_TTSL0_6              (0x40U << ETH_MACPPSTTNR_TTSL0_Pos)                 /*!< 0x00000040 */
10624 #define ETH_MACPPSTTNR_TTSL0_7              (0x80U << ETH_MACPPSTTNR_TTSL0_Pos)                 /*!< 0x00000080 */
10625 #define ETH_MACPPSTTNR_TTSL0_8              (0x100U << ETH_MACPPSTTNR_TTSL0_Pos)                /*!< 0x00000100 */
10626 #define ETH_MACPPSTTNR_TTSL0_9              (0x200U << ETH_MACPPSTTNR_TTSL0_Pos)                /*!< 0x00000200 */
10627 #define ETH_MACPPSTTNR_TTSL0_10             (0x400U << ETH_MACPPSTTNR_TTSL0_Pos)                /*!< 0x00000400 */
10628 #define ETH_MACPPSTTNR_TTSL0_11             (0x800U << ETH_MACPPSTTNR_TTSL0_Pos)                /*!< 0x00000800 */
10629 #define ETH_MACPPSTTNR_TTSL0_12             (0x1000U << ETH_MACPPSTTNR_TTSL0_Pos)               /*!< 0x00001000 */
10630 #define ETH_MACPPSTTNR_TTSL0_13             (0x2000U << ETH_MACPPSTTNR_TTSL0_Pos)               /*!< 0x00002000 */
10631 #define ETH_MACPPSTTNR_TTSL0_14             (0x4000U << ETH_MACPPSTTNR_TTSL0_Pos)               /*!< 0x00004000 */
10632 #define ETH_MACPPSTTNR_TTSL0_15             (0x8000U << ETH_MACPPSTTNR_TTSL0_Pos)               /*!< 0x00008000 */
10633 #define ETH_MACPPSTTNR_TTSL0_16             (0x10000U << ETH_MACPPSTTNR_TTSL0_Pos)              /*!< 0x00010000 */
10634 #define ETH_MACPPSTTNR_TTSL0_17             (0x20000U << ETH_MACPPSTTNR_TTSL0_Pos)              /*!< 0x00020000 */
10635 #define ETH_MACPPSTTNR_TTSL0_18             (0x40000U << ETH_MACPPSTTNR_TTSL0_Pos)              /*!< 0x00040000 */
10636 #define ETH_MACPPSTTNR_TTSL0_19             (0x80000U << ETH_MACPPSTTNR_TTSL0_Pos)              /*!< 0x00080000 */
10637 #define ETH_MACPPSTTNR_TTSL0_20             (0x100000U << ETH_MACPPSTTNR_TTSL0_Pos)             /*!< 0x00100000 */
10638 #define ETH_MACPPSTTNR_TTSL0_21             (0x200000U << ETH_MACPPSTTNR_TTSL0_Pos)             /*!< 0x00200000 */
10639 #define ETH_MACPPSTTNR_TTSL0_22             (0x400000U << ETH_MACPPSTTNR_TTSL0_Pos)             /*!< 0x00400000 */
10640 #define ETH_MACPPSTTNR_TTSL0_23             (0x800000U << ETH_MACPPSTTNR_TTSL0_Pos)             /*!< 0x00800000 */
10641 #define ETH_MACPPSTTNR_TTSL0_24             (0x1000000U << ETH_MACPPSTTNR_TTSL0_Pos)            /*!< 0x01000000 */
10642 #define ETH_MACPPSTTNR_TTSL0_25             (0x2000000U << ETH_MACPPSTTNR_TTSL0_Pos)            /*!< 0x02000000 */
10643 #define ETH_MACPPSTTNR_TTSL0_26             (0x4000000U << ETH_MACPPSTTNR_TTSL0_Pos)            /*!< 0x04000000 */
10644 #define ETH_MACPPSTTNR_TTSL0_27             (0x8000000U << ETH_MACPPSTTNR_TTSL0_Pos)            /*!< 0x08000000 */
10645 #define ETH_MACPPSTTNR_TTSL0_28             (0x10000000U << ETH_MACPPSTTNR_TTSL0_Pos)           /*!< 0x10000000 */
10646 #define ETH_MACPPSTTNR_TTSL0_29             (0x20000000U << ETH_MACPPSTTNR_TTSL0_Pos)           /*!< 0x20000000 */
10647 #define ETH_MACPPSTTNR_TTSL0_30             (0x40000000U << ETH_MACPPSTTNR_TTSL0_Pos)           /*!< 0x40000000 */
10648 #define ETH_MACPPSTTNR_TRGTBUSY0_Pos        (31U)
10649 #define ETH_MACPPSTTNR_TRGTBUSY0_Msk        (0x1U << ETH_MACPPSTTNR_TRGTBUSY0_Pos)              /*!< 0x80000000 */
10650 #define ETH_MACPPSTTNR_TRGTBUSY0            ETH_MACPPSTTNR_TRGTBUSY0_Msk                        /*!< PPS Target Time Register Busy */
10651 
10652 /*************  Bit definition for ETH_MACPPSIR register  **************/
10653 #define ETH_MACPPSIR_PPSINT0_Pos            (0U)
10654 #define ETH_MACPPSIR_PPSINT0_Msk            (0xFFFFFFFFU << ETH_MACPPSIR_PPSINT0_Pos)           /*!< 0xFFFFFFFF */
10655 #define ETH_MACPPSIR_PPSINT0                ETH_MACPPSIR_PPSINT0_Msk                            /*!< PPS Output Signal Interval */
10656 #define ETH_MACPPSIR_PPSINT0_0              (0x1U << ETH_MACPPSIR_PPSINT0_Pos)                  /*!< 0x00000001 */
10657 #define ETH_MACPPSIR_PPSINT0_1              (0x2U << ETH_MACPPSIR_PPSINT0_Pos)                  /*!< 0x00000002 */
10658 #define ETH_MACPPSIR_PPSINT0_2              (0x4U << ETH_MACPPSIR_PPSINT0_Pos)                  /*!< 0x00000004 */
10659 #define ETH_MACPPSIR_PPSINT0_3              (0x8U << ETH_MACPPSIR_PPSINT0_Pos)                  /*!< 0x00000008 */
10660 #define ETH_MACPPSIR_PPSINT0_4              (0x10U << ETH_MACPPSIR_PPSINT0_Pos)                 /*!< 0x00000010 */
10661 #define ETH_MACPPSIR_PPSINT0_5              (0x20U << ETH_MACPPSIR_PPSINT0_Pos)                 /*!< 0x00000020 */
10662 #define ETH_MACPPSIR_PPSINT0_6              (0x40U << ETH_MACPPSIR_PPSINT0_Pos)                 /*!< 0x00000040 */
10663 #define ETH_MACPPSIR_PPSINT0_7              (0x80U << ETH_MACPPSIR_PPSINT0_Pos)                 /*!< 0x00000080 */
10664 #define ETH_MACPPSIR_PPSINT0_8              (0x100U << ETH_MACPPSIR_PPSINT0_Pos)                /*!< 0x00000100 */
10665 #define ETH_MACPPSIR_PPSINT0_9              (0x200U << ETH_MACPPSIR_PPSINT0_Pos)                /*!< 0x00000200 */
10666 #define ETH_MACPPSIR_PPSINT0_10             (0x400U << ETH_MACPPSIR_PPSINT0_Pos)                /*!< 0x00000400 */
10667 #define ETH_MACPPSIR_PPSINT0_11             (0x800U << ETH_MACPPSIR_PPSINT0_Pos)                /*!< 0x00000800 */
10668 #define ETH_MACPPSIR_PPSINT0_12             (0x1000U << ETH_MACPPSIR_PPSINT0_Pos)               /*!< 0x00001000 */
10669 #define ETH_MACPPSIR_PPSINT0_13             (0x2000U << ETH_MACPPSIR_PPSINT0_Pos)               /*!< 0x00002000 */
10670 #define ETH_MACPPSIR_PPSINT0_14             (0x4000U << ETH_MACPPSIR_PPSINT0_Pos)               /*!< 0x00004000 */
10671 #define ETH_MACPPSIR_PPSINT0_15             (0x8000U << ETH_MACPPSIR_PPSINT0_Pos)               /*!< 0x00008000 */
10672 #define ETH_MACPPSIR_PPSINT0_16             (0x10000U << ETH_MACPPSIR_PPSINT0_Pos)              /*!< 0x00010000 */
10673 #define ETH_MACPPSIR_PPSINT0_17             (0x20000U << ETH_MACPPSIR_PPSINT0_Pos)              /*!< 0x00020000 */
10674 #define ETH_MACPPSIR_PPSINT0_18             (0x40000U << ETH_MACPPSIR_PPSINT0_Pos)              /*!< 0x00040000 */
10675 #define ETH_MACPPSIR_PPSINT0_19             (0x80000U << ETH_MACPPSIR_PPSINT0_Pos)              /*!< 0x00080000 */
10676 #define ETH_MACPPSIR_PPSINT0_20             (0x100000U << ETH_MACPPSIR_PPSINT0_Pos)             /*!< 0x00100000 */
10677 #define ETH_MACPPSIR_PPSINT0_21             (0x200000U << ETH_MACPPSIR_PPSINT0_Pos)             /*!< 0x00200000 */
10678 #define ETH_MACPPSIR_PPSINT0_22             (0x400000U << ETH_MACPPSIR_PPSINT0_Pos)             /*!< 0x00400000 */
10679 #define ETH_MACPPSIR_PPSINT0_23             (0x800000U << ETH_MACPPSIR_PPSINT0_Pos)             /*!< 0x00800000 */
10680 #define ETH_MACPPSIR_PPSINT0_24             (0x1000000U << ETH_MACPPSIR_PPSINT0_Pos)            /*!< 0x01000000 */
10681 #define ETH_MACPPSIR_PPSINT0_25             (0x2000000U << ETH_MACPPSIR_PPSINT0_Pos)            /*!< 0x02000000 */
10682 #define ETH_MACPPSIR_PPSINT0_26             (0x4000000U << ETH_MACPPSIR_PPSINT0_Pos)            /*!< 0x04000000 */
10683 #define ETH_MACPPSIR_PPSINT0_27             (0x8000000U << ETH_MACPPSIR_PPSINT0_Pos)            /*!< 0x08000000 */
10684 #define ETH_MACPPSIR_PPSINT0_28             (0x10000000U << ETH_MACPPSIR_PPSINT0_Pos)           /*!< 0x10000000 */
10685 #define ETH_MACPPSIR_PPSINT0_29             (0x20000000U << ETH_MACPPSIR_PPSINT0_Pos)           /*!< 0x20000000 */
10686 #define ETH_MACPPSIR_PPSINT0_30             (0x40000000U << ETH_MACPPSIR_PPSINT0_Pos)           /*!< 0x40000000 */
10687 #define ETH_MACPPSIR_PPSINT0_31             (0x80000000U << ETH_MACPPSIR_PPSINT0_Pos)           /*!< 0x80000000 */
10688 
10689 /*************  Bit definition for ETH_MACPPSWR register  **************/
10690 #define ETH_MACPPSWR_PPSWIDTH0_Pos          (0U)
10691 #define ETH_MACPPSWR_PPSWIDTH0_Msk          (0xFFFFFFFFU << ETH_MACPPSWR_PPSWIDTH0_Pos)         /*!< 0xFFFFFFFF */
10692 #define ETH_MACPPSWR_PPSWIDTH0              ETH_MACPPSWR_PPSWIDTH0_Msk                          /*!< PPS Output Signal Width */
10693 #define ETH_MACPPSWR_PPSWIDTH0_0            (0x1U << ETH_MACPPSWR_PPSWIDTH0_Pos)                /*!< 0x00000001 */
10694 #define ETH_MACPPSWR_PPSWIDTH0_1            (0x2U << ETH_MACPPSWR_PPSWIDTH0_Pos)                /*!< 0x00000002 */
10695 #define ETH_MACPPSWR_PPSWIDTH0_2            (0x4U << ETH_MACPPSWR_PPSWIDTH0_Pos)                /*!< 0x00000004 */
10696 #define ETH_MACPPSWR_PPSWIDTH0_3            (0x8U << ETH_MACPPSWR_PPSWIDTH0_Pos)                /*!< 0x00000008 */
10697 #define ETH_MACPPSWR_PPSWIDTH0_4            (0x10U << ETH_MACPPSWR_PPSWIDTH0_Pos)               /*!< 0x00000010 */
10698 #define ETH_MACPPSWR_PPSWIDTH0_5            (0x20U << ETH_MACPPSWR_PPSWIDTH0_Pos)               /*!< 0x00000020 */
10699 #define ETH_MACPPSWR_PPSWIDTH0_6            (0x40U << ETH_MACPPSWR_PPSWIDTH0_Pos)               /*!< 0x00000040 */
10700 #define ETH_MACPPSWR_PPSWIDTH0_7            (0x80U << ETH_MACPPSWR_PPSWIDTH0_Pos)               /*!< 0x00000080 */
10701 #define ETH_MACPPSWR_PPSWIDTH0_8            (0x100U << ETH_MACPPSWR_PPSWIDTH0_Pos)              /*!< 0x00000100 */
10702 #define ETH_MACPPSWR_PPSWIDTH0_9            (0x200U << ETH_MACPPSWR_PPSWIDTH0_Pos)              /*!< 0x00000200 */
10703 #define ETH_MACPPSWR_PPSWIDTH0_10           (0x400U << ETH_MACPPSWR_PPSWIDTH0_Pos)              /*!< 0x00000400 */
10704 #define ETH_MACPPSWR_PPSWIDTH0_11           (0x800U << ETH_MACPPSWR_PPSWIDTH0_Pos)              /*!< 0x00000800 */
10705 #define ETH_MACPPSWR_PPSWIDTH0_12           (0x1000U << ETH_MACPPSWR_PPSWIDTH0_Pos)             /*!< 0x00001000 */
10706 #define ETH_MACPPSWR_PPSWIDTH0_13           (0x2000U << ETH_MACPPSWR_PPSWIDTH0_Pos)             /*!< 0x00002000 */
10707 #define ETH_MACPPSWR_PPSWIDTH0_14           (0x4000U << ETH_MACPPSWR_PPSWIDTH0_Pos)             /*!< 0x00004000 */
10708 #define ETH_MACPPSWR_PPSWIDTH0_15           (0x8000U << ETH_MACPPSWR_PPSWIDTH0_Pos)             /*!< 0x00008000 */
10709 #define ETH_MACPPSWR_PPSWIDTH0_16           (0x10000U << ETH_MACPPSWR_PPSWIDTH0_Pos)            /*!< 0x00010000 */
10710 #define ETH_MACPPSWR_PPSWIDTH0_17           (0x20000U << ETH_MACPPSWR_PPSWIDTH0_Pos)            /*!< 0x00020000 */
10711 #define ETH_MACPPSWR_PPSWIDTH0_18           (0x40000U << ETH_MACPPSWR_PPSWIDTH0_Pos)            /*!< 0x00040000 */
10712 #define ETH_MACPPSWR_PPSWIDTH0_19           (0x80000U << ETH_MACPPSWR_PPSWIDTH0_Pos)            /*!< 0x00080000 */
10713 #define ETH_MACPPSWR_PPSWIDTH0_20           (0x100000U << ETH_MACPPSWR_PPSWIDTH0_Pos)           /*!< 0x00100000 */
10714 #define ETH_MACPPSWR_PPSWIDTH0_21           (0x200000U << ETH_MACPPSWR_PPSWIDTH0_Pos)           /*!< 0x00200000 */
10715 #define ETH_MACPPSWR_PPSWIDTH0_22           (0x400000U << ETH_MACPPSWR_PPSWIDTH0_Pos)           /*!< 0x00400000 */
10716 #define ETH_MACPPSWR_PPSWIDTH0_23           (0x800000U << ETH_MACPPSWR_PPSWIDTH0_Pos)           /*!< 0x00800000 */
10717 #define ETH_MACPPSWR_PPSWIDTH0_24           (0x1000000U << ETH_MACPPSWR_PPSWIDTH0_Pos)          /*!< 0x01000000 */
10718 #define ETH_MACPPSWR_PPSWIDTH0_25           (0x2000000U << ETH_MACPPSWR_PPSWIDTH0_Pos)          /*!< 0x02000000 */
10719 #define ETH_MACPPSWR_PPSWIDTH0_26           (0x4000000U << ETH_MACPPSWR_PPSWIDTH0_Pos)          /*!< 0x04000000 */
10720 #define ETH_MACPPSWR_PPSWIDTH0_27           (0x8000000U << ETH_MACPPSWR_PPSWIDTH0_Pos)          /*!< 0x08000000 */
10721 #define ETH_MACPPSWR_PPSWIDTH0_28           (0x10000000U << ETH_MACPPSWR_PPSWIDTH0_Pos)         /*!< 0x10000000 */
10722 #define ETH_MACPPSWR_PPSWIDTH0_29           (0x20000000U << ETH_MACPPSWR_PPSWIDTH0_Pos)         /*!< 0x20000000 */
10723 #define ETH_MACPPSWR_PPSWIDTH0_30           (0x40000000U << ETH_MACPPSWR_PPSWIDTH0_Pos)         /*!< 0x40000000 */
10724 #define ETH_MACPPSWR_PPSWIDTH0_31           (0x80000000U << ETH_MACPPSWR_PPSWIDTH0_Pos)         /*!< 0x80000000 */
10725 
10726 /**************  Bit definition for ETH_MACPOCR register  **************/
10727 #define ETH_MACPOCR_PTOEN_Pos               (0U)
10728 #define ETH_MACPOCR_PTOEN_Msk               (0x1U << ETH_MACPOCR_PTOEN_Pos)                     /*!< 0x00000001 */
10729 #define ETH_MACPOCR_PTOEN                   ETH_MACPOCR_PTOEN_Msk                               /*!< PTP Offload Enable */
10730 #define ETH_MACPOCR_ASYNCEN_Pos             (1U)
10731 #define ETH_MACPOCR_ASYNCEN_Msk             (0x1U << ETH_MACPOCR_ASYNCEN_Pos)                   /*!< 0x00000002 */
10732 #define ETH_MACPOCR_ASYNCEN                 ETH_MACPOCR_ASYNCEN_Msk                             /*!< Automatic PTP SYNC message Enable */
10733 #define ETH_MACPOCR_APDREQEN_Pos            (2U)
10734 #define ETH_MACPOCR_APDREQEN_Msk            (0x1U << ETH_MACPOCR_APDREQEN_Pos)                  /*!< 0x00000004 */
10735 #define ETH_MACPOCR_APDREQEN                ETH_MACPOCR_APDREQEN_Msk                            /*!< Automatic PTP Pdelay_Req message Enable */
10736 #define ETH_MACPOCR_ASYNCTRIG_Pos           (4U)
10737 #define ETH_MACPOCR_ASYNCTRIG_Msk           (0x1U << ETH_MACPOCR_ASYNCTRIG_Pos)                 /*!< 0x00000010 */
10738 #define ETH_MACPOCR_ASYNCTRIG               ETH_MACPOCR_ASYNCTRIG_Msk                           /*!< Automatic PTP SYNC message Trigger */
10739 #define ETH_MACPOCR_APDREQTRIG_Pos          (5U)
10740 #define ETH_MACPOCR_APDREQTRIG_Msk          (0x1U << ETH_MACPOCR_APDREQTRIG_Pos)                /*!< 0x00000020 */
10741 #define ETH_MACPOCR_APDREQTRIG              ETH_MACPOCR_APDREQTRIG_Msk                          /*!< Automatic PTP Pdelay_Req message Trigger */
10742 #define ETH_MACPOCR_DRRDIS_Pos              (6U)
10743 #define ETH_MACPOCR_DRRDIS_Msk              (0x1U << ETH_MACPOCR_DRRDIS_Pos)                    /*!< 0x00000040 */
10744 #define ETH_MACPOCR_DRRDIS                  ETH_MACPOCR_DRRDIS_Msk                              /*!< Disable PTO Delay Request/Response response generation */
10745 #define ETH_MACPOCR_DN_Pos                  (8U)
10746 #define ETH_MACPOCR_DN_Msk                  (0xFFU << ETH_MACPOCR_DN_Pos)                       /*!< 0x0000FF00 */
10747 #define ETH_MACPOCR_DN                      ETH_MACPOCR_DN_Msk                                  /*!< Domain Number */
10748 #define ETH_MACPOCR_DN_0                    (0x1U << ETH_MACPOCR_DN_Pos)                      /*!< 0x00000100 */
10749 #define ETH_MACPOCR_DN_1                    (0x2U << ETH_MACPOCR_DN_Pos)                      /*!< 0x00000200 */
10750 #define ETH_MACPOCR_DN_2                    (0x4U << ETH_MACPOCR_DN_Pos)                      /*!< 0x00000400 */
10751 #define ETH_MACPOCR_DN_3                    (0x8U << ETH_MACPOCR_DN_Pos)                      /*!< 0x00000800 */
10752 #define ETH_MACPOCR_DN_4                    (0x10U << ETH_MACPOCR_DN_Pos)                     /*!< 0x00001000 */
10753 #define ETH_MACPOCR_DN_5                    (0x20U << ETH_MACPOCR_DN_Pos)                     /*!< 0x00002000 */
10754 #define ETH_MACPOCR_DN_6                    (0x40U << ETH_MACPOCR_DN_Pos)                     /*!< 0x00004000 */
10755 #define ETH_MACPOCR_DN_7                    (0x80U << ETH_MACPOCR_DN_Pos)                     /*!< 0x00008000 */
10756 
10757 /*************  Bit definition for ETH_MACSPI0R register  **************/
10758 #define ETH_MACSPI0R_SPI0_Pos               (0U)
10759 #define ETH_MACSPI0R_SPI0_Msk               (0xFFFFFFFFU << ETH_MACSPI0R_SPI0_Pos)              /*!< 0xFFFFFFFF */
10760 #define ETH_MACSPI0R_SPI0                   ETH_MACSPI0R_SPI0_Msk                               /*!< Source Port Identity 0 */
10761 #define ETH_MACSPI0R_SPI0_0                 (0x1U << ETH_MACSPI0R_SPI0_Pos)                     /*!< 0x00000001 */
10762 #define ETH_MACSPI0R_SPI0_1                 (0x2U << ETH_MACSPI0R_SPI0_Pos)                     /*!< 0x00000002 */
10763 #define ETH_MACSPI0R_SPI0_2                 (0x4U << ETH_MACSPI0R_SPI0_Pos)                     /*!< 0x00000004 */
10764 #define ETH_MACSPI0R_SPI0_3                 (0x8U << ETH_MACSPI0R_SPI0_Pos)                     /*!< 0x00000008 */
10765 #define ETH_MACSPI0R_SPI0_4                 (0x10U << ETH_MACSPI0R_SPI0_Pos)                    /*!< 0x00000010 */
10766 #define ETH_MACSPI0R_SPI0_5                 (0x20U << ETH_MACSPI0R_SPI0_Pos)                    /*!< 0x00000020 */
10767 #define ETH_MACSPI0R_SPI0_6                 (0x40U << ETH_MACSPI0R_SPI0_Pos)                    /*!< 0x00000040 */
10768 #define ETH_MACSPI0R_SPI0_7                 (0x80U << ETH_MACSPI0R_SPI0_Pos)                    /*!< 0x00000080 */
10769 #define ETH_MACSPI0R_SPI0_8                 (0x100U << ETH_MACSPI0R_SPI0_Pos)                   /*!< 0x00000100 */
10770 #define ETH_MACSPI0R_SPI0_9                 (0x200U << ETH_MACSPI0R_SPI0_Pos)                   /*!< 0x00000200 */
10771 #define ETH_MACSPI0R_SPI0_10                (0x400U << ETH_MACSPI0R_SPI0_Pos)                   /*!< 0x00000400 */
10772 #define ETH_MACSPI0R_SPI0_11                (0x800U << ETH_MACSPI0R_SPI0_Pos)                   /*!< 0x00000800 */
10773 #define ETH_MACSPI0R_SPI0_12                (0x1000U << ETH_MACSPI0R_SPI0_Pos)                  /*!< 0x00001000 */
10774 #define ETH_MACSPI0R_SPI0_13                (0x2000U << ETH_MACSPI0R_SPI0_Pos)                  /*!< 0x00002000 */
10775 #define ETH_MACSPI0R_SPI0_14                (0x4000U << ETH_MACSPI0R_SPI0_Pos)                  /*!< 0x00004000 */
10776 #define ETH_MACSPI0R_SPI0_15                (0x8000U << ETH_MACSPI0R_SPI0_Pos)                  /*!< 0x00008000 */
10777 #define ETH_MACSPI0R_SPI0_16                (0x10000U << ETH_MACSPI0R_SPI0_Pos)                 /*!< 0x00010000 */
10778 #define ETH_MACSPI0R_SPI0_17                (0x20000U << ETH_MACSPI0R_SPI0_Pos)                 /*!< 0x00020000 */
10779 #define ETH_MACSPI0R_SPI0_18                (0x40000U << ETH_MACSPI0R_SPI0_Pos)                 /*!< 0x00040000 */
10780 #define ETH_MACSPI0R_SPI0_19                (0x80000U << ETH_MACSPI0R_SPI0_Pos)                 /*!< 0x00080000 */
10781 #define ETH_MACSPI0R_SPI0_20                (0x100000U << ETH_MACSPI0R_SPI0_Pos)                /*!< 0x00100000 */
10782 #define ETH_MACSPI0R_SPI0_21                (0x200000U << ETH_MACSPI0R_SPI0_Pos)                /*!< 0x00200000 */
10783 #define ETH_MACSPI0R_SPI0_22                (0x400000U << ETH_MACSPI0R_SPI0_Pos)                /*!< 0x00400000 */
10784 #define ETH_MACSPI0R_SPI0_23                (0x800000U << ETH_MACSPI0R_SPI0_Pos)                /*!< 0x00800000 */
10785 #define ETH_MACSPI0R_SPI0_24                (0x1000000U << ETH_MACSPI0R_SPI0_Pos)               /*!< 0x01000000 */
10786 #define ETH_MACSPI0R_SPI0_25                (0x2000000U << ETH_MACSPI0R_SPI0_Pos)               /*!< 0x02000000 */
10787 #define ETH_MACSPI0R_SPI0_26                (0x4000000U << ETH_MACSPI0R_SPI0_Pos)               /*!< 0x04000000 */
10788 #define ETH_MACSPI0R_SPI0_27                (0x8000000U << ETH_MACSPI0R_SPI0_Pos)               /*!< 0x08000000 */
10789 #define ETH_MACSPI0R_SPI0_28                (0x10000000U << ETH_MACSPI0R_SPI0_Pos)              /*!< 0x10000000 */
10790 #define ETH_MACSPI0R_SPI0_29                (0x20000000U << ETH_MACSPI0R_SPI0_Pos)              /*!< 0x20000000 */
10791 #define ETH_MACSPI0R_SPI0_30                (0x40000000U << ETH_MACSPI0R_SPI0_Pos)              /*!< 0x40000000 */
10792 #define ETH_MACSPI0R_SPI0_31                (0x80000000U << ETH_MACSPI0R_SPI0_Pos)              /*!< 0x80000000 */
10793 
10794 /*************  Bit definition for ETH_MACSPI1R register  **************/
10795 #define ETH_MACSPI1R_SPI1_Pos               (0U)
10796 #define ETH_MACSPI1R_SPI1_Msk               (0xFFFFFFFFU << ETH_MACSPI1R_SPI1_Pos)              /*!< 0xFFFFFFFF */
10797 #define ETH_MACSPI1R_SPI1                   ETH_MACSPI1R_SPI1_Msk                               /*!< Source Port Identity 1 */
10798 #define ETH_MACSPI1R_SPI1_0                 (0x1U << ETH_MACSPI1R_SPI1_Pos)                     /*!< 0x00000001 */
10799 #define ETH_MACSPI1R_SPI1_1                 (0x2U << ETH_MACSPI1R_SPI1_Pos)                     /*!< 0x00000002 */
10800 #define ETH_MACSPI1R_SPI1_2                 (0x4U << ETH_MACSPI1R_SPI1_Pos)                     /*!< 0x00000004 */
10801 #define ETH_MACSPI1R_SPI1_3                 (0x8U << ETH_MACSPI1R_SPI1_Pos)                     /*!< 0x00000008 */
10802 #define ETH_MACSPI1R_SPI1_4                 (0x10U << ETH_MACSPI1R_SPI1_Pos)                    /*!< 0x00000010 */
10803 #define ETH_MACSPI1R_SPI1_5                 (0x20U << ETH_MACSPI1R_SPI1_Pos)                    /*!< 0x00000020 */
10804 #define ETH_MACSPI1R_SPI1_6                 (0x40U << ETH_MACSPI1R_SPI1_Pos)                    /*!< 0x00000040 */
10805 #define ETH_MACSPI1R_SPI1_7                 (0x80U << ETH_MACSPI1R_SPI1_Pos)                    /*!< 0x00000080 */
10806 #define ETH_MACSPI1R_SPI1_8                 (0x100U << ETH_MACSPI1R_SPI1_Pos)                   /*!< 0x00000100 */
10807 #define ETH_MACSPI1R_SPI1_9                 (0x200U << ETH_MACSPI1R_SPI1_Pos)                   /*!< 0x00000200 */
10808 #define ETH_MACSPI1R_SPI1_10                (0x400U << ETH_MACSPI1R_SPI1_Pos)                   /*!< 0x00000400 */
10809 #define ETH_MACSPI1R_SPI1_11                (0x800U << ETH_MACSPI1R_SPI1_Pos)                   /*!< 0x00000800 */
10810 #define ETH_MACSPI1R_SPI1_12                (0x1000U << ETH_MACSPI1R_SPI1_Pos)                  /*!< 0x00001000 */
10811 #define ETH_MACSPI1R_SPI1_13                (0x2000U << ETH_MACSPI1R_SPI1_Pos)                  /*!< 0x00002000 */
10812 #define ETH_MACSPI1R_SPI1_14                (0x4000U << ETH_MACSPI1R_SPI1_Pos)                  /*!< 0x00004000 */
10813 #define ETH_MACSPI1R_SPI1_15                (0x8000U << ETH_MACSPI1R_SPI1_Pos)                  /*!< 0x00008000 */
10814 #define ETH_MACSPI1R_SPI1_16                (0x10000U << ETH_MACSPI1R_SPI1_Pos)                 /*!< 0x00010000 */
10815 #define ETH_MACSPI1R_SPI1_17                (0x20000U << ETH_MACSPI1R_SPI1_Pos)                 /*!< 0x00020000 */
10816 #define ETH_MACSPI1R_SPI1_18                (0x40000U << ETH_MACSPI1R_SPI1_Pos)                 /*!< 0x00040000 */
10817 #define ETH_MACSPI1R_SPI1_19                (0x80000U << ETH_MACSPI1R_SPI1_Pos)                 /*!< 0x00080000 */
10818 #define ETH_MACSPI1R_SPI1_20                (0x100000U << ETH_MACSPI1R_SPI1_Pos)                /*!< 0x00100000 */
10819 #define ETH_MACSPI1R_SPI1_21                (0x200000U << ETH_MACSPI1R_SPI1_Pos)                /*!< 0x00200000 */
10820 #define ETH_MACSPI1R_SPI1_22                (0x400000U << ETH_MACSPI1R_SPI1_Pos)                /*!< 0x00400000 */
10821 #define ETH_MACSPI1R_SPI1_23                (0x800000U << ETH_MACSPI1R_SPI1_Pos)                /*!< 0x00800000 */
10822 #define ETH_MACSPI1R_SPI1_24                (0x1000000U << ETH_MACSPI1R_SPI1_Pos)               /*!< 0x01000000 */
10823 #define ETH_MACSPI1R_SPI1_25                (0x2000000U << ETH_MACSPI1R_SPI1_Pos)               /*!< 0x02000000 */
10824 #define ETH_MACSPI1R_SPI1_26                (0x4000000U << ETH_MACSPI1R_SPI1_Pos)               /*!< 0x04000000 */
10825 #define ETH_MACSPI1R_SPI1_27                (0x8000000U << ETH_MACSPI1R_SPI1_Pos)               /*!< 0x08000000 */
10826 #define ETH_MACSPI1R_SPI1_28                (0x10000000U << ETH_MACSPI1R_SPI1_Pos)              /*!< 0x10000000 */
10827 #define ETH_MACSPI1R_SPI1_29                (0x20000000U << ETH_MACSPI1R_SPI1_Pos)              /*!< 0x20000000 */
10828 #define ETH_MACSPI1R_SPI1_30                (0x40000000U << ETH_MACSPI1R_SPI1_Pos)              /*!< 0x40000000 */
10829 #define ETH_MACSPI1R_SPI1_31                (0x80000000U << ETH_MACSPI1R_SPI1_Pos)              /*!< 0x80000000 */
10830 
10831 /*************  Bit definition for ETH_MACSPI2R register  **************/
10832 #define ETH_MACSPI2R_SPI2_Pos               (0U)
10833 #define ETH_MACSPI2R_SPI2_Msk               (0xFFFFU << ETH_MACSPI2R_SPI2_Pos)                  /*!< 0x0000FFFF */
10834 #define ETH_MACSPI2R_SPI2                   ETH_MACSPI2R_SPI2_Msk                               /*!< Source Port Identity 2 */
10835 #define ETH_MACSPI2R_SPI2_0                 (0x1U << ETH_MACSPI2R_SPI2_Pos)                     /*!< 0x00000001 */
10836 #define ETH_MACSPI2R_SPI2_1                 (0x2U << ETH_MACSPI2R_SPI2_Pos)                     /*!< 0x00000002 */
10837 #define ETH_MACSPI2R_SPI2_2                 (0x4U << ETH_MACSPI2R_SPI2_Pos)                     /*!< 0x00000004 */
10838 #define ETH_MACSPI2R_SPI2_3                 (0x8U << ETH_MACSPI2R_SPI2_Pos)                     /*!< 0x00000008 */
10839 #define ETH_MACSPI2R_SPI2_4                 (0x10U << ETH_MACSPI2R_SPI2_Pos)                    /*!< 0x00000010 */
10840 #define ETH_MACSPI2R_SPI2_5                 (0x20U << ETH_MACSPI2R_SPI2_Pos)                    /*!< 0x00000020 */
10841 #define ETH_MACSPI2R_SPI2_6                 (0x40U << ETH_MACSPI2R_SPI2_Pos)                    /*!< 0x00000040 */
10842 #define ETH_MACSPI2R_SPI2_7                 (0x80U << ETH_MACSPI2R_SPI2_Pos)                    /*!< 0x00000080 */
10843 #define ETH_MACSPI2R_SPI2_8                 (0x100U << ETH_MACSPI2R_SPI2_Pos)                   /*!< 0x00000100 */
10844 #define ETH_MACSPI2R_SPI2_9                 (0x200U << ETH_MACSPI2R_SPI2_Pos)                   /*!< 0x00000200 */
10845 #define ETH_MACSPI2R_SPI2_10                (0x400U << ETH_MACSPI2R_SPI2_Pos)                   /*!< 0x00000400 */
10846 #define ETH_MACSPI2R_SPI2_11                (0x800U << ETH_MACSPI2R_SPI2_Pos)                   /*!< 0x00000800 */
10847 #define ETH_MACSPI2R_SPI2_12                (0x1000U << ETH_MACSPI2R_SPI2_Pos)                  /*!< 0x00001000 */
10848 #define ETH_MACSPI2R_SPI2_13                (0x2000U << ETH_MACSPI2R_SPI2_Pos)                  /*!< 0x00002000 */
10849 #define ETH_MACSPI2R_SPI2_14                (0x4000U << ETH_MACSPI2R_SPI2_Pos)                  /*!< 0x00004000 */
10850 #define ETH_MACSPI2R_SPI2_15                (0x8000U << ETH_MACSPI2R_SPI2_Pos)                  /*!< 0x00008000 */
10851 
10852 /**************  Bit definition for ETH_MACLMIR register  **************/
10853 #define ETH_MACLMIR_LSI_Pos                 (0U)
10854 #define ETH_MACLMIR_LSI_Msk                 (0xFFU << ETH_MACLMIR_LSI_Pos)                      /*!< 0x000000FF */
10855 #define ETH_MACLMIR_LSI                     ETH_MACLMIR_LSI_Msk                                 /*!< Log Sync Interval */
10856 #define ETH_MACLMIR_LSI_0                   (0x1U << ETH_MACLMIR_LSI_Pos)                       /*!< 0x00000001 */
10857 #define ETH_MACLMIR_LSI_1                   (0x2U << ETH_MACLMIR_LSI_Pos)                       /*!< 0x00000002 */
10858 #define ETH_MACLMIR_LSI_2                   (0x4U << ETH_MACLMIR_LSI_Pos)                       /*!< 0x00000004 */
10859 #define ETH_MACLMIR_LSI_3                   (0x8U << ETH_MACLMIR_LSI_Pos)                       /*!< 0x00000008 */
10860 #define ETH_MACLMIR_LSI_4                   (0x10U << ETH_MACLMIR_LSI_Pos)                      /*!< 0x00000010 */
10861 #define ETH_MACLMIR_LSI_5                   (0x20U << ETH_MACLMIR_LSI_Pos)                      /*!< 0x00000020 */
10862 #define ETH_MACLMIR_LSI_6                   (0x40U << ETH_MACLMIR_LSI_Pos)                      /*!< 0x00000040 */
10863 #define ETH_MACLMIR_LSI_7                   (0x80U << ETH_MACLMIR_LSI_Pos)                      /*!< 0x00000080 */
10864 #define ETH_MACLMIR_DRSYNCR_Pos             (8U)
10865 #define ETH_MACLMIR_DRSYNCR_Msk             (0x7U << ETH_MACLMIR_DRSYNCR_Pos)                   /*!< 0x00000700 */
10866 #define ETH_MACLMIR_DRSYNCR                 ETH_MACLMIR_DRSYNCR_Msk                             /*!< Delay_Req to SYNC Ratio */
10867 #define ETH_MACLMIR_DRSYNCR_0               (0x1U << ETH_MACLMIR_DRSYNCR_Pos)                 /*!< 0x00000100 */
10868 #define ETH_MACLMIR_DRSYNCR_1               (0x2U << ETH_MACLMIR_DRSYNCR_Pos)                 /*!< 0x00000200 */
10869 #define ETH_MACLMIR_DRSYNCR_2               (0x4U << ETH_MACLMIR_DRSYNCR_Pos)                 /*!< 0x00000400 */
10870 #define ETH_MACLMIR_LMPDRI_Pos              (24U)
10871 #define ETH_MACLMIR_LMPDRI_Msk              (0xFFU << ETH_MACLMIR_LMPDRI_Pos)                   /*!< 0xFF000000 */
10872 #define ETH_MACLMIR_LMPDRI                  ETH_MACLMIR_LMPDRI_Msk                              /*!< Log Min Pdelay_Req Interval */
10873 #define ETH_MACLMIR_LMPDRI_0                (0x1U << ETH_MACLMIR_LMPDRI_Pos)              /*!< 0x01000000 */
10874 #define ETH_MACLMIR_LMPDRI_1                (0x2U << ETH_MACLMIR_LMPDRI_Pos)              /*!< 0x02000000 */
10875 #define ETH_MACLMIR_LMPDRI_2                (0x4U << ETH_MACLMIR_LMPDRI_Pos)              /*!< 0x04000000 */
10876 #define ETH_MACLMIR_LMPDRI_3                (0x8U << ETH_MACLMIR_LMPDRI_Pos)              /*!< 0x08000000 */
10877 #define ETH_MACLMIR_LMPDRI_4                (0x10U << ETH_MACLMIR_LMPDRI_Pos)             /*!< 0x10000000 */
10878 #define ETH_MACLMIR_LMPDRI_5                (0x20U << ETH_MACLMIR_LMPDRI_Pos)             /*!< 0x20000000 */
10879 #define ETH_MACLMIR_LMPDRI_6                (0x40U << ETH_MACLMIR_LMPDRI_Pos)             /*!< 0x40000000 */
10880 #define ETH_MACLMIR_LMPDRI_7                (0x80U << ETH_MACLMIR_LMPDRI_Pos)             /*!< 0x80000000 */
10881 
10882 /**************  Bit definition for ETH_MTLOMR register  ***************/
10883 #define ETH_MTLOMR_DTXSTS_Pos               (1U)
10884 #define ETH_MTLOMR_DTXSTS_Msk               (0x1U << ETH_MTLOMR_DTXSTS_Pos)                     /*!< 0x00000002 */
10885 #define ETH_MTLOMR_DTXSTS                   ETH_MTLOMR_DTXSTS_Msk                               /*!< Drop Transmit Status */
10886 #define ETH_MTLOMR_RAA_Pos                  (2U)
10887 #define ETH_MTLOMR_RAA_Msk                  (0x1U << ETH_MTLOMR_RAA_Pos)                        /*!< 0x00000004 */
10888 #define ETH_MTLOMR_RAA                      ETH_MTLOMR_RAA_Msk                                  /*!< Receive Arbitration Algorithm */
10889 #define ETH_MTLOMR_SCHALG_Pos               (5U)
10890 #define ETH_MTLOMR_SCHALG_Msk               (0x3U << ETH_MTLOMR_SCHALG_Pos)                     /*!< 0x00000060 */
10891 #define ETH_MTLOMR_SCHALG                   ETH_MTLOMR_SCHALG_Msk                               /*!< Tx Scheduling Algorithm */
10892 #define ETH_MTLOMR_SCHALG_0                 (0x1U << ETH_MTLOMR_SCHALG_Pos)                    /*!< 0x00000020 */
10893 #define ETH_MTLOMR_SCHALG_1                 (0x2U << ETH_MTLOMR_SCHALG_Pos)                    /*!< 0x00000040 */
10894 #define ETH_MTLOMR_CNTPRST_Pos              (8U)
10895 #define ETH_MTLOMR_CNTPRST_Msk              (0x1U << ETH_MTLOMR_CNTPRST_Pos)                    /*!< 0x00000100 */
10896 #define ETH_MTLOMR_CNTPRST                  ETH_MTLOMR_CNTPRST_Msk                              /*!< Counters Preset */
10897 #define ETH_MTLOMR_CNTCLR_Pos               (9U)
10898 #define ETH_MTLOMR_CNTCLR_Msk               (0x1U << ETH_MTLOMR_CNTCLR_Pos)                     /*!< 0x00000200 */
10899 #define ETH_MTLOMR_CNTCLR                   ETH_MTLOMR_CNTCLR_Msk                               /*!< Counters Reset */
10900 
10901 /**************  Bit definition for ETH_MTLISR register  ***************/
10902 #define ETH_MTLISR_Q0IS_Pos                 (0U)
10903 #define ETH_MTLISR_Q0IS_Msk                 (0x1U << ETH_MTLISR_Q0IS_Pos)                       /*!< 0x00000001 */
10904 #define ETH_MTLISR_Q0IS                     ETH_MTLISR_Q0IS_Msk                                 /*!< Queue 0 interrupt status */
10905 #define ETH_MTLISR_Q1IS_Pos                 (1U)
10906 #define ETH_MTLISR_Q1IS_Msk                 (0x1U << ETH_MTLISR_Q1IS_Pos)                       /*!< 0x00000002 */
10907 #define ETH_MTLISR_Q1IS                     ETH_MTLISR_Q1IS_Msk                                 /*!< Queue 1 interrupt status */
10908 
10909 /************  Bit definition for ETH_MTLTXQ0OMR register  *************/
10910 #define ETH_MTLTXQ0OMR_FTQ_Pos              (0U)
10911 #define ETH_MTLTXQ0OMR_FTQ_Msk              (0x1U << ETH_MTLTXQ0OMR_FTQ_Pos)                    /*!< 0x00000001 */
10912 #define ETH_MTLTXQ0OMR_FTQ                  ETH_MTLTXQ0OMR_FTQ_Msk                              /*!< Flush Transmit Queue */
10913 #define ETH_MTLTXQ0OMR_TSF_Pos              (1U)
10914 #define ETH_MTLTXQ0OMR_TSF_Msk              (0x1U << ETH_MTLTXQ0OMR_TSF_Pos)                    /*!< 0x00000002 */
10915 #define ETH_MTLTXQ0OMR_TSF                  ETH_MTLTXQ0OMR_TSF_Msk                              /*!< Transmit Store and Forward */
10916 #define ETH_MTLTXQ0OMR_TXQEN_Pos            (2U)
10917 #define ETH_MTLTXQ0OMR_TXQEN_Msk            (0x3U << ETH_MTLTXQ0OMR_TXQEN_Pos)                  /*!< 0x0000000C */
10918 #define ETH_MTLTXQ0OMR_TXQEN                ETH_MTLTXQ0OMR_TXQEN_Msk                            /*!< Transmit Queue Enable */
10919 #define ETH_MTLTXQ0OMR_TXQEN_0              (0x1U << ETH_MTLTXQ0OMR_TXQEN_Pos)                  /*!< 0x00000004 */
10920 #define ETH_MTLTXQ0OMR_TXQEN_1              (0x2U << ETH_MTLTXQ0OMR_TXQEN_Pos)                  /*!< 0x00000008 */
10921 #define ETH_MTLTXQ0OMR_TTC_Pos              (4U)
10922 #define ETH_MTLTXQ0OMR_TTC_Msk              (0x7U << ETH_MTLTXQ0OMR_TTC_Pos)                    /*!< 0x00000070 */
10923 #define ETH_MTLTXQ0OMR_TTC                  ETH_MTLTXQ0OMR_TTC_Msk                              /*!< Transmit Threshold Control */
10924 #define ETH_MTLTXQ0OMR_TTC_0                (0x1U << ETH_MTLTXQ0OMR_TTC_Pos)                   /*!< 0x00000010 */
10925 #define ETH_MTLTXQ0OMR_TTC_1                (0x2U << ETH_MTLTXQ0OMR_TTC_Pos)                   /*!< 0x00000020 */
10926 #define ETH_MTLTXQ0OMR_TTC_2                (0x4U << ETH_MTLTXQ0OMR_TTC_Pos)                   /*!< 0x00000040 */
10927 #define ETH_MTLTXQ0OMR_TQS_Pos              (16U)
10928 #define ETH_MTLTXQ0OMR_TQS_Msk              (0x1FFU << ETH_MTLTXQ0OMR_TQS_Pos)                  /*!< 0x01FF0000 */
10929 #define ETH_MTLTXQ0OMR_TQS                  ETH_MTLTXQ0OMR_TQS_Msk                              /*!< Transmit Queue Size */
10930 #define ETH_MTLTXQ0OMR_TQS_0                (0x1U << ETH_MTLTXQ0OMR_TQS_Pos)                /*!< 0x00010000 */
10931 #define ETH_MTLTXQ0OMR_TQS_1                (0x2U << ETH_MTLTXQ0OMR_TQS_Pos)                /*!< 0x00020000 */
10932 #define ETH_MTLTXQ0OMR_TQS_2                (0x4U << ETH_MTLTXQ0OMR_TQS_Pos)                /*!< 0x00040000 */
10933 #define ETH_MTLTXQ0OMR_TQS_3                (0x8U << ETH_MTLTXQ0OMR_TQS_Pos)                /*!< 0x00080000 */
10934 #define ETH_MTLTXQ0OMR_TQS_4                (0x10U << ETH_MTLTXQ0OMR_TQS_Pos)               /*!< 0x00100000 */
10935 #define ETH_MTLTXQ0OMR_TQS_5                (0x20U << ETH_MTLTXQ0OMR_TQS_Pos)               /*!< 0x00200000 */
10936 #define ETH_MTLTXQ0OMR_TQS_6                (0x40U << ETH_MTLTXQ0OMR_TQS_Pos)               /*!< 0x00400000 */
10937 #define ETH_MTLTXQ0OMR_TQS_7                (0x80U << ETH_MTLTXQ0OMR_TQS_Pos)               /*!< 0x00800000 */
10938 #define ETH_MTLTXQ0OMR_TQS_8                (0x100U << ETH_MTLTXQ0OMR_TQS_Pos)              /*!< 0x01000000 */
10939 
10940 /*************  Bit definition for ETH_MTLTXQ0UR register  *************/
10941 #define ETH_MTLTXQ0UR_UFFRMCNT_Pos          (0U)
10942 #define ETH_MTLTXQ0UR_UFFRMCNT_Msk          (0x7FFU << ETH_MTLTXQ0UR_UFFRMCNT_Pos)              /*!< 0x000007FF */
10943 #define ETH_MTLTXQ0UR_UFFRMCNT              ETH_MTLTXQ0UR_UFFRMCNT_Msk                          /*!< Underflow Packet Counter */
10944 #define ETH_MTLTXQ0UR_UFFRMCNT_0            (0x1U << ETH_MTLTXQ0UR_UFFRMCNT_Pos)                /*!< 0x00000001 */
10945 #define ETH_MTLTXQ0UR_UFFRMCNT_1            (0x2U << ETH_MTLTXQ0UR_UFFRMCNT_Pos)                /*!< 0x00000002 */
10946 #define ETH_MTLTXQ0UR_UFFRMCNT_2            (0x4U << ETH_MTLTXQ0UR_UFFRMCNT_Pos)                /*!< 0x00000004 */
10947 #define ETH_MTLTXQ0UR_UFFRMCNT_3            (0x8U << ETH_MTLTXQ0UR_UFFRMCNT_Pos)                /*!< 0x00000008 */
10948 #define ETH_MTLTXQ0UR_UFFRMCNT_4            (0x10U << ETH_MTLTXQ0UR_UFFRMCNT_Pos)               /*!< 0x00000010 */
10949 #define ETH_MTLTXQ0UR_UFFRMCNT_5            (0x20U << ETH_MTLTXQ0UR_UFFRMCNT_Pos)               /*!< 0x00000020 */
10950 #define ETH_MTLTXQ0UR_UFFRMCNT_6            (0x40U << ETH_MTLTXQ0UR_UFFRMCNT_Pos)               /*!< 0x00000040 */
10951 #define ETH_MTLTXQ0UR_UFFRMCNT_7            (0x80U << ETH_MTLTXQ0UR_UFFRMCNT_Pos)               /*!< 0x00000080 */
10952 #define ETH_MTLTXQ0UR_UFFRMCNT_8            (0x100U << ETH_MTLTXQ0UR_UFFRMCNT_Pos)              /*!< 0x00000100 */
10953 #define ETH_MTLTXQ0UR_UFFRMCNT_9            (0x200U << ETH_MTLTXQ0UR_UFFRMCNT_Pos)              /*!< 0x00000200 */
10954 #define ETH_MTLTXQ0UR_UFFRMCNT_10           (0x400U << ETH_MTLTXQ0UR_UFFRMCNT_Pos)              /*!< 0x00000400 */
10955 #define ETH_MTLTXQ0UR_UFCNTOVF_Pos          (11U)
10956 #define ETH_MTLTXQ0UR_UFCNTOVF_Msk          (0x1U << ETH_MTLTXQ0UR_UFCNTOVF_Pos)                /*!< 0x00000800 */
10957 #define ETH_MTLTXQ0UR_UFCNTOVF              ETH_MTLTXQ0UR_UFCNTOVF_Msk                          /*!< Overflow Bit for Underflow Packet Counter */
10958 
10959 /*************  Bit definition for ETH_MTLTXQ0DR register  *************/
10960 #define ETH_MTLTXQ0DR_TXQPAUSED_Pos         (0U)
10961 #define ETH_MTLTXQ0DR_TXQPAUSED_Msk         (0x1U << ETH_MTLTXQ0DR_TXQPAUSED_Pos)               /*!< 0x00000001 */
10962 #define ETH_MTLTXQ0DR_TXQPAUSED             ETH_MTLTXQ0DR_TXQPAUSED_Msk                         /*!< Transmit Queue in Pause */
10963 #define ETH_MTLTXQ0DR_TRCSTS_Pos            (1U)
10964 #define ETH_MTLTXQ0DR_TRCSTS_Msk            (0x3U << ETH_MTLTXQ0DR_TRCSTS_Pos)                  /*!< 0x00000006 */
10965 #define ETH_MTLTXQ0DR_TRCSTS                ETH_MTLTXQ0DR_TRCSTS_Msk                            /*!< MTL Tx Queue Read Controller Status */
10966 #define ETH_MTLTXQ0DR_TRCSTS_0              (0x1U << ETH_MTLTXQ0DR_TRCSTS_Pos)                  /*!< 0x00000002 */
10967 #define ETH_MTLTXQ0DR_TRCSTS_1              (0x2U << ETH_MTLTXQ0DR_TRCSTS_Pos)                  /*!< 0x00000004 */
10968 #define ETH_MTLTXQ0DR_TWCSTS_Pos            (3U)
10969 #define ETH_MTLTXQ0DR_TWCSTS_Msk            (0x1U << ETH_MTLTXQ0DR_TWCSTS_Pos)                  /*!< 0x00000008 */
10970 #define ETH_MTLTXQ0DR_TWCSTS                ETH_MTLTXQ0DR_TWCSTS_Msk                            /*!< MTL Tx Queue Write Controller Status */
10971 #define ETH_MTLTXQ0DR_TXQSTS_Pos            (4U)
10972 #define ETH_MTLTXQ0DR_TXQSTS_Msk            (0x1U << ETH_MTLTXQ0DR_TXQSTS_Pos)                  /*!< 0x00000010 */
10973 #define ETH_MTLTXQ0DR_TXQSTS                ETH_MTLTXQ0DR_TXQSTS_Msk                            /*!< MTL Tx Queue Not Empty Status */
10974 #define ETH_MTLTXQ0DR_TXSTSFSTS_Pos         (5U)
10975 #define ETH_MTLTXQ0DR_TXSTSFSTS_Msk         (0x1U << ETH_MTLTXQ0DR_TXSTSFSTS_Pos)               /*!< 0x00000020 */
10976 #define ETH_MTLTXQ0DR_TXSTSFSTS             ETH_MTLTXQ0DR_TXSTSFSTS_Msk                         /*!< MTL Tx Status FIFO Full Status */
10977 #define ETH_MTLTXQ0DR_PTXQ_Pos              (16U)
10978 #define ETH_MTLTXQ0DR_PTXQ_Msk              (0x7U << ETH_MTLTXQ0DR_PTXQ_Pos)                    /*!< 0x00070000 */
10979 #define ETH_MTLTXQ0DR_PTXQ                  ETH_MTLTXQ0DR_PTXQ_Msk                              /*!< Number of Packets in the Transmit Queue */
10980 #define ETH_MTLTXQ0DR_PTXQ_0                (0x1U << ETH_MTLTXQ0DR_PTXQ_Pos)                /*!< 0x00010000 */
10981 #define ETH_MTLTXQ0DR_PTXQ_1                (0x2U << ETH_MTLTXQ0DR_PTXQ_Pos)                /*!< 0x00020000 */
10982 #define ETH_MTLTXQ0DR_PTXQ_2                (0x4U << ETH_MTLTXQ0DR_PTXQ_Pos)                /*!< 0x00040000 */
10983 #define ETH_MTLTXQ0DR_STXSTSF_Pos           (20U)
10984 #define ETH_MTLTXQ0DR_STXSTSF_Msk           (0x7U << ETH_MTLTXQ0DR_STXSTSF_Pos)                 /*!< 0x00700000 */
10985 #define ETH_MTLTXQ0DR_STXSTSF               ETH_MTLTXQ0DR_STXSTSF_Msk                           /*!< Number of Status Words in Tx Status FIFO of Queue */
10986 #define ETH_MTLTXQ0DR_STXSTSF_0             (0x1U << ETH_MTLTXQ0DR_STXSTSF_Pos)            /*!< 0x00100000 */
10987 #define ETH_MTLTXQ0DR_STXSTSF_1             (0x2U << ETH_MTLTXQ0DR_STXSTSF_Pos)            /*!< 0x00200000 */
10988 #define ETH_MTLTXQ0DR_STXSTSF_2             (0x4U << ETH_MTLTXQ0DR_STXSTSF_Pos)            /*!< 0x00400000 */
10989 
10990 /************  Bit definition for ETH_MTLTXQ0ESR register  *************/
10991 #define ETH_MTLTXQ0ESR_ABS_Pos              (0U)
10992 #define ETH_MTLTXQ0ESR_ABS_Msk              (0xFFFFFFU << ETH_MTLTXQ0ESR_ABS_Pos)               /*!< 0x00FFFFFF */
10993 #define ETH_MTLTXQ0ESR_ABS                  ETH_MTLTXQ0ESR_ABS_Msk                              /*!< Average Bits per Slot */
10994 #define ETH_MTLTXQ0ESR_ABS_0                (0x1U << ETH_MTLTXQ0ESR_ABS_Pos)                    /*!< 0x00000001 */
10995 #define ETH_MTLTXQ0ESR_ABS_1                (0x2U << ETH_MTLTXQ0ESR_ABS_Pos)                    /*!< 0x00000002 */
10996 #define ETH_MTLTXQ0ESR_ABS_2                (0x4U << ETH_MTLTXQ0ESR_ABS_Pos)                    /*!< 0x00000004 */
10997 #define ETH_MTLTXQ0ESR_ABS_3                (0x8U << ETH_MTLTXQ0ESR_ABS_Pos)                    /*!< 0x00000008 */
10998 #define ETH_MTLTXQ0ESR_ABS_4                (0x10U << ETH_MTLTXQ0ESR_ABS_Pos)                   /*!< 0x00000010 */
10999 #define ETH_MTLTXQ0ESR_ABS_5                (0x20U << ETH_MTLTXQ0ESR_ABS_Pos)                   /*!< 0x00000020 */
11000 #define ETH_MTLTXQ0ESR_ABS_6                (0x40U << ETH_MTLTXQ0ESR_ABS_Pos)                   /*!< 0x00000040 */
11001 #define ETH_MTLTXQ0ESR_ABS_7                (0x80U << ETH_MTLTXQ0ESR_ABS_Pos)                   /*!< 0x00000080 */
11002 #define ETH_MTLTXQ0ESR_ABS_8                (0x100U << ETH_MTLTXQ0ESR_ABS_Pos)                  /*!< 0x00000100 */
11003 #define ETH_MTLTXQ0ESR_ABS_9                (0x200U << ETH_MTLTXQ0ESR_ABS_Pos)                  /*!< 0x00000200 */
11004 #define ETH_MTLTXQ0ESR_ABS_10               (0x400U << ETH_MTLTXQ0ESR_ABS_Pos)                  /*!< 0x00000400 */
11005 #define ETH_MTLTXQ0ESR_ABS_11               (0x800U << ETH_MTLTXQ0ESR_ABS_Pos)                  /*!< 0x00000800 */
11006 #define ETH_MTLTXQ0ESR_ABS_12               (0x1000U << ETH_MTLTXQ0ESR_ABS_Pos)                 /*!< 0x00001000 */
11007 #define ETH_MTLTXQ0ESR_ABS_13               (0x2000U << ETH_MTLTXQ0ESR_ABS_Pos)                 /*!< 0x00002000 */
11008 #define ETH_MTLTXQ0ESR_ABS_14               (0x4000U << ETH_MTLTXQ0ESR_ABS_Pos)                 /*!< 0x00004000 */
11009 #define ETH_MTLTXQ0ESR_ABS_15               (0x8000U << ETH_MTLTXQ0ESR_ABS_Pos)                 /*!< 0x00008000 */
11010 #define ETH_MTLTXQ0ESR_ABS_16               (0x10000U << ETH_MTLTXQ0ESR_ABS_Pos)                /*!< 0x00010000 */
11011 #define ETH_MTLTXQ0ESR_ABS_17               (0x20000U << ETH_MTLTXQ0ESR_ABS_Pos)                /*!< 0x00020000 */
11012 #define ETH_MTLTXQ0ESR_ABS_18               (0x40000U << ETH_MTLTXQ0ESR_ABS_Pos)                /*!< 0x00040000 */
11013 #define ETH_MTLTXQ0ESR_ABS_19               (0x80000U << ETH_MTLTXQ0ESR_ABS_Pos)                /*!< 0x00080000 */
11014 #define ETH_MTLTXQ0ESR_ABS_20               (0x100000U << ETH_MTLTXQ0ESR_ABS_Pos)               /*!< 0x00100000 */
11015 #define ETH_MTLTXQ0ESR_ABS_21               (0x200000U << ETH_MTLTXQ0ESR_ABS_Pos)               /*!< 0x00200000 */
11016 #define ETH_MTLTXQ0ESR_ABS_22               (0x400000U << ETH_MTLTXQ0ESR_ABS_Pos)               /*!< 0x00400000 */
11017 #define ETH_MTLTXQ0ESR_ABS_23               (0x800000U << ETH_MTLTXQ0ESR_ABS_Pos)               /*!< 0x00800000 */
11018 
11019 /*************  Bit definition for ETH_MTLQ0ICSR register  *************/
11020 #define ETH_MTLQ0ICSR_TXUNFIS_Pos           (0U)
11021 #define ETH_MTLQ0ICSR_TXUNFIS_Msk           (0x1U << ETH_MTLQ0ICSR_TXUNFIS_Pos)                 /*!< 0x00000001 */
11022 #define ETH_MTLQ0ICSR_TXUNFIS               ETH_MTLQ0ICSR_TXUNFIS_Msk                           /*!< Transmit Queue Underflow Interrupt Status */
11023 #define ETH_MTLQ0ICSR_ABPSIS_Pos            (1U)
11024 #define ETH_MTLQ0ICSR_ABPSIS_Msk            (0x1U << ETH_MTLQ0ICSR_ABPSIS_Pos)                  /*!< 0x00000002 */
11025 #define ETH_MTLQ0ICSR_ABPSIS                ETH_MTLQ0ICSR_ABPSIS_Msk                            /*!< Average Bits Per Slot Interrupt Status */
11026 #define ETH_MTLQ0ICSR_TXUIE_Pos             (8U)
11027 #define ETH_MTLQ0ICSR_TXUIE_Msk             (0x1U << ETH_MTLQ0ICSR_TXUIE_Pos)                   /*!< 0x00000100 */
11028 #define ETH_MTLQ0ICSR_TXUIE                 ETH_MTLQ0ICSR_TXUIE_Msk                             /*!< Transmit Queue Underflow Interrupt Enable */
11029 #define ETH_MTLQ0ICSR_ABPSIE_Pos            (9U)
11030 #define ETH_MTLQ0ICSR_ABPSIE_Msk            (0x1U << ETH_MTLQ0ICSR_ABPSIE_Pos)                  /*!< 0x00000200 */
11031 #define ETH_MTLQ0ICSR_ABPSIE                ETH_MTLQ0ICSR_ABPSIE_Msk                            /*!< Average Bits Per Slot Interrupt Enable */
11032 #define ETH_MTLQ0ICSR_RXOVFIS_Pos           (16U)
11033 #define ETH_MTLQ0ICSR_RXOVFIS_Msk           (0x1U << ETH_MTLQ0ICSR_RXOVFIS_Pos)                 /*!< 0x00010000 */
11034 #define ETH_MTLQ0ICSR_RXOVFIS               ETH_MTLQ0ICSR_RXOVFIS_Msk                           /*!< Receive Queue Overflow Interrupt Status */
11035 #define ETH_MTLQ0ICSR_RXOIE_Pos             (24U)
11036 #define ETH_MTLQ0ICSR_RXOIE_Msk             (0x1U << ETH_MTLQ0ICSR_RXOIE_Pos)                   /*!< 0x01000000 */
11037 #define ETH_MTLQ0ICSR_RXOIE                 ETH_MTLQ0ICSR_RXOIE_Msk                             /*!< Receive Queue Overflow Interrupt Enable */
11038 
11039 /************  Bit definition for ETH_MTLRXQ0OMR register  *************/
11040 #define ETH_MTLRXQ0OMR_RTC_Pos              (0U)
11041 #define ETH_MTLRXQ0OMR_RTC_Msk              (0x3U << ETH_MTLRXQ0OMR_RTC_Pos)                    /*!< 0x00000003 */
11042 #define ETH_MTLRXQ0OMR_RTC                  ETH_MTLRXQ0OMR_RTC_Msk                              /*!< Receive Queue Threshold Control */
11043 #define ETH_MTLRXQ0OMR_RTC_0                (0x1U << ETH_MTLRXQ0OMR_RTC_Pos)                    /*!< 0x00000001 */
11044 #define ETH_MTLRXQ0OMR_RTC_1                (0x2U << ETH_MTLRXQ0OMR_RTC_Pos)                    /*!< 0x00000002 */
11045 #define ETH_MTLRXQ0OMR_FUP_Pos              (3U)
11046 #define ETH_MTLRXQ0OMR_FUP_Msk              (0x1U << ETH_MTLRXQ0OMR_FUP_Pos)                    /*!< 0x00000008 */
11047 #define ETH_MTLRXQ0OMR_FUP                  ETH_MTLRXQ0OMR_FUP_Msk                              /*!< Forward Undersized Good Packets */
11048 #define ETH_MTLRXQ0OMR_FEP_Pos              (4U)
11049 #define ETH_MTLRXQ0OMR_FEP_Msk              (0x1U << ETH_MTLRXQ0OMR_FEP_Pos)                    /*!< 0x00000010 */
11050 #define ETH_MTLRXQ0OMR_FEP                  ETH_MTLRXQ0OMR_FEP_Msk                              /*!< Forward Error Packets */
11051 #define ETH_MTLRXQ0OMR_RSF_Pos              (5U)
11052 #define ETH_MTLRXQ0OMR_RSF_Msk              (0x1U << ETH_MTLRXQ0OMR_RSF_Pos)                    /*!< 0x00000020 */
11053 #define ETH_MTLRXQ0OMR_RSF                  ETH_MTLRXQ0OMR_RSF_Msk                              /*!< Receive Queue Store and Forward */
11054 #define ETH_MTLRXQ0OMR_DIS_TCP_EF_Pos       (6U)
11055 #define ETH_MTLRXQ0OMR_DIS_TCP_EF_Msk       (0x1U << ETH_MTLRXQ0OMR_DIS_TCP_EF_Pos)             /*!< 0x00000040 */
11056 #define ETH_MTLRXQ0OMR_DIS_TCP_EF           ETH_MTLRXQ0OMR_DIS_TCP_EF_Msk                       /*!< Disable Dropping of TCP/IP Checksum Error Packets */
11057 #define ETH_MTLRXQ0OMR_EHFC_Pos             (7U)
11058 #define ETH_MTLRXQ0OMR_EHFC_Msk             (0x1U << ETH_MTLRXQ0OMR_EHFC_Pos)                   /*!< 0x00000080 */
11059 #define ETH_MTLRXQ0OMR_EHFC                 ETH_MTLRXQ0OMR_EHFC_Msk                             /*!< Enable Hardware Flow Control */
11060 #define ETH_MTLRXQ0OMR_RFA_Pos              (8U)
11061 #define ETH_MTLRXQ0OMR_RFA_Msk              (0x7U << ETH_MTLRXQ0OMR_RFA_Pos)                    /*!< 0x00000700 */
11062 #define ETH_MTLRXQ0OMR_RFA                  ETH_MTLRXQ0OMR_RFA_Msk                              /*!< Threshold for Activating Flow Control (in half-duplex and full-duplex */
11063 #define ETH_MTLRXQ0OMR_RFA_0                (0x1U << ETH_MTLRXQ0OMR_RFA_Pos)                  /*!< 0x00000100 */
11064 #define ETH_MTLRXQ0OMR_RFA_1                (0x2U << ETH_MTLRXQ0OMR_RFA_Pos)                  /*!< 0x00000200 */
11065 #define ETH_MTLRXQ0OMR_RFA_2                (0x4U << ETH_MTLRXQ0OMR_RFA_Pos)                  /*!< 0x00000400 */
11066 #define ETH_MTLRXQ0OMR_RFD_Pos              (14U)
11067 #define ETH_MTLRXQ0OMR_RFD_Msk              (0x7U << ETH_MTLRXQ0OMR_RFD_Pos)                    /*!< 0x0001C000 */
11068 #define ETH_MTLRXQ0OMR_RFD                  ETH_MTLRXQ0OMR_RFD_Msk                              /*!< Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */
11069 #define ETH_MTLRXQ0OMR_RFD_0                (0x1U << ETH_MTLRXQ0OMR_RFD_Pos)                 /*!< 0x00004000 */
11070 #define ETH_MTLRXQ0OMR_RFD_1                (0x2U << ETH_MTLRXQ0OMR_RFD_Pos)                 /*!< 0x00008000 */
11071 #define ETH_MTLRXQ0OMR_RFD_2                (0x4U << ETH_MTLRXQ0OMR_RFD_Pos)                /*!< 0x00010000 */
11072 #define ETH_MTLRXQ0OMR_RQS_Pos              (20U)
11073 #define ETH_MTLRXQ0OMR_RQS_Msk              (0xFU << ETH_MTLRXQ0OMR_RQS_Pos)                    /*!< 0x00F00000 */
11074 #define ETH_MTLRXQ0OMR_RQS                  ETH_MTLRXQ0OMR_RQS_Msk                              /*!< Receive Queue Size */
11075 #define ETH_MTLRXQ0OMR_RQS_0                (0x1U << ETH_MTLRXQ0OMR_RQS_Pos)               /*!< 0x00100000 */
11076 #define ETH_MTLRXQ0OMR_RQS_1                (0x2U << ETH_MTLRXQ0OMR_RQS_Pos)               /*!< 0x00200000 */
11077 #define ETH_MTLRXQ0OMR_RQS_2                (0x4U << ETH_MTLRXQ0OMR_RQS_Pos)               /*!< 0x00400000 */
11078 #define ETH_MTLRXQ0OMR_RQS_3                (0x8U << ETH_MTLRXQ0OMR_RQS_Pos)               /*!< 0x00800000 */
11079 
11080 /***********  Bit definition for ETH_MTLRXQ0MPOCR register  ************/
11081 #define ETH_MTLRXQ0MPOCR_OVFPKTCNT_Pos      (0U)
11082 #define ETH_MTLRXQ0MPOCR_OVFPKTCNT_Msk      (0x7FFU << ETH_MTLRXQ0MPOCR_OVFPKTCNT_Pos)          /*!< 0x000007FF */
11083 #define ETH_MTLRXQ0MPOCR_OVFPKTCNT          ETH_MTLRXQ0MPOCR_OVFPKTCNT_Msk                      /*!< Overflow Packet Counter */
11084 #define ETH_MTLRXQ0MPOCR_OVFPKTCNT_0        (0x1U << ETH_MTLRXQ0MPOCR_OVFPKTCNT_Pos)            /*!< 0x00000001 */
11085 #define ETH_MTLRXQ0MPOCR_OVFPKTCNT_1        (0x2U << ETH_MTLRXQ0MPOCR_OVFPKTCNT_Pos)            /*!< 0x00000002 */
11086 #define ETH_MTLRXQ0MPOCR_OVFPKTCNT_2        (0x4U << ETH_MTLRXQ0MPOCR_OVFPKTCNT_Pos)            /*!< 0x00000004 */
11087 #define ETH_MTLRXQ0MPOCR_OVFPKTCNT_3        (0x8U << ETH_MTLRXQ0MPOCR_OVFPKTCNT_Pos)            /*!< 0x00000008 */
11088 #define ETH_MTLRXQ0MPOCR_OVFPKTCNT_4        (0x10U << ETH_MTLRXQ0MPOCR_OVFPKTCNT_Pos)           /*!< 0x00000010 */
11089 #define ETH_MTLRXQ0MPOCR_OVFPKTCNT_5        (0x20U << ETH_MTLRXQ0MPOCR_OVFPKTCNT_Pos)           /*!< 0x00000020 */
11090 #define ETH_MTLRXQ0MPOCR_OVFPKTCNT_6        (0x40U << ETH_MTLRXQ0MPOCR_OVFPKTCNT_Pos)           /*!< 0x00000040 */
11091 #define ETH_MTLRXQ0MPOCR_OVFPKTCNT_7        (0x80U << ETH_MTLRXQ0MPOCR_OVFPKTCNT_Pos)           /*!< 0x00000080 */
11092 #define ETH_MTLRXQ0MPOCR_OVFPKTCNT_8        (0x100U << ETH_MTLRXQ0MPOCR_OVFPKTCNT_Pos)          /*!< 0x00000100 */
11093 #define ETH_MTLRXQ0MPOCR_OVFPKTCNT_9        (0x200U << ETH_MTLRXQ0MPOCR_OVFPKTCNT_Pos)          /*!< 0x00000200 */
11094 #define ETH_MTLRXQ0MPOCR_OVFPKTCNT_10       (0x400U << ETH_MTLRXQ0MPOCR_OVFPKTCNT_Pos)          /*!< 0x00000400 */
11095 #define ETH_MTLRXQ0MPOCR_OVFCNTOVF_Pos      (11U)
11096 #define ETH_MTLRXQ0MPOCR_OVFCNTOVF_Msk      (0x1U << ETH_MTLRXQ0MPOCR_OVFCNTOVF_Pos)            /*!< 0x00000800 */
11097 #define ETH_MTLRXQ0MPOCR_OVFCNTOVF          ETH_MTLRXQ0MPOCR_OVFCNTOVF_Msk                      /*!< Overflow Counter Overflow Bit */
11098 #define ETH_MTLRXQ0MPOCR_MISPKTCNT_Pos      (16U)
11099 #define ETH_MTLRXQ0MPOCR_MISPKTCNT_Msk      (0x7FFU << ETH_MTLRXQ0MPOCR_MISPKTCNT_Pos)          /*!< 0x07FF0000 */
11100 #define ETH_MTLRXQ0MPOCR_MISPKTCNT          ETH_MTLRXQ0MPOCR_MISPKTCNT_Msk                      /*!< Missed Packet Counter */
11101 #define ETH_MTLRXQ0MPOCR_MISPKTCNT_0        (0x1U << ETH_MTLRXQ0MPOCR_MISPKTCNT_Pos)        /*!< 0x00010000 */
11102 #define ETH_MTLRXQ0MPOCR_MISPKTCNT_1        (0x2U << ETH_MTLRXQ0MPOCR_MISPKTCNT_Pos)        /*!< 0x00020000 */
11103 #define ETH_MTLRXQ0MPOCR_MISPKTCNT_2        (0x4U << ETH_MTLRXQ0MPOCR_MISPKTCNT_Pos)        /*!< 0x00040000 */
11104 #define ETH_MTLRXQ0MPOCR_MISPKTCNT_3        (0x8U << ETH_MTLRXQ0MPOCR_MISPKTCNT_Pos)        /*!< 0x00080000 */
11105 #define ETH_MTLRXQ0MPOCR_MISPKTCNT_4        (0x10U << ETH_MTLRXQ0MPOCR_MISPKTCNT_Pos)       /*!< 0x00100000 */
11106 #define ETH_MTLRXQ0MPOCR_MISPKTCNT_5        (0x20U << ETH_MTLRXQ0MPOCR_MISPKTCNT_Pos)       /*!< 0x00200000 */
11107 #define ETH_MTLRXQ0MPOCR_MISPKTCNT_6        (0x40U << ETH_MTLRXQ0MPOCR_MISPKTCNT_Pos)       /*!< 0x00400000 */
11108 #define ETH_MTLRXQ0MPOCR_MISPKTCNT_7        (0x80U << ETH_MTLRXQ0MPOCR_MISPKTCNT_Pos)       /*!< 0x00800000 */
11109 #define ETH_MTLRXQ0MPOCR_MISPKTCNT_8        (0x100U << ETH_MTLRXQ0MPOCR_MISPKTCNT_Pos)      /*!< 0x01000000 */
11110 #define ETH_MTLRXQ0MPOCR_MISPKTCNT_9        (0x200U << ETH_MTLRXQ0MPOCR_MISPKTCNT_Pos)      /*!< 0x02000000 */
11111 #define ETH_MTLRXQ0MPOCR_MISPKTCNT_10       (0x400U << ETH_MTLRXQ0MPOCR_MISPKTCNT_Pos)      /*!< 0x04000000 */
11112 #define ETH_MTLRXQ0MPOCR_MISCNTOVF_Pos      (27U)
11113 #define ETH_MTLRXQ0MPOCR_MISCNTOVF_Msk      (0x1U << ETH_MTLRXQ0MPOCR_MISCNTOVF_Pos)            /*!< 0x08000000 */
11114 #define ETH_MTLRXQ0MPOCR_MISCNTOVF          ETH_MTLRXQ0MPOCR_MISCNTOVF_Msk                      /*!< Missed Packet Counter Overflow Bit */
11115 
11116 /*************  Bit definition for ETH_MTLRXQ0DR register  *************/
11117 #define ETH_MTLRXQ0DR_RWCSTS_Pos            (0U)
11118 #define ETH_MTLRXQ0DR_RWCSTS_Msk            (0x1U << ETH_MTLRXQ0DR_RWCSTS_Pos)                  /*!< 0x00000001 */
11119 #define ETH_MTLRXQ0DR_RWCSTS                ETH_MTLRXQ0DR_RWCSTS_Msk                            /*!< MTL Rx Queue Write Controller Active Status */
11120 #define ETH_MTLRXQ0DR_RRCSTS_Pos            (1U)
11121 #define ETH_MTLRXQ0DR_RRCSTS_Msk            (0x3U << ETH_MTLRXQ0DR_RRCSTS_Pos)                  /*!< 0x00000006 */
11122 #define ETH_MTLRXQ0DR_RRCSTS                ETH_MTLRXQ0DR_RRCSTS_Msk                            /*!< MTL Rx Queue Read Controller State */
11123 #define ETH_MTLRXQ0DR_RRCSTS_0              (0x1U << ETH_MTLRXQ0DR_RRCSTS_Pos)                  /*!< 0x00000002 */
11124 #define ETH_MTLRXQ0DR_RRCSTS_1              (0x2U << ETH_MTLRXQ0DR_RRCSTS_Pos)                  /*!< 0x00000004 */
11125 #define ETH_MTLRXQ0DR_RXQSTS_Pos            (4U)
11126 #define ETH_MTLRXQ0DR_RXQSTS_Msk            (0x3U << ETH_MTLRXQ0DR_RXQSTS_Pos)                  /*!< 0x00000030 */
11127 #define ETH_MTLRXQ0DR_RXQSTS                ETH_MTLRXQ0DR_RXQSTS_Msk                            /*!< MTL Rx Queue Fill-Level Status */
11128 #define ETH_MTLRXQ0DR_RXQSTS_0              (0x1U << ETH_MTLRXQ0DR_RXQSTS_Pos)                 /*!< 0x00000010 */
11129 #define ETH_MTLRXQ0DR_RXQSTS_1              (0x2U << ETH_MTLRXQ0DR_RXQSTS_Pos)                 /*!< 0x00000020 */
11130 #define ETH_MTLRXQ0DR_PRXQ_Pos              (16U)
11131 #define ETH_MTLRXQ0DR_PRXQ_Msk              (0x3FFFU << ETH_MTLRXQ0DR_PRXQ_Pos)                 /*!< 0x3FFF0000 */
11132 #define ETH_MTLRXQ0DR_PRXQ                  ETH_MTLRXQ0DR_PRXQ_Msk                              /*!< Number of Packets in Receive Queue */
11133 #define ETH_MTLRXQ0DR_PRXQ_0                (0x1U << ETH_MTLRXQ0DR_PRXQ_Pos)                /*!< 0x00010000 */
11134 #define ETH_MTLRXQ0DR_PRXQ_1                (0x2U << ETH_MTLRXQ0DR_PRXQ_Pos)                /*!< 0x00020000 */
11135 #define ETH_MTLRXQ0DR_PRXQ_2                (0x4U << ETH_MTLRXQ0DR_PRXQ_Pos)                /*!< 0x00040000 */
11136 #define ETH_MTLRXQ0DR_PRXQ_3                (0x8U << ETH_MTLRXQ0DR_PRXQ_Pos)                /*!< 0x00080000 */
11137 #define ETH_MTLRXQ0DR_PRXQ_4                (0x10U << ETH_MTLRXQ0DR_PRXQ_Pos)               /*!< 0x00100000 */
11138 #define ETH_MTLRXQ0DR_PRXQ_5                (0x20U << ETH_MTLRXQ0DR_PRXQ_Pos)               /*!< 0x00200000 */
11139 #define ETH_MTLRXQ0DR_PRXQ_6                (0x40U << ETH_MTLRXQ0DR_PRXQ_Pos)               /*!< 0x00400000 */
11140 #define ETH_MTLRXQ0DR_PRXQ_7                (0x80U << ETH_MTLRXQ0DR_PRXQ_Pos)               /*!< 0x00800000 */
11141 #define ETH_MTLRXQ0DR_PRXQ_8                (0x100U << ETH_MTLRXQ0DR_PRXQ_Pos)              /*!< 0x01000000 */
11142 #define ETH_MTLRXQ0DR_PRXQ_9                (0x200U << ETH_MTLRXQ0DR_PRXQ_Pos)              /*!< 0x02000000 */
11143 #define ETH_MTLRXQ0DR_PRXQ_10               (0x400U << ETH_MTLRXQ0DR_PRXQ_Pos)              /*!< 0x04000000 */
11144 #define ETH_MTLRXQ0DR_PRXQ_11               (0x800U << ETH_MTLRXQ0DR_PRXQ_Pos)              /*!< 0x08000000 */
11145 #define ETH_MTLRXQ0DR_PRXQ_12               (0x1000U << ETH_MTLRXQ0DR_PRXQ_Pos)             /*!< 0x10000000 */
11146 #define ETH_MTLRXQ0DR_PRXQ_13               (0x2000U << ETH_MTLRXQ0DR_PRXQ_Pos)             /*!< 0x20000000 */
11147 
11148 /*************  Bit definition for ETH_MTLRXQ0CR register  *************/
11149 #define ETH_MTLRXQ0CR_RXQ_WEGT_Pos          (0U)
11150 #define ETH_MTLRXQ0CR_RXQ_WEGT_Msk          (0x7U << ETH_MTLRXQ0CR_RXQ_WEGT_Pos)                /*!< 0x00000007 */
11151 #define ETH_MTLRXQ0CR_RXQ_WEGT              ETH_MTLRXQ0CR_RXQ_WEGT_Msk                          /*!< Receive Queue Weight */
11152 #define ETH_MTLRXQ0CR_RXQ_WEGT_0            (0x1U << ETH_MTLRXQ0CR_RXQ_WEGT_Pos)                /*!< 0x00000001 */
11153 #define ETH_MTLRXQ0CR_RXQ_WEGT_1            (0x2U << ETH_MTLRXQ0CR_RXQ_WEGT_Pos)                /*!< 0x00000002 */
11154 #define ETH_MTLRXQ0CR_RXQ_WEGT_2            (0x4U << ETH_MTLRXQ0CR_RXQ_WEGT_Pos)                /*!< 0x00000004 */
11155 #define ETH_MTLRXQ0CR_RXQ_FRM_ARBIT_Pos     (3U)
11156 #define ETH_MTLRXQ0CR_RXQ_FRM_ARBIT_Msk     (0x1U << ETH_MTLRXQ0CR_RXQ_FRM_ARBIT_Pos)           /*!< 0x00000008 */
11157 #define ETH_MTLRXQ0CR_RXQ_FRM_ARBIT         ETH_MTLRXQ0CR_RXQ_FRM_ARBIT_Msk                     /*!< Receive Queue Packet Arbitration */
11158 
11159 /************  Bit definition for ETH_MTLTXQ1OMR register  *************/
11160 #define ETH_MTLTXQ1OMR_FTQ_Pos              (0U)
11161 #define ETH_MTLTXQ1OMR_FTQ_Msk              (0x1U << ETH_MTLTXQ1OMR_FTQ_Pos)                    /*!< 0x00000001 */
11162 #define ETH_MTLTXQ1OMR_FTQ                  ETH_MTLTXQ1OMR_FTQ_Msk                              /*!< Flush Transmit Queue */
11163 #define ETH_MTLTXQ1OMR_TSF_Pos              (1U)
11164 #define ETH_MTLTXQ1OMR_TSF_Msk              (0x1U << ETH_MTLTXQ1OMR_TSF_Pos)                    /*!< 0x00000002 */
11165 #define ETH_MTLTXQ1OMR_TSF                  ETH_MTLTXQ1OMR_TSF_Msk                              /*!< Transmit Store and Forward */
11166 #define ETH_MTLTXQ1OMR_TXQEN_Pos            (2U)
11167 #define ETH_MTLTXQ1OMR_TXQEN_Msk            (0x3U << ETH_MTLTXQ1OMR_TXQEN_Pos)                  /*!< 0x0000000C */
11168 #define ETH_MTLTXQ1OMR_TXQEN                ETH_MTLTXQ1OMR_TXQEN_Msk                            /*!< Transmit Queue Enable */
11169 #define ETH_MTLTXQ1OMR_TXQEN_0              (0x1U << ETH_MTLTXQ1OMR_TXQEN_Pos)                  /*!< 0x00000004 */
11170 #define ETH_MTLTXQ1OMR_TXQEN_1              (0x2U << ETH_MTLTXQ1OMR_TXQEN_Pos)                  /*!< 0x00000008 */
11171 #define ETH_MTLTXQ1OMR_TTC_Pos              (4U)
11172 #define ETH_MTLTXQ1OMR_TTC_Msk              (0x7U << ETH_MTLTXQ1OMR_TTC_Pos)                    /*!< 0x00000070 */
11173 #define ETH_MTLTXQ1OMR_TTC                  ETH_MTLTXQ1OMR_TTC_Msk                              /*!< Transmit Threshold Control */
11174 #define ETH_MTLTXQ1OMR_TTC_0                (0x1U << ETH_MTLTXQ1OMR_TTC_Pos)                   /*!< 0x00000010 */
11175 #define ETH_MTLTXQ1OMR_TTC_1                (0x2U << ETH_MTLTXQ1OMR_TTC_Pos)                   /*!< 0x00000020 */
11176 #define ETH_MTLTXQ1OMR_TTC_2                (0x4U << ETH_MTLTXQ1OMR_TTC_Pos)                   /*!< 0x00000040 */
11177 #define ETH_MTLTXQ1OMR_TQS_Pos              (16U)
11178 #define ETH_MTLTXQ1OMR_TQS_Msk              (0x1FFU << ETH_MTLTXQ1OMR_TQS_Pos)                  /*!< 0x01FF0000 */
11179 #define ETH_MTLTXQ1OMR_TQS                  ETH_MTLTXQ1OMR_TQS_Msk                              /*!< Transmit Queue Size */
11180 #define ETH_MTLTXQ1OMR_TQS_0                (0x1U << ETH_MTLTXQ1OMR_TQS_Pos)                /*!< 0x00010000 */
11181 #define ETH_MTLTXQ1OMR_TQS_1                (0x2U << ETH_MTLTXQ1OMR_TQS_Pos)                /*!< 0x00020000 */
11182 #define ETH_MTLTXQ1OMR_TQS_2                (0x4U << ETH_MTLTXQ1OMR_TQS_Pos)                /*!< 0x00040000 */
11183 #define ETH_MTLTXQ1OMR_TQS_3                (0x8U << ETH_MTLTXQ1OMR_TQS_Pos)                /*!< 0x00080000 */
11184 #define ETH_MTLTXQ1OMR_TQS_4                (0x10U << ETH_MTLTXQ1OMR_TQS_Pos)               /*!< 0x00100000 */
11185 #define ETH_MTLTXQ1OMR_TQS_5                (0x20U << ETH_MTLTXQ1OMR_TQS_Pos)               /*!< 0x00200000 */
11186 #define ETH_MTLTXQ1OMR_TQS_6                (0x40U << ETH_MTLTXQ1OMR_TQS_Pos)               /*!< 0x00400000 */
11187 #define ETH_MTLTXQ1OMR_TQS_7                (0x80U << ETH_MTLTXQ1OMR_TQS_Pos)               /*!< 0x00800000 */
11188 #define ETH_MTLTXQ1OMR_TQS_8                (0x100U << ETH_MTLTXQ1OMR_TQS_Pos)              /*!< 0x01000000 */
11189 
11190 /*************  Bit definition for ETH_MTLTXQ1UR register  *************/
11191 #define ETH_MTLTXQ1UR_UFFRMCNT_Pos          (0U)
11192 #define ETH_MTLTXQ1UR_UFFRMCNT_Msk          (0x7FFU << ETH_MTLTXQ1UR_UFFRMCNT_Pos)              /*!< 0x000007FF */
11193 #define ETH_MTLTXQ1UR_UFFRMCNT              ETH_MTLTXQ1UR_UFFRMCNT_Msk                          /*!< Underflow Packet Counter */
11194 #define ETH_MTLTXQ1UR_UFFRMCNT_0            (0x1U << ETH_MTLTXQ1UR_UFFRMCNT_Pos)                /*!< 0x00000001 */
11195 #define ETH_MTLTXQ1UR_UFFRMCNT_1            (0x2U << ETH_MTLTXQ1UR_UFFRMCNT_Pos)                /*!< 0x00000002 */
11196 #define ETH_MTLTXQ1UR_UFFRMCNT_2            (0x4U << ETH_MTLTXQ1UR_UFFRMCNT_Pos)                /*!< 0x00000004 */
11197 #define ETH_MTLTXQ1UR_UFFRMCNT_3            (0x8U << ETH_MTLTXQ1UR_UFFRMCNT_Pos)                /*!< 0x00000008 */
11198 #define ETH_MTLTXQ1UR_UFFRMCNT_4            (0x10U << ETH_MTLTXQ1UR_UFFRMCNT_Pos)               /*!< 0x00000010 */
11199 #define ETH_MTLTXQ1UR_UFFRMCNT_5            (0x20U << ETH_MTLTXQ1UR_UFFRMCNT_Pos)               /*!< 0x00000020 */
11200 #define ETH_MTLTXQ1UR_UFFRMCNT_6            (0x40U << ETH_MTLTXQ1UR_UFFRMCNT_Pos)               /*!< 0x00000040 */
11201 #define ETH_MTLTXQ1UR_UFFRMCNT_7            (0x80U << ETH_MTLTXQ1UR_UFFRMCNT_Pos)               /*!< 0x00000080 */
11202 #define ETH_MTLTXQ1UR_UFFRMCNT_8            (0x100U << ETH_MTLTXQ1UR_UFFRMCNT_Pos)              /*!< 0x00000100 */
11203 #define ETH_MTLTXQ1UR_UFFRMCNT_9            (0x200U << ETH_MTLTXQ1UR_UFFRMCNT_Pos)              /*!< 0x00000200 */
11204 #define ETH_MTLTXQ1UR_UFFRMCNT_10           (0x400U << ETH_MTLTXQ1UR_UFFRMCNT_Pos)              /*!< 0x00000400 */
11205 #define ETH_MTLTXQ1UR_UFCNTOVF_Pos          (11U)
11206 #define ETH_MTLTXQ1UR_UFCNTOVF_Msk          (0x1U << ETH_MTLTXQ1UR_UFCNTOVF_Pos)                /*!< 0x00000800 */
11207 #define ETH_MTLTXQ1UR_UFCNTOVF              ETH_MTLTXQ1UR_UFCNTOVF_Msk                          /*!< Overflow Bit for Underflow Packet Counter */
11208 
11209 /*************  Bit definition for ETH_MTLTXQ1DR register  *************/
11210 #define ETH_MTLTXQ1DR_TXQPAUSED_Pos         (0U)
11211 #define ETH_MTLTXQ1DR_TXQPAUSED_Msk         (0x1U << ETH_MTLTXQ1DR_TXQPAUSED_Pos)               /*!< 0x00000001 */
11212 #define ETH_MTLTXQ1DR_TXQPAUSED             ETH_MTLTXQ1DR_TXQPAUSED_Msk                         /*!< Transmit Queue in Pause */
11213 #define ETH_MTLTXQ1DR_TRCSTS_Pos            (1U)
11214 #define ETH_MTLTXQ1DR_TRCSTS_Msk            (0x3U << ETH_MTLTXQ1DR_TRCSTS_Pos)                  /*!< 0x00000006 */
11215 #define ETH_MTLTXQ1DR_TRCSTS                ETH_MTLTXQ1DR_TRCSTS_Msk                            /*!< MTL Tx Queue Read Controller Status */
11216 #define ETH_MTLTXQ1DR_TRCSTS_0              (0x1U << ETH_MTLTXQ1DR_TRCSTS_Pos)                  /*!< 0x00000002 */
11217 #define ETH_MTLTXQ1DR_TRCSTS_1              (0x2U << ETH_MTLTXQ1DR_TRCSTS_Pos)                  /*!< 0x00000004 */
11218 #define ETH_MTLTXQ1DR_TWCSTS_Pos            (3U)
11219 #define ETH_MTLTXQ1DR_TWCSTS_Msk            (0x1U << ETH_MTLTXQ1DR_TWCSTS_Pos)                  /*!< 0x00000008 */
11220 #define ETH_MTLTXQ1DR_TWCSTS                ETH_MTLTXQ1DR_TWCSTS_Msk                            /*!< MTL Tx Queue Write Controller Status */
11221 #define ETH_MTLTXQ1DR_TXQSTS_Pos            (4U)
11222 #define ETH_MTLTXQ1DR_TXQSTS_Msk            (0x1U << ETH_MTLTXQ1DR_TXQSTS_Pos)                  /*!< 0x00000010 */
11223 #define ETH_MTLTXQ1DR_TXQSTS                ETH_MTLTXQ1DR_TXQSTS_Msk                            /*!< MTL Tx Queue Not Empty Status */
11224 #define ETH_MTLTXQ1DR_TXSTSFSTS_Pos         (5U)
11225 #define ETH_MTLTXQ1DR_TXSTSFSTS_Msk         (0x1U << ETH_MTLTXQ1DR_TXSTSFSTS_Pos)               /*!< 0x00000020 */
11226 #define ETH_MTLTXQ1DR_TXSTSFSTS             ETH_MTLTXQ1DR_TXSTSFSTS_Msk                         /*!< MTL Tx Status FIFO Full Status */
11227 #define ETH_MTLTXQ1DR_PTXQ_Pos              (16U)
11228 #define ETH_MTLTXQ1DR_PTXQ_Msk              (0x7U << ETH_MTLTXQ1DR_PTXQ_Pos)                    /*!< 0x00070000 */
11229 #define ETH_MTLTXQ1DR_PTXQ                  ETH_MTLTXQ1DR_PTXQ_Msk                              /*!< Number of Packets in the Transmit Queue */
11230 #define ETH_MTLTXQ1DR_PTXQ_0                (0x1U << ETH_MTLTXQ1DR_PTXQ_Pos)                /*!< 0x00010000 */
11231 #define ETH_MTLTXQ1DR_PTXQ_1                (0x2U << ETH_MTLTXQ1DR_PTXQ_Pos)                /*!< 0x00020000 */
11232 #define ETH_MTLTXQ1DR_PTXQ_2                (0x4U << ETH_MTLTXQ1DR_PTXQ_Pos)                /*!< 0x00040000 */
11233 #define ETH_MTLTXQ1DR_STXSTSF_Pos           (20U)
11234 #define ETH_MTLTXQ1DR_STXSTSF_Msk           (0x7U << ETH_MTLTXQ1DR_STXSTSF_Pos)                 /*!< 0x00700000 */
11235 #define ETH_MTLTXQ1DR_STXSTSF               ETH_MTLTXQ1DR_STXSTSF_Msk                           /*!< Number of Status Words in Tx Status FIFO of Queue */
11236 #define ETH_MTLTXQ1DR_STXSTSF_0             (0x1U << ETH_MTLTXQ1DR_STXSTSF_Pos)            /*!< 0x00100000 */
11237 #define ETH_MTLTXQ1DR_STXSTSF_1             (0x2U << ETH_MTLTXQ1DR_STXSTSF_Pos)            /*!< 0x00200000 */
11238 #define ETH_MTLTXQ1DR_STXSTSF_2             (0x4U << ETH_MTLTXQ1DR_STXSTSF_Pos)            /*!< 0x00400000 */
11239 
11240 /************  Bit definition for ETH_MTLTXQ1ECR register  *************/
11241 #define ETH_MTLTXQ1ECR_AVALG_Pos            (2U)
11242 #define ETH_MTLTXQ1ECR_AVALG_Msk            (0x1U << ETH_MTLTXQ1ECR_AVALG_Pos)                  /*!< 0x00000004 */
11243 #define ETH_MTLTXQ1ECR_AVALG                ETH_MTLTXQ1ECR_AVALG_Msk                            /*!< AV Algorithm */
11244 #define ETH_MTLTXQ1ECR_CC_Pos               (3U)
11245 #define ETH_MTLTXQ1ECR_CC_Msk               (0x1U << ETH_MTLTXQ1ECR_CC_Pos)                     /*!< 0x00000008 */
11246 #define ETH_MTLTXQ1ECR_CC                   ETH_MTLTXQ1ECR_CC_Msk                               /*!< Credit Control */
11247 #define ETH_MTLTXQ1ECR_SLC_Pos              (4U)
11248 #define ETH_MTLTXQ1ECR_SLC_Msk              (0x7U << ETH_MTLTXQ1ECR_SLC_Pos)                    /*!< 0x00000070 */
11249 #define ETH_MTLTXQ1ECR_SLC                  ETH_MTLTXQ1ECR_SLC_Msk                              /*!< Slot Count */
11250 #define ETH_MTLTXQ1ECR_SLC_0                (0x1U << ETH_MTLTXQ1ECR_SLC_Pos)                   /*!< 0x00000010 */
11251 #define ETH_MTLTXQ1ECR_SLC_1                (0x2U << ETH_MTLTXQ1ECR_SLC_Pos)                   /*!< 0x00000020 */
11252 #define ETH_MTLTXQ1ECR_SLC_2                (0x4U << ETH_MTLTXQ1ECR_SLC_Pos)                   /*!< 0x00000040 */
11253 
11254 /************  Bit definition for ETH_MTLTXQ1ESR register  *************/
11255 #define ETH_MTLTXQ1ESR_ABS_Pos              (0U)
11256 #define ETH_MTLTXQ1ESR_ABS_Msk              (0xFFFFFFU << ETH_MTLTXQ1ESR_ABS_Pos)               /*!< 0x00FFFFFF */
11257 #define ETH_MTLTXQ1ESR_ABS                  ETH_MTLTXQ1ESR_ABS_Msk                              /*!< Average Bits per Slot */
11258 #define ETH_MTLTXQ1ESR_ABS_0                (0x1U << ETH_MTLTXQ1ESR_ABS_Pos)                    /*!< 0x00000001 */
11259 #define ETH_MTLTXQ1ESR_ABS_1                (0x2U << ETH_MTLTXQ1ESR_ABS_Pos)                    /*!< 0x00000002 */
11260 #define ETH_MTLTXQ1ESR_ABS_2                (0x4U << ETH_MTLTXQ1ESR_ABS_Pos)                    /*!< 0x00000004 */
11261 #define ETH_MTLTXQ1ESR_ABS_3                (0x8U << ETH_MTLTXQ1ESR_ABS_Pos)                    /*!< 0x00000008 */
11262 #define ETH_MTLTXQ1ESR_ABS_4                (0x10U << ETH_MTLTXQ1ESR_ABS_Pos)                   /*!< 0x00000010 */
11263 #define ETH_MTLTXQ1ESR_ABS_5                (0x20U << ETH_MTLTXQ1ESR_ABS_Pos)                   /*!< 0x00000020 */
11264 #define ETH_MTLTXQ1ESR_ABS_6                (0x40U << ETH_MTLTXQ1ESR_ABS_Pos)                   /*!< 0x00000040 */
11265 #define ETH_MTLTXQ1ESR_ABS_7                (0x80U << ETH_MTLTXQ1ESR_ABS_Pos)                   /*!< 0x00000080 */
11266 #define ETH_MTLTXQ1ESR_ABS_8                (0x100U << ETH_MTLTXQ1ESR_ABS_Pos)                  /*!< 0x00000100 */
11267 #define ETH_MTLTXQ1ESR_ABS_9                (0x200U << ETH_MTLTXQ1ESR_ABS_Pos)                  /*!< 0x00000200 */
11268 #define ETH_MTLTXQ1ESR_ABS_10               (0x400U << ETH_MTLTXQ1ESR_ABS_Pos)                  /*!< 0x00000400 */
11269 #define ETH_MTLTXQ1ESR_ABS_11               (0x800U << ETH_MTLTXQ1ESR_ABS_Pos)                  /*!< 0x00000800 */
11270 #define ETH_MTLTXQ1ESR_ABS_12               (0x1000U << ETH_MTLTXQ1ESR_ABS_Pos)                 /*!< 0x00001000 */
11271 #define ETH_MTLTXQ1ESR_ABS_13               (0x2000U << ETH_MTLTXQ1ESR_ABS_Pos)                 /*!< 0x00002000 */
11272 #define ETH_MTLTXQ1ESR_ABS_14               (0x4000U << ETH_MTLTXQ1ESR_ABS_Pos)                 /*!< 0x00004000 */
11273 #define ETH_MTLTXQ1ESR_ABS_15               (0x8000U << ETH_MTLTXQ1ESR_ABS_Pos)                 /*!< 0x00008000 */
11274 #define ETH_MTLTXQ1ESR_ABS_16               (0x10000U << ETH_MTLTXQ1ESR_ABS_Pos)                /*!< 0x00010000 */
11275 #define ETH_MTLTXQ1ESR_ABS_17               (0x20000U << ETH_MTLTXQ1ESR_ABS_Pos)                /*!< 0x00020000 */
11276 #define ETH_MTLTXQ1ESR_ABS_18               (0x40000U << ETH_MTLTXQ1ESR_ABS_Pos)                /*!< 0x00040000 */
11277 #define ETH_MTLTXQ1ESR_ABS_19               (0x80000U << ETH_MTLTXQ1ESR_ABS_Pos)                /*!< 0x00080000 */
11278 #define ETH_MTLTXQ1ESR_ABS_20               (0x100000U << ETH_MTLTXQ1ESR_ABS_Pos)               /*!< 0x00100000 */
11279 #define ETH_MTLTXQ1ESR_ABS_21               (0x200000U << ETH_MTLTXQ1ESR_ABS_Pos)               /*!< 0x00200000 */
11280 #define ETH_MTLTXQ1ESR_ABS_22               (0x400000U << ETH_MTLTXQ1ESR_ABS_Pos)               /*!< 0x00400000 */
11281 #define ETH_MTLTXQ1ESR_ABS_23               (0x800000U << ETH_MTLTXQ1ESR_ABS_Pos)               /*!< 0x00800000 */
11282 
11283 /************  Bit definition for ETH_MTLTXQ1QWR register  *************/
11284 #define ETH_MTLTXQ1QWR_ISCQW_Pos            (0U)
11285 #define ETH_MTLTXQ1QWR_ISCQW_Msk            (0x1FFFFFU << ETH_MTLTXQ1QWR_ISCQW_Pos)             /*!< 0x001FFFFF */
11286 #define ETH_MTLTXQ1QWR_ISCQW                ETH_MTLTXQ1QWR_ISCQW_Msk                            /*!< idleSlopeCredit value for queue 1 */
11287 #define ETH_MTLTXQ1QWR_ISCQW_0              (0x1U << ETH_MTLTXQ1QWR_ISCQW_Pos)                  /*!< 0x00000001 */
11288 #define ETH_MTLTXQ1QWR_ISCQW_1              (0x2U << ETH_MTLTXQ1QWR_ISCQW_Pos)                  /*!< 0x00000002 */
11289 #define ETH_MTLTXQ1QWR_ISCQW_2              (0x4U << ETH_MTLTXQ1QWR_ISCQW_Pos)                  /*!< 0x00000004 */
11290 #define ETH_MTLTXQ1QWR_ISCQW_3              (0x8U << ETH_MTLTXQ1QWR_ISCQW_Pos)                  /*!< 0x00000008 */
11291 #define ETH_MTLTXQ1QWR_ISCQW_4              (0x10U << ETH_MTLTXQ1QWR_ISCQW_Pos)                 /*!< 0x00000010 */
11292 #define ETH_MTLTXQ1QWR_ISCQW_5              (0x20U << ETH_MTLTXQ1QWR_ISCQW_Pos)                 /*!< 0x00000020 */
11293 #define ETH_MTLTXQ1QWR_ISCQW_6              (0x40U << ETH_MTLTXQ1QWR_ISCQW_Pos)                 /*!< 0x00000040 */
11294 #define ETH_MTLTXQ1QWR_ISCQW_7              (0x80U << ETH_MTLTXQ1QWR_ISCQW_Pos)                 /*!< 0x00000080 */
11295 #define ETH_MTLTXQ1QWR_ISCQW_8              (0x100U << ETH_MTLTXQ1QWR_ISCQW_Pos)                /*!< 0x00000100 */
11296 #define ETH_MTLTXQ1QWR_ISCQW_9              (0x200U << ETH_MTLTXQ1QWR_ISCQW_Pos)                /*!< 0x00000200 */
11297 #define ETH_MTLTXQ1QWR_ISCQW_10             (0x400U << ETH_MTLTXQ1QWR_ISCQW_Pos)                /*!< 0x00000400 */
11298 #define ETH_MTLTXQ1QWR_ISCQW_11             (0x800U << ETH_MTLTXQ1QWR_ISCQW_Pos)                /*!< 0x00000800 */
11299 #define ETH_MTLTXQ1QWR_ISCQW_12             (0x1000U << ETH_MTLTXQ1QWR_ISCQW_Pos)               /*!< 0x00001000 */
11300 #define ETH_MTLTXQ1QWR_ISCQW_13             (0x2000U << ETH_MTLTXQ1QWR_ISCQW_Pos)               /*!< 0x00002000 */
11301 #define ETH_MTLTXQ1QWR_ISCQW_14             (0x4000U << ETH_MTLTXQ1QWR_ISCQW_Pos)               /*!< 0x00004000 */
11302 #define ETH_MTLTXQ1QWR_ISCQW_15             (0x8000U << ETH_MTLTXQ1QWR_ISCQW_Pos)               /*!< 0x00008000 */
11303 #define ETH_MTLTXQ1QWR_ISCQW_16             (0x10000U << ETH_MTLTXQ1QWR_ISCQW_Pos)              /*!< 0x00010000 */
11304 #define ETH_MTLTXQ1QWR_ISCQW_17             (0x20000U << ETH_MTLTXQ1QWR_ISCQW_Pos)              /*!< 0x00020000 */
11305 #define ETH_MTLTXQ1QWR_ISCQW_18             (0x40000U << ETH_MTLTXQ1QWR_ISCQW_Pos)              /*!< 0x00040000 */
11306 #define ETH_MTLTXQ1QWR_ISCQW_19             (0x80000U << ETH_MTLTXQ1QWR_ISCQW_Pos)              /*!< 0x00080000 */
11307 #define ETH_MTLTXQ1QWR_ISCQW_20             (0x100000U << ETH_MTLTXQ1QWR_ISCQW_Pos)             /*!< 0x00100000 */
11308 
11309 /************  Bit definition for ETH_MTLTXQ1SSCR register  ************/
11310 #define ETH_MTLTXQ1SSCR_SSC_Pos             (0U)
11311 #define ETH_MTLTXQ1SSCR_SSC_Msk             (0x3FFFU << ETH_MTLTXQ1SSCR_SSC_Pos)                /*!< 0x00003FFF */
11312 #define ETH_MTLTXQ1SSCR_SSC                 ETH_MTLTXQ1SSCR_SSC_Msk                             /*!< sendSlopeCredit Value */
11313 #define ETH_MTLTXQ1SSCR_SSC_0               (0x1U << ETH_MTLTXQ1SSCR_SSC_Pos)                   /*!< 0x00000001 */
11314 #define ETH_MTLTXQ1SSCR_SSC_1               (0x2U << ETH_MTLTXQ1SSCR_SSC_Pos)                   /*!< 0x00000002 */
11315 #define ETH_MTLTXQ1SSCR_SSC_2               (0x4U << ETH_MTLTXQ1SSCR_SSC_Pos)                   /*!< 0x00000004 */
11316 #define ETH_MTLTXQ1SSCR_SSC_3               (0x8U << ETH_MTLTXQ1SSCR_SSC_Pos)                   /*!< 0x00000008 */
11317 #define ETH_MTLTXQ1SSCR_SSC_4               (0x10U << ETH_MTLTXQ1SSCR_SSC_Pos)                  /*!< 0x00000010 */
11318 #define ETH_MTLTXQ1SSCR_SSC_5               (0x20U << ETH_MTLTXQ1SSCR_SSC_Pos)                  /*!< 0x00000020 */
11319 #define ETH_MTLTXQ1SSCR_SSC_6               (0x40U << ETH_MTLTXQ1SSCR_SSC_Pos)                  /*!< 0x00000040 */
11320 #define ETH_MTLTXQ1SSCR_SSC_7               (0x80U << ETH_MTLTXQ1SSCR_SSC_Pos)                  /*!< 0x00000080 */
11321 #define ETH_MTLTXQ1SSCR_SSC_8               (0x100U << ETH_MTLTXQ1SSCR_SSC_Pos)                 /*!< 0x00000100 */
11322 #define ETH_MTLTXQ1SSCR_SSC_9               (0x200U << ETH_MTLTXQ1SSCR_SSC_Pos)                 /*!< 0x00000200 */
11323 #define ETH_MTLTXQ1SSCR_SSC_10              (0x400U << ETH_MTLTXQ1SSCR_SSC_Pos)                 /*!< 0x00000400 */
11324 #define ETH_MTLTXQ1SSCR_SSC_11              (0x800U << ETH_MTLTXQ1SSCR_SSC_Pos)                 /*!< 0x00000800 */
11325 #define ETH_MTLTXQ1SSCR_SSC_12              (0x1000U << ETH_MTLTXQ1SSCR_SSC_Pos)                /*!< 0x00001000 */
11326 #define ETH_MTLTXQ1SSCR_SSC_13              (0x2000U << ETH_MTLTXQ1SSCR_SSC_Pos)                /*!< 0x00002000 */
11327 
11328 /************  Bit definition for ETH_MTLTXQ1HCR register  *************/
11329 #define ETH_MTLTXQ1HCR_HC_Pos               (0U)
11330 #define ETH_MTLTXQ1HCR_HC_Msk               (0x1FFFFFFFU << ETH_MTLTXQ1HCR_HC_Pos)              /*!< 0x1FFFFFFF */
11331 #define ETH_MTLTXQ1HCR_HC                   ETH_MTLTXQ1HCR_HC_Msk                               /*!< hiCredit Value */
11332 #define ETH_MTLTXQ1HCR_HC_0                 (0x1U << ETH_MTLTXQ1HCR_HC_Pos)                     /*!< 0x00000001 */
11333 #define ETH_MTLTXQ1HCR_HC_1                 (0x2U << ETH_MTLTXQ1HCR_HC_Pos)                     /*!< 0x00000002 */
11334 #define ETH_MTLTXQ1HCR_HC_2                 (0x4U << ETH_MTLTXQ1HCR_HC_Pos)                     /*!< 0x00000004 */
11335 #define ETH_MTLTXQ1HCR_HC_3                 (0x8U << ETH_MTLTXQ1HCR_HC_Pos)                     /*!< 0x00000008 */
11336 #define ETH_MTLTXQ1HCR_HC_4                 (0x10U << ETH_MTLTXQ1HCR_HC_Pos)                    /*!< 0x00000010 */
11337 #define ETH_MTLTXQ1HCR_HC_5                 (0x20U << ETH_MTLTXQ1HCR_HC_Pos)                    /*!< 0x00000020 */
11338 #define ETH_MTLTXQ1HCR_HC_6                 (0x40U << ETH_MTLTXQ1HCR_HC_Pos)                    /*!< 0x00000040 */
11339 #define ETH_MTLTXQ1HCR_HC_7                 (0x80U << ETH_MTLTXQ1HCR_HC_Pos)                    /*!< 0x00000080 */
11340 #define ETH_MTLTXQ1HCR_HC_8                 (0x100U << ETH_MTLTXQ1HCR_HC_Pos)                   /*!< 0x00000100 */
11341 #define ETH_MTLTXQ1HCR_HC_9                 (0x200U << ETH_MTLTXQ1HCR_HC_Pos)                   /*!< 0x00000200 */
11342 #define ETH_MTLTXQ1HCR_HC_10                (0x400U << ETH_MTLTXQ1HCR_HC_Pos)                   /*!< 0x00000400 */
11343 #define ETH_MTLTXQ1HCR_HC_11                (0x800U << ETH_MTLTXQ1HCR_HC_Pos)                   /*!< 0x00000800 */
11344 #define ETH_MTLTXQ1HCR_HC_12                (0x1000U << ETH_MTLTXQ1HCR_HC_Pos)                  /*!< 0x00001000 */
11345 #define ETH_MTLTXQ1HCR_HC_13                (0x2000U << ETH_MTLTXQ1HCR_HC_Pos)                  /*!< 0x00002000 */
11346 #define ETH_MTLTXQ1HCR_HC_14                (0x4000U << ETH_MTLTXQ1HCR_HC_Pos)                  /*!< 0x00004000 */
11347 #define ETH_MTLTXQ1HCR_HC_15                (0x8000U << ETH_MTLTXQ1HCR_HC_Pos)                  /*!< 0x00008000 */
11348 #define ETH_MTLTXQ1HCR_HC_16                (0x10000U << ETH_MTLTXQ1HCR_HC_Pos)                 /*!< 0x00010000 */
11349 #define ETH_MTLTXQ1HCR_HC_17                (0x20000U << ETH_MTLTXQ1HCR_HC_Pos)                 /*!< 0x00020000 */
11350 #define ETH_MTLTXQ1HCR_HC_18                (0x40000U << ETH_MTLTXQ1HCR_HC_Pos)                 /*!< 0x00040000 */
11351 #define ETH_MTLTXQ1HCR_HC_19                (0x80000U << ETH_MTLTXQ1HCR_HC_Pos)                 /*!< 0x00080000 */
11352 #define ETH_MTLTXQ1HCR_HC_20                (0x100000U << ETH_MTLTXQ1HCR_HC_Pos)                /*!< 0x00100000 */
11353 #define ETH_MTLTXQ1HCR_HC_21                (0x200000U << ETH_MTLTXQ1HCR_HC_Pos)                /*!< 0x00200000 */
11354 #define ETH_MTLTXQ1HCR_HC_22                (0x400000U << ETH_MTLTXQ1HCR_HC_Pos)                /*!< 0x00400000 */
11355 #define ETH_MTLTXQ1HCR_HC_23                (0x800000U << ETH_MTLTXQ1HCR_HC_Pos)                /*!< 0x00800000 */
11356 #define ETH_MTLTXQ1HCR_HC_24                (0x1000000U << ETH_MTLTXQ1HCR_HC_Pos)               /*!< 0x01000000 */
11357 #define ETH_MTLTXQ1HCR_HC_25                (0x2000000U << ETH_MTLTXQ1HCR_HC_Pos)               /*!< 0x02000000 */
11358 #define ETH_MTLTXQ1HCR_HC_26                (0x4000000U << ETH_MTLTXQ1HCR_HC_Pos)               /*!< 0x04000000 */
11359 #define ETH_MTLTXQ1HCR_HC_27                (0x8000000U << ETH_MTLTXQ1HCR_HC_Pos)               /*!< 0x08000000 */
11360 #define ETH_MTLTXQ1HCR_HC_28                (0x10000000U << ETH_MTLTXQ1HCR_HC_Pos)              /*!< 0x10000000 */
11361 
11362 /************  Bit definition for ETH_MTLTXQ1LCR register  *************/
11363 #define ETH_MTLTXQ1LCR_LC_Pos               (0U)
11364 #define ETH_MTLTXQ1LCR_LC_Msk               (0x1FFFFFFFU << ETH_MTLTXQ1LCR_LC_Pos)              /*!< 0x1FFFFFFF */
11365 #define ETH_MTLTXQ1LCR_LC                   ETH_MTLTXQ1LCR_LC_Msk                               /*!< loCredit Value */
11366 #define ETH_MTLTXQ1LCR_LC_0                 (0x1U << ETH_MTLTXQ1LCR_LC_Pos)                     /*!< 0x00000001 */
11367 #define ETH_MTLTXQ1LCR_LC_1                 (0x2U << ETH_MTLTXQ1LCR_LC_Pos)                     /*!< 0x00000002 */
11368 #define ETH_MTLTXQ1LCR_LC_2                 (0x4U << ETH_MTLTXQ1LCR_LC_Pos)                     /*!< 0x00000004 */
11369 #define ETH_MTLTXQ1LCR_LC_3                 (0x8U << ETH_MTLTXQ1LCR_LC_Pos)                     /*!< 0x00000008 */
11370 #define ETH_MTLTXQ1LCR_LC_4                 (0x10U << ETH_MTLTXQ1LCR_LC_Pos)                    /*!< 0x00000010 */
11371 #define ETH_MTLTXQ1LCR_LC_5                 (0x20U << ETH_MTLTXQ1LCR_LC_Pos)                    /*!< 0x00000020 */
11372 #define ETH_MTLTXQ1LCR_LC_6                 (0x40U << ETH_MTLTXQ1LCR_LC_Pos)                    /*!< 0x00000040 */
11373 #define ETH_MTLTXQ1LCR_LC_7                 (0x80U << ETH_MTLTXQ1LCR_LC_Pos)                    /*!< 0x00000080 */
11374 #define ETH_MTLTXQ1LCR_LC_8                 (0x100U << ETH_MTLTXQ1LCR_LC_Pos)                   /*!< 0x00000100 */
11375 #define ETH_MTLTXQ1LCR_LC_9                 (0x200U << ETH_MTLTXQ1LCR_LC_Pos)                   /*!< 0x00000200 */
11376 #define ETH_MTLTXQ1LCR_LC_10                (0x400U << ETH_MTLTXQ1LCR_LC_Pos)                   /*!< 0x00000400 */
11377 #define ETH_MTLTXQ1LCR_LC_11                (0x800U << ETH_MTLTXQ1LCR_LC_Pos)                   /*!< 0x00000800 */
11378 #define ETH_MTLTXQ1LCR_LC_12                (0x1000U << ETH_MTLTXQ1LCR_LC_Pos)                  /*!< 0x00001000 */
11379 #define ETH_MTLTXQ1LCR_LC_13                (0x2000U << ETH_MTLTXQ1LCR_LC_Pos)                  /*!< 0x00002000 */
11380 #define ETH_MTLTXQ1LCR_LC_14                (0x4000U << ETH_MTLTXQ1LCR_LC_Pos)                  /*!< 0x00004000 */
11381 #define ETH_MTLTXQ1LCR_LC_15                (0x8000U << ETH_MTLTXQ1LCR_LC_Pos)                  /*!< 0x00008000 */
11382 #define ETH_MTLTXQ1LCR_LC_16                (0x10000U << ETH_MTLTXQ1LCR_LC_Pos)                 /*!< 0x00010000 */
11383 #define ETH_MTLTXQ1LCR_LC_17                (0x20000U << ETH_MTLTXQ1LCR_LC_Pos)                 /*!< 0x00020000 */
11384 #define ETH_MTLTXQ1LCR_LC_18                (0x40000U << ETH_MTLTXQ1LCR_LC_Pos)                 /*!< 0x00040000 */
11385 #define ETH_MTLTXQ1LCR_LC_19                (0x80000U << ETH_MTLTXQ1LCR_LC_Pos)                 /*!< 0x00080000 */
11386 #define ETH_MTLTXQ1LCR_LC_20                (0x100000U << ETH_MTLTXQ1LCR_LC_Pos)                /*!< 0x00100000 */
11387 #define ETH_MTLTXQ1LCR_LC_21                (0x200000U << ETH_MTLTXQ1LCR_LC_Pos)                /*!< 0x00200000 */
11388 #define ETH_MTLTXQ1LCR_LC_22                (0x400000U << ETH_MTLTXQ1LCR_LC_Pos)                /*!< 0x00400000 */
11389 #define ETH_MTLTXQ1LCR_LC_23                (0x800000U << ETH_MTLTXQ1LCR_LC_Pos)                /*!< 0x00800000 */
11390 #define ETH_MTLTXQ1LCR_LC_24                (0x1000000U << ETH_MTLTXQ1LCR_LC_Pos)               /*!< 0x01000000 */
11391 #define ETH_MTLTXQ1LCR_LC_25                (0x2000000U << ETH_MTLTXQ1LCR_LC_Pos)               /*!< 0x02000000 */
11392 #define ETH_MTLTXQ1LCR_LC_26                (0x4000000U << ETH_MTLTXQ1LCR_LC_Pos)               /*!< 0x04000000 */
11393 #define ETH_MTLTXQ1LCR_LC_27                (0x8000000U << ETH_MTLTXQ1LCR_LC_Pos)               /*!< 0x08000000 */
11394 #define ETH_MTLTXQ1LCR_LC_28                (0x10000000U << ETH_MTLTXQ1LCR_LC_Pos)              /*!< 0x10000000 */
11395 
11396 /*************  Bit definition for ETH_MTLQ1ICSR register  *************/
11397 #define ETH_MTLQ1ICSR_TXUNFIS_Pos           (0U)
11398 #define ETH_MTLQ1ICSR_TXUNFIS_Msk           (0x1U << ETH_MTLQ1ICSR_TXUNFIS_Pos)                 /*!< 0x00000001 */
11399 #define ETH_MTLQ1ICSR_TXUNFIS               ETH_MTLQ1ICSR_TXUNFIS_Msk                           /*!< Transmit Queue Underflow Interrupt Status */
11400 #define ETH_MTLQ1ICSR_ABPSIS_Pos            (1U)
11401 #define ETH_MTLQ1ICSR_ABPSIS_Msk            (0x1U << ETH_MTLQ1ICSR_ABPSIS_Pos)                  /*!< 0x00000002 */
11402 #define ETH_MTLQ1ICSR_ABPSIS                ETH_MTLQ1ICSR_ABPSIS_Msk                            /*!< Average Bits Per Slot Interrupt Status */
11403 #define ETH_MTLQ1ICSR_TXUIE_Pos             (8U)
11404 #define ETH_MTLQ1ICSR_TXUIE_Msk             (0x1U << ETH_MTLQ1ICSR_TXUIE_Pos)                   /*!< 0x00000100 */
11405 #define ETH_MTLQ1ICSR_TXUIE                 ETH_MTLQ1ICSR_TXUIE_Msk                             /*!< Transmit Queue Underflow Interrupt Enable */
11406 #define ETH_MTLQ1ICSR_ABPSIE_Pos            (9U)
11407 #define ETH_MTLQ1ICSR_ABPSIE_Msk            (0x1U << ETH_MTLQ1ICSR_ABPSIE_Pos)                  /*!< 0x00000200 */
11408 #define ETH_MTLQ1ICSR_ABPSIE                ETH_MTLQ1ICSR_ABPSIE_Msk                            /*!< Average Bits Per Slot Interrupt Enable */
11409 #define ETH_MTLQ1ICSR_RXOVFIS_Pos           (16U)
11410 #define ETH_MTLQ1ICSR_RXOVFIS_Msk           (0x1U << ETH_MTLQ1ICSR_RXOVFIS_Pos)                 /*!< 0x00010000 */
11411 #define ETH_MTLQ1ICSR_RXOVFIS               ETH_MTLQ1ICSR_RXOVFIS_Msk                           /*!< Receive Queue Overflow Interrupt Status */
11412 #define ETH_MTLQ1ICSR_RXOIE_Pos             (24U)
11413 #define ETH_MTLQ1ICSR_RXOIE_Msk             (0x1U << ETH_MTLQ1ICSR_RXOIE_Pos)                   /*!< 0x01000000 */
11414 #define ETH_MTLQ1ICSR_RXOIE                 ETH_MTLQ1ICSR_RXOIE_Msk                             /*!< Receive Queue Overflow Interrupt Enable */
11415 
11416 /************  Bit definition for ETH_MTLRXQ1OMR register  *************/
11417 #define ETH_MTLRXQ1OMR_RTC_Pos              (0U)
11418 #define ETH_MTLRXQ1OMR_RTC_Msk              (0x3U << ETH_MTLRXQ1OMR_RTC_Pos)                    /*!< 0x00000003 */
11419 #define ETH_MTLRXQ1OMR_RTC                  ETH_MTLRXQ1OMR_RTC_Msk                              /*!< Receive Queue Threshold Control */
11420 #define ETH_MTLRXQ1OMR_RTC_0                (0x1U << ETH_MTLRXQ1OMR_RTC_Pos)                    /*!< 0x00000001 */
11421 #define ETH_MTLRXQ1OMR_RTC_1                (0x2U << ETH_MTLRXQ1OMR_RTC_Pos)                    /*!< 0x00000002 */
11422 #define ETH_MTLRXQ1OMR_FUP_Pos              (3U)
11423 #define ETH_MTLRXQ1OMR_FUP_Msk              (0x1U << ETH_MTLRXQ1OMR_FUP_Pos)                    /*!< 0x00000008 */
11424 #define ETH_MTLRXQ1OMR_FUP                  ETH_MTLRXQ1OMR_FUP_Msk                              /*!< Forward Undersized Good Packets */
11425 #define ETH_MTLRXQ1OMR_FEP_Pos              (4U)
11426 #define ETH_MTLRXQ1OMR_FEP_Msk              (0x1U << ETH_MTLRXQ1OMR_FEP_Pos)                    /*!< 0x00000010 */
11427 #define ETH_MTLRXQ1OMR_FEP                  ETH_MTLRXQ1OMR_FEP_Msk                              /*!< Forward Error Packets */
11428 #define ETH_MTLRXQ1OMR_RSF_Pos              (5U)
11429 #define ETH_MTLRXQ1OMR_RSF_Msk              (0x1U << ETH_MTLRXQ1OMR_RSF_Pos)                    /*!< 0x00000020 */
11430 #define ETH_MTLRXQ1OMR_RSF                  ETH_MTLRXQ1OMR_RSF_Msk                              /*!< Receive Queue Store and Forward */
11431 #define ETH_MTLRXQ1OMR_DIS_TCP_EF_Pos       (6U)
11432 #define ETH_MTLRXQ1OMR_DIS_TCP_EF_Msk       (0x1U << ETH_MTLRXQ1OMR_DIS_TCP_EF_Pos)             /*!< 0x00000040 */
11433 #define ETH_MTLRXQ1OMR_DIS_TCP_EF           ETH_MTLRXQ1OMR_DIS_TCP_EF_Msk                       /*!< Disable Dropping of TCP/IP Checksum Error Packets */
11434 #define ETH_MTLRXQ1OMR_EHFC_Pos             (7U)
11435 #define ETH_MTLRXQ1OMR_EHFC_Msk             (0x1U << ETH_MTLRXQ1OMR_EHFC_Pos)                   /*!< 0x00000080 */
11436 #define ETH_MTLRXQ1OMR_EHFC                 ETH_MTLRXQ1OMR_EHFC_Msk                             /*!< Enable Hardware Flow Control */
11437 #define ETH_MTLRXQ1OMR_RFA_Pos              (8U)
11438 #define ETH_MTLRXQ1OMR_RFA_Msk              (0x7U << ETH_MTLRXQ1OMR_RFA_Pos)                    /*!< 0x00000700 */
11439 #define ETH_MTLRXQ1OMR_RFA                  ETH_MTLRXQ1OMR_RFA_Msk                              /*!< Threshold for Activating Flow Control (in half-duplex and full-duplex */
11440 #define ETH_MTLRXQ1OMR_RFA_0                (0x1U << ETH_MTLRXQ1OMR_RFA_Pos)                  /*!< 0x00000100 */
11441 #define ETH_MTLRXQ1OMR_RFA_1                (0x2U << ETH_MTLRXQ1OMR_RFA_Pos)                  /*!< 0x00000200 */
11442 #define ETH_MTLRXQ1OMR_RFA_2                (0x4U << ETH_MTLRXQ1OMR_RFA_Pos)                  /*!< 0x00000400 */
11443 #define ETH_MTLRXQ1OMR_RFD_Pos              (14U)
11444 #define ETH_MTLRXQ1OMR_RFD_Msk              (0x7U << ETH_MTLRXQ1OMR_RFD_Pos)                    /*!< 0x0001C000 */
11445 #define ETH_MTLRXQ1OMR_RFD                  ETH_MTLRXQ1OMR_RFD_Msk                              /*!< Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */
11446 #define ETH_MTLRXQ1OMR_RFD_0                (0x1U << ETH_MTLRXQ1OMR_RFD_Pos)                 /*!< 0x00004000 */
11447 #define ETH_MTLRXQ1OMR_RFD_1                (0x2U << ETH_MTLRXQ1OMR_RFD_Pos)                 /*!< 0x00008000 */
11448 #define ETH_MTLRXQ1OMR_RFD_2                (0x4U << ETH_MTLRXQ1OMR_RFD_Pos)                /*!< 0x00010000 */
11449 #define ETH_MTLRXQ1OMR_RQS_Pos              (20U)
11450 #define ETH_MTLRXQ1OMR_RQS_Msk              (0xFU << ETH_MTLRXQ1OMR_RQS_Pos)                    /*!< 0x00F00000 */
11451 #define ETH_MTLRXQ1OMR_RQS                  ETH_MTLRXQ1OMR_RQS_Msk                              /*!< Receive Queue Size */
11452 #define ETH_MTLRXQ1OMR_RQS_0                (0x1U << ETH_MTLRXQ1OMR_RQS_Pos)               /*!< 0x00100000 */
11453 #define ETH_MTLRXQ1OMR_RQS_1                (0x2U << ETH_MTLRXQ1OMR_RQS_Pos)               /*!< 0x00200000 */
11454 #define ETH_MTLRXQ1OMR_RQS_2                (0x4U << ETH_MTLRXQ1OMR_RQS_Pos)               /*!< 0x00400000 */
11455 #define ETH_MTLRXQ1OMR_RQS_3                (0x8U << ETH_MTLRXQ1OMR_RQS_Pos)               /*!< 0x00800000 */
11456 
11457 /***********  Bit definition for ETH_MTLRXQ1MPOCR register  ************/
11458 #define ETH_MTLRXQ1MPOCR_OVFPKTCNT_Pos      (0U)
11459 #define ETH_MTLRXQ1MPOCR_OVFPKTCNT_Msk      (0x7FFU << ETH_MTLRXQ1MPOCR_OVFPKTCNT_Pos)          /*!< 0x000007FF */
11460 #define ETH_MTLRXQ1MPOCR_OVFPKTCNT          ETH_MTLRXQ1MPOCR_OVFPKTCNT_Msk                      /*!< Overflow Packet Counter */
11461 #define ETH_MTLRXQ1MPOCR_OVFPKTCNT_0        (0x1U << ETH_MTLRXQ1MPOCR_OVFPKTCNT_Pos)            /*!< 0x00000001 */
11462 #define ETH_MTLRXQ1MPOCR_OVFPKTCNT_1        (0x2U << ETH_MTLRXQ1MPOCR_OVFPKTCNT_Pos)            /*!< 0x00000002 */
11463 #define ETH_MTLRXQ1MPOCR_OVFPKTCNT_2        (0x4U << ETH_MTLRXQ1MPOCR_OVFPKTCNT_Pos)            /*!< 0x00000004 */
11464 #define ETH_MTLRXQ1MPOCR_OVFPKTCNT_3        (0x8U << ETH_MTLRXQ1MPOCR_OVFPKTCNT_Pos)            /*!< 0x00000008 */
11465 #define ETH_MTLRXQ1MPOCR_OVFPKTCNT_4        (0x10U << ETH_MTLRXQ1MPOCR_OVFPKTCNT_Pos)           /*!< 0x00000010 */
11466 #define ETH_MTLRXQ1MPOCR_OVFPKTCNT_5        (0x20U << ETH_MTLRXQ1MPOCR_OVFPKTCNT_Pos)           /*!< 0x00000020 */
11467 #define ETH_MTLRXQ1MPOCR_OVFPKTCNT_6        (0x40U << ETH_MTLRXQ1MPOCR_OVFPKTCNT_Pos)           /*!< 0x00000040 */
11468 #define ETH_MTLRXQ1MPOCR_OVFPKTCNT_7        (0x80U << ETH_MTLRXQ1MPOCR_OVFPKTCNT_Pos)           /*!< 0x00000080 */
11469 #define ETH_MTLRXQ1MPOCR_OVFPKTCNT_8        (0x100U << ETH_MTLRXQ1MPOCR_OVFPKTCNT_Pos)          /*!< 0x00000100 */
11470 #define ETH_MTLRXQ1MPOCR_OVFPKTCNT_9        (0x200U << ETH_MTLRXQ1MPOCR_OVFPKTCNT_Pos)          /*!< 0x00000200 */
11471 #define ETH_MTLRXQ1MPOCR_OVFPKTCNT_10       (0x400U << ETH_MTLRXQ1MPOCR_OVFPKTCNT_Pos)          /*!< 0x00000400 */
11472 #define ETH_MTLRXQ1MPOCR_OVFCNTOVF_Pos      (11U)
11473 #define ETH_MTLRXQ1MPOCR_OVFCNTOVF_Msk      (0x1U << ETH_MTLRXQ1MPOCR_OVFCNTOVF_Pos)            /*!< 0x00000800 */
11474 #define ETH_MTLRXQ1MPOCR_OVFCNTOVF          ETH_MTLRXQ1MPOCR_OVFCNTOVF_Msk                      /*!< Overflow Counter Overflow Bit */
11475 #define ETH_MTLRXQ1MPOCR_MISPKTCNT_Pos      (16U)
11476 #define ETH_MTLRXQ1MPOCR_MISPKTCNT_Msk      (0x7FFU << ETH_MTLRXQ1MPOCR_MISPKTCNT_Pos)          /*!< 0x07FF0000 */
11477 #define ETH_MTLRXQ1MPOCR_MISPKTCNT          ETH_MTLRXQ1MPOCR_MISPKTCNT_Msk                      /*!< Missed Packet Counter */
11478 #define ETH_MTLRXQ1MPOCR_MISPKTCNT_0        (0x1U << ETH_MTLRXQ1MPOCR_MISPKTCNT_Pos)        /*!< 0x00010000 */
11479 #define ETH_MTLRXQ1MPOCR_MISPKTCNT_1        (0x2U << ETH_MTLRXQ1MPOCR_MISPKTCNT_Pos)        /*!< 0x00020000 */
11480 #define ETH_MTLRXQ1MPOCR_MISPKTCNT_2        (0x4U << ETH_MTLRXQ1MPOCR_MISPKTCNT_Pos)        /*!< 0x00040000 */
11481 #define ETH_MTLRXQ1MPOCR_MISPKTCNT_3        (0x8U << ETH_MTLRXQ1MPOCR_MISPKTCNT_Pos)        /*!< 0x00080000 */
11482 #define ETH_MTLRXQ1MPOCR_MISPKTCNT_4        (0x10U << ETH_MTLRXQ1MPOCR_MISPKTCNT_Pos)       /*!< 0x00100000 */
11483 #define ETH_MTLRXQ1MPOCR_MISPKTCNT_5        (0x20U << ETH_MTLRXQ1MPOCR_MISPKTCNT_Pos)       /*!< 0x00200000 */
11484 #define ETH_MTLRXQ1MPOCR_MISPKTCNT_6        (0x40U << ETH_MTLRXQ1MPOCR_MISPKTCNT_Pos)       /*!< 0x00400000 */
11485 #define ETH_MTLRXQ1MPOCR_MISPKTCNT_7        (0x80U << ETH_MTLRXQ1MPOCR_MISPKTCNT_Pos)       /*!< 0x00800000 */
11486 #define ETH_MTLRXQ1MPOCR_MISPKTCNT_8        (0x100U << ETH_MTLRXQ1MPOCR_MISPKTCNT_Pos)      /*!< 0x01000000 */
11487 #define ETH_MTLRXQ1MPOCR_MISPKTCNT_9        (0x200U << ETH_MTLRXQ1MPOCR_MISPKTCNT_Pos)      /*!< 0x02000000 */
11488 #define ETH_MTLRXQ1MPOCR_MISPKTCNT_10       (0x400U << ETH_MTLRXQ1MPOCR_MISPKTCNT_Pos)      /*!< 0x04000000 */
11489 #define ETH_MTLRXQ1MPOCR_MISCNTOVF_Pos      (27U)
11490 #define ETH_MTLRXQ1MPOCR_MISCNTOVF_Msk      (0x1U << ETH_MTLRXQ1MPOCR_MISCNTOVF_Pos)            /*!< 0x08000000 */
11491 #define ETH_MTLRXQ1MPOCR_MISCNTOVF          ETH_MTLRXQ1MPOCR_MISCNTOVF_Msk                      /*!< Missed Packet Counter Overflow Bit */
11492 
11493 /*************  Bit definition for ETH_MTLRXQ1DR register  *************/
11494 #define ETH_MTLRXQ1DR_RWCSTS_Pos            (0U)
11495 #define ETH_MTLRXQ1DR_RWCSTS_Msk            (0x1U << ETH_MTLRXQ1DR_RWCSTS_Pos)                  /*!< 0x00000001 */
11496 #define ETH_MTLRXQ1DR_RWCSTS                ETH_MTLRXQ1DR_RWCSTS_Msk                            /*!< MTL Rx Queue Write Controller Active Status */
11497 #define ETH_MTLRXQ1DR_RRCSTS_Pos            (1U)
11498 #define ETH_MTLRXQ1DR_RRCSTS_Msk            (0x3U << ETH_MTLRXQ1DR_RRCSTS_Pos)                  /*!< 0x00000006 */
11499 #define ETH_MTLRXQ1DR_RRCSTS                ETH_MTLRXQ1DR_RRCSTS_Msk                            /*!< MTL Rx Queue Read Controller State */
11500 #define ETH_MTLRXQ1DR_RRCSTS_0              (0x1U << ETH_MTLRXQ1DR_RRCSTS_Pos)                  /*!< 0x00000002 */
11501 #define ETH_MTLRXQ1DR_RRCSTS_1              (0x2U << ETH_MTLRXQ1DR_RRCSTS_Pos)                  /*!< 0x00000004 */
11502 #define ETH_MTLRXQ1DR_RXQSTS_Pos            (4U)
11503 #define ETH_MTLRXQ1DR_RXQSTS_Msk            (0x3U << ETH_MTLRXQ1DR_RXQSTS_Pos)                  /*!< 0x00000030 */
11504 #define ETH_MTLRXQ1DR_RXQSTS                ETH_MTLRXQ1DR_RXQSTS_Msk                            /*!< MTL Rx Queue Fill-Level Status */
11505 #define ETH_MTLRXQ1DR_RXQSTS_0              (0x1U << ETH_MTLRXQ1DR_RXQSTS_Pos)                 /*!< 0x00000010 */
11506 #define ETH_MTLRXQ1DR_RXQSTS_1              (0x2U << ETH_MTLRXQ1DR_RXQSTS_Pos)                 /*!< 0x00000020 */
11507 #define ETH_MTLRXQ1DR_PRXQ_Pos              (16U)
11508 #define ETH_MTLRXQ1DR_PRXQ_Msk              (0x3FFFU << ETH_MTLRXQ1DR_PRXQ_Pos)                 /*!< 0x3FFF0000 */
11509 #define ETH_MTLRXQ1DR_PRXQ                  ETH_MTLRXQ1DR_PRXQ_Msk                              /*!< Number of Packets in Receive Queue */
11510 #define ETH_MTLRXQ1DR_PRXQ_0                (0x1U << ETH_MTLRXQ1DR_PRXQ_Pos)                /*!< 0x00010000 */
11511 #define ETH_MTLRXQ1DR_PRXQ_1                (0x2U << ETH_MTLRXQ1DR_PRXQ_Pos)                /*!< 0x00020000 */
11512 #define ETH_MTLRXQ1DR_PRXQ_2                (0x4U << ETH_MTLRXQ1DR_PRXQ_Pos)                /*!< 0x00040000 */
11513 #define ETH_MTLRXQ1DR_PRXQ_3                (0x8U << ETH_MTLRXQ1DR_PRXQ_Pos)                /*!< 0x00080000 */
11514 #define ETH_MTLRXQ1DR_PRXQ_4                (0x10U << ETH_MTLRXQ1DR_PRXQ_Pos)               /*!< 0x00100000 */
11515 #define ETH_MTLRXQ1DR_PRXQ_5                (0x20U << ETH_MTLRXQ1DR_PRXQ_Pos)               /*!< 0x00200000 */
11516 #define ETH_MTLRXQ1DR_PRXQ_6                (0x40U << ETH_MTLRXQ1DR_PRXQ_Pos)               /*!< 0x00400000 */
11517 #define ETH_MTLRXQ1DR_PRXQ_7                (0x80U << ETH_MTLRXQ1DR_PRXQ_Pos)               /*!< 0x00800000 */
11518 #define ETH_MTLRXQ1DR_PRXQ_8                (0x100U << ETH_MTLRXQ1DR_PRXQ_Pos)              /*!< 0x01000000 */
11519 #define ETH_MTLRXQ1DR_PRXQ_9                (0x200U << ETH_MTLRXQ1DR_PRXQ_Pos)              /*!< 0x02000000 */
11520 #define ETH_MTLRXQ1DR_PRXQ_10               (0x400U << ETH_MTLRXQ1DR_PRXQ_Pos)              /*!< 0x04000000 */
11521 #define ETH_MTLRXQ1DR_PRXQ_11               (0x800U << ETH_MTLRXQ1DR_PRXQ_Pos)              /*!< 0x08000000 */
11522 #define ETH_MTLRXQ1DR_PRXQ_12               (0x1000U << ETH_MTLRXQ1DR_PRXQ_Pos)             /*!< 0x10000000 */
11523 #define ETH_MTLRXQ1DR_PRXQ_13               (0x2000U << ETH_MTLRXQ1DR_PRXQ_Pos)             /*!< 0x20000000 */
11524 
11525 /*************  Bit definition for ETH_MTLRXQ1CR register  *************/
11526 #define ETH_MTLRXQ1CR_RXQ_WEGT_Pos          (0U)
11527 #define ETH_MTLRXQ1CR_RXQ_WEGT_Msk          (0x7U << ETH_MTLRXQ1CR_RXQ_WEGT_Pos)                /*!< 0x00000007 */
11528 #define ETH_MTLRXQ1CR_RXQ_WEGT              ETH_MTLRXQ1CR_RXQ_WEGT_Msk                          /*!< Receive Queue Weight */
11529 #define ETH_MTLRXQ1CR_RXQ_WEGT_0            (0x1U << ETH_MTLRXQ1CR_RXQ_WEGT_Pos)                /*!< 0x00000001 */
11530 #define ETH_MTLRXQ1CR_RXQ_WEGT_1            (0x2U << ETH_MTLRXQ1CR_RXQ_WEGT_Pos)                /*!< 0x00000002 */
11531 #define ETH_MTLRXQ1CR_RXQ_WEGT_2            (0x4U << ETH_MTLRXQ1CR_RXQ_WEGT_Pos)                /*!< 0x00000004 */
11532 #define ETH_MTLRXQ1CR_RXQ_FRM_ARBIT_Pos     (3U)
11533 #define ETH_MTLRXQ1CR_RXQ_FRM_ARBIT_Msk     (0x1U << ETH_MTLRXQ1CR_RXQ_FRM_ARBIT_Pos)           /*!< 0x00000008 */
11534 #define ETH_MTLRXQ1CR_RXQ_FRM_ARBIT         ETH_MTLRXQ1CR_RXQ_FRM_ARBIT_Msk                     /*!< Receive Queue Packet Arbitration */
11535 
11536 /***************  Bit definition for ETH_DMAMR register  ***************/
11537 #define ETH_DMAMR_SWR_Pos                   (0U)
11538 #define ETH_DMAMR_SWR_Msk                   (0x1U << ETH_DMAMR_SWR_Pos)                         /*!< 0x00000001 */
11539 #define ETH_DMAMR_SWR                       ETH_DMAMR_SWR_Msk                                   /*!< Software Reset */
11540 #define ETH_DMAMR_TAA_Pos                   (2U)
11541 #define ETH_DMAMR_TAA_Msk                   (0x7U << ETH_DMAMR_TAA_Pos)                         /*!< 0x0000001C */
11542 #define ETH_DMAMR_TAA                       ETH_DMAMR_TAA_Msk                                   /*!< Transmit Arbitration Algorithm */
11543 #define ETH_DMAMR_TAA_0                     (0x1U << ETH_DMAMR_TAA_Pos)                         /*!< 0x00000004 */
11544 #define ETH_DMAMR_TAA_1                     (0x2U << ETH_DMAMR_TAA_Pos)                         /*!< 0x00000008 */
11545 #define ETH_DMAMR_TAA_2                     (0x4U << ETH_DMAMR_TAA_Pos)                        /*!< 0x00000010 */
11546 #define ETH_DMAMR_TXPR_Pos                  (11U)
11547 #define ETH_DMAMR_TXPR_Msk                  (0x1U << ETH_DMAMR_TXPR_Pos)                        /*!< 0x00000800 */
11548 #define ETH_DMAMR_TXPR                      ETH_DMAMR_TXPR_Msk                                  /*!< Transmit priority */
11549 #define ETH_DMAMR_PR_Pos                    (12U)
11550 #define ETH_DMAMR_PR_Msk                    (0x7U << ETH_DMAMR_PR_Pos)                          /*!< 0x00007000 */
11551 #define ETH_DMAMR_PR                        ETH_DMAMR_PR_Msk                                    /*!< Priority ratio */
11552 #define ETH_DMAMR_PR_0                      (0x1U << ETH_DMAMR_PR_Pos)                       /*!< 0x00001000 */
11553 #define ETH_DMAMR_PR_1                      (0x2U << ETH_DMAMR_PR_Pos)                       /*!< 0x00002000 */
11554 #define ETH_DMAMR_PR_2                      (0x4U << ETH_DMAMR_PR_Pos)                       /*!< 0x00004000 */
11555 #define ETH_DMAMR_INTM_Pos                  (16U)
11556 #define ETH_DMAMR_INTM_Msk                  (0x3U << ETH_DMAMR_INTM_Pos)                        /*!< 0x00030000 */
11557 #define ETH_DMAMR_INTM                      ETH_DMAMR_INTM_Msk                                  /*!< Interrupt Mode */
11558 #define ETH_DMAMR_INTM_0                    (0x1U << ETH_DMAMR_INTM_Pos)                    /*!< 0x00010000 */
11559 #define ETH_DMAMR_INTM_1                    (0x2U << ETH_DMAMR_INTM_Pos)                    /*!< 0x00020000 */
11560 
11561 /**************  Bit definition for ETH_DMASBMR register  **************/
11562 #define ETH_DMASBMR_FB_Pos                  (0U)
11563 #define ETH_DMASBMR_FB_Msk                  (0x1U << ETH_DMASBMR_FB_Pos)                        /*!< 0x00000001 */
11564 #define ETH_DMASBMR_FB                      ETH_DMASBMR_FB_Msk                                  /*!< Fixed Burst Length */
11565 #define ETH_DMASBMR_BLEN4_Pos               (1U)
11566 #define ETH_DMASBMR_BLEN4_Msk               (0x1U << ETH_DMASBMR_BLEN4_Pos)                     /*!< 0x00000002 */
11567 #define ETH_DMASBMR_BLEN4                   ETH_DMASBMR_BLEN4_Msk                               /*!< AXI Burst Length 4 */
11568 #define ETH_DMASBMR_BLEN8_Pos               (2U)
11569 #define ETH_DMASBMR_BLEN8_Msk               (0x1U << ETH_DMASBMR_BLEN8_Pos)                     /*!< 0x00000004 */
11570 #define ETH_DMASBMR_BLEN8                   ETH_DMASBMR_BLEN8_Msk                               /*!< AXI Burst Length 8 */
11571 #define ETH_DMASBMR_BLEN16_Pos              (3U)
11572 #define ETH_DMASBMR_BLEN16_Msk              (0x1U << ETH_DMASBMR_BLEN16_Pos)                    /*!< 0x00000008 */
11573 #define ETH_DMASBMR_BLEN16                  ETH_DMASBMR_BLEN16_Msk                              /*!< AXI Burst Length 16 */
11574 #define ETH_DMASBMR_BLEN32_Pos              (4U)
11575 #define ETH_DMASBMR_BLEN32_Msk              (0x1U << ETH_DMASBMR_BLEN32_Pos)                    /*!< 0x00000010 */
11576 #define ETH_DMASBMR_BLEN32                  ETH_DMASBMR_BLEN32_Msk                              /*!< AXI Burst Length 32 */
11577 #define ETH_DMASBMR_BLEN64_Pos              (5U)
11578 #define ETH_DMASBMR_BLEN64_Msk              (0x1U << ETH_DMASBMR_BLEN64_Pos)                    /*!< 0x00000020 */
11579 #define ETH_DMASBMR_BLEN64                  ETH_DMASBMR_BLEN64_Msk                              /*!< AXI Burst Length 64 */
11580 #define ETH_DMASBMR_BLEN128_Pos             (6U)
11581 #define ETH_DMASBMR_BLEN128_Msk             (0x1U << ETH_DMASBMR_BLEN128_Pos)                   /*!< 0x00000040 */
11582 #define ETH_DMASBMR_BLEN128                 ETH_DMASBMR_BLEN128_Msk                             /*!< AXI Burst Length 128 */
11583 #define ETH_DMASBMR_BLEN256_Pos             (7U)
11584 #define ETH_DMASBMR_BLEN256_Msk             (0x1U << ETH_DMASBMR_BLEN256_Pos)                   /*!< 0x00000080 */
11585 #define ETH_DMASBMR_BLEN256                 ETH_DMASBMR_BLEN256_Msk                             /*!< AXI Burst Length 256 */
11586 #define ETH_DMASBMR_AAL_Pos                 (12U)
11587 #define ETH_DMASBMR_AAL_Msk                 (0x1U << ETH_DMASBMR_AAL_Pos)                       /*!< 0x00001000 */
11588 #define ETH_DMASBMR_AAL                     ETH_DMASBMR_AAL_Msk                                 /*!< Address-Aligned Beats */
11589 #define ETH_DMASBMR_ONEKBBE_Pos             (13U)
11590 #define ETH_DMASBMR_ONEKBBE_Msk             (0x1U << ETH_DMASBMR_ONEKBBE_Pos)                   /*!< 0x00002000 */
11591 #define ETH_DMASBMR_ONEKBBE                 ETH_DMASBMR_ONEKBBE_Msk                             /*!< 1 Kbyte Boundary Crossing Enable for the AXI Master */
11592 #define ETH_DMASBMR_RD_OSR_LMT_Pos          (16U)
11593 #define ETH_DMASBMR_RD_OSR_LMT_Msk          (0x3U << ETH_DMASBMR_RD_OSR_LMT_Pos)                /*!< 0x00030000 */
11594 #define ETH_DMASBMR_RD_OSR_LMT              ETH_DMASBMR_RD_OSR_LMT_Msk                          /*!< AXI Maximum Read Outstanding Request Limit */
11595 #define ETH_DMASBMR_RD_OSR_LMT_0            (0x1U << ETH_DMASBMR_RD_OSR_LMT_Pos)            /*!< 0x00010000 */
11596 #define ETH_DMASBMR_RD_OSR_LMT_1            (0x2U << ETH_DMASBMR_RD_OSR_LMT_Pos)            /*!< 0x00020000 */
11597 #define ETH_DMASBMR_WR_OSR_LMT_Pos          (24U)
11598 #define ETH_DMASBMR_WR_OSR_LMT_Msk          (0x3U << ETH_DMASBMR_WR_OSR_LMT_Pos)                /*!< 0x03000000 */
11599 #define ETH_DMASBMR_WR_OSR_LMT              ETH_DMASBMR_WR_OSR_LMT_Msk                          /*!< AXI Maximum Write Outstanding Request Limit */
11600 #define ETH_DMASBMR_WR_OSR_LMT_0            (0x1U << ETH_DMASBMR_WR_OSR_LMT_Pos)          /*!< 0x01000000 */
11601 #define ETH_DMASBMR_WR_OSR_LMT_1            (0x2U << ETH_DMASBMR_WR_OSR_LMT_Pos)          /*!< 0x02000000 */
11602 #define ETH_DMASBMR_LPI_XIT_PKT_Pos         (30U)
11603 #define ETH_DMASBMR_LPI_XIT_PKT_Msk         (0x1U << ETH_DMASBMR_LPI_XIT_PKT_Pos)               /*!< 0x40000000 */
11604 #define ETH_DMASBMR_LPI_XIT_PKT             ETH_DMASBMR_LPI_XIT_PKT_Msk                         /*!< Unlock on Magic Packet or Remote wakeup Packet */
11605 #define ETH_DMASBMR_EN_LPI_Pos              (31U)
11606 #define ETH_DMASBMR_EN_LPI_Msk              (0x1U << ETH_DMASBMR_EN_LPI_Pos)                    /*!< 0x80000000 */
11607 #define ETH_DMASBMR_EN_LPI                  ETH_DMASBMR_EN_LPI_Msk                              /*!< Enable Low Power Interface (LPI) */
11608 
11609 /**************  Bit definition for ETH_DMAISR register  ***************/
11610 #define ETH_DMAISR_DC0IS_Pos                (0U)
11611 #define ETH_DMAISR_DC0IS_Msk                (0x1U << ETH_DMAISR_DC0IS_Pos)                      /*!< 0x00000001 */
11612 #define ETH_DMAISR_DC0IS                    ETH_DMAISR_DC0IS_Msk                                /*!< DMA Channel 0 Interrupt Status */
11613 #define ETH_DMAISR_DC1IS_Pos                (1U)
11614 #define ETH_DMAISR_DC1IS_Msk                (0x1U << ETH_DMAISR_DC1IS_Pos)                      /*!< 0x00000002 */
11615 #define ETH_DMAISR_DC1IS                    ETH_DMAISR_DC1IS_Msk                                /*!< DMA Channel 1 Interrupt Status */
11616 #define ETH_DMAISR_MTLIS_Pos                (16U)
11617 #define ETH_DMAISR_MTLIS_Msk                (0x1U << ETH_DMAISR_MTLIS_Pos)                      /*!< 0x00010000 */
11618 #define ETH_DMAISR_MTLIS                    ETH_DMAISR_MTLIS_Msk                                /*!< MTL Interrupt Status */
11619 #define ETH_DMAISR_MACIS_Pos                (17U)
11620 #define ETH_DMAISR_MACIS_Msk                (0x1U << ETH_DMAISR_MACIS_Pos)                      /*!< 0x00020000 */
11621 #define ETH_DMAISR_MACIS                    ETH_DMAISR_MACIS_Msk                                /*!< MAC Interrupt Status */
11622 
11623 /**************  Bit definition for ETH_DMADSR register  ***************/
11624 #define ETH_DMADSR_AXWHSTS_Pos              (0U)
11625 #define ETH_DMADSR_AXWHSTS_Msk              (0x1U << ETH_DMADSR_AXWHSTS_Pos)                    /*!< 0x00000001 */
11626 #define ETH_DMADSR_AXWHSTS                  ETH_DMADSR_AXWHSTS_Msk                              /*!< AXI Master Write Channel */
11627 #define ETH_DMADSR_AXRHSTS_Pos              (1U)
11628 #define ETH_DMADSR_AXRHSTS_Msk              (0x1U << ETH_DMADSR_AXRHSTS_Pos)                    /*!< 0x00000002 */
11629 #define ETH_DMADSR_AXRHSTS                  ETH_DMADSR_AXRHSTS_Msk                              /*!< AXI Master Read Channel Status */
11630 #define ETH_DMADSR_RPS0_Pos                 (8U)
11631 #define ETH_DMADSR_RPS0_Msk                 (0xFU << ETH_DMADSR_RPS0_Pos)                       /*!< 0x00000F00 */
11632 #define ETH_DMADSR_RPS0                     ETH_DMADSR_RPS0_Msk                                 /*!< DMA Channel 0 Receive Process State */
11633 #define ETH_DMADSR_RPS0_0                   (0x1U << ETH_DMADSR_RPS0_Pos)                     /*!< 0x00000100 */
11634 #define ETH_DMADSR_RPS0_1                   (0x2U << ETH_DMADSR_RPS0_Pos)                     /*!< 0x00000200 */
11635 #define ETH_DMADSR_RPS0_2                   (0x4U << ETH_DMADSR_RPS0_Pos)                     /*!< 0x00000400 */
11636 #define ETH_DMADSR_RPS0_3                   (0x8U << ETH_DMADSR_RPS0_Pos)                     /*!< 0x00000800 */
11637 #define ETH_DMADSR_TPS0_Pos                 (12U)
11638 #define ETH_DMADSR_TPS0_Msk                 (0xFU << ETH_DMADSR_TPS0_Pos)                       /*!< 0x0000F000 */
11639 #define ETH_DMADSR_TPS0                     ETH_DMADSR_TPS0_Msk                                 /*!< DMA Channel 0 Transmit Process State */
11640 #define ETH_DMADSR_TPS0_0                   (0x1U << ETH_DMADSR_TPS0_Pos)                    /*!< 0x00001000 */
11641 #define ETH_DMADSR_TPS0_1                   (0x2U << ETH_DMADSR_TPS0_Pos)                    /*!< 0x00002000 */
11642 #define ETH_DMADSR_TPS0_2                   (0x4U << ETH_DMADSR_TPS0_Pos)                    /*!< 0x00004000 */
11643 #define ETH_DMADSR_TPS0_3                   (0x8U << ETH_DMADSR_TPS0_Pos)                    /*!< 0x00008000 */
11644 #define ETH_DMADSR_RPS1_Pos                 (16U)
11645 #define ETH_DMADSR_RPS1_Msk                 (0xFU << ETH_DMADSR_RPS1_Pos)                       /*!< 0x000F0000 */
11646 #define ETH_DMADSR_RPS1                     ETH_DMADSR_RPS1_Msk                                 /*!< DMA Channel 1 Receive Process State */
11647 #define ETH_DMADSR_RPS1_0                   (0x1U << ETH_DMADSR_RPS1_Pos)                   /*!< 0x00010000 */
11648 #define ETH_DMADSR_RPS1_1                   (0x2U << ETH_DMADSR_RPS1_Pos)                   /*!< 0x00020000 */
11649 #define ETH_DMADSR_RPS1_2                   (0x4U << ETH_DMADSR_RPS1_Pos)                   /*!< 0x00040000 */
11650 #define ETH_DMADSR_RPS1_3                   (0x8U << ETH_DMADSR_RPS1_Pos)                   /*!< 0x00080000 */
11651 #define ETH_DMADSR_TPS1_Pos                 (20U)
11652 #define ETH_DMADSR_TPS1_Msk                 (0xFU << ETH_DMADSR_TPS1_Pos)                       /*!< 0x00F00000 */
11653 #define ETH_DMADSR_TPS1                     ETH_DMADSR_TPS1_Msk                                 /*!< DMA Channel 1 Transmit Process State */
11654 #define ETH_DMADSR_TPS1_0                   (0x1U << ETH_DMADSR_TPS1_Pos)                  /*!< 0x00100000 */
11655 #define ETH_DMADSR_TPS1_1                   (0x2U << ETH_DMADSR_TPS1_Pos)                  /*!< 0x00200000 */
11656 #define ETH_DMADSR_TPS1_2                   (0x4U << ETH_DMADSR_TPS1_Pos)                  /*!< 0x00400000 */
11657 #define ETH_DMADSR_TPS1_3                   (0x8U << ETH_DMADSR_TPS1_Pos)                  /*!< 0x00800000 */
11658 
11659 /************  Bit definition for ETH_DMAA4TXACR register  *************/
11660 #define ETH_DMAA4TXACR_TDRC_Pos             (0U)
11661 #define ETH_DMAA4TXACR_TDRC_Msk             (0xFU << ETH_DMAA4TXACR_TDRC_Pos)                   /*!< 0x0000000F */
11662 #define ETH_DMAA4TXACR_TDRC                 ETH_DMAA4TXACR_TDRC_Msk                             /*!< Transmit DMA Read Descriptor Cache Control */
11663 #define ETH_DMAA4TXACR_TDRC_0               (0x1U << ETH_DMAA4TXACR_TDRC_Pos)                   /*!< 0x00000001 */
11664 #define ETH_DMAA4TXACR_TDRC_1               (0x2U << ETH_DMAA4TXACR_TDRC_Pos)                   /*!< 0x00000002 */
11665 #define ETH_DMAA4TXACR_TDRC_2               (0x4U << ETH_DMAA4TXACR_TDRC_Pos)                   /*!< 0x00000004 */
11666 #define ETH_DMAA4TXACR_TDRC_3               (0x8U << ETH_DMAA4TXACR_TDRC_Pos)                   /*!< 0x00000008 */
11667 #define ETH_DMAA4TXACR_TEC_Pos              (8U)
11668 #define ETH_DMAA4TXACR_TEC_Msk              (0xFU << ETH_DMAA4TXACR_TEC_Pos)                    /*!< 0x00000F00 */
11669 #define ETH_DMAA4TXACR_TEC                  ETH_DMAA4TXACR_TEC_Msk                              /*!< Transmit DMA Extended Packet Buffer or TSO Payload Cache Control */
11670 #define ETH_DMAA4TXACR_TEC_0                (0x1U << ETH_DMAA4TXACR_TEC_Pos)                  /*!< 0x00000100 */
11671 #define ETH_DMAA4TXACR_TEC_1                (0x2U << ETH_DMAA4TXACR_TEC_Pos)                  /*!< 0x00000200 */
11672 #define ETH_DMAA4TXACR_TEC_2                (0x4U << ETH_DMAA4TXACR_TEC_Pos)                  /*!< 0x00000400 */
11673 #define ETH_DMAA4TXACR_TEC_3                (0x8U << ETH_DMAA4TXACR_TEC_Pos)                  /*!< 0x00000800 */
11674 #define ETH_DMAA4TXACR_THC_Pos              (16U)
11675 #define ETH_DMAA4TXACR_THC_Msk              (0xFU << ETH_DMAA4TXACR_THC_Pos)                    /*!< 0x000F0000 */
11676 #define ETH_DMAA4TXACR_THC                  ETH_DMAA4TXACR_THC_Msk                              /*!< Transmit DMA First Packet Buffer or TSO Header Cache Control */
11677 #define ETH_DMAA4TXACR_THC_0                (0x1U << ETH_DMAA4TXACR_THC_Pos)                /*!< 0x00010000 */
11678 #define ETH_DMAA4TXACR_THC_1                (0x2U << ETH_DMAA4TXACR_THC_Pos)                /*!< 0x00020000 */
11679 #define ETH_DMAA4TXACR_THC_2                (0x4U << ETH_DMAA4TXACR_THC_Pos)                /*!< 0x00040000 */
11680 #define ETH_DMAA4TXACR_THC_3                (0x8U << ETH_DMAA4TXACR_THC_Pos)                /*!< 0x00080000 */
11681 
11682 /************  Bit definition for ETH_DMAA4RXACR register  *************/
11683 #define ETH_DMAA4RXACR_RDWC_Pos             (0U)
11684 #define ETH_DMAA4RXACR_RDWC_Msk             (0xFU << ETH_DMAA4RXACR_RDWC_Pos)                   /*!< 0x0000000F */
11685 #define ETH_DMAA4RXACR_RDWC                 ETH_DMAA4RXACR_RDWC_Msk                             /*!< Receive DMA Write Descriptor Cache Control */
11686 #define ETH_DMAA4RXACR_RDWC_0               (0x1U << ETH_DMAA4RXACR_RDWC_Pos)                   /*!< 0x00000001 */
11687 #define ETH_DMAA4RXACR_RDWC_1               (0x2U << ETH_DMAA4RXACR_RDWC_Pos)                   /*!< 0x00000002 */
11688 #define ETH_DMAA4RXACR_RDWC_2               (0x4U << ETH_DMAA4RXACR_RDWC_Pos)                   /*!< 0x00000004 */
11689 #define ETH_DMAA4RXACR_RDWC_3               (0x8U << ETH_DMAA4RXACR_RDWC_Pos)                   /*!< 0x00000008 */
11690 #define ETH_DMAA4RXACR_RPC_Pos              (8U)
11691 #define ETH_DMAA4RXACR_RPC_Msk              (0xFU << ETH_DMAA4RXACR_RPC_Pos)                    /*!< 0x00000F00 */
11692 #define ETH_DMAA4RXACR_RPC                  ETH_DMAA4RXACR_RPC_Msk                              /*!< Receive DMA Payload Cache Control */
11693 #define ETH_DMAA4RXACR_RPC_0                (0x1U << ETH_DMAA4RXACR_RPC_Pos)                  /*!< 0x00000100 */
11694 #define ETH_DMAA4RXACR_RPC_1                (0x2U << ETH_DMAA4RXACR_RPC_Pos)                  /*!< 0x00000200 */
11695 #define ETH_DMAA4RXACR_RPC_2                (0x4U << ETH_DMAA4RXACR_RPC_Pos)                  /*!< 0x00000400 */
11696 #define ETH_DMAA4RXACR_RPC_3                (0x8U << ETH_DMAA4RXACR_RPC_Pos)                  /*!< 0x00000800 */
11697 #define ETH_DMAA4RXACR_RHC_Pos              (16U)
11698 #define ETH_DMAA4RXACR_RHC_Msk              (0xFU << ETH_DMAA4RXACR_RHC_Pos)                    /*!< 0x000F0000 */
11699 #define ETH_DMAA4RXACR_RHC                  ETH_DMAA4RXACR_RHC_Msk                              /*!< Receive DMA Header Cache Control */
11700 #define ETH_DMAA4RXACR_RHC_0                (0x1U << ETH_DMAA4RXACR_RHC_Pos)                /*!< 0x00010000 */
11701 #define ETH_DMAA4RXACR_RHC_1                (0x2U << ETH_DMAA4RXACR_RHC_Pos)                /*!< 0x00020000 */
11702 #define ETH_DMAA4RXACR_RHC_2                (0x4U << ETH_DMAA4RXACR_RHC_Pos)                /*!< 0x00040000 */
11703 #define ETH_DMAA4RXACR_RHC_3                (0x8U << ETH_DMAA4RXACR_RHC_Pos)                /*!< 0x00080000 */
11704 #define ETH_DMAA4RXACR_RDC_Pos              (24U)
11705 #define ETH_DMAA4RXACR_RDC_Msk              (0xFU << ETH_DMAA4RXACR_RDC_Pos)                    /*!< 0x0F000000 */
11706 #define ETH_DMAA4RXACR_RDC                  ETH_DMAA4RXACR_RDC_Msk                              /*!< Receive DMA Buffer Cache Control */
11707 #define ETH_DMAA4RXACR_RDC_0                (0x1U << ETH_DMAA4RXACR_RDC_Pos)              /*!< 0x01000000 */
11708 #define ETH_DMAA4RXACR_RDC_1                (0x2U << ETH_DMAA4RXACR_RDC_Pos)              /*!< 0x02000000 */
11709 #define ETH_DMAA4RXACR_RDC_2                (0x4U << ETH_DMAA4RXACR_RDC_Pos)              /*!< 0x04000000 */
11710 #define ETH_DMAA4RXACR_RDC_3                (0x8U << ETH_DMAA4RXACR_RDC_Pos)              /*!< 0x08000000 */
11711 
11712 /*************  Bit definition for ETH_DMAA4DACR register  *************/
11713 #define ETH_DMAA4DACR_TDWC_Pos              (0U)
11714 #define ETH_DMAA4DACR_TDWC_Msk              (0xFU << ETH_DMAA4DACR_TDWC_Pos)                    /*!< 0x0000000F */
11715 #define ETH_DMAA4DACR_TDWC                  ETH_DMAA4DACR_TDWC_Msk                              /*!< Transmit DMA Write Descriptor Cache control */
11716 #define ETH_DMAA4DACR_TDWC_0                (0x1U << ETH_DMAA4DACR_TDWC_Pos)                    /*!< 0x00000001 */
11717 #define ETH_DMAA4DACR_TDWC_1                (0x2U << ETH_DMAA4DACR_TDWC_Pos)                    /*!< 0x00000002 */
11718 #define ETH_DMAA4DACR_TDWC_2                (0x4U << ETH_DMAA4DACR_TDWC_Pos)                    /*!< 0x00000004 */
11719 #define ETH_DMAA4DACR_TDWC_3                (0x8U << ETH_DMAA4DACR_TDWC_Pos)                    /*!< 0x00000008 */
11720 #define ETH_DMAA4DACR_TDWD_Pos              (4U)
11721 #define ETH_DMAA4DACR_TDWD_Msk              (0x3U << ETH_DMAA4DACR_TDWD_Pos)                    /*!< 0x00000030 */
11722 #define ETH_DMAA4DACR_TDWD                  ETH_DMAA4DACR_TDWD_Msk                              /*!< Transmit DMA Write Descriptor Domain control */
11723 #define ETH_DMAA4DACR_TDWD_0                (0x1U << ETH_DMAA4DACR_TDWD_Pos)                   /*!< 0x00000010 */
11724 #define ETH_DMAA4DACR_TDWD_1                (0x2U << ETH_DMAA4DACR_TDWD_Pos)                   /*!< 0x00000020 */
11725 #define ETH_DMAA4DACR_RDRC_Pos              (8U)
11726 #define ETH_DMAA4DACR_RDRC_Msk              (0xFU << ETH_DMAA4DACR_RDRC_Pos)                    /*!< 0x00000F00 */
11727 #define ETH_DMAA4DACR_RDRC                  ETH_DMAA4DACR_RDRC_Msk                              /*!< Receive DMA Read Descriptor Cache control */
11728 #define ETH_DMAA4DACR_RDRC_0                (0x1U << ETH_DMAA4DACR_RDRC_Pos)                  /*!< 0x00000100 */
11729 #define ETH_DMAA4DACR_RDRC_1                (0x2U << ETH_DMAA4DACR_RDRC_Pos)                  /*!< 0x00000200 */
11730 #define ETH_DMAA4DACR_RDRC_2                (0x4U << ETH_DMAA4DACR_RDRC_Pos)                  /*!< 0x00000400 */
11731 #define ETH_DMAA4DACR_RDRC_3                (0x8U << ETH_DMAA4DACR_RDRC_Pos)                  /*!< 0x00000800 */
11732 
11733 /**************  Bit definition for ETH_DMAC0CR register  **************/
11734 #define ETH_DMAC0CR_MSS_Pos                 (0U)
11735 #define ETH_DMAC0CR_MSS_Msk                 (0x3FFFU << ETH_DMAC0CR_MSS_Pos)                    /*!< 0x00003FFF */
11736 #define ETH_DMAC0CR_MSS                     ETH_DMAC0CR_MSS_Msk                                 /*!< Maximum Segment Size */
11737 #define ETH_DMAC0CR_MSS_0                   (0x1U << ETH_DMAC0CR_MSS_Pos)                       /*!< 0x00000001 */
11738 #define ETH_DMAC0CR_MSS_1                   (0x2U << ETH_DMAC0CR_MSS_Pos)                       /*!< 0x00000002 */
11739 #define ETH_DMAC0CR_MSS_2                   (0x4U << ETH_DMAC0CR_MSS_Pos)                       /*!< 0x00000004 */
11740 #define ETH_DMAC0CR_MSS_3                   (0x8U << ETH_DMAC0CR_MSS_Pos)                       /*!< 0x00000008 */
11741 #define ETH_DMAC0CR_MSS_4                   (0x10U << ETH_DMAC0CR_MSS_Pos)                      /*!< 0x00000010 */
11742 #define ETH_DMAC0CR_MSS_5                   (0x20U << ETH_DMAC0CR_MSS_Pos)                      /*!< 0x00000020 */
11743 #define ETH_DMAC0CR_MSS_6                   (0x40U << ETH_DMAC0CR_MSS_Pos)                      /*!< 0x00000040 */
11744 #define ETH_DMAC0CR_MSS_7                   (0x80U << ETH_DMAC0CR_MSS_Pos)                      /*!< 0x00000080 */
11745 #define ETH_DMAC0CR_MSS_8                   (0x100U << ETH_DMAC0CR_MSS_Pos)                     /*!< 0x00000100 */
11746 #define ETH_DMAC0CR_MSS_9                   (0x200U << ETH_DMAC0CR_MSS_Pos)                     /*!< 0x00000200 */
11747 #define ETH_DMAC0CR_MSS_10                  (0x400U << ETH_DMAC0CR_MSS_Pos)                     /*!< 0x00000400 */
11748 #define ETH_DMAC0CR_MSS_11                  (0x800U << ETH_DMAC0CR_MSS_Pos)                     /*!< 0x00000800 */
11749 #define ETH_DMAC0CR_MSS_12                  (0x1000U << ETH_DMAC0CR_MSS_Pos)                    /*!< 0x00001000 */
11750 #define ETH_DMAC0CR_MSS_13                  (0x2000U << ETH_DMAC0CR_MSS_Pos)                    /*!< 0x00002000 */
11751 #define ETH_DMAC0CR_PBLX8_Pos               (16U)
11752 #define ETH_DMAC0CR_PBLX8_Msk               (0x1U << ETH_DMAC0CR_PBLX8_Pos)                     /*!< 0x00010000 */
11753 #define ETH_DMAC0CR_PBLX8                   ETH_DMAC0CR_PBLX8_Msk                               /*!< 8xPBL mode */
11754 #define ETH_DMAC0CR_DSL_Pos                 (18U)
11755 #define ETH_DMAC0CR_DSL_Msk                 (0x7U << ETH_DMAC0CR_DSL_Pos)                       /*!< 0x001C0000 */
11756 #define ETH_DMAC0CR_DSL                     ETH_DMAC0CR_DSL_Msk                                 /*!< Descriptor Skip Length */
11757 #define ETH_DMAC0CR_DSL_0                   (0x1U << ETH_DMAC0CR_DSL_Pos)                   /*!< 0x00040000 */
11758 #define ETH_DMAC0CR_DSL_1                   (0x2U << ETH_DMAC0CR_DSL_Pos)                   /*!< 0x00080000 */
11759 #define ETH_DMAC0CR_DSL_2                   (0x4U << ETH_DMAC0CR_DSL_Pos)                  /*!< 0x00100000 */
11760 
11761 /*************  Bit definition for ETH_DMAC0TXCR register  *************/
11762 #define ETH_DMAC0TXCR_ST_Pos                (0U)
11763 #define ETH_DMAC0TXCR_ST_Msk                (0x1U << ETH_DMAC0TXCR_ST_Pos)                      /*!< 0x00000001 */
11764 #define ETH_DMAC0TXCR_ST                    ETH_DMAC0TXCR_ST_Msk                                /*!< Start or Stop Transmission Command */
11765 #define ETH_DMAC0TXCR_TCW_Pos               (1U)
11766 #define ETH_DMAC0TXCR_TCW_Msk               (0x7U << ETH_DMAC0TXCR_TCW_Pos)                     /*!< 0x0000000E */
11767 #define ETH_DMAC0TXCR_TCW                   ETH_DMAC0TXCR_TCW_Msk                               /*!< Transmit Channel Weight */
11768 #define ETH_DMAC0TXCR_TCW_0                 (0x1U << ETH_DMAC0TXCR_TCW_Pos)                     /*!< 0x00000002 */
11769 #define ETH_DMAC0TXCR_TCW_1                 (0x2U << ETH_DMAC0TXCR_TCW_Pos)                     /*!< 0x00000004 */
11770 #define ETH_DMAC0TXCR_TCW_2                 (0x4U << ETH_DMAC0TXCR_TCW_Pos)                     /*!< 0x00000008 */
11771 #define ETH_DMAC0TXCR_OSF_Pos               (4U)
11772 #define ETH_DMAC0TXCR_OSF_Msk               (0x1U << ETH_DMAC0TXCR_OSF_Pos)                     /*!< 0x00000010 */
11773 #define ETH_DMAC0TXCR_OSF                   ETH_DMAC0TXCR_OSF_Msk                               /*!< Operate on Second Packet */
11774 #define ETH_DMAC0TXCR_TSE_Pos               (12U)
11775 #define ETH_DMAC0TXCR_TSE_Msk               (0x1U << ETH_DMAC0TXCR_TSE_Pos)                     /*!< 0x00001000 */
11776 #define ETH_DMAC0TXCR_TSE                   ETH_DMAC0TXCR_TSE_Msk                               /*!< TCP Segmentation Enabled */
11777 #define ETH_DMAC0TXCR_TXPBL_Pos             (16U)
11778 #define ETH_DMAC0TXCR_TXPBL_Msk             (0x3FU << ETH_DMAC0TXCR_TXPBL_Pos)                  /*!< 0x003F0000 */
11779 #define ETH_DMAC0TXCR_TXPBL                 ETH_DMAC0TXCR_TXPBL_Msk                             /*!< Transmit Programmable Burst Length */
11780 #define ETH_DMAC0TXCR_TXPBL_0               (0x1U << ETH_DMAC0TXCR_TXPBL_Pos)               /*!< 0x00010000 */
11781 #define ETH_DMAC0TXCR_TXPBL_1               (0x2U << ETH_DMAC0TXCR_TXPBL_Pos)               /*!< 0x00020000 */
11782 #define ETH_DMAC0TXCR_TXPBL_2               (0x4U << ETH_DMAC0TXCR_TXPBL_Pos)               /*!< 0x00040000 */
11783 #define ETH_DMAC0TXCR_TXPBL_3               (0x8U << ETH_DMAC0TXCR_TXPBL_Pos)               /*!< 0x00080000 */
11784 #define ETH_DMAC0TXCR_TXPBL_4               (0x10U << ETH_DMAC0TXCR_TXPBL_Pos)              /*!< 0x00100000 */
11785 #define ETH_DMAC0TXCR_TXPBL_5               (0x20U << ETH_DMAC0TXCR_TXPBL_Pos)              /*!< 0x00200000 */
11786 #define ETH_DMAC0TXCR_TQOS_Pos              (24U)
11787 #define ETH_DMAC0TXCR_TQOS_Msk              (0xFU << ETH_DMAC0TXCR_TQOS_Pos)                    /*!< 0x0F000000 */
11788 #define ETH_DMAC0TXCR_TQOS                  ETH_DMAC0TXCR_TQOS_Msk                              /*!< Transmit QOS. */
11789 #define ETH_DMAC0TXCR_TQOS_0                (0x1U << ETH_DMAC0TXCR_TQOS_Pos)              /*!< 0x01000000 */
11790 #define ETH_DMAC0TXCR_TQOS_1                (0x2U << ETH_DMAC0TXCR_TQOS_Pos)              /*!< 0x02000000 */
11791 #define ETH_DMAC0TXCR_TQOS_2                (0x4U << ETH_DMAC0TXCR_TQOS_Pos)              /*!< 0x04000000 */
11792 #define ETH_DMAC0TXCR_TQOS_3                (0x8U << ETH_DMAC0TXCR_TQOS_Pos)              /*!< 0x08000000 */
11793 
11794 /*************  Bit definition for ETH_DMAC0RXCR register  *************/
11795 #define ETH_DMAC0RXCR_SR_Pos                (0U)
11796 #define ETH_DMAC0RXCR_SR_Msk                (0x1U << ETH_DMAC0RXCR_SR_Pos)                      /*!< 0x00000001 */
11797 #define ETH_DMAC0RXCR_SR                    ETH_DMAC0RXCR_SR_Msk                                /*!< Start or Stop Receive */
11798 #define ETH_DMAC0RXCR_RBSZ_Pos              (1U)
11799 #define ETH_DMAC0RXCR_RBSZ_Msk              (0x3FFFU << ETH_DMAC0RXCR_RBSZ_Pos)                 /*!< 0x00007FFE */
11800 #define ETH_DMAC0RXCR_RBSZ                  ETH_DMAC0RXCR_RBSZ_Msk                              /*!< Receive Buffer size */
11801 #define ETH_DMAC0RXCR_RBSZ_0                (0x1U << ETH_DMAC0RXCR_RBSZ_Pos)                    /*!< 0x00000002 */
11802 #define ETH_DMAC0RXCR_RBSZ_1                (0x2U << ETH_DMAC0RXCR_RBSZ_Pos)                    /*!< 0x00000004 */
11803 #define ETH_DMAC0RXCR_RBSZ_2                (0x4U << ETH_DMAC0RXCR_RBSZ_Pos)                    /*!< 0x00000008 */
11804 #define ETH_DMAC0RXCR_RBSZ_3                (0x8U << ETH_DMAC0RXCR_RBSZ_Pos)                   /*!< 0x00000010 */
11805 #define ETH_DMAC0RXCR_RBSZ_4                (0x10U << ETH_DMAC0RXCR_RBSZ_Pos)                   /*!< 0x00000020 */
11806 #define ETH_DMAC0RXCR_RBSZ_5                (0x20U << ETH_DMAC0RXCR_RBSZ_Pos)                   /*!< 0x00000040 */
11807 #define ETH_DMAC0RXCR_RBSZ_6                (0x40U << ETH_DMAC0RXCR_RBSZ_Pos)                   /*!< 0x00000080 */
11808 #define ETH_DMAC0RXCR_RBSZ_7                (0x80U << ETH_DMAC0RXCR_RBSZ_Pos)                  /*!< 0x00000100 */
11809 #define ETH_DMAC0RXCR_RBSZ_8                (0x100U << ETH_DMAC0RXCR_RBSZ_Pos)                  /*!< 0x00000200 */
11810 #define ETH_DMAC0RXCR_RBSZ_9                (0x200U << ETH_DMAC0RXCR_RBSZ_Pos)                  /*!< 0x00000400 */
11811 #define ETH_DMAC0RXCR_RBSZ_10               (0x400U << ETH_DMAC0RXCR_RBSZ_Pos)                  /*!< 0x00000800 */
11812 #define ETH_DMAC0RXCR_RBSZ_11               (0x800U << ETH_DMAC0RXCR_RBSZ_Pos)                 /*!< 0x00001000 */
11813 #define ETH_DMAC0RXCR_RBSZ_12               (0x1000U << ETH_DMAC0RXCR_RBSZ_Pos)                 /*!< 0x00002000 */
11814 #define ETH_DMAC0RXCR_RBSZ_13               (0x2000U << ETH_DMAC0RXCR_RBSZ_Pos)                 /*!< 0x00004000 */
11815 #define ETH_DMAC0RXCR_RXPBL_Pos             (16U)
11816 #define ETH_DMAC0RXCR_RXPBL_Msk             (0x3FU << ETH_DMAC0RXCR_RXPBL_Pos)                  /*!< 0x003F0000 */
11817 #define ETH_DMAC0RXCR_RXPBL                 ETH_DMAC0RXCR_RXPBL_Msk                             /*!< Receive Programmable Burst Length */
11818 #define ETH_DMAC0RXCR_RXPBL_0               (0x1U << ETH_DMAC0RXCR_RXPBL_Pos)               /*!< 0x00010000 */
11819 #define ETH_DMAC0RXCR_RXPBL_1               (0x2U << ETH_DMAC0RXCR_RXPBL_Pos)               /*!< 0x00020000 */
11820 #define ETH_DMAC0RXCR_RXPBL_2               (0x4U << ETH_DMAC0RXCR_RXPBL_Pos)               /*!< 0x00040000 */
11821 #define ETH_DMAC0RXCR_RXPBL_3               (0x8U << ETH_DMAC0RXCR_RXPBL_Pos)               /*!< 0x00080000 */
11822 #define ETH_DMAC0RXCR_RXPBL_4               (0x10U << ETH_DMAC0RXCR_RXPBL_Pos)              /*!< 0x00100000 */
11823 #define ETH_DMAC0RXCR_RXPBL_5               (0x20U << ETH_DMAC0RXCR_RXPBL_Pos)              /*!< 0x00200000 */
11824 #define ETH_DMAC0RXCR_RQOS_Pos              (24U)
11825 #define ETH_DMAC0RXCR_RQOS_Msk              (0xFU << ETH_DMAC0RXCR_RQOS_Pos)                    /*!< 0x0F000000 */
11826 #define ETH_DMAC0RXCR_RQOS                  ETH_DMAC0RXCR_RQOS_Msk                              /*!< Rx AXI4 QOS. */
11827 #define ETH_DMAC0RXCR_RQOS_0                (0x1U << ETH_DMAC0RXCR_RQOS_Pos)              /*!< 0x01000000 */
11828 #define ETH_DMAC0RXCR_RQOS_1                (0x2U << ETH_DMAC0RXCR_RQOS_Pos)              /*!< 0x02000000 */
11829 #define ETH_DMAC0RXCR_RQOS_2                (0x4U << ETH_DMAC0RXCR_RQOS_Pos)              /*!< 0x04000000 */
11830 #define ETH_DMAC0RXCR_RQOS_3                (0x8U << ETH_DMAC0RXCR_RQOS_Pos)              /*!< 0x08000000 */
11831 #define ETH_DMAC0RXCR_RPF_Pos               (31U)
11832 #define ETH_DMAC0RXCR_RPF_Msk               (0x1U << ETH_DMAC0RXCR_RPF_Pos)                     /*!< 0x80000000 */
11833 #define ETH_DMAC0RXCR_RPF                   ETH_DMAC0RXCR_RPF_Msk                               /*!< DMA Rx Channel0 Packet Flush */
11834 
11835 /************  Bit definition for ETH_DMAC0TXDLAR register  ************/
11836 #define ETH_DMAC0TXDLAR_TDESLA_Pos          (3U)
11837 #define ETH_DMAC0TXDLAR_TDESLA_Msk          (0x1FFFFFFFU << ETH_DMAC0TXDLAR_TDESLA_Pos)         /*!< 0xFFFFFFF8 */
11838 #define ETH_DMAC0TXDLAR_TDESLA              ETH_DMAC0TXDLAR_TDESLA_Msk                          /*!< Start of Transmit List */
11839 #define ETH_DMAC0TXDLAR_TDESLA_0            (0x1U << ETH_DMAC0TXDLAR_TDESLA_Pos)                /*!< 0x00000008 */
11840 #define ETH_DMAC0TXDLAR_TDESLA_1            (0x2U << ETH_DMAC0TXDLAR_TDESLA_Pos)               /*!< 0x00000010 */
11841 #define ETH_DMAC0TXDLAR_TDESLA_2            (0x4U << ETH_DMAC0TXDLAR_TDESLA_Pos)               /*!< 0x00000020 */
11842 #define ETH_DMAC0TXDLAR_TDESLA_3            (0x8U << ETH_DMAC0TXDLAR_TDESLA_Pos)               /*!< 0x00000040 */
11843 #define ETH_DMAC0TXDLAR_TDESLA_4            (0x10U << ETH_DMAC0TXDLAR_TDESLA_Pos)               /*!< 0x00000080 */
11844 #define ETH_DMAC0TXDLAR_TDESLA_5            (0x20U << ETH_DMAC0TXDLAR_TDESLA_Pos)              /*!< 0x00000100 */
11845 #define ETH_DMAC0TXDLAR_TDESLA_6            (0x40U << ETH_DMAC0TXDLAR_TDESLA_Pos)              /*!< 0x00000200 */
11846 #define ETH_DMAC0TXDLAR_TDESLA_7            (0x80U << ETH_DMAC0TXDLAR_TDESLA_Pos)              /*!< 0x00000400 */
11847 #define ETH_DMAC0TXDLAR_TDESLA_8            (0x100U << ETH_DMAC0TXDLAR_TDESLA_Pos)              /*!< 0x00000800 */
11848 #define ETH_DMAC0TXDLAR_TDESLA_9            (0x200U << ETH_DMAC0TXDLAR_TDESLA_Pos)             /*!< 0x00001000 */
11849 #define ETH_DMAC0TXDLAR_TDESLA_10           (0x400U << ETH_DMAC0TXDLAR_TDESLA_Pos)             /*!< 0x00002000 */
11850 #define ETH_DMAC0TXDLAR_TDESLA_11           (0x800U << ETH_DMAC0TXDLAR_TDESLA_Pos)             /*!< 0x00004000 */
11851 #define ETH_DMAC0TXDLAR_TDESLA_12           (0x1000U << ETH_DMAC0TXDLAR_TDESLA_Pos)             /*!< 0x00008000 */
11852 #define ETH_DMAC0TXDLAR_TDESLA_13           (0x2000U << ETH_DMAC0TXDLAR_TDESLA_Pos)            /*!< 0x00010000 */
11853 #define ETH_DMAC0TXDLAR_TDESLA_14           (0x4000U << ETH_DMAC0TXDLAR_TDESLA_Pos)            /*!< 0x00020000 */
11854 #define ETH_DMAC0TXDLAR_TDESLA_15           (0x8000U << ETH_DMAC0TXDLAR_TDESLA_Pos)            /*!< 0x00040000 */
11855 #define ETH_DMAC0TXDLAR_TDESLA_16           (0x10000U << ETH_DMAC0TXDLAR_TDESLA_Pos)            /*!< 0x00080000 */
11856 #define ETH_DMAC0TXDLAR_TDESLA_17           (0x20000U << ETH_DMAC0TXDLAR_TDESLA_Pos)           /*!< 0x00100000 */
11857 #define ETH_DMAC0TXDLAR_TDESLA_18           (0x40000U << ETH_DMAC0TXDLAR_TDESLA_Pos)           /*!< 0x00200000 */
11858 #define ETH_DMAC0TXDLAR_TDESLA_19           (0x80000U << ETH_DMAC0TXDLAR_TDESLA_Pos)           /*!< 0x00400000 */
11859 #define ETH_DMAC0TXDLAR_TDESLA_20           (0x100000U << ETH_DMAC0TXDLAR_TDESLA_Pos)           /*!< 0x00800000 */
11860 #define ETH_DMAC0TXDLAR_TDESLA_21           (0x200000U << ETH_DMAC0TXDLAR_TDESLA_Pos)          /*!< 0x01000000 */
11861 #define ETH_DMAC0TXDLAR_TDESLA_22           (0x400000U << ETH_DMAC0TXDLAR_TDESLA_Pos)          /*!< 0x02000000 */
11862 #define ETH_DMAC0TXDLAR_TDESLA_23           (0x800000U << ETH_DMAC0TXDLAR_TDESLA_Pos)          /*!< 0x04000000 */
11863 #define ETH_DMAC0TXDLAR_TDESLA_24           (0x1000000U << ETH_DMAC0TXDLAR_TDESLA_Pos)          /*!< 0x08000000 */
11864 #define ETH_DMAC0TXDLAR_TDESLA_25           (0x2000000U << ETH_DMAC0TXDLAR_TDESLA_Pos)         /*!< 0x10000000 */
11865 #define ETH_DMAC0TXDLAR_TDESLA_26           (0x4000000U << ETH_DMAC0TXDLAR_TDESLA_Pos)         /*!< 0x20000000 */
11866 #define ETH_DMAC0TXDLAR_TDESLA_27           (0x8000000U << ETH_DMAC0TXDLAR_TDESLA_Pos)         /*!< 0x40000000 */
11867 #define ETH_DMAC0TXDLAR_TDESLA_28           (0x10000000U << ETH_DMAC0TXDLAR_TDESLA_Pos)         /*!< 0x80000000 */
11868 
11869 /************  Bit definition for ETH_DMAC0RXDLAR register  ************/
11870 #define ETH_DMAC0RXDLAR_RDESLA_Pos          (3U)
11871 #define ETH_DMAC0RXDLAR_RDESLA_Msk          (0x1FFFFFFFU << ETH_DMAC0RXDLAR_RDESLA_Pos)         /*!< 0xFFFFFFF8 */
11872 #define ETH_DMAC0RXDLAR_RDESLA              ETH_DMAC0RXDLAR_RDESLA_Msk                          /*!< Start of Receive List */
11873 #define ETH_DMAC0RXDLAR_RDESLA_0            (0x1U << ETH_DMAC0RXDLAR_RDESLA_Pos)                /*!< 0x00000008 */
11874 #define ETH_DMAC0RXDLAR_RDESLA_1            (0x2U << ETH_DMAC0RXDLAR_RDESLA_Pos)               /*!< 0x00000010 */
11875 #define ETH_DMAC0RXDLAR_RDESLA_2            (0x4U << ETH_DMAC0RXDLAR_RDESLA_Pos)               /*!< 0x00000020 */
11876 #define ETH_DMAC0RXDLAR_RDESLA_3            (0x8U << ETH_DMAC0RXDLAR_RDESLA_Pos)               /*!< 0x00000040 */
11877 #define ETH_DMAC0RXDLAR_RDESLA_4            (0x10U << ETH_DMAC0RXDLAR_RDESLA_Pos)               /*!< 0x00000080 */
11878 #define ETH_DMAC0RXDLAR_RDESLA_5            (0x20U << ETH_DMAC0RXDLAR_RDESLA_Pos)              /*!< 0x00000100 */
11879 #define ETH_DMAC0RXDLAR_RDESLA_6            (0x40U << ETH_DMAC0RXDLAR_RDESLA_Pos)              /*!< 0x00000200 */
11880 #define ETH_DMAC0RXDLAR_RDESLA_7            (0x80U << ETH_DMAC0RXDLAR_RDESLA_Pos)              /*!< 0x00000400 */
11881 #define ETH_DMAC0RXDLAR_RDESLA_8            (0x100U << ETH_DMAC0RXDLAR_RDESLA_Pos)              /*!< 0x00000800 */
11882 #define ETH_DMAC0RXDLAR_RDESLA_9            (0x200U << ETH_DMAC0RXDLAR_RDESLA_Pos)             /*!< 0x00001000 */
11883 #define ETH_DMAC0RXDLAR_RDESLA_10           (0x400U << ETH_DMAC0RXDLAR_RDESLA_Pos)             /*!< 0x00002000 */
11884 #define ETH_DMAC0RXDLAR_RDESLA_11           (0x800U << ETH_DMAC0RXDLAR_RDESLA_Pos)             /*!< 0x00004000 */
11885 #define ETH_DMAC0RXDLAR_RDESLA_12           (0x1000U << ETH_DMAC0RXDLAR_RDESLA_Pos)             /*!< 0x00008000 */
11886 #define ETH_DMAC0RXDLAR_RDESLA_13           (0x2000U << ETH_DMAC0RXDLAR_RDESLA_Pos)            /*!< 0x00010000 */
11887 #define ETH_DMAC0RXDLAR_RDESLA_14           (0x4000U << ETH_DMAC0RXDLAR_RDESLA_Pos)            /*!< 0x00020000 */
11888 #define ETH_DMAC0RXDLAR_RDESLA_15           (0x8000U << ETH_DMAC0RXDLAR_RDESLA_Pos)            /*!< 0x00040000 */
11889 #define ETH_DMAC0RXDLAR_RDESLA_16           (0x10000U << ETH_DMAC0RXDLAR_RDESLA_Pos)            /*!< 0x00080000 */
11890 #define ETH_DMAC0RXDLAR_RDESLA_17           (0x20000U << ETH_DMAC0RXDLAR_RDESLA_Pos)           /*!< 0x00100000 */
11891 #define ETH_DMAC0RXDLAR_RDESLA_18           (0x40000U << ETH_DMAC0RXDLAR_RDESLA_Pos)           /*!< 0x00200000 */
11892 #define ETH_DMAC0RXDLAR_RDESLA_19           (0x80000U << ETH_DMAC0RXDLAR_RDESLA_Pos)           /*!< 0x00400000 */
11893 #define ETH_DMAC0RXDLAR_RDESLA_20           (0x100000U << ETH_DMAC0RXDLAR_RDESLA_Pos)           /*!< 0x00800000 */
11894 #define ETH_DMAC0RXDLAR_RDESLA_21           (0x200000U << ETH_DMAC0RXDLAR_RDESLA_Pos)          /*!< 0x01000000 */
11895 #define ETH_DMAC0RXDLAR_RDESLA_22           (0x400000U << ETH_DMAC0RXDLAR_RDESLA_Pos)          /*!< 0x02000000 */
11896 #define ETH_DMAC0RXDLAR_RDESLA_23           (0x800000U << ETH_DMAC0RXDLAR_RDESLA_Pos)          /*!< 0x04000000 */
11897 #define ETH_DMAC0RXDLAR_RDESLA_24           (0x1000000U << ETH_DMAC0RXDLAR_RDESLA_Pos)          /*!< 0x08000000 */
11898 #define ETH_DMAC0RXDLAR_RDESLA_25           (0x2000000U << ETH_DMAC0RXDLAR_RDESLA_Pos)         /*!< 0x10000000 */
11899 #define ETH_DMAC0RXDLAR_RDESLA_26           (0x4000000U << ETH_DMAC0RXDLAR_RDESLA_Pos)         /*!< 0x20000000 */
11900 #define ETH_DMAC0RXDLAR_RDESLA_27           (0x8000000U << ETH_DMAC0RXDLAR_RDESLA_Pos)         /*!< 0x40000000 */
11901 #define ETH_DMAC0RXDLAR_RDESLA_28           (0x10000000U << ETH_DMAC0RXDLAR_RDESLA_Pos)         /*!< 0x80000000 */
11902 
11903 /************  Bit definition for ETH_DMAC0TXDTPR register  ************/
11904 #define ETH_DMAC0TXDTPR_TDT_Pos             (3U)
11905 #define ETH_DMAC0TXDTPR_TDT_Msk             (0x1FFFFFFFU << ETH_DMAC0TXDTPR_TDT_Pos)            /*!< 0xFFFFFFF8 */
11906 #define ETH_DMAC0TXDTPR_TDT                 ETH_DMAC0TXDTPR_TDT_Msk                             /*!< Transmit Descriptor Tail Pointer */
11907 #define ETH_DMAC0TXDTPR_TDT_0               (0x1U << ETH_DMAC0TXDTPR_TDT_Pos)                   /*!< 0x00000008 */
11908 #define ETH_DMAC0TXDTPR_TDT_1               (0x2U << ETH_DMAC0TXDTPR_TDT_Pos)                  /*!< 0x00000010 */
11909 #define ETH_DMAC0TXDTPR_TDT_2               (0x4U << ETH_DMAC0TXDTPR_TDT_Pos)                  /*!< 0x00000020 */
11910 #define ETH_DMAC0TXDTPR_TDT_3               (0x8U << ETH_DMAC0TXDTPR_TDT_Pos)                  /*!< 0x00000040 */
11911 #define ETH_DMAC0TXDTPR_TDT_4               (0x10U << ETH_DMAC0TXDTPR_TDT_Pos)                  /*!< 0x00000080 */
11912 #define ETH_DMAC0TXDTPR_TDT_5               (0x20U << ETH_DMAC0TXDTPR_TDT_Pos)                 /*!< 0x00000100 */
11913 #define ETH_DMAC0TXDTPR_TDT_6               (0x40U << ETH_DMAC0TXDTPR_TDT_Pos)                 /*!< 0x00000200 */
11914 #define ETH_DMAC0TXDTPR_TDT_7               (0x80U << ETH_DMAC0TXDTPR_TDT_Pos)                 /*!< 0x00000400 */
11915 #define ETH_DMAC0TXDTPR_TDT_8               (0x100U << ETH_DMAC0TXDTPR_TDT_Pos)                 /*!< 0x00000800 */
11916 #define ETH_DMAC0TXDTPR_TDT_9               (0x200U << ETH_DMAC0TXDTPR_TDT_Pos)                /*!< 0x00001000 */
11917 #define ETH_DMAC0TXDTPR_TDT_10              (0x400U << ETH_DMAC0TXDTPR_TDT_Pos)                /*!< 0x00002000 */
11918 #define ETH_DMAC0TXDTPR_TDT_11              (0x800U << ETH_DMAC0TXDTPR_TDT_Pos)                /*!< 0x00004000 */
11919 #define ETH_DMAC0TXDTPR_TDT_12              (0x1000U << ETH_DMAC0TXDTPR_TDT_Pos)                /*!< 0x00008000 */
11920 #define ETH_DMAC0TXDTPR_TDT_13              (0x2000U << ETH_DMAC0TXDTPR_TDT_Pos)               /*!< 0x00010000 */
11921 #define ETH_DMAC0TXDTPR_TDT_14              (0x4000U << ETH_DMAC0TXDTPR_TDT_Pos)               /*!< 0x00020000 */
11922 #define ETH_DMAC0TXDTPR_TDT_15              (0x8000U << ETH_DMAC0TXDTPR_TDT_Pos)               /*!< 0x00040000 */
11923 #define ETH_DMAC0TXDTPR_TDT_16              (0x10000U << ETH_DMAC0TXDTPR_TDT_Pos)               /*!< 0x00080000 */
11924 #define ETH_DMAC0TXDTPR_TDT_17              (0x20000U << ETH_DMAC0TXDTPR_TDT_Pos)              /*!< 0x00100000 */
11925 #define ETH_DMAC0TXDTPR_TDT_18              (0x40000U << ETH_DMAC0TXDTPR_TDT_Pos)              /*!< 0x00200000 */
11926 #define ETH_DMAC0TXDTPR_TDT_19              (0x80000U << ETH_DMAC0TXDTPR_TDT_Pos)              /*!< 0x00400000 */
11927 #define ETH_DMAC0TXDTPR_TDT_20              (0x100000U << ETH_DMAC0TXDTPR_TDT_Pos)              /*!< 0x00800000 */
11928 #define ETH_DMAC0TXDTPR_TDT_21              (0x200000U << ETH_DMAC0TXDTPR_TDT_Pos)             /*!< 0x01000000 */
11929 #define ETH_DMAC0TXDTPR_TDT_22              (0x400000U << ETH_DMAC0TXDTPR_TDT_Pos)             /*!< 0x02000000 */
11930 #define ETH_DMAC0TXDTPR_TDT_23              (0x800000U << ETH_DMAC0TXDTPR_TDT_Pos)             /*!< 0x04000000 */
11931 #define ETH_DMAC0TXDTPR_TDT_24              (0x1000000U << ETH_DMAC0TXDTPR_TDT_Pos)             /*!< 0x08000000 */
11932 #define ETH_DMAC0TXDTPR_TDT_25              (0x2000000U << ETH_DMAC0TXDTPR_TDT_Pos)            /*!< 0x10000000 */
11933 #define ETH_DMAC0TXDTPR_TDT_26              (0x4000000U << ETH_DMAC0TXDTPR_TDT_Pos)            /*!< 0x20000000 */
11934 #define ETH_DMAC0TXDTPR_TDT_27              (0x8000000U << ETH_DMAC0TXDTPR_TDT_Pos)            /*!< 0x40000000 */
11935 #define ETH_DMAC0TXDTPR_TDT_28              (0x10000000U << ETH_DMAC0TXDTPR_TDT_Pos)            /*!< 0x80000000 */
11936 
11937 /************  Bit definition for ETH_DMAC0RXDTPR register  ************/
11938 #define ETH_DMAC0RXDTPR_RDT_Pos             (3U)
11939 #define ETH_DMAC0RXDTPR_RDT_Msk             (0x1FFFFFFFU << ETH_DMAC0RXDTPR_RDT_Pos)            /*!< 0xFFFFFFF8 */
11940 #define ETH_DMAC0RXDTPR_RDT                 ETH_DMAC0RXDTPR_RDT_Msk                             /*!< Receive Descriptor Tail Pointer */
11941 #define ETH_DMAC0RXDTPR_RDT_0               (0x1U << ETH_DMAC0RXDTPR_RDT_Pos)                   /*!< 0x00000008 */
11942 #define ETH_DMAC0RXDTPR_RDT_1               (0x2U << ETH_DMAC0RXDTPR_RDT_Pos)                  /*!< 0x00000010 */
11943 #define ETH_DMAC0RXDTPR_RDT_2               (0x4U << ETH_DMAC0RXDTPR_RDT_Pos)                  /*!< 0x00000020 */
11944 #define ETH_DMAC0RXDTPR_RDT_3               (0x8U << ETH_DMAC0RXDTPR_RDT_Pos)                  /*!< 0x00000040 */
11945 #define ETH_DMAC0RXDTPR_RDT_4               (0x10U << ETH_DMAC0RXDTPR_RDT_Pos)                  /*!< 0x00000080 */
11946 #define ETH_DMAC0RXDTPR_RDT_5               (0x20U << ETH_DMAC0RXDTPR_RDT_Pos)                 /*!< 0x00000100 */
11947 #define ETH_DMAC0RXDTPR_RDT_6               (0x40U << ETH_DMAC0RXDTPR_RDT_Pos)                 /*!< 0x00000200 */
11948 #define ETH_DMAC0RXDTPR_RDT_7               (0x80U << ETH_DMAC0RXDTPR_RDT_Pos)                 /*!< 0x00000400 */
11949 #define ETH_DMAC0RXDTPR_RDT_8               (0x100U << ETH_DMAC0RXDTPR_RDT_Pos)                 /*!< 0x00000800 */
11950 #define ETH_DMAC0RXDTPR_RDT_9               (0x200U << ETH_DMAC0RXDTPR_RDT_Pos)                /*!< 0x00001000 */
11951 #define ETH_DMAC0RXDTPR_RDT_10              (0x400U << ETH_DMAC0RXDTPR_RDT_Pos)                /*!< 0x00002000 */
11952 #define ETH_DMAC0RXDTPR_RDT_11              (0x800U << ETH_DMAC0RXDTPR_RDT_Pos)                /*!< 0x00004000 */
11953 #define ETH_DMAC0RXDTPR_RDT_12              (0x1000U << ETH_DMAC0RXDTPR_RDT_Pos)                /*!< 0x00008000 */
11954 #define ETH_DMAC0RXDTPR_RDT_13              (0x2000U << ETH_DMAC0RXDTPR_RDT_Pos)               /*!< 0x00010000 */
11955 #define ETH_DMAC0RXDTPR_RDT_14              (0x4000U << ETH_DMAC0RXDTPR_RDT_Pos)               /*!< 0x00020000 */
11956 #define ETH_DMAC0RXDTPR_RDT_15              (0x8000U << ETH_DMAC0RXDTPR_RDT_Pos)               /*!< 0x00040000 */
11957 #define ETH_DMAC0RXDTPR_RDT_16              (0x10000U << ETH_DMAC0RXDTPR_RDT_Pos)               /*!< 0x00080000 */
11958 #define ETH_DMAC0RXDTPR_RDT_17              (0x20000U << ETH_DMAC0RXDTPR_RDT_Pos)              /*!< 0x00100000 */
11959 #define ETH_DMAC0RXDTPR_RDT_18              (0x40000U << ETH_DMAC0RXDTPR_RDT_Pos)              /*!< 0x00200000 */
11960 #define ETH_DMAC0RXDTPR_RDT_19              (0x80000U << ETH_DMAC0RXDTPR_RDT_Pos)              /*!< 0x00400000 */
11961 #define ETH_DMAC0RXDTPR_RDT_20              (0x100000U << ETH_DMAC0RXDTPR_RDT_Pos)              /*!< 0x00800000 */
11962 #define ETH_DMAC0RXDTPR_RDT_21              (0x200000U << ETH_DMAC0RXDTPR_RDT_Pos)             /*!< 0x01000000 */
11963 #define ETH_DMAC0RXDTPR_RDT_22              (0x400000U << ETH_DMAC0RXDTPR_RDT_Pos)             /*!< 0x02000000 */
11964 #define ETH_DMAC0RXDTPR_RDT_23              (0x800000U << ETH_DMAC0RXDTPR_RDT_Pos)             /*!< 0x04000000 */
11965 #define ETH_DMAC0RXDTPR_RDT_24              (0x1000000U << ETH_DMAC0RXDTPR_RDT_Pos)             /*!< 0x08000000 */
11966 #define ETH_DMAC0RXDTPR_RDT_25              (0x2000000U << ETH_DMAC0RXDTPR_RDT_Pos)            /*!< 0x10000000 */
11967 #define ETH_DMAC0RXDTPR_RDT_26              (0x4000000U << ETH_DMAC0RXDTPR_RDT_Pos)            /*!< 0x20000000 */
11968 #define ETH_DMAC0RXDTPR_RDT_27              (0x8000000U << ETH_DMAC0RXDTPR_RDT_Pos)            /*!< 0x40000000 */
11969 #define ETH_DMAC0RXDTPR_RDT_28              (0x10000000U << ETH_DMAC0RXDTPR_RDT_Pos)            /*!< 0x80000000 */
11970 
11971 /************  Bit definition for ETH_DMAC0TXRLR register  *************/
11972 #define ETH_DMAC0TXRLR_TDRL_Pos             (0U)
11973 #define ETH_DMAC0TXRLR_TDRL_Msk             (0x3FFU << ETH_DMAC0TXRLR_TDRL_Pos)                 /*!< 0x000003FF */
11974 #define ETH_DMAC0TXRLR_TDRL                 ETH_DMAC0TXRLR_TDRL_Msk                             /*!< Transmit Descriptor Ring Length */
11975 #define ETH_DMAC0TXRLR_TDRL_0               (0x1U << ETH_DMAC0TXRLR_TDRL_Pos)                   /*!< 0x00000001 */
11976 #define ETH_DMAC0TXRLR_TDRL_1               (0x2U << ETH_DMAC0TXRLR_TDRL_Pos)                   /*!< 0x00000002 */
11977 #define ETH_DMAC0TXRLR_TDRL_2               (0x4U << ETH_DMAC0TXRLR_TDRL_Pos)                   /*!< 0x00000004 */
11978 #define ETH_DMAC0TXRLR_TDRL_3               (0x8U << ETH_DMAC0TXRLR_TDRL_Pos)                   /*!< 0x00000008 */
11979 #define ETH_DMAC0TXRLR_TDRL_4               (0x10U << ETH_DMAC0TXRLR_TDRL_Pos)                  /*!< 0x00000010 */
11980 #define ETH_DMAC0TXRLR_TDRL_5               (0x20U << ETH_DMAC0TXRLR_TDRL_Pos)                  /*!< 0x00000020 */
11981 #define ETH_DMAC0TXRLR_TDRL_6               (0x40U << ETH_DMAC0TXRLR_TDRL_Pos)                  /*!< 0x00000040 */
11982 #define ETH_DMAC0TXRLR_TDRL_7               (0x80U << ETH_DMAC0TXRLR_TDRL_Pos)                  /*!< 0x00000080 */
11983 #define ETH_DMAC0TXRLR_TDRL_8               (0x100U << ETH_DMAC0TXRLR_TDRL_Pos)                 /*!< 0x00000100 */
11984 #define ETH_DMAC0TXRLR_TDRL_9               (0x200U << ETH_DMAC0TXRLR_TDRL_Pos)                 /*!< 0x00000200 */
11985 
11986 /************  Bit definition for ETH_DMAC0RXRLR register  *************/
11987 #define ETH_DMAC0RXRLR_RDRL_Pos             (0U)
11988 #define ETH_DMAC0RXRLR_RDRL_Msk             (0x3FFU << ETH_DMAC0RXRLR_RDRL_Pos)                 /*!< 0x000003FF */
11989 #define ETH_DMAC0RXRLR_RDRL                 ETH_DMAC0RXRLR_RDRL_Msk                             /*!< Receive Descriptor Ring Length */
11990 #define ETH_DMAC0RXRLR_RDRL_0               (0x1U << ETH_DMAC0RXRLR_RDRL_Pos)                   /*!< 0x00000001 */
11991 #define ETH_DMAC0RXRLR_RDRL_1               (0x2U << ETH_DMAC0RXRLR_RDRL_Pos)                   /*!< 0x00000002 */
11992 #define ETH_DMAC0RXRLR_RDRL_2               (0x4U << ETH_DMAC0RXRLR_RDRL_Pos)                   /*!< 0x00000004 */
11993 #define ETH_DMAC0RXRLR_RDRL_3               (0x8U << ETH_DMAC0RXRLR_RDRL_Pos)                   /*!< 0x00000008 */
11994 #define ETH_DMAC0RXRLR_RDRL_4               (0x10U << ETH_DMAC0RXRLR_RDRL_Pos)                  /*!< 0x00000010 */
11995 #define ETH_DMAC0RXRLR_RDRL_5               (0x20U << ETH_DMAC0RXRLR_RDRL_Pos)                  /*!< 0x00000020 */
11996 #define ETH_DMAC0RXRLR_RDRL_6               (0x40U << ETH_DMAC0RXRLR_RDRL_Pos)                  /*!< 0x00000040 */
11997 #define ETH_DMAC0RXRLR_RDRL_7               (0x80U << ETH_DMAC0RXRLR_RDRL_Pos)                  /*!< 0x00000080 */
11998 #define ETH_DMAC0RXRLR_RDRL_8               (0x100U << ETH_DMAC0RXRLR_RDRL_Pos)                 /*!< 0x00000100 */
11999 #define ETH_DMAC0RXRLR_RDRL_9               (0x200U << ETH_DMAC0RXRLR_RDRL_Pos)                 /*!< 0x00000200 */
12000 
12001 /*************  Bit definition for ETH_DMAC0IER register  **************/
12002 #define ETH_DMAC0IER_TIE_Pos                (0U)
12003 #define ETH_DMAC0IER_TIE_Msk                (0x1U << ETH_DMAC0IER_TIE_Pos)                      /*!< 0x00000001 */
12004 #define ETH_DMAC0IER_TIE                    ETH_DMAC0IER_TIE_Msk                                /*!< Transmit Interrupt Enable */
12005 #define ETH_DMAC0IER_TXSE_Pos               (1U)
12006 #define ETH_DMAC0IER_TXSE_Msk               (0x1U << ETH_DMAC0IER_TXSE_Pos)                     /*!< 0x00000002 */
12007 #define ETH_DMAC0IER_TXSE                   ETH_DMAC0IER_TXSE_Msk                               /*!< Transmit Stopped Enable */
12008 #define ETH_DMAC0IER_TBUE_Pos               (2U)
12009 #define ETH_DMAC0IER_TBUE_Msk               (0x1U << ETH_DMAC0IER_TBUE_Pos)                     /*!< 0x00000004 */
12010 #define ETH_DMAC0IER_TBUE                   ETH_DMAC0IER_TBUE_Msk                               /*!< Transmit Buffer Unavailable Enable */
12011 #define ETH_DMAC0IER_RIE_Pos                (6U)
12012 #define ETH_DMAC0IER_RIE_Msk                (0x1U << ETH_DMAC0IER_RIE_Pos)                      /*!< 0x00000040 */
12013 #define ETH_DMAC0IER_RIE                    ETH_DMAC0IER_RIE_Msk                                /*!< Receive Interrupt Enable */
12014 #define ETH_DMAC0IER_RBUE_Pos               (7U)
12015 #define ETH_DMAC0IER_RBUE_Msk               (0x1U << ETH_DMAC0IER_RBUE_Pos)                     /*!< 0x00000080 */
12016 #define ETH_DMAC0IER_RBUE                   ETH_DMAC0IER_RBUE_Msk                               /*!< Receive Buffer Unavailable Enable */
12017 #define ETH_DMAC0IER_RSE_Pos                (8U)
12018 #define ETH_DMAC0IER_RSE_Msk                (0x1U << ETH_DMAC0IER_RSE_Pos)                      /*!< 0x00000100 */
12019 #define ETH_DMAC0IER_RSE                    ETH_DMAC0IER_RSE_Msk                                /*!< Receive Stopped Enable */
12020 #define ETH_DMAC0IER_RWTE_Pos               (9U)
12021 #define ETH_DMAC0IER_RWTE_Msk               (0x1U << ETH_DMAC0IER_RWTE_Pos)                     /*!< 0x00000200 */
12022 #define ETH_DMAC0IER_RWTE                   ETH_DMAC0IER_RWTE_Msk                               /*!< Receive Watchdog Timeout Enable */
12023 #define ETH_DMAC0IER_ETIE_Pos               (10U)
12024 #define ETH_DMAC0IER_ETIE_Msk               (0x1U << ETH_DMAC0IER_ETIE_Pos)                     /*!< 0x00000400 */
12025 #define ETH_DMAC0IER_ETIE                   ETH_DMAC0IER_ETIE_Msk                               /*!< Early Transmit Interrupt Enable */
12026 #define ETH_DMAC0IER_ERIE_Pos               (11U)
12027 #define ETH_DMAC0IER_ERIE_Msk               (0x1U << ETH_DMAC0IER_ERIE_Pos)                     /*!< 0x00000800 */
12028 #define ETH_DMAC0IER_ERIE                   ETH_DMAC0IER_ERIE_Msk                               /*!< Early Receive Interrupt Enable */
12029 #define ETH_DMAC0IER_FBEE_Pos               (12U)
12030 #define ETH_DMAC0IER_FBEE_Msk               (0x1U << ETH_DMAC0IER_FBEE_Pos)                     /*!< 0x00001000 */
12031 #define ETH_DMAC0IER_FBEE                   ETH_DMAC0IER_FBEE_Msk                               /*!< Fatal Bus Error Enable */
12032 #define ETH_DMAC0IER_CDEE_Pos               (13U)
12033 #define ETH_DMAC0IER_CDEE_Msk               (0x1U << ETH_DMAC0IER_CDEE_Pos)                     /*!< 0x00002000 */
12034 #define ETH_DMAC0IER_CDEE                   ETH_DMAC0IER_CDEE_Msk                               /*!< Context Descriptor Error Enable */
12035 #define ETH_DMAC0IER_AIE_Pos                (14U)
12036 #define ETH_DMAC0IER_AIE_Msk                (0x1U << ETH_DMAC0IER_AIE_Pos)                      /*!< 0x00004000 */
12037 #define ETH_DMAC0IER_AIE                    ETH_DMAC0IER_AIE_Msk                                /*!< Abnormal Interrupt Summary Enable */
12038 #define ETH_DMAC0IER_NIE_Pos                (15U)
12039 #define ETH_DMAC0IER_NIE_Msk                (0x1U << ETH_DMAC0IER_NIE_Pos)                      /*!< 0x00008000 */
12040 #define ETH_DMAC0IER_NIE                    ETH_DMAC0IER_NIE_Msk                                /*!< Normal Interrupt Summary Enable */
12041 
12042 /************  Bit definition for ETH_DMAC0RXIWTR register  ************/
12043 #define ETH_DMAC0RXIWTR_RWT_Pos             (0U)
12044 #define ETH_DMAC0RXIWTR_RWT_Msk             (0xFFU << ETH_DMAC0RXIWTR_RWT_Pos)                  /*!< 0x000000FF */
12045 #define ETH_DMAC0RXIWTR_RWT                 ETH_DMAC0RXIWTR_RWT_Msk                             /*!< Receive Interrupt Watchdog Timer Count */
12046 #define ETH_DMAC0RXIWTR_RWT_0               (0x1U << ETH_DMAC0RXIWTR_RWT_Pos)                   /*!< 0x00000001 */
12047 #define ETH_DMAC0RXIWTR_RWT_1               (0x2U << ETH_DMAC0RXIWTR_RWT_Pos)                   /*!< 0x00000002 */
12048 #define ETH_DMAC0RXIWTR_RWT_2               (0x4U << ETH_DMAC0RXIWTR_RWT_Pos)                   /*!< 0x00000004 */
12049 #define ETH_DMAC0RXIWTR_RWT_3               (0x8U << ETH_DMAC0RXIWTR_RWT_Pos)                   /*!< 0x00000008 */
12050 #define ETH_DMAC0RXIWTR_RWT_4               (0x10U << ETH_DMAC0RXIWTR_RWT_Pos)                  /*!< 0x00000010 */
12051 #define ETH_DMAC0RXIWTR_RWT_5               (0x20U << ETH_DMAC0RXIWTR_RWT_Pos)                  /*!< 0x00000020 */
12052 #define ETH_DMAC0RXIWTR_RWT_6               (0x40U << ETH_DMAC0RXIWTR_RWT_Pos)                  /*!< 0x00000040 */
12053 #define ETH_DMAC0RXIWTR_RWT_7               (0x80U << ETH_DMAC0RXIWTR_RWT_Pos)                  /*!< 0x00000080 */
12054 
12055 /************  Bit definition for ETH_DMAC0SFCSR register  *************/
12056 #define ETH_DMAC0SFCSR_ESC_Pos              (0U)
12057 #define ETH_DMAC0SFCSR_ESC_Msk              (0x1U << ETH_DMAC0SFCSR_ESC_Pos)                    /*!< 0x00000001 */
12058 #define ETH_DMAC0SFCSR_ESC                  ETH_DMAC0SFCSR_ESC_Msk                              /*!< Enable Slot Comparison */
12059 #define ETH_DMAC0SFCSR_ASC_Pos              (1U)
12060 #define ETH_DMAC0SFCSR_ASC_Msk              (0x1U << ETH_DMAC0SFCSR_ASC_Pos)                    /*!< 0x00000002 */
12061 #define ETH_DMAC0SFCSR_ASC                  ETH_DMAC0SFCSR_ASC_Msk                              /*!< Advance Slot Check */
12062 #define ETH_DMAC0SFCSR_RSN_Pos              (16U)
12063 #define ETH_DMAC0SFCSR_RSN_Msk              (0xFU << ETH_DMAC0SFCSR_RSN_Pos)                    /*!< 0x000F0000 */
12064 #define ETH_DMAC0SFCSR_RSN                  ETH_DMAC0SFCSR_RSN_Msk                              /*!< Reference Slot Number */
12065 #define ETH_DMAC0SFCSR_RSN_0                (0x1U << ETH_DMAC0SFCSR_RSN_Pos)                /*!< 0x00010000 */
12066 #define ETH_DMAC0SFCSR_RSN_1                (0x2U << ETH_DMAC0SFCSR_RSN_Pos)                /*!< 0x00020000 */
12067 #define ETH_DMAC0SFCSR_RSN_2                (0x4U << ETH_DMAC0SFCSR_RSN_Pos)                /*!< 0x00040000 */
12068 #define ETH_DMAC0SFCSR_RSN_3                (0x8U << ETH_DMAC0SFCSR_RSN_Pos)                /*!< 0x00080000 */
12069 
12070 /************  Bit definition for ETH_DMAC0CATXDR register  ************/
12071 #define ETH_DMAC0CATXDR_CURTDESAPTR_Pos     (0U)
12072 #define ETH_DMAC0CATXDR_CURTDESAPTR_Msk     (0xFFFFFFFFU << ETH_DMAC0CATXDR_CURTDESAPTR_Pos)    /*!< 0xFFFFFFFF */
12073 #define ETH_DMAC0CATXDR_CURTDESAPTR         ETH_DMAC0CATXDR_CURTDESAPTR_Msk                     /*!< Application Transmit Descriptor Address Pointer */
12074 #define ETH_DMAC0CATXDR_CURTDESAPTR_0       (0x1U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos)           /*!< 0x00000001 */
12075 #define ETH_DMAC0CATXDR_CURTDESAPTR_1       (0x2U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos)           /*!< 0x00000002 */
12076 #define ETH_DMAC0CATXDR_CURTDESAPTR_2       (0x4U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos)           /*!< 0x00000004 */
12077 #define ETH_DMAC0CATXDR_CURTDESAPTR_3       (0x8U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos)           /*!< 0x00000008 */
12078 #define ETH_DMAC0CATXDR_CURTDESAPTR_4       (0x10U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos)          /*!< 0x00000010 */
12079 #define ETH_DMAC0CATXDR_CURTDESAPTR_5       (0x20U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos)          /*!< 0x00000020 */
12080 #define ETH_DMAC0CATXDR_CURTDESAPTR_6       (0x40U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos)          /*!< 0x00000040 */
12081 #define ETH_DMAC0CATXDR_CURTDESAPTR_7       (0x80U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos)          /*!< 0x00000080 */
12082 #define ETH_DMAC0CATXDR_CURTDESAPTR_8       (0x100U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos)         /*!< 0x00000100 */
12083 #define ETH_DMAC0CATXDR_CURTDESAPTR_9       (0x200U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos)         /*!< 0x00000200 */
12084 #define ETH_DMAC0CATXDR_CURTDESAPTR_10      (0x400U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos)         /*!< 0x00000400 */
12085 #define ETH_DMAC0CATXDR_CURTDESAPTR_11      (0x800U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos)         /*!< 0x00000800 */
12086 #define ETH_DMAC0CATXDR_CURTDESAPTR_12      (0x1000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos)        /*!< 0x00001000 */
12087 #define ETH_DMAC0CATXDR_CURTDESAPTR_13      (0x2000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos)        /*!< 0x00002000 */
12088 #define ETH_DMAC0CATXDR_CURTDESAPTR_14      (0x4000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos)        /*!< 0x00004000 */
12089 #define ETH_DMAC0CATXDR_CURTDESAPTR_15      (0x8000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos)        /*!< 0x00008000 */
12090 #define ETH_DMAC0CATXDR_CURTDESAPTR_16      (0x10000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos)       /*!< 0x00010000 */
12091 #define ETH_DMAC0CATXDR_CURTDESAPTR_17      (0x20000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos)       /*!< 0x00020000 */
12092 #define ETH_DMAC0CATXDR_CURTDESAPTR_18      (0x40000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos)       /*!< 0x00040000 */
12093 #define ETH_DMAC0CATXDR_CURTDESAPTR_19      (0x80000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos)       /*!< 0x00080000 */
12094 #define ETH_DMAC0CATXDR_CURTDESAPTR_20      (0x100000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos)      /*!< 0x00100000 */
12095 #define ETH_DMAC0CATXDR_CURTDESAPTR_21      (0x200000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos)      /*!< 0x00200000 */
12096 #define ETH_DMAC0CATXDR_CURTDESAPTR_22      (0x400000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos)      /*!< 0x00400000 */
12097 #define ETH_DMAC0CATXDR_CURTDESAPTR_23      (0x800000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos)      /*!< 0x00800000 */
12098 #define ETH_DMAC0CATXDR_CURTDESAPTR_24      (0x1000000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos)     /*!< 0x01000000 */
12099 #define ETH_DMAC0CATXDR_CURTDESAPTR_25      (0x2000000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos)     /*!< 0x02000000 */
12100 #define ETH_DMAC0CATXDR_CURTDESAPTR_26      (0x4000000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos)     /*!< 0x04000000 */
12101 #define ETH_DMAC0CATXDR_CURTDESAPTR_27      (0x8000000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos)     /*!< 0x08000000 */
12102 #define ETH_DMAC0CATXDR_CURTDESAPTR_28      (0x10000000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos)    /*!< 0x10000000 */
12103 #define ETH_DMAC0CATXDR_CURTDESAPTR_29      (0x20000000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos)    /*!< 0x20000000 */
12104 #define ETH_DMAC0CATXDR_CURTDESAPTR_30      (0x40000000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos)    /*!< 0x40000000 */
12105 #define ETH_DMAC0CATXDR_CURTDESAPTR_31      (0x80000000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos)    /*!< 0x80000000 */
12106 
12107 /************  Bit definition for ETH_DMAC0CARXDR register  ************/
12108 #define ETH_DMAC0CARXDR_CURRDESAPTR_Pos     (0U)
12109 #define ETH_DMAC0CARXDR_CURRDESAPTR_Msk     (0xFFFFFFFFU << ETH_DMAC0CARXDR_CURRDESAPTR_Pos)    /*!< 0xFFFFFFFF */
12110 #define ETH_DMAC0CARXDR_CURRDESAPTR         ETH_DMAC0CARXDR_CURRDESAPTR_Msk                     /*!< Application Receive Descriptor Address Pointer */
12111 #define ETH_DMAC0CARXDR_CURRDESAPTR_0       (0x1U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos)           /*!< 0x00000001 */
12112 #define ETH_DMAC0CARXDR_CURRDESAPTR_1       (0x2U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos)           /*!< 0x00000002 */
12113 #define ETH_DMAC0CARXDR_CURRDESAPTR_2       (0x4U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos)           /*!< 0x00000004 */
12114 #define ETH_DMAC0CARXDR_CURRDESAPTR_3       (0x8U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos)           /*!< 0x00000008 */
12115 #define ETH_DMAC0CARXDR_CURRDESAPTR_4       (0x10U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos)          /*!< 0x00000010 */
12116 #define ETH_DMAC0CARXDR_CURRDESAPTR_5       (0x20U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos)          /*!< 0x00000020 */
12117 #define ETH_DMAC0CARXDR_CURRDESAPTR_6       (0x40U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos)          /*!< 0x00000040 */
12118 #define ETH_DMAC0CARXDR_CURRDESAPTR_7       (0x80U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos)          /*!< 0x00000080 */
12119 #define ETH_DMAC0CARXDR_CURRDESAPTR_8       (0x100U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos)         /*!< 0x00000100 */
12120 #define ETH_DMAC0CARXDR_CURRDESAPTR_9       (0x200U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos)         /*!< 0x00000200 */
12121 #define ETH_DMAC0CARXDR_CURRDESAPTR_10      (0x400U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos)         /*!< 0x00000400 */
12122 #define ETH_DMAC0CARXDR_CURRDESAPTR_11      (0x800U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos)         /*!< 0x00000800 */
12123 #define ETH_DMAC0CARXDR_CURRDESAPTR_12      (0x1000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos)        /*!< 0x00001000 */
12124 #define ETH_DMAC0CARXDR_CURRDESAPTR_13      (0x2000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos)        /*!< 0x00002000 */
12125 #define ETH_DMAC0CARXDR_CURRDESAPTR_14      (0x4000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos)        /*!< 0x00004000 */
12126 #define ETH_DMAC0CARXDR_CURRDESAPTR_15      (0x8000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos)        /*!< 0x00008000 */
12127 #define ETH_DMAC0CARXDR_CURRDESAPTR_16      (0x10000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos)       /*!< 0x00010000 */
12128 #define ETH_DMAC0CARXDR_CURRDESAPTR_17      (0x20000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos)       /*!< 0x00020000 */
12129 #define ETH_DMAC0CARXDR_CURRDESAPTR_18      (0x40000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos)       /*!< 0x00040000 */
12130 #define ETH_DMAC0CARXDR_CURRDESAPTR_19      (0x80000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos)       /*!< 0x00080000 */
12131 #define ETH_DMAC0CARXDR_CURRDESAPTR_20      (0x100000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos)      /*!< 0x00100000 */
12132 #define ETH_DMAC0CARXDR_CURRDESAPTR_21      (0x200000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos)      /*!< 0x00200000 */
12133 #define ETH_DMAC0CARXDR_CURRDESAPTR_22      (0x400000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos)      /*!< 0x00400000 */
12134 #define ETH_DMAC0CARXDR_CURRDESAPTR_23      (0x800000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos)      /*!< 0x00800000 */
12135 #define ETH_DMAC0CARXDR_CURRDESAPTR_24      (0x1000000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos)     /*!< 0x01000000 */
12136 #define ETH_DMAC0CARXDR_CURRDESAPTR_25      (0x2000000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos)     /*!< 0x02000000 */
12137 #define ETH_DMAC0CARXDR_CURRDESAPTR_26      (0x4000000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos)     /*!< 0x04000000 */
12138 #define ETH_DMAC0CARXDR_CURRDESAPTR_27      (0x8000000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos)     /*!< 0x08000000 */
12139 #define ETH_DMAC0CARXDR_CURRDESAPTR_28      (0x10000000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos)    /*!< 0x10000000 */
12140 #define ETH_DMAC0CARXDR_CURRDESAPTR_29      (0x20000000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos)    /*!< 0x20000000 */
12141 #define ETH_DMAC0CARXDR_CURRDESAPTR_30      (0x40000000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos)    /*!< 0x40000000 */
12142 #define ETH_DMAC0CARXDR_CURRDESAPTR_31      (0x80000000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos)    /*!< 0x80000000 */
12143 
12144 /************  Bit definition for ETH_DMAC0CATXBR register  ************/
12145 #define ETH_DMAC0CATXBR_CURTBUFAPTR_Pos     (0U)
12146 #define ETH_DMAC0CATXBR_CURTBUFAPTR_Msk     (0xFFFFFFFFU << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos)    /*!< 0xFFFFFFFF */
12147 #define ETH_DMAC0CATXBR_CURTBUFAPTR         ETH_DMAC0CATXBR_CURTBUFAPTR_Msk                     /*!< Application Transmit Buffer Address Pointer */
12148 #define ETH_DMAC0CATXBR_CURTBUFAPTR_0       (0x1U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos)           /*!< 0x00000001 */
12149 #define ETH_DMAC0CATXBR_CURTBUFAPTR_1       (0x2U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos)           /*!< 0x00000002 */
12150 #define ETH_DMAC0CATXBR_CURTBUFAPTR_2       (0x4U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos)           /*!< 0x00000004 */
12151 #define ETH_DMAC0CATXBR_CURTBUFAPTR_3       (0x8U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos)           /*!< 0x00000008 */
12152 #define ETH_DMAC0CATXBR_CURTBUFAPTR_4       (0x10U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos)          /*!< 0x00000010 */
12153 #define ETH_DMAC0CATXBR_CURTBUFAPTR_5       (0x20U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos)          /*!< 0x00000020 */
12154 #define ETH_DMAC0CATXBR_CURTBUFAPTR_6       (0x40U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos)          /*!< 0x00000040 */
12155 #define ETH_DMAC0CATXBR_CURTBUFAPTR_7       (0x80U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos)          /*!< 0x00000080 */
12156 #define ETH_DMAC0CATXBR_CURTBUFAPTR_8       (0x100U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos)         /*!< 0x00000100 */
12157 #define ETH_DMAC0CATXBR_CURTBUFAPTR_9       (0x200U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos)         /*!< 0x00000200 */
12158 #define ETH_DMAC0CATXBR_CURTBUFAPTR_10      (0x400U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos)         /*!< 0x00000400 */
12159 #define ETH_DMAC0CATXBR_CURTBUFAPTR_11      (0x800U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos)         /*!< 0x00000800 */
12160 #define ETH_DMAC0CATXBR_CURTBUFAPTR_12      (0x1000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos)        /*!< 0x00001000 */
12161 #define ETH_DMAC0CATXBR_CURTBUFAPTR_13      (0x2000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos)        /*!< 0x00002000 */
12162 #define ETH_DMAC0CATXBR_CURTBUFAPTR_14      (0x4000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos)        /*!< 0x00004000 */
12163 #define ETH_DMAC0CATXBR_CURTBUFAPTR_15      (0x8000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos)        /*!< 0x00008000 */
12164 #define ETH_DMAC0CATXBR_CURTBUFAPTR_16      (0x10000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos)       /*!< 0x00010000 */
12165 #define ETH_DMAC0CATXBR_CURTBUFAPTR_17      (0x20000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos)       /*!< 0x00020000 */
12166 #define ETH_DMAC0CATXBR_CURTBUFAPTR_18      (0x40000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos)       /*!< 0x00040000 */
12167 #define ETH_DMAC0CATXBR_CURTBUFAPTR_19      (0x80000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos)       /*!< 0x00080000 */
12168 #define ETH_DMAC0CATXBR_CURTBUFAPTR_20      (0x100000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos)      /*!< 0x00100000 */
12169 #define ETH_DMAC0CATXBR_CURTBUFAPTR_21      (0x200000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos)      /*!< 0x00200000 */
12170 #define ETH_DMAC0CATXBR_CURTBUFAPTR_22      (0x400000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos)      /*!< 0x00400000 */
12171 #define ETH_DMAC0CATXBR_CURTBUFAPTR_23      (0x800000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos)      /*!< 0x00800000 */
12172 #define ETH_DMAC0CATXBR_CURTBUFAPTR_24      (0x1000000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos)     /*!< 0x01000000 */
12173 #define ETH_DMAC0CATXBR_CURTBUFAPTR_25      (0x2000000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos)     /*!< 0x02000000 */
12174 #define ETH_DMAC0CATXBR_CURTBUFAPTR_26      (0x4000000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos)     /*!< 0x04000000 */
12175 #define ETH_DMAC0CATXBR_CURTBUFAPTR_27      (0x8000000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos)     /*!< 0x08000000 */
12176 #define ETH_DMAC0CATXBR_CURTBUFAPTR_28      (0x10000000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos)    /*!< 0x10000000 */
12177 #define ETH_DMAC0CATXBR_CURTBUFAPTR_29      (0x20000000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos)    /*!< 0x20000000 */
12178 #define ETH_DMAC0CATXBR_CURTBUFAPTR_30      (0x40000000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos)    /*!< 0x40000000 */
12179 #define ETH_DMAC0CATXBR_CURTBUFAPTR_31      (0x80000000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos)    /*!< 0x80000000 */
12180 
12181 /************  Bit definition for ETH_DMAC0CARXBR register  ************/
12182 #define ETH_DMAC0CARXBR_CURRBUFAPTR_Pos     (0U)
12183 #define ETH_DMAC0CARXBR_CURRBUFAPTR_Msk     (0xFFFFFFFFU << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos)    /*!< 0xFFFFFFFF */
12184 #define ETH_DMAC0CARXBR_CURRBUFAPTR         ETH_DMAC0CARXBR_CURRBUFAPTR_Msk                     /*!< Application Receive Buffer Address Pointer */
12185 #define ETH_DMAC0CARXBR_CURRBUFAPTR_0       (0x1U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos)           /*!< 0x00000001 */
12186 #define ETH_DMAC0CARXBR_CURRBUFAPTR_1       (0x2U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos)           /*!< 0x00000002 */
12187 #define ETH_DMAC0CARXBR_CURRBUFAPTR_2       (0x4U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos)           /*!< 0x00000004 */
12188 #define ETH_DMAC0CARXBR_CURRBUFAPTR_3       (0x8U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos)           /*!< 0x00000008 */
12189 #define ETH_DMAC0CARXBR_CURRBUFAPTR_4       (0x10U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos)          /*!< 0x00000010 */
12190 #define ETH_DMAC0CARXBR_CURRBUFAPTR_5       (0x20U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos)          /*!< 0x00000020 */
12191 #define ETH_DMAC0CARXBR_CURRBUFAPTR_6       (0x40U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos)          /*!< 0x00000040 */
12192 #define ETH_DMAC0CARXBR_CURRBUFAPTR_7       (0x80U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos)          /*!< 0x00000080 */
12193 #define ETH_DMAC0CARXBR_CURRBUFAPTR_8       (0x100U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos)         /*!< 0x00000100 */
12194 #define ETH_DMAC0CARXBR_CURRBUFAPTR_9       (0x200U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos)         /*!< 0x00000200 */
12195 #define ETH_DMAC0CARXBR_CURRBUFAPTR_10      (0x400U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos)         /*!< 0x00000400 */
12196 #define ETH_DMAC0CARXBR_CURRBUFAPTR_11      (0x800U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos)         /*!< 0x00000800 */
12197 #define ETH_DMAC0CARXBR_CURRBUFAPTR_12      (0x1000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos)        /*!< 0x00001000 */
12198 #define ETH_DMAC0CARXBR_CURRBUFAPTR_13      (0x2000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos)        /*!< 0x00002000 */
12199 #define ETH_DMAC0CARXBR_CURRBUFAPTR_14      (0x4000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos)        /*!< 0x00004000 */
12200 #define ETH_DMAC0CARXBR_CURRBUFAPTR_15      (0x8000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos)        /*!< 0x00008000 */
12201 #define ETH_DMAC0CARXBR_CURRBUFAPTR_16      (0x10000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos)       /*!< 0x00010000 */
12202 #define ETH_DMAC0CARXBR_CURRBUFAPTR_17      (0x20000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos)       /*!< 0x00020000 */
12203 #define ETH_DMAC0CARXBR_CURRBUFAPTR_18      (0x40000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos)       /*!< 0x00040000 */
12204 #define ETH_DMAC0CARXBR_CURRBUFAPTR_19      (0x80000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos)       /*!< 0x00080000 */
12205 #define ETH_DMAC0CARXBR_CURRBUFAPTR_20      (0x100000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos)      /*!< 0x00100000 */
12206 #define ETH_DMAC0CARXBR_CURRBUFAPTR_21      (0x200000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos)      /*!< 0x00200000 */
12207 #define ETH_DMAC0CARXBR_CURRBUFAPTR_22      (0x400000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos)      /*!< 0x00400000 */
12208 #define ETH_DMAC0CARXBR_CURRBUFAPTR_23      (0x800000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos)      /*!< 0x00800000 */
12209 #define ETH_DMAC0CARXBR_CURRBUFAPTR_24      (0x1000000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos)     /*!< 0x01000000 */
12210 #define ETH_DMAC0CARXBR_CURRBUFAPTR_25      (0x2000000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos)     /*!< 0x02000000 */
12211 #define ETH_DMAC0CARXBR_CURRBUFAPTR_26      (0x4000000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos)     /*!< 0x04000000 */
12212 #define ETH_DMAC0CARXBR_CURRBUFAPTR_27      (0x8000000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos)     /*!< 0x08000000 */
12213 #define ETH_DMAC0CARXBR_CURRBUFAPTR_28      (0x10000000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos)    /*!< 0x10000000 */
12214 #define ETH_DMAC0CARXBR_CURRBUFAPTR_29      (0x20000000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos)    /*!< 0x20000000 */
12215 #define ETH_DMAC0CARXBR_CURRBUFAPTR_30      (0x40000000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos)    /*!< 0x40000000 */
12216 #define ETH_DMAC0CARXBR_CURRBUFAPTR_31      (0x80000000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos)    /*!< 0x80000000 */
12217 
12218 /**************  Bit definition for ETH_DMAC0SR register  **************/
12219 #define ETH_DMAC0SR_TI_Pos                  (0U)
12220 #define ETH_DMAC0SR_TI_Msk                  (0x1U << ETH_DMAC0SR_TI_Pos)                        /*!< 0x00000001 */
12221 #define ETH_DMAC0SR_TI                      ETH_DMAC0SR_TI_Msk                                  /*!< Transmit Interrupt */
12222 #define ETH_DMAC0SR_TPS_Pos                 (1U)
12223 #define ETH_DMAC0SR_TPS_Msk                 (0x1U << ETH_DMAC0SR_TPS_Pos)                       /*!< 0x00000002 */
12224 #define ETH_DMAC0SR_TPS                     ETH_DMAC0SR_TPS_Msk                                 /*!< Transmit Process Stopped */
12225 #define ETH_DMAC0SR_TBU_Pos                 (2U)
12226 #define ETH_DMAC0SR_TBU_Msk                 (0x1U << ETH_DMAC0SR_TBU_Pos)                       /*!< 0x00000004 */
12227 #define ETH_DMAC0SR_TBU                     ETH_DMAC0SR_TBU_Msk                                 /*!< Transmit Buffer Unavailable */
12228 #define ETH_DMAC0SR_RI_Pos                  (6U)
12229 #define ETH_DMAC0SR_RI_Msk                  (0x1U << ETH_DMAC0SR_RI_Pos)                        /*!< 0x00000040 */
12230 #define ETH_DMAC0SR_RI                      ETH_DMAC0SR_RI_Msk                                  /*!< Receive Interrupt */
12231 #define ETH_DMAC0SR_RBU_Pos                 (7U)
12232 #define ETH_DMAC0SR_RBU_Msk                 (0x1U << ETH_DMAC0SR_RBU_Pos)                       /*!< 0x00000080 */
12233 #define ETH_DMAC0SR_RBU                     ETH_DMAC0SR_RBU_Msk                                 /*!< Receive Buffer Unavailable */
12234 #define ETH_DMAC0SR_RPS_Pos                 (8U)
12235 #define ETH_DMAC0SR_RPS_Msk                 (0x1U << ETH_DMAC0SR_RPS_Pos)                       /*!< 0x00000100 */
12236 #define ETH_DMAC0SR_RPS                     ETH_DMAC0SR_RPS_Msk                                 /*!< Receive Process Stopped */
12237 #define ETH_DMAC0SR_RWT_Pos                 (9U)
12238 #define ETH_DMAC0SR_RWT_Msk                 (0x1U << ETH_DMAC0SR_RWT_Pos)                       /*!< 0x00000200 */
12239 #define ETH_DMAC0SR_RWT                     ETH_DMAC0SR_RWT_Msk                                 /*!< Receive Watchdog Timeout */
12240 #define ETH_DMAC0SR_ETI_Pos                 (10U)
12241 #define ETH_DMAC0SR_ETI_Msk                 (0x1U << ETH_DMAC0SR_ETI_Pos)                       /*!< 0x00000400 */
12242 #define ETH_DMAC0SR_ETI                     ETH_DMAC0SR_ETI_Msk                                 /*!< Early Transmit Interrupt */
12243 #define ETH_DMAC0SR_ERI_Pos                 (11U)
12244 #define ETH_DMAC0SR_ERI_Msk                 (0x1U << ETH_DMAC0SR_ERI_Pos)                       /*!< 0x00000800 */
12245 #define ETH_DMAC0SR_ERI                     ETH_DMAC0SR_ERI_Msk                                 /*!< Early Receive Interrupt */
12246 #define ETH_DMAC0SR_FBE_Pos                 (12U)
12247 #define ETH_DMAC0SR_FBE_Msk                 (0x1U << ETH_DMAC0SR_FBE_Pos)                       /*!< 0x00001000 */
12248 #define ETH_DMAC0SR_FBE                     ETH_DMAC0SR_FBE_Msk                                 /*!< Fatal Bus Error */
12249 #define ETH_DMAC0SR_CDE_Pos                 (13U)
12250 #define ETH_DMAC0SR_CDE_Msk                 (0x1U << ETH_DMAC0SR_CDE_Pos)                       /*!< 0x00002000 */
12251 #define ETH_DMAC0SR_CDE                     ETH_DMAC0SR_CDE_Msk                                 /*!< Context Descriptor Error */
12252 #define ETH_DMAC0SR_AIS_Pos                 (14U)
12253 #define ETH_DMAC0SR_AIS_Msk                 (0x1U << ETH_DMAC0SR_AIS_Pos)                       /*!< 0x00004000 */
12254 #define ETH_DMAC0SR_AIS                     ETH_DMAC0SR_AIS_Msk                                 /*!< Abnormal Interrupt Summary */
12255 #define ETH_DMAC0SR_NIS_Pos                 (15U)
12256 #define ETH_DMAC0SR_NIS_Msk                 (0x1U << ETH_DMAC0SR_NIS_Pos)                       /*!< 0x00008000 */
12257 #define ETH_DMAC0SR_NIS                     ETH_DMAC0SR_NIS_Msk                                 /*!< Normal Interrupt Summary */
12258 #define ETH_DMAC0SR_TEB_Pos                 (16U)
12259 #define ETH_DMAC0SR_TEB_Msk                 (0x7U << ETH_DMAC0SR_TEB_Pos)                       /*!< 0x00070000 */
12260 #define ETH_DMAC0SR_TEB                     ETH_DMAC0SR_TEB_Msk                                 /*!< Tx DMA Error Bits */
12261 #define ETH_DMAC0SR_TEB_0                   (0x1U << ETH_DMAC0SR_TEB_Pos)                   /*!< 0x00010000 */
12262 #define ETH_DMAC0SR_TEB_1                   (0x2U << ETH_DMAC0SR_TEB_Pos)                   /*!< 0x00020000 */
12263 #define ETH_DMAC0SR_TEB_2                   (0x4U << ETH_DMAC0SR_TEB_Pos)                   /*!< 0x00040000 */
12264 #define ETH_DMAC0SR_REB_Pos                 (19U)
12265 #define ETH_DMAC0SR_REB_Msk                 (0x7U << ETH_DMAC0SR_REB_Pos)                       /*!< 0x00380000 */
12266 #define ETH_DMAC0SR_REB                     ETH_DMAC0SR_REB_Msk                                 /*!< Rx DMA Error Bits */
12267 #define ETH_DMAC0SR_REB_0                   (0x1U << ETH_DMAC0SR_REB_Pos)                   /*!< 0x00080000 */
12268 #define ETH_DMAC0SR_REB_1                   (0x2U << ETH_DMAC0SR_REB_Pos)                  /*!< 0x00100000 */
12269 #define ETH_DMAC0SR_REB_2                   (0x4U << ETH_DMAC0SR_REB_Pos)                  /*!< 0x00200000 */
12270 
12271 /*************  Bit definition for ETH_DMAC0MFCR register  *************/
12272 #define ETH_DMAC0MFCR_MFC_Pos               (0U)
12273 #define ETH_DMAC0MFCR_MFC_Msk               (0x7FFU << ETH_DMAC0MFCR_MFC_Pos)                   /*!< 0x000007FF */
12274 #define ETH_DMAC0MFCR_MFC                   ETH_DMAC0MFCR_MFC_Msk                               /*!< Dropped Packet Counters */
12275 #define ETH_DMAC0MFCR_MFC_0                 (0x1U << ETH_DMAC0MFCR_MFC_Pos)                     /*!< 0x00000001 */
12276 #define ETH_DMAC0MFCR_MFC_1                 (0x2U << ETH_DMAC0MFCR_MFC_Pos)                     /*!< 0x00000002 */
12277 #define ETH_DMAC0MFCR_MFC_2                 (0x4U << ETH_DMAC0MFCR_MFC_Pos)                     /*!< 0x00000004 */
12278 #define ETH_DMAC0MFCR_MFC_3                 (0x8U << ETH_DMAC0MFCR_MFC_Pos)                     /*!< 0x00000008 */
12279 #define ETH_DMAC0MFCR_MFC_4                 (0x10U << ETH_DMAC0MFCR_MFC_Pos)                    /*!< 0x00000010 */
12280 #define ETH_DMAC0MFCR_MFC_5                 (0x20U << ETH_DMAC0MFCR_MFC_Pos)                    /*!< 0x00000020 */
12281 #define ETH_DMAC0MFCR_MFC_6                 (0x40U << ETH_DMAC0MFCR_MFC_Pos)                    /*!< 0x00000040 */
12282 #define ETH_DMAC0MFCR_MFC_7                 (0x80U << ETH_DMAC0MFCR_MFC_Pos)                    /*!< 0x00000080 */
12283 #define ETH_DMAC0MFCR_MFC_8                 (0x100U << ETH_DMAC0MFCR_MFC_Pos)                   /*!< 0x00000100 */
12284 #define ETH_DMAC0MFCR_MFC_9                 (0x200U << ETH_DMAC0MFCR_MFC_Pos)                   /*!< 0x00000200 */
12285 #define ETH_DMAC0MFCR_MFC_10                (0x400U << ETH_DMAC0MFCR_MFC_Pos)                   /*!< 0x00000400 */
12286 #define ETH_DMAC0MFCR_MFCO_Pos              (15U)
12287 #define ETH_DMAC0MFCR_MFCO_Msk              (0x1U << ETH_DMAC0MFCR_MFCO_Pos)                    /*!< 0x00008000 */
12288 #define ETH_DMAC0MFCR_MFCO                  ETH_DMAC0MFCR_MFCO_Msk                              /*!< Overflow status of the MFC Counter */
12289 
12290 /**************  Bit definition for ETH_DMAC1CR register  **************/
12291 #define ETH_DMAC1CR_MSS_Pos                 (0U)
12292 #define ETH_DMAC1CR_MSS_Msk                 (0x3FFFU << ETH_DMAC1CR_MSS_Pos)                    /*!< 0x00003FFF */
12293 #define ETH_DMAC1CR_MSS                     ETH_DMAC1CR_MSS_Msk                                 /*!< Maximum Segment Size */
12294 #define ETH_DMAC1CR_MSS_0                   (0x1U << ETH_DMAC1CR_MSS_Pos)                       /*!< 0x00000001 */
12295 #define ETH_DMAC1CR_MSS_1                   (0x2U << ETH_DMAC1CR_MSS_Pos)                       /*!< 0x00000002 */
12296 #define ETH_DMAC1CR_MSS_2                   (0x4U << ETH_DMAC1CR_MSS_Pos)                       /*!< 0x00000004 */
12297 #define ETH_DMAC1CR_MSS_3                   (0x8U << ETH_DMAC1CR_MSS_Pos)                       /*!< 0x00000008 */
12298 #define ETH_DMAC1CR_MSS_4                   (0x10U << ETH_DMAC1CR_MSS_Pos)                      /*!< 0x00000010 */
12299 #define ETH_DMAC1CR_MSS_5                   (0x20U << ETH_DMAC1CR_MSS_Pos)                      /*!< 0x00000020 */
12300 #define ETH_DMAC1CR_MSS_6                   (0x40U << ETH_DMAC1CR_MSS_Pos)                      /*!< 0x00000040 */
12301 #define ETH_DMAC1CR_MSS_7                   (0x80U << ETH_DMAC1CR_MSS_Pos)                      /*!< 0x00000080 */
12302 #define ETH_DMAC1CR_MSS_8                   (0x100U << ETH_DMAC1CR_MSS_Pos)                     /*!< 0x00000100 */
12303 #define ETH_DMAC1CR_MSS_9                   (0x200U << ETH_DMAC1CR_MSS_Pos)                     /*!< 0x00000200 */
12304 #define ETH_DMAC1CR_MSS_10                  (0x400U << ETH_DMAC1CR_MSS_Pos)                     /*!< 0x00000400 */
12305 #define ETH_DMAC1CR_MSS_11                  (0x800U << ETH_DMAC1CR_MSS_Pos)                     /*!< 0x00000800 */
12306 #define ETH_DMAC1CR_MSS_12                  (0x1000U << ETH_DMAC1CR_MSS_Pos)                    /*!< 0x00001000 */
12307 #define ETH_DMAC1CR_MSS_13                  (0x2000U << ETH_DMAC1CR_MSS_Pos)                    /*!< 0x00002000 */
12308 #define ETH_DMAC1CR_PBLX8_Pos               (16U)
12309 #define ETH_DMAC1CR_PBLX8_Msk               (0x1U << ETH_DMAC1CR_PBLX8_Pos)                     /*!< 0x00010000 */
12310 #define ETH_DMAC1CR_PBLX8                   ETH_DMAC1CR_PBLX8_Msk                               /*!< 8xPBL mode */
12311 #define ETH_DMAC1CR_DSL_Pos                 (18U)
12312 #define ETH_DMAC1CR_DSL_Msk                 (0x7U << ETH_DMAC1CR_DSL_Pos)                       /*!< 0x001C0000 */
12313 #define ETH_DMAC1CR_DSL                     ETH_DMAC1CR_DSL_Msk                                 /*!< Descriptor Skip Length */
12314 #define ETH_DMAC1CR_DSL_0                   (0x1U << ETH_DMAC1CR_DSL_Pos)                   /*!< 0x00040000 */
12315 #define ETH_DMAC1CR_DSL_1                   (0x2U << ETH_DMAC1CR_DSL_Pos)                   /*!< 0x00080000 */
12316 #define ETH_DMAC1CR_DSL_2                   (0x4U << ETH_DMAC1CR_DSL_Pos)                  /*!< 0x00100000 */
12317 
12318 /*************  Bit definition for ETH_DMAC1TXCR register  *************/
12319 #define ETH_DMAC1TXCR_ST_Pos                (0U)
12320 #define ETH_DMAC1TXCR_ST_Msk                (0x1U << ETH_DMAC1TXCR_ST_Pos)                      /*!< 0x00000001 */
12321 #define ETH_DMAC1TXCR_ST                    ETH_DMAC1TXCR_ST_Msk                                /*!< Start or Stop Transmission Command */
12322 #define ETH_DMAC1TXCR_TCW_Pos               (1U)
12323 #define ETH_DMAC1TXCR_TCW_Msk               (0x7U << ETH_DMAC1TXCR_TCW_Pos)                     /*!< 0x0000000E */
12324 #define ETH_DMAC1TXCR_TCW                   ETH_DMAC1TXCR_TCW_Msk                               /*!< Transmit Channel Weight */
12325 #define ETH_DMAC1TXCR_TCW_0                 (0x1U << ETH_DMAC1TXCR_TCW_Pos)                     /*!< 0x00000002 */
12326 #define ETH_DMAC1TXCR_TCW_1                 (0x2U << ETH_DMAC1TXCR_TCW_Pos)                     /*!< 0x00000004 */
12327 #define ETH_DMAC1TXCR_TCW_2                 (0x4U << ETH_DMAC1TXCR_TCW_Pos)                     /*!< 0x00000008 */
12328 #define ETH_DMAC1TXCR_OSF_Pos               (4U)
12329 #define ETH_DMAC1TXCR_OSF_Msk               (0x1U << ETH_DMAC1TXCR_OSF_Pos)                     /*!< 0x00000010 */
12330 #define ETH_DMAC1TXCR_OSF                   ETH_DMAC1TXCR_OSF_Msk                               /*!< Operate on Second Packet */
12331 #define ETH_DMAC1TXCR_TSE_Pos               (12U)
12332 #define ETH_DMAC1TXCR_TSE_Msk               (0x1U << ETH_DMAC1TXCR_TSE_Pos)                     /*!< 0x00001000 */
12333 #define ETH_DMAC1TXCR_TSE                   ETH_DMAC1TXCR_TSE_Msk                               /*!< TCP Segmentation Enabled */
12334 #define ETH_DMAC1TXCR_TXPBL_Pos             (16U)
12335 #define ETH_DMAC1TXCR_TXPBL_Msk             (0x3FU << ETH_DMAC1TXCR_TXPBL_Pos)                  /*!< 0x003F0000 */
12336 #define ETH_DMAC1TXCR_TXPBL                 ETH_DMAC1TXCR_TXPBL_Msk                             /*!< Transmit Programmable Burst Length */
12337 #define ETH_DMAC1TXCR_TXPBL_0               (0x1U << ETH_DMAC1TXCR_TXPBL_Pos)               /*!< 0x00010000 */
12338 #define ETH_DMAC1TXCR_TXPBL_1               (0x2U << ETH_DMAC1TXCR_TXPBL_Pos)               /*!< 0x00020000 */
12339 #define ETH_DMAC1TXCR_TXPBL_2               (0x4U << ETH_DMAC1TXCR_TXPBL_Pos)               /*!< 0x00040000 */
12340 #define ETH_DMAC1TXCR_TXPBL_3               (0x8U << ETH_DMAC1TXCR_TXPBL_Pos)               /*!< 0x00080000 */
12341 #define ETH_DMAC1TXCR_TXPBL_4               (0x10U << ETH_DMAC1TXCR_TXPBL_Pos)              /*!< 0x00100000 */
12342 #define ETH_DMAC1TXCR_TXPBL_5               (0x20U << ETH_DMAC1TXCR_TXPBL_Pos)              /*!< 0x00200000 */
12343 #define ETH_DMAC1TXCR_TQOS_Pos              (24U)
12344 #define ETH_DMAC1TXCR_TQOS_Msk              (0xFU << ETH_DMAC1TXCR_TQOS_Pos)                    /*!< 0x0F000000 */
12345 #define ETH_DMAC1TXCR_TQOS                  ETH_DMAC1TXCR_TQOS_Msk                              /*!< Transmit QOS. */
12346 #define ETH_DMAC1TXCR_TQOS_0                (0x1U << ETH_DMAC1TXCR_TQOS_Pos)              /*!< 0x01000000 */
12347 #define ETH_DMAC1TXCR_TQOS_1                (0x2U << ETH_DMAC1TXCR_TQOS_Pos)              /*!< 0x02000000 */
12348 #define ETH_DMAC1TXCR_TQOS_2                (0x4U << ETH_DMAC1TXCR_TQOS_Pos)              /*!< 0x04000000 */
12349 #define ETH_DMAC1TXCR_TQOS_3                (0x8U << ETH_DMAC1TXCR_TQOS_Pos)              /*!< 0x08000000 */
12350 
12351 /************  Bit definition for ETH_DMAC1TXDLAR register  ************/
12352 #define ETH_DMAC1TXDLAR_TDESLA_Pos          (3U)
12353 #define ETH_DMAC1TXDLAR_TDESLA_Msk          (0x1FFFFFFFU << ETH_DMAC1TXDLAR_TDESLA_Pos)         /*!< 0xFFFFFFF8 */
12354 #define ETH_DMAC1TXDLAR_TDESLA              ETH_DMAC1TXDLAR_TDESLA_Msk                          /*!< Start of Transmit List */
12355 #define ETH_DMAC1TXDLAR_TDESLA_0            (0x1U << ETH_DMAC1TXDLAR_TDESLA_Pos)                /*!< 0x00000008 */
12356 #define ETH_DMAC1TXDLAR_TDESLA_1            (0x2U << ETH_DMAC1TXDLAR_TDESLA_Pos)               /*!< 0x00000010 */
12357 #define ETH_DMAC1TXDLAR_TDESLA_2            (0x4U << ETH_DMAC1TXDLAR_TDESLA_Pos)               /*!< 0x00000020 */
12358 #define ETH_DMAC1TXDLAR_TDESLA_3            (0x8U << ETH_DMAC1TXDLAR_TDESLA_Pos)               /*!< 0x00000040 */
12359 #define ETH_DMAC1TXDLAR_TDESLA_4            (0x10U << ETH_DMAC1TXDLAR_TDESLA_Pos)               /*!< 0x00000080 */
12360 #define ETH_DMAC1TXDLAR_TDESLA_5            (0x20U << ETH_DMAC1TXDLAR_TDESLA_Pos)              /*!< 0x00000100 */
12361 #define ETH_DMAC1TXDLAR_TDESLA_6            (0x40U << ETH_DMAC1TXDLAR_TDESLA_Pos)              /*!< 0x00000200 */
12362 #define ETH_DMAC1TXDLAR_TDESLA_7            (0x80U << ETH_DMAC1TXDLAR_TDESLA_Pos)              /*!< 0x00000400 */
12363 #define ETH_DMAC1TXDLAR_TDESLA_8            (0x100U << ETH_DMAC1TXDLAR_TDESLA_Pos)              /*!< 0x00000800 */
12364 #define ETH_DMAC1TXDLAR_TDESLA_9            (0x200U << ETH_DMAC1TXDLAR_TDESLA_Pos)             /*!< 0x00001000 */
12365 #define ETH_DMAC1TXDLAR_TDESLA_10           (0x400U << ETH_DMAC1TXDLAR_TDESLA_Pos)             /*!< 0x00002000 */
12366 #define ETH_DMAC1TXDLAR_TDESLA_11           (0x800U << ETH_DMAC1TXDLAR_TDESLA_Pos)             /*!< 0x00004000 */
12367 #define ETH_DMAC1TXDLAR_TDESLA_12           (0x1000U << ETH_DMAC1TXDLAR_TDESLA_Pos)             /*!< 0x00008000 */
12368 #define ETH_DMAC1TXDLAR_TDESLA_13           (0x2000U << ETH_DMAC1TXDLAR_TDESLA_Pos)            /*!< 0x00010000 */
12369 #define ETH_DMAC1TXDLAR_TDESLA_14           (0x4000U << ETH_DMAC1TXDLAR_TDESLA_Pos)            /*!< 0x00020000 */
12370 #define ETH_DMAC1TXDLAR_TDESLA_15           (0x8000U << ETH_DMAC1TXDLAR_TDESLA_Pos)            /*!< 0x00040000 */
12371 #define ETH_DMAC1TXDLAR_TDESLA_16           (0x10000U << ETH_DMAC1TXDLAR_TDESLA_Pos)            /*!< 0x00080000 */
12372 #define ETH_DMAC1TXDLAR_TDESLA_17           (0x20000U << ETH_DMAC1TXDLAR_TDESLA_Pos)           /*!< 0x00100000 */
12373 #define ETH_DMAC1TXDLAR_TDESLA_18           (0x40000U << ETH_DMAC1TXDLAR_TDESLA_Pos)           /*!< 0x00200000 */
12374 #define ETH_DMAC1TXDLAR_TDESLA_19           (0x80000U << ETH_DMAC1TXDLAR_TDESLA_Pos)           /*!< 0x00400000 */
12375 #define ETH_DMAC1TXDLAR_TDESLA_20           (0x100000U << ETH_DMAC1TXDLAR_TDESLA_Pos)           /*!< 0x00800000 */
12376 #define ETH_DMAC1TXDLAR_TDESLA_21           (0x200000U << ETH_DMAC1TXDLAR_TDESLA_Pos)          /*!< 0x01000000 */
12377 #define ETH_DMAC1TXDLAR_TDESLA_22           (0x400000U << ETH_DMAC1TXDLAR_TDESLA_Pos)          /*!< 0x02000000 */
12378 #define ETH_DMAC1TXDLAR_TDESLA_23           (0x800000U << ETH_DMAC1TXDLAR_TDESLA_Pos)          /*!< 0x04000000 */
12379 #define ETH_DMAC1TXDLAR_TDESLA_24           (0x1000000U << ETH_DMAC1TXDLAR_TDESLA_Pos)          /*!< 0x08000000 */
12380 #define ETH_DMAC1TXDLAR_TDESLA_25           (0x2000000U << ETH_DMAC1TXDLAR_TDESLA_Pos)         /*!< 0x10000000 */
12381 #define ETH_DMAC1TXDLAR_TDESLA_26           (0x4000000U << ETH_DMAC1TXDLAR_TDESLA_Pos)         /*!< 0x20000000 */
12382 #define ETH_DMAC1TXDLAR_TDESLA_27           (0x8000000U << ETH_DMAC1TXDLAR_TDESLA_Pos)         /*!< 0x40000000 */
12383 #define ETH_DMAC1TXDLAR_TDESLA_28           (0x10000000U << ETH_DMAC1TXDLAR_TDESLA_Pos)         /*!< 0x80000000 */
12384 
12385 /************  Bit definition for ETH_DMAC1TXDTPR register  ************/
12386 #define ETH_DMAC1TXDTPR_TDT_Pos             (3U)
12387 #define ETH_DMAC1TXDTPR_TDT_Msk             (0x1FFFFFFFU << ETH_DMAC1TXDTPR_TDT_Pos)            /*!< 0xFFFFFFF8 */
12388 #define ETH_DMAC1TXDTPR_TDT                 ETH_DMAC1TXDTPR_TDT_Msk                             /*!< Transmit Descriptor Tail Pointer */
12389 #define ETH_DMAC1TXDTPR_TDT_0               (0x1U << ETH_DMAC1TXDTPR_TDT_Pos)                   /*!< 0x00000008 */
12390 #define ETH_DMAC1TXDTPR_TDT_1               (0x2U << ETH_DMAC1TXDTPR_TDT_Pos)                  /*!< 0x00000010 */
12391 #define ETH_DMAC1TXDTPR_TDT_2               (0x4U << ETH_DMAC1TXDTPR_TDT_Pos)                  /*!< 0x00000020 */
12392 #define ETH_DMAC1TXDTPR_TDT_3               (0x8U << ETH_DMAC1TXDTPR_TDT_Pos)                  /*!< 0x00000040 */
12393 #define ETH_DMAC1TXDTPR_TDT_4               (0x10U << ETH_DMAC1TXDTPR_TDT_Pos)                  /*!< 0x00000080 */
12394 #define ETH_DMAC1TXDTPR_TDT_5               (0x20U << ETH_DMAC1TXDTPR_TDT_Pos)                 /*!< 0x00000100 */
12395 #define ETH_DMAC1TXDTPR_TDT_6               (0x40U << ETH_DMAC1TXDTPR_TDT_Pos)                 /*!< 0x00000200 */
12396 #define ETH_DMAC1TXDTPR_TDT_7               (0x80U << ETH_DMAC1TXDTPR_TDT_Pos)                 /*!< 0x00000400 */
12397 #define ETH_DMAC1TXDTPR_TDT_8               (0x100U << ETH_DMAC1TXDTPR_TDT_Pos)                 /*!< 0x00000800 */
12398 #define ETH_DMAC1TXDTPR_TDT_9               (0x200U << ETH_DMAC1TXDTPR_TDT_Pos)                /*!< 0x00001000 */
12399 #define ETH_DMAC1TXDTPR_TDT_10              (0x400U << ETH_DMAC1TXDTPR_TDT_Pos)                /*!< 0x00002000 */
12400 #define ETH_DMAC1TXDTPR_TDT_11              (0x800U << ETH_DMAC1TXDTPR_TDT_Pos)                /*!< 0x00004000 */
12401 #define ETH_DMAC1TXDTPR_TDT_12              (0x1000U << ETH_DMAC1TXDTPR_TDT_Pos)                /*!< 0x00008000 */
12402 #define ETH_DMAC1TXDTPR_TDT_13              (0x2000U << ETH_DMAC1TXDTPR_TDT_Pos)               /*!< 0x00010000 */
12403 #define ETH_DMAC1TXDTPR_TDT_14              (0x4000U << ETH_DMAC1TXDTPR_TDT_Pos)               /*!< 0x00020000 */
12404 #define ETH_DMAC1TXDTPR_TDT_15              (0x8000U << ETH_DMAC1TXDTPR_TDT_Pos)               /*!< 0x00040000 */
12405 #define ETH_DMAC1TXDTPR_TDT_16              (0x10000U << ETH_DMAC1TXDTPR_TDT_Pos)               /*!< 0x00080000 */
12406 #define ETH_DMAC1TXDTPR_TDT_17              (0x20000U << ETH_DMAC1TXDTPR_TDT_Pos)              /*!< 0x00100000 */
12407 #define ETH_DMAC1TXDTPR_TDT_18              (0x40000U << ETH_DMAC1TXDTPR_TDT_Pos)              /*!< 0x00200000 */
12408 #define ETH_DMAC1TXDTPR_TDT_19              (0x80000U << ETH_DMAC1TXDTPR_TDT_Pos)              /*!< 0x00400000 */
12409 #define ETH_DMAC1TXDTPR_TDT_20              (0x100000U << ETH_DMAC1TXDTPR_TDT_Pos)              /*!< 0x00800000 */
12410 #define ETH_DMAC1TXDTPR_TDT_21              (0x200000U << ETH_DMAC1TXDTPR_TDT_Pos)             /*!< 0x01000000 */
12411 #define ETH_DMAC1TXDTPR_TDT_22              (0x400000U << ETH_DMAC1TXDTPR_TDT_Pos)             /*!< 0x02000000 */
12412 #define ETH_DMAC1TXDTPR_TDT_23              (0x800000U << ETH_DMAC1TXDTPR_TDT_Pos)             /*!< 0x04000000 */
12413 #define ETH_DMAC1TXDTPR_TDT_24              (0x1000000U << ETH_DMAC1TXDTPR_TDT_Pos)             /*!< 0x08000000 */
12414 #define ETH_DMAC1TXDTPR_TDT_25              (0x2000000U << ETH_DMAC1TXDTPR_TDT_Pos)            /*!< 0x10000000 */
12415 #define ETH_DMAC1TXDTPR_TDT_26              (0x4000000U << ETH_DMAC1TXDTPR_TDT_Pos)            /*!< 0x20000000 */
12416 #define ETH_DMAC1TXDTPR_TDT_27              (0x8000000U << ETH_DMAC1TXDTPR_TDT_Pos)            /*!< 0x40000000 */
12417 #define ETH_DMAC1TXDTPR_TDT_28              (0x10000000U << ETH_DMAC1TXDTPR_TDT_Pos)            /*!< 0x80000000 */
12418 
12419 /************  Bit definition for ETH_DMAC1TXRLR register  *************/
12420 #define ETH_DMAC1TXRLR_TDRL_Pos             (0U)
12421 #define ETH_DMAC1TXRLR_TDRL_Msk             (0x3FFU << ETH_DMAC1TXRLR_TDRL_Pos)                 /*!< 0x000003FF */
12422 #define ETH_DMAC1TXRLR_TDRL                 ETH_DMAC1TXRLR_TDRL_Msk                             /*!< Transmit Descriptor Ring Length */
12423 #define ETH_DMAC1TXRLR_TDRL_0               (0x1U << ETH_DMAC1TXRLR_TDRL_Pos)                   /*!< 0x00000001 */
12424 #define ETH_DMAC1TXRLR_TDRL_1               (0x2U << ETH_DMAC1TXRLR_TDRL_Pos)                   /*!< 0x00000002 */
12425 #define ETH_DMAC1TXRLR_TDRL_2               (0x4U << ETH_DMAC1TXRLR_TDRL_Pos)                   /*!< 0x00000004 */
12426 #define ETH_DMAC1TXRLR_TDRL_3               (0x8U << ETH_DMAC1TXRLR_TDRL_Pos)                   /*!< 0x00000008 */
12427 #define ETH_DMAC1TXRLR_TDRL_4               (0x10U << ETH_DMAC1TXRLR_TDRL_Pos)                  /*!< 0x00000010 */
12428 #define ETH_DMAC1TXRLR_TDRL_5               (0x20U << ETH_DMAC1TXRLR_TDRL_Pos)                  /*!< 0x00000020 */
12429 #define ETH_DMAC1TXRLR_TDRL_6               (0x40U << ETH_DMAC1TXRLR_TDRL_Pos)                  /*!< 0x00000040 */
12430 #define ETH_DMAC1TXRLR_TDRL_7               (0x80U << ETH_DMAC1TXRLR_TDRL_Pos)                  /*!< 0x00000080 */
12431 #define ETH_DMAC1TXRLR_TDRL_8               (0x100U << ETH_DMAC1TXRLR_TDRL_Pos)                 /*!< 0x00000100 */
12432 #define ETH_DMAC1TXRLR_TDRL_9               (0x200U << ETH_DMAC1TXRLR_TDRL_Pos)                 /*!< 0x00000200 */
12433 
12434 /*************  Bit definition for ETH_DMAC1IER register  **************/
12435 #define ETH_DMAC1IER_TIE_Pos                (0U)
12436 #define ETH_DMAC1IER_TIE_Msk                (0x1U << ETH_DMAC1IER_TIE_Pos)                      /*!< 0x00000001 */
12437 #define ETH_DMAC1IER_TIE                    ETH_DMAC1IER_TIE_Msk                                /*!< Transmit Interrupt Enable */
12438 #define ETH_DMAC1IER_TXSE_Pos               (1U)
12439 #define ETH_DMAC1IER_TXSE_Msk               (0x1U << ETH_DMAC1IER_TXSE_Pos)                     /*!< 0x00000002 */
12440 #define ETH_DMAC1IER_TXSE                   ETH_DMAC1IER_TXSE_Msk                               /*!< Transmit Stopped Enable */
12441 #define ETH_DMAC1IER_TBUE_Pos               (2U)
12442 #define ETH_DMAC1IER_TBUE_Msk               (0x1U << ETH_DMAC1IER_TBUE_Pos)                     /*!< 0x00000004 */
12443 #define ETH_DMAC1IER_TBUE                   ETH_DMAC1IER_TBUE_Msk                               /*!< Transmit Buffer Unavailable Enable */
12444 #define ETH_DMAC1IER_RIE_Pos                (6U)
12445 #define ETH_DMAC1IER_RIE_Msk                (0x1U << ETH_DMAC1IER_RIE_Pos)                      /*!< 0x00000040 */
12446 #define ETH_DMAC1IER_RIE                    ETH_DMAC1IER_RIE_Msk                                /*!< Receive Interrupt Enable */
12447 #define ETH_DMAC1IER_RBUE_Pos               (7U)
12448 #define ETH_DMAC1IER_RBUE_Msk               (0x1U << ETH_DMAC1IER_RBUE_Pos)                     /*!< 0x00000080 */
12449 #define ETH_DMAC1IER_RBUE                   ETH_DMAC1IER_RBUE_Msk                               /*!< Receive Buffer Unavailable Enable */
12450 #define ETH_DMAC1IER_RSE_Pos                (8U)
12451 #define ETH_DMAC1IER_RSE_Msk                (0x1U << ETH_DMAC1IER_RSE_Pos)                      /*!< 0x00000100 */
12452 #define ETH_DMAC1IER_RSE                    ETH_DMAC1IER_RSE_Msk                                /*!< Receive Stopped Enable */
12453 #define ETH_DMAC1IER_RWTE_Pos               (9U)
12454 #define ETH_DMAC1IER_RWTE_Msk               (0x1U << ETH_DMAC1IER_RWTE_Pos)                     /*!< 0x00000200 */
12455 #define ETH_DMAC1IER_RWTE                   ETH_DMAC1IER_RWTE_Msk                               /*!< Receive Watchdog Timeout Enable */
12456 #define ETH_DMAC1IER_ETIE_Pos               (10U)
12457 #define ETH_DMAC1IER_ETIE_Msk               (0x1U << ETH_DMAC1IER_ETIE_Pos)                     /*!< 0x00000400 */
12458 #define ETH_DMAC1IER_ETIE                   ETH_DMAC1IER_ETIE_Msk                               /*!< Early Transmit Interrupt Enable */
12459 #define ETH_DMAC1IER_ERIE_Pos               (11U)
12460 #define ETH_DMAC1IER_ERIE_Msk               (0x1U << ETH_DMAC1IER_ERIE_Pos)                     /*!< 0x00000800 */
12461 #define ETH_DMAC1IER_ERIE                   ETH_DMAC1IER_ERIE_Msk                               /*!< Early Receive Interrupt Enable */
12462 #define ETH_DMAC1IER_FBEE_Pos               (12U)
12463 #define ETH_DMAC1IER_FBEE_Msk               (0x1U << ETH_DMAC1IER_FBEE_Pos)                     /*!< 0x00001000 */
12464 #define ETH_DMAC1IER_FBEE                   ETH_DMAC1IER_FBEE_Msk                               /*!< Fatal Bus Error Enable */
12465 #define ETH_DMAC1IER_CDEE_Pos               (13U)
12466 #define ETH_DMAC1IER_CDEE_Msk               (0x1U << ETH_DMAC1IER_CDEE_Pos)                     /*!< 0x00002000 */
12467 #define ETH_DMAC1IER_CDEE                   ETH_DMAC1IER_CDEE_Msk                               /*!< Context Descriptor Error Enable */
12468 #define ETH_DMAC1IER_AIE_Pos                (14U)
12469 #define ETH_DMAC1IER_AIE_Msk                (0x1U << ETH_DMAC1IER_AIE_Pos)                      /*!< 0x00004000 */
12470 #define ETH_DMAC1IER_AIE                    ETH_DMAC1IER_AIE_Msk                                /*!< Abnormal Interrupt Summary Enable */
12471 #define ETH_DMAC1IER_NIE_Pos                (15U)
12472 #define ETH_DMAC1IER_NIE_Msk                (0x1U << ETH_DMAC1IER_NIE_Pos)                      /*!< 0x00008000 */
12473 #define ETH_DMAC1IER_NIE                    ETH_DMAC1IER_NIE_Msk                                /*!< Normal Interrupt Summary Enable */
12474 
12475 /************  Bit definition for ETH_DMAC1SFCSR register  *************/
12476 #define ETH_DMAC1SFCSR_ESC_Pos              (0U)
12477 #define ETH_DMAC1SFCSR_ESC_Msk              (0x1U << ETH_DMAC1SFCSR_ESC_Pos)                    /*!< 0x00000001 */
12478 #define ETH_DMAC1SFCSR_ESC                  ETH_DMAC1SFCSR_ESC_Msk                              /*!< Enable Slot Comparison */
12479 #define ETH_DMAC1SFCSR_ASC_Pos              (1U)
12480 #define ETH_DMAC1SFCSR_ASC_Msk              (0x1U << ETH_DMAC1SFCSR_ASC_Pos)                    /*!< 0x00000002 */
12481 #define ETH_DMAC1SFCSR_ASC                  ETH_DMAC1SFCSR_ASC_Msk                              /*!< Advance Slot Check */
12482 #define ETH_DMAC1SFCSR_RSN_Pos              (16U)
12483 #define ETH_DMAC1SFCSR_RSN_Msk              (0xFU << ETH_DMAC1SFCSR_RSN_Pos)                    /*!< 0x000F0000 */
12484 #define ETH_DMAC1SFCSR_RSN                  ETH_DMAC1SFCSR_RSN_Msk                              /*!< Reference Slot Number */
12485 #define ETH_DMAC1SFCSR_RSN_0                (0x1U << ETH_DMAC1SFCSR_RSN_Pos)                /*!< 0x00010000 */
12486 #define ETH_DMAC1SFCSR_RSN_1                (0x2U << ETH_DMAC1SFCSR_RSN_Pos)                /*!< 0x00020000 */
12487 #define ETH_DMAC1SFCSR_RSN_2                (0x4U << ETH_DMAC1SFCSR_RSN_Pos)                /*!< 0x00040000 */
12488 #define ETH_DMAC1SFCSR_RSN_3                (0x8U << ETH_DMAC1SFCSR_RSN_Pos)                /*!< 0x00080000 */
12489 
12490 /************  Bit definition for ETH_DMAC1CATXDR register  ************/
12491 #define ETH_DMAC1CATXDR_CURTDESAPTR_Pos     (0U)
12492 #define ETH_DMAC1CATXDR_CURTDESAPTR_Msk     (0xFFFFFFFFU << ETH_DMAC1CATXDR_CURTDESAPTR_Pos)    /*!< 0xFFFFFFFF */
12493 #define ETH_DMAC1CATXDR_CURTDESAPTR         ETH_DMAC1CATXDR_CURTDESAPTR_Msk                     /*!< Application Transmit Descriptor Address Pointer */
12494 #define ETH_DMAC1CATXDR_CURTDESAPTR_0       (0x1U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos)           /*!< 0x00000001 */
12495 #define ETH_DMAC1CATXDR_CURTDESAPTR_1       (0x2U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos)           /*!< 0x00000002 */
12496 #define ETH_DMAC1CATXDR_CURTDESAPTR_2       (0x4U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos)           /*!< 0x00000004 */
12497 #define ETH_DMAC1CATXDR_CURTDESAPTR_3       (0x8U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos)           /*!< 0x00000008 */
12498 #define ETH_DMAC1CATXDR_CURTDESAPTR_4       (0x10U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos)          /*!< 0x00000010 */
12499 #define ETH_DMAC1CATXDR_CURTDESAPTR_5       (0x20U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos)          /*!< 0x00000020 */
12500 #define ETH_DMAC1CATXDR_CURTDESAPTR_6       (0x40U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos)          /*!< 0x00000040 */
12501 #define ETH_DMAC1CATXDR_CURTDESAPTR_7       (0x80U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos)          /*!< 0x00000080 */
12502 #define ETH_DMAC1CATXDR_CURTDESAPTR_8       (0x100U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos)         /*!< 0x00000100 */
12503 #define ETH_DMAC1CATXDR_CURTDESAPTR_9       (0x200U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos)         /*!< 0x00000200 */
12504 #define ETH_DMAC1CATXDR_CURTDESAPTR_10      (0x400U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos)         /*!< 0x00000400 */
12505 #define ETH_DMAC1CATXDR_CURTDESAPTR_11      (0x800U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos)         /*!< 0x00000800 */
12506 #define ETH_DMAC1CATXDR_CURTDESAPTR_12      (0x1000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos)        /*!< 0x00001000 */
12507 #define ETH_DMAC1CATXDR_CURTDESAPTR_13      (0x2000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos)        /*!< 0x00002000 */
12508 #define ETH_DMAC1CATXDR_CURTDESAPTR_14      (0x4000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos)        /*!< 0x00004000 */
12509 #define ETH_DMAC1CATXDR_CURTDESAPTR_15      (0x8000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos)        /*!< 0x00008000 */
12510 #define ETH_DMAC1CATXDR_CURTDESAPTR_16      (0x10000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos)       /*!< 0x00010000 */
12511 #define ETH_DMAC1CATXDR_CURTDESAPTR_17      (0x20000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos)       /*!< 0x00020000 */
12512 #define ETH_DMAC1CATXDR_CURTDESAPTR_18      (0x40000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos)       /*!< 0x00040000 */
12513 #define ETH_DMAC1CATXDR_CURTDESAPTR_19      (0x80000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos)       /*!< 0x00080000 */
12514 #define ETH_DMAC1CATXDR_CURTDESAPTR_20      (0x100000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos)      /*!< 0x00100000 */
12515 #define ETH_DMAC1CATXDR_CURTDESAPTR_21      (0x200000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos)      /*!< 0x00200000 */
12516 #define ETH_DMAC1CATXDR_CURTDESAPTR_22      (0x400000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos)      /*!< 0x00400000 */
12517 #define ETH_DMAC1CATXDR_CURTDESAPTR_23      (0x800000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos)      /*!< 0x00800000 */
12518 #define ETH_DMAC1CATXDR_CURTDESAPTR_24      (0x1000000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos)     /*!< 0x01000000 */
12519 #define ETH_DMAC1CATXDR_CURTDESAPTR_25      (0x2000000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos)     /*!< 0x02000000 */
12520 #define ETH_DMAC1CATXDR_CURTDESAPTR_26      (0x4000000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos)     /*!< 0x04000000 */
12521 #define ETH_DMAC1CATXDR_CURTDESAPTR_27      (0x8000000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos)     /*!< 0x08000000 */
12522 #define ETH_DMAC1CATXDR_CURTDESAPTR_28      (0x10000000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos)    /*!< 0x10000000 */
12523 #define ETH_DMAC1CATXDR_CURTDESAPTR_29      (0x20000000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos)    /*!< 0x20000000 */
12524 #define ETH_DMAC1CATXDR_CURTDESAPTR_30      (0x40000000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos)    /*!< 0x40000000 */
12525 #define ETH_DMAC1CATXDR_CURTDESAPTR_31      (0x80000000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos)    /*!< 0x80000000 */
12526 
12527 /************  Bit definition for ETH_DMAC1CATXBR register  ************/
12528 #define ETH_DMAC1CATXBR_CURTBUFAPTR_Pos     (0U)
12529 #define ETH_DMAC1CATXBR_CURTBUFAPTR_Msk     (0xFFFFFFFFU << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos)    /*!< 0xFFFFFFFF */
12530 #define ETH_DMAC1CATXBR_CURTBUFAPTR         ETH_DMAC1CATXBR_CURTBUFAPTR_Msk                     /*!< Application Transmit Buffer Address Pointer */
12531 #define ETH_DMAC1CATXBR_CURTBUFAPTR_0       (0x1U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos)           /*!< 0x00000001 */
12532 #define ETH_DMAC1CATXBR_CURTBUFAPTR_1       (0x2U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos)           /*!< 0x00000002 */
12533 #define ETH_DMAC1CATXBR_CURTBUFAPTR_2       (0x4U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos)           /*!< 0x00000004 */
12534 #define ETH_DMAC1CATXBR_CURTBUFAPTR_3       (0x8U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos)           /*!< 0x00000008 */
12535 #define ETH_DMAC1CATXBR_CURTBUFAPTR_4       (0x10U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos)          /*!< 0x00000010 */
12536 #define ETH_DMAC1CATXBR_CURTBUFAPTR_5       (0x20U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos)          /*!< 0x00000020 */
12537 #define ETH_DMAC1CATXBR_CURTBUFAPTR_6       (0x40U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos)          /*!< 0x00000040 */
12538 #define ETH_DMAC1CATXBR_CURTBUFAPTR_7       (0x80U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos)          /*!< 0x00000080 */
12539 #define ETH_DMAC1CATXBR_CURTBUFAPTR_8       (0x100U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos)         /*!< 0x00000100 */
12540 #define ETH_DMAC1CATXBR_CURTBUFAPTR_9       (0x200U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos)         /*!< 0x00000200 */
12541 #define ETH_DMAC1CATXBR_CURTBUFAPTR_10      (0x400U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos)         /*!< 0x00000400 */
12542 #define ETH_DMAC1CATXBR_CURTBUFAPTR_11      (0x800U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos)         /*!< 0x00000800 */
12543 #define ETH_DMAC1CATXBR_CURTBUFAPTR_12      (0x1000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos)        /*!< 0x00001000 */
12544 #define ETH_DMAC1CATXBR_CURTBUFAPTR_13      (0x2000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos)        /*!< 0x00002000 */
12545 #define ETH_DMAC1CATXBR_CURTBUFAPTR_14      (0x4000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos)        /*!< 0x00004000 */
12546 #define ETH_DMAC1CATXBR_CURTBUFAPTR_15      (0x8000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos)        /*!< 0x00008000 */
12547 #define ETH_DMAC1CATXBR_CURTBUFAPTR_16      (0x10000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos)       /*!< 0x00010000 */
12548 #define ETH_DMAC1CATXBR_CURTBUFAPTR_17      (0x20000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos)       /*!< 0x00020000 */
12549 #define ETH_DMAC1CATXBR_CURTBUFAPTR_18      (0x40000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos)       /*!< 0x00040000 */
12550 #define ETH_DMAC1CATXBR_CURTBUFAPTR_19      (0x80000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos)       /*!< 0x00080000 */
12551 #define ETH_DMAC1CATXBR_CURTBUFAPTR_20      (0x100000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos)      /*!< 0x00100000 */
12552 #define ETH_DMAC1CATXBR_CURTBUFAPTR_21      (0x200000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos)      /*!< 0x00200000 */
12553 #define ETH_DMAC1CATXBR_CURTBUFAPTR_22      (0x400000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos)      /*!< 0x00400000 */
12554 #define ETH_DMAC1CATXBR_CURTBUFAPTR_23      (0x800000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos)      /*!< 0x00800000 */
12555 #define ETH_DMAC1CATXBR_CURTBUFAPTR_24      (0x1000000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos)     /*!< 0x01000000 */
12556 #define ETH_DMAC1CATXBR_CURTBUFAPTR_25      (0x2000000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos)     /*!< 0x02000000 */
12557 #define ETH_DMAC1CATXBR_CURTBUFAPTR_26      (0x4000000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos)     /*!< 0x04000000 */
12558 #define ETH_DMAC1CATXBR_CURTBUFAPTR_27      (0x8000000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos)     /*!< 0x08000000 */
12559 #define ETH_DMAC1CATXBR_CURTBUFAPTR_28      (0x10000000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos)    /*!< 0x10000000 */
12560 #define ETH_DMAC1CATXBR_CURTBUFAPTR_29      (0x20000000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos)    /*!< 0x20000000 */
12561 #define ETH_DMAC1CATXBR_CURTBUFAPTR_30      (0x40000000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos)    /*!< 0x40000000 */
12562 #define ETH_DMAC1CATXBR_CURTBUFAPTR_31      (0x80000000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos)    /*!< 0x80000000 */
12563 
12564 /**************  Bit definition for ETH_DMAC1SR register  **************/
12565 #define ETH_DMAC1SR_TI_Pos                  (0U)
12566 #define ETH_DMAC1SR_TI_Msk                  (0x1U << ETH_DMAC1SR_TI_Pos)                        /*!< 0x00000001 */
12567 #define ETH_DMAC1SR_TI                      ETH_DMAC1SR_TI_Msk                                  /*!< Transmit Interrupt */
12568 #define ETH_DMAC1SR_TPS_Pos                 (1U)
12569 #define ETH_DMAC1SR_TPS_Msk                 (0x1U << ETH_DMAC1SR_TPS_Pos)                       /*!< 0x00000002 */
12570 #define ETH_DMAC1SR_TPS                     ETH_DMAC1SR_TPS_Msk                                 /*!< Transmit Process Stopped */
12571 #define ETH_DMAC1SR_TBU_Pos                 (2U)
12572 #define ETH_DMAC1SR_TBU_Msk                 (0x1U << ETH_DMAC1SR_TBU_Pos)                       /*!< 0x00000004 */
12573 #define ETH_DMAC1SR_TBU                     ETH_DMAC1SR_TBU_Msk                                 /*!< Transmit Buffer Unavailable */
12574 #define ETH_DMAC1SR_RI_Pos                  (6U)
12575 #define ETH_DMAC1SR_RI_Msk                  (0x1U << ETH_DMAC1SR_RI_Pos)                        /*!< 0x00000040 */
12576 #define ETH_DMAC1SR_RI                      ETH_DMAC1SR_RI_Msk                                  /*!< Receive Interrupt */
12577 #define ETH_DMAC1SR_RBU_Pos                 (7U)
12578 #define ETH_DMAC1SR_RBU_Msk                 (0x1U << ETH_DMAC1SR_RBU_Pos)                       /*!< 0x00000080 */
12579 #define ETH_DMAC1SR_RBU                     ETH_DMAC1SR_RBU_Msk                                 /*!< Receive Buffer Unavailable */
12580 #define ETH_DMAC1SR_RPS_Pos                 (8U)
12581 #define ETH_DMAC1SR_RPS_Msk                 (0x1U << ETH_DMAC1SR_RPS_Pos)                       /*!< 0x00000100 */
12582 #define ETH_DMAC1SR_RPS                     ETH_DMAC1SR_RPS_Msk                                 /*!< Receive Process Stopped */
12583 #define ETH_DMAC1SR_RWT_Pos                 (9U)
12584 #define ETH_DMAC1SR_RWT_Msk                 (0x1U << ETH_DMAC1SR_RWT_Pos)                       /*!< 0x00000200 */
12585 #define ETH_DMAC1SR_RWT                     ETH_DMAC1SR_RWT_Msk                                 /*!< Receive Watchdog Timeout */
12586 #define ETH_DMAC1SR_ETI_Pos                 (10U)
12587 #define ETH_DMAC1SR_ETI_Msk                 (0x1U << ETH_DMAC1SR_ETI_Pos)                       /*!< 0x00000400 */
12588 #define ETH_DMAC1SR_ETI                     ETH_DMAC1SR_ETI_Msk                                 /*!< Early Transmit Interrupt */
12589 #define ETH_DMAC1SR_ERI_Pos                 (11U)
12590 #define ETH_DMAC1SR_ERI_Msk                 (0x1U << ETH_DMAC1SR_ERI_Pos)                       /*!< 0x00000800 */
12591 #define ETH_DMAC1SR_ERI                     ETH_DMAC1SR_ERI_Msk                                 /*!< Early Receive Interrupt */
12592 #define ETH_DMAC1SR_FBE_Pos                 (12U)
12593 #define ETH_DMAC1SR_FBE_Msk                 (0x1U << ETH_DMAC1SR_FBE_Pos)                       /*!< 0x00001000 */
12594 #define ETH_DMAC1SR_FBE                     ETH_DMAC1SR_FBE_Msk                                 /*!< Fatal Bus Error */
12595 #define ETH_DMAC1SR_CDE_Pos                 (13U)
12596 #define ETH_DMAC1SR_CDE_Msk                 (0x1U << ETH_DMAC1SR_CDE_Pos)                       /*!< 0x00002000 */
12597 #define ETH_DMAC1SR_CDE                     ETH_DMAC1SR_CDE_Msk                                 /*!< Context Descriptor Error */
12598 #define ETH_DMAC1SR_AIS_Pos                 (14U)
12599 #define ETH_DMAC1SR_AIS_Msk                 (0x1U << ETH_DMAC1SR_AIS_Pos)                       /*!< 0x00004000 */
12600 #define ETH_DMAC1SR_AIS                     ETH_DMAC1SR_AIS_Msk                                 /*!< Abnormal Interrupt Summary */
12601 #define ETH_DMAC1SR_NIS_Pos                 (15U)
12602 #define ETH_DMAC1SR_NIS_Msk                 (0x1U << ETH_DMAC1SR_NIS_Pos)                       /*!< 0x00008000 */
12603 #define ETH_DMAC1SR_NIS                     ETH_DMAC1SR_NIS_Msk                                 /*!< Normal Interrupt Summary */
12604 #define ETH_DMAC1SR_TEB_Pos                 (16U)
12605 #define ETH_DMAC1SR_TEB_Msk                 (0x7U << ETH_DMAC1SR_TEB_Pos)                       /*!< 0x00070000 */
12606 #define ETH_DMAC1SR_TEB                     ETH_DMAC1SR_TEB_Msk                                 /*!< Tx DMA Error Bits */
12607 #define ETH_DMAC1SR_TEB_0                   (0x1U << ETH_DMAC1SR_TEB_Pos)                   /*!< 0x00010000 */
12608 #define ETH_DMAC1SR_TEB_1                   (0x2U << ETH_DMAC1SR_TEB_Pos)                   /*!< 0x00020000 */
12609 #define ETH_DMAC1SR_TEB_2                   (0x4U << ETH_DMAC1SR_TEB_Pos)                   /*!< 0x00040000 */
12610 #define ETH_DMAC1SR_REB_Pos                 (19U)
12611 #define ETH_DMAC1SR_REB_Msk                 (0x7U << ETH_DMAC1SR_REB_Pos)                       /*!< 0x00380000 */
12612 #define ETH_DMAC1SR_REB                     ETH_DMAC1SR_REB_Msk                                 /*!< Rx DMA Error Bits */
12613 #define ETH_DMAC1SR_REB_0                   (0x1U << ETH_DMAC1SR_REB_Pos)                   /*!< 0x00080000 */
12614 #define ETH_DMAC1SR_REB_1                   (0x2U << ETH_DMAC1SR_REB_Pos)                  /*!< 0x00100000 */
12615 #define ETH_DMAC1SR_REB_2                   (0x4U << ETH_DMAC1SR_REB_Pos)                  /*!< 0x00200000 */
12616 
12617 /*************  Bit definition for ETH_DMAC1MFCR register  *************/
12618 #define ETH_DMAC1MFCR_MFC_Pos               (0U)
12619 #define ETH_DMAC1MFCR_MFC_Msk               (0x7FFU << ETH_DMAC1MFCR_MFC_Pos)                   /*!< 0x000007FF */
12620 #define ETH_DMAC1MFCR_MFC                   ETH_DMAC1MFCR_MFC_Msk                               /*!< Dropped Packet Counters */
12621 #define ETH_DMAC1MFCR_MFC_0                 (0x1U << ETH_DMAC1MFCR_MFC_Pos)                     /*!< 0x00000001 */
12622 #define ETH_DMAC1MFCR_MFC_1                 (0x2U << ETH_DMAC1MFCR_MFC_Pos)                     /*!< 0x00000002 */
12623 #define ETH_DMAC1MFCR_MFC_2                 (0x4U << ETH_DMAC1MFCR_MFC_Pos)                     /*!< 0x00000004 */
12624 #define ETH_DMAC1MFCR_MFC_3                 (0x8U << ETH_DMAC1MFCR_MFC_Pos)                     /*!< 0x00000008 */
12625 #define ETH_DMAC1MFCR_MFC_4                 (0x10U << ETH_DMAC1MFCR_MFC_Pos)                    /*!< 0x00000010 */
12626 #define ETH_DMAC1MFCR_MFC_5                 (0x20U << ETH_DMAC1MFCR_MFC_Pos)                    /*!< 0x00000020 */
12627 #define ETH_DMAC1MFCR_MFC_6                 (0x40U << ETH_DMAC1MFCR_MFC_Pos)                    /*!< 0x00000040 */
12628 #define ETH_DMAC1MFCR_MFC_7                 (0x80U << ETH_DMAC1MFCR_MFC_Pos)                    /*!< 0x00000080 */
12629 #define ETH_DMAC1MFCR_MFC_8                 (0x100U << ETH_DMAC1MFCR_MFC_Pos)                   /*!< 0x00000100 */
12630 #define ETH_DMAC1MFCR_MFC_9                 (0x200U << ETH_DMAC1MFCR_MFC_Pos)                   /*!< 0x00000200 */
12631 #define ETH_DMAC1MFCR_MFC_10                (0x400U << ETH_DMAC1MFCR_MFC_Pos)                   /*!< 0x00000400 */
12632 #define ETH_DMAC1MFCR_MFCO_Pos              (15U)
12633 #define ETH_DMAC1MFCR_MFCO_Msk              (0x1U << ETH_DMAC1MFCR_MFCO_Pos)                    /*!< 0x00008000 */
12634 #define ETH_DMAC1MFCR_MFCO                  ETH_DMAC1MFCR_MFCO_Msk                              /*!< Overflow status of the MFC Counter */
12635 
12636 
12637 /******************************************************************************/
12638 /*                                                                            */
12639 /*                             DMA Controller                                 */
12640 /*                                                                            */
12641 /******************************************************************************/
12642 /********************  Bits definition for DMA_SxCR register  *****************/
12643 #define DMA_SxCR_MBURST_Pos      (23U)
12644 #define DMA_SxCR_MBURST_Msk      (0x3U << DMA_SxCR_MBURST_Pos)                 /*!< 0x01800000 */
12645 #define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk
12646 #define DMA_SxCR_MBURST_0        (0x1U << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */
12647 #define DMA_SxCR_MBURST_1        (0x2U << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */
12648 #define DMA_SxCR_PBURST_Pos      (21U)
12649 #define DMA_SxCR_PBURST_Msk      (0x3U << DMA_SxCR_PBURST_Pos)                 /*!< 0x00600000 */
12650 #define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk
12651 #define DMA_SxCR_PBURST_0        (0x1U << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */
12652 #define DMA_SxCR_PBURST_1        (0x2U << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */
12653 #define DMA_SxCR_ACK_Pos         (20U)
12654 #define DMA_SxCR_ACK_Msk         (0x1U << DMA_SxCR_ACK_Pos)                    /*!< 0x00100000 */
12655 #define DMA_SxCR_ACK             DMA_SxCR_ACK_Msk
12656 #define DMA_SxCR_CT_Pos          (19U)
12657 #define DMA_SxCR_CT_Msk          (0x1U << DMA_SxCR_CT_Pos)                     /*!< 0x00080000 */
12658 #define DMA_SxCR_CT              DMA_SxCR_CT_Msk
12659 #define DMA_SxCR_DBM_Pos         (18U)
12660 #define DMA_SxCR_DBM_Msk         (0x1U << DMA_SxCR_DBM_Pos)                    /*!< 0x00040000 */
12661 #define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk
12662 #define DMA_SxCR_PL_Pos          (16U)
12663 #define DMA_SxCR_PL_Msk          (0x3U << DMA_SxCR_PL_Pos)                     /*!< 0x00030000 */
12664 #define DMA_SxCR_PL              DMA_SxCR_PL_Msk
12665 #define DMA_SxCR_PL_0            (0x1U << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */
12666 #define DMA_SxCR_PL_1            (0x2U << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */
12667 #define DMA_SxCR_PINCOS_Pos      (15U)
12668 #define DMA_SxCR_PINCOS_Msk      (0x1U << DMA_SxCR_PINCOS_Pos)                 /*!< 0x00008000 */
12669 #define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk
12670 #define DMA_SxCR_MSIZE_Pos       (13U)
12671 #define DMA_SxCR_MSIZE_Msk       (0x3U << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00006000 */
12672 #define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk
12673 #define DMA_SxCR_MSIZE_0         (0x1U << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */
12674 #define DMA_SxCR_MSIZE_1         (0x2U << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */
12675 #define DMA_SxCR_PSIZE_Pos       (11U)
12676 #define DMA_SxCR_PSIZE_Msk       (0x3U << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001800 */
12677 #define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk
12678 #define DMA_SxCR_PSIZE_0         (0x1U << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */
12679 #define DMA_SxCR_PSIZE_1         (0x2U << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */
12680 #define DMA_SxCR_MINC_Pos        (10U)
12681 #define DMA_SxCR_MINC_Msk        (0x1U << DMA_SxCR_MINC_Pos)                   /*!< 0x00000400 */
12682 #define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk
12683 #define DMA_SxCR_PINC_Pos        (9U)
12684 #define DMA_SxCR_PINC_Msk        (0x1U << DMA_SxCR_PINC_Pos)                   /*!< 0x00000200 */
12685 #define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk
12686 #define DMA_SxCR_CIRC_Pos        (8U)
12687 #define DMA_SxCR_CIRC_Msk        (0x1U << DMA_SxCR_CIRC_Pos)                   /*!< 0x00000100 */
12688 #define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk
12689 #define DMA_SxCR_DIR_Pos         (6U)
12690 #define DMA_SxCR_DIR_Msk         (0x3U << DMA_SxCR_DIR_Pos)                    /*!< 0x000000C0 */
12691 #define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk
12692 #define DMA_SxCR_DIR_0           (0x1U << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */
12693 #define DMA_SxCR_DIR_1           (0x2U << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */
12694 #define DMA_SxCR_PFCTRL_Pos      (5U)
12695 #define DMA_SxCR_PFCTRL_Msk      (0x1U << DMA_SxCR_PFCTRL_Pos)                 /*!< 0x00000020 */
12696 #define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk
12697 #define DMA_SxCR_TCIE_Pos        (4U)
12698 #define DMA_SxCR_TCIE_Msk        (0x1U << DMA_SxCR_TCIE_Pos)                   /*!< 0x00000010 */
12699 #define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk
12700 #define DMA_SxCR_HTIE_Pos        (3U)
12701 #define DMA_SxCR_HTIE_Msk        (0x1U << DMA_SxCR_HTIE_Pos)                   /*!< 0x00000008 */
12702 #define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk
12703 #define DMA_SxCR_TEIE_Pos        (2U)
12704 #define DMA_SxCR_TEIE_Msk        (0x1U << DMA_SxCR_TEIE_Pos)                   /*!< 0x00000004 */
12705 #define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk
12706 #define DMA_SxCR_DMEIE_Pos       (1U)
12707 #define DMA_SxCR_DMEIE_Msk       (0x1U << DMA_SxCR_DMEIE_Pos)                  /*!< 0x00000002 */
12708 #define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk
12709 #define DMA_SxCR_EN_Pos          (0U)
12710 #define DMA_SxCR_EN_Msk          (0x1U << DMA_SxCR_EN_Pos)                     /*!< 0x00000001 */
12711 #define DMA_SxCR_EN              DMA_SxCR_EN_Msk
12712 
12713 /********************  Bits definition for DMA_SxCNDTR register  **************/
12714 #define DMA_SxNDT_Pos            (0U)
12715 #define DMA_SxNDT_Msk            (0xFFFFU << DMA_SxNDT_Pos)                    /*!< 0x0000FFFF */
12716 #define DMA_SxNDT                DMA_SxNDT_Msk
12717 #define DMA_SxNDT_0              (0x0001U << DMA_SxNDT_Pos)                    /*!< 0x00000001 */
12718 #define DMA_SxNDT_1              (0x0002U << DMA_SxNDT_Pos)                    /*!< 0x00000002 */
12719 #define DMA_SxNDT_2              (0x0004U << DMA_SxNDT_Pos)                    /*!< 0x00000004 */
12720 #define DMA_SxNDT_3              (0x0008U << DMA_SxNDT_Pos)                    /*!< 0x00000008 */
12721 #define DMA_SxNDT_4              (0x0010U << DMA_SxNDT_Pos)                    /*!< 0x00000010 */
12722 #define DMA_SxNDT_5              (0x0020U << DMA_SxNDT_Pos)                    /*!< 0x00000020 */
12723 #define DMA_SxNDT_6              (0x0040U << DMA_SxNDT_Pos)                    /*!< 0x00000040 */
12724 #define DMA_SxNDT_7              (0x0080U << DMA_SxNDT_Pos)                    /*!< 0x00000080 */
12725 #define DMA_SxNDT_8              (0x0100U << DMA_SxNDT_Pos)                    /*!< 0x00000100 */
12726 #define DMA_SxNDT_9              (0x0200U << DMA_SxNDT_Pos)                    /*!< 0x00000200 */
12727 #define DMA_SxNDT_10             (0x0400U << DMA_SxNDT_Pos)                    /*!< 0x00000400 */
12728 #define DMA_SxNDT_11             (0x0800U << DMA_SxNDT_Pos)                    /*!< 0x00000800 */
12729 #define DMA_SxNDT_12             (0x1000U << DMA_SxNDT_Pos)                    /*!< 0x00001000 */
12730 #define DMA_SxNDT_13             (0x2000U << DMA_SxNDT_Pos)                    /*!< 0x00002000 */
12731 #define DMA_SxNDT_14             (0x4000U << DMA_SxNDT_Pos)                    /*!< 0x00004000 */
12732 #define DMA_SxNDT_15             (0x8000U << DMA_SxNDT_Pos)                    /*!< 0x00008000 */
12733 
12734 /********************  Bits definition for DMA_SxFCR register  ****************/
12735 #define DMA_SxFCR_FEIE_Pos       (7U)
12736 #define DMA_SxFCR_FEIE_Msk       (0x1U << DMA_SxFCR_FEIE_Pos)                  /*!< 0x00000080 */
12737 #define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk
12738 #define DMA_SxFCR_FS_Pos         (3U)
12739 #define DMA_SxFCR_FS_Msk         (0x7U << DMA_SxFCR_FS_Pos)                    /*!< 0x00000038 */
12740 #define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk
12741 #define DMA_SxFCR_FS_0           (0x1U << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */
12742 #define DMA_SxFCR_FS_1           (0x2U << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */
12743 #define DMA_SxFCR_FS_2           (0x4U << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */
12744 #define DMA_SxFCR_DMDIS_Pos      (2U)
12745 #define DMA_SxFCR_DMDIS_Msk      (0x1U << DMA_SxFCR_DMDIS_Pos)                 /*!< 0x00000004 */
12746 #define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk
12747 #define DMA_SxFCR_FTH_Pos        (0U)
12748 #define DMA_SxFCR_FTH_Msk        (0x3U << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000003 */
12749 #define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk
12750 #define DMA_SxFCR_FTH_0          (0x1U << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */
12751 #define DMA_SxFCR_FTH_1          (0x2U << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */
12752 
12753 /******************  Bit definition for DMA_CPAR register  ********************/
12754 #define DMA_SxPAR_PA_Pos         (0U)
12755 #define DMA_SxPAR_PA_Msk         (0xFFFFFFFFU << DMA_SxPAR_PA_Pos)             /*!< 0xFFFFFFFF */
12756 #define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */
12757 
12758 /******************  Bit definition for DMA_CMAR register  ********************/
12759 #define DMA_SxM0AR_M0A_Pos        (0U)
12760 #define DMA_SxM0AR_M0A_Msk        (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos)            /*!< 0xFFFFFFFF */
12761 #define DMA_SxM0AR_M0A            DMA_SxM0AR_M0A_Msk                             /*!< Memory Address    */
12762 #define DMA_SxM1AR_M1A_Pos        (0U)
12763 #define DMA_SxM1AR_M1A_Msk        (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos)            /*!< 0xFFFFFFFF */
12764 #define DMA_SxM1AR_M1A            DMA_SxM1AR_M1A_Msk                             /*!< Memory Address    */
12765 
12766 /********************  Bits definition for DMA_LISR register  *****************/
12767 #define DMA_LISR_TCIF3_Pos       (27U)
12768 #define DMA_LISR_TCIF3_Msk       (0x1U << DMA_LISR_TCIF3_Pos)                  /*!< 0x08000000 */
12769 #define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk
12770 #define DMA_LISR_HTIF3_Pos       (26U)
12771 #define DMA_LISR_HTIF3_Msk       (0x1U << DMA_LISR_HTIF3_Pos)                  /*!< 0x04000000 */
12772 #define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk
12773 #define DMA_LISR_TEIF3_Pos       (25U)
12774 #define DMA_LISR_TEIF3_Msk       (0x1U << DMA_LISR_TEIF3_Pos)                  /*!< 0x02000000 */
12775 #define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk
12776 #define DMA_LISR_DMEIF3_Pos      (24U)
12777 #define DMA_LISR_DMEIF3_Msk      (0x1U << DMA_LISR_DMEIF3_Pos)                 /*!< 0x01000000 */
12778 #define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk
12779 #define DMA_LISR_FEIF3_Pos       (22U)
12780 #define DMA_LISR_FEIF3_Msk       (0x1U << DMA_LISR_FEIF3_Pos)                  /*!< 0x00400000 */
12781 #define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk
12782 #define DMA_LISR_TCIF2_Pos       (21U)
12783 #define DMA_LISR_TCIF2_Msk       (0x1U << DMA_LISR_TCIF2_Pos)                  /*!< 0x00200000 */
12784 #define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk
12785 #define DMA_LISR_HTIF2_Pos       (20U)
12786 #define DMA_LISR_HTIF2_Msk       (0x1U << DMA_LISR_HTIF2_Pos)                  /*!< 0x00100000 */
12787 #define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk
12788 #define DMA_LISR_TEIF2_Pos       (19U)
12789 #define DMA_LISR_TEIF2_Msk       (0x1U << DMA_LISR_TEIF2_Pos)                  /*!< 0x00080000 */
12790 #define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk
12791 #define DMA_LISR_DMEIF2_Pos      (18U)
12792 #define DMA_LISR_DMEIF2_Msk      (0x1U << DMA_LISR_DMEIF2_Pos)                 /*!< 0x00040000 */
12793 #define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk
12794 #define DMA_LISR_FEIF2_Pos       (16U)
12795 #define DMA_LISR_FEIF2_Msk       (0x1U << DMA_LISR_FEIF2_Pos)                  /*!< 0x00010000 */
12796 #define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk
12797 #define DMA_LISR_TCIF1_Pos       (11U)
12798 #define DMA_LISR_TCIF1_Msk       (0x1U << DMA_LISR_TCIF1_Pos)                  /*!< 0x00000800 */
12799 #define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk
12800 #define DMA_LISR_HTIF1_Pos       (10U)
12801 #define DMA_LISR_HTIF1_Msk       (0x1U << DMA_LISR_HTIF1_Pos)                  /*!< 0x00000400 */
12802 #define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk
12803 #define DMA_LISR_TEIF1_Pos       (9U)
12804 #define DMA_LISR_TEIF1_Msk       (0x1U << DMA_LISR_TEIF1_Pos)                  /*!< 0x00000200 */
12805 #define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk
12806 #define DMA_LISR_DMEIF1_Pos      (8U)
12807 #define DMA_LISR_DMEIF1_Msk      (0x1U << DMA_LISR_DMEIF1_Pos)                 /*!< 0x00000100 */
12808 #define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk
12809 #define DMA_LISR_FEIF1_Pos       (6U)
12810 #define DMA_LISR_FEIF1_Msk       (0x1U << DMA_LISR_FEIF1_Pos)                  /*!< 0x00000040 */
12811 #define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk
12812 #define DMA_LISR_TCIF0_Pos       (5U)
12813 #define DMA_LISR_TCIF0_Msk       (0x1U << DMA_LISR_TCIF0_Pos)                  /*!< 0x00000020 */
12814 #define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk
12815 #define DMA_LISR_HTIF0_Pos       (4U)
12816 #define DMA_LISR_HTIF0_Msk       (0x1U << DMA_LISR_HTIF0_Pos)                  /*!< 0x00000010 */
12817 #define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk
12818 #define DMA_LISR_TEIF0_Pos       (3U)
12819 #define DMA_LISR_TEIF0_Msk       (0x1U << DMA_LISR_TEIF0_Pos)                  /*!< 0x00000008 */
12820 #define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk
12821 #define DMA_LISR_DMEIF0_Pos      (2U)
12822 #define DMA_LISR_DMEIF0_Msk      (0x1U << DMA_LISR_DMEIF0_Pos)                 /*!< 0x00000004 */
12823 #define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk
12824 #define DMA_LISR_FEIF0_Pos       (0U)
12825 #define DMA_LISR_FEIF0_Msk       (0x1U << DMA_LISR_FEIF0_Pos)                  /*!< 0x00000001 */
12826 #define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk
12827 
12828 /********************  Bits definition for DMA_HISR register  *****************/
12829 #define DMA_HISR_TCIF7_Pos       (27U)
12830 #define DMA_HISR_TCIF7_Msk       (0x1U << DMA_HISR_TCIF7_Pos)                  /*!< 0x08000000 */
12831 #define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk
12832 #define DMA_HISR_HTIF7_Pos       (26U)
12833 #define DMA_HISR_HTIF7_Msk       (0x1U << DMA_HISR_HTIF7_Pos)                  /*!< 0x04000000 */
12834 #define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk
12835 #define DMA_HISR_TEIF7_Pos       (25U)
12836 #define DMA_HISR_TEIF7_Msk       (0x1U << DMA_HISR_TEIF7_Pos)                  /*!< 0x02000000 */
12837 #define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk
12838 #define DMA_HISR_DMEIF7_Pos      (24U)
12839 #define DMA_HISR_DMEIF7_Msk      (0x1U << DMA_HISR_DMEIF7_Pos)                 /*!< 0x01000000 */
12840 #define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk
12841 #define DMA_HISR_FEIF7_Pos       (22U)
12842 #define DMA_HISR_FEIF7_Msk       (0x1U << DMA_HISR_FEIF7_Pos)                  /*!< 0x00400000 */
12843 #define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk
12844 #define DMA_HISR_TCIF6_Pos       (21U)
12845 #define DMA_HISR_TCIF6_Msk       (0x1U << DMA_HISR_TCIF6_Pos)                  /*!< 0x00200000 */
12846 #define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk
12847 #define DMA_HISR_HTIF6_Pos       (20U)
12848 #define DMA_HISR_HTIF6_Msk       (0x1U << DMA_HISR_HTIF6_Pos)                  /*!< 0x00100000 */
12849 #define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk
12850 #define DMA_HISR_TEIF6_Pos       (19U)
12851 #define DMA_HISR_TEIF6_Msk       (0x1U << DMA_HISR_TEIF6_Pos)                  /*!< 0x00080000 */
12852 #define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk
12853 #define DMA_HISR_DMEIF6_Pos      (18U)
12854 #define DMA_HISR_DMEIF6_Msk      (0x1U << DMA_HISR_DMEIF6_Pos)                 /*!< 0x00040000 */
12855 #define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk
12856 #define DMA_HISR_FEIF6_Pos       (16U)
12857 #define DMA_HISR_FEIF6_Msk       (0x1U << DMA_HISR_FEIF6_Pos)                  /*!< 0x00010000 */
12858 #define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk
12859 #define DMA_HISR_TCIF5_Pos       (11U)
12860 #define DMA_HISR_TCIF5_Msk       (0x1U << DMA_HISR_TCIF5_Pos)                  /*!< 0x00000800 */
12861 #define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk
12862 #define DMA_HISR_HTIF5_Pos       (10U)
12863 #define DMA_HISR_HTIF5_Msk       (0x1U << DMA_HISR_HTIF5_Pos)                  /*!< 0x00000400 */
12864 #define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk
12865 #define DMA_HISR_TEIF5_Pos       (9U)
12866 #define DMA_HISR_TEIF5_Msk       (0x1U << DMA_HISR_TEIF5_Pos)                  /*!< 0x00000200 */
12867 #define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk
12868 #define DMA_HISR_DMEIF5_Pos      (8U)
12869 #define DMA_HISR_DMEIF5_Msk      (0x1U << DMA_HISR_DMEIF5_Pos)                 /*!< 0x00000100 */
12870 #define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk
12871 #define DMA_HISR_FEIF5_Pos       (6U)
12872 #define DMA_HISR_FEIF5_Msk       (0x1U << DMA_HISR_FEIF5_Pos)                  /*!< 0x00000040 */
12873 #define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk
12874 #define DMA_HISR_TCIF4_Pos       (5U)
12875 #define DMA_HISR_TCIF4_Msk       (0x1U << DMA_HISR_TCIF4_Pos)                  /*!< 0x00000020 */
12876 #define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk
12877 #define DMA_HISR_HTIF4_Pos       (4U)
12878 #define DMA_HISR_HTIF4_Msk       (0x1U << DMA_HISR_HTIF4_Pos)                  /*!< 0x00000010 */
12879 #define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk
12880 #define DMA_HISR_TEIF4_Pos       (3U)
12881 #define DMA_HISR_TEIF4_Msk       (0x1U << DMA_HISR_TEIF4_Pos)                  /*!< 0x00000008 */
12882 #define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk
12883 #define DMA_HISR_DMEIF4_Pos      (2U)
12884 #define DMA_HISR_DMEIF4_Msk      (0x1U << DMA_HISR_DMEIF4_Pos)                 /*!< 0x00000004 */
12885 #define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk
12886 #define DMA_HISR_FEIF4_Pos       (0U)
12887 #define DMA_HISR_FEIF4_Msk       (0x1U << DMA_HISR_FEIF4_Pos)                  /*!< 0x00000001 */
12888 #define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk
12889 
12890 /********************  Bits definition for DMA_LIFCR register  ****************/
12891 #define DMA_LIFCR_CTCIF3_Pos     (27U)
12892 #define DMA_LIFCR_CTCIF3_Msk     (0x1U << DMA_LIFCR_CTCIF3_Pos)                /*!< 0x08000000 */
12893 #define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk
12894 #define DMA_LIFCR_CHTIF3_Pos     (26U)
12895 #define DMA_LIFCR_CHTIF3_Msk     (0x1U << DMA_LIFCR_CHTIF3_Pos)                /*!< 0x04000000 */
12896 #define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk
12897 #define DMA_LIFCR_CTEIF3_Pos     (25U)
12898 #define DMA_LIFCR_CTEIF3_Msk     (0x1U << DMA_LIFCR_CTEIF3_Pos)                /*!< 0x02000000 */
12899 #define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk
12900 #define DMA_LIFCR_CDMEIF3_Pos    (24U)
12901 #define DMA_LIFCR_CDMEIF3_Msk    (0x1U << DMA_LIFCR_CDMEIF3_Pos)               /*!< 0x01000000 */
12902 #define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk
12903 #define DMA_LIFCR_CFEIF3_Pos     (22U)
12904 #define DMA_LIFCR_CFEIF3_Msk     (0x1U << DMA_LIFCR_CFEIF3_Pos)                /*!< 0x00400000 */
12905 #define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk
12906 #define DMA_LIFCR_CTCIF2_Pos     (21U)
12907 #define DMA_LIFCR_CTCIF2_Msk     (0x1U << DMA_LIFCR_CTCIF2_Pos)                /*!< 0x00200000 */
12908 #define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk
12909 #define DMA_LIFCR_CHTIF2_Pos     (20U)
12910 #define DMA_LIFCR_CHTIF2_Msk     (0x1U << DMA_LIFCR_CHTIF2_Pos)                /*!< 0x00100000 */
12911 #define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk
12912 #define DMA_LIFCR_CTEIF2_Pos     (19U)
12913 #define DMA_LIFCR_CTEIF2_Msk     (0x1U << DMA_LIFCR_CTEIF2_Pos)                /*!< 0x00080000 */
12914 #define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk
12915 #define DMA_LIFCR_CDMEIF2_Pos    (18U)
12916 #define DMA_LIFCR_CDMEIF2_Msk    (0x1U << DMA_LIFCR_CDMEIF2_Pos)               /*!< 0x00040000 */
12917 #define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk
12918 #define DMA_LIFCR_CFEIF2_Pos     (16U)
12919 #define DMA_LIFCR_CFEIF2_Msk     (0x1U << DMA_LIFCR_CFEIF2_Pos)                /*!< 0x00010000 */
12920 #define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk
12921 #define DMA_LIFCR_CTCIF1_Pos     (11U)
12922 #define DMA_LIFCR_CTCIF1_Msk     (0x1U << DMA_LIFCR_CTCIF1_Pos)                /*!< 0x00000800 */
12923 #define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk
12924 #define DMA_LIFCR_CHTIF1_Pos     (10U)
12925 #define DMA_LIFCR_CHTIF1_Msk     (0x1U << DMA_LIFCR_CHTIF1_Pos)                /*!< 0x00000400 */
12926 #define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk
12927 #define DMA_LIFCR_CTEIF1_Pos     (9U)
12928 #define DMA_LIFCR_CTEIF1_Msk     (0x1U << DMA_LIFCR_CTEIF1_Pos)                /*!< 0x00000200 */
12929 #define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk
12930 #define DMA_LIFCR_CDMEIF1_Pos    (8U)
12931 #define DMA_LIFCR_CDMEIF1_Msk    (0x1U << DMA_LIFCR_CDMEIF1_Pos)               /*!< 0x00000100 */
12932 #define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk
12933 #define DMA_LIFCR_CFEIF1_Pos     (6U)
12934 #define DMA_LIFCR_CFEIF1_Msk     (0x1U << DMA_LIFCR_CFEIF1_Pos)                /*!< 0x00000040 */
12935 #define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk
12936 #define DMA_LIFCR_CTCIF0_Pos     (5U)
12937 #define DMA_LIFCR_CTCIF0_Msk     (0x1U << DMA_LIFCR_CTCIF0_Pos)                /*!< 0x00000020 */
12938 #define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk
12939 #define DMA_LIFCR_CHTIF0_Pos     (4U)
12940 #define DMA_LIFCR_CHTIF0_Msk     (0x1U << DMA_LIFCR_CHTIF0_Pos)                /*!< 0x00000010 */
12941 #define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk
12942 #define DMA_LIFCR_CTEIF0_Pos     (3U)
12943 #define DMA_LIFCR_CTEIF0_Msk     (0x1U << DMA_LIFCR_CTEIF0_Pos)                /*!< 0x00000008 */
12944 #define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk
12945 #define DMA_LIFCR_CDMEIF0_Pos    (2U)
12946 #define DMA_LIFCR_CDMEIF0_Msk    (0x1U << DMA_LIFCR_CDMEIF0_Pos)               /*!< 0x00000004 */
12947 #define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk
12948 #define DMA_LIFCR_CFEIF0_Pos     (0U)
12949 #define DMA_LIFCR_CFEIF0_Msk     (0x1U << DMA_LIFCR_CFEIF0_Pos)                /*!< 0x00000001 */
12950 #define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk
12951 
12952 /********************  Bits definition for DMA_HIFCR  register  ****************/
12953 #define DMA_HIFCR_CTCIF7_Pos     (27U)
12954 #define DMA_HIFCR_CTCIF7_Msk     (0x1U << DMA_HIFCR_CTCIF7_Pos)                /*!< 0x08000000 */
12955 #define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk
12956 #define DMA_HIFCR_CHTIF7_Pos     (26U)
12957 #define DMA_HIFCR_CHTIF7_Msk     (0x1U << DMA_HIFCR_CHTIF7_Pos)                /*!< 0x04000000 */
12958 #define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk
12959 #define DMA_HIFCR_CTEIF7_Pos     (25U)
12960 #define DMA_HIFCR_CTEIF7_Msk     (0x1U << DMA_HIFCR_CTEIF7_Pos)                /*!< 0x02000000 */
12961 #define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk
12962 #define DMA_HIFCR_CDMEIF7_Pos    (24U)
12963 #define DMA_HIFCR_CDMEIF7_Msk    (0x1U << DMA_HIFCR_CDMEIF7_Pos)               /*!< 0x01000000 */
12964 #define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk
12965 #define DMA_HIFCR_CFEIF7_Pos     (22U)
12966 #define DMA_HIFCR_CFEIF7_Msk     (0x1U << DMA_HIFCR_CFEIF7_Pos)                /*!< 0x00400000 */
12967 #define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk
12968 #define DMA_HIFCR_CTCIF6_Pos     (21U)
12969 #define DMA_HIFCR_CTCIF6_Msk     (0x1U << DMA_HIFCR_CTCIF6_Pos)                /*!< 0x00200000 */
12970 #define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk
12971 #define DMA_HIFCR_CHTIF6_Pos     (20U)
12972 #define DMA_HIFCR_CHTIF6_Msk     (0x1U << DMA_HIFCR_CHTIF6_Pos)                /*!< 0x00100000 */
12973 #define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk
12974 #define DMA_HIFCR_CTEIF6_Pos     (19U)
12975 #define DMA_HIFCR_CTEIF6_Msk     (0x1U << DMA_HIFCR_CTEIF6_Pos)                /*!< 0x00080000 */
12976 #define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk
12977 #define DMA_HIFCR_CDMEIF6_Pos    (18U)
12978 #define DMA_HIFCR_CDMEIF6_Msk    (0x1U << DMA_HIFCR_CDMEIF6_Pos)               /*!< 0x00040000 */
12979 #define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk
12980 #define DMA_HIFCR_CFEIF6_Pos     (16U)
12981 #define DMA_HIFCR_CFEIF6_Msk     (0x1U << DMA_HIFCR_CFEIF6_Pos)                /*!< 0x00010000 */
12982 #define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk
12983 #define DMA_HIFCR_CTCIF5_Pos     (11U)
12984 #define DMA_HIFCR_CTCIF5_Msk     (0x1U << DMA_HIFCR_CTCIF5_Pos)                /*!< 0x00000800 */
12985 #define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk
12986 #define DMA_HIFCR_CHTIF5_Pos     (10U)
12987 #define DMA_HIFCR_CHTIF5_Msk     (0x1U << DMA_HIFCR_CHTIF5_Pos)                /*!< 0x00000400 */
12988 #define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk
12989 #define DMA_HIFCR_CTEIF5_Pos     (9U)
12990 #define DMA_HIFCR_CTEIF5_Msk     (0x1U << DMA_HIFCR_CTEIF5_Pos)                /*!< 0x00000200 */
12991 #define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk
12992 #define DMA_HIFCR_CDMEIF5_Pos    (8U)
12993 #define DMA_HIFCR_CDMEIF5_Msk    (0x1U << DMA_HIFCR_CDMEIF5_Pos)               /*!< 0x00000100 */
12994 #define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk
12995 #define DMA_HIFCR_CFEIF5_Pos     (6U)
12996 #define DMA_HIFCR_CFEIF5_Msk     (0x1U << DMA_HIFCR_CFEIF5_Pos)                /*!< 0x00000040 */
12997 #define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk
12998 #define DMA_HIFCR_CTCIF4_Pos     (5U)
12999 #define DMA_HIFCR_CTCIF4_Msk     (0x1U << DMA_HIFCR_CTCIF4_Pos)                /*!< 0x00000020 */
13000 #define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk
13001 #define DMA_HIFCR_CHTIF4_Pos     (4U)
13002 #define DMA_HIFCR_CHTIF4_Msk     (0x1U << DMA_HIFCR_CHTIF4_Pos)                /*!< 0x00000010 */
13003 #define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk
13004 #define DMA_HIFCR_CTEIF4_Pos     (3U)
13005 #define DMA_HIFCR_CTEIF4_Msk     (0x1U << DMA_HIFCR_CTEIF4_Pos)                /*!< 0x00000008 */
13006 #define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk
13007 #define DMA_HIFCR_CDMEIF4_Pos    (2U)
13008 #define DMA_HIFCR_CDMEIF4_Msk    (0x1U << DMA_HIFCR_CDMEIF4_Pos)               /*!< 0x00000004 */
13009 #define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk
13010 #define DMA_HIFCR_CFEIF4_Pos     (0U)
13011 #define DMA_HIFCR_CFEIF4_Msk     (0x1U << DMA_HIFCR_CFEIF4_Pos)                /*!< 0x00000001 */
13012 #define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk
13013 
13014 /**********************  Bit definition for DMA_HWCFGR2 register  ***************/
13015 #define DMA_HWCFGR2_FIFO_SIZE_Pos         (0U)
13016 #define DMA_HWCFGR2_FIFO_SIZE_Msk         (0x3U << DMA_HWCFGR2_FIFO_SIZE_Pos)          /*!< 0x00000003 */
13017 #define DMA_HWCFGR2_FIFO_SIZE              DMA_HWCFGR2_FIFO_SIZE_Msk                   /*!< FIFO size, common to all streams*/
13018 #define DMA_HWCFGR2_WRITE_BUFFERABLE_Pos  (4U)
13019 #define DMA_HWCFGR2_WRITE_BUFFERABLE_Msk  (0x1U << DMA_HWCFGR2_WRITE_BUFFERABLE_Pos)   /*!< 0x00000010 */
13020 #define DMA_HWCFGR2_WRITE_BUFFERABLE       DMA_HWCFGR2_WRITE_BUFFERABLE_Msk            /*!< Write bufferable*/
13021 #define DMA_HWCFGR2_CHSEL_WIDTH_Pos       (8U)
13022 #define DMA_HWCFGR2_CHSEL_WIDTH_Msk       (0x7U << DMA_HWCFGR2_CHSEL_WIDTH_Pos)        /*!< 0x00000700 */
13023 #define DMA_HWCFGR2_CHSEL_WIDTH            DMA_HWCFGR2_CHSEL_WIDTH_Msk                 /*!< width of the CHSEL field */
13024 
13025 /**********************  Bit definition for DMA_HWCFGR1 register  ***************/
13026 #define DMA_HWCFGR1_DMA_DEF0_Pos  (0U)
13027 #define DMA_HWCFGR1_DMA_DEF0_Msk  (0x3U << DMA_HWCFGR1_DMA_DEF0_Pos)          /*!< 0x00000003 */
13028 #define DMA_HWCFGR1_DMA_DEF0      DMA_HWCFGR1_DMA_DEF0_Msk                     /*!< Type of the stream 0 */
13029 #define DMA_HWCFGR1_DMA_DEF1_Pos  (4U)
13030 #define DMA_HWCFGR1_DMA_DEF1_Msk  (0x3U << DMA_HWCFGR1_DMA_DEF1_Pos)          /*!< 0x00000030 */
13031 #define DMA_HWCFGR1_DMA_DEF1      DMA_HWCFGR1_DMA_DEF1_Msk                     /*!< Type of the stream 1 */
13032 #define DMA_HWCFGR1_DMA_DEF2_Pos  (8U)
13033 #define DMA_HWCFGR1_DMA_DEF2_Msk  (0x3U << DMA_HWCFGR1_DMA_DEF2_Pos)          /*!< 0x00000300 */
13034 #define DMA_HWCFGR1_DMA_DEF2      DMA_HWCFGR1_DMA_DEF2_Msk                     /*!< Type of the stream 2 */
13035 #define DMA_HWCFGR1_DMA_DEF3_Pos  (12U)
13036 #define DMA_HWCFGR1_DMA_DEF3_Msk  (0x3U << DMA_HWCFGR1_DMA_DEF3_Pos)          /*!< 0x00003000 */
13037 #define DMA_HWCFGR1_DMA_DEF3      DMA_HWCFGR1_DMA_DEF3_Msk                     /*!< Type of the stream 3 */
13038 #define DMA_HWCFGR1_DMA_DEF4_Pos  (16U)
13039 #define DMA_HWCFGR1_DMA_DEF4_Msk  (0x3U << DMA_HWCFGR1_DMA_DEF4_Pos)          /*!< 0x00030000 */
13040 #define DMA_HWCFGR1_DMA_DEF4      DMA_HWCFGR1_DMA_DEF4_Msk                     /*!< Type of the stream 4 */
13041 #define DMA_HWCFGR1_DMA_DEF5_Pos  (20U)
13042 #define DMA_HWCFGR1_DMA_DEF5_Msk  (0x3U << DMA_HWCFGR1_DMA_DEF5_Pos)          /*!< 0x00300000 */
13043 #define DMA_HWCFGR1_DMA_DEF5      DMA_HWCFGR1_DMA_DEF5_Msk                     /*!< Type of the stream 5 */
13044 #define DMA_HWCFGR1_DMA_DEF6_Pos  (24U)
13045 #define DMA_HWCFGR1_DMA_DEF6_Msk  (0x3U << DMA_HWCFGR1_DMA_DEF6_Pos)          /*!< 0x03000000 */
13046 #define DMA_HWCFGR1_DMA_DEF6      DMA_HWCFGR1_DMA_DEF6_Msk                     /*!< Type of the stream 6 */
13047 #define DMA_HWCFGR1_DMA_DEF7_Pos  (28U)
13048 #define DMA_HWCFGR1_DMA_DEF7_Msk  (0x3U << DMA_HWCFGR1_DMA_DEF7_Pos)          /*!< 0x30000000 */
13049 #define DMA_HWCFGR1_DMA_DEF7      DMA_HWCFGR1_DMA_DEF7_Msk                     /*!< Type of the stream 7 */
13050 
13051 /**********************  Bit definition for DMA_VERR register  *****************/
13052 #define DMA_VERR_MINREV_Pos      (0U)
13053 #define DMA_VERR_MINREV_Msk      (0xFU << DMA_VERR_MINREV_Pos)               /*!< 0x0000000F */
13054 #define DMA_VERR_MINREV          DMA_VERR_MINREV_Msk                         /*!< Minor Revision number */
13055 #define DMA_VERR_MAJREV_Pos      (4U)
13056 #define DMA_VERR_MAJREV_Msk      (0xFU << DMA_VERR_MAJREV_Pos)               /*!< 0x000000F0 */
13057 #define DMA_VERR_MAJREV          DMA_VERR_MAJREV_Msk                         /*!< Major Revision number */
13058 
13059 /**********************  Bit definition for DMA_IPIDR register  ****************/
13060 #define DMA_IPIDR_ID_Pos         (0U)
13061 #define DMA_IPIDR_ID_Msk         (0xFFFFFFFFU << DMA_IPIDR_ID_Pos)         /*!< 0xFFFFFFFF */
13062 #define DMA_IPIDR_ID             DMA_IPIDR_ID_Msk                          /*!< IP Identification */
13063 
13064 /**********************  Bit definition for DMA_SIDR register  *****************/
13065 #define DMA_SIDR_SID_Pos         (0U)
13066 #define DMA_SIDR_SID_Msk         (0xFFFFFFFFU << DMA_SIDR_SID_Pos)           /*!< 0xFFFFFFFF */
13067 #define DMA_SIDR_SID             DMA_SIDR_SID_Msk                            /*!< IP size identification */
13068 
13069 /******************************************************************************/
13070 /*                                                                            */
13071 /*                             DMAMUX Controller                              */
13072 /*                                                                            */
13073 /******************************************************************************/
13074 /********************  Bits definition for DMAMUX_CxCR register  **************/
13075 #define DMAMUX_CxCR_DMAREQ_ID_Pos      (0U)
13076 #define DMAMUX_CxCR_DMAREQ_ID_Msk      (0xFFU << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x000000FF */
13077 #define DMAMUX_CxCR_DMAREQ_ID          DMAMUX_CxCR_DMAREQ_ID_Msk
13078 #define DMAMUX_CxCR_DMAREQ_ID_0        (0x01U << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000001 */
13079 #define DMAMUX_CxCR_DMAREQ_ID_1        (0x02U << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000002 */
13080 #define DMAMUX_CxCR_DMAREQ_ID_2        (0x04U << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000004 */
13081 #define DMAMUX_CxCR_DMAREQ_ID_3        (0x08U << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000008 */
13082 #define DMAMUX_CxCR_DMAREQ_ID_4        (0x10U << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000010 */
13083 #define DMAMUX_CxCR_DMAREQ_ID_5        (0x20U << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000020 */
13084 #define DMAMUX_CxCR_DMAREQ_ID_6        (0x40U << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000040 */
13085 #define DMAMUX_CxCR_DMAREQ_ID_7        (0x80U << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000080 */
13086 #define DMAMUX_CxCR_SOIE_Pos           (8U)
13087 #define DMAMUX_CxCR_SOIE_Msk           (0x1U << DMAMUX_CxCR_SOIE_Pos)          /*!< 0x00000100 */
13088 #define DMAMUX_CxCR_SOIE               DMAMUX_CxCR_SOIE_Msk
13089 #define DMAMUX_CxCR_EGE_Pos            (9U)
13090 #define DMAMUX_CxCR_EGE_Msk            (0x1U << DMAMUX_CxCR_EGE_Pos)           /*!< 0x00000200 */
13091 #define DMAMUX_CxCR_EGE                DMAMUX_CxCR_EGE_Msk
13092 #define DMAMUX_CxCR_SE_Pos             (16U)
13093 #define DMAMUX_CxCR_SE_Msk             (0x1U << DMAMUX_CxCR_SE_Pos)            /*!< 0x00010000 */
13094 #define DMAMUX_CxCR_SE                 DMAMUX_CxCR_SE_Msk
13095 #define DMAMUX_CxCR_SPOL_Pos           (17U)
13096 #define DMAMUX_CxCR_SPOL_Msk           (0x3U << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00060000 */
13097 #define DMAMUX_CxCR_SPOL               DMAMUX_CxCR_SPOL_Msk
13098 #define DMAMUX_CxCR_SPOL_0             (0x1U << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00020000 */
13099 #define DMAMUX_CxCR_SPOL_1             (0x2U << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00040000 */
13100 #define DMAMUX_CxCR_NBREQ_Pos          (19U)
13101 #define DMAMUX_CxCR_NBREQ_Msk          (0x1FU << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00F80000 */
13102 #define DMAMUX_CxCR_NBREQ              DMAMUX_CxCR_NBREQ_Msk
13103 #define DMAMUX_CxCR_NBREQ_0            (0x01U << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00080000 */
13104 #define DMAMUX_CxCR_NBREQ_1            (0x02U << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00100000 */
13105 #define DMAMUX_CxCR_NBREQ_2            (0x04U << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00200000 */
13106 #define DMAMUX_CxCR_NBREQ_3            (0x08U << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00400000 */
13107 #define DMAMUX_CxCR_NBREQ_4            (0x10U << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00800000 */
13108 #define DMAMUX_CxCR_SYNC_ID_Pos        (24U)
13109 #define DMAMUX_CxCR_SYNC_ID_Msk        (0x1FU << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x1F000000 */
13110 #define DMAMUX_CxCR_SYNC_ID            DMAMUX_CxCR_SYNC_ID_Msk
13111 #define DMAMUX_CxCR_SYNC_ID_0          (0x01U << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x01000000 */
13112 #define DMAMUX_CxCR_SYNC_ID_1          (0x02U << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x02000000 */
13113 #define DMAMUX_CxCR_SYNC_ID_2          (0x04U << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x04000000 */
13114 #define DMAMUX_CxCR_SYNC_ID_3          (0x08U << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x08000000 */
13115 #define DMAMUX_CxCR_SYNC_ID_4          (0x10U << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x10000000 */
13116 
13117 /********************  Bits definition for DMAMUX_CSR register  **************/
13118 #define DMAMUX_CSR_SOF0_Pos            (0U)
13119 #define DMAMUX_CSR_SOF0_Msk            (0x1U << DMAMUX_CSR_SOF0_Pos)           /*!< 0x00000001 */
13120 #define DMAMUX_CSR_SOF0                DMAMUX_CSR_SOF0_Msk
13121 #define DMAMUX_CSR_SOF1_Pos            (1U)
13122 #define DMAMUX_CSR_SOF1_Msk            (0x1U << DMAMUX_CSR_SOF1_Pos)           /*!< 0x00000002 */
13123 #define DMAMUX_CSR_SOF1                DMAMUX_CSR_SOF1_Msk
13124 #define DMAMUX_CSR_SOF2_Pos            (2U)
13125 #define DMAMUX_CSR_SOF2_Msk            (0x1U << DMAMUX_CSR_SOF2_Pos)           /*!< 0x00000004 */
13126 #define DMAMUX_CSR_SOF2                DMAMUX_CSR_SOF2_Msk
13127 #define DMAMUX_CSR_SOF3_Pos            (3U)
13128 #define DMAMUX_CSR_SOF3_Msk            (0x1U << DMAMUX_CSR_SOF3_Pos)           /*!< 0x00000008 */
13129 #define DMAMUX_CSR_SOF3                DMAMUX_CSR_SOF3_Msk
13130 #define DMAMUX_CSR_SOF4_Pos            (4U)
13131 #define DMAMUX_CSR_SOF4_Msk            (0x1U << DMAMUX_CSR_SOF4_Pos)           /*!< 0x00000010 */
13132 #define DMAMUX_CSR_SOF4                DMAMUX_CSR_SOF4_Msk
13133 #define DMAMUX_CSR_SOF5_Pos            (5U)
13134 #define DMAMUX_CSR_SOF5_Msk            (0x1U << DMAMUX_CSR_SOF5_Pos)           /*!< 0x00000020 */
13135 #define DMAMUX_CSR_SOF5                DMAMUX_CSR_SOF5_Msk
13136 #define DMAMUX_CSR_SOF6_Pos            (6U)
13137 #define DMAMUX_CSR_SOF6_Msk            (0x1U << DMAMUX_CSR_SOF6_Pos)           /*!< 0x00000040 */
13138 #define DMAMUX_CSR_SOF6                DMAMUX_CSR_SOF6_Msk
13139 #define DMAMUX_CSR_SOF7_Pos            (7U)
13140 #define DMAMUX_CSR_SOF7_Msk            (0x1U << DMAMUX_CSR_SOF7_Pos)           /*!< 0x00000080 */
13141 #define DMAMUX_CSR_SOF7                DMAMUX_CSR_SOF7_Msk
13142 #define DMAMUX_CSR_SOF8_Pos            (8U)
13143 #define DMAMUX_CSR_SOF8_Msk            (0x1U << DMAMUX_CSR_SOF8_Pos)           /*!< 0x00000100 */
13144 #define DMAMUX_CSR_SOF8                DMAMUX_CSR_SOF8_Msk
13145 #define DMAMUX_CSR_SOF9_Pos            (9U)
13146 #define DMAMUX_CSR_SOF9_Msk            (0x1U << DMAMUX_CSR_SOF9_Pos)           /*!< 0x00000200 */
13147 #define DMAMUX_CSR_SOF9                DMAMUX_CSR_SOF9_Msk
13148 #define DMAMUX_CSR_SOF10_Pos           (10U)
13149 #define DMAMUX_CSR_SOF10_Msk           (0x1U << DMAMUX_CSR_SOF10_Pos)          /*!< 0x00000400 */
13150 #define DMAMUX_CSR_SOF10               DMAMUX_CSR_SOF10_Msk
13151 #define DMAMUX_CSR_SOF11_Pos           (11U)
13152 #define DMAMUX_CSR_SOF11_Msk           (0x1U << DMAMUX_CSR_SOF11_Pos)          /*!< 0x00000800 */
13153 #define DMAMUX_CSR_SOF11               DMAMUX_CSR_SOF11_Msk
13154 #define DMAMUX_CSR_SOF12_Pos           (12U)
13155 #define DMAMUX_CSR_SOF12_Msk           (0x1U << DMAMUX_CSR_SOF12_Pos)          /*!< 0x00001000 */
13156 #define DMAMUX_CSR_SOF12               DMAMUX_CSR_SOF12_Msk
13157 #define DMAMUX_CSR_SOF13_Pos           (13U)
13158 #define DMAMUX_CSR_SOF13_Msk           (0x1U << DMAMUX_CSR_SOF13_Pos)          /*!< 0x00002000 */
13159 #define DMAMUX_CSR_SOF13               DMAMUX_CSR_SOF13_Msk
13160 #define DMAMUX_CSR_SOF14_Pos           (14U)
13161 #define DMAMUX_CSR_SOF14_Msk           (0x1U << DMAMUX_CSR_SOF14_Pos)          /*!< 0x00004000 */
13162 #define DMAMUX_CSR_SOF14               DMAMUX_CSR_SOF14_Msk
13163 #define DMAMUX_CSR_SOF15_Pos           (15U)
13164 #define DMAMUX_CSR_SOF15_Msk           (0x1U << DMAMUX_CSR_SOF15_Pos)          /*!< 0x00008000 */
13165 #define DMAMUX_CSR_SOF15               DMAMUX_CSR_SOF15_Msk
13166 
13167 /********************  Bits definition for DMAMUX_CFR register  **************/
13168 #define DMAMUX_CFR_CSOF0_Pos           (0U)
13169 #define DMAMUX_CFR_CSOF0_Msk           (0x1U << DMAMUX_CFR_CSOF0_Pos)          /*!< 0x00000001 */
13170 #define DMAMUX_CFR_CSOF0               DMAMUX_CFR_CSOF0_Msk
13171 #define DMAMUX_CFR_CSOF1_Pos           (1U)
13172 #define DMAMUX_CFR_CSOF1_Msk           (0x1U << DMAMUX_CFR_CSOF1_Pos)          /*!< 0x00000002 */
13173 #define DMAMUX_CFR_CSOF1               DMAMUX_CFR_CSOF1_Msk
13174 #define DMAMUX_CFR_CSOF2_Pos           (2U)
13175 #define DMAMUX_CFR_CSOF2_Msk           (0x1U << DMAMUX_CFR_CSOF2_Pos)          /*!< 0x00000004 */
13176 #define DMAMUX_CFR_CSOF2               DMAMUX_CFR_CSOF2_Msk
13177 #define DMAMUX_CFR_CSOF3_Pos           (3U)
13178 #define DMAMUX_CFR_CSOF3_Msk           (0x1U << DMAMUX_CFR_CSOF3_Pos)          /*!< 0x00000008 */
13179 #define DMAMUX_CFR_CSOF3               DMAMUX_CFR_CSOF3_Msk
13180 #define DMAMUX_CFR_CSOF4_Pos           (4U)
13181 #define DMAMUX_CFR_CSOF4_Msk           (0x1U << DMAMUX_CFR_CSOF4_Pos)          /*!< 0x00000010 */
13182 #define DMAMUX_CFR_CSOF4               DMAMUX_CFR_CSOF4_Msk
13183 #define DMAMUX_CFR_CSOF5_Pos           (5U)
13184 #define DMAMUX_CFR_CSOF5_Msk           (0x1U << DMAMUX_CFR_CSOF5_Pos)          /*!< 0x00000020 */
13185 #define DMAMUX_CFR_CSOF5               DMAMUX_CFR_CSOF5_Msk
13186 #define DMAMUX_CFR_CSOF6_Pos           (6U)
13187 #define DMAMUX_CFR_CSOF6_Msk           (0x1U << DMAMUX_CFR_CSOF6_Pos)          /*!< 0x00000040 */
13188 #define DMAMUX_CFR_CSOF6               DMAMUX_CFR_CSOF6_Msk
13189 #define DMAMUX_CFR_CSOF7_Pos           (7U)
13190 #define DMAMUX_CFR_CSOF7_Msk           (0x1U << DMAMUX_CFR_CSOF7_Pos)          /*!< 0x00000080 */
13191 #define DMAMUX_CFR_CSOF7               DMAMUX_CFR_CSOF7_Msk
13192 #define DMAMUX_CFR_CSOF8_Pos           (8U)
13193 #define DMAMUX_CFR_CSOF8_Msk           (0x1U << DMAMUX_CFR_CSOF8_Pos)          /*!< 0x00000100 */
13194 #define DMAMUX_CFR_CSOF8               DMAMUX_CFR_CSOF8_Msk
13195 #define DMAMUX_CFR_CSOF9_Pos           (9U)
13196 #define DMAMUX_CFR_CSOF9_Msk           (0x1U << DMAMUX_CFR_CSOF9_Pos)          /*!< 0x00000200 */
13197 #define DMAMUX_CFR_CSOF9               DMAMUX_CFR_CSOF9_Msk
13198 #define DMAMUX_CFR_CSOF10_Pos          (10U)
13199 #define DMAMUX_CFR_CSOF10_Msk          (0x1U << DMAMUX_CFR_CSOF10_Pos)         /*!< 0x00000400 */
13200 #define DMAMUX_CFR_CSOF10              DMAMUX_CFR_CSOF10_Msk
13201 #define DMAMUX_CFR_CSOF11_Pos          (11U)
13202 #define DMAMUX_CFR_CSOF11_Msk          (0x1U << DMAMUX_CFR_CSOF11_Pos)         /*!< 0x00000800 */
13203 #define DMAMUX_CFR_CSOF11              DMAMUX_CFR_CSOF11_Msk
13204 #define DMAMUX_CFR_CSOF12_Pos          (12U)
13205 #define DMAMUX_CFR_CSOF12_Msk          (0x1U << DMAMUX_CFR_CSOF12_Pos)         /*!< 0x00001000 */
13206 #define DMAMUX_CFR_CSOF12              DMAMUX_CFR_CSOF12_Msk
13207 #define DMAMUX_CFR_CSOF13_Pos          (13U)
13208 #define DMAMUX_CFR_CSOF13_Msk          (0x1U << DMAMUX_CFR_CSOF13_Pos)         /*!< 0x00002000 */
13209 #define DMAMUX_CFR_CSOF13              DMAMUX_CFR_CSOF13_Msk
13210 #define DMAMUX_CFR_CSOF14_Pos          (14U)
13211 #define DMAMUX_CFR_CSOF14_Msk          (0x1U << DMAMUX_CFR_CSOF14_Pos)         /*!< 0x00004000 */
13212 #define DMAMUX_CFR_CSOF14              DMAMUX_CFR_CSOF14_Msk
13213 #define DMAMUX_CFR_CSOF15_Pos          (15U)
13214 #define DMAMUX_CFR_CSOF15_Msk          (0x1U << DMAMUX_CFR_CSOF15_Pos)         /*!< 0x00008000 */
13215 #define DMAMUX_CFR_CSOF15              DMAMUX_CFR_CSOF15_Msk
13216 
13217 /********************  Bits definition for DMAMUX_RGxCR register  ************/
13218 #define DMAMUX_RGxCR_SIG_ID_Pos        (0U)
13219 #define DMAMUX_RGxCR_SIG_ID_Msk        (0x1FU << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x0000001F */
13220 #define DMAMUX_RGxCR_SIG_ID            DMAMUX_RGxCR_SIG_ID_Msk
13221 #define DMAMUX_RGxCR_SIG_ID_0          (0x01U << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000001 */
13222 #define DMAMUX_RGxCR_SIG_ID_1          (0x02U << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000002 */
13223 #define DMAMUX_RGxCR_SIG_ID_2          (0x04U << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000004 */
13224 #define DMAMUX_RGxCR_SIG_ID_3          (0x08U << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000008 */
13225 #define DMAMUX_RGxCR_SIG_ID_4          (0x10U << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000010 */
13226 #define DMAMUX_RGxCR_OIE_Pos           (8U)
13227 #define DMAMUX_RGxCR_OIE_Msk           (0x1U << DMAMUX_RGxCR_OIE_Pos)          /*!< 0x00000100 */
13228 #define DMAMUX_RGxCR_OIE               DMAMUX_RGxCR_OIE_Msk
13229 #define DMAMUX_RGxCR_GE_Pos            (16U)
13230 #define DMAMUX_RGxCR_GE_Msk            (0x1U << DMAMUX_RGxCR_GE_Pos)           /*!< 0x00010000 */
13231 #define DMAMUX_RGxCR_GE                DMAMUX_RGxCR_GE_Msk
13232 #define DMAMUX_RGxCR_GPOL_Pos          (17U)
13233 #define DMAMUX_RGxCR_GPOL_Msk          (0x3U << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00060000 */
13234 #define DMAMUX_RGxCR_GPOL              DMAMUX_RGxCR_GPOL_Msk
13235 #define DMAMUX_RGxCR_GPOL_0            (0x1U << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00020000 */
13236 #define DMAMUX_RGxCR_GPOL_1            (0x2U << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00040000 */
13237 #define DMAMUX_RGxCR_GNBREQ_Pos        (19U)
13238 #define DMAMUX_RGxCR_GNBREQ_Msk        (0x1FU << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00F80000 */
13239 #define DMAMUX_RGxCR_GNBREQ            DMAMUX_RGxCR_GNBREQ_Msk                 /*!< Number of DMA requests to be generated */
13240 #define DMAMUX_RGxCR_GNBREQ_0          (0x01U << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00080000 */
13241 #define DMAMUX_RGxCR_GNBREQ_1          (0x02U << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00100000 */
13242 #define DMAMUX_RGxCR_GNBREQ_2          (0x04U << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00200000 */
13243 #define DMAMUX_RGxCR_GNBREQ_3          (0x08U << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00400000 */
13244 #define DMAMUX_RGxCR_GNBREQ_4          (0x10U << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00800000 */
13245 
13246 /********************  Bits definition for DMAMUX_RGSR register  **************/
13247 #define DMAMUX_RGSR_OF0_Pos            (0U)
13248 #define DMAMUX_RGSR_OF0_Msk            (0x1U << DMAMUX_RGSR_OF0_Pos)           /*!< 0x00000001 */
13249 #define DMAMUX_RGSR_OF0                DMAMUX_RGSR_OF0_Msk
13250 #define DMAMUX_RGSR_OF1_Pos            (1U)
13251 #define DMAMUX_RGSR_OF1_Msk            (0x1U << DMAMUX_RGSR_OF1_Pos)           /*!< 0x00000002 */
13252 #define DMAMUX_RGSR_OF1                DMAMUX_RGSR_OF1_Msk
13253 #define DMAMUX_RGSR_OF2_Pos            (2U)
13254 #define DMAMUX_RGSR_OF2_Msk            (0x1U << DMAMUX_RGSR_OF2_Pos)           /*!< 0x00000004 */
13255 #define DMAMUX_RGSR_OF2                DMAMUX_RGSR_OF2_Msk
13256 #define DMAMUX_RGSR_OF3_Pos            (3U)
13257 #define DMAMUX_RGSR_OF3_Msk            (0x1U << DMAMUX_RGSR_OF3_Pos)           /*!< 0x00000008 */
13258 #define DMAMUX_RGSR_OF3                DMAMUX_RGSR_OF3_Msk
13259 #define DMAMUX_RGSR_OF4_Pos            (4U)
13260 #define DMAMUX_RGSR_OF4_Msk            (0x1U << DMAMUX_RGSR_OF4_Pos)           /*!< 0x00000010 */
13261 #define DMAMUX_RGSR_OF4                DMAMUX_RGSR_OF4_Msk
13262 #define DMAMUX_RGSR_OF5_Pos            (5U)
13263 #define DMAMUX_RGSR_OF5_Msk            (0x1U << DMAMUX_RGSR_OF5_Pos)           /*!< 0x00000020 */
13264 #define DMAMUX_RGSR_OF5                DMAMUX_RGSR_OF5_Msk
13265 #define DMAMUX_RGSR_OF6_Pos            (6U)
13266 #define DMAMUX_RGSR_OF6_Msk            (0x1U << DMAMUX_RGSR_OF6_Pos)           /*!< 0x00000040 */
13267 #define DMAMUX_RGSR_OF6                DMAMUX_RGSR_OF6_Msk
13268 #define DMAMUX_RGSR_OF7_Pos            (7U)
13269 #define DMAMUX_RGSR_OF7_Msk            (0x1U << DMAMUX_RGSR_OF7_Pos)           /*!< 0x00000080 */
13270 #define DMAMUX_RGSR_OF7                DMAMUX_RGSR_OF7_Msk
13271 
13272 /********************  Bits definition for DMAMUX_RGCFR register  **************/
13273 #define DMAMUX_RGCFR_COF0_Pos          (0U)
13274 #define DMAMUX_RGCFR_COF0_Msk          (0x1U << DMAMUX_RGCFR_COF0_Pos)         /*!< 0x00000001 */
13275 #define DMAMUX_RGCFR_COF0              DMAMUX_RGCFR_COF0_Msk
13276 #define DMAMUX_RGCFR_COF1_Pos          (1U)
13277 #define DMAMUX_RGCFR_COF1_Msk          (0x1U << DMAMUX_RGCFR_COF1_Pos)         /*!< 0x00000002 */
13278 #define DMAMUX_RGCFR_COF1              DMAMUX_RGCFR_COF1_Msk
13279 #define DMAMUX_RGCFR_COF2_Pos          (2U)
13280 #define DMAMUX_RGCFR_COF2_Msk          (0x1U << DMAMUX_RGCFR_COF2_Pos)         /*!< 0x00000004 */
13281 #define DMAMUX_RGCFR_COF2              DMAMUX_RGCFR_COF2_Msk
13282 #define DMAMUX_RGCFR_COF3_Pos          (3U)
13283 #define DMAMUX_RGCFR_COF3_Msk          (0x1U << DMAMUX_RGCFR_COF3_Pos)         /*!< 0x00000008 */
13284 #define DMAMUX_RGCFR_COF3              DMAMUX_RGCFR_COF3_Msk
13285 #define DMAMUX_RGCFR_COF4_Pos          (4U)
13286 #define DMAMUX_RGCFR_COF4_Msk          (0x1U << DMAMUX_RGCFR_COF4_Pos)         /*!< 0x00000010 */
13287 #define DMAMUX_RGCFR_COF4              DMAMUX_RGCFR_COF4_Msk
13288 #define DMAMUX_RGCFR_COF5_Pos          (5U)
13289 #define DMAMUX_RGCFR_COF5_Msk          (0x1U << DMAMUX_RGCFR_COF5_Pos)         /*!< 0x00000020 */
13290 #define DMAMUX_RGCFR_COF5              DMAMUX_RGCFR_COF5_Msk
13291 #define DMAMUX_RGCFR_COF6_Pos          (6U)
13292 #define DMAMUX_RGCFR_COF6_Msk          (0x1U << DMAMUX_RGCFR_COF6_Pos)         /*!< 0x00000040 */
13293 #define DMAMUX_RGCFR_COF6              DMAMUX_RGCFR_COF6_Msk
13294 #define DMAMUX_RGCFR_COF7_Pos          (7U)
13295 #define DMAMUX_RGCFR_COF7_Msk          (0x1U << DMAMUX_RGCFR_COF7_Pos)         /*!< 0x00000080 */
13296 #define DMAMUX_RGCFR_COF7              DMAMUX_RGCFR_COF7_Msk
13297 
13298 /**********************  Bit definition for DMAMUX_VERR register  *****************/
13299 #define DMAMUX_VERR_MINREV_Pos      (0U)
13300 #define DMAMUX_VERR_MINREV_Msk      (0xFU << DMAMUX_VERR_MINREV_Pos)               /*!< 0x0000000F */
13301 #define DMAMUX_VERR_MINREV          DMAMUX_VERR_MINREV_Msk                         /*!< Minor Revision number */
13302 #define DMAMUX_VERR_MAJREV_Pos      (4U)
13303 #define DMAMUX_VERR_MAJREV_Msk      (0xFU << DMAMUX_VERR_MAJREV_Pos)               /*!< 0x000000F0 */
13304 #define DMAMUX_VERR_MAJREV          DMAMUX_VERR_MAJREV_Msk                         /*!< Major Revision number */
13305 
13306 /**********************  Bit definition for DMAMUX_IPIDR register  ****************/
13307 #define DMAMUX_IPIDR_IPID_Pos       (0U)
13308 #define DMAMUX_IPIDR_IPID_Msk       (0xFFFFFFFFU << DMAMUX_IPIDR_IPID_Pos)         /*!< 0xFFFFFFFF */
13309 #define DMAMUX_IPIDR_IPID           DMAMUX_IPIDR_IPID_Msk                          /*!< IP Identification */
13310 
13311 /**********************  Bit definition for DMAMUX_SIDR register  *****************/
13312 #define DMAMUX_SIDR_SID_Pos         (0U)
13313 #define DMAMUX_SIDR_SID_Msk         (0xFFFFFFFFU << DMAMUX_SIDR_SID_Pos)           /*!< 0xFFFFFFFF */
13314 #define DMAMUX_SIDR_SID             DMAMUX_SIDR_SID_Msk                            /*!< IP size identification */
13315 
13316 /******************************************************************************/
13317 /*                                                                            */
13318 /*                     Display Serial Interface (DSI)                         */
13319 /*                                                                            */
13320 /******************************************************************************/
13321 /*******************  Bit definition for DSI_VR register  *****************/
13322 #define DSI_VR                         ((uint32_t)0x3133312AU)               /*!< DSI Host Version */
13323 
13324 /*******************  Bit definition for DSI_CR register  *****************/
13325 #define DSI_CR_EN                      ((uint32_t)0x00000001U)               /*!< DSI Host power up and reset */
13326 
13327 /*******************  Bit definition for DSI_CCR register  ****************/
13328 #define DSI_CCR_TXECKDIV               ((uint32_t)0x000000FFU)               /*!< TX Escape Clock Division */
13329 #define DSI_CCR_TXECKDIV0              ((uint32_t)0x00000001U)
13330 #define DSI_CCR_TXECKDIV1              ((uint32_t)0x00000002U)
13331 #define DSI_CCR_TXECKDIV2              ((uint32_t)0x00000004U)
13332 #define DSI_CCR_TXECKDIV3              ((uint32_t)0x00000008U)
13333 #define DSI_CCR_TXECKDIV4              ((uint32_t)0x00000010U)
13334 #define DSI_CCR_TXECKDIV5              ((uint32_t)0x00000020U)
13335 #define DSI_CCR_TXECKDIV6              ((uint32_t)0x00000040U)
13336 #define DSI_CCR_TXECKDIV7              ((uint32_t)0x00000080U)
13337 
13338 #define DSI_CCR_TOCKDIV                ((uint32_t)0x0000FF00U)               /*!< Timeout Clock Division */
13339 #define DSI_CCR_TOCKDIV0               ((uint32_t)0x00000100U)
13340 #define DSI_CCR_TOCKDIV1               ((uint32_t)0x00000200U)
13341 #define DSI_CCR_TOCKDIV2               ((uint32_t)0x00000400U)
13342 #define DSI_CCR_TOCKDIV3               ((uint32_t)0x00000800U)
13343 #define DSI_CCR_TOCKDIV4               ((uint32_t)0x00001000U)
13344 #define DSI_CCR_TOCKDIV5               ((uint32_t)0x00002000U)
13345 #define DSI_CCR_TOCKDIV6               ((uint32_t)0x00004000U)
13346 #define DSI_CCR_TOCKDIV7               ((uint32_t)0x00008000U)
13347 
13348 /*******************  Bit definition for DSI_LVCIDR register  *************/
13349 #define DSI_LVCIDR_VCID                ((uint32_t)0x00000003U)               /*!< Virtual Channel ID */
13350 #define DSI_LVCIDR_VCID0               ((uint32_t)0x00000001U)
13351 #define DSI_LVCIDR_VCID1               ((uint32_t)0x00000002U)
13352 
13353 /*******************  Bit definition for DSI_LCOLCR register  *************/
13354 #define DSI_LCOLCR_COLC                ((uint32_t)0x0000000FU)               /*!< Color Coding */
13355 #define DSI_LCOLCR_COLC0               ((uint32_t)0x00000001U)
13356 #define DSI_LCOLCR_COLC1               ((uint32_t)0x00000002U)
13357 #define DSI_LCOLCR_COLC2               ((uint32_t)0x00000004U)
13358 #define DSI_LCOLCR_COLC3               ((uint32_t)0x00000008U)
13359 
13360 #define DSI_LCOLCR_LPE                 ((uint32_t)0x00000100U)               /*!< Loosly Packet Enable */
13361 
13362 /*******************  Bit definition for DSI_LPCR register  ***************/
13363 #define DSI_LPCR_DEP                   ((uint32_t)0x00000001U)               /*!< Data Enable Polarity */
13364 #define DSI_LPCR_VSP                   ((uint32_t)0x00000002U)               /*!< VSYNC Polarity */
13365 #define DSI_LPCR_HSP                   ((uint32_t)0x00000004U)               /*!< HSYNC Polarity */
13366 
13367 /*******************  Bit definition for DSI_LPMCR register  **************/
13368 #define DSI_LPMCR_VLPSIZE              ((uint32_t)0x000000FFU)               /*!< VACT Largest Packet Size */
13369 #define DSI_LPMCR_VLPSIZE0             ((uint32_t)0x00000001U)
13370 #define DSI_LPMCR_VLPSIZE1             ((uint32_t)0x00000002U)
13371 #define DSI_LPMCR_VLPSIZE2             ((uint32_t)0x00000004U)
13372 #define DSI_LPMCR_VLPSIZE3             ((uint32_t)0x00000008U)
13373 #define DSI_LPMCR_VLPSIZE4             ((uint32_t)0x00000010U)
13374 #define DSI_LPMCR_VLPSIZE5             ((uint32_t)0x00000020U)
13375 #define DSI_LPMCR_VLPSIZE6             ((uint32_t)0x00000040U)
13376 #define DSI_LPMCR_VLPSIZE7             ((uint32_t)0x00000080U)
13377 
13378 #define DSI_LPMCR_LPSIZE               ((uint32_t)0x00FF0000U)               /*!< Largest Packet Size */
13379 #define DSI_LPMCR_LPSIZE0              ((uint32_t)0x00010000U)
13380 #define DSI_LPMCR_LPSIZE1              ((uint32_t)0x00020000U)
13381 #define DSI_LPMCR_LPSIZE2              ((uint32_t)0x00040000U)
13382 #define DSI_LPMCR_LPSIZE3              ((uint32_t)0x00080000U)
13383 #define DSI_LPMCR_LPSIZE4              ((uint32_t)0x00100000U)
13384 #define DSI_LPMCR_LPSIZE5              ((uint32_t)0x00200000U)
13385 #define DSI_LPMCR_LPSIZE6              ((uint32_t)0x00400000U)
13386 #define DSI_LPMCR_LPSIZE7              ((uint32_t)0x00800000U)
13387 
13388 /*******************  Bit definition for DSI_PCR register  ****************/
13389 #define DSI_PCR_ETTXE                  ((uint32_t)0x00000001U)               /*!< EoTp Transmission Enable */
13390 #define DSI_PCR_ETRXE                  ((uint32_t)0x00000002U)               /*!< EoTp Reception Enable */
13391 #define DSI_PCR_BTAE                   ((uint32_t)0x00000004U)               /*!< Bus Turn Around Enable */
13392 #define DSI_PCR_ECCRXE                 ((uint32_t)0x00000008U)               /*!< ECC Reception Enable */
13393 #define DSI_PCR_CRCRXE                 ((uint32_t)0x00000010U)               /*!< CRC Reception Enable */
13394 
13395 /*******************  Bit definition for DSI_GVCIDR register  *************/
13396 #define DSI_GVCIDR_VCID                ((uint32_t)0x00000003U)               /*!< Virtual Channel ID */
13397 #define DSI_GVCIDR_VCID0               ((uint32_t)0x00000001U)
13398 #define DSI_GVCIDR_VCID1               ((uint32_t)0x00000002U)
13399 
13400 /*******************  Bit definition for DSI_MCR register  ****************/
13401 #define DSI_MCR_CMDM                   ((uint32_t)0x00000001U)               /*!< Command Mode */
13402 
13403 /*******************  Bit definition for DSI_VMCR register  ***************/
13404 #define DSI_VMCR_VMT                   ((uint32_t)0x00000003U)               /*!< Video Mode Type */
13405 #define DSI_VMCR_VMT0                  ((uint32_t)0x00000001U)
13406 #define DSI_VMCR_VMT1                  ((uint32_t)0x00000002U)
13407 
13408 #define DSI_VMCR_LPVSAE                ((uint32_t)0x00000100U)               /*!< Low-Power Vertical Sync Active Enable */
13409 #define DSI_VMCR_LPVBPE                ((uint32_t)0x00000200U)               /*!< Low-power Vertical Back-Porch Enable */
13410 #define DSI_VMCR_LPVFPE                ((uint32_t)0x00000400U)               /*!< Low-power Vertical Front-porch Enable */
13411 #define DSI_VMCR_LPVAE                 ((uint32_t)0x00000800U)               /*!< Low-Power Vertical Active Enable */
13412 #define DSI_VMCR_LPHBPE                ((uint32_t)0x00001000U)               /*!< Low-Power Horizontal Back-Porch Enable */
13413 #define DSI_VMCR_LPHFPE                ((uint32_t)0x00002000U)               /*!< Low-Power Horizontal Front-Porch Enable */
13414 #define DSI_VMCR_FBTAAE                ((uint32_t)0x00004000U)               /*!< Frame Bus-Turn-Around Acknowledge Enable */
13415 #define DSI_VMCR_LPCE                  ((uint32_t)0x00008000U)               /*!< Low-Power Command Enable */
13416 #define DSI_VMCR_PGE                   ((uint32_t)0x00010000U)               /*!< Pattern Generator Enable */
13417 #define DSI_VMCR_PGM                   ((uint32_t)0x00100000U)               /*!< Pattern Generator Mode */
13418 #define DSI_VMCR_PGO                   ((uint32_t)0x01000000U)               /*!< Pattern Generator Orientation */
13419 
13420 /*******************  Bit definition for DSI_VPCR register  ***************/
13421 #define DSI_VPCR_VPSIZE                ((uint32_t)0x00003FFFU)               /*!< Video Packet Size */
13422 #define DSI_VPCR_VPSIZE0               ((uint32_t)0x00000001U)
13423 #define DSI_VPCR_VPSIZE1               ((uint32_t)0x00000002U)
13424 #define DSI_VPCR_VPSIZE2               ((uint32_t)0x00000004U)
13425 #define DSI_VPCR_VPSIZE3               ((uint32_t)0x00000008U)
13426 #define DSI_VPCR_VPSIZE4               ((uint32_t)0x00000010U)
13427 #define DSI_VPCR_VPSIZE5               ((uint32_t)0x00000020U)
13428 #define DSI_VPCR_VPSIZE6               ((uint32_t)0x00000040U)
13429 #define DSI_VPCR_VPSIZE7               ((uint32_t)0x00000080U)
13430 #define DSI_VPCR_VPSIZE8               ((uint32_t)0x00000100U)
13431 #define DSI_VPCR_VPSIZE9               ((uint32_t)0x00000200U)
13432 #define DSI_VPCR_VPSIZE10              ((uint32_t)0x00000400U)
13433 #define DSI_VPCR_VPSIZE11              ((uint32_t)0x00000800U)
13434 #define DSI_VPCR_VPSIZE12              ((uint32_t)0x00001000U)
13435 #define DSI_VPCR_VPSIZE13              ((uint32_t)0x00002000U)
13436 
13437 /*******************  Bit definition for DSI_VCCR register  ***************/
13438 #define DSI_VCCR_NUMC                  ((uint32_t)0x00001FFFU)               /*!< Number of Chunks */
13439 #define DSI_VCCR_NUMC0                 ((uint32_t)0x00000001U)
13440 #define DSI_VCCR_NUMC1                 ((uint32_t)0x00000002U)
13441 #define DSI_VCCR_NUMC2                 ((uint32_t)0x00000004U)
13442 #define DSI_VCCR_NUMC3                 ((uint32_t)0x00000008U)
13443 #define DSI_VCCR_NUMC4                 ((uint32_t)0x00000010U)
13444 #define DSI_VCCR_NUMC5                 ((uint32_t)0x00000020U)
13445 #define DSI_VCCR_NUMC6                 ((uint32_t)0x00000040U)
13446 #define DSI_VCCR_NUMC7                 ((uint32_t)0x00000080U)
13447 #define DSI_VCCR_NUMC8                 ((uint32_t)0x00000100U)
13448 #define DSI_VCCR_NUMC9                 ((uint32_t)0x00000200U)
13449 #define DSI_VCCR_NUMC10                ((uint32_t)0x00000400U)
13450 #define DSI_VCCR_NUMC11                ((uint32_t)0x00000800U)
13451 #define DSI_VCCR_NUMC12                ((uint32_t)0x00001000U)
13452 
13453 /*******************  Bit definition for DSI_VNPCR register  **************/
13454 #define DSI_VNPCR_NPSIZE               ((uint32_t)0x00001FFFU)               /*!< Null Packet Size */
13455 #define DSI_VNPCR_NPSIZE0              ((uint32_t)0x00000001U)
13456 #define DSI_VNPCR_NPSIZE1              ((uint32_t)0x00000002U)
13457 #define DSI_VNPCR_NPSIZE2              ((uint32_t)0x00000004U)
13458 #define DSI_VNPCR_NPSIZE3              ((uint32_t)0x00000008U)
13459 #define DSI_VNPCR_NPSIZE4              ((uint32_t)0x00000010U)
13460 #define DSI_VNPCR_NPSIZE5              ((uint32_t)0x00000020U)
13461 #define DSI_VNPCR_NPSIZE6              ((uint32_t)0x00000040U)
13462 #define DSI_VNPCR_NPSIZE7              ((uint32_t)0x00000080U)
13463 #define DSI_VNPCR_NPSIZE8              ((uint32_t)0x00000100U)
13464 #define DSI_VNPCR_NPSIZE9              ((uint32_t)0x00000200U)
13465 #define DSI_VNPCR_NPSIZE10             ((uint32_t)0x00000400U)
13466 #define DSI_VNPCR_NPSIZE11             ((uint32_t)0x00000800U)
13467 #define DSI_VNPCR_NPSIZE12             ((uint32_t)0x00001000U)
13468 
13469 /*******************  Bit definition for DSI_VHSACR register  *************/
13470 #define DSI_VHSACR_HSA                 ((uint32_t)0x00000FFFU)               /*!< Horizontal Synchronism Active duration */
13471 #define DSI_VHSACR_HSA0                ((uint32_t)0x00000001U)
13472 #define DSI_VHSACR_HSA1                ((uint32_t)0x00000002U)
13473 #define DSI_VHSACR_HSA2                ((uint32_t)0x00000004U)
13474 #define DSI_VHSACR_HSA3                ((uint32_t)0x00000008U)
13475 #define DSI_VHSACR_HSA4                ((uint32_t)0x00000010U)
13476 #define DSI_VHSACR_HSA5                ((uint32_t)0x00000020U)
13477 #define DSI_VHSACR_HSA6                ((uint32_t)0x00000040U)
13478 #define DSI_VHSACR_HSA7                ((uint32_t)0x00000080U)
13479 #define DSI_VHSACR_HSA8                ((uint32_t)0x00000100U)
13480 #define DSI_VHSACR_HSA9                ((uint32_t)0x00000200U)
13481 #define DSI_VHSACR_HSA10               ((uint32_t)0x00000400U)
13482 #define DSI_VHSACR_HSA11               ((uint32_t)0x00000800U)
13483 
13484 /*******************  Bit definition for DSI_VHBPCR register  *************/
13485 #define DSI_VHBPCR_HBP                 ((uint32_t)0x00000FFFU)               /*!< Horizontal Back-Porch duration */
13486 #define DSI_VHBPCR_HBP0                ((uint32_t)0x00000001U)
13487 #define DSI_VHBPCR_HBP1                ((uint32_t)0x00000002U)
13488 #define DSI_VHBPCR_HBP2                ((uint32_t)0x00000004U)
13489 #define DSI_VHBPCR_HBP3                ((uint32_t)0x00000008U)
13490 #define DSI_VHBPCR_HBP4                ((uint32_t)0x00000010U)
13491 #define DSI_VHBPCR_HBP5                ((uint32_t)0x00000020U)
13492 #define DSI_VHBPCR_HBP6                ((uint32_t)0x00000040U)
13493 #define DSI_VHBPCR_HBP7                ((uint32_t)0x00000080U)
13494 #define DSI_VHBPCR_HBP8                ((uint32_t)0x00000100U)
13495 #define DSI_VHBPCR_HBP9                ((uint32_t)0x00000200U)
13496 #define DSI_VHBPCR_HBP10               ((uint32_t)0x00000400U)
13497 #define DSI_VHBPCR_HBP11               ((uint32_t)0x00000800U)
13498 
13499 /*******************  Bit definition for DSI_VLCR register  ***************/
13500 #define DSI_VLCR_HLINE                 ((uint32_t)0x00007FFFU)               /*!< Horizontal Line duration */
13501 #define DSI_VLCR_HLINE0                ((uint32_t)0x00000001U)
13502 #define DSI_VLCR_HLINE1                ((uint32_t)0x00000002U)
13503 #define DSI_VLCR_HLINE2                ((uint32_t)0x00000004U)
13504 #define DSI_VLCR_HLINE3                ((uint32_t)0x00000008U)
13505 #define DSI_VLCR_HLINE4                ((uint32_t)0x00000010U)
13506 #define DSI_VLCR_HLINE5                ((uint32_t)0x00000020U)
13507 #define DSI_VLCR_HLINE6                ((uint32_t)0x00000040U)
13508 #define DSI_VLCR_HLINE7                ((uint32_t)0x00000080U)
13509 #define DSI_VLCR_HLINE8                ((uint32_t)0x00000100U)
13510 #define DSI_VLCR_HLINE9                ((uint32_t)0x00000200U)
13511 #define DSI_VLCR_HLINE10               ((uint32_t)0x00000400U)
13512 #define DSI_VLCR_HLINE11               ((uint32_t)0x00000800U)
13513 #define DSI_VLCR_HLINE12               ((uint32_t)0x00001000U)
13514 #define DSI_VLCR_HLINE13               ((uint32_t)0x00002000U)
13515 #define DSI_VLCR_HLINE14               ((uint32_t)0x00004000U)
13516 
13517 /*******************  Bit definition for DSI_VVSACR register  *************/
13518 #define DSI_VVSACR_VSA                 ((uint32_t)0x000003FFU)               /*!< Vertical Synchronism Active duration */
13519 #define DSI_VVSACR_VSA0                ((uint32_t)0x00000001U)
13520 #define DSI_VVSACR_VSA1                ((uint32_t)0x00000002U)
13521 #define DSI_VVSACR_VSA2                ((uint32_t)0x00000004U)
13522 #define DSI_VVSACR_VSA3                ((uint32_t)0x00000008U)
13523 #define DSI_VVSACR_VSA4                ((uint32_t)0x00000010U)
13524 #define DSI_VVSACR_VSA5                ((uint32_t)0x00000020U)
13525 #define DSI_VVSACR_VSA6                ((uint32_t)0x00000040U)
13526 #define DSI_VVSACR_VSA7                ((uint32_t)0x00000080U)
13527 #define DSI_VVSACR_VSA8                ((uint32_t)0x00000100U)
13528 #define DSI_VVSACR_VSA9                ((uint32_t)0x00000200U)
13529 
13530 /*******************  Bit definition for DSI_VVBPCR register  *************/
13531 #define DSI_VVBPCR_VBP                 ((uint32_t)0x000003FFU)               /*!< Vertical Back-Porch duration */
13532 #define DSI_VVBPCR_VBP0                ((uint32_t)0x00000001U)
13533 #define DSI_VVBPCR_VBP1                ((uint32_t)0x00000002U)
13534 #define DSI_VVBPCR_VBP2                ((uint32_t)0x00000004U)
13535 #define DSI_VVBPCR_VBP3                ((uint32_t)0x00000008U)
13536 #define DSI_VVBPCR_VBP4                ((uint32_t)0x00000010U)
13537 #define DSI_VVBPCR_VBP5                ((uint32_t)0x00000020U)
13538 #define DSI_VVBPCR_VBP6                ((uint32_t)0x00000040U)
13539 #define DSI_VVBPCR_VBP7                ((uint32_t)0x00000080U)
13540 #define DSI_VVBPCR_VBP8                ((uint32_t)0x00000100U)
13541 #define DSI_VVBPCR_VBP9                ((uint32_t)0x00000200U)
13542 
13543 /*******************  Bit definition for DSI_VVFPCR register  *************/
13544 #define DSI_VVFPCR_VFP                 ((uint32_t)0x000003FFU)               /*!< Vertical Front-Porch duration */
13545 #define DSI_VVFPCR_VFP0                ((uint32_t)0x00000001U)
13546 #define DSI_VVFPCR_VFP1                ((uint32_t)0x00000002U)
13547 #define DSI_VVFPCR_VFP2                ((uint32_t)0x00000004U)
13548 #define DSI_VVFPCR_VFP3                ((uint32_t)0x00000008U)
13549 #define DSI_VVFPCR_VFP4                ((uint32_t)0x00000010U)
13550 #define DSI_VVFPCR_VFP5                ((uint32_t)0x00000020U)
13551 #define DSI_VVFPCR_VFP6                ((uint32_t)0x00000040U)
13552 #define DSI_VVFPCR_VFP7                ((uint32_t)0x00000080U)
13553 #define DSI_VVFPCR_VFP8                ((uint32_t)0x00000100U)
13554 #define DSI_VVFPCR_VFP9                ((uint32_t)0x00000200U)
13555 
13556 /*******************  Bit definition for DSI_VVACR register  **************/
13557 #define DSI_VVACR_VA                   ((uint32_t)0x00003FFFU)               /*!< Vertical Active duration */
13558 #define DSI_VVACR_VA0                  ((uint32_t)0x00000001U)
13559 #define DSI_VVACR_VA1                  ((uint32_t)0x00000002U)
13560 #define DSI_VVACR_VA2                  ((uint32_t)0x00000004U)
13561 #define DSI_VVACR_VA3                  ((uint32_t)0x00000008U)
13562 #define DSI_VVACR_VA4                  ((uint32_t)0x00000010U)
13563 #define DSI_VVACR_VA5                  ((uint32_t)0x00000020U)
13564 #define DSI_VVACR_VA6                  ((uint32_t)0x00000040U)
13565 #define DSI_VVACR_VA7                  ((uint32_t)0x00000080U)
13566 #define DSI_VVACR_VA8                  ((uint32_t)0x00000100U)
13567 #define DSI_VVACR_VA9                  ((uint32_t)0x00000200U)
13568 #define DSI_VVACR_VA10                 ((uint32_t)0x00000400U)
13569 #define DSI_VVACR_VA11                 ((uint32_t)0x00000800U)
13570 #define DSI_VVACR_VA12                 ((uint32_t)0x00001000U)
13571 #define DSI_VVACR_VA13                 ((uint32_t)0x00002000U)
13572 
13573 /*******************  Bit definition for DSI_LCCR register  ***************/
13574 #define DSI_LCCR_CMDSIZE               ((uint32_t)0x0000FFFFU)               /*!< Command Size */
13575 #define DSI_LCCR_CMDSIZE0              ((uint32_t)0x00000001U)
13576 #define DSI_LCCR_CMDSIZE1              ((uint32_t)0x00000002U)
13577 #define DSI_LCCR_CMDSIZE2              ((uint32_t)0x00000004U)
13578 #define DSI_LCCR_CMDSIZE3              ((uint32_t)0x00000008U)
13579 #define DSI_LCCR_CMDSIZE4              ((uint32_t)0x00000010U)
13580 #define DSI_LCCR_CMDSIZE5              ((uint32_t)0x00000020U)
13581 #define DSI_LCCR_CMDSIZE6              ((uint32_t)0x00000040U)
13582 #define DSI_LCCR_CMDSIZE7              ((uint32_t)0x00000080U)
13583 #define DSI_LCCR_CMDSIZE8              ((uint32_t)0x00000100U)
13584 #define DSI_LCCR_CMDSIZE9              ((uint32_t)0x00000200U)
13585 #define DSI_LCCR_CMDSIZE10             ((uint32_t)0x00000400U)
13586 #define DSI_LCCR_CMDSIZE11             ((uint32_t)0x00000800U)
13587 #define DSI_LCCR_CMDSIZE12             ((uint32_t)0x00001000U)
13588 #define DSI_LCCR_CMDSIZE13             ((uint32_t)0x00002000U)
13589 #define DSI_LCCR_CMDSIZE14             ((uint32_t)0x00004000U)
13590 #define DSI_LCCR_CMDSIZE15             ((uint32_t)0x00008000U)
13591 
13592 /*******************  Bit definition for DSI_CMCR register  ***************/
13593 #define DSI_CMCR_TEARE                 ((uint32_t)0x00000001U)               /*!< Tearing Effect Acknowledge Request Enable */
13594 #define DSI_CMCR_ARE                   ((uint32_t)0x00000002U)               /*!< Acknowledge Request Enable */
13595 #define DSI_CMCR_GSW0TX                ((uint32_t)0x00000100U)               /*!< Generic Short Write Zero parameters Transmission */
13596 #define DSI_CMCR_GSW1TX                ((uint32_t)0x00000200U)               /*!< Generic Short Write One parameters Transmission */
13597 #define DSI_CMCR_GSW2TX                ((uint32_t)0x00000400U)               /*!< Generic Short Write Two parameters Transmission */
13598 #define DSI_CMCR_GSR0TX                ((uint32_t)0x00000800U)               /*!< Generic Short Read Zero parameters Transmission */
13599 #define DSI_CMCR_GSR1TX                ((uint32_t)0x00001000U)               /*!< Generic Short Read One parameters Transmission */
13600 #define DSI_CMCR_GSR2TX                ((uint32_t)0x00002000U)               /*!< Generic Short Read Two parameters Transmission */
13601 #define DSI_CMCR_GLWTX                 ((uint32_t)0x00004000U)               /*!< Generic Long Write Transmission */
13602 #define DSI_CMCR_DSW0TX                ((uint32_t)0x00010000U)               /*!< DCS Short Write Zero parameter Transmission */
13603 #define DSI_CMCR_DSW1TX                ((uint32_t)0x00020000U)               /*!< DCS Short Read One parameter Transmission */
13604 #define DSI_CMCR_DSR0TX                ((uint32_t)0x00040000U)               /*!< DCS Short Read Zero parameter Transmission */
13605 #define DSI_CMCR_DLWTX                 ((uint32_t)0x00080000U)               /*!< DCS Long Write Transmission */
13606 #define DSI_CMCR_MRDPS                 ((uint32_t)0x01000000U)               /*!< Maximum Read Packet Size */
13607 
13608 /*******************  Bit definition for DSI_GHCR register  ***************/
13609 #define DSI_GHCR_DT                    ((uint32_t)0x0000003FU)               /*!< Type */
13610 #define DSI_GHCR_DT0                   ((uint32_t)0x00000001U)
13611 #define DSI_GHCR_DT1                   ((uint32_t)0x00000002U)
13612 #define DSI_GHCR_DT2                   ((uint32_t)0x00000004U)
13613 #define DSI_GHCR_DT3                   ((uint32_t)0x00000008U)
13614 #define DSI_GHCR_DT4                   ((uint32_t)0x00000010U)
13615 #define DSI_GHCR_DT5                   ((uint32_t)0x00000020U)
13616 
13617 #define DSI_GHCR_VCID                  ((uint32_t)0x000000C0U)               /*!< Channel */
13618 #define DSI_GHCR_VCID0                 ((uint32_t)0x00000040U)
13619 #define DSI_GHCR_VCID1                 ((uint32_t)0x00000080U)
13620 
13621 #define DSI_GHCR_WCLSB                 ((uint32_t)0x0000FF00U)               /*!< WordCount LSB */
13622 #define DSI_GHCR_WCLSB0                ((uint32_t)0x00000100U)
13623 #define DSI_GHCR_WCLSB1                ((uint32_t)0x00000200U)
13624 #define DSI_GHCR_WCLSB2                ((uint32_t)0x00000400U)
13625 #define DSI_GHCR_WCLSB3                ((uint32_t)0x00000800U)
13626 #define DSI_GHCR_WCLSB4                ((uint32_t)0x00001000U)
13627 #define DSI_GHCR_WCLSB5                ((uint32_t)0x00002000U)
13628 #define DSI_GHCR_WCLSB6                ((uint32_t)0x00004000U)
13629 #define DSI_GHCR_WCLSB7                ((uint32_t)0x00008000U)
13630 
13631 #define DSI_GHCR_WCMSB                 ((uint32_t)0x00FF0000U)               /*!< WordCount MSB */
13632 #define DSI_GHCR_WCMSB0                ((uint32_t)0x00010000U)
13633 #define DSI_GHCR_WCMSB1                ((uint32_t)0x00020000U)
13634 #define DSI_GHCR_WCMSB2                ((uint32_t)0x00040000U)
13635 #define DSI_GHCR_WCMSB3                ((uint32_t)0x00080000U)
13636 #define DSI_GHCR_WCMSB4                ((uint32_t)0x00100000U)
13637 #define DSI_GHCR_WCMSB5                ((uint32_t)0x00200000U)
13638 #define DSI_GHCR_WCMSB6                ((uint32_t)0x00400000U)
13639 #define DSI_GHCR_WCMSB7                ((uint32_t)0x00800000U)
13640 
13641 /*******************  Bit definition for DSI_GPDR register  ***************/
13642 #define DSI_GPDR_DATA1                 ((uint32_t)0x000000FFU)               /*!< Payload Byte 1 */
13643 #define DSI_GPDR_DATA1_0               ((uint32_t)0x00000001U)
13644 #define DSI_GPDR_DATA1_1               ((uint32_t)0x00000002U)
13645 #define DSI_GPDR_DATA1_2               ((uint32_t)0x00000004U)
13646 #define DSI_GPDR_DATA1_3               ((uint32_t)0x00000008U)
13647 #define DSI_GPDR_DATA1_4               ((uint32_t)0x00000010U)
13648 #define DSI_GPDR_DATA1_5               ((uint32_t)0x00000020U)
13649 #define DSI_GPDR_DATA1_6               ((uint32_t)0x00000040U)
13650 #define DSI_GPDR_DATA1_7               ((uint32_t)0x00000080U)
13651 
13652 #define DSI_GPDR_DATA2                 ((uint32_t)0x0000FF00U)               /*!< Payload Byte 2 */
13653 #define DSI_GPDR_DATA2_0               ((uint32_t)0x00000100U)
13654 #define DSI_GPDR_DATA2_1               ((uint32_t)0x00000200U)
13655 #define DSI_GPDR_DATA2_2               ((uint32_t)0x00000400U)
13656 #define DSI_GPDR_DATA2_3               ((uint32_t)0x00000800U)
13657 #define DSI_GPDR_DATA2_4               ((uint32_t)0x00001000U)
13658 #define DSI_GPDR_DATA2_5               ((uint32_t)0x00002000U)
13659 #define DSI_GPDR_DATA2_6               ((uint32_t)0x00004000U)
13660 #define DSI_GPDR_DATA2_7               ((uint32_t)0x00008000U)
13661 
13662 #define DSI_GPDR_DATA3                 ((uint32_t)0x00FF0000U)               /*!< Payload Byte 3 */
13663 #define DSI_GPDR_DATA3_0               ((uint32_t)0x00010000U)
13664 #define DSI_GPDR_DATA3_1               ((uint32_t)0x00020000U)
13665 #define DSI_GPDR_DATA3_2               ((uint32_t)0x00040000U)
13666 #define DSI_GPDR_DATA3_3               ((uint32_t)0x00080000U)
13667 #define DSI_GPDR_DATA3_4               ((uint32_t)0x00100000U)
13668 #define DSI_GPDR_DATA3_5               ((uint32_t)0x00200000U)
13669 #define DSI_GPDR_DATA3_6               ((uint32_t)0x00400000U)
13670 #define DSI_GPDR_DATA3_7               ((uint32_t)0x00800000U)
13671 
13672 #define DSI_GPDR_DATA4                 ((uint32_t)0xFF000000U)               /*!< Payload Byte 4 */
13673 #define DSI_GPDR_DATA4_0               ((uint32_t)0x01000000U)
13674 #define DSI_GPDR_DATA4_1               ((uint32_t)0x02000000U)
13675 #define DSI_GPDR_DATA4_2               ((uint32_t)0x04000000U)
13676 #define DSI_GPDR_DATA4_3               ((uint32_t)0x08000000U)
13677 #define DSI_GPDR_DATA4_4               ((uint32_t)0x10000000U)
13678 #define DSI_GPDR_DATA4_5               ((uint32_t)0x20000000U)
13679 #define DSI_GPDR_DATA4_6               ((uint32_t)0x40000000U)
13680 #define DSI_GPDR_DATA4_7               ((uint32_t)0x80000000U)
13681 
13682 /*******************  Bit definition for DSI_GPSR register  ***************/
13683 #define DSI_GPSR_CMDFE                 ((uint32_t)0x00000001U)               /*!< Command FIFO Empty */
13684 #define DSI_GPSR_CMDFF                 ((uint32_t)0x00000002U)               /*!< Command FIFO Full */
13685 #define DSI_GPSR_PWRFE                 ((uint32_t)0x00000004U)               /*!< Payload Write FIFO Empty */
13686 #define DSI_GPSR_PWRFF                 ((uint32_t)0x00000008U)               /*!< Payload Write FIFO Full */
13687 #define DSI_GPSR_PRDFE                 ((uint32_t)0x00000010U)               /*!< Payload Read FIFO Empty */
13688 #define DSI_GPSR_PRDFF                 ((uint32_t)0x00000020U)               /*!< Payload Read FIFO Full */
13689 #define DSI_GPSR_RCB                   ((uint32_t)0x00000040U)               /*!< Read Command Busy */
13690 
13691 /*******************  Bit definition for DSI_TCCR0 register  **************/
13692 #define DSI_TCCR0_LPRX_TOCNT           ((uint32_t)0x0000FFFFU)               /*!< Low-power Reception Timeout Counter */
13693 #define DSI_TCCR0_LPRX_TOCNT0          ((uint32_t)0x00000001U)
13694 #define DSI_TCCR0_LPRX_TOCNT1          ((uint32_t)0x00000002U)
13695 #define DSI_TCCR0_LPRX_TOCNT2          ((uint32_t)0x00000004U)
13696 #define DSI_TCCR0_LPRX_TOCNT3          ((uint32_t)0x00000008U)
13697 #define DSI_TCCR0_LPRX_TOCNT4          ((uint32_t)0x00000010U)
13698 #define DSI_TCCR0_LPRX_TOCNT5          ((uint32_t)0x00000020U)
13699 #define DSI_TCCR0_LPRX_TOCNT6          ((uint32_t)0x00000040U)
13700 #define DSI_TCCR0_LPRX_TOCNT7          ((uint32_t)0x00000080U)
13701 #define DSI_TCCR0_LPRX_TOCNT8          ((uint32_t)0x00000100U)
13702 #define DSI_TCCR0_LPRX_TOCNT9          ((uint32_t)0x00000200U)
13703 #define DSI_TCCR0_LPRX_TOCNT10         ((uint32_t)0x00000400U)
13704 #define DSI_TCCR0_LPRX_TOCNT11         ((uint32_t)0x00000800U)
13705 #define DSI_TCCR0_LPRX_TOCNT12         ((uint32_t)0x00001000U)
13706 #define DSI_TCCR0_LPRX_TOCNT13         ((uint32_t)0x00002000U)
13707 #define DSI_TCCR0_LPRX_TOCNT14         ((uint32_t)0x00004000U)
13708 #define DSI_TCCR0_LPRX_TOCNT15         ((uint32_t)0x00008000U)
13709 
13710 #define DSI_TCCR0_HSTX_TOCNT           ((uint32_t)0xFFFF0000U)               /*!< High-Speed Transmission Timeout Counter */
13711 #define DSI_TCCR0_HSTX_TOCNT0          ((uint32_t)0x00010000U)
13712 #define DSI_TCCR0_HSTX_TOCNT1          ((uint32_t)0x00020000U)
13713 #define DSI_TCCR0_HSTX_TOCNT2          ((uint32_t)0x00040000U)
13714 #define DSI_TCCR0_HSTX_TOCNT3          ((uint32_t)0x00080000U)
13715 #define DSI_TCCR0_HSTX_TOCNT4          ((uint32_t)0x00100000U)
13716 #define DSI_TCCR0_HSTX_TOCNT5          ((uint32_t)0x00200000U)
13717 #define DSI_TCCR0_HSTX_TOCNT6          ((uint32_t)0x00400000U)
13718 #define DSI_TCCR0_HSTX_TOCNT7          ((uint32_t)0x00800000U)
13719 #define DSI_TCCR0_HSTX_TOCNT8          ((uint32_t)0x01000000U)
13720 #define DSI_TCCR0_HSTX_TOCNT9          ((uint32_t)0x02000000U)
13721 #define DSI_TCCR0_HSTX_TOCNT10         ((uint32_t)0x04000000U)
13722 #define DSI_TCCR0_HSTX_TOCNT11         ((uint32_t)0x08000000U)
13723 #define DSI_TCCR0_HSTX_TOCNT12         ((uint32_t)0x10000000U)
13724 #define DSI_TCCR0_HSTX_TOCNT13         ((uint32_t)0x20000000U)
13725 #define DSI_TCCR0_HSTX_TOCNT14         ((uint32_t)0x40000000U)
13726 #define DSI_TCCR0_HSTX_TOCNT15         ((uint32_t)0x80000000U)
13727 
13728 /*******************  Bit definition for DSI_TCCR1 register  **************/
13729 #define DSI_TCCR1_HSRD_TOCNT           ((uint32_t)0x0000FFFFU)               /*!< High-Speed Read Timeout Counter */
13730 #define DSI_TCCR1_HSRD_TOCNT0          ((uint32_t)0x00000001U)
13731 #define DSI_TCCR1_HSRD_TOCNT1          ((uint32_t)0x00000002U)
13732 #define DSI_TCCR1_HSRD_TOCNT2          ((uint32_t)0x00000004U)
13733 #define DSI_TCCR1_HSRD_TOCNT3          ((uint32_t)0x00000008U)
13734 #define DSI_TCCR1_HSRD_TOCNT4          ((uint32_t)0x00000010U)
13735 #define DSI_TCCR1_HSRD_TOCNT5          ((uint32_t)0x00000020U)
13736 #define DSI_TCCR1_HSRD_TOCNT6          ((uint32_t)0x00000040U)
13737 #define DSI_TCCR1_HSRD_TOCNT7          ((uint32_t)0x00000080U)
13738 #define DSI_TCCR1_HSRD_TOCNT8          ((uint32_t)0x00000100U)
13739 #define DSI_TCCR1_HSRD_TOCNT9          ((uint32_t)0x00000200U)
13740 #define DSI_TCCR1_HSRD_TOCNT10         ((uint32_t)0x00000400U)
13741 #define DSI_TCCR1_HSRD_TOCNT11         ((uint32_t)0x00000800U)
13742 #define DSI_TCCR1_HSRD_TOCNT12         ((uint32_t)0x00001000U)
13743 #define DSI_TCCR1_HSRD_TOCNT13         ((uint32_t)0x00002000U)
13744 #define DSI_TCCR1_HSRD_TOCNT14         ((uint32_t)0x00004000U)
13745 #define DSI_TCCR1_HSRD_TOCNT15         ((uint32_t)0x00008000U)
13746 
13747 /*******************  Bit definition for DSI_TCCR2 register  **************/
13748 #define DSI_TCCR2_LPRD_TOCNT           ((uint32_t)0x0000FFFFU)               /*!< Low-Power Read Timeout Counter */
13749 #define DSI_TCCR2_LPRD_TOCNT0          ((uint32_t)0x00000001U)
13750 #define DSI_TCCR2_LPRD_TOCNT1          ((uint32_t)0x00000002U)
13751 #define DSI_TCCR2_LPRD_TOCNT2          ((uint32_t)0x00000004U)
13752 #define DSI_TCCR2_LPRD_TOCNT3          ((uint32_t)0x00000008U)
13753 #define DSI_TCCR2_LPRD_TOCNT4          ((uint32_t)0x00000010U)
13754 #define DSI_TCCR2_LPRD_TOCNT5          ((uint32_t)0x00000020U)
13755 #define DSI_TCCR2_LPRD_TOCNT6          ((uint32_t)0x00000040U)
13756 #define DSI_TCCR2_LPRD_TOCNT7          ((uint32_t)0x00000080U)
13757 #define DSI_TCCR2_LPRD_TOCNT8          ((uint32_t)0x00000100U)
13758 #define DSI_TCCR2_LPRD_TOCNT9          ((uint32_t)0x00000200U)
13759 #define DSI_TCCR2_LPRD_TOCNT10         ((uint32_t)0x00000400U)
13760 #define DSI_TCCR2_LPRD_TOCNT11         ((uint32_t)0x00000800U)
13761 #define DSI_TCCR2_LPRD_TOCNT12         ((uint32_t)0x00001000U)
13762 #define DSI_TCCR2_LPRD_TOCNT13         ((uint32_t)0x00002000U)
13763 #define DSI_TCCR2_LPRD_TOCNT14         ((uint32_t)0x00004000U)
13764 #define DSI_TCCR2_LPRD_TOCNT15         ((uint32_t)0x00008000U)
13765 
13766 /*******************  Bit definition for DSI_TCCR3 register  **************/
13767 #define DSI_TCCR3_HSWR_TOCNT           ((uint32_t)0x0000FFFFU)               /*!< High-Speed Write Timeout Counter */
13768 #define DSI_TCCR3_HSWR_TOCNT0          ((uint32_t)0x00000001U)
13769 #define DSI_TCCR3_HSWR_TOCNT1          ((uint32_t)0x00000002U)
13770 #define DSI_TCCR3_HSWR_TOCNT2          ((uint32_t)0x00000004U)
13771 #define DSI_TCCR3_HSWR_TOCNT3          ((uint32_t)0x00000008U)
13772 #define DSI_TCCR3_HSWR_TOCNT4          ((uint32_t)0x00000010U)
13773 #define DSI_TCCR3_HSWR_TOCNT5          ((uint32_t)0x00000020U)
13774 #define DSI_TCCR3_HSWR_TOCNT6          ((uint32_t)0x00000040U)
13775 #define DSI_TCCR3_HSWR_TOCNT7          ((uint32_t)0x00000080U)
13776 #define DSI_TCCR3_HSWR_TOCNT8          ((uint32_t)0x00000100U)
13777 #define DSI_TCCR3_HSWR_TOCNT9          ((uint32_t)0x00000200U)
13778 #define DSI_TCCR3_HSWR_TOCNT10         ((uint32_t)0x00000400U)
13779 #define DSI_TCCR3_HSWR_TOCNT11         ((uint32_t)0x00000800U)
13780 #define DSI_TCCR3_HSWR_TOCNT12         ((uint32_t)0x00001000U)
13781 #define DSI_TCCR3_HSWR_TOCNT13         ((uint32_t)0x00002000U)
13782 #define DSI_TCCR3_HSWR_TOCNT14         ((uint32_t)0x00004000U)
13783 #define DSI_TCCR3_HSWR_TOCNT15         ((uint32_t)0x00008000U)
13784 
13785 #define DSI_TCCR3_PM                   ((uint32_t)0x01000000U)               /*!< Presp Mode */
13786 
13787 /*******************  Bit definition for DSI_TCCR4 register  **************/
13788 #define DSI_TCCR4_LPWR_TOCNT           ((uint32_t)0x0000FFFFU)               /*!< Low-Power Write Timeout Counter */
13789 #define DSI_TCCR4_LPWR_TOCNT0          ((uint32_t)0x00000001U)
13790 #define DSI_TCCR4_LPWR_TOCNT1          ((uint32_t)0x00000002U)
13791 #define DSI_TCCR4_LPWR_TOCNT2          ((uint32_t)0x00000004U)
13792 #define DSI_TCCR4_LPWR_TOCNT3          ((uint32_t)0x00000008U)
13793 #define DSI_TCCR4_LPWR_TOCNT4          ((uint32_t)0x00000010U)
13794 #define DSI_TCCR4_LPWR_TOCNT5          ((uint32_t)0x00000020U)
13795 #define DSI_TCCR4_LPWR_TOCNT6          ((uint32_t)0x00000040U)
13796 #define DSI_TCCR4_LPWR_TOCNT7          ((uint32_t)0x00000080U)
13797 #define DSI_TCCR4_LPWR_TOCNT8          ((uint32_t)0x00000100U)
13798 #define DSI_TCCR4_LPWR_TOCNT9          ((uint32_t)0x00000200U)
13799 #define DSI_TCCR4_LPWR_TOCNT10         ((uint32_t)0x00000400U)
13800 #define DSI_TCCR4_LPWR_TOCNT11         ((uint32_t)0x00000800U)
13801 #define DSI_TCCR4_LPWR_TOCNT12         ((uint32_t)0x00001000U)
13802 #define DSI_TCCR4_LPWR_TOCNT13         ((uint32_t)0x00002000U)
13803 #define DSI_TCCR4_LPWR_TOCNT14         ((uint32_t)0x00004000U)
13804 #define DSI_TCCR4_LPWR_TOCNT15         ((uint32_t)0x00008000U)
13805 
13806 /*******************  Bit definition for DSI_TCCR5 register  **************/
13807 #define DSI_TCCR5_BTA_TOCNT            ((uint32_t)0x0000FFFFU)               /*!< Bus-Turn-Around Timeout Counter */
13808 #define DSI_TCCR5_BTA_TOCNT0           ((uint32_t)0x00000001U)
13809 #define DSI_TCCR5_BTA_TOCNT1           ((uint32_t)0x00000002U)
13810 #define DSI_TCCR5_BTA_TOCNT2           ((uint32_t)0x00000004U)
13811 #define DSI_TCCR5_BTA_TOCNT3           ((uint32_t)0x00000008U)
13812 #define DSI_TCCR5_BTA_TOCNT4           ((uint32_t)0x00000010U)
13813 #define DSI_TCCR5_BTA_TOCNT5           ((uint32_t)0x00000020U)
13814 #define DSI_TCCR5_BTA_TOCNT6           ((uint32_t)0x00000040U)
13815 #define DSI_TCCR5_BTA_TOCNT7           ((uint32_t)0x00000080U)
13816 #define DSI_TCCR5_BTA_TOCNT8           ((uint32_t)0x00000100U)
13817 #define DSI_TCCR5_BTA_TOCNT9           ((uint32_t)0x00000200U)
13818 #define DSI_TCCR5_BTA_TOCNT10          ((uint32_t)0x00000400U)
13819 #define DSI_TCCR5_BTA_TOCNT11          ((uint32_t)0x00000800U)
13820 #define DSI_TCCR5_BTA_TOCNT12          ((uint32_t)0x00001000U)
13821 #define DSI_TCCR5_BTA_TOCNT13          ((uint32_t)0x00002000U)
13822 #define DSI_TCCR5_BTA_TOCNT14          ((uint32_t)0x00004000U)
13823 #define DSI_TCCR5_BTA_TOCNT15          ((uint32_t)0x00008000U)
13824 
13825 /*******************  Bit definition for DSI_TDCR register  ***************/
13826 #define DSI_TDCR_3DM                   ((uint32_t)0x00000003U)               /*!< 3D Mode */
13827 #define DSI_TDCR_3DM0                  ((uint32_t)0x00000001U)
13828 #define DSI_TDCR_3DM1                  ((uint32_t)0x00000002U)
13829 
13830 #define DSI_TDCR_3DF                   ((uint32_t)0x0000000CU)               /*!< 3D Format */
13831 #define DSI_TDCR_3DF0                  ((uint32_t)0x00000004U)
13832 #define DSI_TDCR_3DF1                  ((uint32_t)0x00000008U)
13833 
13834 #define DSI_TDCR_SVS                   ((uint32_t)0x00000010U)               /*!< Second VSYNC */
13835 #define DSI_TDCR_RF                    ((uint32_t)0x00000020U)               /*!< Right First */
13836 #define DSI_TDCR_S3DC                  ((uint32_t)0x00010000U)               /*!< Send 3D Control */
13837 
13838 /*******************  Bit definition for DSI_CLCR register  ***************/
13839 #define DSI_CLCR_DPCC                  ((uint32_t)0x00000001U)               /*!< D-PHY Clock Control */
13840 #define DSI_CLCR_ACR                   ((uint32_t)0x00000002U)               /*!< Automatic Clocklane Control */
13841 
13842 /*******************  Bit definition for DSI_CLTCR register  **************/
13843 #define DSI_CLTCR_LP2HS_TIME           ((uint32_t)0x000003FFU)               /*!< Low-Power to High-Speed Time */
13844 #define DSI_CLTCR_LP2HS_TIME0          ((uint32_t)0x00000001U)
13845 #define DSI_CLTCR_LP2HS_TIME1          ((uint32_t)0x00000002U)
13846 #define DSI_CLTCR_LP2HS_TIME2          ((uint32_t)0x00000004U)
13847 #define DSI_CLTCR_LP2HS_TIME3          ((uint32_t)0x00000008U)
13848 #define DSI_CLTCR_LP2HS_TIME4          ((uint32_t)0x00000010U)
13849 #define DSI_CLTCR_LP2HS_TIME5          ((uint32_t)0x00000020U)
13850 #define DSI_CLTCR_LP2HS_TIME6          ((uint32_t)0x00000040U)
13851 #define DSI_CLTCR_LP2HS_TIME7          ((uint32_t)0x00000080U)
13852 #define DSI_CLTCR_LP2HS_TIME8          ((uint32_t)0x00000100U)
13853 #define DSI_CLTCR_LP2HS_TIME9          ((uint32_t)0x00000200U)
13854 
13855 #define DSI_CLTCR_HS2LP_TIME           ((uint32_t)0x03FF0000U)               /*!< High-Speed to Low-Power Time */
13856 #define DSI_CLTCR_HS2LP_TIME0          ((uint32_t)0x00010000U)
13857 #define DSI_CLTCR_HS2LP_TIME1          ((uint32_t)0x00020000U)
13858 #define DSI_CLTCR_HS2LP_TIME2          ((uint32_t)0x00040000U)
13859 #define DSI_CLTCR_HS2LP_TIME3          ((uint32_t)0x00080000U)
13860 #define DSI_CLTCR_HS2LP_TIME4          ((uint32_t)0x00100000U)
13861 #define DSI_CLTCR_HS2LP_TIME5          ((uint32_t)0x00200000U)
13862 #define DSI_CLTCR_HS2LP_TIME6          ((uint32_t)0x00400000U)
13863 #define DSI_CLTCR_HS2LP_TIME7          ((uint32_t)0x00800000U)
13864 #define DSI_CLTCR_HS2LP_TIME8          ((uint32_t)0x01000000U)
13865 #define DSI_CLTCR_HS2LP_TIME9          ((uint32_t)0x02000000U)
13866 
13867 /*******************  Bit definition for DSI_DLTCR register  **************/
13868 #define DSI_DLTCR_LP2HS_TIME           ((uint32_t)0x000003FFU)               /*!< Low-Power to High-Speed Time */
13869 #define DSI_DLTCR_LP2HS_TIME0          ((uint32_t)0x00000001U)
13870 #define DSI_DLTCR_LP2HS_TIME1          ((uint32_t)0x00000002U)
13871 #define DSI_DLTCR_LP2HS_TIME2          ((uint32_t)0x00000004U)
13872 #define DSI_DLTCR_LP2HS_TIME3          ((uint32_t)0x00000008U)
13873 #define DSI_DLTCR_LP2HS_TIME4          ((uint32_t)0x00000010U)
13874 #define DSI_DLTCR_LP2HS_TIME5          ((uint32_t)0x00000020U)
13875 #define DSI_DLTCR_LP2HS_TIME6          ((uint32_t)0x00000040U)
13876 #define DSI_DLTCR_LP2HS_TIME7          ((uint32_t)0x00000080U)
13877 #define DSI_DLTCR_LP2HS_TIME8          ((uint32_t)0x00000100U)
13878 #define DSI_DLTCR_LP2HS_TIME9          ((uint32_t)0x00000200U)
13879 
13880 #define DSI_DLTCR_HS2LP_TIME           ((uint32_t)0x03FF0000U)               /*!< High-Speed to Low-Power Time */
13881 #define DSI_DLTCR_HS2LP_TIME0          ((uint32_t)0x00010000U)
13882 #define DSI_DLTCR_HS2LP_TIME1          ((uint32_t)0x00020000U)
13883 #define DSI_DLTCR_HS2LP_TIME2          ((uint32_t)0x00040000U)
13884 #define DSI_DLTCR_HS2LP_TIME3          ((uint32_t)0x00080000U)
13885 #define DSI_DLTCR_HS2LP_TIME4          ((uint32_t)0x00100000U)
13886 #define DSI_DLTCR_HS2LP_TIME5          ((uint32_t)0x00200000U)
13887 #define DSI_DLTCR_HS2LP_TIME6          ((uint32_t)0x00400000U)
13888 #define DSI_DLTCR_HS2LP_TIME7          ((uint32_t)0x00800000U)
13889 #define DSI_DLTCR_HS2LP_TIME8          ((uint32_t)0x01000000U)
13890 #define DSI_DLTCR_HS2LP_TIME9          ((uint32_t)0x02000000U)
13891 
13892 /*******************  Bit definition for DSI_PCTLR register  **************/
13893 #define DSI_PCTLR_DEN                  ((uint32_t)0x00000002U)               /*!< Digital Enable */
13894 #define DSI_PCTLR_CKE                  ((uint32_t)0x00000004U)               /*!< Clock Enable */
13895 
13896 /*******************  Bit definition for DSI_PCONFR register  *************/
13897 #define DSI_PCONFR_NL                  ((uint32_t)0x00000003U)               /*!< Number of Lanes */
13898 #define DSI_PCONFR_NL0                 ((uint32_t)0x00000001U)
13899 #define DSI_PCONFR_NL1                 ((uint32_t)0x00000002U)
13900 
13901 #define DSI_PCONFR_SW_TIME             ((uint32_t)0x0000FF00U)               /*!< Stop Wait Time */
13902 #define DSI_PCONFR_SW_TIME0            ((uint32_t)0x00000100U)
13903 #define DSI_PCONFR_SW_TIME1            ((uint32_t)0x00000200U)
13904 #define DSI_PCONFR_SW_TIME2            ((uint32_t)0x00000400U)
13905 #define DSI_PCONFR_SW_TIME3            ((uint32_t)0x00000800U)
13906 #define DSI_PCONFR_SW_TIME4            ((uint32_t)0x00001000U)
13907 #define DSI_PCONFR_SW_TIME5            ((uint32_t)0x00002000U)
13908 #define DSI_PCONFR_SW_TIME6            ((uint32_t)0x00004000U)
13909 #define DSI_PCONFR_SW_TIME7            ((uint32_t)0x00008000U)
13910 
13911 /*******************  Bit definition for DSI_PUCR register  ***************/
13912 #define DSI_PUCR_URCL                  ((uint32_t)0x00000001U)               /*!< ULPS Request on Clock Lane */
13913 #define DSI_PUCR_UECL                  ((uint32_t)0x00000002U)               /*!< ULPS Exit on Clock Lane */
13914 #define DSI_PUCR_URDL                  ((uint32_t)0x00000004U)               /*!< ULPS Request on Data Lane */
13915 #define DSI_PUCR_UEDL                  ((uint32_t)0x00000008U)               /*!< ULPS Exit on Data Lane */
13916 
13917 /*******************  Bit definition for DSI_PTTCR register  **************/
13918 #define DSI_PTTCR_TX_TRIG              ((uint32_t)0x0000000FU)               /*!< Transmission Trigger */
13919 #define DSI_PTTCR_TX_TRIG0             ((uint32_t)0x00000001U)
13920 #define DSI_PTTCR_TX_TRIG1             ((uint32_t)0x00000002U)
13921 #define DSI_PTTCR_TX_TRIG2             ((uint32_t)0x00000004U)
13922 #define DSI_PTTCR_TX_TRIG3             ((uint32_t)0x00000008U)
13923 
13924 /*******************  Bit definition for DSI_PSR register  ****************/
13925 #define DSI_PSR_PD                     ((uint32_t)0x00000002U)               /*!< PHY Direction */
13926 #define DSI_PSR_PSSC                   ((uint32_t)0x00000004U)               /*!< PHY Stop State Clock lane */
13927 #define DSI_PSR_UANC                   ((uint32_t)0x00000008U)               /*!< ULPS Active Not Clock lane */
13928 #define DSI_PSR_PSS0                   ((uint32_t)0x00000010U)               /*!< PHY Stop State lane 0 */
13929 #define DSI_PSR_UAN0                   ((uint32_t)0x00000020U)               /*!< ULPS Active Not lane 0 */
13930 #define DSI_PSR_RUE0                   ((uint32_t)0x00000040U)               /*!< RX ULPS Escape lane 0 */
13931 #define DSI_PSR_PSS1                   ((uint32_t)0x00000080U)               /*!< PHY Stop State lane 1 */
13932 #define DSI_PSR_UAN1                   ((uint32_t)0x00000100U)               /*!< ULPS Active Not lane 1 */
13933 
13934 /*******************  Bit definition for DSI_ISR0 register  ***************/
13935 #define DSI_ISR0_AE0                   ((uint32_t)0x00000001U)               /*!< Acknowledge Error 0 */
13936 #define DSI_ISR0_AE1                   ((uint32_t)0x00000002U)               /*!< Acknowledge Error 1 */
13937 #define DSI_ISR0_AE2                   ((uint32_t)0x00000004U)               /*!< Acknowledge Error 2 */
13938 #define DSI_ISR0_AE3                   ((uint32_t)0x00000008U)               /*!< Acknowledge Error 3 */
13939 #define DSI_ISR0_AE4                   ((uint32_t)0x00000010U)               /*!< Acknowledge Error 4 */
13940 #define DSI_ISR0_AE5                   ((uint32_t)0x00000020U)               /*!< Acknowledge Error 5 */
13941 #define DSI_ISR0_AE6                   ((uint32_t)0x00000040U)               /*!< Acknowledge Error 6 */
13942 #define DSI_ISR0_AE7                   ((uint32_t)0x00000080U)               /*!< Acknowledge Error 7 */
13943 #define DSI_ISR0_AE8                   ((uint32_t)0x00000100U)               /*!< Acknowledge Error 8 */
13944 #define DSI_ISR0_AE9                   ((uint32_t)0x00000200U)               /*!< Acknowledge Error 9 */
13945 #define DSI_ISR0_AE10                  ((uint32_t)0x00000400U)               /*!< Acknowledge Error 10 */
13946 #define DSI_ISR0_AE11                  ((uint32_t)0x00000800U)               /*!< Acknowledge Error 11 */
13947 #define DSI_ISR0_AE12                  ((uint32_t)0x00001000U)               /*!< Acknowledge Error 12 */
13948 #define DSI_ISR0_AE13                  ((uint32_t)0x00002000U)               /*!< Acknowledge Error 13 */
13949 #define DSI_ISR0_AE14                  ((uint32_t)0x00004000U)               /*!< Acknowledge Error 14 */
13950 #define DSI_ISR0_AE15                  ((uint32_t)0x00008000U)               /*!< Acknowledge Error 15 */
13951 #define DSI_ISR0_PE0                   ((uint32_t)0x00010000U)               /*!< PHY Error 0 */
13952 #define DSI_ISR0_PE1                   ((uint32_t)0x00020000U)               /*!< PHY Error 1 */
13953 #define DSI_ISR0_PE2                   ((uint32_t)0x00040000U)               /*!< PHY Error 2 */
13954 #define DSI_ISR0_PE3                   ((uint32_t)0x00080000U)               /*!< PHY Error 3 */
13955 #define DSI_ISR0_PE4                   ((uint32_t)0x00100000U)               /*!< PHY Error 4 */
13956 
13957 /*******************  Bit definition for DSI_ISR1 register  ***************/
13958 #define DSI_ISR1_TOHSTX                ((uint32_t)0x00000001U)               /*!< Timeout High-Speed Transmission */
13959 #define DSI_ISR1_TOLPRX                ((uint32_t)0x00000002U)               /*!< Timeout Low-Power Reception */
13960 #define DSI_ISR1_ECCSE                 ((uint32_t)0x00000004U)               /*!< ECC Single-bit Error */
13961 #define DSI_ISR1_ECCME                 ((uint32_t)0x00000008U)               /*!< ECC Multi-bit Error */
13962 #define DSI_ISR1_CRCE                  ((uint32_t)0x00000010U)               /*!< CRC Error */
13963 #define DSI_ISR1_PSE                   ((uint32_t)0x00000020U)               /*!< Packet Size Error */
13964 #define DSI_ISR1_EOTPE                 ((uint32_t)0x00000040U)               /*!< EoTp Error */
13965 #define DSI_ISR1_LPWRE                 ((uint32_t)0x00000080U)               /*!< LTDC Payload Write Error */
13966 #define DSI_ISR1_GCWRE                 ((uint32_t)0x00000100U)               /*!< Generic Command Write Error */
13967 #define DSI_ISR1_GPWRE                 ((uint32_t)0x00000200U)               /*!< Generic Payload Write Error */
13968 #define DSI_ISR1_GPTXE                 ((uint32_t)0x00000400U)               /*!< Generic Payload Transmit Error */
13969 #define DSI_ISR1_GPRDE                 ((uint32_t)0x00000800U)               /*!< Generic Payload Read Error */
13970 #define DSI_ISR1_GPRXE                 ((uint32_t)0x00001000U)               /*!< Generic Payload Receive Error */
13971 
13972 /*******************  Bit definition for DSI_IER0 register  ***************/
13973 #define DSI_IER0_AE0IE                 ((uint32_t)0x00000001U)               /*!< Acknowledge Error 0 Interrupt Enable */
13974 #define DSI_IER0_AE1IE                 ((uint32_t)0x00000002U)               /*!< Acknowledge Error 1 Interrupt Enable */
13975 #define DSI_IER0_AE2IE                 ((uint32_t)0x00000004U)               /*!< Acknowledge Error 2 Interrupt Enable */
13976 #define DSI_IER0_AE3IE                 ((uint32_t)0x00000008U)               /*!< Acknowledge Error 3 Interrupt Enable */
13977 #define DSI_IER0_AE4IE                 ((uint32_t)0x00000010U)               /*!< Acknowledge Error 4 Interrupt Enable */
13978 #define DSI_IER0_AE5IE                 ((uint32_t)0x00000020U)               /*!< Acknowledge Error 5 Interrupt Enable */
13979 #define DSI_IER0_AE6IE                 ((uint32_t)0x00000040U)               /*!< Acknowledge Error 6 Interrupt Enable */
13980 #define DSI_IER0_AE7IE                 ((uint32_t)0x00000080U)               /*!< Acknowledge Error 7 Interrupt Enable */
13981 #define DSI_IER0_AE8IE                 ((uint32_t)0x00000100U)               /*!< Acknowledge Error 8 Interrupt Enable */
13982 #define DSI_IER0_AE9IE                 ((uint32_t)0x00000200U)               /*!< Acknowledge Error 9 Interrupt Enable */
13983 #define DSI_IER0_AE10IE                ((uint32_t)0x00000400U)               /*!< Acknowledge Error 10 Interrupt Enable */
13984 #define DSI_IER0_AE11IE                ((uint32_t)0x00000800U)               /*!< Acknowledge Error 11 Interrupt Enable */
13985 #define DSI_IER0_AE12IE                ((uint32_t)0x00001000U)               /*!< Acknowledge Error 12 Interrupt Enable */
13986 #define DSI_IER0_AE13IE                ((uint32_t)0x00002000U)               /*!< Acknowledge Error 13 Interrupt Enable */
13987 #define DSI_IER0_AE14IE                ((uint32_t)0x00004000U)               /*!< Acknowledge Error 14 Interrupt Enable */
13988 #define DSI_IER0_AE15IE                ((uint32_t)0x00008000U)               /*!< Acknowledge Error 15 Interrupt Enable */
13989 #define DSI_IER0_PE0IE                 ((uint32_t)0x00010000U)               /*!< PHY Error 0 Interrupt Enable */
13990 #define DSI_IER0_PE1IE                 ((uint32_t)0x00020000U)               /*!< PHY Error 1 Interrupt Enable */
13991 #define DSI_IER0_PE2IE                 ((uint32_t)0x00040000U)               /*!< PHY Error 2 Interrupt Enable */
13992 #define DSI_IER0_PE3IE                 ((uint32_t)0x00080000U)               /*!< PHY Error 3 Interrupt Enable */
13993 #define DSI_IER0_PE4IE                 ((uint32_t)0x00100000U)               /*!< PHY Error 4 Interrupt Enable */
13994 
13995 /*******************  Bit definition for DSI_IER1 register  ***************/
13996 #define DSI_IER1_TOHSTXIE              ((uint32_t)0x00000001U)               /*!< Timeout High-Speed Transmission Interrupt Enable */
13997 #define DSI_IER1_TOLPRXIE              ((uint32_t)0x00000002U)               /*!< Timeout Low-Power Reception Interrupt Enable */
13998 #define DSI_IER1_ECCSEIE               ((uint32_t)0x00000004U)               /*!< ECC Single-bit Error Interrupt Enable */
13999 #define DSI_IER1_ECCMEIE               ((uint32_t)0x00000008U)               /*!< ECC Multi-bit Error Interrupt Enable */
14000 #define DSI_IER1_CRCEIE                ((uint32_t)0x00000010U)               /*!< CRC Error Interrupt Enable */
14001 #define DSI_IER1_PSEIE                 ((uint32_t)0x00000020U)               /*!< Packet Size Error Interrupt Enable */
14002 #define DSI_IER1_EOTPEIE               ((uint32_t)0x00000040U)               /*!< EoTp Error Interrupt Enable */
14003 #define DSI_IER1_LPWREIE               ((uint32_t)0x00000080U)               /*!< LTDC Payload Write Error Interrupt Enable */
14004 #define DSI_IER1_GCWREIE               ((uint32_t)0x00000100U)               /*!< Generic Command Write Error Interrupt Enable */
14005 #define DSI_IER1_GPWREIE               ((uint32_t)0x00000200U)               /*!< Generic Payload Write Error Interrupt Enable */
14006 #define DSI_IER1_GPTXEIE               ((uint32_t)0x00000400U)               /*!< Generic Payload Transmit Error Interrupt Enable */
14007 #define DSI_IER1_GPRDEIE               ((uint32_t)0x00000800U)               /*!< Generic Payload Read Error Interrupt Enable */
14008 #define DSI_IER1_GPRXEIE               ((uint32_t)0x00001000U)               /*!< Generic Payload Receive Error Interrupt Enable */
14009 
14010 /*******************  Bit definition for DSI_FIR0 register  ***************/
14011 #define DSI_FIR0_FAE0                  ((uint32_t)0x00000001U)               /*!< Force Acknowledge Error 0 */
14012 #define DSI_FIR0_FAE1                  ((uint32_t)0x00000002U)               /*!< Force Acknowledge Error 1 */
14013 #define DSI_FIR0_FAE2                  ((uint32_t)0x00000004U)               /*!< Force Acknowledge Error 2 */
14014 #define DSI_FIR0_FAE3                  ((uint32_t)0x00000008U)               /*!< Force Acknowledge Error 3 */
14015 #define DSI_FIR0_FAE4                  ((uint32_t)0x00000010U)               /*!< Force Acknowledge Error 4 */
14016 #define DSI_FIR0_FAE5                  ((uint32_t)0x00000020U)               /*!< Force Acknowledge Error 5 */
14017 #define DSI_FIR0_FAE6                  ((uint32_t)0x00000040U)               /*!< Force Acknowledge Error 6 */
14018 #define DSI_FIR0_FAE7                  ((uint32_t)0x00000080U)               /*!< Force Acknowledge Error 7 */
14019 #define DSI_FIR0_FAE8                  ((uint32_t)0x00000100U)               /*!< Force Acknowledge Error 8 */
14020 #define DSI_FIR0_FAE9                  ((uint32_t)0x00000200U)               /*!< Force Acknowledge Error 9 */
14021 #define DSI_FIR0_FAE10                 ((uint32_t)0x00000400U)               /*!< Force Acknowledge Error 10 */
14022 #define DSI_FIR0_FAE11                 ((uint32_t)0x00000800U)               /*!< Force Acknowledge Error 11 */
14023 #define DSI_FIR0_FAE12                 ((uint32_t)0x00001000U)               /*!< Force Acknowledge Error 12 */
14024 #define DSI_FIR0_FAE13                 ((uint32_t)0x00002000U)               /*!< Force Acknowledge Error 13 */
14025 #define DSI_FIR0_FAE14                 ((uint32_t)0x00004000U)               /*!< Force Acknowledge Error 14 */
14026 #define DSI_FIR0_FAE15                 ((uint32_t)0x00008000U)               /*!< Force Acknowledge Error 15 */
14027 #define DSI_FIR0_FPE0                  ((uint32_t)0x00010000U)               /*!< Force PHY Error 0 */
14028 #define DSI_FIR0_FPE1                  ((uint32_t)0x00020000U)               /*!< Force PHY Error 1 */
14029 #define DSI_FIR0_FPE2                  ((uint32_t)0x00040000U)               /*!< Force PHY Error 2 */
14030 #define DSI_FIR0_FPE3                  ((uint32_t)0x00080000U)               /*!< Force PHY Error 3 */
14031 #define DSI_FIR0_FPE4                  ((uint32_t)0x00100000U)               /*!< Force PHY Error 4 */
14032 
14033 /*******************  Bit definition for DSI_FIR1 register  ***************/
14034 #define DSI_FIR1_FTOHSTX               ((uint32_t)0x00000001U)               /*!< Force Timeout High-Speed Transmission */
14035 #define DSI_FIR1_FTOLPRX               ((uint32_t)0x00000002U)               /*!< Force Timeout Low-Power Reception */
14036 #define DSI_FIR1_FECCSE                ((uint32_t)0x00000004U)               /*!< Force ECC Single-bit Error */
14037 #define DSI_FIR1_FECCME                ((uint32_t)0x00000008U)               /*!< Force ECC Multi-bit Error */
14038 #define DSI_FIR1_FCRCE                 ((uint32_t)0x00000010U)               /*!< Force CRC Error */
14039 #define DSI_FIR1_FPSE                  ((uint32_t)0x00000020U)               /*!< Force Packet Size Error */
14040 #define DSI_FIR1_FEOTPE                ((uint32_t)0x00000040U)               /*!< Force EoTp Error */
14041 #define DSI_FIR1_FLPWRE                ((uint32_t)0x00000080U)               /*!< Force LTDC Payload Write Error */
14042 #define DSI_FIR1_FGCWRE                ((uint32_t)0x00000100U)               /*!< Force Generic Command Write Error */
14043 #define DSI_FIR1_FGPWRE                ((uint32_t)0x00000200U)               /*!< Force Generic Payload Write Error */
14044 #define DSI_FIR1_FGPTXE                ((uint32_t)0x00000400U)               /*!< Force Generic Payload Transmit Error */
14045 #define DSI_FIR1_FGPRDE                ((uint32_t)0x00000800U)               /*!< Force Generic Payload Read Error */
14046 #define DSI_FIR1_FGPRXE                ((uint32_t)0x00001000U)               /*!< Force Generic Payload Receive Error */
14047 
14048 /*******************  Bit definition for DSI_DLTRCR register  *************/
14049 #define DSI_DLTRCR_MRD_TIME            ((uint32_t)0x00007FFFU)               /*!< Maximum Read Time */
14050 #define DSI_DLTRCR_MRD_TIME0           ((uint32_t)0x00000001U)
14051 #define DSI_DLTRCR_MRD_TIME1           ((uint32_t)0x00000002U)
14052 #define DSI_DLTRCR_MRD_TIME2           ((uint32_t)0x00000004U)
14053 #define DSI_DLTRCR_MRD_TIME3           ((uint32_t)0x00000008U)
14054 #define DSI_DLTRCR_MRD_TIME4           ((uint32_t)0x00000010U)
14055 #define DSI_DLTRCR_MRD_TIME5           ((uint32_t)0x00000020U)
14056 #define DSI_DLTRCR_MRD_TIME6           ((uint32_t)0x00000040U)
14057 #define DSI_DLTRCR_MRD_TIME7           ((uint32_t)0x00000080U)
14058 #define DSI_DLTRCR_MRD_TIME8           ((uint32_t)0x00000100U)
14059 #define DSI_DLTRCR_MRD_TIME9           ((uint32_t)0x00000200U)
14060 #define DSI_DLTRCR_MRD_TIME10          ((uint32_t)0x00000400U)
14061 #define DSI_DLTRCR_MRD_TIME11          ((uint32_t)0x00000800U)
14062 #define DSI_DLTRCR_MRD_TIME12          ((uint32_t)0x00001000U)
14063 #define DSI_DLTRCR_MRD_TIME13          ((uint32_t)0x00002000U)
14064 #define DSI_DLTRCR_MRD_TIME14          ((uint32_t)0x00004000U)
14065 
14066 /*******************  Bit definition for DSI_VSCR register  ***************/
14067 #define DSI_VSCR_EN                    ((uint32_t)0x00000001U)               /*!< Enable */
14068 #define DSI_VSCR_UR                    ((uint32_t)0x00000100U)               /*!< Update Register */
14069 
14070 /*******************  Bit definition for DSI_LCVCIDR register  ************/
14071 #define DSI_LCVCIDR_VCID               ((uint32_t)0x00000003U)               /*!< Virtual Channel ID */
14072 #define DSI_LCVCIDR_VCID0              ((uint32_t)0x00000001U)
14073 #define DSI_LCVCIDR_VCID1              ((uint32_t)0x00000002U)
14074 
14075 /*******************  Bit definition for DSI_LCCCR register  **************/
14076 #define DSI_LCCCR_COLC                 ((uint32_t)0x0000000FU)               /*!< Color Coding */
14077 #define DSI_LCCCR_COLC0                ((uint32_t)0x00000001U)
14078 #define DSI_LCCCR_COLC1                ((uint32_t)0x00000002U)
14079 #define DSI_LCCCR_COLC2                ((uint32_t)0x00000004U)
14080 #define DSI_LCCCR_COLC3                ((uint32_t)0x00000008U)
14081 
14082 #define DSI_LCCCR_LPE                  ((uint32_t)0x00000100U)               /*!< Loosely Packed Enable */
14083 
14084 /*******************  Bit definition for DSI_LPMCCR register  *************/
14085 #define DSI_LPMCCR_VLPSIZE             ((uint32_t)0x000000FFU)               /*!< VACT Largest Packet Size */
14086 #define DSI_LPMCCR_VLPSIZE0            ((uint32_t)0x00000001U)
14087 #define DSI_LPMCCR_VLPSIZE1            ((uint32_t)0x00000002U)
14088 #define DSI_LPMCCR_VLPSIZE2            ((uint32_t)0x00000004U)
14089 #define DSI_LPMCCR_VLPSIZE3            ((uint32_t)0x00000008U)
14090 #define DSI_LPMCCR_VLPSIZE4            ((uint32_t)0x00000010U)
14091 #define DSI_LPMCCR_VLPSIZE5            ((uint32_t)0x00000020U)
14092 #define DSI_LPMCCR_VLPSIZE6            ((uint32_t)0x00000040U)
14093 #define DSI_LPMCCR_VLPSIZE7            ((uint32_t)0x00000080U)
14094 
14095 #define DSI_LPMCCR_LPSIZE              ((uint32_t)0x00FF0000U)               /*!< Largest Packet Size */
14096 #define DSI_LPMCCR_LPSIZE0             ((uint32_t)0x00010000U)
14097 #define DSI_LPMCCR_LPSIZE1             ((uint32_t)0x00020000U)
14098 #define DSI_LPMCCR_LPSIZE2             ((uint32_t)0x00040000U)
14099 #define DSI_LPMCCR_LPSIZE3             ((uint32_t)0x00080000U)
14100 #define DSI_LPMCCR_LPSIZE4             ((uint32_t)0x00100000U)
14101 #define DSI_LPMCCR_LPSIZE5             ((uint32_t)0x00200000U)
14102 #define DSI_LPMCCR_LPSIZE6             ((uint32_t)0x00400000U)
14103 #define DSI_LPMCCR_LPSIZE7             ((uint32_t)0x00800000U)
14104 
14105 /*******************  Bit definition for DSI_VMCCR register  **************/
14106 #define DSI_VMCCR_VMT                  ((uint32_t)0x00000003U)               /*!< Video Mode Type */
14107 #define DSI_VMCCR_VMT0                 ((uint32_t)0x00000001U)
14108 #define DSI_VMCCR_VMT1                 ((uint32_t)0x00000002U)
14109 
14110 #define DSI_VMCCR_LPVSAE               ((uint32_t)0x00000100U)               /*!< Low-power Vertical Sync time Enable */
14111 #define DSI_VMCCR_LPVBPE               ((uint32_t)0x00000200U)               /*!< Low-power Vertical Back-porch Enable */
14112 #define DSI_VMCCR_LPVFPE               ((uint32_t)0x00000400U)               /*!< Low-power Vertical Front-porch Enable */
14113 #define DSI_VMCCR_LPVAE                ((uint32_t)0x00000800U)               /*!< Low-power Vertical Active Enable */
14114 #define DSI_VMCCR_LPHBPE               ((uint32_t)0x00001000U)               /*!< Low-power Horizontal Back-porch Enable */
14115 #define DSI_VMCCR_LPHFE                ((uint32_t)0x00002000U)               /*!< Low-power Horizontal Front-porch Enable */
14116 #define DSI_VMCCR_FBTAAE               ((uint32_t)0x00004000U)               /*!< Frame BTA Acknowledge Enable */
14117 #define DSI_VMCCR_LPCE                 ((uint32_t)0x00008000U)               /*!< Low-power Command Enable */
14118 
14119 /*******************  Bit definition for DSI_VPCCR register  **************/
14120 #define DSI_VPCCR_VPSIZE               ((uint32_t)0x00003FFFU)               /*!< Video Packet Size */
14121 #define DSI_VPCCR_VPSIZE0              ((uint32_t)0x00000001U)
14122 #define DSI_VPCCR_VPSIZE1              ((uint32_t)0x00000002U)
14123 #define DSI_VPCCR_VPSIZE2              ((uint32_t)0x00000004U)
14124 #define DSI_VPCCR_VPSIZE3              ((uint32_t)0x00000008U)
14125 #define DSI_VPCCR_VPSIZE4              ((uint32_t)0x00000010U)
14126 #define DSI_VPCCR_VPSIZE5              ((uint32_t)0x00000020U)
14127 #define DSI_VPCCR_VPSIZE6              ((uint32_t)0x00000040U)
14128 #define DSI_VPCCR_VPSIZE7              ((uint32_t)0x00000080U)
14129 #define DSI_VPCCR_VPSIZE8              ((uint32_t)0x00000100U)
14130 #define DSI_VPCCR_VPSIZE9              ((uint32_t)0x00000200U)
14131 #define DSI_VPCCR_VPSIZE10             ((uint32_t)0x00000400U)
14132 #define DSI_VPCCR_VPSIZE11             ((uint32_t)0x00000800U)
14133 #define DSI_VPCCR_VPSIZE12             ((uint32_t)0x00001000U)
14134 #define DSI_VPCCR_VPSIZE13             ((uint32_t)0x00002000U)
14135 
14136 /*******************  Bit definition for DSI_VCCCR register  **************/
14137 #define DSI_VCCCR_NUMC                 ((uint32_t)0x00001FFFU)               /*!< Number of Chunks */
14138 #define DSI_VCCCR_NUMC0                ((uint32_t)0x00000001U)
14139 #define DSI_VCCCR_NUMC1                ((uint32_t)0x00000002U)
14140 #define DSI_VCCCR_NUMC2                ((uint32_t)0x00000004U)
14141 #define DSI_VCCCR_NUMC3                ((uint32_t)0x00000008U)
14142 #define DSI_VCCCR_NUMC4                ((uint32_t)0x00000010U)
14143 #define DSI_VCCCR_NUMC5                ((uint32_t)0x00000020U)
14144 #define DSI_VCCCR_NUMC6                ((uint32_t)0x00000040U)
14145 #define DSI_VCCCR_NUMC7                ((uint32_t)0x00000080U)
14146 #define DSI_VCCCR_NUMC8                ((uint32_t)0x00000100U)
14147 #define DSI_VCCCR_NUMC9                ((uint32_t)0x00000200U)
14148 #define DSI_VCCCR_NUMC10               ((uint32_t)0x00000400U)
14149 #define DSI_VCCCR_NUMC11               ((uint32_t)0x00000800U)
14150 #define DSI_VCCCR_NUMC12               ((uint32_t)0x00001000U)
14151 
14152 /*******************  Bit definition for DSI_VNPCCR register  *************/
14153 #define DSI_VNPCCR_NPSIZE              ((uint32_t)0x00001FFFU)               /*!< Number of Chunks */
14154 #define DSI_VNPCCR_NPSIZE0             ((uint32_t)0x00000001U)
14155 #define DSI_VNPCCR_NPSIZE1             ((uint32_t)0x00000002U)
14156 #define DSI_VNPCCR_NPSIZE2             ((uint32_t)0x00000004U)
14157 #define DSI_VNPCCR_NPSIZE3             ((uint32_t)0x00000008U)
14158 #define DSI_VNPCCR_NPSIZE4             ((uint32_t)0x00000010U)
14159 #define DSI_VNPCCR_NPSIZE5             ((uint32_t)0x00000020U)
14160 #define DSI_VNPCCR_NPSIZE6             ((uint32_t)0x00000040U)
14161 #define DSI_VNPCCR_NPSIZE7             ((uint32_t)0x00000080U)
14162 #define DSI_VNPCCR_NPSIZE8             ((uint32_t)0x00000100U)
14163 #define DSI_VNPCCR_NPSIZE9             ((uint32_t)0x00000200U)
14164 #define DSI_VNPCCR_NPSIZE10            ((uint32_t)0x00000400U)
14165 #define DSI_VNPCCR_NPSIZE11            ((uint32_t)0x00000800U)
14166 #define DSI_VNPCCR_NPSIZE12            ((uint32_t)0x00001000U)
14167 
14168 /*******************  Bit definition for DSI_VHSACCR register  ************/
14169 #define DSI_VHSACCR_HSA                ((uint32_t)0x00000FFFU)               /*!< Horizontal Synchronism Active duration */
14170 #define DSI_VHSACCR_HSA0               ((uint32_t)0x00000001U)
14171 #define DSI_VHSACCR_HSA1               ((uint32_t)0x00000002U)
14172 #define DSI_VHSACCR_HSA2               ((uint32_t)0x00000004U)
14173 #define DSI_VHSACCR_HSA3               ((uint32_t)0x00000008U)
14174 #define DSI_VHSACCR_HSA4               ((uint32_t)0x00000010U)
14175 #define DSI_VHSACCR_HSA5               ((uint32_t)0x00000020U)
14176 #define DSI_VHSACCR_HSA6               ((uint32_t)0x00000040U)
14177 #define DSI_VHSACCR_HSA7               ((uint32_t)0x00000080U)
14178 #define DSI_VHSACCR_HSA8               ((uint32_t)0x00000100U)
14179 #define DSI_VHSACCR_HSA9               ((uint32_t)0x00000200U)
14180 #define DSI_VHSACCR_HSA10              ((uint32_t)0x00000400U)
14181 #define DSI_VHSACCR_HSA11              ((uint32_t)0x00000800U)
14182 
14183 /*******************  Bit definition for DSI_VHBPCCR register  ************/
14184 #define DSI_VHBPCCR_HBP                ((uint32_t)0x00000FFFU)               /*!< Horizontal Back-Porch duration */
14185 #define DSI_VHBPCCR_HBP0               ((uint32_t)0x00000001U)
14186 #define DSI_VHBPCCR_HBP1               ((uint32_t)0x00000002U)
14187 #define DSI_VHBPCCR_HBP2               ((uint32_t)0x00000004U)
14188 #define DSI_VHBPCCR_HBP3               ((uint32_t)0x00000008U)
14189 #define DSI_VHBPCCR_HBP4               ((uint32_t)0x00000010U)
14190 #define DSI_VHBPCCR_HBP5               ((uint32_t)0x00000020U)
14191 #define DSI_VHBPCCR_HBP6               ((uint32_t)0x00000040U)
14192 #define DSI_VHBPCCR_HBP7               ((uint32_t)0x00000080U)
14193 #define DSI_VHBPCCR_HBP8               ((uint32_t)0x00000100U)
14194 #define DSI_VHBPCCR_HBP9               ((uint32_t)0x00000200U)
14195 #define DSI_VHBPCCR_HBP10              ((uint32_t)0x00000400U)
14196 #define DSI_VHBPCCR_HBP11              ((uint32_t)0x00000800U)
14197 
14198 /*******************  Bit definition for DSI_VLCCR register  **************/
14199 #define DSI_VLCCR_HLINE                ((uint32_t)0x00007FFFU)               /*!< Horizontal Line duration */
14200 #define DSI_VLCCR_HLINE0               ((uint32_t)0x00000001U)
14201 #define DSI_VLCCR_HLINE1               ((uint32_t)0x00000002U)
14202 #define DSI_VLCCR_HLINE2               ((uint32_t)0x00000004U)
14203 #define DSI_VLCCR_HLINE3               ((uint32_t)0x00000008U)
14204 #define DSI_VLCCR_HLINE4               ((uint32_t)0x00000010U)
14205 #define DSI_VLCCR_HLINE5               ((uint32_t)0x00000020U)
14206 #define DSI_VLCCR_HLINE6               ((uint32_t)0x00000040U)
14207 #define DSI_VLCCR_HLINE7               ((uint32_t)0x00000080U)
14208 #define DSI_VLCCR_HLINE8               ((uint32_t)0x00000100U)
14209 #define DSI_VLCCR_HLINE9               ((uint32_t)0x00000200U)
14210 #define DSI_VLCCR_HLINE10              ((uint32_t)0x00000400U)
14211 #define DSI_VLCCR_HLINE11              ((uint32_t)0x00000800U)
14212 #define DSI_VLCCR_HLINE12              ((uint32_t)0x00001000U)
14213 #define DSI_VLCCR_HLINE13              ((uint32_t)0x00002000U)
14214 #define DSI_VLCCR_HLINE14              ((uint32_t)0x00004000U)
14215 
14216 /*******************  Bit definition for DSI_VVSACCR register  ***************/
14217 #define DSI_VVSACCR_VSA                ((uint32_t)0x000003FFU)               /*!< Vertical Synchronism Active duration */
14218 #define DSI_VVSACCR_VSA0               ((uint32_t)0x00000001U)
14219 #define DSI_VVSACCR_VSA1               ((uint32_t)0x00000002U)
14220 #define DSI_VVSACCR_VSA2               ((uint32_t)0x00000004U)
14221 #define DSI_VVSACCR_VSA3               ((uint32_t)0x00000008U)
14222 #define DSI_VVSACCR_VSA4               ((uint32_t)0x00000010U)
14223 #define DSI_VVSACCR_VSA5               ((uint32_t)0x00000020U)
14224 #define DSI_VVSACCR_VSA6               ((uint32_t)0x00000040U)
14225 #define DSI_VVSACCR_VSA7               ((uint32_t)0x00000080U)
14226 #define DSI_VVSACCR_VSA8               ((uint32_t)0x00000100U)
14227 #define DSI_VVSACCR_VSA9               ((uint32_t)0x00000200U)
14228 
14229 /*******************  Bit definition for DSI_VVBPCCR register  ************/
14230 #define DSI_VVBPCCR_VBP                ((uint32_t)0x000003FFU)               /*!< Vertical Back-Porch duration */
14231 #define DSI_VVBPCCR_VBP0               ((uint32_t)0x00000001U)
14232 #define DSI_VVBPCCR_VBP1               ((uint32_t)0x00000002U)
14233 #define DSI_VVBPCCR_VBP2               ((uint32_t)0x00000004U)
14234 #define DSI_VVBPCCR_VBP3               ((uint32_t)0x00000008U)
14235 #define DSI_VVBPCCR_VBP4               ((uint32_t)0x00000010U)
14236 #define DSI_VVBPCCR_VBP5               ((uint32_t)0x00000020U)
14237 #define DSI_VVBPCCR_VBP6               ((uint32_t)0x00000040U)
14238 #define DSI_VVBPCCR_VBP7               ((uint32_t)0x00000080U)
14239 #define DSI_VVBPCCR_VBP8               ((uint32_t)0x00000100U)
14240 #define DSI_VVBPCCR_VBP9               ((uint32_t)0x00000200U)
14241 
14242 /*******************  Bit definition for DSI_VVFPCCR register  ************/
14243 #define DSI_VVFPCCR_VFP                ((uint32_t)0x000003FFU)               /*!< Vertical Front-Porch duration */
14244 #define DSI_VVFPCCR_VFP0               ((uint32_t)0x00000001U)
14245 #define DSI_VVFPCCR_VFP1               ((uint32_t)0x00000002U)
14246 #define DSI_VVFPCCR_VFP2               ((uint32_t)0x00000004U)
14247 #define DSI_VVFPCCR_VFP3               ((uint32_t)0x00000008U)
14248 #define DSI_VVFPCCR_VFP4               ((uint32_t)0x00000010U)
14249 #define DSI_VVFPCCR_VFP5               ((uint32_t)0x00000020U)
14250 #define DSI_VVFPCCR_VFP6               ((uint32_t)0x00000040U)
14251 #define DSI_VVFPCCR_VFP7               ((uint32_t)0x00000080U)
14252 #define DSI_VVFPCCR_VFP8               ((uint32_t)0x00000100U)
14253 #define DSI_VVFPCCR_VFP9               ((uint32_t)0x00000200U)
14254 
14255 /*******************  Bit definition for DSI_VVACCR register  *************/
14256 #define DSI_VVACCR_VA                  ((uint32_t)0x00003FFFU)               /*!< Vertical Active duration */
14257 #define DSI_VVACCR_VA0                 ((uint32_t)0x00000001U)
14258 #define DSI_VVACCR_VA1                 ((uint32_t)0x00000002U)
14259 #define DSI_VVACCR_VA2                 ((uint32_t)0x00000004U)
14260 #define DSI_VVACCR_VA3                 ((uint32_t)0x00000008U)
14261 #define DSI_VVACCR_VA4                 ((uint32_t)0x00000010U)
14262 #define DSI_VVACCR_VA5                 ((uint32_t)0x00000020U)
14263 #define DSI_VVACCR_VA6                 ((uint32_t)0x00000040U)
14264 #define DSI_VVACCR_VA7                 ((uint32_t)0x00000080U)
14265 #define DSI_VVACCR_VA8                 ((uint32_t)0x00000100U)
14266 #define DSI_VVACCR_VA9                 ((uint32_t)0x00000200U)
14267 #define DSI_VVACCR_VA10                ((uint32_t)0x00000400U)
14268 #define DSI_VVACCR_VA11                ((uint32_t)0x00000800U)
14269 #define DSI_VVACCR_VA12                ((uint32_t)0x00001000U)
14270 #define DSI_VVACCR_VA13                ((uint32_t)0x00002000U)
14271 
14272 /*******************  Bit definition for DSI_TDCCR register  **************/
14273 #define DSI_TDCCR_3DM                  ((uint32_t)0x00000003U)               /*!< 3D Mode */
14274 #define DSI_TDCCR_3DM0                 ((uint32_t)0x00000001U)
14275 #define DSI_TDCCR_3DM1                 ((uint32_t)0x00000002U)
14276 
14277 #define DSI_TDCCR_3DF                  ((uint32_t)0x0000000CU)               /*!< 3D Format */
14278 #define DSI_TDCCR_3DF0                 ((uint32_t)0x00000004U)
14279 #define DSI_TDCCR_3DF1                 ((uint32_t)0x00000008U)
14280 
14281 #define DSI_TDCCR_SVS                  ((uint32_t)0x00000010U)               /*!< Second VSYNC */
14282 #define DSI_TDCCR_RF                   ((uint32_t)0x00000020U)               /*!< Right First */
14283 #define DSI_TDCCR_S3DC                 ((uint32_t)0x00010000U)               /*!< Send 3D Control */
14284 
14285 /*******************  Bit definition for DSI_WCFGR register  ***************/
14286 #define DSI_WCFGR_DSIM                 ((uint32_t)0x00000001U)               /*!< DSI Mode */
14287 
14288 #define DSI_WCFGR_COLMUX               ((uint32_t)0x0000000EU)               /*!< Color Multiplexing */
14289 #define DSI_WCFGR_COLMUX0              ((uint32_t)0x00000002U)
14290 #define DSI_WCFGR_COLMUX1              ((uint32_t)0x00000004U)
14291 #define DSI_WCFGR_COLMUX2              ((uint32_t)0x00000008U)
14292 
14293 #define DSI_WCFGR_TESRC                ((uint32_t)0x00000010U)               /*!< Tearing Effect Source */
14294 #define DSI_WCFGR_TEPOL                ((uint32_t)0x00000020U)               /*!< Tearing Effect Polarity */
14295 #define DSI_WCFGR_AR                   ((uint32_t)0x00000040U)               /*!< Automatic Refresh */
14296 #define DSI_WCFGR_VSPOL                ((uint32_t)0x00000080U)               /*!< VSync Polarity */
14297 
14298 /*******************  Bit definition for DSI_WCR register  *****************/
14299 #define DSI_WCR_COLM                   ((uint32_t)0x00000001U)               /*!< Color Mode */
14300 #define DSI_WCR_SHTDN                  ((uint32_t)0x00000002U)               /*!< Shutdown */
14301 #define DSI_WCR_LTDCEN                 ((uint32_t)0x00000004U)               /*!< LTDC Enable */
14302 #define DSI_WCR_DSIEN                  ((uint32_t)0x00000008U)               /*!< DSI Enable */
14303 
14304 /*******************  Bit definition for DSI_WIER register  ****************/
14305 #define DSI_WIER_TEIE                  ((uint32_t)0x00000001U)               /*!< Tearing Effect Interrupt Enable */
14306 #define DSI_WIER_ERIE                  ((uint32_t)0x00000002U)               /*!< End of Refresh Interrupt Enable */
14307 #define DSI_WIER_PLLLIE                ((uint32_t)0x00000200U)               /*!< PLL Lock Interrupt Enable */
14308 #define DSI_WIER_PLLUIE                ((uint32_t)0x00000400U)               /*!< PLL Unlock Interrupt Enable */
14309 #define DSI_WIER_RRIE                  ((uint32_t)0x00002000U)               /*!< Regulator Ready Interrupt Enable */
14310 
14311 /*******************  Bit definition for DSI_WISR register  ****************/
14312 #define DSI_WISR_TEIF                  ((uint32_t)0x00000001U)               /*!< Tearing Effect Interrupt Flag */
14313 #define DSI_WISR_ERIF                  ((uint32_t)0x00000002U)               /*!< End of Refresh Interrupt Flag */
14314 #define DSI_WISR_BUSY                  ((uint32_t)0x00000004U)               /*!< Busy Flag */
14315 #define DSI_WISR_PLLLS                 ((uint32_t)0x00000100U)               /*!< PLL Lock Status */
14316 #define DSI_WISR_PLLLIF                ((uint32_t)0x00000200U)               /*!< PLL Lock Interrupt Flag */
14317 #define DSI_WISR_PLLUIF                ((uint32_t)0x00000400U)               /*!< PLL Unlock Interrupt Flag */
14318 #define DSI_WISR_RRS                   ((uint32_t)0x00001000U)               /*!< Regulator Ready Flag */
14319 #define DSI_WISR_RRIF                  ((uint32_t)0x00002000U)               /*!< Regulator Ready Interrupt Flag */
14320 
14321 /*******************  Bit definition for DSI_WIFCR register  ***************/
14322 #define DSI_WIFCR_CTEIF                ((uint32_t)0x00000001U)               /*!< Clear Tearing Effect Interrupt Flag */
14323 #define DSI_WIFCR_CERIF                ((uint32_t)0x00000002U)               /*!< Clear End of Refresh Interrupt Flag */
14324 #define DSI_WIFCR_CPLLLIF              ((uint32_t)0x00000200U)               /*!< Clear PLL Lock Interrupt Flag */
14325 #define DSI_WIFCR_CPLLUIF              ((uint32_t)0x00000400U)               /*!< Clear PLL Unlock Interrupt Flag */
14326 #define DSI_WIFCR_CRRIF                ((uint32_t)0x00002000U)               /*!< Clear Regulator Ready Interrupt Flag */
14327 
14328 /*******************  Bit definition for DSI_WPCR0 register  ***************/
14329 #define DSI_WPCR0_UIX4                 ((uint32_t)0x0000003FU)               /*!< Unit Interval multiplied by 4 */
14330 #define DSI_WPCR0_UIX4_0               ((uint32_t)0x00000001U)
14331 #define DSI_WPCR0_UIX4_1               ((uint32_t)0x00000002U)
14332 #define DSI_WPCR0_UIX4_2               ((uint32_t)0x00000004U)
14333 #define DSI_WPCR0_UIX4_3               ((uint32_t)0x00000008U)
14334 #define DSI_WPCR0_UIX4_4               ((uint32_t)0x00000010U)
14335 #define DSI_WPCR0_UIX4_5               ((uint32_t)0x00000020U)
14336 
14337 #define DSI_WPCR0_SWCL                 ((uint32_t)0x00000040U)               /*!< Swap pins on clock lane */
14338 #define DSI_WPCR0_SWDL0                ((uint32_t)0x00000080U)               /*!< Swap pins on data lane 1 */
14339 #define DSI_WPCR0_SWDL1                ((uint32_t)0x00000100U)               /*!< Swap pins on data lane 2 */
14340 #define DSI_WPCR0_HSICL                ((uint32_t)0x00000200U)               /*!< Invert the high-speed data signal on clock lane */
14341 #define DSI_WPCR0_HSIDL0               ((uint32_t)0x00000400U)               /*!< Invert the high-speed data signal on lane 1 */
14342 #define DSI_WPCR0_HSIDL1               ((uint32_t)0x00000800U)               /*!< Invert the high-speed data signal on lane 2 */
14343 #define DSI_WPCR0_FTXSMCL              ((uint32_t)0x00001000U)               /*!< Force clock lane in TX stop mode */
14344 #define DSI_WPCR0_FTXSMDL              ((uint32_t)0x00002000U)               /*!< Force data lanes in TX stop mode */
14345 #define DSI_WPCR0_CDOFFDL              ((uint32_t)0x00004000U)               /*!< Contention detection OFF */
14346 #define DSI_WPCR0_TDDL                 ((uint32_t)0x00010000U)               /*!< Turn Disable Data Lanes */
14347 
14348 /*******************  Bit definition for DSI_WPCR1 register  ***************/
14349 #define DSI_WPCR1_SKEWCL               ((uint32_t)0x00000003U)               /*!< Skew on Clock Lanes */
14350 #define DSI_WPCR1_SKEWCL0              ((uint32_t)0x00000001U)
14351 #define DSI_WPCR1_SKEWCL1              ((uint32_t)0x00000002U)
14352 
14353 #define DSI_WPCR1_SKEWDL               ((uint32_t)0x0000000CU)               /*!< Skew on Data Lanes */
14354 #define DSI_WPCR1_SKEWDL0              ((uint32_t)0x00000004U)
14355 #define DSI_WPCR1_SKEWDL1              ((uint32_t)0x00000008U)
14356 
14357 #define DSI_WPCR1_LPTXSRCL             ((uint32_t)0x000000C0U)               /*!< Low-Power TX Slew Rate on Clock Lanes */
14358 #define DSI_WPCR1_LPTXSRCL0            ((uint32_t)0x00000040U)
14359 #define DSI_WPCR1_LPTXSRCL1            ((uint32_t)0x00000080U)
14360 
14361 #define DSI_WPCR1_LPTXSRDL             ((uint32_t)0x00000300U)               /*!< Low-Power TX Slew Rate on Data Lanes */
14362 #define DSI_WPCR1_LPTXSRDL0            ((uint32_t)0x00000100U)
14363 #define DSI_WPCR1_LPTXSRDL1            ((uint32_t)0x00000200U)
14364 
14365 #define DSI_WPCR1_SDDCCL               ((uint32_t)0x00001000U)               /*!< SDD Control Clock Lane */
14366 #define DSI_WPCR1_SDDCDL               ((uint32_t)0x00002000U)               /*!< SDD Control Data Lanes */
14367 #define DSI_WPCR1_HSTXSRUCL            ((uint32_t)0x00010000U)               /*!< High-Speed TX Slew-Rate Up Clock Lane */
14368 #define DSI_WPCR1_HSTXSRDCL            ((uint32_t)0x00020000U)               /*!< High-Speed TX Slew-Rate Down Clock Lane */
14369 #define DSI_WPCR1_HSTXSRUDL            ((uint32_t)0x00040000U)               /*!< High-Speed TX Slew-Rate Up Data Lane */
14370 #define DSI_WPCR1_HSTXSRDDL            ((uint32_t)0x00080000U)               /*!< High-Speed TX Slew-Rate Down Data Lane */
14371 
14372 /*******************  Bit definition for DSI_WRPCR register  ***************/
14373 #define DSI_WRPCR_PLLEN                ((uint32_t)0x00000001U)               /*!< PLL Enable */
14374 
14375 #define DSI_WRPCR_PLL_NDIV             ((uint32_t)0x000001FCU)               /*!< PLL Loop Division Factor */
14376 #define DSI_WRPCR_PLL_NDIV0            ((uint32_t)0x00000004U)
14377 #define DSI_WRPCR_PLL_NDIV1            ((uint32_t)0x00000008U)
14378 #define DSI_WRPCR_PLL_NDIV2            ((uint32_t)0x00000010U)
14379 #define DSI_WRPCR_PLL_NDIV3            ((uint32_t)0x00000020U)
14380 #define DSI_WRPCR_PLL_NDIV4            ((uint32_t)0x00000040U)
14381 #define DSI_WRPCR_PLL_NDIV5            ((uint32_t)0x00000080U)
14382 #define DSI_WRPCR_PLL_NDIV6            ((uint32_t)0x00000100U)
14383 
14384 #define DSI_WRPCR_PLL_IDF              ((uint32_t)0x00007800U)               /*!< PLL Input Division Factor */
14385 #define DSI_WRPCR_PLL_IDF0             ((uint32_t)0x00000800U)
14386 #define DSI_WRPCR_PLL_IDF1             ((uint32_t)0x00001000U)
14387 #define DSI_WRPCR_PLL_IDF2             ((uint32_t)0x00002000U)
14388 #define DSI_WRPCR_PLL_IDF3             ((uint32_t)0x00004000U)
14389 
14390 #define DSI_WRPCR_PLL_ODF              ((uint32_t)0x00030000U)               /*!< PLL Output Division Factor */
14391 #define DSI_WRPCR_PLL_ODF0             ((uint32_t)0x00010000U)
14392 #define DSI_WRPCR_PLL_ODF1             ((uint32_t)0x00020000U)
14393 
14394 #define DSI_WRPCR_REGEN                ((uint32_t)0x01000000U)               /*!< Regulator Enable */
14395 
14396 #define DSI_WRPCR_BGREN                ((uint32_t)0x10000000U)               /*!< Bandgap Enable */
14397 
14398 /**********************  Bit definition for DSI_HWCFGR register  ***************/
14399 #define DSI_HWCFGR_TECHNO_Pos    (0U)
14400 #define DSI_HWCFGR_TECHNO_Msk    (0xFU << DSI_HWCFGR_TECHNO_Pos)            /*!< 0x0000000F */
14401 #define DSI_HWCFGR_TECHNO        DSI_HWCFGR_TECHNO_Msk                      /*!< Size of the payload FIFO */
14402 #define DSI_HWCFGR_FIFOSIZE_Pos  (4U)
14403 #define DSI_HWCFGR_FIFOSIZE_Msk  (0xFFFU << DSI_HWCFGR_FIFOSIZE_Pos)         /*!< 0x0000FFF0 */
14404 #define DSI_HWCFGR_FIFOSIZE      DSI_HWCFGR_FIFOSIZE_Msk                     /*!< Technology used. */
14405 
14406 
14407 /**********************  Bit definition for DSI_VERR register  *****************/
14408 #define DSI_VERR_MINREV_Pos      (0U)
14409 #define DSI_VERR_MINREV_Msk      (0xFU << DSI_VERR_MINREV_Pos)               /*!< 0x0000000F */
14410 #define DSI_VERR_MINREV          DSI_VERR_MINREV_Msk                         /*!< Minor Revision number */
14411 #define DSI_VERR_MAJREV_Pos      (4U)
14412 #define DSI_VERR_MAJREV_Msk      (0xFU << DSI_VERR_MAJREV_Pos)               /*!< 0x000000F0 */
14413 #define DSI_VERR_MAJREV          DSI_VERR_MAJREV_Msk                         /*!< Major Revision number */
14414 
14415 /**********************  Bit definition for DSI_IPIDR register  ****************/
14416 #define DSI_IPIDR_IPID_Pos       (0U)
14417 #define DSI_IPIDR_IPID_Msk       (0xFFFFFFFFU << DSI_IPIDR_IPID_Pos)         /*!< 0xFFFFFFFF */
14418 #define DSI_IPIDR_IPID           DSI_IPIDR_IPID_Msk                          /*!< IP Identification */
14419 
14420 /**********************  Bit definition for DSI_SIDR register  *****************/
14421 #define DSI_SIDR_SID_Pos         (0U)
14422 #define DSI_SIDR_SID_Msk         (0xFFFFFFFFU << DSI_SIDR_SID_Pos)           /*!< 0xFFFFFFFF */
14423 #define DSI_SIDR_SID             DSI_SIDR_SID_Msk                            /*!< IP size identification */
14424 
14425 /******************************************************************************/
14426 /*                                                                            */
14427 /*                    External Interrupt/Event Controller                     */
14428 /*                                                                            */
14429 /******************************************************************************/
14430 /*******************  Bit definition for EXTI_IMR1 register  *******************/
14431 #define EXTI_IMR1_IM0_Pos          (0U)
14432 #define EXTI_IMR1_IM0_Msk          (0x1U << EXTI_IMR1_IM0_Pos)                 /*!< 0x00000001 */
14433 #define EXTI_IMR1_IM0              EXTI_IMR1_IM0_Msk                           /*!< Interrupt Mask on line 0 */
14434 #define EXTI_IMR1_IM1_Pos          (1U)
14435 #define EXTI_IMR1_IM1_Msk          (0x1U << EXTI_IMR1_IM1_Pos)                 /*!< 0x00000002 */
14436 #define EXTI_IMR1_IM1              EXTI_IMR1_IM1_Msk                           /*!< Interrupt Mask on line 1 */
14437 #define EXTI_IMR1_IM2_Pos          (2U)
14438 #define EXTI_IMR1_IM2_Msk          (0x1U << EXTI_IMR1_IM2_Pos)                 /*!< 0x00000004 */
14439 #define EXTI_IMR1_IM2              EXTI_IMR1_IM2_Msk                           /*!< Interrupt Mask on line 2 */
14440 #define EXTI_IMR1_IM3_Pos          (3U)
14441 #define EXTI_IMR1_IM3_Msk          (0x1U << EXTI_IMR1_IM3_Pos)                 /*!< 0x00000008 */
14442 #define EXTI_IMR1_IM3              EXTI_IMR1_IM3_Msk                           /*!< Interrupt Mask on line 3 */
14443 #define EXTI_IMR1_IM4_Pos          (4U)
14444 #define EXTI_IMR1_IM4_Msk          (0x1U << EXTI_IMR1_IM4_Pos)                 /*!< 0x00000010 */
14445 #define EXTI_IMR1_IM4              EXTI_IMR1_IM4_Msk                           /*!< Interrupt Mask on line 4 */
14446 #define EXTI_IMR1_IM5_Pos          (5U)
14447 #define EXTI_IMR1_IM5_Msk          (0x1U << EXTI_IMR1_IM5_Pos)                 /*!< 0x00000020 */
14448 #define EXTI_IMR1_IM5              EXTI_IMR1_IM5_Msk                           /*!< Interrupt Mask on line 5 */
14449 #define EXTI_IMR1_IM6_Pos          (6U)
14450 #define EXTI_IMR1_IM6_Msk          (0x1U << EXTI_IMR1_IM6_Pos)                 /*!< 0x00000040 */
14451 #define EXTI_IMR1_IM6              EXTI_IMR1_IM6_Msk                           /*!< Interrupt Mask on line 6 */
14452 #define EXTI_IMR1_IM7_Pos          (7U)
14453 #define EXTI_IMR1_IM7_Msk          (0x1U << EXTI_IMR1_IM7_Pos)                 /*!< 0x00000080 */
14454 #define EXTI_IMR1_IM7              EXTI_IMR1_IM7_Msk                           /*!< Interrupt Mask on line 7 */
14455 #define EXTI_IMR1_IM8_Pos          (8U)
14456 #define EXTI_IMR1_IM8_Msk          (0x1U << EXTI_IMR1_IM8_Pos)                 /*!< 0x00000100 */
14457 #define EXTI_IMR1_IM8              EXTI_IMR1_IM8_Msk                           /*!< Interrupt Mask on line 8 */
14458 #define EXTI_IMR1_IM9_Pos          (9U)
14459 #define EXTI_IMR1_IM9_Msk          (0x1U << EXTI_IMR1_IM9_Pos)                 /*!< 0x00000200 */
14460 #define EXTI_IMR1_IM9              EXTI_IMR1_IM9_Msk                           /*!< Interrupt Mask on line 9 */
14461 #define EXTI_IMR1_IM10_Pos         (10U)
14462 #define EXTI_IMR1_IM10_Msk         (0x1U << EXTI_IMR1_IM10_Pos)                /*!< 0x00000400 */
14463 #define EXTI_IMR1_IM10             EXTI_IMR1_IM10_Msk                          /*!< Interrupt Mask on line 10 */
14464 #define EXTI_IMR1_IM11_Pos         (11U)
14465 #define EXTI_IMR1_IM11_Msk         (0x1U << EXTI_IMR1_IM11_Pos)                /*!< 0x00000800 */
14466 #define EXTI_IMR1_IM11             EXTI_IMR1_IM11_Msk                          /*!< Interrupt Mask on line 11 */
14467 #define EXTI_IMR1_IM12_Pos         (12U)
14468 #define EXTI_IMR1_IM12_Msk         (0x1U << EXTI_IMR1_IM12_Pos)                /*!< 0x00001000 */
14469 #define EXTI_IMR1_IM12             EXTI_IMR1_IM12_Msk                          /*!< Interrupt Mask on line 12 */
14470 #define EXTI_IMR1_IM13_Pos         (13U)
14471 #define EXTI_IMR1_IM13_Msk         (0x1U << EXTI_IMR1_IM13_Pos)                /*!< 0x00002000 */
14472 #define EXTI_IMR1_IM13             EXTI_IMR1_IM13_Msk                          /*!< Interrupt Mask on line 13 */
14473 #define EXTI_IMR1_IM14_Pos         (14U)
14474 #define EXTI_IMR1_IM14_Msk         (0x1U << EXTI_IMR1_IM14_Pos)                /*!< 0x00004000 */
14475 #define EXTI_IMR1_IM14             EXTI_IMR1_IM14_Msk                          /*!< Interrupt Mask on line 14 */
14476 #define EXTI_IMR1_IM15_Pos         (15U)
14477 #define EXTI_IMR1_IM15_Msk         (0x1U << EXTI_IMR1_IM15_Pos)                /*!< 0x00008000 */
14478 #define EXTI_IMR1_IM15             EXTI_IMR1_IM15_Msk                          /*!< Interrupt Mask on line 15 */
14479 #define EXTI_IMR1_IM16_Pos         (16U)
14480 #define EXTI_IMR1_IM16_Msk         (0x1U << EXTI_IMR1_IM16_Pos)                /*!< 0x00010000 */
14481 #define EXTI_IMR1_IM16             EXTI_IMR1_IM16_Msk                          /*!< Interrupt Mask on line 16 */
14482 #define EXTI_IMR1_IM17_Pos         (17U)
14483 #define EXTI_IMR1_IM17_Msk         (0x1U << EXTI_IMR1_IM17_Pos)                /*!< 0x00020000 */
14484 #define EXTI_IMR1_IM17             EXTI_IMR1_IM17_Msk                          /*!< Interrupt Mask on line 17 */
14485 #define EXTI_IMR1_IM18_Pos         (18U)
14486 #define EXTI_IMR1_IM18_Msk         (0x1U << EXTI_IMR1_IM18_Pos)                /*!< 0x00040000 */
14487 #define EXTI_IMR1_IM18             EXTI_IMR1_IM18_Msk                          /*!< Interrupt Mask on line 18 */
14488 #define EXTI_IMR1_IM19_Pos         (19U)
14489 #define EXTI_IMR1_IM19_Msk         (0x1U << EXTI_IMR1_IM19_Pos)                /*!< 0x00080000 */
14490 #define EXTI_IMR1_IM19             EXTI_IMR1_IM19_Msk                          /*!< Interrupt Mask on line 19 */
14491 #define EXTI_IMR1_IM20_Pos         (20U)
14492 #define EXTI_IMR1_IM20_Msk         (0x1U << EXTI_IMR1_IM20_Pos)                /*!< 0x00100000 */
14493 #define EXTI_IMR1_IM20             EXTI_IMR1_IM20_Msk                          /*!< Interrupt Mask on line 20 */
14494 #define EXTI_IMR1_IM21_Pos         (21U)
14495 #define EXTI_IMR1_IM21_Msk         (0x1U << EXTI_IMR1_IM21_Pos)                /*!< 0x00200000 */
14496 #define EXTI_IMR1_IM21             EXTI_IMR1_IM21_Msk                          /*!< Interrupt Mask on line 21 */
14497 #define EXTI_IMR1_IM22_Pos         (22U)
14498 #define EXTI_IMR1_IM22_Msk         (0x1U << EXTI_IMR1_IM22_Pos)                /*!< 0x00400000 */
14499 #define EXTI_IMR1_IM22             EXTI_IMR1_IM22_Msk                          /*!< Interrupt Mask on line 22 */
14500 #define EXTI_IMR1_IM23_Pos         (23U)
14501 #define EXTI_IMR1_IM23_Msk         (0x1U << EXTI_IMR1_IM23_Pos)                /*!< 0x00800000 */
14502 #define EXTI_IMR1_IM23             EXTI_IMR1_IM23_Msk                          /*!< Interrupt Mask on line 23 */
14503 #define EXTI_IMR1_IM24_Pos         (24U)
14504 #define EXTI_IMR1_IM24_Msk         (0x1U << EXTI_IMR1_IM24_Pos)                /*!< 0x01000000 */
14505 #define EXTI_IMR1_IM24             EXTI_IMR1_IM24_Msk                          /*!< Interrupt Mask on line 24 */
14506 #define EXTI_IMR1_IM25_Pos         (25U)
14507 #define EXTI_IMR1_IM25_Msk         (0x1U << EXTI_IMR1_IM25_Pos)                /*!< 0x02000000 */
14508 #define EXTI_IMR1_IM25             EXTI_IMR1_IM25_Msk                          /*!< Interrupt Mask on line 25 */
14509 #define EXTI_IMR1_IM26_Pos         (26U)
14510 #define EXTI_IMR1_IM26_Msk         (0x1U << EXTI_IMR1_IM26_Pos)                /*!< 0x04000000 */
14511 #define EXTI_IMR1_IM26             EXTI_IMR1_IM26_Msk                          /*!< Interrupt Mask on line 26 */
14512 #define EXTI_IMR1_IM27_Pos         (27U)
14513 #define EXTI_IMR1_IM27_Msk         (0x1U << EXTI_IMR1_IM27_Pos)                /*!< 0x08000000 */
14514 #define EXTI_IMR1_IM27             EXTI_IMR1_IM27_Msk                          /*!< Interrupt Mask on line 27 */
14515 #define EXTI_IMR1_IM28_Pos         (28U)
14516 #define EXTI_IMR1_IM28_Msk         (0x1U << EXTI_IMR1_IM28_Pos)                /*!< 0x10000000 */
14517 #define EXTI_IMR1_IM28             EXTI_IMR1_IM28_Msk                          /*!< Interrupt Mask on line 28 */
14518 #define EXTI_IMR1_IM29_Pos         (29U)
14519 #define EXTI_IMR1_IM29_Msk         (0x1U << EXTI_IMR1_IM29_Pos)                /*!< 0x20000000 */
14520 #define EXTI_IMR1_IM29             EXTI_IMR1_IM29_Msk                          /*!< Interrupt Mask on line 29 */
14521 #define EXTI_IMR1_IM30_Pos         (30U)
14522 #define EXTI_IMR1_IM30_Msk         (0x1U << EXTI_IMR1_IM30_Pos)                /*!< 0x40000000 */
14523 #define EXTI_IMR1_IM30             EXTI_IMR1_IM30_Msk                          /*!< Interrupt Mask on line 30 */
14524 #define EXTI_IMR1_IM31_Pos         (31U)
14525 #define EXTI_IMR1_IM31_Msk         (0x1U << EXTI_IMR1_IM31_Pos)                /*!< 0x80000000 */
14526 #define EXTI_IMR1_IM31             EXTI_IMR1_IM31_Msk                          /*!< Interrupt Mask on line 31 */
14527 /*******************  Bit definition for EXTI_IMR2 register  *******************/
14528 #define EXTI_IMR2_IM32_Pos         (0U)
14529 #define EXTI_IMR2_IM32_Msk         (0x1U << EXTI_IMR2_IM32_Pos)                /*!< 0x00000001 */
14530 #define EXTI_IMR2_IM32             EXTI_IMR2_IM32_Msk                          /*!< Interrupt Mask on line 32 */
14531 #define EXTI_IMR2_IM33_Pos         (1U)
14532 #define EXTI_IMR2_IM33_Msk         (0x1U << EXTI_IMR2_IM33_Pos)                /*!< 0x00000002 */
14533 #define EXTI_IMR2_IM33             EXTI_IMR2_IM33_Msk                          /*!< Interrupt Mask on line 33 */
14534 #define EXTI_IMR2_IM34_Pos         (2U)
14535 #define EXTI_IMR2_IM34_Msk         (0x1U << EXTI_IMR2_IM34_Pos)                /*!< 0x00000004 */
14536 #define EXTI_IMR2_IM34             EXTI_IMR2_IM34_Msk                          /*!< Interrupt Mask on line 34 */
14537 #define EXTI_IMR2_IM35_Pos         (3U)
14538 #define EXTI_IMR2_IM35_Msk         (0x1U << EXTI_IMR2_IM35_Pos)                /*!< 0x00000008 */
14539 #define EXTI_IMR2_IM35             EXTI_IMR2_IM35_Msk                          /*!< Interrupt Mask on line 35 */
14540 #define EXTI_IMR2_IM36_Pos         (4U)
14541 #define EXTI_IMR2_IM36_Msk         (0x1U << EXTI_IMR2_IM36_Pos)                /*!< 0x00000010 */
14542 #define EXTI_IMR2_IM36             EXTI_IMR2_IM36_Msk                          /*!< Interrupt Mask on line 36 */
14543 #define EXTI_IMR2_IM37_Pos         (5U)
14544 #define EXTI_IMR2_IM37_Msk         (0x1U << EXTI_IMR2_IM37_Pos)                /*!< 0x00000020 */
14545 #define EXTI_IMR2_IM37             EXTI_IMR2_IM37_Msk                          /*!< Interrupt Mask on line 37 */
14546 #define EXTI_IMR2_IM38_Pos         (6U)
14547 #define EXTI_IMR2_IM38_Msk         (0x1U << EXTI_IMR2_IM38_Pos)                /*!< 0x00000040 */
14548 #define EXTI_IMR2_IM38             EXTI_IMR2_IM38_Msk                          /*!< Interrupt Mask on line 38 */
14549 #define EXTI_IMR2_IM39_Pos         (7U)
14550 #define EXTI_IMR2_IM39_Msk         (0x1U << EXTI_IMR2_IM39_Pos)                /*!< 0x00000080 */
14551 #define EXTI_IMR2_IM39             EXTI_IMR2_IM39_Msk                          /*!< Interrupt Mask on line 39 */
14552 #define EXTI_IMR2_IM40_Pos         (8U)
14553 #define EXTI_IMR2_IM40_Msk         (0x1U << EXTI_IMR2_IM40_Pos)                /*!< 0x00000100 */
14554 #define EXTI_IMR2_IM40             EXTI_IMR2_IM40_Msk                          /*!< Interrupt Mask on line 40 */
14555 #define EXTI_IMR2_IM41_Pos         (9U)
14556 #define EXTI_IMR2_IM41_Msk         (0x1U << EXTI_IMR2_IM41_Pos)                /*!< 0x00000200 */
14557 #define EXTI_IMR2_IM41             EXTI_IMR2_IM41_Msk                          /*!< Interrupt Mask on line 41 */
14558 #define EXTI_IMR2_IM42_Pos         (10U)
14559 #define EXTI_IMR2_IM42_Msk         (0x1U << EXTI_IMR2_IM42_Pos)                /*!< 0x00000400 */
14560 #define EXTI_IMR2_IM42             EXTI_IMR2_IM42_Msk                          /*!< Interrupt Mask on line 42 */
14561 #define EXTI_IMR2_IM43_Pos         (11U)
14562 #define EXTI_IMR2_IM43_Msk         (0x1U << EXTI_IMR2_IM43_Pos)                /*!< 0x00000800 */
14563 #define EXTI_IMR2_IM43             EXTI_IMR2_IM43_Msk                          /*!< Interrupt Mask on line 43 */
14564 #define EXTI_IMR2_IM44_Pos         (12U)
14565 #define EXTI_IMR2_IM44_Msk         (0x1U << EXTI_IMR2_IM44_Pos)                /*!< 0x00001000 */
14566 #define EXTI_IMR2_IM44             EXTI_IMR2_IM44_Msk                          /*!< Interrupt Mask on line 44 */
14567 #define EXTI_IMR2_IM45_Pos         (13U)
14568 #define EXTI_IMR2_IM45_Msk         (0x1U << EXTI_IMR2_IM45_Pos)                /*!< 0x00002000 */
14569 #define EXTI_IMR2_IM45             EXTI_IMR2_IM45_Msk                          /*!< Interrupt Mask on line 45 */
14570 #define EXTI_IMR2_IM46_Pos         (14U)
14571 #define EXTI_IMR2_IM46_Msk         (0x1U << EXTI_IMR2_IM46_Pos)                /*!< 0x00004000 */
14572 #define EXTI_IMR2_IM46             EXTI_IMR2_IM46_Msk                          /*!< Interrupt Mask on line 46 */
14573 #define EXTI_IMR2_IM47_Pos         (15U)
14574 #define EXTI_IMR2_IM47_Msk         (0x1U << EXTI_IMR2_IM47_Pos)                /*!< 0x00008000 */
14575 #define EXTI_IMR2_IM47             EXTI_IMR2_IM47_Msk                          /*!< Interrupt Mask on line 47 */
14576 #define EXTI_IMR2_IM48_Pos         (16U)
14577 #define EXTI_IMR2_IM48_Msk         (0x1U << EXTI_IMR2_IM48_Pos)                /*!< 0x00010000 */
14578 #define EXTI_IMR2_IM48             EXTI_IMR2_IM48_Msk                          /*!< Interrupt Mask on line 48 */
14579 #define EXTI_IMR2_IM49_Pos         (17U)
14580 #define EXTI_IMR2_IM49_Msk         (0x1U << EXTI_IMR2_IM49_Pos)                /*!< 0x00020000 */
14581 #define EXTI_IMR2_IM49             EXTI_IMR2_IM49_Msk                          /*!< Interrupt Mask on line 49 */
14582 #define EXTI_IMR2_IM50_Pos         (18U)
14583 #define EXTI_IMR2_IM50_Msk         (0x1U << EXTI_IMR2_IM50_Pos)                /*!< 0x00040000 */
14584 #define EXTI_IMR2_IM50             EXTI_IMR2_IM50_Msk                          /*!< Interrupt Mask on line 50 */
14585 #define EXTI_IMR2_IM51_Pos         (19U)
14586 #define EXTI_IMR2_IM51_Msk         (0x1U << EXTI_IMR2_IM51_Pos)                /*!< 0x00080000 */
14587 #define EXTI_IMR2_IM51             EXTI_IMR2_IM51_Msk                          /*!< Interrupt Mask on line 51 */
14588 #define EXTI_IMR2_IM52_Pos         (20U)
14589 #define EXTI_IMR2_IM52_Msk         (0x1U << EXTI_IMR2_IM52_Pos)                /*!< 0x00100000 */
14590 #define EXTI_IMR2_IM52             EXTI_IMR2_IM52_Msk                          /*!< Interrupt Mask on line 52 */
14591 #define EXTI_IMR2_IM53_Pos         (21U)
14592 #define EXTI_IMR2_IM53_Msk         (0x1U << EXTI_IMR2_IM53_Pos)                /*!< 0x00200000 */
14593 #define EXTI_IMR2_IM53             EXTI_IMR2_IM53_Msk                          /*!< Interrupt Mask on line 53 */
14594 #define EXTI_IMR2_IM54_Pos         (22U)
14595 #define EXTI_IMR2_IM54_Msk         (0x1U << EXTI_IMR2_IM54_Pos)                /*!< 0x00400000 */
14596 #define EXTI_IMR2_IM54             EXTI_IMR2_IM54_Msk                          /*!< Interrupt Mask on line 54 */
14597 #define EXTI_IMR2_IM55_Pos         (23U)
14598 #define EXTI_IMR2_IM55_Msk         (0x1U << EXTI_IMR2_IM55_Pos)                /*!< 0x00800000 */
14599 #define EXTI_IMR2_IM55             EXTI_IMR2_IM55_Msk                          /*!< Interrupt Mask on line 55 */
14600 #define EXTI_IMR2_IM56_Pos         (24U)
14601 #define EXTI_IMR2_IM56_Msk         (0x1U << EXTI_IMR2_IM56_Pos)                /*!< 0x01000000 */
14602 #define EXTI_IMR2_IM56             EXTI_IMR2_IM56_Msk                          /*!< Interrupt Mask on line 56 */
14603 #define EXTI_IMR2_IM57_Pos         (25U)
14604 #define EXTI_IMR2_IM57_Msk         (0x1U << EXTI_IMR2_IM57_Pos)                /*!< 0x02000000 */
14605 #define EXTI_IMR2_IM57             EXTI_IMR2_IM57_Msk                          /*!< Interrupt Mask on line 57 */
14606 #define EXTI_IMR2_IM58_Pos         (26U)
14607 #define EXTI_IMR2_IM58_Msk         (0x1U << EXTI_IMR2_IM58_Pos)                /*!< 0x04000000 */
14608 #define EXTI_IMR2_IM58             EXTI_IMR2_IM58_Msk                          /*!< Interrupt Mask on line 58 */
14609 #define EXTI_IMR2_IM59_Pos         (27U)
14610 #define EXTI_IMR2_IM59_Msk         (0x1U << EXTI_IMR2_IM59_Pos)                /*!< 0x08000000 */
14611 #define EXTI_IMR2_IM59             EXTI_IMR2_IM59_Msk                          /*!< Interrupt Mask on line 59 */
14612 #define EXTI_IMR2_IM60_Pos         (28U)
14613 #define EXTI_IMR2_IM60_Msk         (0x1U << EXTI_IMR2_IM60_Pos)                /*!< 0x10000000 */
14614 #define EXTI_IMR2_IM60             EXTI_IMR2_IM60_Msk                          /*!< Interrupt Mask on line 60 */
14615 #define EXTI_IMR2_IM61_Pos         (29U)
14616 #define EXTI_IMR2_IM61_Msk         (0x1U << EXTI_IMR2_IM61_Pos)                /*!< 0x20000000 */
14617 #define EXTI_IMR2_IM61             EXTI_IMR2_IM61_Msk                          /*!< Interrupt Mask on line 61 */
14618 #define EXTI_IMR2_IM62_Pos         (30U)
14619 #define EXTI_IMR2_IM62_Msk         (0x1U << EXTI_IMR2_IM62_Pos)                /*!< 0x40000000 */
14620 #define EXTI_IMR2_IM62             EXTI_IMR2_IM62_Msk                          /*!< Interrupt Mask on line 62 */
14621 #define EXTI_IMR2_IM63_Pos         (31U)
14622 #define EXTI_IMR2_IM63_Msk         (0x1U << EXTI_IMR2_IM63_Pos)                /*!< 0x80000000 */
14623 #define EXTI_IMR2_IM63             EXTI_IMR2_IM63_Msk                          /*!< Interrupt Mask on line 63 */
14624 /*******************  Bit definition for EXTI_IMR3 register  *******************/
14625 #define EXTI_IMR3_IM64_Pos         (0U)
14626 #define EXTI_IMR3_IM64_Msk         (0x1U << EXTI_IMR3_IM64_Pos)                /*!< 0x00000001 */
14627 #define EXTI_IMR3_IM64             EXTI_IMR3_IM64_Msk                          /*!< Interrupt Mask on line 64 */
14628 #define EXTI_IMR3_IM65_Pos         (1U)
14629 #define EXTI_IMR3_IM65_Msk         (0x1U << EXTI_IMR3_IM65_Pos)                /*!< 0x00000002 */
14630 #define EXTI_IMR3_IM65             EXTI_IMR3_IM65_Msk                          /*!< Interrupt Mask on line 65 */
14631 #define EXTI_IMR3_IM66_Pos         (2U)
14632 #define EXTI_IMR3_IM66_Msk         (0x1U << EXTI_IMR3_IM66_Pos)                /*!< 0x00000004 */
14633 #define EXTI_IMR3_IM66             EXTI_IMR3_IM66_Msk                          /*!< Interrupt Mask on line 66 */
14634 #define EXTI_IMR3_IM67_Pos         (3U)
14635 #define EXTI_IMR3_IM67_Msk         (0x1U << EXTI_IMR3_IM67_Pos)                /*!< 0x00000008 */
14636 #define EXTI_IMR3_IM67             EXTI_IMR3_IM67_Msk                          /*!< Interrupt Mask on line 67 */
14637 #define EXTI_IMR3_IM68_Pos         (4U)
14638 #define EXTI_IMR3_IM68_Msk         (0x1U << EXTI_IMR3_IM68_Pos)                /*!< 0x00000010 */
14639 #define EXTI_IMR3_IM68             EXTI_IMR3_IM68_Msk                          /*!< Interrupt Mask on line 68 */
14640 #define EXTI_IMR3_IM69_Pos         (5U)
14641 #define EXTI_IMR3_IM69_Msk         (0x1U << EXTI_IMR3_IM69_Pos)                /*!< 0x00000020 */
14642 #define EXTI_IMR3_IM69             EXTI_IMR3_IM69_Msk                          /*!< Interrupt Mask on line 69 */
14643 #define EXTI_IMR3_IM70_Pos         (6U)
14644 #define EXTI_IMR3_IM70_Msk         (0x1U << EXTI_IMR3_IM70_Pos)                /*!< 0x00000040 */
14645 #define EXTI_IMR3_IM70             EXTI_IMR3_IM70_Msk                          /*!< Interrupt Mask on line 70 */
14646 #define EXTI_IMR3_IM71_Pos         (7U)
14647 #define EXTI_IMR3_IM71_Msk         (0x1U << EXTI_IMR3_IM71_Pos)                /*!< 0x00000080 */
14648 #define EXTI_IMR3_IM71             EXTI_IMR3_IM71_Msk                          /*!< Interrupt Mask on line 71 */
14649 #define EXTI_IMR3_IM72_Pos         (8U)
14650 #define EXTI_IMR3_IM72_Msk         (0x1U << EXTI_IMR3_IM72_Pos)                /*!< 0x00000100 */
14651 #define EXTI_IMR3_IM72             EXTI_IMR3_IM72_Msk                          /*!< Interrupt Mask on line 72 */
14652 #define EXTI_IMR3_IM73_Pos         (9U)
14653 #define EXTI_IMR3_IM73_Msk         (0x1U << EXTI_IMR3_IM73_Pos)                /*!< 0x00000200 */
14654 #define EXTI_IMR3_IM73             EXTI_IMR3_IM73_Msk                          /*!< Interrupt Mask on line 73 */
14655 #define EXTI_IMR3_IM74_Pos         (10U)
14656 #define EXTI_IMR3_IM74_Msk         (0x1U << EXTI_IMR3_IM74_Pos)                /*!< 0x00000400 */
14657 #define EXTI_IMR3_IM74             EXTI_IMR3_IM74_Msk                          /*!< Interrupt Mask on line 74 */
14658 #define EXTI_IMR3_IM75_Pos         (11U)
14659 #define EXTI_IMR3_IM75_Msk         (0x1U << EXTI_IMR3_IM75_Pos)                /*!< 0x00000800 */
14660 #define EXTI_IMR3_IM75             EXTI_IMR3_IM75_Msk                          /*!< Interrupt Mask on line 75 */
14661 #define EXTI_IMR3_IM76_Pos         (12U)
14662 #define EXTI_IMR3_IM76_Msk         (0x1U << EXTI_IMR3_IM76_Pos)                /*!< 0x00001000 */
14663 #define EXTI_IMR3_IM76             EXTI_IMR3_IM76_Msk                          /*!< Interrupt Mask on line 76 */
14664 #define EXTI_IMR3_IM77_Pos         (13U)
14665 #define EXTI_IMR3_IM77_Msk         (0x1U << EXTI_IMR3_IM77_Pos)                /*!< 0x00002000 */
14666 #define EXTI_IMR3_IM77             EXTI_IMR3_IM77_Msk                          /*!< Interrupt Mask on line 77 */
14667 #define EXTI_IMR3_IM78_Pos         (14U)
14668 #define EXTI_IMR3_IM78_Msk         (0x1U << EXTI_IMR3_IM78_Pos)                /*!< 0x00004000 */
14669 #define EXTI_IMR3_IM78             EXTI_IMR3_IM78_Msk                          /*!< Interrupt Mask on line 78 */
14670 #define EXTI_IMR3_IM79_Pos         (15U)
14671 #define EXTI_IMR3_IM79_Msk         (0x1U << EXTI_IMR3_IM79_Pos)                /*!< 0x00008000 */
14672 #define EXTI_IMR3_IM79             EXTI_IMR3_IM79_Msk                          /*!< Interrupt Mask on line 79 */
14673 #define EXTI_IMR3_IM80_Pos         (16U)
14674 #define EXTI_IMR3_IM80_Msk         (0x1U << EXTI_IMR3_IM80_Pos)                /*!< 0x00010000 */
14675 #define EXTI_IMR3_IM80             EXTI_IMR3_IM80_Msk                          /*!< Interrupt Mask on line 80 */
14676 #define EXTI_IMR3_IM81_Pos         (17U)
14677 #define EXTI_IMR3_IM81_Msk         (0x1U << EXTI_IMR3_IM81_Pos)                /*!< 0x00020000 */
14678 #define EXTI_IMR3_IM81             EXTI_IMR3_IM81_Msk                          /*!< Interrupt Mask on line 81 */
14679 #define EXTI_IMR3_IM82_Pos         (18U)
14680 #define EXTI_IMR3_IM82_Msk         (0x1U << EXTI_IMR3_IM82_Pos)                /*!< 0x00040000 */
14681 #define EXTI_IMR3_IM82             EXTI_IMR3_IM82_Msk                          /*!< Interrupt Mask on line 82 */
14682 #define EXTI_IMR3_IM84_Pos         (20U)
14683 #define EXTI_IMR3_IM84_Msk         (0x1U << EXTI_IMR3_IM84_Pos)                /*!< 0x00100000 */
14684 #define EXTI_IMR3_IM84             EXTI_IMR3_IM84_Msk                          /*!< Interrupt Mask on line 84 */
14685 #define EXTI_IMR3_IM85_Pos         (21U)
14686 #define EXTI_IMR3_IM85_Msk         (0x1U << EXTI_IMR3_IM85_Pos)                /*!< 0x00200000 */
14687 #define EXTI_IMR3_IM85             EXTI_IMR3_IM85_Msk                          /*!< Interrupt Mask on line 85 */
14688 #define EXTI_IMR3_IM86_Pos         (22U)
14689 #define EXTI_IMR3_IM86_Msk         (0x1U << EXTI_IMR3_IM86_Pos)                /*!< 0x00400000 */
14690 #define EXTI_IMR3_IM86             EXTI_IMR3_IM86_Msk                          /*!< Interrupt Mask on line 86 */
14691 #define EXTI_IMR3_IM87_Pos         (23U)
14692 #define EXTI_IMR3_IM87_Msk         (0x1U << EXTI_IMR3_IM87_Pos)                /*!< 0x00800000 */
14693 #define EXTI_IMR3_IM87             EXTI_IMR3_IM87_Msk                          /*!< Interrupt Mask on line 87 */
14694 #define EXTI_IMR3_IM88_Pos         (24U)
14695 #define EXTI_IMR3_IM88_Msk         (0x1U << EXTI_IMR3_IM88_Pos)                /*!< 0x01000000 */
14696 #define EXTI_IMR3_IM88             EXTI_IMR3_IM88_Msk                          /*!< Interrupt Mask on line 88 */
14697 /*******************  Bit definition for EXTI_EMR1 register  *******************/
14698 #define EXTI_EMR1_EM0_Pos          (0U)
14699 #define EXTI_EMR1_EM0_Msk          (0x1U << EXTI_EMR1_EM0_Pos)                 /*!< 0x00000001 */
14700 #define EXTI_EMR1_EM0              EXTI_EMR1_EM0_Msk                           /*!< Event Mask on line 0 */
14701 #define EXTI_EMR1_EM1_Pos          (1U)
14702 #define EXTI_EMR1_EM1_Msk          (0x1U << EXTI_EMR1_EM1_Pos)                 /*!< 0x00000002 */
14703 #define EXTI_EMR1_EM1              EXTI_EMR1_EM1_Msk                           /*!< Event Mask on line 1 */
14704 #define EXTI_EMR1_EM2_Pos          (2U)
14705 #define EXTI_EMR1_EM2_Msk          (0x1U << EXTI_EMR1_EM2_Pos)                 /*!< 0x00000004 */
14706 #define EXTI_EMR1_EM2              EXTI_EMR1_EM2_Msk                           /*!< Event Mask on line 2 */
14707 #define EXTI_EMR1_EM3_Pos          (3U)
14708 #define EXTI_EMR1_EM3_Msk          (0x1U << EXTI_EMR1_EM3_Pos)                 /*!< 0x00000008 */
14709 #define EXTI_EMR1_EM3              EXTI_EMR1_EM3_Msk                           /*!< Event Mask on line 3 */
14710 #define EXTI_EMR1_EM4_Pos          (4U)
14711 #define EXTI_EMR1_EM4_Msk          (0x1U << EXTI_EMR1_EM4_Pos)                 /*!< 0x00000010 */
14712 #define EXTI_EMR1_EM4              EXTI_EMR1_EM4_Msk                           /*!< Event Mask on line 4 */
14713 #define EXTI_EMR1_EM5_Pos          (5U)
14714 #define EXTI_EMR1_EM5_Msk          (0x1U << EXTI_EMR1_EM5_Pos)                 /*!< 0x00000020 */
14715 #define EXTI_EMR1_EM5              EXTI_EMR1_EM5_Msk                           /*!< Event Mask on line 5 */
14716 #define EXTI_EMR1_EM6_Pos          (6U)
14717 #define EXTI_EMR1_EM6_Msk          (0x1U << EXTI_EMR1_EM6_Pos)                 /*!< 0x00000040 */
14718 #define EXTI_EMR1_EM6              EXTI_EMR1_EM6_Msk                           /*!< Event Mask on line 6 */
14719 #define EXTI_EMR1_EM7_Pos          (7U)
14720 #define EXTI_EMR1_EM7_Msk          (0x1U << EXTI_EMR1_EM7_Pos)                 /*!< 0x00000080 */
14721 #define EXTI_EMR1_EM7              EXTI_EMR1_EM7_Msk                           /*!< Event Mask on line 7 */
14722 #define EXTI_EMR1_EM8_Pos          (8U)
14723 #define EXTI_EMR1_EM8_Msk          (0x1U << EXTI_EMR1_EM8_Pos)                 /*!< 0x00000100 */
14724 #define EXTI_EMR1_EM8              EXTI_EMR1_EM8_Msk                           /*!< Event Mask on line 8 */
14725 #define EXTI_EMR1_EM9_Pos          (9U)
14726 #define EXTI_EMR1_EM9_Msk          (0x1U << EXTI_EMR1_EM9_Pos)                 /*!< 0x00000200 */
14727 #define EXTI_EMR1_EM9              EXTI_EMR1_EM9_Msk                           /*!< Event Mask on line 9 */
14728 #define EXTI_EMR1_EM10_Pos         (10U)
14729 #define EXTI_EMR1_EM10_Msk         (0x1U << EXTI_EMR1_EM10_Pos)                /*!< 0x00000400 */
14730 #define EXTI_EMR1_EM10             EXTI_EMR1_EM10_Msk                          /*!< Event Mask on line 10 */
14731 #define EXTI_EMR1_EM11_Pos         (11U)
14732 #define EXTI_EMR1_EM11_Msk         (0x1U << EXTI_EMR1_EM11_Pos)                /*!< 0x00000800 */
14733 #define EXTI_EMR1_EM11             EXTI_EMR1_EM11_Msk                          /*!< Event Mask on line 11 */
14734 #define EXTI_EMR1_EM12_Pos         (12U)
14735 #define EXTI_EMR1_EM12_Msk         (0x1U << EXTI_EMR1_EM12_Pos)                /*!< 0x00001000 */
14736 #define EXTI_EMR1_EM12             EXTI_EMR1_EM12_Msk                          /*!< Event Mask on line 12 */
14737 #define EXTI_EMR1_EM13_Pos         (13U)
14738 #define EXTI_EMR1_EM13_Msk         (0x1U << EXTI_EMR1_EM13_Pos)                /*!< 0x00002000 */
14739 #define EXTI_EMR1_EM13             EXTI_EMR1_EM13_Msk                          /*!< Event Mask on line 13 */
14740 #define EXTI_EMR1_EM14_Pos         (14U)
14741 #define EXTI_EMR1_EM14_Msk         (0x1U << EXTI_EMR1_EM14_Pos)                /*!< 0x00004000 */
14742 #define EXTI_EMR1_EM14             EXTI_EMR1_EM14_Msk                          /*!< Event Mask on line 14 */
14743 #define EXTI_EMR1_EM15_Pos         (15U)
14744 #define EXTI_EMR1_EM15_Msk         (0x1U << EXTI_EMR1_EM15_Pos)                /*!< 0x00008000 */
14745 #define EXTI_EMR1_EM15             EXTI_EMR1_EM15_Msk                          /*!< Event Mask on line 15 */
14746 #define EXTI_EMR1_EM16_Pos         (16U)
14747 #define EXTI_EMR1_EM16_Msk         (0x1U << EXTI_EMR1_EM16_Pos)                /*!< 0x00010000 */
14748 #define EXTI_EMR1_EM16             EXTI_EMR1_EM16_Msk                          /*!< Event Mask on line 16 */
14749 #define EXTI_EMR1_EM17_Pos         (17U)
14750 #define EXTI_EMR1_EM17_Msk         (0x1U << EXTI_EMR1_EM17_Pos)                /*!< 0x00020000 */
14751 #define EXTI_EMR1_EM17             EXTI_EMR1_EM17_Msk                          /*!< Event Mask on line 17 */
14752 #define EXTI_EMR1_EM18_Pos         (18U)
14753 #define EXTI_EMR1_EM18_Msk         (0x1U << EXTI_EMR1_EM18_Pos)                /*!< 0x00040000 */
14754 #define EXTI_EMR1_EM18             EXTI_EMR1_EM18_Msk                          /*!< Event Mask on line 18 */
14755 #define EXTI_EMR1_EM20_Pos         (20U)
14756 #define EXTI_EMR1_EM20_Msk         (0x1U << EXTI_EMR1_EM20_Pos)                /*!< 0x00100000 */
14757 #define EXTI_EMR1_EM20             EXTI_EMR1_EM20_Msk                          /*!< Event Mask on line 20 */
14758 #define EXTI_EMR1_EM21_Pos         (21U)
14759 #define EXTI_EMR1_EM21_Msk         (0x1U << EXTI_EMR1_EM21_Pos)                /*!< 0x00200000 */
14760 #define EXTI_EMR1_EM21             EXTI_EMR1_EM21_Msk                          /*!< Event Mask on line 21 */
14761 #define EXTI_EMR1_EM22_Pos         (22U)
14762 #define EXTI_EMR1_EM22_Msk         (0x1U << EXTI_EMR1_EM22_Pos)                /*!< 0x00400000 */
14763 #define EXTI_EMR1_EM22             EXTI_EMR1_EM22_Msk                          /*!< Event Mask on line 22 */
14764 #define EXTI_EMR1_EM23_Pos         (23U)
14765 #define EXTI_EMR1_EM23_Msk         (0x1U << EXTI_EMR1_EM23_Pos)                /*!< 0x00800000 */
14766 #define EXTI_EMR1_EM23             EXTI_EMR1_EM23_Msk                          /*!< Event Mask on line 23 */
14767 #define EXTI_EMR1_EM24_Pos         (24U)
14768 #define EXTI_EMR1_EM24_Msk         (0x1U << EXTI_EMR1_EM24_Pos)                /*!< 0x01000000 */
14769 #define EXTI_EMR1_EM24             EXTI_EMR1_EM24_Msk                          /*!< Event Mask on line 24 */
14770 #define EXTI_EMR1_EM25_Pos         (25U)
14771 #define EXTI_EMR1_EM25_Msk         (0x1U << EXTI_EMR1_EM25_Pos)                /*!< 0x02000000 */
14772 #define EXTI_EMR1_EM25             EXTI_EMR1_EM25_Msk                          /*!< Event Mask on line 25 */
14773 #define EXTI_EMR1_EM26_Pos         (26U)
14774 #define EXTI_EMR1_EM26_Msk         (0x1U << EXTI_EMR1_EM26_Pos)                /*!< 0x04000000 */
14775 #define EXTI_EMR1_EM26             EXTI_EMR1_EM26_Msk                          /*!< Event Mask on line 26 */
14776 #define EXTI_EMR1_EM27_Pos         (27U)
14777 #define EXTI_EMR1_EM27_Msk         (0x1U << EXTI_EMR1_EM27_Pos)                /*!< 0x08000000 */
14778 #define EXTI_EMR1_EM27             EXTI_EMR1_EM27_Msk                          /*!< Event Mask on line 27 */
14779 #define EXTI_EMR1_EM28_Pos         (28U)
14780 #define EXTI_EMR1_EM28_Msk         (0x1U << EXTI_EMR1_EM28_Pos)                /*!< 0x10000000 */
14781 #define EXTI_EMR1_EM28             EXTI_EMR1_EM28_Msk                          /*!< Event Mask on line 28 */
14782 #define EXTI_EMR1_EM29_Pos         (29U)
14783 #define EXTI_EMR1_EM29_Msk         (0x1U << EXTI_EMR1_EM29_Pos)                /*!< 0x20000000 */
14784 #define EXTI_EMR1_EM29             EXTI_EMR1_EM29_Msk                          /*!< Event Mask on line 29 */
14785 #define EXTI_EMR1_EM30_Pos         (30U)
14786 #define EXTI_EMR1_EM30_Msk         (0x1U << EXTI_EMR1_EM30_Pos)                /*!< 0x40000000 */
14787 #define EXTI_EMR1_EM30             EXTI_EMR1_EM30_Msk                          /*!< Event Mask on line 30 */
14788 #define EXTI_EMR1_EM31_Pos         (31U)
14789 #define EXTI_EMR1_EM31_Msk         (0x1U << EXTI_EMR1_EM31_Pos)                /*!< 0x80000000 */
14790 #define EXTI_EMR1_EM31             EXTI_EMR1_EM31_Msk                          /*!< Event Mask on line 31 */
14791 /*******************  Bit definition for EXTI_EMR2 register  *******************/
14792 #define EXTI_EMR2_EM32_Pos         (0U)
14793 #define EXTI_EMR2_EM32_Msk         (0x1U << EXTI_EMR2_EM32_Pos)                /*!< 0x00000001 */
14794 #define EXTI_EMR2_EM32             EXTI_EMR2_EM32_Msk                          /*!< Event Mask on line 32*/
14795 #define EXTI_EMR2_EM33_Pos         (1U)
14796 #define EXTI_EMR2_EM33_Msk         (0x1U << EXTI_EMR2_EM33_Pos)                /*!< 0x00000002 */
14797 #define EXTI_EMR2_EM33             EXTI_EMR2_EM33_Msk                          /*!< Event Mask on line 33*/
14798 #define EXTI_EMR2_EM34_Pos         (2U)
14799 #define EXTI_EMR2_EM34_Msk         (0x1U << EXTI_EMR2_EM34_Pos)                /*!< 0x00000004 */
14800 #define EXTI_EMR2_EM34             EXTI_EMR2_EM34_Msk                          /*!< Event Mask on line 34*/
14801 #define EXTI_EMR2_EM35_Pos         (3U)
14802 #define EXTI_EMR2_EM35_Msk         (0x1U << EXTI_EMR2_EM35_Pos)                /*!< 0x00000008 */
14803 #define EXTI_EMR2_EM35             EXTI_EMR2_EM35_Msk                          /*!< Event Mask on line 35*/
14804 #define EXTI_EMR2_EM36_Pos         (4U)
14805 #define EXTI_EMR2_EM36_Msk         (0x1U << EXTI_EMR2_EM36_Pos)                /*!< 0x00000010 */
14806 #define EXTI_EMR2_EM36             EXTI_EMR2_EM36_Msk                          /*!< Event Mask on line 36*/
14807 #define EXTI_EMR2_EM37_Pos         (5U)
14808 #define EXTI_EMR2_EM37_Msk         (0x1U << EXTI_EMR2_EM37_Pos)                /*!< 0x00000020 */
14809 #define EXTI_EMR2_EM37             EXTI_EMR2_EM37_Msk                          /*!< Event Mask on line 37*/
14810 #define EXTI_EMR2_EM38_Pos         (6U)
14811 #define EXTI_EMR2_EM38_Msk         (0x1U << EXTI_EMR2_EM38_Pos)                /*!< 0x00000040 */
14812 #define EXTI_EMR2_EM38             EXTI_EMR2_EM38_Msk                          /*!< Event Mask on line 38*/
14813 #define EXTI_EMR2_EM39_Pos         (7U)
14814 #define EXTI_EMR2_EM39_Msk         (0x1U << EXTI_EMR2_EM39_Pos)                /*!< 0x00000080 */
14815 #define EXTI_EMR2_EM39             EXTI_EMR2_EM39_Msk                          /*!< Event Mask on line 39*/
14816 #define EXTI_EMR2_EM40_Pos         (8U)
14817 #define EXTI_EMR2_EM40_Msk         (0x1U << EXTI_EMR2_EM40_Pos)                /*!< 0x00000100 */
14818 #define EXTI_EMR2_EM40             EXTI_EMR2_EM40_Msk                          /*!< Event Mask on line 40*/
14819 #define EXTI_EMR2_EM41_Pos         (9U)
14820 #define EXTI_EMR2_EM41_Msk         (0x1U << EXTI_EMR2_EM41_Pos)                /*!< 0x00000200 */
14821 #define EXTI_EMR2_EM41             EXTI_EMR2_EM41_Msk                          /*!< Event Mask on line 41*/
14822 #define EXTI_EMR2_EM42_Pos         (10U)
14823 #define EXTI_EMR2_EM42_Msk         (0x1U << EXTI_EMR2_EM42_Pos)                /*!< 0x00000400 */
14824 #define EXTI_EMR2_EM42             EXTI_EMR2_EM42_Msk                          /*!< Event Mask on line 42 */
14825 #define EXTI_EMR2_EM43_Pos         (11U)
14826 #define EXTI_EMR2_EM43_Msk         (0x1U << EXTI_EMR2_EM43_Pos)                /*!< 0x00000800 */
14827 #define EXTI_EMR2_EM43             EXTI_EMR2_EM43_Msk                          /*!< Event Mask on line 43 */
14828 #define EXTI_EMR2_EM44_Pos         (12U)
14829 #define EXTI_EMR2_EM44_Msk         (0x1U << EXTI_EMR2_EM44_Pos)                /*!< 0x00001000 */
14830 #define EXTI_EMR2_EM44             EXTI_EMR2_EM44_Msk                          /*!< Event Mask on line 44 */
14831 #define EXTI_EMR2_EM45_Pos         (13U)
14832 #define EXTI_EMR2_EM45_Msk         (0x1U << EXTI_EMR2_EM45_Pos)                /*!< 0x00002000 */
14833 #define EXTI_EMR2_EM45             EXTI_EMR2_EM45_Msk                          /*!< Event Mask on line 45 */
14834 #define EXTI_EMR2_EM46_Pos         (14U)
14835 #define EXTI_EMR2_EM46_Msk         (0x1U << EXTI_EMR2_EM46_Pos)                /*!< 0x00004000 */
14836 #define EXTI_EMR2_EM46             EXTI_EMR2_EM46_Msk                          /*!< Event Mask on line 46 */
14837 #define EXTI_EMR2_EM47_Pos         (15U)
14838 #define EXTI_EMR2_EM47_Msk         (0x1U << EXTI_EMR2_EM47_Pos)                /*!< 0x00008000 */
14839 #define EXTI_EMR2_EM47             EXTI_EMR2_EM47_Msk                          /*!< Event Mask on line 47 */
14840 #define EXTI_EMR2_EM48_Pos         (16U)
14841 #define EXTI_EMR2_EM48_Msk         (0x1U << EXTI_EMR2_EM48_Pos)                /*!< 0x00010000 */
14842 #define EXTI_EMR2_EM48             EXTI_EMR2_EM48_Msk                          /*!< Event Mask on line 48 */
14843 #define EXTI_EMR2_EM49_Pos         (17U)
14844 #define EXTI_EMR2_EM49_Msk         (0x1U << EXTI_EMR2_EM49_Pos)                /*!< 0x00020000 */
14845 #define EXTI_EMR2_EM49             EXTI_EMR2_EM49_Msk                          /*!< Event Mask on line 49 */
14846 #define EXTI_EMR2_EM50_Pos         (18U)
14847 #define EXTI_EMR2_EM50_Msk         (0x1U << EXTI_EMR2_EM50_Pos)                /*!< 0x00040000 */
14848 #define EXTI_EMR2_EM50             EXTI_EMR2_EM50_Msk                          /*!< Event Mask on line 50 */
14849 #define EXTI_EMR2_EM51_Pos         (19U)
14850 #define EXTI_EMR2_EM51_Msk         (0x1U << EXTI_EMR2_EM51_Pos)                /*!< 0x00080000 */
14851 #define EXTI_EMR2_EM51             EXTI_EMR2_EM51_Msk                          /*!< Event Mask on line 51 */
14852 #define EXTI_EMR2_EM52_Pos         (20U)
14853 #define EXTI_EMR2_EM52_Msk         (0x1U << EXTI_EMR2_EM52_Pos)                /*!< 0x00100000 */
14854 #define EXTI_EMR2_EM52             EXTI_EMR2_EM52_Msk                          /*!< Event Mask on line 52 */
14855 #define EXTI_EMR2_EM53_Pos         (21U)
14856 #define EXTI_EMR2_EM53_Msk         (0x1U << EXTI_EMR2_EM53_Pos)                /*!< 0x00200000 */
14857 #define EXTI_EMR2_EM53             EXTI_EMR2_EM53_Msk                          /*!< Event Mask on line 53 */
14858 #define EXTI_EMR2_EM54_Pos         (22U)
14859 #define EXTI_EMR2_EM54_Msk         (0x1U << EXTI_EMR2_EM54_Pos)                /*!< 0x00400000 */
14860 #define EXTI_EMR2_EM54             EXTI_EMR2_EM54_Msk                          /*!< Event Mask on line 54 */
14861 #define EXTI_EMR2_EM55_Pos         (23U)
14862 #define EXTI_EMR2_EM55_Msk         (0x1U << EXTI_EMR2_EM55_Pos)                /*!< 0x00800000 */
14863 #define EXTI_EMR2_EM55             EXTI_EMR2_EM55_Msk                          /*!< Event Mask on line 55 */
14864 #define EXTI_EMR2_EM56_Pos         (24U)
14865 #define EXTI_EMR2_EM56_Msk         (0x1U << EXTI_EMR2_EM56_Pos)                /*!< 0x01000000 */
14866 #define EXTI_EMR2_EM56             EXTI_EMR2_EM56_Msk                          /*!< Event Mask on line 56 */
14867 #define EXTI_EMR2_EM57_Pos         (25U)
14868 #define EXTI_EMR2_EM57_Msk         (0x1U << EXTI_EMR2_EM57_Pos)                /*!< 0x02000000 */
14869 #define EXTI_EMR2_EM57             EXTI_EMR2_EM57_Msk                          /*!< Event Mask on line 57 */
14870 #define EXTI_EMR2_EM58_Pos         (26U)
14871 #define EXTI_EMR2_EM58_Msk         (0x1U << EXTI_EMR2_EM58_Pos)                /*!< 0x04000000 */
14872 #define EXTI_EMR2_EM58             EXTI_EMR2_EM58_Msk                          /*!< Event Mask on line 58 */
14873 #define EXTI_EMR2_EM59_Pos         (27U)
14874 #define EXTI_EMR2_EM59_Msk         (0x1U << EXTI_EMR2_EM59_Pos)                /*!< 0x08000000 */
14875 #define EXTI_EMR2_EM59             EXTI_EMR2_EM59_Msk                          /*!< Event Mask on line 59 */
14876 #define EXTI_EMR2_EM60_Pos         (28U)
14877 #define EXTI_EMR2_EM60_Msk         (0x1U << EXTI_EMR2_EM60_Pos)                /*!< 0x10000000 */
14878 #define EXTI_EMR2_EM60             EXTI_EMR2_EM60_Msk                          /*!< Event Mask on line 60 */
14879 #define EXTI_EMR2_EM61_Pos         (29U)
14880 #define EXTI_EMR2_EM61_Msk         (0x1U << EXTI_EMR2_EM61_Pos)                /*!< 0x20000000 */
14881 #define EXTI_EMR2_EM61             EXTI_EMR2_EM61_Msk                          /*!< Event Mask on line 61 */
14882 #define EXTI_EMR2_EM62_Pos         (30U)
14883 #define EXTI_EMR2_EM62_Msk         (0x1U << EXTI_EMR2_EM62_Pos)                /*!< 0x40000000 */
14884 #define EXTI_EMR2_EM62             EXTI_EMR2_EM62_Msk                          /*!< Event Mask on line 62 */
14885 #define EXTI_EMR2_EM63_Pos         (31U)
14886 #define EXTI_EMR2_EM63_Msk         (0x1U << EXTI_EMR2_EM63_Pos)                /*!< 0x80000000 */
14887 #define EXTI_EMR2_EM63             EXTI_EMR2_EM63_Msk                          /*!< Event Mask on line 63 */
14888 /*******************  Bit definition for EXTI_EMR3 register  *******************/
14889 #define EXTI_EMR3_EM64_Pos         (0U)
14890 #define EXTI_EMR3_EM64_Msk         (0x1U << EXTI_EMR3_EM64_Pos)                /*!< 0x00000001 */
14891 #define EXTI_EMR3_EM64             EXTI_EMR3_EM64_Msk                          /*!< Event Mask on line 64*/
14892 #define EXTI_EMR3_EM65_Pos         (1U)
14893 #define EXTI_EMR3_EM65_Msk         (0x1U << EXTI_EMR3_EM65_Pos)                /*!< 0x00000002 */
14894 #define EXTI_EMR3_EM65             EXTI_EMR3_EM65_Msk                          /*!< Event Mask on line 65*/
14895 #define EXTI_EMR3_EM66_Pos         (2U)
14896 #define EXTI_EMR3_EM66_Msk         (0x1U << EXTI_EMR3_EM66_Pos)                /*!< 0x00000004 */
14897 #define EXTI_EMR3_EM66             EXTI_EMR3_EM66_Msk                          /*!< Event Mask on line 66*/
14898 #define EXTI_EMR3_EM67_Pos         (3U)
14899 #define EXTI_EMR3_EM67_Msk         (0x1U << EXTI_EMR3_EM67_Pos)                /*!< 0x00000008 */
14900 #define EXTI_EMR3_EM67             EXTI_EMR3_EM67_Msk                          /*!< Event Mask on line 67*/
14901 #define EXTI_EMR3_EM68_Pos         (4U)
14902 #define EXTI_EMR3_EM68_Msk         (0x1U << EXTI_EMR3_EM68_Pos)                /*!< 0x00000010 */
14903 #define EXTI_EMR3_EM68             EXTI_EMR3_EM68_Msk                          /*!< Event Mask on line 68*/
14904 #define EXTI_EMR3_EM69_Pos         (5U)
14905 #define EXTI_EMR3_EM69_Msk         (0x1U << EXTI_EMR3_EM69_Pos)                /*!< 0x00000020 */
14906 #define EXTI_EMR3_EM69             EXTI_EMR3_EM69_Msk                          /*!< Event Mask on line 69*/
14907 #define EXTI_EMR3_EM70_Pos         (6U)
14908 #define EXTI_EMR3_EM70_Msk         (0x1U << EXTI_EMR3_EM70_Pos)                /*!< 0x00000040 */
14909 #define EXTI_EMR3_EM70             EXTI_EMR3_EM70_Msk                          /*!< Event Mask on line 70*/
14910 #define EXTI_EMR3_EM71_Pos         (7U)
14911 #define EXTI_EMR3_EM71_Msk         (0x1U << EXTI_EMR3_EM71_Pos)                /*!< 0x00000080 */
14912 #define EXTI_EMR3_EM71             EXTI_EMR3_EM71_Msk                          /*!< Event Mask on line 71*/
14913 #define EXTI_EMR3_EM72_Pos         (8U)
14914 #define EXTI_EMR3_EM72_Msk         (0x1U << EXTI_EMR3_EM72_Pos)                /*!< 0x00000100 */
14915 #define EXTI_EMR3_EM72             EXTI_EMR3_EM72_Msk                          /*!< Event Mask on line 72*/
14916 #define EXTI_EMR3_EM73_Pos         (9U)
14917 #define EXTI_EMR3_EM73_Msk         (0x1U << EXTI_EMR3_EM73_Pos)                /*!< 0x00000200 */
14918 #define EXTI_EMR3_EM73             EXTI_EMR3_EM73_Msk                          /*!< Event Mask on line 73*/
14919 #define EXTI_EMR3_EM74_Pos         (10U)
14920 #define EXTI_EMR3_EM74_Msk         (0x1U << EXTI_EMR3_EM74_Pos)                /*!< 0x00000400 */
14921 #define EXTI_EMR3_EM74             EXTI_EMR3_EM74_Msk                          /*!< Event Mask on line 74 */
14922 #define EXTI_EMR3_EM75_Pos         (11U)
14923 #define EXTI_EMR3_EM75_Msk         (0x1U << EXTI_EMR3_EM75_Pos)                /*!< 0x00000800 */
14924 #define EXTI_EMR3_EM75             EXTI_EMR3_EM75_Msk                          /*!< Event Mask on line 75 */
14925 #define EXTI_EMR3_EM76_Pos         (12U)
14926 #define EXTI_EMR3_EM76_Msk         (0x1U << EXTI_EMR3_EM76_Pos)                /*!< 0x00001000 */
14927 #define EXTI_EMR3_EM76             EXTI_EMR3_EM76_Msk                          /*!< Event Mask on line 76 */
14928 #define EXTI_EMR3_EM77_Pos         (13U)
14929 #define EXTI_EMR3_EM77_Msk         (0x1U << EXTI_EMR3_EM77_Pos)                /*!< 0x00002000 */
14930 #define EXTI_EMR3_EM77             EXTI_EMR3_EM77_Msk                          /*!< Event Mask on line 77 */
14931 #define EXTI_EMR3_EM78_Pos         (14U)
14932 #define EXTI_EMR3_EM78_Msk         (0x1U << EXTI_EMR3_EM78_Pos)                /*!< 0x00004000 */
14933 #define EXTI_EMR3_EM78             EXTI_EMR3_EM78_Msk                          /*!< Event Mask on line 78 */
14934 #define EXTI_EMR3_EM79_Pos         (15U)
14935 #define EXTI_EMR3_EM79_Msk         (0x1U << EXTI_EMR3_EM79_Pos)                /*!< 0x00008000 */
14936 #define EXTI_EMR3_EM79             EXTI_EMR3_EM79_Msk                          /*!< Event Mask on line 79 */
14937 #define EXTI_EMR3_EM80_Pos         (16U)
14938 #define EXTI_EMR3_EM80_Msk         (0x1U << EXTI_EMR3_EM80_Pos)                /*!< 0x00010000 */
14939 #define EXTI_EMR3_EM80             EXTI_EMR3_EM80_Msk                          /*!< Event Mask on line 80 */
14940 #define EXTI_EMR3_EM81_Pos         (17U)
14941 #define EXTI_EMR3_EM81_Msk         (0x1U << EXTI_EMR3_EM81_Pos)                /*!< 0x00020000 */
14942 #define EXTI_EMR3_EM81             EXTI_EMR3_EM81_Msk                          /*!< Event Mask on line 81 */
14943 #define EXTI_EMR3_EM82_Pos         (18U)
14944 #define EXTI_EMR3_EM82_Msk         (0x1U << EXTI_EMR3_EM82_Pos)                /*!< 0x00040000 */
14945 #define EXTI_EMR3_EM82             EXTI_EMR3_EM82_Msk                          /*!< Event Mask on line 82 */
14946 #define EXTI_EMR3_EM84_Pos         (20U)
14947 #define EXTI_EMR3_EM84_Msk         (0x1U << EXTI_EMR3_EM84_Pos)                /*!< 0x00100000 */
14948 #define EXTI_EMR3_EM84             EXTI_EMR3_EM84_Msk                          /*!< Event Mask on line 84 */
14949 #define EXTI_EMR3_EM85_Pos         (21U)
14950 #define EXTI_EMR3_EM85_Msk         (0x1U << EXTI_EMR3_EM85_Pos)                /*!< 0x00200000 */
14951 #define EXTI_EMR3_EM85             EXTI_EMR3_EM85_Msk                          /*!< Event Mask on line 85 */
14952 #define EXTI_EMR3_EM86_Pos         (22U)
14953 #define EXTI_EMR3_EM86_Msk         (0x1U << EXTI_EMR3_EM86_Pos)                /*!< 0x00400000 */
14954 #define EXTI_EMR3_EM86             EXTI_EMR3_EM86_Msk                          /*!< Event Mask on line 86 */
14955 #define EXTI_EMR3_EM87_Pos         (23U)
14956 #define EXTI_EMR3_EM87_Msk         (0x1U << EXTI_EMR3_EM87_Pos)                /*!< 0x00800000 */
14957 #define EXTI_EMR3_EM87             EXTI_EMR3_EM87_Msk                          /*!< Event Mask on line 87 */
14958 #define EXTI_EMR3_EM88_Pos         (24U)
14959 #define EXTI_EMR3_EM88_Msk         (0x1U << EXTI_EMR3_EM88_Pos)                /*!< 0x01000000 */
14960 #define EXTI_EMR3_EM88             EXTI_EMR3_EM88_Msk                          /*!< Event Mask on line 88 */
14961 /******************  Bit definition for EXTI_RTSR1 register  *******************/
14962 #define EXTI_RTSR1_TR0_Pos         (0U)
14963 #define EXTI_RTSR1_TR0_Msk         (0x1U << EXTI_RTSR1_TR0_Pos)                /*!< 0x00000001 */
14964 #define EXTI_RTSR1_TR0             EXTI_RTSR1_TR0_Msk                          /*!< Rising trigger event configuration bit of line 0 */
14965 #define EXTI_RTSR1_TR1_Pos         (1U)
14966 #define EXTI_RTSR1_TR1_Msk         (0x1U << EXTI_RTSR1_TR1_Pos)                /*!< 0x00000002 */
14967 #define EXTI_RTSR1_TR1             EXTI_RTSR1_TR1_Msk                          /*!< Rising trigger event configuration bit of line 1 */
14968 #define EXTI_RTSR1_TR2_Pos         (2U)
14969 #define EXTI_RTSR1_TR2_Msk         (0x1U << EXTI_RTSR1_TR2_Pos)                /*!< 0x00000004 */
14970 #define EXTI_RTSR1_TR2             EXTI_RTSR1_TR2_Msk                          /*!< Rising trigger event configuration bit of line 2 */
14971 #define EXTI_RTSR1_TR3_Pos         (3U)
14972 #define EXTI_RTSR1_TR3_Msk         (0x1U << EXTI_RTSR1_TR3_Pos)                /*!< 0x00000008 */
14973 #define EXTI_RTSR1_TR3             EXTI_RTSR1_TR3_Msk                          /*!< Rising trigger event configuration bit of line 3 */
14974 #define EXTI_RTSR1_TR4_Pos         (4U)
14975 #define EXTI_RTSR1_TR4_Msk         (0x1U << EXTI_RTSR1_TR4_Pos)                /*!< 0x00000010 */
14976 #define EXTI_RTSR1_TR4             EXTI_RTSR1_TR4_Msk                          /*!< Rising trigger event configuration bit of line 4 */
14977 #define EXTI_RTSR1_TR5_Pos         (5U)
14978 #define EXTI_RTSR1_TR5_Msk         (0x1U << EXTI_RTSR1_TR5_Pos)                /*!< 0x00000020 */
14979 #define EXTI_RTSR1_TR5             EXTI_RTSR1_TR5_Msk                          /*!< Rising trigger event configuration bit of line 5 */
14980 #define EXTI_RTSR1_TR6_Pos         (6U)
14981 #define EXTI_RTSR1_TR6_Msk         (0x1U << EXTI_RTSR1_TR6_Pos)                /*!< 0x00000040 */
14982 #define EXTI_RTSR1_TR6             EXTI_RTSR1_TR6_Msk                          /*!< Rising trigger event configuration bit of line 6 */
14983 #define EXTI_RTSR1_TR7_Pos         (7U)
14984 #define EXTI_RTSR1_TR7_Msk         (0x1U << EXTI_RTSR1_TR7_Pos)                /*!< 0x00000080 */
14985 #define EXTI_RTSR1_TR7             EXTI_RTSR1_TR7_Msk                          /*!< Rising trigger event configuration bit of line 7 */
14986 #define EXTI_RTSR1_TR8_Pos         (8U)
14987 #define EXTI_RTSR1_TR8_Msk         (0x1U << EXTI_RTSR1_TR8_Pos)                /*!< 0x00000100 */
14988 #define EXTI_RTSR1_TR8             EXTI_RTSR1_TR8_Msk                          /*!< Rising trigger event configuration bit of line 8 */
14989 #define EXTI_RTSR1_TR9_Pos         (9U)
14990 #define EXTI_RTSR1_TR9_Msk         (0x1U << EXTI_RTSR1_TR9_Pos)                /*!< 0x00000200 */
14991 #define EXTI_RTSR1_TR9             EXTI_RTSR1_TR9_Msk                          /*!< Rising trigger event configuration bit of line 9 */
14992 #define EXTI_RTSR1_TR10_Pos        (10U)
14993 #define EXTI_RTSR1_TR10_Msk        (0x1U << EXTI_RTSR1_TR10_Pos)               /*!< 0x00000400 */
14994 #define EXTI_RTSR1_TR10            EXTI_RTSR1_TR10_Msk                         /*!< Rising trigger event configuration bit of line 10 */
14995 #define EXTI_RTSR1_TR11_Pos        (11U)
14996 #define EXTI_RTSR1_TR11_Msk        (0x1U << EXTI_RTSR1_TR11_Pos)               /*!< 0x00000800 */
14997 #define EXTI_RTSR1_TR11            EXTI_RTSR1_TR11_Msk                         /*!< Rising trigger event configuration bit of line 11 */
14998 #define EXTI_RTSR1_TR12_Pos        (12U)
14999 #define EXTI_RTSR1_TR12_Msk        (0x1U << EXTI_RTSR1_TR12_Pos)               /*!< 0x00001000 */
15000 #define EXTI_RTSR1_TR12            EXTI_RTSR1_TR12_Msk                         /*!< Rising trigger event configuration bit of line 12 */
15001 #define EXTI_RTSR1_TR13_Pos        (13U)
15002 #define EXTI_RTSR1_TR13_Msk        (0x1U << EXTI_RTSR1_TR13_Pos)               /*!< 0x00002000 */
15003 #define EXTI_RTSR1_TR13            EXTI_RTSR1_TR13_Msk                         /*!< Rising trigger event configuration bit of line 13 */
15004 #define EXTI_RTSR1_TR14_Pos        (14U)
15005 #define EXTI_RTSR1_TR14_Msk        (0x1U << EXTI_RTSR1_TR14_Pos)               /*!< 0x00004000 */
15006 #define EXTI_RTSR1_TR14            EXTI_RTSR1_TR14_Msk                         /*!< Rising trigger event configuration bit of line 14 */
15007 #define EXTI_RTSR1_TR15_Pos        (15U)
15008 #define EXTI_RTSR1_TR15_Msk        (0x1U << EXTI_RTSR1_TR15_Pos)               /*!< 0x00008000 */
15009 #define EXTI_RTSR1_TR15            EXTI_RTSR1_TR15_Msk                         /*!< Rising trigger event configuration bit of line 15 */
15010 #define EXTI_RTSR1_TR16_Pos        (16U)
15011 #define EXTI_RTSR1_TR16_Msk        (0x1U << EXTI_RTSR1_TR16_Pos)               /*!< 0x00010000 */
15012 #define EXTI_RTSR1_TR16            EXTI_RTSR1_TR16_Msk                         /*!< Rising trigger event configuration bit of line 16 */
15013 #define EXTI_RTSR1_TR17_Pos        (17U)
15014 #define EXTI_RTSR1_TR17_Msk        (0x1U << EXTI_RTSR1_TR17_Pos)               /*!< 0x00020000 */
15015 #define EXTI_RTSR1_TR17            EXTI_RTSR1_TR17_Msk                         /*!< Rising trigger event configuration bit of line 17 */
15016 #define EXTI_RTSR1_TR18_Pos        (18U)
15017 #define EXTI_RTSR1_TR18_Msk        (0x1U << EXTI_RTSR1_TR18_Pos)               /*!< 0x00040000 */
15018 #define EXTI_RTSR1_TR18            EXTI_RTSR1_TR18_Msk                         /*!< Rising trigger event configuration bit of line 18 */
15019 #define EXTI_RTSR1_TR19_Pos        (19U)
15020 #define EXTI_RTSR1_TR19_Msk        (0x1U << EXTI_RTSR1_TR19_Pos)               /*!< 0x00080000 */
15021 #define EXTI_RTSR1_TR19            EXTI_RTSR1_TR19_Msk                         /*!< Rising trigger event configuration bit of line 19 */
15022 #define EXTI_RTSR1_TR20_Pos        (20U)
15023 #define EXTI_RTSR1_TR20_Msk        (0x1U << EXTI_RTSR1_TR20_Pos)               /*!< 0x00100000 */
15024 #define EXTI_RTSR1_TR20            EXTI_RTSR1_TR20_Msk                         /*!< Rising trigger event configuration bit of line 20 */
15025 #define EXTI_RTSR1_TR21_Pos        (21U)
15026 #define EXTI_RTSR1_TR21_Msk        (0x1U << EXTI_RTSR1_TR21_Pos)               /*!< 0x00200000 */
15027 #define EXTI_RTSR1_TR21            EXTI_RTSR1_TR21_Msk                         /*!< Rising trigger event configuration bit of line 21 */
15028 /******************  Bit definition for EXTI_RTSR2 register  *******************/
15029 #define EXTI_RTSR2_TR49_Pos        (17U)
15030 #define EXTI_RTSR2_TR49_Msk        (0x1U << EXTI_RTSR2_TR49_Pos)               /*!< 0x00020000 */
15031 #define EXTI_RTSR2_TR49            EXTI_RTSR2_TR49_Msk                         /*!< Rising trigger event configuration bit of line 49 */
15032 #define EXTI_RTSR2_TR51_Pos        (19U)
15033 #define EXTI_RTSR2_TR51_Msk        (0x1U << EXTI_RTSR2_TR51_Pos)               /*!< 0x00080000 */
15034 #define EXTI_RTSR2_TR51            EXTI_RTSR2_TR51_Msk                         /*!< Rising trigger event configuration bit of line 51 */
15035 /******************  Bit definition for EXTI_RTSR3 register  *******************/
15036 #define EXTI_RTSR3_TR85_Pos        (21U)
15037 #define EXTI_RTSR3_TR85_Msk        (0x1U << EXTI_RTSR3_TR85_Pos)               /*!< 0x00200000 */
15038 #define EXTI_RTSR3_TR85            EXTI_RTSR3_TR85_Msk                         /*!< Rising trigger event configuration bit of line 85 */
15039 #define EXTI_RTSR3_TR86_Pos        (22U)
15040 #define EXTI_RTSR3_TR86_Msk        (0x1U << EXTI_RTSR3_TR86_Pos)               /*!< 0x00400000 */
15041 #define EXTI_RTSR3_TR86            EXTI_RTSR3_TR86_Msk                         /*!< Rising trigger event configuration bit of line 86 */
15042 
15043 /******************  Bit definition for EXTI_FTSR1 register  *******************/
15044 #define EXTI_FTSR1_TR0_Pos         (0U)
15045 #define EXTI_FTSR1_TR0_Msk         (0x1U << EXTI_FTSR1_TR0_Pos)                /*!< 0x00000001 */
15046 #define EXTI_FTSR1_TR0             EXTI_FTSR1_TR0_Msk                          /*!< Falling trigger event configuration bit of line 0 */
15047 #define EXTI_FTSR1_TR1_Pos         (1U)
15048 #define EXTI_FTSR1_TR1_Msk         (0x1U << EXTI_FTSR1_TR1_Pos)                /*!< 0x00000002 */
15049 #define EXTI_FTSR1_TR1             EXTI_FTSR1_TR1_Msk                          /*!< Falling trigger event configuration bit of line 1 */
15050 #define EXTI_FTSR1_TR2_Pos         (2U)
15051 #define EXTI_FTSR1_TR2_Msk         (0x1U << EXTI_FTSR1_TR2_Pos)                /*!< 0x00000004 */
15052 #define EXTI_FTSR1_TR2             EXTI_FTSR1_TR2_Msk                          /*!< Falling trigger event configuration bit of line 2 */
15053 #define EXTI_FTSR1_TR3_Pos         (3U)
15054 #define EXTI_FTSR1_TR3_Msk         (0x1U << EXTI_FTSR1_TR3_Pos)                /*!< 0x00000008 */
15055 #define EXTI_FTSR1_TR3             EXTI_FTSR1_TR3_Msk                          /*!< Falling trigger event configuration bit of line 3 */
15056 #define EXTI_FTSR1_TR4_Pos         (4U)
15057 #define EXTI_FTSR1_TR4_Msk         (0x1U << EXTI_FTSR1_TR4_Pos)                /*!< 0x00000010 */
15058 #define EXTI_FTSR1_TR4             EXTI_FTSR1_TR4_Msk                          /*!< Falling trigger event configuration bit of line 4 */
15059 #define EXTI_FTSR1_TR5_Pos         (5U)
15060 #define EXTI_FTSR1_TR5_Msk         (0x1U << EXTI_FTSR1_TR5_Pos)                /*!< 0x00000020 */
15061 #define EXTI_FTSR1_TR5             EXTI_FTSR1_TR5_Msk                          /*!< Falling trigger event configuration bit of line 5 */
15062 #define EXTI_FTSR1_TR6_Pos         (6U)
15063 #define EXTI_FTSR1_TR6_Msk         (0x1U << EXTI_FTSR1_TR6_Pos)                /*!< 0x00000040 */
15064 #define EXTI_FTSR1_TR6             EXTI_FTSR1_TR6_Msk                          /*!< Falling trigger event configuration bit of line 6 */
15065 #define EXTI_FTSR1_TR7_Pos         (7U)
15066 #define EXTI_FTSR1_TR7_Msk         (0x1U << EXTI_FTSR1_TR7_Pos)                /*!< 0x00000080 */
15067 #define EXTI_FTSR1_TR7             EXTI_FTSR1_TR7_Msk                          /*!< Falling trigger event configuration bit of line 7 */
15068 #define EXTI_FTSR1_TR8_Pos         (8U)
15069 #define EXTI_FTSR1_TR8_Msk         (0x1U << EXTI_FTSR1_TR8_Pos)                /*!< 0x00000100 */
15070 #define EXTI_FTSR1_TR8             EXTI_FTSR1_TR8_Msk                          /*!< Falling trigger event configuration bit of line 8 */
15071 #define EXTI_FTSR1_TR9_Pos         (9U)
15072 #define EXTI_FTSR1_TR9_Msk         (0x1U << EXTI_FTSR1_TR9_Pos)                /*!< 0x00000200 */
15073 #define EXTI_FTSR1_TR9             EXTI_FTSR1_TR9_Msk                          /*!< Falling trigger event configuration bit of line 9 */
15074 #define EXTI_FTSR1_TR10_Pos        (10U)
15075 #define EXTI_FTSR1_TR10_Msk        (0x1U << EXTI_FTSR1_TR10_Pos)               /*!< 0x00000400 */
15076 #define EXTI_FTSR1_TR10            EXTI_FTSR1_TR10_Msk                         /*!< Falling trigger event configuration bit of line 10 */
15077 #define EXTI_FTSR1_TR11_Pos        (11U)
15078 #define EXTI_FTSR1_TR11_Msk        (0x1U << EXTI_FTSR1_TR11_Pos)               /*!< 0x00000800 */
15079 #define EXTI_FTSR1_TR11            EXTI_FTSR1_TR11_Msk                         /*!< Falling trigger event configuration bit of line 11 */
15080 #define EXTI_FTSR1_TR12_Pos        (12U)
15081 #define EXTI_FTSR1_TR12_Msk        (0x1U << EXTI_FTSR1_TR12_Pos)               /*!< 0x00001000 */
15082 #define EXTI_FTSR1_TR12            EXTI_FTSR1_TR12_Msk                         /*!< Falling trigger event configuration bit of line 12 */
15083 #define EXTI_FTSR1_TR13_Pos        (13U)
15084 #define EXTI_FTSR1_TR13_Msk        (0x1U << EXTI_FTSR1_TR13_Pos)               /*!< 0x00002000 */
15085 #define EXTI_FTSR1_TR13            EXTI_FTSR1_TR13_Msk                         /*!< Falling trigger event configuration bit of line 13 */
15086 #define EXTI_FTSR1_TR14_Pos        (14U)
15087 #define EXTI_FTSR1_TR14_Msk        (0x1U << EXTI_FTSR1_TR14_Pos)               /*!< 0x00004000 */
15088 #define EXTI_FTSR1_TR14            EXTI_FTSR1_TR14_Msk                         /*!< Falling trigger event configuration bit of line 14 */
15089 #define EXTI_FTSR1_TR15_Pos        (15U)
15090 #define EXTI_FTSR1_TR15_Msk        (0x1U << EXTI_FTSR1_TR15_Pos)               /*!< 0x00008000 */
15091 #define EXTI_FTSR1_TR15            EXTI_FTSR1_TR15_Msk                         /*!< Falling trigger event configuration bit of line 15 */
15092 #define EXTI_FTSR1_TR16_Pos        (16U)
15093 #define EXTI_FTSR1_TR16_Msk        (0x1U << EXTI_FTSR1_TR16_Pos)               /*!< 0x00010000 */
15094 #define EXTI_FTSR1_TR16            EXTI_FTSR1_TR16_Msk                         /*!< Falling trigger event configuration bit of line 16 */
15095 #define EXTI_FTSR1_TR17_Pos        (17U)
15096 #define EXTI_FTSR1_TR17_Msk        (0x1U << EXTI_FTSR1_TR17_Pos)               /*!< 0x00020000 */
15097 #define EXTI_FTSR1_TR17            EXTI_FTSR1_TR17_Msk                         /*!< Falling trigger event configuration bit of line 17 */
15098 #define EXTI_FTSR1_TR18_Pos        (18U)
15099 #define EXTI_FTSR1_TR18_Msk        (0x1U << EXTI_FTSR1_TR18_Pos)               /*!< 0x00040000 */
15100 #define EXTI_FTSR1_TR18            EXTI_FTSR1_TR18_Msk                         /*!< Falling trigger event configuration bit of line 18 */
15101 #define EXTI_FTSR1_TR19_Pos        (19U)
15102 #define EXTI_FTSR1_TR19_Msk        (0x1U << EXTI_FTSR1_TR19_Pos)               /*!< 0x00080000 */
15103 #define EXTI_FTSR1_TR19            EXTI_FTSR1_TR19_Msk                         /*!< Falling trigger event configuration bit of line 19 */
15104 #define EXTI_FTSR1_TR20_Pos        (20U)
15105 #define EXTI_FTSR1_TR20_Msk        (0x1U << EXTI_FTSR1_TR20_Pos)               /*!< 0x00100000 */
15106 #define EXTI_FTSR1_TR20            EXTI_FTSR1_TR20_Msk                         /*!< Falling trigger event configuration bit of line 20 */
15107 #define EXTI_FTSR1_TR21_Pos        (21U)
15108 #define EXTI_FTSR1_TR21_Msk        (0x1U << EXTI_FTSR1_TR21_Pos)               /*!< 0x00200000 */
15109 #define EXTI_FTSR1_TR21            EXTI_FTSR1_TR21_Msk                         /*!< Falling trigger event configuration bit of line 21 */
15110 /******************  Bit definition for EXTI_FTSR2 register  *******************/
15111 #define EXTI_FTSR2_TR49_Pos        (17U)
15112 #define EXTI_FTSR2_TR49_Msk        (0x1U << EXTI_FTSR2_TR49_Pos)               /*!< 0x00020000 */
15113 #define EXTI_FTSR2_TR49            EXTI_FTSR2_TR49_Msk                         /*!< Falling trigger event configuration bit of line 49 */
15114 #define EXTI_FTSR2_TR51_Pos        (19U)
15115 #define EXTI_FTSR2_TR51_Msk        (0x1U << EXTI_FTSR2_TR51_Pos)               /*!< 0x00080000 */
15116 #define EXTI_FTSR2_TR51            EXTI_FTSR2_TR51_Msk                         /*!< Falling trigger event configuration bit of line 51 */
15117 
15118 /******************  Bit definition for EXTI_FTSR3 register  *******************/
15119 #define EXTI_FTSR3_TR85_Pos        (21U)
15120 #define EXTI_FTSR3_TR85_Msk        (0x1U << EXTI_FTSR3_TR85_Pos)               /*!< 0x00200000 */
15121 #define EXTI_FTSR3_TR85            EXTI_FTSR3_TR85_Msk                         /*!< Falling trigger event configuration bit of line 85 */
15122 #define EXTI_FTSR3_TR86_Pos        (22U)
15123 #define EXTI_FTSR3_TR86_Msk        (0x1U << EXTI_FTSR3_TR86_Pos)               /*!< 0x00400000 */
15124 #define EXTI_FTSR3_TR86            EXTI_FTSR3_TR86_Msk                         /*!< Falling trigger event configuration bit of line 86 */
15125 /******************  Bit definition for EXTI_SWIER1 register  ******************/
15126 #define EXTI_SWIER1_SWIER0_Pos     (0U)
15127 #define EXTI_SWIER1_SWIER0_Msk     (0x1U << EXTI_SWIER1_SWIER0_Pos)            /*!< 0x00000001 */
15128 #define EXTI_SWIER1_SWIER0         EXTI_SWIER1_SWIER0_Msk                      /*!< Software Interrupt on line 0 */
15129 #define EXTI_SWIER1_SWIER1_Pos     (1U)
15130 #define EXTI_SWIER1_SWIER1_Msk     (0x1U << EXTI_SWIER1_SWIER1_Pos)            /*!< 0x00000002 */
15131 #define EXTI_SWIER1_SWIER1         EXTI_SWIER1_SWIER1_Msk                      /*!< Software Interrupt on line 1 */
15132 #define EXTI_SWIER1_SWIER2_Pos     (2U)
15133 #define EXTI_SWIER1_SWIER2_Msk     (0x1U << EXTI_SWIER1_SWIER2_Pos)            /*!< 0x00000004 */
15134 #define EXTI_SWIER1_SWIER2         EXTI_SWIER1_SWIER2_Msk                      /*!< Software Interrupt on line 2 */
15135 #define EXTI_SWIER1_SWIER3_Pos     (3U)
15136 #define EXTI_SWIER1_SWIER3_Msk     (0x1U << EXTI_SWIER1_SWIER3_Pos)            /*!< 0x00000008 */
15137 #define EXTI_SWIER1_SWIER3         EXTI_SWIER1_SWIER3_Msk                      /*!< Software Interrupt on line 3 */
15138 #define EXTI_SWIER1_SWIER4_Pos     (4U)
15139 #define EXTI_SWIER1_SWIER4_Msk     (0x1U << EXTI_SWIER1_SWIER4_Pos)            /*!< 0x00000010 */
15140 #define EXTI_SWIER1_SWIER4         EXTI_SWIER1_SWIER4_Msk                      /*!< Software Interrupt on line 4 */
15141 #define EXTI_SWIER1_SWIER5_Pos     (5U)
15142 #define EXTI_SWIER1_SWIER5_Msk     (0x1U << EXTI_SWIER1_SWIER5_Pos)            /*!< 0x00000020 */
15143 #define EXTI_SWIER1_SWIER5         EXTI_SWIER1_SWIER5_Msk                      /*!< Software Interrupt on line 5 */
15144 #define EXTI_SWIER1_SWIER6_Pos     (6U)
15145 #define EXTI_SWIER1_SWIER6_Msk     (0x1U << EXTI_SWIER1_SWIER6_Pos)            /*!< 0x00000040 */
15146 #define EXTI_SWIER1_SWIER6         EXTI_SWIER1_SWIER6_Msk                      /*!< Software Interrupt on line 6 */
15147 #define EXTI_SWIER1_SWIER7_Pos     (7U)
15148 #define EXTI_SWIER1_SWIER7_Msk     (0x1U << EXTI_SWIER1_SWIER7_Pos)            /*!< 0x00000080 */
15149 #define EXTI_SWIER1_SWIER7         EXTI_SWIER1_SWIER7_Msk                      /*!< Software Interrupt on line 7 */
15150 #define EXTI_SWIER1_SWIER8_Pos     (8U)
15151 #define EXTI_SWIER1_SWIER8_Msk     (0x1U << EXTI_SWIER1_SWIER8_Pos)            /*!< 0x00000100 */
15152 #define EXTI_SWIER1_SWIER8         EXTI_SWIER1_SWIER8_Msk                      /*!< Software Interrupt on line 8 */
15153 #define EXTI_SWIER1_SWIER9_Pos     (9U)
15154 #define EXTI_SWIER1_SWIER9_Msk     (0x1U << EXTI_SWIER1_SWIER9_Pos)            /*!< 0x00000200 */
15155 #define EXTI_SWIER1_SWIER9         EXTI_SWIER1_SWIER9_Msk                      /*!< Software Interrupt on line 9 */
15156 #define EXTI_SWIER1_SWIER10_Pos    (10U)
15157 #define EXTI_SWIER1_SWIER10_Msk    (0x1U << EXTI_SWIER1_SWIER10_Pos)           /*!< 0x00000400 */
15158 #define EXTI_SWIER1_SWIER10        EXTI_SWIER1_SWIER10_Msk                     /*!< Software Interrupt on line 10 */
15159 #define EXTI_SWIER1_SWIER11_Pos    (11U)
15160 #define EXTI_SWIER1_SWIER11_Msk    (0x1U << EXTI_SWIER1_SWIER11_Pos)           /*!< 0x00000800 */
15161 #define EXTI_SWIER1_SWIER11        EXTI_SWIER1_SWIER11_Msk                     /*!< Software Interrupt on line 11 */
15162 #define EXTI_SWIER1_SWIER12_Pos    (12U)
15163 #define EXTI_SWIER1_SWIER12_Msk    (0x1U << EXTI_SWIER1_SWIER12_Pos)           /*!< 0x00001000 */
15164 #define EXTI_SWIER1_SWIER12        EXTI_SWIER1_SWIER12_Msk                     /*!< Software Interrupt on line 12 */
15165 #define EXTI_SWIER1_SWIER13_Pos    (13U)
15166 #define EXTI_SWIER1_SWIER13_Msk    (0x1U << EXTI_SWIER1_SWIER13_Pos)           /*!< 0x00002000 */
15167 #define EXTI_SWIER1_SWIER13        EXTI_SWIER1_SWIER13_Msk                     /*!< Software Interrupt on line 13 */
15168 #define EXTI_SWIER1_SWIER14_Pos    (14U)
15169 #define EXTI_SWIER1_SWIER14_Msk    (0x1U << EXTI_SWIER1_SWIER14_Pos)           /*!< 0x00004000 */
15170 #define EXTI_SWIER1_SWIER14        EXTI_SWIER1_SWIER14_Msk                     /*!< Software Interrupt on line 14 */
15171 #define EXTI_SWIER1_SWIER15_Pos    (15U)
15172 #define EXTI_SWIER1_SWIER15_Msk    (0x1U << EXTI_SWIER1_SWIER15_Pos)           /*!< 0x00008000 */
15173 #define EXTI_SWIER1_SWIER15        EXTI_SWIER1_SWIER15_Msk                     /*!< Software Interrupt on line 15 */
15174 #define EXTI_SWIER1_SWIER16_Pos    (16U)
15175 #define EXTI_SWIER1_SWIER16_Msk    (0x1U << EXTI_SWIER1_SWIER16_Pos)           /*!< 0x00010000 */
15176 #define EXTI_SWIER1_SWIER16        EXTI_SWIER1_SWIER16_Msk                     /*!< Software Interrupt on line 16 */
15177 #define EXTI_SWIER1_SWIER17_Pos    (17U)
15178 #define EXTI_SWIER1_SWIER17_Msk    (0x1U << EXTI_SWIER1_SWIER17_Pos)           /*!< 0x00020000 */
15179 #define EXTI_SWIER1_SWIER17        EXTI_SWIER1_SWIER17_Msk                     /*!< Software Interrupt on line 17 */
15180 #define EXTI_SWIER1_SWIER18_Pos    (18U)
15181 #define EXTI_SWIER1_SWIER18_Msk    (0x1U << EXTI_SWIER1_SWIER18_Pos)           /*!< 0x00040000 */
15182 #define EXTI_SWIER1_SWIER18        EXTI_SWIER1_SWIER18_Msk                     /*!< Software Interrupt on line 18 */
15183 #define EXTI_SWIER1_SWIER19_Pos    (19U)
15184 #define EXTI_SWIER1_SWIER19_Msk    (0x1U << EXTI_SWIER1_SWIER19_Pos)           /*!< 0x00080000 */
15185 #define EXTI_SWIER1_SWIER19        EXTI_SWIER1_SWIER19_Msk                     /*!< Software Interrupt on line 19 */
15186 #define EXTI_SWIER1_SWIER20_Pos    (20U)
15187 #define EXTI_SWIER1_SWIER20_Msk    (0x1U << EXTI_SWIER1_SWIER20_Pos)           /*!< 0x00100000 */
15188 #define EXTI_SWIER1_SWIER20        EXTI_SWIER1_SWIER20_Msk                     /*!< Software Interrupt on line 20 */
15189 #define EXTI_SWIER1_SWIER21_Pos    (21U)
15190 #define EXTI_SWIER1_SWIER21_Msk    (0x1U << EXTI_SWIER1_SWIER21_Pos)           /*!< 0x00200000 */
15191 #define EXTI_SWIER1_SWIER21        EXTI_SWIER1_SWIER21_Msk                     /*!< Software Interrupt on line 21 */
15192 
15193 /******************  Bit definition for EXTI_SWIER2 register  ******************/
15194 #define EXTI_SWIER2_SWIER49_Pos    (17U)
15195 #define EXTI_SWIER2_SWIER49_Msk    (0x1U << EXTI_SWIER2_SWIER49_Pos)           /*!< 0x00020000 */
15196 #define EXTI_SWIER2_SWIER49        EXTI_SWIER2_SWIER49_Msk                     /*!< Software Interrupt on line 49 */
15197 #define EXTI_SWIER2_SWIER51_Pos    (19U)
15198 #define EXTI_SWIER2_SWIER51_Msk    (0x1U << EXTI_SWIER2_SWIER51_Pos)           /*!< 0x00080000 */
15199 #define EXTI_SWIER2_SWIER51        EXTI_SWIER2_SWIER51_Msk                     /*!< Software Interrupt on line 51 */
15200 
15201 /******************  Bit definition for EXTI_SWIER3 register  ******************/
15202 #define EXTI_SWIER3_SWIER85_Pos    (21U)
15203 #define EXTI_SWIER3_SWIER85_Msk    (0x1U << EXTI_SWIER3_SWIER85_Pos)           /*!< 0x00200000 */
15204 #define EXTI_SWIER3_SWIER85        EXTI_SWIER3_SWIER85_Msk                     /*!< Software Interrupt on line 85 */
15205 #define EXTI_SWIER3_SWIER86_Pos    (22U)
15206 #define EXTI_SWIER3_SWIER86_Msk    (0x1U << EXTI_SWIER3_SWIER86_Pos)           /*!< 0x00400000 */
15207 #define EXTI_SWIER3_SWIER86        EXTI_SWIER3_SWIER86_Msk                     /*!< Software Interrupt on line 86 */
15208 
15209 /*******************  Bit definition for EXTI_PR1 register  ********************/
15210 #define EXTI_PR1_PR0_Pos           (0U)
15211 #define EXTI_PR1_PR0_Msk           (0x1U << EXTI_PR1_PR0_Pos)                  /*!< 0x00000001 */
15212 #define EXTI_PR1_PR0               EXTI_PR1_PR0_Msk                            /*!< Pending bit for line 0 */
15213 #define EXTI_PR1_PR1_Pos           (1U)
15214 #define EXTI_PR1_PR1_Msk           (0x1U << EXTI_PR1_PR1_Pos)                  /*!< 0x00000002 */
15215 #define EXTI_PR1_PR1               EXTI_PR1_PR1_Msk                            /*!< Pending bit for line 1 */
15216 #define EXTI_PR1_PR2_Pos           (2U)
15217 #define EXTI_PR1_PR2_Msk           (0x1U << EXTI_PR1_PR2_Pos)                  /*!< 0x00000004 */
15218 #define EXTI_PR1_PR2               EXTI_PR1_PR2_Msk                            /*!< Pending bit for line 2 */
15219 #define EXTI_PR1_PR3_Pos           (3U)
15220 #define EXTI_PR1_PR3_Msk           (0x1U << EXTI_PR1_PR3_Pos)                  /*!< 0x00000008 */
15221 #define EXTI_PR1_PR3               EXTI_PR1_PR3_Msk                            /*!< Pending bit for line 3 */
15222 #define EXTI_PR1_PR4_Pos           (4U)
15223 #define EXTI_PR1_PR4_Msk           (0x1U << EXTI_PR1_PR4_Pos)                  /*!< 0x00000010 */
15224 #define EXTI_PR1_PR4               EXTI_PR1_PR4_Msk                            /*!< Pending bit for line 4 */
15225 #define EXTI_PR1_PR5_Pos           (5U)
15226 #define EXTI_PR1_PR5_Msk           (0x1U << EXTI_PR1_PR5_Pos)                  /*!< 0x00000020 */
15227 #define EXTI_PR1_PR5               EXTI_PR1_PR5_Msk                            /*!< Pending bit for line 5 */
15228 #define EXTI_PR1_PR6_Pos           (6U)
15229 #define EXTI_PR1_PR6_Msk           (0x1U << EXTI_PR1_PR6_Pos)                  /*!< 0x00000040 */
15230 #define EXTI_PR1_PR6               EXTI_PR1_PR6_Msk                            /*!< Pending bit for line 6 */
15231 #define EXTI_PR1_PR7_Pos           (7U)
15232 #define EXTI_PR1_PR7_Msk           (0x1U << EXTI_PR1_PR7_Pos)                  /*!< 0x00000080 */
15233 #define EXTI_PR1_PR7               EXTI_PR1_PR7_Msk                            /*!< Pending bit for line 7 */
15234 #define EXTI_PR1_PR8_Pos           (8U)
15235 #define EXTI_PR1_PR8_Msk           (0x1U << EXTI_PR1_PR8_Pos)                  /*!< 0x00000100 */
15236 #define EXTI_PR1_PR8               EXTI_PR1_PR8_Msk                            /*!< Pending bit for line 8 */
15237 #define EXTI_PR1_PR9_Pos           (9U)
15238 #define EXTI_PR1_PR9_Msk           (0x1U << EXTI_PR1_PR9_Pos)                  /*!< 0x00000200 */
15239 #define EXTI_PR1_PR9               EXTI_PR1_PR9_Msk                            /*!< Pending bit for line 9 */
15240 #define EXTI_PR1_PR10_Pos          (10U)
15241 #define EXTI_PR1_PR10_Msk          (0x1U << EXTI_PR1_PR10_Pos)                 /*!< 0x00000400 */
15242 #define EXTI_PR1_PR10              EXTI_PR1_PR10_Msk                           /*!< Pending bit for line 10 */
15243 #define EXTI_PR1_PR11_Pos          (11U)
15244 #define EXTI_PR1_PR11_Msk          (0x1U << EXTI_PR1_PR11_Pos)                 /*!< 0x00000800 */
15245 #define EXTI_PR1_PR11              EXTI_PR1_PR11_Msk                           /*!< Pending bit for line 11 */
15246 #define EXTI_PR1_PR12_Pos          (12U)
15247 #define EXTI_PR1_PR12_Msk          (0x1U << EXTI_PR1_PR12_Pos)                 /*!< 0x00001000 */
15248 #define EXTI_PR1_PR12              EXTI_PR1_PR12_Msk                           /*!< Pending bit for line 12 */
15249 #define EXTI_PR1_PR13_Pos          (13U)
15250 #define EXTI_PR1_PR13_Msk          (0x1U << EXTI_PR1_PR13_Pos)                 /*!< 0x00002000 */
15251 #define EXTI_PR1_PR13              EXTI_PR1_PR13_Msk                           /*!< Pending bit for line 13 */
15252 #define EXTI_PR1_PR14_Pos          (14U)
15253 #define EXTI_PR1_PR14_Msk          (0x1U << EXTI_PR1_PR14_Pos)                 /*!< 0x00004000 */
15254 #define EXTI_PR1_PR14              EXTI_PR1_PR14_Msk                           /*!< Pending bit for line 14 */
15255 #define EXTI_PR1_PR15_Pos          (15U)
15256 #define EXTI_PR1_PR15_Msk          (0x1U << EXTI_PR1_PR15_Pos)                 /*!< 0x00008000 */
15257 #define EXTI_PR1_PR15              EXTI_PR1_PR15_Msk                           /*!< Pending bit for line 15 */
15258 #define EXTI_PR1_PR16_Pos          (16U)
15259 #define EXTI_PR1_PR16_Msk          (0x1U << EXTI_PR1_PR16_Pos)                 /*!< 0x00010000 */
15260 #define EXTI_PR1_PR16              EXTI_PR1_PR16_Msk                           /*!< Pending bit for line 16 */
15261 
15262 /*******************  Bit definition for EXTI_PR3 register  ********************/
15263 #define EXTI_PR3_PR65_Pos          (1U)
15264 #define EXTI_PR3_PR65_Msk          (0x1U << EXTI_PR3_PR65_Pos)                 /*!< 0x00000002 */
15265 #define EXTI_PR3_PR65              EXTI_PR3_PR65_Msk                           /*!< Pending bit for line 65 */
15266 #define EXTI_PR3_PR66_Pos          (2U)
15267 #define EXTI_PR3_PR66_Msk          (0x1U << EXTI_PR3_PR66_Pos)                 /*!< 0x00000004 */
15268 #define EXTI_PR3_PR66              EXTI_PR3_PR66_Msk                           /*!< Pending bit for line 66 */
15269 #define EXTI_PR3_PR68_Pos          (4U)
15270 #define EXTI_PR3_PR68_Msk          (0x1U << EXTI_PR3_PR68_Pos)                 /*!< 0x00000010 */
15271 #define EXTI_PR3_PR68              EXTI_PR3_PR68_Msk                           /*!< Pending bit for line 68 */
15272 #define EXTI_PR3_PR73_Pos          (9U)
15273 #define EXTI_PR3_PR73_Msk          (0x1U << EXTI_PR3_PR73_Pos)                 /*!< 0x00000200 */
15274 #define EXTI_PR3_PR73              EXTI_PR3_PR73_Msk                           /*!< Pending bit for line 73 */
15275 #define EXTI_PR3_PR74_Pos          (10U)
15276 #define EXTI_PR3_PR74_Msk          (0x1U << EXTI_PR3_PR74_Pos)                 /*!< 0x00000400 */
15277 #define EXTI_PR3_PR74              EXTI_PR3_PR74_Msk                           /*!< Pending bit for line 74 */
15278 
15279 /*****************  Bit definition for EXTI_EXTICR1 register  ***************/
15280 #define EXTI_EXTICR1_EXTI0_Pos        (0U)
15281 #define EXTI_EXTICR1_EXTI0_Msk        (0x0FU << EXTI_EXTICR1_EXTI0_Pos)        /*!< 0x0000000F */
15282 #define EXTI_EXTICR1_EXTI0            EXTI_EXTICR1_EXTI0_Msk                   /*!<EXTI 0 configuration */
15283 #define EXTI_EXTICR1_EXTI1_Pos        (8U)
15284 #define EXTI_EXTICR1_EXTI1_Msk        (0x0FU << EXTI_EXTICR1_EXTI1_Pos)        /*!< 0x00000F00 */
15285 #define EXTI_EXTICR1_EXTI1            EXTI_EXTICR1_EXTI1_Msk                   /*!<EXTI 1 configuration */
15286 #define EXTI_EXTICR1_EXTI2_Pos        (16U)
15287 #define EXTI_EXTICR1_EXTI2_Msk        (0x0FU << EXTI_EXTICR1_EXTI2_Pos)        /*!< 0x000F0000 */
15288 #define EXTI_EXTICR1_EXTI2            EXTI_EXTICR1_EXTI2_Msk                   /*!<EXTI 2 configuration */
15289 #define EXTI_EXTICR1_EXTI3_Pos        (24U)
15290 #define EXTI_EXTICR1_EXTI3_Msk        (0x0FU << EXTI_EXTICR1_EXTI3_Pos)        /*!< 0x0F000000 */
15291 #define EXTI_EXTICR1_EXTI3            EXTI_EXTICR1_EXTI3_Msk                   /*!<EXTI 3 configuration */
15292 /**
15293   * @brief   EXTI0 configuration
15294   */
15295 #define EXTI_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000)                   /*!<PA[0] pin */
15296 #define EXTI_EXTICR1_EXTI0_PB_Pos     (0U)
15297 #define EXTI_EXTICR1_EXTI0_PB_Msk     (0x1U << EXTI_EXTICR1_EXTI0_PB_Pos)      /*!< 0x00000001 */
15298 #define EXTI_EXTICR1_EXTI0_PB         EXTI_EXTICR1_EXTI0_PB_Msk                /*!<PB[0] pin */
15299 #define EXTI_EXTICR1_EXTI0_PC_Pos     (1U)
15300 #define EXTI_EXTICR1_EXTI0_PC_Msk     (0x1U << EXTI_EXTICR1_EXTI0_PC_Pos)      /*!< 0x00000002 */
15301 #define EXTI_EXTICR1_EXTI0_PC         EXTI_EXTICR1_EXTI0_PC_Msk                /*!<PC[0] pin */
15302 #define EXTI_EXTICR1_EXTI0_PD_Pos     (0U)
15303 #define EXTI_EXTICR1_EXTI0_PD_Msk     (0x3U << EXTI_EXTICR1_EXTI0_PD_Pos)      /*!< 0x00000003 */
15304 #define EXTI_EXTICR1_EXTI0_PD         EXTI_EXTICR1_EXTI0_PD_Msk                /*!<PD[0] pin */
15305 #define EXTI_EXTICR1_EXTI0_PE_Pos     (2U)
15306 #define EXTI_EXTICR1_EXTI0_PE_Msk     (0x1U << EXTI_EXTICR1_EXTI0_PE_Pos)      /*!< 0x00000004 */
15307 #define EXTI_EXTICR1_EXTI0_PE         EXTI_EXTICR1_EXTI0_PE_Msk                /*!<PE[0] pin */
15308 #define EXTI_EXTICR1_EXTI0_PF_Pos     (0U)
15309 #define EXTI_EXTICR1_EXTI0_PF_Msk     (0x5U << EXTI_EXTICR1_EXTI0_PF_Pos)      /*!< 0x00000005 */
15310 #define EXTI_EXTICR1_EXTI0_PF         EXTI_EXTICR1_EXTI0_PF_Msk                /*!<PF[0] pin */
15311 #define EXTI_EXTICR1_EXTI0_PG_Pos     (1U)
15312 #define EXTI_EXTICR1_EXTI0_PG_Msk     (0x3U << EXTI_EXTICR1_EXTI0_PG_Pos)      /*!< 0x00000006 */
15313 #define EXTI_EXTICR1_EXTI0_PG         EXTI_EXTICR1_EXTI0_PG_Msk                /*!<PG[0] pin */
15314 #define EXTI_EXTICR1_EXTI0_PH_Pos     (0U)
15315 #define EXTI_EXTICR1_EXTI0_PH_Msk     (0x7U << EXTI_EXTICR1_EXTI0_PH_Pos)      /*!< 0x00000007 */
15316 #define EXTI_EXTICR1_EXTI0_PH         EXTI_EXTICR1_EXTI0_PH_Msk                /*!<PH[0] pin */
15317 #define EXTI_EXTICR1_EXTI0_PI_Pos     (3U)
15318 #define EXTI_EXTICR1_EXTI0_PI_Msk     (0x1U << EXTI_EXTICR1_EXTI0_PI_Pos)      /*!< 0x00000008 */
15319 #define EXTI_EXTICR1_EXTI0_PI         EXTI_EXTICR1_EXTI0_PI_Msk                /*!<PI[0] pin */
15320 #define EXTI_EXTICR1_EXTI0_PJ_Pos     (0U)
15321 #define EXTI_EXTICR1_EXTI0_PJ_Msk     (0x9U << EXTI_EXTICR1_EXTI0_PJ_Pos)      /*!< 0x00000009 */
15322 #define EXTI_EXTICR1_EXTI0_PJ         EXTI_EXTICR1_EXTI0_PJ_Msk                /*!<PJ[0] pin */
15323 #define EXTI_EXTICR1_EXTI0_PK_Pos     (1U)
15324 #define EXTI_EXTICR1_EXTI0_PK_Msk     (0x5U << EXTI_EXTICR1_EXTI0_PK_Pos)      /*!< 0x0000000A */
15325 #define EXTI_EXTICR1_EXTI0_PK         EXTI_EXTICR1_EXTI0_PK_Msk                /*!<PK[0] pin */
15326 #define EXTI_EXTICR1_EXTI0_PZ_Pos     (0U)
15327 #define EXTI_EXTICR1_EXTI0_PZ_Msk     (0xBU << EXTI_EXTICR1_EXTI0_PZ_Pos)      /*!< 0x0000000B */
15328 #define EXTI_EXTICR1_EXTI0_PZ         EXTI_EXTICR1_EXTI0_PZ_Msk                /*!<PZ[0] pin */
15329 
15330 
15331 
15332 /**
15333   * @brief   EXTI1 configuration
15334   */
15335 #define EXTI_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000)                   /*!<PA[1] pin */
15336 #define EXTI_EXTICR1_EXTI1_PB_Pos     (8U)
15337 #define EXTI_EXTICR1_EXTI1_PB_Msk     (0x1U << EXTI_EXTICR1_EXTI1_PB_Pos)      /*!< 0x00000100 */
15338 #define EXTI_EXTICR1_EXTI1_PB         EXTI_EXTICR1_EXTI1_PB_Msk                /*!<PB[1] pin */
15339 #define EXTI_EXTICR1_EXTI1_PC_Pos     (9U)
15340 #define EXTI_EXTICR1_EXTI1_PC_Msk     (0x1U << EXTI_EXTICR1_EXTI1_PC_Pos)      /*!< 0x00000200 */
15341 #define EXTI_EXTICR1_EXTI1_PC         EXTI_EXTICR1_EXTI1_PC_Msk                /*!<PC[1] pin */
15342 #define EXTI_EXTICR1_EXTI1_PD_Pos     (8U)
15343 #define EXTI_EXTICR1_EXTI1_PD_Msk     (0x3U << EXTI_EXTICR1_EXTI1_PD_Pos)      /*!< 0x00000300 */
15344 #define EXTI_EXTICR1_EXTI1_PD         EXTI_EXTICR1_EXTI1_PD_Msk                /*!<PD[1] pin */
15345 #define EXTI_EXTICR1_EXTI1_PE_Pos     (10U)
15346 #define EXTI_EXTICR1_EXTI1_PE_Msk     (0x1U << EXTI_EXTICR1_EXTI1_PE_Pos)      /*!< 0x00000400 */
15347 #define EXTI_EXTICR1_EXTI1_PE         EXTI_EXTICR1_EXTI1_PE_Msk                /*!<PE[1] pin */
15348 #define EXTI_EXTICR1_EXTI1_PF_Pos     (8U)
15349 #define EXTI_EXTICR1_EXTI1_PF_Msk     (0x5U << EXTI_EXTICR1_EXTI1_PF_Pos)      /*!< 0x00000500 */
15350 #define EXTI_EXTICR1_EXTI1_PF         EXTI_EXTICR1_EXTI1_PF_Msk                /*!<PF[1] pin */
15351 #define EXTI_EXTICR1_EXTI1_PG_Pos     (9U)
15352 #define EXTI_EXTICR1_EXTI1_PG_Msk     (0x3U << EXTI_EXTICR1_EXTI1_PG_Pos)      /*!< 0x00000600 */
15353 #define EXTI_EXTICR1_EXTI1_PG         EXTI_EXTICR1_EXTI1_PG_Msk                /*!<PG[1] pin */
15354 #define EXTI_EXTICR1_EXTI1_PH_Pos     (8U)
15355 #define EXTI_EXTICR1_EXTI1_PH_Msk     (0x7U << EXTI_EXTICR1_EXTI1_PH_Pos)      /*!< 0x00000700 */
15356 #define EXTI_EXTICR1_EXTI1_PH         EXTI_EXTICR1_EXTI1_PH_Msk                /*!<PH[1] pin */
15357 #define EXTI_EXTICR1_EXTI1_PI_Pos     (11U)
15358 #define EXTI_EXTICR1_EXTI1_PI_Msk     (0x1U << EXTI_EXTICR1_EXTI1_PI_Pos)      /*!< 0x00000800 */
15359 #define EXTI_EXTICR1_EXTI1_PI         EXTI_EXTICR1_EXTI1_PI_Msk                /*!<PI[1] pin */
15360 #define EXTI_EXTICR1_EXTI1_PJ_Pos     (8U)
15361 #define EXTI_EXTICR1_EXTI1_PJ_Msk     (0x9U << EXTI_EXTICR1_EXTI1_PJ_Pos)      /*!< 0x00000900 */
15362 #define EXTI_EXTICR1_EXTI1_PJ         EXTI_EXTICR1_EXTI1_PJ_Msk                /*!<PJ[1] pin */
15363 #define EXTI_EXTICR1_EXTI1_PK_Pos     (9U)
15364 #define EXTI_EXTICR1_EXTI1_PK_Msk     (0x5U << EXTI_EXTICR1_EXTI1_PK_Pos)      /*!< 0x00000A00 */
15365 #define EXTI_EXTICR1_EXTI1_PK         EXTI_EXTICR1_EXTI1_PK_Msk                /*!<PK[1] pin */
15366 #define EXTI_EXTICR1_EXTI1_PZ_Pos     (8U)
15367 #define EXTI_EXTICR1_EXTI1_PZ_Msk     (0xBU << EXTI_EXTICR1_EXTI1_PZ_Pos)      /*!< 0x00000B00 */
15368 #define EXTI_EXTICR1_EXTI1_PZ         EXTI_EXTICR1_EXTI1_PZ_Msk                /*!<PZ[1] pin */
15369 
15370 /**
15371   * @brief   EXTI2 configuration
15372   */
15373 #define EXTI_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000)                   /*!<PA[2] pin */
15374 #define EXTI_EXTICR1_EXTI2_PB_Pos     (16U)
15375 #define EXTI_EXTICR1_EXTI2_PB_Msk     (0x1U << EXTI_EXTICR1_EXTI2_PB_Pos)      /*!< 0x00010000 */
15376 #define EXTI_EXTICR1_EXTI2_PB         EXTI_EXTICR1_EXTI2_PB_Msk                /*!<PB[2] pin */
15377 #define EXTI_EXTICR1_EXTI2_PC_Pos     (17U)
15378 #define EXTI_EXTICR1_EXTI2_PC_Msk     (0x1U << EXTI_EXTICR1_EXTI2_PC_Pos)      /*!< 0x00020000 */
15379 #define EXTI_EXTICR1_EXTI2_PC         EXTI_EXTICR1_EXTI2_PC_Msk                /*!<PC[2] pin */
15380 #define EXTI_EXTICR1_EXTI2_PD_Pos     (16U)
15381 #define EXTI_EXTICR1_EXTI2_PD_Msk     (0x3U << EXTI_EXTICR1_EXTI2_PD_Pos)      /*!< 0x00030000 */
15382 #define EXTI_EXTICR1_EXTI2_PD         EXTI_EXTICR1_EXTI2_PD_Msk                /*!<PD[2] pin */
15383 #define EXTI_EXTICR1_EXTI2_PE_Pos     (18U)
15384 #define EXTI_EXTICR1_EXTI2_PE_Msk     (0x1U << EXTI_EXTICR1_EXTI2_PE_Pos)      /*!< 0x00040000 */
15385 #define EXTI_EXTICR1_EXTI2_PE         EXTI_EXTICR1_EXTI2_PE_Msk                /*!<PE[2] pin */
15386 #define EXTI_EXTICR1_EXTI2_PF_Pos     (16U)
15387 #define EXTI_EXTICR1_EXTI2_PF_Msk     (0x5U << EXTI_EXTICR1_EXTI2_PF_Pos)      /*!< 0x00050000 */
15388 #define EXTI_EXTICR1_EXTI2_PF         EXTI_EXTICR1_EXTI2_PF_Msk                /*!<PF[2] pin */
15389 #define EXTI_EXTICR1_EXTI2_PG_Pos     (17U)
15390 #define EXTI_EXTICR1_EXTI2_PG_Msk     (0x3U << EXTI_EXTICR1_EXTI2_PG_Pos)      /*!< 0x00060000 */
15391 #define EXTI_EXTICR1_EXTI2_PG         EXTI_EXTICR1_EXTI2_PG_Msk                /*!<PG[2] pin */
15392 #define EXTI_EXTICR1_EXTI2_PH_Pos     (16U)
15393 #define EXTI_EXTICR1_EXTI2_PH_Msk     (0x7U << EXTI_EXTICR1_EXTI2_PH_Pos)      /*!< 0x00070000 */
15394 #define EXTI_EXTICR1_EXTI2_PH         EXTI_EXTICR1_EXTI2_PH_Msk                /*!<PH[2] pin */
15395 #define EXTI_EXTICR1_EXTI2_PI_Pos     (19U)
15396 #define EXTI_EXTICR1_EXTI2_PI_Msk     (0x1U << EXTI_EXTICR1_EXTI2_PI_Pos)      /*!< 0x00080000 */
15397 #define EXTI_EXTICR1_EXTI2_PI         EXTI_EXTICR1_EXTI2_PI_Msk                /*!<PI[2] pin */
15398 #define EXTI_EXTICR1_EXTI2_PJ_Pos     (16U)
15399 #define EXTI_EXTICR1_EXTI2_PJ_Msk     (0x9U << EXTI_EXTICR1_EXTI2_PJ_Pos)      /*!< 0x00090000 */
15400 #define EXTI_EXTICR1_EXTI2_PJ         EXTI_EXTICR1_EXTI2_PJ_Msk                /*!<PJ[2] pin */
15401 #define EXTI_EXTICR1_EXTI2_PK_Pos     (17U)
15402 #define EXTI_EXTICR1_EXTI2_PK_Msk     (0x5U << EXTI_EXTICR1_EXTI2_PK_Pos)      /*!< 0x000A0000 */
15403 #define EXTI_EXTICR1_EXTI2_PK         EXTI_EXTICR1_EXTI2_PK_Msk                /*!<PK[2] pin */
15404 #define EXTI_EXTICR1_EXTI2_PZ_Pos     (16U)
15405 #define EXTI_EXTICR1_EXTI2_PZ_Msk     (0xBU << EXTI_EXTICR1_EXTI2_PZ_Pos)      /*!< 0x000B0000 */
15406 #define EXTI_EXTICR1_EXTI2_PZ         EXTI_EXTICR1_EXTI2_PZ_Msk                /*!<PZ[2] pin */
15407 
15408 /**
15409   * @brief   EXTI3 configuration
15410   */
15411 #define EXTI_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000)                   /*!<PA[3] pin */
15412 #define EXTI_EXTICR1_EXTI3_PB_Pos     (24U)
15413 #define EXTI_EXTICR1_EXTI3_PB_Msk     (0x1U << EXTI_EXTICR1_EXTI3_PB_Pos)      /*!< 0x01000000 */
15414 #define EXTI_EXTICR1_EXTI3_PB         EXTI_EXTICR1_EXTI3_PB_Msk                /*!<PB[3] pin */
15415 #define EXTI_EXTICR1_EXTI3_PC_Pos     (25U)
15416 #define EXTI_EXTICR1_EXTI3_PC_Msk     (0x1U << EXTI_EXTICR1_EXTI3_PC_Pos)      /*!< 0x02000000 */
15417 #define EXTI_EXTICR1_EXTI3_PC         EXTI_EXTICR1_EXTI3_PC_Msk                /*!<PC[3] pin */
15418 #define EXTI_EXTICR1_EXTI3_PD_Pos     (24U)
15419 #define EXTI_EXTICR1_EXTI3_PD_Msk     (0x3U << EXTI_EXTICR1_EXTI3_PD_Pos)      /*!< 0x03000000 */
15420 #define EXTI_EXTICR1_EXTI3_PD         EXTI_EXTICR1_EXTI3_PD_Msk                /*!<PD[3] pin */
15421 #define EXTI_EXTICR1_EXTI3_PE_Pos     (26U)
15422 #define EXTI_EXTICR1_EXTI3_PE_Msk     (0x1U << EXTI_EXTICR1_EXTI3_PE_Pos)      /*!< 0x04000000 */
15423 #define EXTI_EXTICR1_EXTI3_PE         EXTI_EXTICR1_EXTI3_PE_Msk                /*!<PE[3] pin */
15424 #define EXTI_EXTICR1_EXTI3_PF_Pos     (24U)
15425 #define EXTI_EXTICR1_EXTI3_PF_Msk     (0x5U << EXTI_EXTICR1_EXTI3_PF_Pos)      /*!< 0x05000000 */
15426 #define EXTI_EXTICR1_EXTI3_PF         EXTI_EXTICR1_EXTI3_PF_Msk                /*!<PF[3] pin */
15427 #define EXTI_EXTICR1_EXTI3_PG_Pos     (25U)
15428 #define EXTI_EXTICR1_EXTI3_PG_Msk     (0x3U << EXTI_EXTICR1_EXTI3_PG_Pos)      /*!< 0x06000000 */
15429 #define EXTI_EXTICR1_EXTI3_PG         EXTI_EXTICR1_EXTI3_PG_Msk                /*!<PG[3] pin */
15430 #define EXTI_EXTICR1_EXTI3_PH_Pos     (24U)
15431 #define EXTI_EXTICR1_EXTI3_PH_Msk     (0x7U << EXTI_EXTICR1_EXTI3_PH_Pos)      /*!< 0x07000000 */
15432 #define EXTI_EXTICR1_EXTI3_PH         EXTI_EXTICR1_EXTI3_PH_Msk                /*!<PH[3] pin */
15433 #define EXTI_EXTICR1_EXTI3_PI_Pos     (27U)
15434 #define EXTI_EXTICR1_EXTI3_PI_Msk     (0x1U << EXTI_EXTICR1_EXTI3_PI_Pos)      /*!< 0x08000000 */
15435 #define EXTI_EXTICR1_EXTI3_PI         EXTI_EXTICR1_EXTI3_PI_Msk                /*!<PI[3] pin */
15436 #define EXTI_EXTICR1_EXTI3_PJ_Pos     (24U)
15437 #define EXTI_EXTICR1_EXTI3_PJ_Msk     (0x9U << EXTI_EXTICR1_EXTI3_PJ_Pos)      /*!< 0x09000000 */
15438 #define EXTI_EXTICR1_EXTI3_PJ         EXTI_EXTICR1_EXTI3_PJ_Msk                /*!<PJ[3] pin */
15439 #define EXTI_EXTICR1_EXTI3_PK_Pos     (25U)
15440 #define EXTI_EXTICR1_EXTI3_PK_Msk     (0x5U << EXTI_EXTICR1_EXTI3_PK_Pos)      /*!< 0x0A000000 */
15441 #define EXTI_EXTICR1_EXTI3_PK         EXTI_EXTICR1_EXTI3_PK_Msk                /*!<PK[3] pin */
15442 #define EXTI_EXTICR1_EXTI3_PZ_Pos     (24U)
15443 #define EXTI_EXTICR1_EXTI3_PZ_Msk     (0xBU << EXTI_EXTICR1_EXTI3_PZ_Pos)      /*!< 0x0B000000 */
15444 #define EXTI_EXTICR1_EXTI3_PZ         EXTI_EXTICR1_EXTI3_PZ_Msk                /*!<PZ[3] pin */
15445 
15446 
15447 /*****************  Bit definition for EXTI_EXTICR2 register  ***************/
15448 #define EXTI_EXTICR2_EXTI4_Pos        (0U)
15449 #define EXTI_EXTICR2_EXTI4_Msk        (0x0FU << EXTI_EXTICR2_EXTI4_Pos)        /*!< 0x000000F */
15450 #define EXTI_EXTICR2_EXTI4            EXTI_EXTICR2_EXTI4_Msk                   /*!<EXTI 4 configuration */
15451 #define EXTI_EXTICR2_EXTI5_Pos        (8U)
15452 #define EXTI_EXTICR2_EXTI5_Msk        (0x0FU << EXTI_EXTICR2_EXTI5_Pos)        /*!< 0x00000F00 */
15453 #define EXTI_EXTICR2_EXTI5            EXTI_EXTICR2_EXTI5_Msk                   /*!<EXTI 5 configuration */
15454 #define EXTI_EXTICR2_EXTI6_Pos        (16U)
15455 #define EXTI_EXTICR2_EXTI6_Msk        (0x0FU << EXTI_EXTICR2_EXTI6_Pos)        /*!< 0x000F0000 */
15456 #define EXTI_EXTICR2_EXTI6            EXTI_EXTICR2_EXTI6_Msk                   /*!<EXTI 6 configuration */
15457 #define EXTI_EXTICR2_EXTI7_Pos        (24U)
15458 #define EXTI_EXTICR2_EXTI7_Msk        (0x0FU << EXTI_EXTICR2_EXTI7_Pos)        /*!< 0x0F000000 */
15459 #define EXTI_EXTICR2_EXTI7            EXTI_EXTICR2_EXTI7_Msk                   /*!<EXTI 7 configuration */
15460 
15461 /**
15462   * @brief   EXTI4 configuration
15463   */
15464 #define EXTI_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000)                   /*!<PA[4] pin */
15465 #define EXTI_EXTICR2_EXTI4_PB_Pos     (0U)
15466 #define EXTI_EXTICR2_EXTI4_PB_Msk     (0x1U << EXTI_EXTICR2_EXTI4_PB_Pos)      /*!< 0x00000001 */
15467 #define EXTI_EXTICR2_EXTI4_PB         EXTI_EXTICR2_EXTI4_PB_Msk                /*!<PB[4] pin */
15468 #define EXTI_EXTICR2_EXTI4_PC_Pos     (1U)
15469 #define EXTI_EXTICR2_EXTI4_PC_Msk     (0x1U << EXTI_EXTICR2_EXTI4_PC_Pos)      /*!< 0x00000002 */
15470 #define EXTI_EXTICR2_EXTI4_PC         EXTI_EXTICR2_EXTI4_PC_Msk                /*!<PC[4] pin */
15471 #define EXTI_EXTICR2_EXTI4_PD_Pos     (0U)
15472 #define EXTI_EXTICR2_EXTI4_PD_Msk     (0x3U << EXTI_EXTICR2_EXTI4_PD_Pos)      /*!< 0x00000003 */
15473 #define EXTI_EXTICR2_EXTI4_PD         EXTI_EXTICR2_EXTI4_PD_Msk                /*!<PD[4] pin */
15474 #define EXTI_EXTICR2_EXTI4_PE_Pos     (2U)
15475 #define EXTI_EXTICR2_EXTI4_PE_Msk     (0x1U << EXTI_EXTICR2_EXTI4_PE_Pos)      /*!< 0x00000004 */
15476 #define EXTI_EXTICR2_EXTI4_PE         EXTI_EXTICR2_EXTI4_PE_Msk                /*!<PE[4] pin */
15477 #define EXTI_EXTICR2_EXTI4_PF_Pos     (0U)
15478 #define EXTI_EXTICR2_EXTI4_PF_Msk     (0x5U << EXTI_EXTICR2_EXTI4_PF_Pos)      /*!< 0x00000005 */
15479 #define EXTI_EXTICR2_EXTI4_PF         EXTI_EXTICR2_EXTI4_PF_Msk                /*!<PF[4] pin */
15480 #define EXTI_EXTICR2_EXTI4_PG_Pos     (1U)
15481 #define EXTI_EXTICR2_EXTI4_PG_Msk     (0x3U << EXTI_EXTICR2_EXTI4_PG_Pos)      /*!< 0x00000006 */
15482 #define EXTI_EXTICR2_EXTI4_PG         EXTI_EXTICR2_EXTI4_PG_Msk                /*!<PG[4] pin */
15483 #define EXTI_EXTICR2_EXTI4_PH_Pos     (0U)
15484 #define EXTI_EXTICR2_EXTI4_PH_Msk     (0x7U << EXTI_EXTICR2_EXTI4_PH_Pos)      /*!< 0x00000007 */
15485 #define EXTI_EXTICR2_EXTI4_PH         EXTI_EXTICR2_EXTI4_PH_Msk                /*!<PH[4] pin */
15486 #define EXTI_EXTICR2_EXTI4_PI_Pos     (3U)
15487 #define EXTI_EXTICR2_EXTI4_PI_Msk     (0x1U << EXTI_EXTICR2_EXTI4_PI_Pos)      /*!< 0x00000008 */
15488 #define EXTI_EXTICR2_EXTI4_PI         EXTI_EXTICR2_EXTI4_PI_Msk                /*!<PI[4] pin */
15489 #define EXTI_EXTICR2_EXTI4_PJ_Pos     (0U)
15490 #define EXTI_EXTICR2_EXTI4_PJ_Msk     (0x9U << EXTI_EXTICR2_EXTI4_PJ_Pos)      /*!< 0x00000009 */
15491 #define EXTI_EXTICR2_EXTI4_PJ         EXTI_EXTICR2_EXTI4_PJ_Msk                /*!<PJ[4] pin */
15492 #define EXTI_EXTICR2_EXTI4_PK_Pos     (1U)
15493 #define EXTI_EXTICR2_EXTI4_PK_Msk     (0x5U << EXTI_EXTICR2_EXTI4_PK_Pos)      /*!< 0x0000000A */
15494 #define EXTI_EXTICR2_EXTI4_PK         EXTI_EXTICR2_EXTI4_PK_Msk                /*!<PK[4] pin */
15495 #define EXTI_EXTICR2_EXTI4_PZ_Pos     (0U)
15496 #define EXTI_EXTICR2_EXTI4_PZ_Msk     (0xBU << EXTI_EXTICR2_EXTI4_PZ_Pos)      /*!< 0x0000000B */
15497 #define EXTI_EXTICR2_EXTI4_PZ         EXTI_EXTICR2_EXTI4_PZ_Msk                /*!<PZ[4] pin */
15498 
15499 /**
15500   * @brief   EXTI5 configuration
15501   */
15502 #define EXTI_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000)                   /*!<PA[5] pin */
15503 #define EXTI_EXTICR2_EXTI5_PB_Pos     (8U)
15504 #define EXTI_EXTICR2_EXTI5_PB_Msk     (0x1U << EXTI_EXTICR2_EXTI5_PB_Pos)      /*!< 0x00000100 */
15505 #define EXTI_EXTICR2_EXTI5_PB         EXTI_EXTICR2_EXTI5_PB_Msk                /*!<PB[5] pin */
15506 #define EXTI_EXTICR2_EXTI5_PC_Pos     (9U)
15507 #define EXTI_EXTICR2_EXTI5_PC_Msk     (0x1U << EXTI_EXTICR2_EXTI5_PC_Pos)      /*!< 0x00000200 */
15508 #define EXTI_EXTICR2_EXTI5_PC         EXTI_EXTICR2_EXTI5_PC_Msk                /*!<PC[5] pin */
15509 #define EXTI_EXTICR2_EXTI5_PD_Pos     (8U)
15510 #define EXTI_EXTICR2_EXTI5_PD_Msk     (0x3U << EXTI_EXTICR2_EXTI5_PD_Pos)      /*!< 0x00000300 */
15511 #define EXTI_EXTICR2_EXTI5_PD         EXTI_EXTICR2_EXTI5_PD_Msk                /*!<PD[5] pin */
15512 #define EXTI_EXTICR2_EXTI5_PE_Pos     (10U)
15513 #define EXTI_EXTICR2_EXTI5_PE_Msk     (0x1U << EXTI_EXTICR2_EXTI5_PE_Pos)      /*!< 0x00000400 */
15514 #define EXTI_EXTICR2_EXTI5_PE         EXTI_EXTICR2_EXTI5_PE_Msk                /*!<PE[5] pin */
15515 #define EXTI_EXTICR2_EXTI5_PF_Pos     (8U)
15516 #define EXTI_EXTICR2_EXTI5_PF_Msk     (0x5U << EXTI_EXTICR2_EXTI5_PF_Pos)      /*!< 0x00000500 */
15517 #define EXTI_EXTICR2_EXTI5_PF         EXTI_EXTICR2_EXTI5_PF_Msk                /*!<PF[5] pin */
15518 #define EXTI_EXTICR2_EXTI5_PG_Pos     (9U)
15519 #define EXTI_EXTICR2_EXTI5_PG_Msk     (0x3U << EXTI_EXTICR2_EXTI5_PG_Pos)      /*!< 0x00000600 */
15520 #define EXTI_EXTICR2_EXTI5_PG         EXTI_EXTICR2_EXTI5_PG_Msk                /*!<PG[5] pin */
15521 #define EXTI_EXTICR2_EXTI5_PH_Pos     (8U)
15522 #define EXTI_EXTICR2_EXTI5_PH_Msk     (0x7U << EXTI_EXTICR2_EXTI5_PH_Pos)      /*!< 0x00000700 */
15523 #define EXTI_EXTICR2_EXTI5_PH         EXTI_EXTICR2_EXTI5_PH_Msk                /*!<PH[5] pin */
15524 #define EXTI_EXTICR2_EXTI5_PI_Pos     (11U)
15525 #define EXTI_EXTICR2_EXTI5_PI_Msk     (0x1U << EXTI_EXTICR2_EXTI5_PI_Pos)      /*!< 0x00000800 */
15526 #define EXTI_EXTICR2_EXTI5_PI         EXTI_EXTICR2_EXTI5_PI_Msk                /*!<PI[5] pin */
15527 #define EXTI_EXTICR2_EXTI5_PJ_Pos     (8U)
15528 #define EXTI_EXTICR2_EXTI5_PJ_Msk     (0x9U << EXTI_EXTICR2_EXTI5_PJ_Pos)      /*!< 0x00000900 */
15529 #define EXTI_EXTICR2_EXTI5_PJ         EXTI_EXTICR2_EXTI5_PJ_Msk                /*!<PJ[5] pin */
15530 #define EXTI_EXTICR2_EXTI5_PK_Pos     (9U)
15531 #define EXTI_EXTICR2_EXTI5_PK_Msk     (0x5U << EXTI_EXTICR2_EXTI5_PK_Pos)      /*!< 0x00000A00 */
15532 #define EXTI_EXTICR2_EXTI5_PK         EXTI_EXTICR2_EXTI5_PK_Msk                /*!<PK[5] pin */
15533 #define EXTI_EXTICR2_EXTI5_PZ_Pos     (8U)
15534 #define EXTI_EXTICR2_EXTI5_PZ_Msk     (0xBU << EXTI_EXTICR2_EXTI5_PZ_Pos)      /*!< 0x00000B00 */
15535 #define EXTI_EXTICR2_EXTI5_PZ         EXTI_EXTICR2_EXTI5_PZ_Msk                /*!<PZ[5] pin */
15536 
15537 /**
15538   * @brief   EXTI6 configuration
15539   */
15540 #define EXTI_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000)                   /*!<PA[6] pin */
15541 #define EXTI_EXTICR2_EXTI6_PB_Pos     (16U)
15542 #define EXTI_EXTICR2_EXTI6_PB_Msk     (0x1U << EXTI_EXTICR2_EXTI6_PB_Pos)      /*!< 0x00010000 */
15543 #define EXTI_EXTICR2_EXTI6_PB         EXTI_EXTICR2_EXTI6_PB_Msk                /*!<PB[6] pin */
15544 #define EXTI_EXTICR2_EXTI6_PC_Pos     (17U)
15545 #define EXTI_EXTICR2_EXTI6_PC_Msk     (0x1U << EXTI_EXTICR2_EXTI6_PC_Pos)      /*!< 0x00020000 */
15546 #define EXTI_EXTICR2_EXTI6_PC         EXTI_EXTICR2_EXTI6_PC_Msk                /*!<PC[6] pin */
15547 #define EXTI_EXTICR2_EXTI6_PD_Pos     (16U)
15548 #define EXTI_EXTICR2_EXTI6_PD_Msk     (0x3U << EXTI_EXTICR2_EXTI6_PD_Pos)      /*!< 0x00030000 */
15549 #define EXTI_EXTICR2_EXTI6_PD         EXTI_EXTICR2_EXTI6_PD_Msk                /*!<PD[6] pin */
15550 #define EXTI_EXTICR2_EXTI6_PE_Pos     (18U)
15551 #define EXTI_EXTICR2_EXTI6_PE_Msk     (0x1U << EXTI_EXTICR2_EXTI6_PE_Pos)      /*!< 0x00040000 */
15552 #define EXTI_EXTICR2_EXTI6_PE         EXTI_EXTICR2_EXTI6_PE_Msk                /*!<PE[6] pin */
15553 #define EXTI_EXTICR2_EXTI6_PF_Pos     (16U)
15554 #define EXTI_EXTICR2_EXTI6_PF_Msk     (0x5U << EXTI_EXTICR2_EXTI6_PF_Pos)      /*!< 0x00050000 */
15555 #define EXTI_EXTICR2_EXTI6_PF         EXTI_EXTICR2_EXTI6_PF_Msk                /*!<PF[6] pin */
15556 #define EXTI_EXTICR2_EXTI6_PG_Pos     (17U)
15557 #define EXTI_EXTICR2_EXTI6_PG_Msk     (0x3U << EXTI_EXTICR2_EXTI6_PG_Pos)      /*!< 0x00060000 */
15558 #define EXTI_EXTICR2_EXTI6_PG         EXTI_EXTICR2_EXTI6_PG_Msk                /*!<PG[6] pin */
15559 #define EXTI_EXTICR2_EXTI6_PH_Pos     (16U)
15560 #define EXTI_EXTICR2_EXTI6_PH_Msk     (0x7U << EXTI_EXTICR2_EXTI6_PH_Pos)      /*!< 0x00070000 */
15561 #define EXTI_EXTICR2_EXTI6_PH         EXTI_EXTICR2_EXTI6_PH_Msk                /*!<PH[6] pin */
15562 #define EXTI_EXTICR2_EXTI6_PI_Pos     (19U)
15563 #define EXTI_EXTICR2_EXTI6_PI_Msk     (0x1U << EXTI_EXTICR2_EXTI6_PI_Pos)      /*!< 0x00080000 */
15564 #define EXTI_EXTICR2_EXTI6_PI         EXTI_EXTICR2_EXTI6_PI_Msk                /*!<PI[6] pin */
15565 #define EXTI_EXTICR2_EXTI6_PJ_Pos     (16U)
15566 #define EXTI_EXTICR2_EXTI6_PJ_Msk     (0x9U << EXTI_EXTICR2_EXTI6_PJ_Pos)      /*!< 0x00090000 */
15567 #define EXTI_EXTICR2_EXTI6_PJ         EXTI_EXTICR2_EXTI6_PJ_Msk                /*!<PJ[6] pin */
15568 #define EXTI_EXTICR2_EXTI6_PK_Pos     (17U)
15569 #define EXTI_EXTICR2_EXTI6_PK_Msk     (0x5U << EXTI_EXTICR2_EXTI6_PK_Pos)      /*!< 0x000A0000 */
15570 #define EXTI_EXTICR2_EXTI6_PK         EXTI_EXTICR2_EXTI6_PK_Msk                /*!<PK[6] pin */
15571 #define EXTI_EXTICR2_EXTI6_PZ_Pos     (16U)
15572 #define EXTI_EXTICR2_EXTI6_PZ_Msk     (0xBU << EXTI_EXTICR2_EXTI6_PZ_Pos)      /*!< 0x000B0000 */
15573 #define EXTI_EXTICR2_EXTI6_PZ         EXTI_EXTICR2_EXTI6_PZ_Msk                /*!<PZ[6] pin */
15574 
15575 /**
15576   * @brief   EXTI7 configuration
15577   */
15578 #define EXTI_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000)                   /*!<PA[7] pin */
15579 #define EXTI_EXTICR2_EXTI7_PB_Pos     (24U)
15580 #define EXTI_EXTICR2_EXTI7_PB_Msk     (0x1U << EXTI_EXTICR2_EXTI7_PB_Pos)      /*!< 0x01000000 */
15581 #define EXTI_EXTICR2_EXTI7_PB         EXTI_EXTICR2_EXTI7_PB_Msk                /*!<PB[7] pin */
15582 #define EXTI_EXTICR2_EXTI7_PC_Pos     (25U)
15583 #define EXTI_EXTICR2_EXTI7_PC_Msk     (0x1U << EXTI_EXTICR2_EXTI7_PC_Pos)      /*!< 0x02000000 */
15584 #define EXTI_EXTICR2_EXTI7_PC         EXTI_EXTICR2_EXTI7_PC_Msk                /*!<PC[7] pin */
15585 #define EXTI_EXTICR2_EXTI7_PD_Pos     (24U)
15586 #define EXTI_EXTICR2_EXTI7_PD_Msk     (0x3U << EXTI_EXTICR2_EXTI7_PD_Pos)      /*!< 0x03000000 */
15587 #define EXTI_EXTICR2_EXTI7_PD         EXTI_EXTICR2_EXTI7_PD_Msk                /*!<PD[7] pin */
15588 #define EXTI_EXTICR2_EXTI7_PE_Pos     (26U)
15589 #define EXTI_EXTICR2_EXTI7_PE_Msk     (0x1U << EXTI_EXTICR2_EXTI7_PE_Pos)      /*!< 0x04000000 */
15590 #define EXTI_EXTICR2_EXTI7_PE         EXTI_EXTICR2_EXTI7_PE_Msk                /*!<PE[7] pin */
15591 #define EXTI_EXTICR2_EXTI7_PF_Pos     (24U)
15592 #define EXTI_EXTICR2_EXTI7_PF_Msk     (0x5U << EXTI_EXTICR2_EXTI7_PF_Pos)      /*!< 0x05000000 */
15593 #define EXTI_EXTICR2_EXTI7_PF         EXTI_EXTICR2_EXTI7_PF_Msk                /*!<PF[7] pin */
15594 #define EXTI_EXTICR2_EXTI7_PG_Pos     (25U)
15595 #define EXTI_EXTICR2_EXTI7_PG_Msk     (0x3U << EXTI_EXTICR2_EXTI7_PG_Pos)      /*!< 0x06000000 */
15596 #define EXTI_EXTICR2_EXTI7_PG         EXTI_EXTICR2_EXTI7_PG_Msk                /*!<PG[7] pin */
15597 #define EXTI_EXTICR2_EXTI7_PH_Pos     (24U)
15598 #define EXTI_EXTICR2_EXTI7_PH_Msk     (0x7U << EXTI_EXTICR2_EXTI7_PH_Pos)      /*!< 0x07000000 */
15599 #define EXTI_EXTICR2_EXTI7_PH         EXTI_EXTICR2_EXTI7_PH_Msk                /*!<PH[7] pin */
15600 #define EXTI_EXTICR2_EXTI7_PI_Pos     (27U)
15601 #define EXTI_EXTICR2_EXTI7_PI_Msk     (0x1U << EXTI_EXTICR2_EXTI7_PI_Pos)      /*!< 0x08000000 */
15602 #define EXTI_EXTICR2_EXTI7_PI         EXTI_EXTICR2_EXTI7_PI_Msk                /*!<PI[7] pin */
15603 #define EXTI_EXTICR2_EXTI7_PJ_Pos     (24U)
15604 #define EXTI_EXTICR2_EXTI7_PJ_Msk     (0x9U << EXTI_EXTICR2_EXTI7_PJ_Pos)      /*!< 0x09000000 */
15605 #define EXTI_EXTICR2_EXTI7_PJ         EXTI_EXTICR2_EXTI7_PJ_Msk                /*!<PJ[7] pin */
15606 #define EXTI_EXTICR2_EXTI7_PK_Pos     (25U)
15607 #define EXTI_EXTICR2_EXTI7_PK_Msk     (0x5U << EXTI_EXTICR2_EXTI7_PK_Pos)      /*!< 0x0A000000 */
15608 #define EXTI_EXTICR2_EXTI7_PK         EXTI_EXTICR2_EXTI7_PK_Msk                /*!<PK[7] pin */
15609 #define EXTI_EXTICR2_EXTI7_PZ_Pos     (24U)
15610 #define EXTI_EXTICR2_EXTI7_PZ_Msk     (0xBU << EXTI_EXTICR2_EXTI7_PZ_Pos)      /*!< 0x0B000000 */
15611 #define EXTI_EXTICR2_EXTI7_PZ         EXTI_EXTICR2_EXTI7_PZ_Msk                /*!<PZ[7] pin */
15612 
15613 
15614 /*****************  Bit definition for EXTI_EXTICR3 register  ***************/
15615 #define EXTI_EXTICR3_EXTI8_Pos        (0U)
15616 #define EXTI_EXTICR3_EXTI8_Msk        (0x0FU << EXTI_EXTICR3_EXTI8_Pos)        /*!< 0x0000000F */
15617 #define EXTI_EXTICR3_EXTI8            EXTI_EXTICR3_EXTI8_Msk                   /*!<EXTI 8 configuration */
15618 #define EXTI_EXTICR3_EXTI9_Pos        (8U)
15619 #define EXTI_EXTICR3_EXTI9_Msk        (0x0FU << EXTI_EXTICR3_EXTI9_Pos)        /*!< 0x00000F00 */
15620 #define EXTI_EXTICR3_EXTI9            EXTI_EXTICR3_EXTI9_Msk                   /*!<EXTI 9 configuration */
15621 #define EXTI_EXTICR3_EXTI10_Pos       (16U)
15622 #define EXTI_EXTICR3_EXTI10_Msk       (0x0FU << EXTI_EXTICR3_EXTI10_Pos)       /*!< 0x000F0000 */
15623 #define EXTI_EXTICR3_EXTI10           EXTI_EXTICR3_EXTI10_Msk                  /*!<EXTI 10 configuration */
15624 #define EXTI_EXTICR3_EXTI11_Pos       (24U)
15625 #define EXTI_EXTICR3_EXTI11_Msk       (0x0FU << EXTI_EXTICR3_EXTI11_Pos)       /*!< 0x0F000000 */
15626 #define EXTI_EXTICR3_EXTI11           EXTI_EXTICR3_EXTI11_Msk                  /*!<EXTI 11 configuration */
15627 
15628 /**
15629   * @brief   EXTI8 configuration
15630   */
15631 #define EXTI_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000)                   /*!<PA[8] pin */
15632 #define EXTI_EXTICR3_EXTI8_PB_Pos     (0U)
15633 #define EXTI_EXTICR3_EXTI8_PB_Msk     (0x1U << EXTI_EXTICR3_EXTI8_PB_Pos)      /*!< 0x00000001 */
15634 #define EXTI_EXTICR3_EXTI8_PB         EXTI_EXTICR3_EXTI8_PB_Msk                /*!<PB[8] pin */
15635 #define EXTI_EXTICR3_EXTI8_PC_Pos     (1U)
15636 #define EXTI_EXTICR3_EXTI8_PC_Msk     (0x1U << EXTI_EXTICR3_EXTI8_PC_Pos)      /*!< 0x00000002 */
15637 #define EXTI_EXTICR3_EXTI8_PC         EXTI_EXTICR3_EXTI8_PC_Msk                /*!<PC[8] pin */
15638 #define EXTI_EXTICR3_EXTI8_PD_Pos     (0U)
15639 #define EXTI_EXTICR3_EXTI8_PD_Msk     (0x3U << EXTI_EXTICR3_EXTI8_PD_Pos)      /*!< 0x00000003 */
15640 #define EXTI_EXTICR3_EXTI8_PD         EXTI_EXTICR3_EXTI8_PD_Msk                /*!<PD[8] pin */
15641 #define EXTI_EXTICR3_EXTI8_PE_Pos     (2U)
15642 #define EXTI_EXTICR3_EXTI8_PE_Msk     (0x1U << EXTI_EXTICR3_EXTI8_PE_Pos)      /*!< 0x00000004 */
15643 #define EXTI_EXTICR3_EXTI8_PE         EXTI_EXTICR3_EXTI8_PE_Msk                /*!<PE[8] pin */
15644 #define EXTI_EXTICR3_EXTI8_PF_Pos     (0U)
15645 #define EXTI_EXTICR3_EXTI8_PF_Msk     (0x5U << EXTI_EXTICR3_EXTI8_PF_Pos)      /*!< 0x00000005 */
15646 #define EXTI_EXTICR3_EXTI8_PF         EXTI_EXTICR3_EXTI8_PF_Msk                /*!<PF[8] pin */
15647 #define EXTI_EXTICR3_EXTI8_PG_Pos     (1U)
15648 #define EXTI_EXTICR3_EXTI8_PG_Msk     (0x3U << EXTI_EXTICR3_EXTI8_PG_Pos)      /*!< 0x00000006 */
15649 #define EXTI_EXTICR3_EXTI8_PG         EXTI_EXTICR3_EXTI8_PG_Msk                /*!<PG[8] pin */
15650 #define EXTI_EXTICR3_EXTI8_PH_Pos     (0U)
15651 #define EXTI_EXTICR3_EXTI8_PH_Msk     (0x7U << EXTI_EXTICR3_EXTI8_PH_Pos)      /*!< 0x00000007 */
15652 #define EXTI_EXTICR3_EXTI8_PH         EXTI_EXTICR3_EXTI8_PH_Msk                /*!<PH[8] pin */
15653 #define EXTI_EXTICR3_EXTI8_PI_Pos     (3U)
15654 #define EXTI_EXTICR3_EXTI8_PI_Msk     (0x1U << EXTI_EXTICR3_EXTI8_PI_Pos)      /*!< 0x00000008 */
15655 #define EXTI_EXTICR3_EXTI8_PI         EXTI_EXTICR3_EXTI8_PI_Msk                /*!<PI[8] pin */
15656 #define EXTI_EXTICR3_EXTI8_PJ_Pos     (0U)
15657 #define EXTI_EXTICR3_EXTI8_PJ_Msk     (0x9U << EXTI_EXTICR3_EXTI8_PJ_Pos)      /*!< 0x00000009 */
15658 #define EXTI_EXTICR3_EXTI8_PJ         EXTI_EXTICR3_EXTI8_PJ_Msk                /*!<PJ[8] pin */
15659 
15660 /**
15661   * @brief   EXTI9 configuration
15662   */
15663 #define EXTI_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000)                   /*!<PA[9] pin */
15664 #define EXTI_EXTICR3_EXTI9_PB_Pos     (8U)
15665 #define EXTI_EXTICR3_EXTI9_PB_Msk     (0x1U << EXTI_EXTICR3_EXTI9_PB_Pos)      /*!< 0x00000100 */
15666 #define EXTI_EXTICR3_EXTI9_PB         EXTI_EXTICR3_EXTI9_PB_Msk                /*!<PB[9] pin */
15667 #define EXTI_EXTICR3_EXTI9_PC_Pos     (9U)
15668 #define EXTI_EXTICR3_EXTI9_PC_Msk     (0x1U << EXTI_EXTICR3_EXTI9_PC_Pos)      /*!< 0x00000200 */
15669 #define EXTI_EXTICR3_EXTI9_PC         EXTI_EXTICR3_EXTI9_PC_Msk                /*!<PC[9] pin */
15670 #define EXTI_EXTICR3_EXTI9_PD_Pos     (8U)
15671 #define EXTI_EXTICR3_EXTI9_PD_Msk     (0x3U << EXTI_EXTICR3_EXTI9_PD_Pos)      /*!< 0x00000300 */
15672 #define EXTI_EXTICR3_EXTI9_PD         EXTI_EXTICR3_EXTI9_PD_Msk                /*!<PD[9] pin */
15673 #define EXTI_EXTICR3_EXTI9_PE_Pos     (10U)
15674 #define EXTI_EXTICR3_EXTI9_PE_Msk     (0x1U << EXTI_EXTICR3_EXTI9_PE_Pos)      /*!< 0x00000400 */
15675 #define EXTI_EXTICR3_EXTI9_PE         EXTI_EXTICR3_EXTI9_PE_Msk                /*!<PE[9] pin */
15676 #define EXTI_EXTICR3_EXTI9_PF_Pos     (8U)
15677 #define EXTI_EXTICR3_EXTI9_PF_Msk     (0x5U << EXTI_EXTICR3_EXTI9_PF_Pos)      /*!< 0x00000500 */
15678 #define EXTI_EXTICR3_EXTI9_PF         EXTI_EXTICR3_EXTI9_PF_Msk                /*!<PF[9] pin */
15679 #define EXTI_EXTICR3_EXTI9_PG_Pos     (9U)
15680 #define EXTI_EXTICR3_EXTI9_PG_Msk     (0x3U << EXTI_EXTICR3_EXTI9_PG_Pos)      /*!< 0x00000600 */
15681 #define EXTI_EXTICR3_EXTI9_PG         EXTI_EXTICR3_EXTI9_PG_Msk                /*!<PG[9] pin */
15682 #define EXTI_EXTICR3_EXTI9_PH_Pos     (8U)
15683 #define EXTI_EXTICR3_EXTI9_PH_Msk     (0x7U << EXTI_EXTICR3_EXTI9_PH_Pos)      /*!< 0x00000700 */
15684 #define EXTI_EXTICR3_EXTI9_PH         EXTI_EXTICR3_EXTI9_PH_Msk                /*!<PH[9] pin */
15685 #define EXTI_EXTICR3_EXTI9_PI_Pos     (11U)
15686 #define EXTI_EXTICR3_EXTI9_PI_Msk     (0x1U << EXTI_EXTICR3_EXTI9_PI_Pos)      /*!< 0x00000800 */
15687 #define EXTI_EXTICR3_EXTI9_PI         EXTI_EXTICR3_EXTI9_PI_Msk                /*!<PI[9] pin */
15688 #define EXTI_EXTICR3_EXTI9_PJ_Pos     (8U)
15689 #define EXTI_EXTICR3_EXTI9_PJ_Msk     (0x9U << EXTI_EXTICR3_EXTI9_PJ_Pos)      /*!< 0x00000900 */
15690 #define EXTI_EXTICR3_EXTI9_PJ         EXTI_EXTICR3_EXTI9_PJ_Msk                /*!<PJ[9] pin */
15691 
15692 /**
15693   * @brief   EXTI10 configuration
15694   */
15695 #define EXTI_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000)                   /*!<PA[10] pin */
15696 #define EXTI_EXTICR3_EXTI10_PB_Pos    (16U)
15697 #define EXTI_EXTICR3_EXTI10_PB_Msk    (0x1U << EXTI_EXTICR3_EXTI10_PB_Pos)     /*!< 0x00010000 */
15698 #define EXTI_EXTICR3_EXTI10_PB        EXTI_EXTICR3_EXTI10_PB_Msk               /*!<PB[10] pin */
15699 #define EXTI_EXTICR3_EXTI10_PC_Pos    (17U)
15700 #define EXTI_EXTICR3_EXTI10_PC_Msk    (0x1U << EXTI_EXTICR3_EXTI10_PC_Pos)     /*!< 0x00020000 */
15701 #define EXTI_EXTICR3_EXTI10_PC        EXTI_EXTICR3_EXTI10_PC_Msk               /*!<PC[10] pin */
15702 #define EXTI_EXTICR3_EXTI10_PD_Pos    (16U)
15703 #define EXTI_EXTICR3_EXTI10_PD_Msk    (0x3U << EXTI_EXTICR3_EXTI10_PD_Pos)     /*!< 0x00030000 */
15704 #define EXTI_EXTICR3_EXTI10_PD        EXTI_EXTICR3_EXTI10_PD_Msk               /*!<PD[10] pin */
15705 #define EXTI_EXTICR3_EXTI10_PE_Pos    (18U)
15706 #define EXTI_EXTICR3_EXTI10_PE_Msk    (0x1U << EXTI_EXTICR3_EXTI10_PE_Pos)     /*!< 0x00040000 */
15707 #define EXTI_EXTICR3_EXTI10_PE        EXTI_EXTICR3_EXTI10_PE_Msk               /*!<PE[10] pin */
15708 #define EXTI_EXTICR3_EXTI10_PF_Pos    (16U)
15709 #define EXTI_EXTICR3_EXTI10_PF_Msk    (0x5U << EXTI_EXTICR3_EXTI10_PF_Pos)     /*!< 0x00050000 */
15710 #define EXTI_EXTICR3_EXTI10_PF        EXTI_EXTICR3_EXTI10_PF_Msk               /*!<PF[10] pin */
15711 #define EXTI_EXTICR3_EXTI10_PG_Pos    (17U)
15712 #define EXTI_EXTICR3_EXTI10_PG_Msk    (0x3U << EXTI_EXTICR3_EXTI10_PG_Pos)     /*!< 0x00060000 */
15713 #define EXTI_EXTICR3_EXTI10_PG        EXTI_EXTICR3_EXTI10_PG_Msk               /*!<PG[10] pin */
15714 #define EXTI_EXTICR3_EXTI10_PH_Pos    (16U)
15715 #define EXTI_EXTICR3_EXTI10_PH_Msk    (0x7U << EXTI_EXTICR3_EXTI10_PH_Pos)     /*!< 0x00070000 */
15716 #define EXTI_EXTICR3_EXTI10_PH        EXTI_EXTICR3_EXTI10_PH_Msk               /*!<PH[10] pin */
15717 #define EXTI_EXTICR3_EXTI10_PI_Pos    (19U)
15718 #define EXTI_EXTICR3_EXTI10_PI_Msk    (0x1U << EXTI_EXTICR3_EXTI10_PI_Pos)     /*!< 0x00080000 */
15719 #define EXTI_EXTICR3_EXTI10_PI        EXTI_EXTICR3_EXTI10_PI_Msk               /*!<PI[10] pin */
15720 #define EXTI_EXTICR3_EXTI10_PJ_Pos    (16U)
15721 #define EXTI_EXTICR3_EXTI10_PJ_Msk    (0x9U << EXTI_EXTICR3_EXTI10_PJ_Pos)     /*!< 0x00090000 */
15722 #define EXTI_EXTICR3_EXTI10_PJ        EXTI_EXTICR3_EXTI10_PJ_Msk               /*!<PJ[10] pin */
15723 
15724 /**
15725   * @brief   EXTI11 configuration
15726   */
15727 #define EXTI_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000)                   /*!<PA[11] pin */
15728 #define EXTI_EXTICR3_EXTI11_PB_Pos    (24U)
15729 #define EXTI_EXTICR3_EXTI11_PB_Msk    (0x1U << EXTI_EXTICR3_EXTI11_PB_Pos)     /*!< 0x01000000 */
15730 #define EXTI_EXTICR3_EXTI11_PB        EXTI_EXTICR3_EXTI11_PB_Msk               /*!<PB[11] pin */
15731 #define EXTI_EXTICR3_EXTI11_PC_Pos    (25U)
15732 #define EXTI_EXTICR3_EXTI11_PC_Msk    (0x1U << EXTI_EXTICR3_EXTI11_PC_Pos)     /*!< 0x02000000 */
15733 #define EXTI_EXTICR3_EXTI11_PC        EXTI_EXTICR3_EXTI11_PC_Msk               /*!<PC[11] pin */
15734 #define EXTI_EXTICR3_EXTI11_PD_Pos    (24U)
15735 #define EXTI_EXTICR3_EXTI11_PD_Msk    (0x3U << EXTI_EXTICR3_EXTI11_PD_Pos)     /*!< 0x03000000 */
15736 #define EXTI_EXTICR3_EXTI11_PD        EXTI_EXTICR3_EXTI11_PD_Msk               /*!<PD[11] pin */
15737 #define EXTI_EXTICR3_EXTI11_PE_Pos    (26U)
15738 #define EXTI_EXTICR3_EXTI11_PE_Msk    (0x1U << EXTI_EXTICR3_EXTI11_PE_Pos)     /*!< 0x04000000 */
15739 #define EXTI_EXTICR3_EXTI11_PE        EXTI_EXTICR3_EXTI11_PE_Msk               /*!<PE[11] pin */
15740 #define EXTI_EXTICR3_EXTI11_PF_Pos    (24U)
15741 #define EXTI_EXTICR3_EXTI11_PF_Msk    (0x5U << EXTI_EXTICR3_EXTI11_PF_Pos)     /*!< 0x05000000 */
15742 #define EXTI_EXTICR3_EXTI11_PF        EXTI_EXTICR3_EXTI11_PF_Msk               /*!<PF[11] pin */
15743 #define EXTI_EXTICR3_EXTI11_PG_Pos    (25U)
15744 #define EXTI_EXTICR3_EXTI11_PG_Msk    (0x3U << EXTI_EXTICR3_EXTI11_PG_Pos)     /*!< 0x06000000 */
15745 #define EXTI_EXTICR3_EXTI11_PG        EXTI_EXTICR3_EXTI11_PG_Msk               /*!<PG[11] pin */
15746 #define EXTI_EXTICR3_EXTI11_PH_Pos    (24U)
15747 #define EXTI_EXTICR3_EXTI11_PH_Msk    (0x7U << EXTI_EXTICR3_EXTI11_PH_Pos)     /*!< 0x07000000 */
15748 #define EXTI_EXTICR3_EXTI11_PH        EXTI_EXTICR3_EXTI11_PH_Msk               /*!<PH[11] pin */
15749 #define EXTI_EXTICR3_EXTI11_PI_Pos    (27U)
15750 #define EXTI_EXTICR3_EXTI11_PI_Msk    (0x1U << EXTI_EXTICR3_EXTI11_PI_Pos)     /*!< 0x08000000 */
15751 #define EXTI_EXTICR3_EXTI11_PI        EXTI_EXTICR3_EXTI11_PI_Msk               /*!<PI[11] pin */
15752 #define EXTI_EXTICR3_EXTI11_PJ_Pos    (24U)
15753 #define EXTI_EXTICR3_EXTI11_PJ_Msk    (0x9U << EXTI_EXTICR3_EXTI11_PJ_Pos)     /*!< 0x09000000 */
15754 #define EXTI_EXTICR3_EXTI11_PJ        EXTI_EXTICR3_EXTI11_PJ_Msk               /*!<PJ[11] pin */
15755 
15756 
15757 /*****************  Bit definition for EXTI_EXTICR4 register  ***************/
15758 #define EXTI_EXTICR4_EXTI12_Pos       (0U)
15759 #define EXTI_EXTICR4_EXTI12_Msk       (0x0FU << EXTI_EXTICR4_EXTI12_Pos)       /*!< 0x0000000F */
15760 #define EXTI_EXTICR4_EXTI12           EXTI_EXTICR4_EXTI12_Msk                  /*!<EXTI 12 configuration */
15761 #define EXTI_EXTICR4_EXTI13_Pos       (8U)
15762 #define EXTI_EXTICR4_EXTI13_Msk       (0x0FU << EXTI_EXTICR4_EXTI13_Pos)       /*!< 0x00000F00 */
15763 #define EXTI_EXTICR4_EXTI13           EXTI_EXTICR4_EXTI13_Msk                  /*!<EXTI 13 configuration */
15764 #define EXTI_EXTICR4_EXTI14_Pos       (16U)
15765 #define EXTI_EXTICR4_EXTI14_Msk       (0x0FU << EXTI_EXTICR4_EXTI14_Pos)       /*!< 0x000F0000 */
15766 #define EXTI_EXTICR4_EXTI14           EXTI_EXTICR4_EXTI14_Msk                  /*!<EXTI 14 configuration */
15767 #define EXTI_EXTICR4_EXTI15_Pos       (24U)
15768 #define EXTI_EXTICR4_EXTI15_Msk       (0x0FU << EXTI_EXTICR4_EXTI15_Pos)       /*!< 0x0F000000 */
15769 #define EXTI_EXTICR4_EXTI15           EXTI_EXTICR4_EXTI15_Msk                  /*!<EXTI 15 configuration */
15770 
15771 /**
15772   * @brief   EXTI12 configuration
15773   */
15774 #define EXTI_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000)                   /*!<PA[12] pin */
15775 #define EXTI_EXTICR4_EXTI12_PB_Pos    (0U)
15776 #define EXTI_EXTICR4_EXTI12_PB_Msk    (0x1U << EXTI_EXTICR4_EXTI12_PB_Pos)     /*!< 0x00000001 */
15777 #define EXTI_EXTICR4_EXTI12_PB        EXTI_EXTICR4_EXTI12_PB_Msk               /*!<PB[12] pin */
15778 #define EXTI_EXTICR4_EXTI12_PC_Pos    (1U)
15779 #define EXTI_EXTICR4_EXTI12_PC_Msk    (0x1U << EXTI_EXTICR4_EXTI12_PC_Pos)     /*!< 0x00000002 */
15780 #define EXTI_EXTICR4_EXTI12_PC        EXTI_EXTICR4_EXTI12_PC_Msk               /*!<PC[12] pin */
15781 #define EXTI_EXTICR4_EXTI12_PD_Pos    (0U)
15782 #define EXTI_EXTICR4_EXTI12_PD_Msk    (0x3U << EXTI_EXTICR4_EXTI12_PD_Pos)     /*!< 0x00000003 */
15783 #define EXTI_EXTICR4_EXTI12_PD        EXTI_EXTICR4_EXTI12_PD_Msk               /*!<PD[12] pin */
15784 #define EXTI_EXTICR4_EXTI12_PE_Pos    (2U)
15785 #define EXTI_EXTICR4_EXTI12_PE_Msk    (0x1U << EXTI_EXTICR4_EXTI12_PE_Pos)     /*!< 0x00000004 */
15786 #define EXTI_EXTICR4_EXTI12_PE        EXTI_EXTICR4_EXTI12_PE_Msk               /*!<PE[12] pin */
15787 #define EXTI_EXTICR4_EXTI12_PF_Pos    (0U)
15788 #define EXTI_EXTICR4_EXTI12_PF_Msk    (0x5U << EXTI_EXTICR4_EXTI12_PF_Pos)     /*!< 0x00000005 */
15789 #define EXTI_EXTICR4_EXTI12_PF        EXTI_EXTICR4_EXTI12_PF_Msk               /*!<PF[12] pin */
15790 #define EXTI_EXTICR4_EXTI12_PG_Pos    (1U)
15791 #define EXTI_EXTICR4_EXTI12_PG_Msk    (0x3U << EXTI_EXTICR4_EXTI12_PG_Pos)     /*!< 0x00000006 */
15792 #define EXTI_EXTICR4_EXTI12_PG        EXTI_EXTICR4_EXTI12_PG_Msk               /*!<PG[12] pin */
15793 #define EXTI_EXTICR4_EXTI12_PH_Pos    (0U)
15794 #define EXTI_EXTICR4_EXTI12_PH_Msk    (0x7U << EXTI_EXTICR4_EXTI12_PH_Pos)     /*!< 0x00000007 */
15795 #define EXTI_EXTICR4_EXTI12_PH        EXTI_EXTICR4_EXTI12_PH_Msk               /*!<PH[12] pin */
15796 #define EXTI_EXTICR4_EXTI12_PI_Pos    (3U)
15797 #define EXTI_EXTICR4_EXTI12_PI_Msk    (0x1U << EXTI_EXTICR4_EXTI12_PI_Pos)     /*!< 0x00000008 */
15798 #define EXTI_EXTICR4_EXTI12_PI        EXTI_EXTICR4_EXTI12_PI_Msk               /*!<PI[12] pin */
15799 #define EXTI_EXTICR4_EXTI12_PJ_Pos    (0U)
15800 #define EXTI_EXTICR4_EXTI12_PJ_Msk    (0x9U << EXTI_EXTICR4_EXTI12_PJ_Pos)     /*!< 0x00000009 */
15801 #define EXTI_EXTICR4_EXTI12_PJ        EXTI_EXTICR4_EXTI12_PJ_Msk               /*!<PJ[12] pin */
15802 
15803 /**
15804   * @brief   EXTI13 configuration
15805   */
15806 #define EXTI_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000)                   /*!<PA[13] pin */
15807 #define EXTI_EXTICR4_EXTI13_PB_Pos    (8U)
15808 #define EXTI_EXTICR4_EXTI13_PB_Msk    (0x1U << EXTI_EXTICR4_EXTI13_PB_Pos)     /*!< 0x00000100 */
15809 #define EXTI_EXTICR4_EXTI13_PB        EXTI_EXTICR4_EXTI13_PB_Msk               /*!<PB[13] pin */
15810 #define EXTI_EXTICR4_EXTI13_PC_Pos    (9U)
15811 #define EXTI_EXTICR4_EXTI13_PC_Msk    (0x1U << EXTI_EXTICR4_EXTI13_PC_Pos)     /*!< 0x00000200 */
15812 #define EXTI_EXTICR4_EXTI13_PC        EXTI_EXTICR4_EXTI13_PC_Msk               /*!<PC[13] pin */
15813 #define EXTI_EXTICR4_EXTI13_PD_Pos    (8U)
15814 #define EXTI_EXTICR4_EXTI13_PD_Msk    (0x3U << EXTI_EXTICR4_EXTI13_PD_Pos)     /*!< 0x00000300 */
15815 #define EXTI_EXTICR4_EXTI13_PD        EXTI_EXTICR4_EXTI13_PD_Msk               /*!<PD[13] pin */
15816 #define EXTI_EXTICR4_EXTI13_PE_Pos    (10U)
15817 #define EXTI_EXTICR4_EXTI13_PE_Msk    (0x1U << EXTI_EXTICR4_EXTI13_PE_Pos)     /*!< 0x00000400 */
15818 #define EXTI_EXTICR4_EXTI13_PE        EXTI_EXTICR4_EXTI13_PE_Msk               /*!<PE[13] pin */
15819 #define EXTI_EXTICR4_EXTI13_PF_Pos    (8U)
15820 #define EXTI_EXTICR4_EXTI13_PF_Msk    (0x5U << EXTI_EXTICR4_EXTI13_PF_Pos)     /*!< 0x00000500 */
15821 #define EXTI_EXTICR4_EXTI13_PF        EXTI_EXTICR4_EXTI13_PF_Msk               /*!<PF[13] pin */
15822 #define EXTI_EXTICR4_EXTI13_PG_Pos    (9U)
15823 #define EXTI_EXTICR4_EXTI13_PG_Msk    (0x3U << EXTI_EXTICR4_EXTI13_PG_Pos)     /*!< 0x00000600 */
15824 #define EXTI_EXTICR4_EXTI13_PG        EXTI_EXTICR4_EXTI13_PG_Msk               /*!<PG[13] pin */
15825 #define EXTI_EXTICR4_EXTI13_PH_Pos    (8U)
15826 #define EXTI_EXTICR4_EXTI13_PH_Msk    (0x7U << EXTI_EXTICR4_EXTI13_PH_Pos)     /*!< 0x00000700 */
15827 #define EXTI_EXTICR4_EXTI13_PH        EXTI_EXTICR4_EXTI13_PH_Msk               /*!<PH[13] pin */
15828 #define EXTI_EXTICR4_EXTI13_PI_Pos    (11U)
15829 #define EXTI_EXTICR4_EXTI13_PI_Msk    (0x1U << EXTI_EXTICR4_EXTI13_PI_Pos)     /*!< 0x00000800 */
15830 #define EXTI_EXTICR4_EXTI13_PI        EXTI_EXTICR4_EXTI13_PI_Msk               /*!<PI[13] pin */
15831 #define EXTI_EXTICR4_EXTI13_PJ_Pos    (8U)
15832 #define EXTI_EXTICR4_EXTI13_PJ_Msk    (0x9U << EXTI_EXTICR4_EXTI13_PJ_Pos)     /*!< 0x00000900 */
15833 #define EXTI_EXTICR4_EXTI13_PJ        EXTI_EXTICR4_EXTI13_PJ_Msk               /*!<PJ[13] pin */
15834 
15835 /**
15836   * @brief   EXTI14 configuration
15837   */
15838 #define EXTI_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000)                   /*!<PA[14] pin */
15839 #define EXTI_EXTICR4_EXTI14_PB_Pos    (16U)
15840 #define EXTI_EXTICR4_EXTI14_PB_Msk    (0x1U << EXTI_EXTICR4_EXTI14_PB_Pos)     /*!< 0x00010000 */
15841 #define EXTI_EXTICR4_EXTI14_PB        EXTI_EXTICR4_EXTI14_PB_Msk               /*!<PB[14] pin */
15842 #define EXTI_EXTICR4_EXTI14_PC_Pos    (17U)
15843 #define EXTI_EXTICR4_EXTI14_PC_Msk    (0x1U << EXTI_EXTICR4_EXTI14_PC_Pos)     /*!< 0x00020000 */
15844 #define EXTI_EXTICR4_EXTI14_PC        EXTI_EXTICR4_EXTI14_PC_Msk               /*!<PC[14] pin */
15845 #define EXTI_EXTICR4_EXTI14_PD_Pos    (16U)
15846 #define EXTI_EXTICR4_EXTI14_PD_Msk    (0x3U << EXTI_EXTICR4_EXTI14_PD_Pos)     /*!< 0x00030000 */
15847 #define EXTI_EXTICR4_EXTI14_PD        EXTI_EXTICR4_EXTI14_PD_Msk               /*!<PD[14] pin */
15848 #define EXTI_EXTICR4_EXTI14_PE_Pos    (18U)
15849 #define EXTI_EXTICR4_EXTI14_PE_Msk    (0x1U << EXTI_EXTICR4_EXTI14_PE_Pos)     /*!< 0x00040000 */
15850 #define EXTI_EXTICR4_EXTI14_PE        EXTI_EXTICR4_EXTI14_PE_Msk               /*!<PE[14] pin */
15851 #define EXTI_EXTICR4_EXTI14_PF_Pos    (16U)
15852 #define EXTI_EXTICR4_EXTI14_PF_Msk    (0x5U << EXTI_EXTICR4_EXTI14_PF_Pos)     /*!< 0x00050000 */
15853 #define EXTI_EXTICR4_EXTI14_PF        EXTI_EXTICR4_EXTI14_PF_Msk               /*!<PF[14] pin */
15854 #define EXTI_EXTICR4_EXTI14_PG_Pos    (17U)
15855 #define EXTI_EXTICR4_EXTI14_PG_Msk    (0x3U << EXTI_EXTICR4_EXTI14_PG_Pos)     /*!< 0x00060000 */
15856 #define EXTI_EXTICR4_EXTI14_PG        EXTI_EXTICR4_EXTI14_PG_Msk               /*!<PG[14] pin */
15857 #define EXTI_EXTICR4_EXTI14_PH_Pos    (16U)
15858 #define EXTI_EXTICR4_EXTI14_PH_Msk    (0x7U << EXTI_EXTICR4_EXTI14_PH_Pos)     /*!< 0x00070000 */
15859 #define EXTI_EXTICR4_EXTI14_PH        EXTI_EXTICR4_EXTI14_PH_Msk               /*!<PH[14] pin */
15860 #define EXTI_EXTICR4_EXTI14_PI_Pos    (19U)
15861 #define EXTI_EXTICR4_EXTI14_PI_Msk    (0x1U << EXTI_EXTICR4_EXTI14_PI_Pos)     /*!< 0x00080000 */
15862 #define EXTI_EXTICR4_EXTI14_PI        EXTI_EXTICR4_EXTI14_PI_Msk               /*!<PI[14] pin */
15863 #define EXTI_EXTICR4_EXTI14_PJ_Pos    (16U)
15864 #define EXTI_EXTICR4_EXTI14_PJ_Msk    (0x9U << EXTI_EXTICR4_EXTI14_PJ_Pos)     /*!< 0x00090000 */
15865 #define EXTI_EXTICR4_EXTI14_PJ        EXTI_EXTICR4_EXTI14_PJ_Msk               /*!<PJ[14] pin */
15866 
15867 /**
15868   * @brief   EXTI15 configuration
15869   */
15870 #define EXTI_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000)                   /*!<PA[15] pin */
15871 #define EXTI_EXTICR4_EXTI15_PB_Pos    (24U)
15872 #define EXTI_EXTICR4_EXTI15_PB_Msk    (0x1U << EXTI_EXTICR4_EXTI15_PB_Pos)     /*!< 0x01000000 */
15873 #define EXTI_EXTICR4_EXTI15_PB        EXTI_EXTICR4_EXTI15_PB_Msk               /*!<PB[15] pin */
15874 #define EXTI_EXTICR4_EXTI15_PC_Pos    (25U)
15875 #define EXTI_EXTICR4_EXTI15_PC_Msk    (0x1U << EXTI_EXTICR4_EXTI15_PC_Pos)     /*!< 0x02000000 */
15876 #define EXTI_EXTICR4_EXTI15_PC        EXTI_EXTICR4_EXTI15_PC_Msk               /*!<PC[15] pin */
15877 #define EXTI_EXTICR4_EXTI15_PD_Pos    (24U)
15878 #define EXTI_EXTICR4_EXTI15_PD_Msk    (0x3U << EXTI_EXTICR4_EXTI15_PD_Pos)     /*!< 0x03000000 */
15879 #define EXTI_EXTICR4_EXTI15_PD        EXTI_EXTICR4_EXTI15_PD_Msk               /*!<PD[15] pin */
15880 #define EXTI_EXTICR4_EXTI15_PE_Pos    (26U)
15881 #define EXTI_EXTICR4_EXTI15_PE_Msk    (0x1U << EXTI_EXTICR4_EXTI15_PE_Pos)     /*!< 0x04000000 */
15882 #define EXTI_EXTICR4_EXTI15_PE        EXTI_EXTICR4_EXTI15_PE_Msk               /*!<PE[15] pin */
15883 #define EXTI_EXTICR4_EXTI15_PF_Pos    (24U)
15884 #define EXTI_EXTICR4_EXTI15_PF_Msk    (0x5U << EXTI_EXTICR4_EXTI15_PF_Pos)     /*!< 0x05000000 */
15885 #define EXTI_EXTICR4_EXTI15_PF        EXTI_EXTICR4_EXTI15_PF_Msk               /*!<PF[15] pin */
15886 #define EXTI_EXTICR4_EXTI15_PG_Pos    (25U)
15887 #define EXTI_EXTICR4_EXTI15_PG_Msk    (0x3U << EXTI_EXTICR4_EXTI15_PG_Pos)     /*!< 0x06000000 */
15888 #define EXTI_EXTICR4_EXTI15_PG        EXTI_EXTICR4_EXTI15_PG_Msk               /*!<PG[15] pin */
15889 #define EXTI_EXTICR4_EXTI15_PH_Pos    (24U)
15890 #define EXTI_EXTICR4_EXTI15_PH_Msk    (0x7U << EXTI_EXTICR4_EXTI15_PH_Pos)     /*!< 0x07000000 */
15891 #define EXTI_EXTICR4_EXTI15_PH        EXTI_EXTICR4_EXTI15_PH_Msk               /*!<PH[15] pin */
15892 #define EXTI_EXTICR4_EXTI15_PI_Pos    (27U)
15893 #define EXTI_EXTICR4_EXTI15_PI_Msk    (0x1U << EXTI_EXTICR4_EXTI15_PI_Pos)     /*!< 0x08000000 */
15894 #define EXTI_EXTICR4_EXTI15_PI        EXTI_EXTICR4_EXTI15_PI_Msk               /*!<PI[15] pin */
15895 #define EXTI_EXTICR4_EXTI15_PJ_Pos    (24U)
15896 #define EXTI_EXTICR4_EXTI15_PJ_Msk    (0x9U << EXTI_EXTICR4_EXTI15_PJ_Pos)     /*!< 0x09000000 */
15897 #define EXTI_EXTICR4_EXTI15_PJ        EXTI_EXTICR4_EXTI15_PJ_Msk               /*!<PJ[15] pin */
15898 
15899 /**********************  Bit definition for EXTI_HWCFGR1 register  ***************/
15900 #define EXTI_HWCFGR1_NBEVENTS_Pos  (0U)
15901 #define EXTI_HWCFGR1_NBEVENTS_Msk  (0xFFU << EXTI_HWCFGR1_NBEVENTS_Pos)          /*!< 0x000000FF */
15902 #define EXTI_HWCFGR1_NBEVENTS       EXTI_HWCFGR1_NBEVENTS_Msk                    /*!< Number of EVENT */
15903 #define EXTI_HWCFGR1_NBCPUS_Pos    (8U)
15904 #define EXTI_HWCFGR1_NBCPUS_Msk    (0xFU << EXTI_HWCFGR1_NBCPUS_Pos)             /*!< 0x00000F00 */
15905 #define EXTI_HWCFGR1_NBCPUS         EXTI_HWCFGR1_NBCPUS_Msk                      /*!< Number of CPUs */
15906 #define EXTI_HWCFGR1_CPUEVTEN_Pos  (12U)
15907 #define EXTI_HWCFGR1_CPUEVTEN_Msk  (0xFU << EXTI_HWCFGR1_CPUEVTEN_Pos)           /*!< 0x0000F000 */
15908 #define EXTI_HWCFGR1_CPUEVTEN       EXTI_HWCFGR1_CPUEVTEN_Msk                    /*!< CPU(m) event output enable */
15909 #define EXTI_HWCFGR1_NBIOPORT_Pos  (16U)
15910 #define EXTI_HWCFGR1_NBIOPORT_Msk  (0xFFU << EXTI_HWCFGR1_NBIOPORT_Pos)          /*!< 0x00FF0000 */
15911 #define EXTI_HWCFGR1_NBIOPORT       EXTI_HWCFGR1_NBIOPORT_Msk                    /*!< Number of IO ports on EXTI */
15912 
15913 /**********************  Bit definition for EXTI_VERR register  *****************/
15914 #define EXTI_VERR_MINREV_Pos      (0U)
15915 #define EXTI_VERR_MINREV_Msk      (0xFU << EXTI_VERR_MINREV_Pos)               /*!< 0x0000000F */
15916 #define EXTI_VERR_MINREV          EXTI_VERR_MINREV_Msk                         /*!< Minor Revision number */
15917 #define EXTI_VERR_MAJREV_Pos      (4U)
15918 #define EXTI_VERR_MAJREV_Msk      (0xFU << EXTI_VERR_MAJREV_Pos)               /*!< 0x000000F0 */
15919 #define EXTI_VERR_MAJREV          EXTI_VERR_MAJREV_Msk                         /*!< Major Revision number */
15920 
15921 /**********************  Bit definition for EXTI_IPIDR register  ****************/
15922 #define EXTI_IPIDR_IPID_Pos       (0U)
15923 #define EXTI_IPIDR_IPID_Msk       (0xFFFFFFFFU << EXTI_IPIDR_IPID_Pos)         /*!< 0xFFFFFFFF */
15924 #define EXTI_IPIDR_IPID           EXTI_IPIDR_IPID_Msk                          /*!< IP Identification */
15925 
15926 /**********************  Bit definition for EXTI_SIDR register  *****************/
15927 #define EXTI_SIDR_SID_Pos         (0U)
15928 #define EXTI_SIDR_SID_Msk         (0xFFFFFFFFU << EXTI_SIDR_SID_Pos)           /*!< 0xFFFFFFFF */
15929 #define EXTI_SIDR_SID             EXTI_SIDR_SID_Msk                            /*!< IP size identification */
15930 
15931 /******************************************************************************/
15932 /*                                                                            */
15933 /*                           FDCAN Controller                                 */
15934 /*                                                                            */
15935 /******************************************************************************/
15936 
15937 /*******************  Bit definition for FDCAN_CCCR register  *****************/
15938 #define FDCAN_CCCR_INIT_Pos       (0U)
15939 #define FDCAN_CCCR_INIT_Msk       (0x1U << FDCAN_CCCR_INIT_Pos)                /*!< 0x00000001 */
15940 #define FDCAN_CCCR_INIT           FDCAN_CCCR_INIT_Msk                          /*!< Initialization bit */
15941 #define FDCAN_CCCR_CCCE_Pos       (1U)
15942 #define FDCAN_CCCR_CCCE_Msk       (0x1U << FDCAN_CCCR_CCCE_Pos)                /*!< 0x00000002 */
15943 #define FDCAN_CCCR_CCCE           FDCAN_CCCR_CCCE_Msk                          /*!< Configuration Change Enable bit */
15944 
15945 
15946 /******************************************************************************/
15947 /*                                                                            */
15948 /*                          Flexible Memory Controller                        */
15949 /*                                                                            */
15950 /******************************************************************************/
15951 /******************  Bit definition for FMC_BCR1 register  *******************/
15952 #define FMC_BCR1_MBKEN_Pos         (0U)
15953 #define FMC_BCR1_MBKEN_Msk         (0x1U << FMC_BCR1_MBKEN_Pos)                /*!< 0x00000001 */
15954 #define FMC_BCR1_MBKEN             FMC_BCR1_MBKEN_Msk                          /*!<Memory bank enable bit                 */
15955 #define FMC_BCR1_MUXEN_Pos         (1U)
15956 #define FMC_BCR1_MUXEN_Msk         (0x1U << FMC_BCR1_MUXEN_Pos)                /*!< 0x00000002 */
15957 #define FMC_BCR1_MUXEN             FMC_BCR1_MUXEN_Msk                          /*!<Address/data multiplexing enable bit   */
15958 
15959 #define FMC_BCR1_MTYP_Pos          (2U)
15960 #define FMC_BCR1_MTYP_Msk          (0x3U << FMC_BCR1_MTYP_Pos)                 /*!< 0x0000000C */
15961 #define FMC_BCR1_MTYP              FMC_BCR1_MTYP_Msk                           /*!<MTYP[1:0] bits (Memory type)           */
15962 #define FMC_BCR1_MTYP_0            (0x1U << FMC_BCR1_MTYP_Pos)                 /*!< 0x00000004 */
15963 #define FMC_BCR1_MTYP_1            (0x2U << FMC_BCR1_MTYP_Pos)                 /*!< 0x00000008 */
15964 
15965 #define FMC_BCR1_MWID_Pos          (4U)
15966 #define FMC_BCR1_MWID_Msk          (0x3U << FMC_BCR1_MWID_Pos)                 /*!< 0x00000030 */
15967 #define FMC_BCR1_MWID              FMC_BCR1_MWID_Msk                           /*!<MWID[1:0] bits (Memory data bus width) */
15968 #define FMC_BCR1_MWID_0            (0x1U << FMC_BCR1_MWID_Pos)                 /*!< 0x00000010 */
15969 #define FMC_BCR1_MWID_1            (0x2U << FMC_BCR1_MWID_Pos)                 /*!< 0x00000020 */
15970 
15971 #define FMC_BCR1_FACCEN_Pos        (6U)
15972 #define FMC_BCR1_FACCEN_Msk        (0x1U << FMC_BCR1_FACCEN_Pos)               /*!< 0x00000040 */
15973 #define FMC_BCR1_FACCEN            FMC_BCR1_FACCEN_Msk                         /*!<Flash access enable        */
15974 #define FMC_BCR1_BURSTEN_Pos       (8U)
15975 #define FMC_BCR1_BURSTEN_Msk       (0x1U << FMC_BCR1_BURSTEN_Pos)              /*!< 0x00000100 */
15976 #define FMC_BCR1_BURSTEN           FMC_BCR1_BURSTEN_Msk                        /*!<Burst enable bit           */
15977 #define FMC_BCR1_WAITPOL_Pos       (9U)
15978 #define FMC_BCR1_WAITPOL_Msk       (0x1U << FMC_BCR1_WAITPOL_Pos)              /*!< 0x00000200 */
15979 #define FMC_BCR1_WAITPOL           FMC_BCR1_WAITPOL_Msk                        /*!<Wait signal polarity bit   */
15980 #define FMC_BCR1_WRAPMOD_Pos       (10U)
15981 #define FMC_BCR1_WRAPMOD_Msk       (0x1U << FMC_BCR1_WRAPMOD_Pos)              /*!< 0x00000400 */
15982 #define FMC_BCR1_WRAPMOD           FMC_BCR1_WRAPMOD_Msk                        /*!<Wrapped burst mode support */
15983 #define FMC_BCR1_WAITCFG_Pos       (11U)
15984 #define FMC_BCR1_WAITCFG_Msk       (0x1U << FMC_BCR1_WAITCFG_Pos)              /*!< 0x00000800 */
15985 #define FMC_BCR1_WAITCFG           FMC_BCR1_WAITCFG_Msk                        /*!<Wait timing configuration  */
15986 #define FMC_BCR1_WREN_Pos          (12U)
15987 #define FMC_BCR1_WREN_Msk          (0x1U << FMC_BCR1_WREN_Pos)                 /*!< 0x00001000 */
15988 #define FMC_BCR1_WREN              FMC_BCR1_WREN_Msk                           /*!<Write enable bit           */
15989 #define FMC_BCR1_WAITEN_Pos        (13U)
15990 #define FMC_BCR1_WAITEN_Msk        (0x1U << FMC_BCR1_WAITEN_Pos)               /*!< 0x00002000 */
15991 #define FMC_BCR1_WAITEN            FMC_BCR1_WAITEN_Msk                         /*!<Wait enable bit            */
15992 #define FMC_BCR1_EXTMOD_Pos        (14U)
15993 #define FMC_BCR1_EXTMOD_Msk        (0x1U << FMC_BCR1_EXTMOD_Pos)               /*!< 0x00004000 */
15994 #define FMC_BCR1_EXTMOD            FMC_BCR1_EXTMOD_Msk                         /*!<Extended mode enable       */
15995 #define FMC_BCR1_ASYNCWAIT_Pos     (15U)
15996 #define FMC_BCR1_ASYNCWAIT_Msk     (0x1U << FMC_BCR1_ASYNCWAIT_Pos)            /*!< 0x00008000 */
15997 #define FMC_BCR1_ASYNCWAIT         FMC_BCR1_ASYNCWAIT_Msk                      /*!<Asynchronous wait          */
15998 
15999 #define FMC_BCR1_CPSIZE_Pos        (16U)
16000 #define FMC_BCR1_CPSIZE_Msk        (0x7U << FMC_BCR1_CPSIZE_Pos)               /*!< 0x00070000 */
16001 #define FMC_BCR1_CPSIZE            FMC_BCR1_CPSIZE_Msk                         /*!<PSIZE[2:0] bits CRAM Page Size */
16002 #define FMC_BCR1_CPSIZE_0          (0x1U << FMC_BCR1_CPSIZE_Pos)               /*!< 0x00010000 */
16003 #define FMC_BCR1_CPSIZE_1          (0x2U << FMC_BCR1_CPSIZE_Pos)               /*!< 0x00020000 */
16004 #define FMC_BCR1_CPSIZE_2          (0x4U << FMC_BCR1_CPSIZE_Pos)               /*!< 0x00040000 */
16005 
16006 #define FMC_BCR1_CBURSTRW_Pos      (19U)
16007 #define FMC_BCR1_CBURSTRW_Msk      (0x1U << FMC_BCR1_CBURSTRW_Pos)             /*!< 0x00080000 */
16008 #define FMC_BCR1_CBURSTRW          FMC_BCR1_CBURSTRW_Msk                       /*!<Write burst enable         */
16009 #define FMC_BCR1_CCLKEN_Pos        (20U)
16010 #define FMC_BCR1_CCLKEN_Msk        (0x1U << FMC_BCR1_CCLKEN_Pos)               /*!< 0x00100000 */
16011 #define FMC_BCR1_CCLKEN            FMC_BCR1_CCLKEN_Msk                         /*!<Continous clock enable     */
16012 
16013 #define FMC_BCR1_NBLSET_Pos        (22U)
16014 #define FMC_BCR1_NBLSET_Msk        (0x3U << FMC_BCR1_NBLSET_Pos)                /*!< 0x00C00000 */
16015 #define FMC_BCR1_NBLSET            FMC_BCR1_NBLSET_Msk                          /*!< NBLSET[1:0] bits Byte lane (NBL) SETUP */
16016 #define FMC_BCR1_NBLSET_0          (0x1U << FMC_BCR1_NBLSET_Pos)                /*!< 0x00400000 */
16017 #define FMC_BCR1_NBLSET_1          (0x2U << FMC_BCR1_NBLSET_Pos)                /*!< 0x00800000 */
16018 
16019 #define FMC_BCR1_FMCEN_Pos         (31U)
16020 #define FMC_BCR1_FMCEN_Msk         (0x1UL << FMC_BCR1_FMCEN_Pos)                /*!< 0x80000000 */
16021 #define FMC_BCR1_FMCEN             FMC_BCR1_FMCEN_Msk                           /*!<FMC controller enable*/
16022 
16023 /******************  Bit definition for FMC_BCR2 register  *******************/
16024 #define FMC_BCR2_MBKEN_Pos         (0U)
16025 #define FMC_BCR2_MBKEN_Msk         (0x1U << FMC_BCR2_MBKEN_Pos)                /*!< 0x00000001 */
16026 #define FMC_BCR2_MBKEN             FMC_BCR2_MBKEN_Msk                          /*!<Memory bank enable bit                 */
16027 #define FMC_BCR2_MUXEN_Pos         (1U)
16028 #define FMC_BCR2_MUXEN_Msk         (0x1U << FMC_BCR2_MUXEN_Pos)                /*!< 0x00000002 */
16029 #define FMC_BCR2_MUXEN             FMC_BCR2_MUXEN_Msk                          /*!<Address/data multiplexing enable bit   */
16030 
16031 #define FMC_BCR2_MTYP_Pos          (2U)
16032 #define FMC_BCR2_MTYP_Msk          (0x3U << FMC_BCR2_MTYP_Pos)                 /*!< 0x0000000C */
16033 #define FMC_BCR2_MTYP              FMC_BCR2_MTYP_Msk                           /*!<MTYP[1:0] bits (Memory type)           */
16034 #define FMC_BCR2_MTYP_0            (0x1U << FMC_BCR2_MTYP_Pos)                 /*!< 0x00000004 */
16035 #define FMC_BCR2_MTYP_1            (0x2U << FMC_BCR2_MTYP_Pos)                 /*!< 0x00000008 */
16036 
16037 #define FMC_BCR2_MWID_Pos          (4U)
16038 #define FMC_BCR2_MWID_Msk          (0x3U << FMC_BCR2_MWID_Pos)                 /*!< 0x00000030 */
16039 #define FMC_BCR2_MWID              FMC_BCR2_MWID_Msk                           /*!<MWID[1:0] bits (Memory data bus width) */
16040 #define FMC_BCR2_MWID_0            (0x1U << FMC_BCR2_MWID_Pos)                 /*!< 0x00000010 */
16041 #define FMC_BCR2_MWID_1            (0x2U << FMC_BCR2_MWID_Pos)                 /*!< 0x00000020 */
16042 
16043 #define FMC_BCR2_FACCEN_Pos        (6U)
16044 #define FMC_BCR2_FACCEN_Msk        (0x1U << FMC_BCR2_FACCEN_Pos)               /*!< 0x00000040 */
16045 #define FMC_BCR2_FACCEN            FMC_BCR2_FACCEN_Msk                         /*!<Flash access enable        */
16046 #define FMC_BCR2_BURSTEN_Pos       (8U)
16047 #define FMC_BCR2_BURSTEN_Msk       (0x1U << FMC_BCR2_BURSTEN_Pos)              /*!< 0x00000100 */
16048 #define FMC_BCR2_BURSTEN           FMC_BCR2_BURSTEN_Msk                        /*!<Burst enable bit           */
16049 #define FMC_BCR2_WAITPOL_Pos       (9U)
16050 #define FMC_BCR2_WAITPOL_Msk       (0x1U << FMC_BCR2_WAITPOL_Pos)              /*!< 0x00000200 */
16051 #define FMC_BCR2_WAITPOL           FMC_BCR2_WAITPOL_Msk                        /*!<Wait signal polarity bit   */
16052 #define FMC_BCR2_WRAPMOD_Pos       (10U)
16053 #define FMC_BCR2_WRAPMOD_Msk       (0x1U << FMC_BCR2_WRAPMOD_Pos)              /*!< 0x00000400 */
16054 #define FMC_BCR2_WRAPMOD           FMC_BCR2_WRAPMOD_Msk                        /*!<Wrapped burst mode support */
16055 #define FMC_BCR2_WAITCFG_Pos       (11U)
16056 #define FMC_BCR2_WAITCFG_Msk       (0x1U << FMC_BCR2_WAITCFG_Pos)              /*!< 0x00000800 */
16057 #define FMC_BCR2_WAITCFG           FMC_BCR2_WAITCFG_Msk                        /*!<Wait timing configuration  */
16058 #define FMC_BCR2_WREN_Pos          (12U)
16059 #define FMC_BCR2_WREN_Msk          (0x1U << FMC_BCR2_WREN_Pos)                 /*!< 0x00001000 */
16060 #define FMC_BCR2_WREN              FMC_BCR2_WREN_Msk                           /*!<Write enable bit           */
16061 #define FMC_BCR2_WAITEN_Pos        (13U)
16062 #define FMC_BCR2_WAITEN_Msk        (0x1U << FMC_BCR2_WAITEN_Pos)               /*!< 0x00002000 */
16063 #define FMC_BCR2_WAITEN            FMC_BCR2_WAITEN_Msk                         /*!<Wait enable bit            */
16064 #define FMC_BCR2_EXTMOD_Pos        (14U)
16065 #define FMC_BCR2_EXTMOD_Msk        (0x1U << FMC_BCR2_EXTMOD_Pos)               /*!< 0x00004000 */
16066 #define FMC_BCR2_EXTMOD            FMC_BCR2_EXTMOD_Msk                         /*!<Extended mode enable       */
16067 #define FMC_BCR2_ASYNCWAIT_Pos     (15U)
16068 #define FMC_BCR2_ASYNCWAIT_Msk     (0x1U << FMC_BCR2_ASYNCWAIT_Pos)            /*!< 0x00008000 */
16069 #define FMC_BCR2_ASYNCWAIT         FMC_BCR2_ASYNCWAIT_Msk                      /*!<Asynchronous wait          */
16070 
16071 #define FMC_BCR2_PSIZE_Pos         (16U)
16072 #define FMC_BCR2_PSIZE_Msk         (0x7U << FMC_BCR2_PSIZE_Pos)                /*!< 0x00070000 */
16073 #define FMC_BCR2_PSIZE             FMC_BCR2_PSIZE_Msk                          /*!<PSIZE[2:0] bits CRAM Page Size */
16074 #define FMC_BCR2_PSIZE_0           (0x1U << FMC_BCR2_PSIZE_Pos)                /*!< 0x00010000 */
16075 #define FMC_BCR2_PSIZE_1           (0x2U << FMC_BCR2_PSIZE_Pos)                /*!< 0x00020000 */
16076 #define FMC_BCR2_PSIZE_2           (0x4U << FMC_BCR2_PSIZE_Pos)                /*!< 0x00040000 */
16077 
16078 #define FMC_BCR2_CBURSTRW_Pos      (19U)
16079 #define FMC_BCR2_CBURSTRW_Msk      (0x1U << FMC_BCR2_CBURSTRW_Pos)             /*!< 0x00080000 */
16080 #define FMC_BCR2_CBURSTRW          FMC_BCR2_CBURSTRW_Msk                       /*!<Write burst enable         */
16081 
16082 #define FMC_BCR2_NBLSET_Pos        (22U)
16083 #define FMC_BCR2_NBLSET_Msk        (0x3U << FMC_BCR1_NBLSET_Pos)                /*!< 0x00C00000 */
16084 #define FMC_BCR2_NBLSET            FMC_BCR1_NBLSET_Msk                          /*!< NBLSET[1:0] bits Byte lane (NBL) SETUP */
16085 #define FMC_BCR2_NBLSET_0          (0x1U << FMC_BCR1_NBLSET_Pos)                /*!< 0x00400000 */
16086 #define FMC_BCR2_NBLSET_1          (0x2U << FMC_BCR1_NBLSET_Pos)                /*!< 0x00800000 */
16087 
16088 /******************  Bit definition for FMC_BCR3 register  *******************/
16089 #define FMC_BCR3_MBKEN_Pos         (0U)
16090 #define FMC_BCR3_MBKEN_Msk         (0x1U << FMC_BCR3_MBKEN_Pos)                /*!< 0x00000001 */
16091 #define FMC_BCR3_MBKEN             FMC_BCR3_MBKEN_Msk                          /*!<Memory bank enable bit                 */
16092 #define FMC_BCR3_MUXEN_Pos         (1U)
16093 #define FMC_BCR3_MUXEN_Msk         (0x1U << FMC_BCR3_MUXEN_Pos)                /*!< 0x00000002 */
16094 #define FMC_BCR3_MUXEN             FMC_BCR3_MUXEN_Msk                          /*!<Address/data multiplexing enable bit   */
16095 
16096 #define FMC_BCR3_MTYP_Pos          (2U)
16097 #define FMC_BCR3_MTYP_Msk          (0x3U << FMC_BCR3_MTYP_Pos)                 /*!< 0x0000000C */
16098 #define FMC_BCR3_MTYP              FMC_BCR3_MTYP_Msk                           /*!<MTYP[1:0] bits (Memory type)           */
16099 #define FMC_BCR3_MTYP_0            (0x1U << FMC_BCR3_MTYP_Pos)                 /*!< 0x00000004 */
16100 #define FMC_BCR3_MTYP_1            (0x2U << FMC_BCR3_MTYP_Pos)                 /*!< 0x00000008 */
16101 
16102 #define FMC_BCR3_MWID_Pos          (4U)
16103 #define FMC_BCR3_MWID_Msk          (0x3U << FMC_BCR3_MWID_Pos)                 /*!< 0x00000030 */
16104 #define FMC_BCR3_MWID              FMC_BCR3_MWID_Msk                           /*!<MWID[1:0] bits (Memory data bus width) */
16105 #define FMC_BCR3_MWID_0            (0x1U << FMC_BCR3_MWID_Pos)                 /*!< 0x00000010 */
16106 #define FMC_BCR3_MWID_1            (0x2U << FMC_BCR3_MWID_Pos)                 /*!< 0x00000020 */
16107 
16108 #define FMC_BCR3_FACCEN_Pos        (6U)
16109 #define FMC_BCR3_FACCEN_Msk        (0x1U << FMC_BCR3_FACCEN_Pos)               /*!< 0x00000040 */
16110 #define FMC_BCR3_FACCEN            FMC_BCR3_FACCEN_Msk                         /*!<Flash access enable        */
16111 #define FMC_BCR3_BURSTEN_Pos       (8U)
16112 #define FMC_BCR3_BURSTEN_Msk       (0x1U << FMC_BCR3_BURSTEN_Pos)              /*!< 0x00000100 */
16113 #define FMC_BCR3_BURSTEN           FMC_BCR3_BURSTEN_Msk                        /*!<Burst enable bit           */
16114 #define FMC_BCR3_WAITPOL_Pos       (9U)
16115 #define FMC_BCR3_WAITPOL_Msk       (0x1U << FMC_BCR3_WAITPOL_Pos)              /*!< 0x00000200 */
16116 #define FMC_BCR3_WAITPOL           FMC_BCR3_WAITPOL_Msk                        /*!<Wait signal polarity bit   */
16117 #define FMC_BCR3_WRAPMOD_Pos       (10U)
16118 #define FMC_BCR3_WRAPMOD_Msk       (0x1U << FMC_BCR3_WRAPMOD_Pos)              /*!< 0x00000400 */
16119 #define FMC_BCR3_WRAPMOD           FMC_BCR3_WRAPMOD_Msk                        /*!<Wrapped burst mode support */
16120 #define FMC_BCR3_WAITCFG_Pos       (11U)
16121 #define FMC_BCR3_WAITCFG_Msk       (0x1U << FMC_BCR3_WAITCFG_Pos)              /*!< 0x00000800 */
16122 #define FMC_BCR3_WAITCFG           FMC_BCR3_WAITCFG_Msk                        /*!<Wait timing configuration  */
16123 #define FMC_BCR3_WREN_Pos          (12U)
16124 #define FMC_BCR3_WREN_Msk          (0x1U << FMC_BCR3_WREN_Pos)                 /*!< 0x00001000 */
16125 #define FMC_BCR3_WREN              FMC_BCR3_WREN_Msk                           /*!<Write enable bit           */
16126 #define FMC_BCR3_WAITEN_Pos        (13U)
16127 #define FMC_BCR3_WAITEN_Msk        (0x1U << FMC_BCR3_WAITEN_Pos)               /*!< 0x00002000 */
16128 #define FMC_BCR3_WAITEN            FMC_BCR3_WAITEN_Msk                         /*!<Wait enable bit            */
16129 #define FMC_BCR3_EXTMOD_Pos        (14U)
16130 #define FMC_BCR3_EXTMOD_Msk        (0x1U << FMC_BCR3_EXTMOD_Pos)               /*!< 0x00004000 */
16131 #define FMC_BCR3_EXTMOD            FMC_BCR3_EXTMOD_Msk                         /*!<Extended mode enable       */
16132 #define FMC_BCR3_ASYNCWAIT_Pos     (15U)
16133 #define FMC_BCR3_ASYNCWAIT_Msk     (0x1U << FMC_BCR3_ASYNCWAIT_Pos)            /*!< 0x00008000 */
16134 #define FMC_BCR3_ASYNCWAIT         FMC_BCR3_ASYNCWAIT_Msk                      /*!<Asynchronous wait          */
16135 
16136 #define FMC_BCR3_PSIZE_Pos         (16U)
16137 #define FMC_BCR3_PSIZE_Msk         (0x7U << FMC_BCR3_PSIZE_Pos)                /*!< 0x00070000 */
16138 #define FMC_BCR3_PSIZE             FMC_BCR3_PSIZE_Msk                          /*!<PSIZE[2:0] bits CRAM Page Size */
16139 #define FMC_BCR3_PSIZE_0           (0x1U << FMC_BCR3_PSIZE_Pos)                /*!< 0x00010000 */
16140 #define FMC_BCR3_PSIZE_1           (0x2U << FMC_BCR3_PSIZE_Pos)                /*!< 0x00020000 */
16141 #define FMC_BCR3_PSIZE_2           (0x4U << FMC_BCR3_PSIZE_Pos)                /*!< 0x00040000 */
16142 
16143 #define FMC_BCR3_CBURSTRW_Pos      (19U)
16144 #define FMC_BCR3_CBURSTRW_Msk      (0x1U << FMC_BCR3_CBURSTRW_Pos)             /*!< 0x00080000 */
16145 #define FMC_BCR3_CBURSTRW          FMC_BCR3_CBURSTRW_Msk                       /*!<Write burst enable         */
16146 
16147 #define FMC_BCR3_NBLSET_Pos        (22U)
16148 #define FMC_BCR3_NBLSET_Msk        (0x3U << FMC_BCR1_NBLSET_Pos)                /*!< 0x00C00000 */
16149 #define FMC_BCR3_NBLSET            FMC_BCR1_NBLSET_Msk                          /*!< NBLSET[1:0] bits Byte lane (NBL) SETUP */
16150 #define FMC_BCR3_NBLSET_0          (0x1U << FMC_BCR1_NBLSET_Pos)                /*!< 0x00400000 */
16151 #define FMC_BCR3_NBLSET_1          (0x2U << FMC_BCR1_NBLSET_Pos)                /*!< 0x00800000 */
16152 
16153 /******************  Bit definition for FMC_BCR4 register  *******************/
16154 #define FMC_BCR4_MBKEN_Pos         (0U)
16155 #define FMC_BCR4_MBKEN_Msk         (0x1U << FMC_BCR4_MBKEN_Pos)                /*!< 0x00000001 */
16156 #define FMC_BCR4_MBKEN             FMC_BCR4_MBKEN_Msk                          /*!<Memory bank enable bit                 */
16157 #define FMC_BCR4_MUXEN_Pos         (1U)
16158 #define FMC_BCR4_MUXEN_Msk         (0x1U << FMC_BCR4_MUXEN_Pos)                /*!< 0x00000002 */
16159 #define FMC_BCR4_MUXEN             FMC_BCR4_MUXEN_Msk                          /*!<Address/data multiplexing enable bit   */
16160 
16161 #define FMC_BCR4_MTYP_Pos          (2U)
16162 #define FMC_BCR4_MTYP_Msk          (0x3U << FMC_BCR4_MTYP_Pos)                 /*!< 0x0000000C */
16163 #define FMC_BCR4_MTYP              FMC_BCR4_MTYP_Msk                           /*!<MTYP[1:0] bits (Memory type)           */
16164 #define FMC_BCR4_MTYP_0            (0x1U << FMC_BCR4_MTYP_Pos)                 /*!< 0x00000004 */
16165 #define FMC_BCR4_MTYP_1            (0x2U << FMC_BCR4_MTYP_Pos)                 /*!< 0x00000008 */
16166 
16167 #define FMC_BCR4_MWID_Pos          (4U)
16168 #define FMC_BCR4_MWID_Msk          (0x3U << FMC_BCR4_MWID_Pos)                 /*!< 0x00000030 */
16169 #define FMC_BCR4_MWID              FMC_BCR4_MWID_Msk                           /*!<MWID[1:0] bits (Memory data bus width) */
16170 #define FMC_BCR4_MWID_0            (0x1U << FMC_BCR4_MWID_Pos)                 /*!< 0x00000010 */
16171 #define FMC_BCR4_MWID_1            (0x2U << FMC_BCR4_MWID_Pos)                 /*!< 0x00000020 */
16172 
16173 #define FMC_BCR4_FACCEN_Pos        (6U)
16174 #define FMC_BCR4_FACCEN_Msk        (0x1U << FMC_BCR4_FACCEN_Pos)               /*!< 0x00000040 */
16175 #define FMC_BCR4_FACCEN            FMC_BCR4_FACCEN_Msk                         /*!<Flash access enable        */
16176 #define FMC_BCR4_BURSTEN_Pos       (8U)
16177 #define FMC_BCR4_BURSTEN_Msk       (0x1U << FMC_BCR4_BURSTEN_Pos)              /*!< 0x00000100 */
16178 #define FMC_BCR4_BURSTEN           FMC_BCR4_BURSTEN_Msk                        /*!<Burst enable bit           */
16179 #define FMC_BCR4_WAITPOL_Pos       (9U)
16180 #define FMC_BCR4_WAITPOL_Msk       (0x1U << FMC_BCR4_WAITPOL_Pos)              /*!< 0x00000200 */
16181 #define FMC_BCR4_WAITPOL           FMC_BCR4_WAITPOL_Msk                        /*!<Wait signal polarity bit   */
16182 #define FMC_BCR4_WRAPMOD_Pos       (10U)
16183 #define FMC_BCR4_WRAPMOD_Msk       (0x1U << FMC_BCR4_WRAPMOD_Pos)              /*!< 0x00000400 */
16184 #define FMC_BCR4_WRAPMOD           FMC_BCR4_WRAPMOD_Msk                        /*!<Wrapped burst mode support */
16185 #define FMC_BCR4_WAITCFG_Pos       (11U)
16186 #define FMC_BCR4_WAITCFG_Msk       (0x1U << FMC_BCR4_WAITCFG_Pos)              /*!< 0x00000800 */
16187 #define FMC_BCR4_WAITCFG           FMC_BCR4_WAITCFG_Msk                        /*!<Wait timing configuration  */
16188 #define FMC_BCR4_WREN_Pos          (12U)
16189 #define FMC_BCR4_WREN_Msk          (0x1U << FMC_BCR4_WREN_Pos)                 /*!< 0x00001000 */
16190 #define FMC_BCR4_WREN              FMC_BCR4_WREN_Msk                           /*!<Write enable bit           */
16191 #define FMC_BCR4_WAITEN_Pos        (13U)
16192 #define FMC_BCR4_WAITEN_Msk        (0x1U << FMC_BCR4_WAITEN_Pos)               /*!< 0x00002000 */
16193 #define FMC_BCR4_WAITEN            FMC_BCR4_WAITEN_Msk                         /*!<Wait enable bit            */
16194 #define FMC_BCR4_EXTMOD_Pos        (14U)
16195 #define FMC_BCR4_EXTMOD_Msk        (0x1U << FMC_BCR4_EXTMOD_Pos)               /*!< 0x00004000 */
16196 #define FMC_BCR4_EXTMOD            FMC_BCR4_EXTMOD_Msk                         /*!<Extended mode enable       */
16197 #define FMC_BCR4_ASYNCWAIT_Pos     (15U)
16198 #define FMC_BCR4_ASYNCWAIT_Msk     (0x1U << FMC_BCR4_ASYNCWAIT_Pos)            /*!< 0x00008000 */
16199 #define FMC_BCR4_ASYNCWAIT         FMC_BCR4_ASYNCWAIT_Msk                      /*!<Asynchronous wait          */
16200 
16201 #define FMC_BCR4_PSIZE_Pos         (16U)
16202 #define FMC_BCR4_PSIZE_Msk         (0x7U << FMC_BCR4_PSIZE_Pos)                /*!< 0x00070000 */
16203 #define FMC_BCR4_PSIZE             FMC_BCR4_PSIZE_Msk                          /*!<PSIZE[2:0] bits CRAM Page Size */
16204 #define FMC_BCR4_PSIZE_0           (0x1U << FMC_BCR4_PSIZE_Pos)                /*!< 0x00010000 */
16205 #define FMC_BCR4_PSIZE_1           (0x2U << FMC_BCR4_PSIZE_Pos)                /*!< 0x00020000 */
16206 #define FMC_BCR4_PSIZE_2           (0x4U << FMC_BCR4_PSIZE_Pos)                /*!< 0x00040000 */
16207 
16208 #define FMC_BCR4_CBURSTRW_Pos      (19U)
16209 #define FMC_BCR4_CBURSTRW_Msk      (0x1U << FMC_BCR4_CBURSTRW_Pos)             /*!< 0x00080000 */
16210 #define FMC_BCR4_CBURSTRW          FMC_BCR4_CBURSTRW_Msk                       /*!<Write burst enable         */
16211 
16212 #define FMC_BCR4_NBLSET_Pos        (22U)
16213 #define FMC_BCR4_NBLSET_Msk        (0x3U << FMC_BCR1_NBLSET_Pos)                /*!< 0x00C00000 */
16214 #define FMC_BCR4_NBLSET            FMC_BCR1_NBLSET_Msk                          /*!< NBLSET[1:0] bits Byte lane (NBL) SETUP */
16215 #define FMC_BCR4_NBLSET_0          (0x1U << FMC_BCR1_NBLSET_Pos)                /*!< 0x00400000 */
16216 #define FMC_BCR4_NBLSET_1          (0x2U << FMC_BCR1_NBLSET_Pos)                /*!< 0x00800000 */
16217 
16218 /******************  Bit definition for FMC_BTR1 register  ******************/
16219 #define FMC_BTR1_ADDSET_Pos        (0U)
16220 #define FMC_BTR1_ADDSET_Msk        (0xFU << FMC_BTR1_ADDSET_Pos)               /*!< 0x0000000F */
16221 #define FMC_BTR1_ADDSET            FMC_BTR1_ADDSET_Msk                         /*!<ADDSET[3:0] bits (Address setup phase duration) */
16222 #define FMC_BTR1_ADDSET_0          (0x1U << FMC_BTR1_ADDSET_Pos)               /*!< 0x00000001 */
16223 #define FMC_BTR1_ADDSET_1          (0x2U << FMC_BTR1_ADDSET_Pos)               /*!< 0x00000002 */
16224 #define FMC_BTR1_ADDSET_2          (0x4U << FMC_BTR1_ADDSET_Pos)               /*!< 0x00000004 */
16225 #define FMC_BTR1_ADDSET_3          (0x8U << FMC_BTR1_ADDSET_Pos)               /*!< 0x00000008 */
16226 
16227 #define FMC_BTR1_ADDHLD_Pos        (4U)
16228 #define FMC_BTR1_ADDHLD_Msk        (0xFU << FMC_BTR1_ADDHLD_Pos)               /*!< 0x000000F0 */
16229 #define FMC_BTR1_ADDHLD            FMC_BTR1_ADDHLD_Msk                         /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
16230 #define FMC_BTR1_ADDHLD_0          (0x1U << FMC_BTR1_ADDHLD_Pos)               /*!< 0x00000010 */
16231 #define FMC_BTR1_ADDHLD_1          (0x2U << FMC_BTR1_ADDHLD_Pos)               /*!< 0x00000020 */
16232 #define FMC_BTR1_ADDHLD_2          (0x4U << FMC_BTR1_ADDHLD_Pos)               /*!< 0x00000040 */
16233 #define FMC_BTR1_ADDHLD_3          (0x8U << FMC_BTR1_ADDHLD_Pos)               /*!< 0x00000080 */
16234 
16235 #define FMC_BTR1_DATAST_Pos        (8U)
16236 #define FMC_BTR1_DATAST_Msk        (0xFFU << FMC_BTR1_DATAST_Pos)              /*!< 0x0000FF00 */
16237 #define FMC_BTR1_DATAST            FMC_BTR1_DATAST_Msk                         /*!<DATAST [3:0] bits (Data-phase duration) */
16238 #define FMC_BTR1_DATAST_0          (0x01U << FMC_BTR1_DATAST_Pos)              /*!< 0x00000100 */
16239 #define FMC_BTR1_DATAST_1          (0x02U << FMC_BTR1_DATAST_Pos)              /*!< 0x00000200 */
16240 #define FMC_BTR1_DATAST_2          (0x04U << FMC_BTR1_DATAST_Pos)              /*!< 0x00000400 */
16241 #define FMC_BTR1_DATAST_3          (0x08U << FMC_BTR1_DATAST_Pos)              /*!< 0x00000800 */
16242 #define FMC_BTR1_DATAST_4          (0x10U << FMC_BTR1_DATAST_Pos)              /*!< 0x00001000 */
16243 #define FMC_BTR1_DATAST_5          (0x20U << FMC_BTR1_DATAST_Pos)              /*!< 0x00002000 */
16244 #define FMC_BTR1_DATAST_6          (0x40U << FMC_BTR1_DATAST_Pos)              /*!< 0x00004000 */
16245 #define FMC_BTR1_DATAST_7          (0x80U << FMC_BTR1_DATAST_Pos)              /*!< 0x00008000 */
16246 
16247 #define FMC_BTR1_BUSTURN_Pos       (16U)
16248 #define FMC_BTR1_BUSTURN_Msk       (0xFU << FMC_BTR1_BUSTURN_Pos)              /*!< 0x000F0000 */
16249 #define FMC_BTR1_BUSTURN           FMC_BTR1_BUSTURN_Msk                        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
16250 #define FMC_BTR1_BUSTURN_0         (0x1U << FMC_BTR1_BUSTURN_Pos)              /*!< 0x00010000 */
16251 #define FMC_BTR1_BUSTURN_1         (0x2U << FMC_BTR1_BUSTURN_Pos)              /*!< 0x00020000 */
16252 #define FMC_BTR1_BUSTURN_2         (0x4U << FMC_BTR1_BUSTURN_Pos)              /*!< 0x00040000 */
16253 #define FMC_BTR1_BUSTURN_3         (0x8U << FMC_BTR1_BUSTURN_Pos)              /*!< 0x00080000 */
16254 
16255 #define FMC_BTR1_CLKDIV_Pos        (20U)
16256 #define FMC_BTR1_CLKDIV_Msk        (0xFU << FMC_BTR1_CLKDIV_Pos)               /*!< 0x00F00000 */
16257 #define FMC_BTR1_CLKDIV            FMC_BTR1_CLKDIV_Msk                         /*!<CLKDIV[3:0] bits (Clock divide ratio) */
16258 #define FMC_BTR1_CLKDIV_0          (0x1U << FMC_BTR1_CLKDIV_Pos)               /*!< 0x00100000 */
16259 #define FMC_BTR1_CLKDIV_1          (0x2U << FMC_BTR1_CLKDIV_Pos)               /*!< 0x00200000 */
16260 #define FMC_BTR1_CLKDIV_2          (0x4U << FMC_BTR1_CLKDIV_Pos)               /*!< 0x00400000 */
16261 #define FMC_BTR1_CLKDIV_3          (0x8U << FMC_BTR1_CLKDIV_Pos)               /*!< 0x00800000 */
16262 
16263 #define FMC_BTR1_DATLAT_Pos        (24U)
16264 #define FMC_BTR1_DATLAT_Msk        (0xFU << FMC_BTR1_DATLAT_Pos)               /*!< 0x0F000000 */
16265 #define FMC_BTR1_DATLAT            FMC_BTR1_DATLAT_Msk                         /*!<DATLA[3:0] bits (Data latency) */
16266 #define FMC_BTR1_DATLAT_0          (0x1U << FMC_BTR1_DATLAT_Pos)               /*!< 0x01000000 */
16267 #define FMC_BTR1_DATLAT_1          (0x2U << FMC_BTR1_DATLAT_Pos)               /*!< 0x02000000 */
16268 #define FMC_BTR1_DATLAT_2          (0x4U << FMC_BTR1_DATLAT_Pos)               /*!< 0x04000000 */
16269 #define FMC_BTR1_DATLAT_3          (0x8U << FMC_BTR1_DATLAT_Pos)               /*!< 0x08000000 */
16270 
16271 #define FMC_BTR1_ACCMOD_Pos        (28U)
16272 #define FMC_BTR1_ACCMOD_Msk        (0x3U << FMC_BTR1_ACCMOD_Pos)               /*!< 0x30000000 */
16273 #define FMC_BTR1_ACCMOD            FMC_BTR1_ACCMOD_Msk                         /*!<ACCMOD[1:0] bits (Access mode) */
16274 #define FMC_BTR1_ACCMOD_0          (0x1U << FMC_BTR1_ACCMOD_Pos)               /*!< 0x10000000 */
16275 #define FMC_BTR1_ACCMOD_1          (0x2U << FMC_BTR1_ACCMOD_Pos)               /*!< 0x20000000 */
16276 
16277 #define FMC_BTR1_DATAHLD_Pos       (30U)
16278 #define FMC_BTR1_DATAHLD_Msk       (0x3U << FMC_BTR1_DATAHLD_Pos)              /*!< 0xC0000000 */
16279 #define FMC_BTR1_DATAHLD           FMC_BTR1_DATAHLD_Msk                        /*!<DATAHLD[1:0] bits (Data Hold phase duration) */
16280 #define FMC_BTR1_DATAHLD_0         (0x1U << FMC_BTR1_DATAHLD_Pos)              /*!< 0x40000000 */
16281 #define FMC_BTR1_DATAHLD_1         (0x2U << FMC_BTR1_DATAHLD_Pos)              /*!< 0x80000000 */
16282 
16283 /******************  Bit definition for FMC_BTR2 register  *******************/
16284 #define FMC_BTR2_ADDSET_Pos        (0U)
16285 #define FMC_BTR2_ADDSET_Msk        (0xFU << FMC_BTR2_ADDSET_Pos)               /*!< 0x0000000F */
16286 #define FMC_BTR2_ADDSET            FMC_BTR2_ADDSET_Msk                         /*!<ADDSET[3:0] bits (Address setup phase duration) */
16287 #define FMC_BTR2_ADDSET_0          (0x1U << FMC_BTR2_ADDSET_Pos)               /*!< 0x00000001 */
16288 #define FMC_BTR2_ADDSET_1          (0x2U << FMC_BTR2_ADDSET_Pos)               /*!< 0x00000002 */
16289 #define FMC_BTR2_ADDSET_2          (0x4U << FMC_BTR2_ADDSET_Pos)               /*!< 0x00000004 */
16290 #define FMC_BTR2_ADDSET_3          (0x8U << FMC_BTR2_ADDSET_Pos)               /*!< 0x00000008 */
16291 
16292 #define FMC_BTR2_ADDHLD_Pos        (4U)
16293 #define FMC_BTR2_ADDHLD_Msk        (0xFU << FMC_BTR2_ADDHLD_Pos)               /*!< 0x000000F0 */
16294 #define FMC_BTR2_ADDHLD            FMC_BTR2_ADDHLD_Msk                         /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
16295 #define FMC_BTR2_ADDHLD_0          (0x1U << FMC_BTR2_ADDHLD_Pos)               /*!< 0x00000010 */
16296 #define FMC_BTR2_ADDHLD_1          (0x2U << FMC_BTR2_ADDHLD_Pos)               /*!< 0x00000020 */
16297 #define FMC_BTR2_ADDHLD_2          (0x4U << FMC_BTR2_ADDHLD_Pos)               /*!< 0x00000040 */
16298 #define FMC_BTR2_ADDHLD_3          (0x8U << FMC_BTR2_ADDHLD_Pos)               /*!< 0x00000080 */
16299 
16300 #define FMC_BTR2_DATAST_Pos        (8U)
16301 #define FMC_BTR2_DATAST_Msk        (0xFFU << FMC_BTR2_DATAST_Pos)              /*!< 0x0000FF00 */
16302 #define FMC_BTR2_DATAST            FMC_BTR2_DATAST_Msk                         /*!<DATAST [3:0] bits (Data-phase duration) */
16303 #define FMC_BTR2_DATAST_0          (0x01U << FMC_BTR2_DATAST_Pos)              /*!< 0x00000100 */
16304 #define FMC_BTR2_DATAST_1          (0x02U << FMC_BTR2_DATAST_Pos)              /*!< 0x00000200 */
16305 #define FMC_BTR2_DATAST_2          (0x04U << FMC_BTR2_DATAST_Pos)              /*!< 0x00000400 */
16306 #define FMC_BTR2_DATAST_3          (0x08U << FMC_BTR2_DATAST_Pos)              /*!< 0x00000800 */
16307 #define FMC_BTR2_DATAST_4          (0x10U << FMC_BTR2_DATAST_Pos)              /*!< 0x00001000 */
16308 #define FMC_BTR2_DATAST_5          (0x20U << FMC_BTR2_DATAST_Pos)              /*!< 0x00002000 */
16309 #define FMC_BTR2_DATAST_6          (0x40U << FMC_BTR2_DATAST_Pos)              /*!< 0x00004000 */
16310 #define FMC_BTR2_DATAST_7          (0x80U << FMC_BTR2_DATAST_Pos)              /*!< 0x00008000 */
16311 
16312 #define FMC_BTR2_BUSTURN_Pos       (16U)
16313 #define FMC_BTR2_BUSTURN_Msk       (0xFU << FMC_BTR2_BUSTURN_Pos)              /*!< 0x000F0000 */
16314 #define FMC_BTR2_BUSTURN           FMC_BTR2_BUSTURN_Msk                        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
16315 #define FMC_BTR2_BUSTURN_0         (0x1U << FMC_BTR2_BUSTURN_Pos)              /*!< 0x00010000 */
16316 #define FMC_BTR2_BUSTURN_1         (0x2U << FMC_BTR2_BUSTURN_Pos)              /*!< 0x00020000 */
16317 #define FMC_BTR2_BUSTURN_2         (0x4U << FMC_BTR2_BUSTURN_Pos)              /*!< 0x00040000 */
16318 #define FMC_BTR2_BUSTURN_3         (0x8U << FMC_BTR2_BUSTURN_Pos)              /*!< 0x00080000 */
16319 
16320 #define FMC_BTR2_CLKDIV_Pos        (20U)
16321 #define FMC_BTR2_CLKDIV_Msk        (0xFU << FMC_BTR2_CLKDIV_Pos)               /*!< 0x00F00000 */
16322 #define FMC_BTR2_CLKDIV            FMC_BTR2_CLKDIV_Msk                         /*!<CLKDIV[3:0] bits (Clock divide ratio) */
16323 #define FMC_BTR2_CLKDIV_0          (0x1U << FMC_BTR2_CLKDIV_Pos)               /*!< 0x00100000 */
16324 #define FMC_BTR2_CLKDIV_1          (0x2U << FMC_BTR2_CLKDIV_Pos)               /*!< 0x00200000 */
16325 #define FMC_BTR2_CLKDIV_2          (0x4U << FMC_BTR2_CLKDIV_Pos)               /*!< 0x00400000 */
16326 #define FMC_BTR2_CLKDIV_3          (0x8U << FMC_BTR2_CLKDIV_Pos)               /*!< 0x00800000 */
16327 
16328 #define FMC_BTR2_DATLAT_Pos        (24U)
16329 #define FMC_BTR2_DATLAT_Msk        (0xFU << FMC_BTR2_DATLAT_Pos)               /*!< 0x0F000000 */
16330 #define FMC_BTR2_DATLAT            FMC_BTR2_DATLAT_Msk                         /*!<DATLA[3:0] bits (Data latency) */
16331 #define FMC_BTR2_DATLAT_0          (0x1U << FMC_BTR2_DATLAT_Pos)               /*!< 0x01000000 */
16332 #define FMC_BTR2_DATLAT_1          (0x2U << FMC_BTR2_DATLAT_Pos)               /*!< 0x02000000 */
16333 #define FMC_BTR2_DATLAT_2          (0x4U << FMC_BTR2_DATLAT_Pos)               /*!< 0x04000000 */
16334 #define FMC_BTR2_DATLAT_3          (0x8U << FMC_BTR2_DATLAT_Pos)               /*!< 0x08000000 */
16335 
16336 #define FMC_BTR2_ACCMOD_Pos        (28U)
16337 #define FMC_BTR2_ACCMOD_Msk        (0x3U << FMC_BTR2_ACCMOD_Pos)               /*!< 0x30000000 */
16338 #define FMC_BTR2_ACCMOD            FMC_BTR2_ACCMOD_Msk                         /*!<ACCMOD[1:0] bits (Access mode) */
16339 #define FMC_BTR2_ACCMOD_0          (0x1U << FMC_BTR2_ACCMOD_Pos)               /*!< 0x10000000 */
16340 #define FMC_BTR2_ACCMOD_1          (0x2U << FMC_BTR2_ACCMOD_Pos)               /*!< 0x20000000 */
16341 
16342 #define FMC_BTR2_DATAHLD_Pos       (30U)
16343 #define FMC_BTR2_DATAHLD_Msk       (0x3U << FMC_BTR2_DATAHLD_Pos)              /*!< 0xC0000000 */
16344 #define FMC_BTR2_DATAHLD           FMC_BTR2_DATAHLD_Msk                        /*!<DATAHLD[1:0] bits (Data Hold phase duration) */
16345 #define FMC_BTR2_DATAHLD_0         (0x1U << FMC_BTR2_DATAHLD_Pos)              /*!< 0x40000000 */
16346 #define FMC_BTR2_DATAHLD_1         (0x2U << FMC_BTR2_DATAHLD_Pos)              /*!< 0x80000000 */
16347 
16348 /*******************  Bit definition for FMC_BTR3 register  *******************/
16349 #define FMC_BTR3_ADDSET_Pos        (0U)
16350 #define FMC_BTR3_ADDSET_Msk        (0xFU << FMC_BTR3_ADDSET_Pos)               /*!< 0x0000000F */
16351 #define FMC_BTR3_ADDSET            FMC_BTR3_ADDSET_Msk                         /*!<ADDSET[3:0] bits (Address setup phase duration) */
16352 #define FMC_BTR3_ADDSET_0          (0x1U << FMC_BTR3_ADDSET_Pos)               /*!< 0x00000001 */
16353 #define FMC_BTR3_ADDSET_1          (0x2U << FMC_BTR3_ADDSET_Pos)               /*!< 0x00000002 */
16354 #define FMC_BTR3_ADDSET_2          (0x4U << FMC_BTR3_ADDSET_Pos)               /*!< 0x00000004 */
16355 #define FMC_BTR3_ADDSET_3          (0x8U << FMC_BTR3_ADDSET_Pos)               /*!< 0x00000008 */
16356 
16357 #define FMC_BTR3_ADDHLD_Pos        (4U)
16358 #define FMC_BTR3_ADDHLD_Msk        (0xFU << FMC_BTR3_ADDHLD_Pos)               /*!< 0x000000F0 */
16359 #define FMC_BTR3_ADDHLD            FMC_BTR3_ADDHLD_Msk                         /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
16360 #define FMC_BTR3_ADDHLD_0          (0x1U << FMC_BTR3_ADDHLD_Pos)               /*!< 0x00000010 */
16361 #define FMC_BTR3_ADDHLD_1          (0x2U << FMC_BTR3_ADDHLD_Pos)               /*!< 0x00000020 */
16362 #define FMC_BTR3_ADDHLD_2          (0x4U << FMC_BTR3_ADDHLD_Pos)               /*!< 0x00000040 */
16363 #define FMC_BTR3_ADDHLD_3          (0x8U << FMC_BTR3_ADDHLD_Pos)               /*!< 0x00000080 */
16364 
16365 #define FMC_BTR3_DATAST_Pos        (8U)
16366 #define FMC_BTR3_DATAST_Msk        (0xFFU << FMC_BTR3_DATAST_Pos)              /*!< 0x0000FF00 */
16367 #define FMC_BTR3_DATAST            FMC_BTR3_DATAST_Msk                         /*!<DATAST [3:0] bits (Data-phase duration) */
16368 #define FMC_BTR3_DATAST_0          (0x01U << FMC_BTR3_DATAST_Pos)              /*!< 0x00000100 */
16369 #define FMC_BTR3_DATAST_1          (0x02U << FMC_BTR3_DATAST_Pos)              /*!< 0x00000200 */
16370 #define FMC_BTR3_DATAST_2          (0x04U << FMC_BTR3_DATAST_Pos)              /*!< 0x00000400 */
16371 #define FMC_BTR3_DATAST_3          (0x08U << FMC_BTR3_DATAST_Pos)              /*!< 0x00000800 */
16372 #define FMC_BTR3_DATAST_4          (0x10U << FMC_BTR3_DATAST_Pos)              /*!< 0x00001000 */
16373 #define FMC_BTR3_DATAST_5          (0x20U << FMC_BTR3_DATAST_Pos)              /*!< 0x00002000 */
16374 #define FMC_BTR3_DATAST_6          (0x40U << FMC_BTR3_DATAST_Pos)              /*!< 0x00004000 */
16375 #define FMC_BTR3_DATAST_7          (0x80U << FMC_BTR3_DATAST_Pos)              /*!< 0x00008000 */
16376 
16377 #define FMC_BTR3_BUSTURN_Pos       (16U)
16378 #define FMC_BTR3_BUSTURN_Msk       (0xFU << FMC_BTR3_BUSTURN_Pos)              /*!< 0x000F0000 */
16379 #define FMC_BTR3_BUSTURN           FMC_BTR3_BUSTURN_Msk                        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
16380 #define FMC_BTR3_BUSTURN_0         (0x1U << FMC_BTR3_BUSTURN_Pos)              /*!< 0x00010000 */
16381 #define FMC_BTR3_BUSTURN_1         (0x2U << FMC_BTR3_BUSTURN_Pos)              /*!< 0x00020000 */
16382 #define FMC_BTR3_BUSTURN_2         (0x4U << FMC_BTR3_BUSTURN_Pos)              /*!< 0x00040000 */
16383 #define FMC_BTR3_BUSTURN_3         (0x8U << FMC_BTR3_BUSTURN_Pos)              /*!< 0x00080000 */
16384 
16385 #define FMC_BTR3_CLKDIV_Pos        (20U)
16386 #define FMC_BTR3_CLKDIV_Msk        (0xFU << FMC_BTR3_CLKDIV_Pos)               /*!< 0x00F00000 */
16387 #define FMC_BTR3_CLKDIV            FMC_BTR3_CLKDIV_Msk                         /*!<CLKDIV[3:0] bits (Clock divide ratio) */
16388 #define FMC_BTR3_CLKDIV_0          (0x1U << FMC_BTR3_CLKDIV_Pos)               /*!< 0x00100000 */
16389 #define FMC_BTR3_CLKDIV_1          (0x2U << FMC_BTR3_CLKDIV_Pos)               /*!< 0x00200000 */
16390 #define FMC_BTR3_CLKDIV_2          (0x4U << FMC_BTR3_CLKDIV_Pos)               /*!< 0x00400000 */
16391 #define FMC_BTR3_CLKDIV_3          (0x8U << FMC_BTR3_CLKDIV_Pos)               /*!< 0x00800000 */
16392 
16393 #define FMC_BTR3_DATLAT_Pos        (24U)
16394 #define FMC_BTR3_DATLAT_Msk        (0xFU << FMC_BTR3_DATLAT_Pos)               /*!< 0x0F000000 */
16395 #define FMC_BTR3_DATLAT            FMC_BTR3_DATLAT_Msk                         /*!<DATLA[3:0] bits (Data latency) */
16396 #define FMC_BTR3_DATLAT_0          (0x1U << FMC_BTR3_DATLAT_Pos)               /*!< 0x01000000 */
16397 #define FMC_BTR3_DATLAT_1          (0x2U << FMC_BTR3_DATLAT_Pos)               /*!< 0x02000000 */
16398 #define FMC_BTR3_DATLAT_2          (0x4U << FMC_BTR3_DATLAT_Pos)               /*!< 0x04000000 */
16399 #define FMC_BTR3_DATLAT_3          (0x8U << FMC_BTR3_DATLAT_Pos)               /*!< 0x08000000 */
16400 
16401 #define FMC_BTR3_ACCMOD_Pos        (28U)
16402 #define FMC_BTR3_ACCMOD_Msk        (0x3U << FMC_BTR3_ACCMOD_Pos)               /*!< 0x30000000 */
16403 #define FMC_BTR3_ACCMOD            FMC_BTR3_ACCMOD_Msk                         /*!<ACCMOD[1:0] bits (Access mode) */
16404 #define FMC_BTR3_ACCMOD_0          (0x1U << FMC_BTR3_ACCMOD_Pos)               /*!< 0x10000000 */
16405 #define FMC_BTR3_ACCMOD_1          (0x2U << FMC_BTR3_ACCMOD_Pos)               /*!< 0x20000000 */
16406 
16407 #define FMC_BTR3_DATAHLD_Pos       (30U)
16408 #define FMC_BTR3_DATAHLD_Msk       (0x3U << FMC_BTR3_DATAHLD_Pos)              /*!< 0xC0000000 */
16409 #define FMC_BTR3_DATAHLD           FMC_BTR3_DATAHLD_Msk                        /*!<DATAHLD[1:0] bits (Data Hold phase duration) */
16410 #define FMC_BTR3_DATAHLD_0         (0x1U << FMC_BTR3_DATAHLD_Pos)              /*!< 0x40000000 */
16411 #define FMC_BTR3_DATAHLD_1         (0x2U << FMC_BTR3_DATAHLD_Pos)              /*!< 0x80000000 */
16412 
16413 /******************  Bit definition for FMC_BTR4 register  *******************/
16414 #define FMC_BTR4_ADDSET_Pos        (0U)
16415 #define FMC_BTR4_ADDSET_Msk        (0xFU << FMC_BTR4_ADDSET_Pos)               /*!< 0x0000000F */
16416 #define FMC_BTR4_ADDSET            FMC_BTR4_ADDSET_Msk                         /*!<ADDSET[3:0] bits (Address setup phase duration) */
16417 #define FMC_BTR4_ADDSET_0          (0x1U << FMC_BTR4_ADDSET_Pos)               /*!< 0x00000001 */
16418 #define FMC_BTR4_ADDSET_1          (0x2U << FMC_BTR4_ADDSET_Pos)               /*!< 0x00000002 */
16419 #define FMC_BTR4_ADDSET_2          (0x4U << FMC_BTR4_ADDSET_Pos)               /*!< 0x00000004 */
16420 #define FMC_BTR4_ADDSET_3          (0x8U << FMC_BTR4_ADDSET_Pos)               /*!< 0x00000008 */
16421 
16422 #define FMC_BTR4_ADDHLD_Pos        (4U)
16423 #define FMC_BTR4_ADDHLD_Msk        (0xFU << FMC_BTR4_ADDHLD_Pos)               /*!< 0x000000F0 */
16424 #define FMC_BTR4_ADDHLD            FMC_BTR4_ADDHLD_Msk                         /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
16425 #define FMC_BTR4_ADDHLD_0          (0x1U << FMC_BTR4_ADDHLD_Pos)               /*!< 0x00000010 */
16426 #define FMC_BTR4_ADDHLD_1          (0x2U << FMC_BTR4_ADDHLD_Pos)               /*!< 0x00000020 */
16427 #define FMC_BTR4_ADDHLD_2          (0x4U << FMC_BTR4_ADDHLD_Pos)               /*!< 0x00000040 */
16428 #define FMC_BTR4_ADDHLD_3          (0x8U << FMC_BTR4_ADDHLD_Pos)               /*!< 0x00000080 */
16429 
16430 #define FMC_BTR4_DATAST_Pos        (8U)
16431 #define FMC_BTR4_DATAST_Msk        (0xFFU << FMC_BTR4_DATAST_Pos)              /*!< 0x0000FF00 */
16432 #define FMC_BTR4_DATAST            FMC_BTR4_DATAST_Msk                         /*!<DATAST [3:0] bits (Data-phase duration) */
16433 #define FMC_BTR4_DATAST_0          (0x01U << FMC_BTR4_DATAST_Pos)              /*!< 0x00000100 */
16434 #define FMC_BTR4_DATAST_1          (0x02U << FMC_BTR4_DATAST_Pos)              /*!< 0x00000200 */
16435 #define FMC_BTR4_DATAST_2          (0x04U << FMC_BTR4_DATAST_Pos)              /*!< 0x00000400 */
16436 #define FMC_BTR4_DATAST_3          (0x08U << FMC_BTR4_DATAST_Pos)              /*!< 0x00000800 */
16437 #define FMC_BTR4_DATAST_4          (0x10U << FMC_BTR4_DATAST_Pos)              /*!< 0x00001000 */
16438 #define FMC_BTR4_DATAST_5          (0x20U << FMC_BTR4_DATAST_Pos)              /*!< 0x00002000 */
16439 #define FMC_BTR4_DATAST_6          (0x40U << FMC_BTR4_DATAST_Pos)              /*!< 0x00004000 */
16440 #define FMC_BTR4_DATAST_7          (0x80U << FMC_BTR4_DATAST_Pos)              /*!< 0x00008000 */
16441 
16442 #define FMC_BTR4_BUSTURN_Pos       (16U)
16443 #define FMC_BTR4_BUSTURN_Msk       (0xFU << FMC_BTR4_BUSTURN_Pos)              /*!< 0x000F0000 */
16444 #define FMC_BTR4_BUSTURN           FMC_BTR4_BUSTURN_Msk                        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
16445 #define FMC_BTR4_BUSTURN_0         (0x1U << FMC_BTR4_BUSTURN_Pos)              /*!< 0x00010000 */
16446 #define FMC_BTR4_BUSTURN_1         (0x2U << FMC_BTR4_BUSTURN_Pos)              /*!< 0x00020000 */
16447 #define FMC_BTR4_BUSTURN_2         (0x4U << FMC_BTR4_BUSTURN_Pos)              /*!< 0x00040000 */
16448 #define FMC_BTR4_BUSTURN_3         (0x8U << FMC_BTR4_BUSTURN_Pos)              /*!< 0x00080000 */
16449 
16450 #define FMC_BTR4_CLKDIV_Pos        (20U)
16451 #define FMC_BTR4_CLKDIV_Msk        (0xFU << FMC_BTR4_CLKDIV_Pos)               /*!< 0x00F00000 */
16452 #define FMC_BTR4_CLKDIV            FMC_BTR4_CLKDIV_Msk                         /*!<CLKDIV[3:0] bits (Clock divide ratio) */
16453 #define FMC_BTR4_CLKDIV_0          (0x1U << FMC_BTR4_CLKDIV_Pos)               /*!< 0x00100000 */
16454 #define FMC_BTR4_CLKDIV_1          (0x2U << FMC_BTR4_CLKDIV_Pos)               /*!< 0x00200000 */
16455 #define FMC_BTR4_CLKDIV_2          (0x4U << FMC_BTR4_CLKDIV_Pos)               /*!< 0x00400000 */
16456 #define FMC_BTR4_CLKDIV_3          (0x8U << FMC_BTR4_CLKDIV_Pos)               /*!< 0x00800000 */
16457 
16458 #define FMC_BTR4_DATLAT_Pos        (24U)
16459 #define FMC_BTR4_DATLAT_Msk        (0xFU << FMC_BTR4_DATLAT_Pos)               /*!< 0x0F000000 */
16460 #define FMC_BTR4_DATLAT            FMC_BTR4_DATLAT_Msk                         /*!<DATLA[3:0] bits (Data latency) */
16461 #define FMC_BTR4_DATLAT_0          (0x1U << FMC_BTR4_DATLAT_Pos)               /*!< 0x01000000 */
16462 #define FMC_BTR4_DATLAT_1          (0x2U << FMC_BTR4_DATLAT_Pos)               /*!< 0x02000000 */
16463 #define FMC_BTR4_DATLAT_2          (0x4U << FMC_BTR4_DATLAT_Pos)               /*!< 0x04000000 */
16464 #define FMC_BTR4_DATLAT_3          (0x8U << FMC_BTR4_DATLAT_Pos)               /*!< 0x08000000 */
16465 
16466 #define FMC_BTR4_ACCMOD_Pos        (28U)
16467 #define FMC_BTR4_ACCMOD_Msk        (0x3U << FMC_BTR4_ACCMOD_Pos)               /*!< 0x30000000 */
16468 #define FMC_BTR4_ACCMOD            FMC_BTR4_ACCMOD_Msk                         /*!<ACCMOD[1:0] bits (Access mode) */
16469 #define FMC_BTR4_ACCMOD_0          (0x1U << FMC_BTR4_ACCMOD_Pos)               /*!< 0x10000000 */
16470 #define FMC_BTR4_ACCMOD_1          (0x2U << FMC_BTR4_ACCMOD_Pos)               /*!< 0x20000000 */
16471 
16472 #define FMC_BTR4_DATAHLD_Pos       (30U)
16473 #define FMC_BTR4_DATAHLD_Msk       (0x3U << FMC_BTR4_DATAHLD_Pos)              /*!< 0xC0000000 */
16474 #define FMC_BTR4_DATAHLD           FMC_BTR4_DATAHLD_Msk                        /*!<DATAHLD[1:0] bits (Data Hold phase duration) */
16475 #define FMC_BTR4_DATAHLD_0         (0x1U << FMC_BTR4_DATAHLD_Pos)              /*!< 0x40000000 */
16476 #define FMC_BTR4_DATAHLD_1         (0x2U << FMC_BTR4_DATAHLD_Pos)              /*!< 0x80000000 */
16477 
16478 /******************  Bit definition for FMC_PCSCNTR register  *****************/
16479 #define FMC_PCSCNTR_CSCOUNT_Pos        (0U)
16480 #define FMC_PCSCNTR_CSCOUNT_Msk        (0xFFFFU << FMC_PCSCNTR_CSCOUNT_Pos)    /*!< 0x0000FFFF */
16481 #define FMC_PCSCNTR_CSCOUNT            FMC_PCSCNTR_CSCOUNT_Msk                 /*!<CSCOUNT[15:0] bits Chip Select (CS) counter */
16482 
16483 #define FMC_PCSCNTR_CNTB1EN_Pos        (16U)
16484 #define FMC_PCSCNTR_CNTB1EN_Msk        (0x1U << FMC_PCSCNTR_CNTB1EN_Pos)       /*!< 0x00010000 */
16485 #define FMC_PCSCNTR_CNTB1EN            FMC_PCSCNTR_CNTB1EN_Msk                 /*!<CNTB1EN bit Counter Bank1 enable */
16486 
16487 #define FMC_PCSCNTR_CNTB2EN_Pos        (17U)
16488 #define FMC_PCSCNTR_CNTB2EN_Msk        (0x1U << FMC_PCSCNTR_CNTB2EN_Pos)       /*!< 0x00020000 */
16489 #define FMC_PCSCNTR_CNTB2EN            FMC_PCSCNTR_CNTB2EN_Msk                 /*!<CNTB2EN bit Counter Bank2 enable */
16490 
16491 #define FMC_PCSCNTR_CNTB3EN_Pos        (18U)
16492 #define FMC_PCSCNTR_CNTB3EN_Msk        (0x1U << FMC_PCSCNTR_CNTB3EN_Pos)       /*!< 0x00040000 */
16493 #define FMC_PCSCNTR_CNTB3EN            FMC_PCSCNTR_CNTB3EN_Msk                 /*!<CNTB3EN bit Counter Bank3 enable */
16494 
16495 #define FMC_PCSCNTR_CNTB4EN_Pos        (19U)
16496 #define FMC_PCSCNTR_CNTB4EN_Msk        (0x1U << FMC_PCSCNTR_CNTB4EN_Pos)       /*!< 0x00080000 */
16497 #define FMC_PCSCNTR_CNTB4EN            FMC_PCSCNTR_CNTB4EN_Msk                 /*!<CNTB4EN bit Counter Bank4 enable */
16498 
16499 /******************  Bit definition for FMC_BWTR1 register  ******************/
16500 #define FMC_BWTR1_ADDSET_Pos       (0U)
16501 #define FMC_BWTR1_ADDSET_Msk       (0xFU << FMC_BWTR1_ADDSET_Pos)              /*!< 0x0000000F */
16502 #define FMC_BWTR1_ADDSET           FMC_BWTR1_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
16503 #define FMC_BWTR1_ADDSET_0         (0x1U << FMC_BWTR1_ADDSET_Pos)              /*!< 0x00000001 */
16504 #define FMC_BWTR1_ADDSET_1         (0x2U << FMC_BWTR1_ADDSET_Pos)              /*!< 0x00000002 */
16505 #define FMC_BWTR1_ADDSET_2         (0x4U << FMC_BWTR1_ADDSET_Pos)              /*!< 0x00000004 */
16506 #define FMC_BWTR1_ADDSET_3         (0x8U << FMC_BWTR1_ADDSET_Pos)              /*!< 0x00000008 */
16507 
16508 #define FMC_BWTR1_ADDHLD_Pos       (4U)
16509 #define FMC_BWTR1_ADDHLD_Msk       (0xFU << FMC_BWTR1_ADDHLD_Pos)              /*!< 0x000000F0 */
16510 #define FMC_BWTR1_ADDHLD           FMC_BWTR1_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
16511 #define FMC_BWTR1_ADDHLD_0         (0x1U << FMC_BWTR1_ADDHLD_Pos)              /*!< 0x00000010 */
16512 #define FMC_BWTR1_ADDHLD_1         (0x2U << FMC_BWTR1_ADDHLD_Pos)              /*!< 0x00000020 */
16513 #define FMC_BWTR1_ADDHLD_2         (0x4U << FMC_BWTR1_ADDHLD_Pos)              /*!< 0x00000040 */
16514 #define FMC_BWTR1_ADDHLD_3         (0x8U << FMC_BWTR1_ADDHLD_Pos)              /*!< 0x00000080 */
16515 
16516 #define FMC_BWTR1_DATAST_Pos       (8U)
16517 #define FMC_BWTR1_DATAST_Msk       (0xFFU << FMC_BWTR1_DATAST_Pos)             /*!< 0x0000FF00 */
16518 #define FMC_BWTR1_DATAST           FMC_BWTR1_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
16519 #define FMC_BWTR1_DATAST_0         (0x01U << FMC_BWTR1_DATAST_Pos)             /*!< 0x00000100 */
16520 #define FMC_BWTR1_DATAST_1         (0x02U << FMC_BWTR1_DATAST_Pos)             /*!< 0x00000200 */
16521 #define FMC_BWTR1_DATAST_2         (0x04U << FMC_BWTR1_DATAST_Pos)             /*!< 0x00000400 */
16522 #define FMC_BWTR1_DATAST_3         (0x08U << FMC_BWTR1_DATAST_Pos)             /*!< 0x00000800 */
16523 #define FMC_BWTR1_DATAST_4         (0x10U << FMC_BWTR1_DATAST_Pos)             /*!< 0x00001000 */
16524 #define FMC_BWTR1_DATAST_5         (0x20U << FMC_BWTR1_DATAST_Pos)             /*!< 0x00002000 */
16525 #define FMC_BWTR1_DATAST_6         (0x40U << FMC_BWTR1_DATAST_Pos)             /*!< 0x00004000 */
16526 #define FMC_BWTR1_DATAST_7         (0x80U << FMC_BWTR1_DATAST_Pos)             /*!< 0x00008000 */
16527 
16528 #define FMC_BWTR1_CLKDIV_Pos       (20U)
16529 #define FMC_BWTR1_CLKDIV_Msk       (0xFU << FMC_BWTR1_CLKDIV_Pos)              /*!< 0x00F00000 */
16530 #define FMC_BWTR1_CLKDIV           FMC_BWTR1_CLKDIV_Msk                        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
16531 #define FMC_BWTR1_CLKDIV_0         (0x1U << FMC_BWTR1_CLKDIV_Pos)              /*!< 0x00100000 */
16532 #define FMC_BWTR1_CLKDIV_1         (0x2U << FMC_BWTR1_CLKDIV_Pos)              /*!< 0x00200000 */
16533 #define FMC_BWTR1_CLKDIV_2         (0x4U << FMC_BWTR1_CLKDIV_Pos)              /*!< 0x00400000 */
16534 #define FMC_BWTR1_CLKDIV_3         (0x8U << FMC_BWTR1_CLKDIV_Pos)              /*!< 0x00800000 */
16535 
16536 #define FMC_BWTR1_DATLAT_Pos       (24U)
16537 #define FMC_BWTR1_DATLAT_Msk       (0xFU << FMC_BWTR1_DATLAT_Pos)              /*!< 0x0F000000 */
16538 #define FMC_BWTR1_DATLAT           FMC_BWTR1_DATLAT_Msk                        /*!<DATLA[3:0] bits (Data latency) */
16539 #define FMC_BWTR1_DATLAT_0         (0x1U << FMC_BWTR1_DATLAT_Pos)              /*!< 0x01000000 */
16540 #define FMC_BWTR1_DATLAT_1         (0x2U << FMC_BWTR1_DATLAT_Pos)              /*!< 0x02000000 */
16541 #define FMC_BWTR1_DATLAT_2         (0x4U << FMC_BWTR1_DATLAT_Pos)              /*!< 0x04000000 */
16542 #define FMC_BWTR1_DATLAT_3         (0x8U << FMC_BWTR1_DATLAT_Pos)              /*!< 0x08000000 */
16543 
16544 #define FMC_BWTR1_BUSTURN_Pos      (16U)
16545 #define FMC_BWTR1_BUSTURN_Msk      (0xFU << FMC_BWTR1_BUSTURN_Pos)             /*!< 0x000F0000 */
16546 #define FMC_BWTR1_BUSTURN          FMC_BWTR1_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
16547 #define FMC_BWTR1_BUSTURN_0        (0x1U << FMC_BWTR1_BUSTURN_Pos)             /*!< 0x00010000 */
16548 #define FMC_BWTR1_BUSTURN_1        (0x2U << FMC_BWTR1_BUSTURN_Pos)             /*!< 0x00020000 */
16549 #define FMC_BWTR1_BUSTURN_2        (0x4U << FMC_BWTR1_BUSTURN_Pos)             /*!< 0x00040000 */
16550 #define FMC_BWTR1_BUSTURN_3        (0x8U << FMC_BWTR1_BUSTURN_Pos)             /*!< 0x00080000 */
16551 
16552 
16553 #define FMC_BWTR1_ACCMOD_Pos       (28U)
16554 #define FMC_BWTR1_ACCMOD_Msk       (0x3U << FMC_BWTR1_ACCMOD_Pos)              /*!< 0x30000000 */
16555 #define FMC_BWTR1_ACCMOD           FMC_BWTR1_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
16556 #define FMC_BWTR1_ACCMOD_0         (0x1U << FMC_BWTR1_ACCMOD_Pos)              /*!< 0x10000000 */
16557 #define FMC_BWTR1_ACCMOD_1         (0x2U << FMC_BWTR1_ACCMOD_Pos)              /*!< 0x20000000 */
16558 
16559 #define FMC_BWTR1_DATAHLD_Pos       (30U)
16560 #define FMC_BWTR1_DATAHLD_Msk       (0x3U << FMC_BWTR1_DATAHLD_Pos)            /*!< 0xC0000000 */
16561 #define FMC_BWTR1_DATAHLD           FMC_BWTR1_DATAHLD_Msk                      /*!<DATAHLD[1:0] bits (Data Hold phase duration) */
16562 #define FMC_BWTR1_DATAHLD_0         (0x1U << FMC_BWTR1_DATAHLD_Pos)            /*!< 0x40000000 */
16563 #define FMC_BWTR1_DATAHLD_1         (0x2U << FMC_BWTR1_DATAHLD_Pos)            /*!< 0x80000000 */
16564 
16565 /******************  Bit definition for FMC_BWTR2 register  ******************/
16566 #define FMC_BWTR2_ADDSET_Pos       (0U)
16567 #define FMC_BWTR2_ADDSET_Msk       (0xFU << FMC_BWTR2_ADDSET_Pos)              /*!< 0x0000000F */
16568 #define FMC_BWTR2_ADDSET           FMC_BWTR2_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
16569 #define FMC_BWTR2_ADDSET_0         (0x1U << FMC_BWTR2_ADDSET_Pos)              /*!< 0x00000001 */
16570 #define FMC_BWTR2_ADDSET_1         (0x2U << FMC_BWTR2_ADDSET_Pos)              /*!< 0x00000002 */
16571 #define FMC_BWTR2_ADDSET_2         (0x4U << FMC_BWTR2_ADDSET_Pos)              /*!< 0x00000004 */
16572 #define FMC_BWTR2_ADDSET_3         (0x8U << FMC_BWTR2_ADDSET_Pos)              /*!< 0x00000008 */
16573 
16574 #define FMC_BWTR2_ADDHLD_Pos       (4U)
16575 #define FMC_BWTR2_ADDHLD_Msk       (0xFU << FMC_BWTR2_ADDHLD_Pos)              /*!< 0x000000F0 */
16576 #define FMC_BWTR2_ADDHLD           FMC_BWTR2_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
16577 #define FMC_BWTR2_ADDHLD_0         (0x1U << FMC_BWTR2_ADDHLD_Pos)              /*!< 0x00000010 */
16578 #define FMC_BWTR2_ADDHLD_1         (0x2U << FMC_BWTR2_ADDHLD_Pos)              /*!< 0x00000020 */
16579 #define FMC_BWTR2_ADDHLD_2         (0x4U << FMC_BWTR2_ADDHLD_Pos)              /*!< 0x00000040 */
16580 #define FMC_BWTR2_ADDHLD_3         (0x8U << FMC_BWTR2_ADDHLD_Pos)              /*!< 0x00000080 */
16581 
16582 #define FMC_BWTR2_DATAST_Pos       (8U)
16583 #define FMC_BWTR2_DATAST_Msk       (0xFFU << FMC_BWTR2_DATAST_Pos)             /*!< 0x0000FF00 */
16584 #define FMC_BWTR2_DATAST           FMC_BWTR2_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
16585 #define FMC_BWTR2_DATAST_0         (0x01U << FMC_BWTR2_DATAST_Pos)             /*!< 0x00000100 */
16586 #define FMC_BWTR2_DATAST_1         (0x02U << FMC_BWTR2_DATAST_Pos)             /*!< 0x00000200 */
16587 #define FMC_BWTR2_DATAST_2         (0x04U << FMC_BWTR2_DATAST_Pos)             /*!< 0x00000400 */
16588 #define FMC_BWTR2_DATAST_3         (0x08U << FMC_BWTR2_DATAST_Pos)             /*!< 0x00000800 */
16589 #define FMC_BWTR2_DATAST_4         (0x10U << FMC_BWTR2_DATAST_Pos)             /*!< 0x00001000 */
16590 #define FMC_BWTR2_DATAST_5         (0x20U << FMC_BWTR2_DATAST_Pos)             /*!< 0x00002000 */
16591 #define FMC_BWTR2_DATAST_6         (0x40U << FMC_BWTR2_DATAST_Pos)             /*!< 0x00004000 */
16592 #define FMC_BWTR2_DATAST_7         (0x80U << FMC_BWTR2_DATAST_Pos)             /*!< 0x00008000 */
16593 
16594 #define FMC_BWTR2_CLKDIV_Pos       (20U)
16595 #define FMC_BWTR2_CLKDIV_Msk       (0xFU << FMC_BWTR2_CLKDIV_Pos)              /*!< 0x00F00000 */
16596 #define FMC_BWTR2_CLKDIV           FMC_BWTR2_CLKDIV_Msk                        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
16597 #define FMC_BWTR2_CLKDIV_0         (0x1U << FMC_BWTR2_CLKDIV_Pos)              /*!< 0x00100000 */
16598 #define FMC_BWTR2_CLKDIV_1         (0x2U << FMC_BWTR2_CLKDIV_Pos)              /*!< 0x00200000 */
16599 #define FMC_BWTR2_CLKDIV_2         (0x4U << FMC_BWTR2_CLKDIV_Pos)              /*!< 0x00400000 */
16600 #define FMC_BWTR2_CLKDIV_3         (0x8U << FMC_BWTR2_CLKDIV_Pos)              /*!< 0x00800000 */
16601 
16602 #define FMC_BWTR2_DATLAT_Pos       (24U)
16603 #define FMC_BWTR2_DATLAT_Msk       (0xFU << FMC_BWTR2_DATLAT_Pos)              /*!< 0x0F000000 */
16604 #define FMC_BWTR2_DATLAT           FMC_BWTR2_DATLAT_Msk                        /*!<DATLA[3:0] bits (Data latency) */
16605 #define FMC_BWTR2_DATLAT_0         (0x1U << FMC_BWTR2_DATLAT_Pos)              /*!< 0x01000000 */
16606 #define FMC_BWTR2_DATLAT_1         (0x2U << FMC_BWTR2_DATLAT_Pos)              /*!< 0x02000000 */
16607 #define FMC_BWTR2_DATLAT_2         (0x4U << FMC_BWTR2_DATLAT_Pos)              /*!< 0x04000000 */
16608 #define FMC_BWTR2_DATLAT_3         (0x8U << FMC_BWTR2_DATLAT_Pos)              /*!< 0x08000000 */
16609 
16610 #define FMC_BWTR2_ACCMOD_Pos       (28U)
16611 #define FMC_BWTR2_ACCMOD_Msk       (0x3U << FMC_BWTR2_ACCMOD_Pos)              /*!< 0x30000000 */
16612 #define FMC_BWTR2_ACCMOD           FMC_BWTR2_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
16613 #define FMC_BWTR2_ACCMOD_0         (0x1U << FMC_BWTR2_ACCMOD_Pos)              /*!< 0x10000000 */
16614 #define FMC_BWTR2_ACCMOD_1         (0x2U << FMC_BWTR2_ACCMOD_Pos)              /*!< 0x20000000 */
16615 
16616 #define FMC_BWTR2_DATAHLD_Pos       (30U)
16617 #define FMC_BWTR2_DATAHLD_Msk       (0x3U << FMC_BWTR2_DATAHLD_Pos)            /*!< 0xC0000000 */
16618 #define FMC_BWTR2_DATAHLD           FMC_BWTR2_DATAHLD_Msk                      /*!<DATAHLD[1:0] bits (Data Hold phase duration) */
16619 #define FMC_BWTR2_DATAHLD_0         (0x1U << FMC_BWTR2_DATAHLD_Pos)            /*!< 0x40000000 */
16620 #define FMC_BWTR2_DATAHLD_1         (0x2U << FMC_BWTR2_DATAHLD_Pos)            /*!< 0x80000000 */
16621 
16622 /******************  Bit definition for FMC_BWTR3 register  ******************/
16623 #define FMC_BWTR3_ADDSET_Pos       (0U)
16624 #define FMC_BWTR3_ADDSET_Msk       (0xFU << FMC_BWTR3_ADDSET_Pos)              /*!< 0x0000000F */
16625 #define FMC_BWTR3_ADDSET           FMC_BWTR3_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
16626 #define FMC_BWTR3_ADDSET_0         (0x1U << FMC_BWTR3_ADDSET_Pos)              /*!< 0x00000001 */
16627 #define FMC_BWTR3_ADDSET_1         (0x2U << FMC_BWTR3_ADDSET_Pos)              /*!< 0x00000002 */
16628 #define FMC_BWTR3_ADDSET_2         (0x4U << FMC_BWTR3_ADDSET_Pos)              /*!< 0x00000004 */
16629 #define FMC_BWTR3_ADDSET_3         (0x8U << FMC_BWTR3_ADDSET_Pos)              /*!< 0x00000008 */
16630 
16631 #define FMC_BWTR3_ADDHLD_Pos       (4U)
16632 #define FMC_BWTR3_ADDHLD_Msk       (0xFU << FMC_BWTR3_ADDHLD_Pos)              /*!< 0x000000F0 */
16633 #define FMC_BWTR3_ADDHLD           FMC_BWTR3_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
16634 #define FMC_BWTR3_ADDHLD_0         (0x1U << FMC_BWTR3_ADDHLD_Pos)              /*!< 0x00000010 */
16635 #define FMC_BWTR3_ADDHLD_1         (0x2U << FMC_BWTR3_ADDHLD_Pos)              /*!< 0x00000020 */
16636 #define FMC_BWTR3_ADDHLD_2         (0x4U << FMC_BWTR3_ADDHLD_Pos)              /*!< 0x00000040 */
16637 #define FMC_BWTR3_ADDHLD_3         (0x8U << FMC_BWTR3_ADDHLD_Pos)              /*!< 0x00000080 */
16638 
16639 #define FMC_BWTR3_DATAST_Pos       (8U)
16640 #define FMC_BWTR3_DATAST_Msk       (0xFFU << FMC_BWTR3_DATAST_Pos)             /*!< 0x0000FF00 */
16641 #define FMC_BWTR3_DATAST           FMC_BWTR3_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
16642 #define FMC_BWTR3_DATAST_0         (0x01U << FMC_BWTR3_DATAST_Pos)             /*!< 0x00000100 */
16643 #define FMC_BWTR3_DATAST_1         (0x02U << FMC_BWTR3_DATAST_Pos)             /*!< 0x00000200 */
16644 #define FMC_BWTR3_DATAST_2         (0x04U << FMC_BWTR3_DATAST_Pos)             /*!< 0x00000400 */
16645 #define FMC_BWTR3_DATAST_3         (0x08U << FMC_BWTR3_DATAST_Pos)             /*!< 0x00000800 */
16646 #define FMC_BWTR3_DATAST_4         (0x10U << FMC_BWTR3_DATAST_Pos)             /*!< 0x00001000 */
16647 #define FMC_BWTR3_DATAST_5         (0x20U << FMC_BWTR3_DATAST_Pos)             /*!< 0x00002000 */
16648 #define FMC_BWTR3_DATAST_6         (0x40U << FMC_BWTR3_DATAST_Pos)             /*!< 0x00004000 */
16649 #define FMC_BWTR3_DATAST_7         (0x80U << FMC_BWTR3_DATAST_Pos)             /*!< 0x00008000 */
16650 
16651 #define FMC_BWTR3_CLKDIV_Pos       (20U)
16652 #define FMC_BWTR3_CLKDIV_Msk       (0xFU << FMC_BWTR3_CLKDIV_Pos)              /*!< 0x00F00000 */
16653 #define FMC_BWTR3_CLKDIV           FMC_BWTR3_CLKDIV_Msk                        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
16654 #define FMC_BWTR3_CLKDIV_0         (0x1U << FMC_BWTR3_CLKDIV_Pos)              /*!< 0x00100000 */
16655 #define FMC_BWTR3_CLKDIV_1         (0x2U << FMC_BWTR3_CLKDIV_Pos)              /*!< 0x00200000 */
16656 #define FMC_BWTR3_CLKDIV_2         (0x4U << FMC_BWTR3_CLKDIV_Pos)              /*!< 0x00400000 */
16657 #define FMC_BWTR3_CLKDIV_3         (0x8U << FMC_BWTR3_CLKDIV_Pos)              /*!< 0x00800000 */
16658 
16659 #define FMC_BWTR3_DATLAT_Pos       (24U)
16660 #define FMC_BWTR3_DATLAT_Msk       (0xFU << FMC_BWTR3_DATLAT_Pos)              /*!< 0x0F000000 */
16661 #define FMC_BWTR3_DATLAT           FMC_BWTR3_DATLAT_Msk                        /*!<DATLA[3:0] bits (Data latency) */
16662 #define FMC_BWTR3_DATLAT_0         (0x1U << FMC_BWTR3_DATLAT_Pos)              /*!< 0x01000000 */
16663 #define FMC_BWTR3_DATLAT_1         (0x2U << FMC_BWTR3_DATLAT_Pos)              /*!< 0x02000000 */
16664 #define FMC_BWTR3_DATLAT_2         (0x4U << FMC_BWTR3_DATLAT_Pos)              /*!< 0x04000000 */
16665 #define FMC_BWTR3_DATLAT_3         (0x8U << FMC_BWTR3_DATLAT_Pos)              /*!< 0x08000000 */
16666 
16667 #define FMC_BWTR3_ACCMOD_Pos       (28U)
16668 #define FMC_BWTR3_ACCMOD_Msk       (0x3U << FMC_BWTR3_ACCMOD_Pos)              /*!< 0x30000000 */
16669 #define FMC_BWTR3_ACCMOD           FMC_BWTR3_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
16670 #define FMC_BWTR3_ACCMOD_0         (0x1U << FMC_BWTR3_ACCMOD_Pos)              /*!< 0x10000000 */
16671 #define FMC_BWTR3_ACCMOD_1         (0x2U << FMC_BWTR3_ACCMOD_Pos)              /*!< 0x20000000 */
16672 
16673 #define FMC_BWTR3_DATAHLD_Pos       (30U)
16674 #define FMC_BWTR3_DATAHLD_Msk       (0x3U << FMC_BWTR3_DATAHLD_Pos)            /*!< 0xC0000000 */
16675 #define FMC_BWTR3_DATAHLD           FMC_BWTR3_DATAHLD_Msk                      /*!<DATAHLD[1:0] bits (Data Hold phase duration) */
16676 #define FMC_BWTR3_DATAHLD_0         (0x1U << FMC_BWTR3_DATAHLD_Pos)            /*!< 0x40000000 */
16677 #define FMC_BWTR3_DATAHLD_1         (0x2U << FMC_BWTR3_DATAHLD_Pos)            /*!< 0x80000000 */
16678 
16679 /******************  Bit definition for FMC_BWTR4 register  ******************/
16680 #define FMC_BWTR4_ADDSET_Pos       (0U)
16681 #define FMC_BWTR4_ADDSET_Msk       (0xFU << FMC_BWTR4_ADDSET_Pos)              /*!< 0x0000000F */
16682 #define FMC_BWTR4_ADDSET           FMC_BWTR4_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
16683 #define FMC_BWTR4_ADDSET_0         (0x1U << FMC_BWTR4_ADDSET_Pos)              /*!< 0x00000001 */
16684 #define FMC_BWTR4_ADDSET_1         (0x2U << FMC_BWTR4_ADDSET_Pos)              /*!< 0x00000002 */
16685 #define FMC_BWTR4_ADDSET_2         (0x4U << FMC_BWTR4_ADDSET_Pos)              /*!< 0x00000004 */
16686 #define FMC_BWTR4_ADDSET_3         (0x8U << FMC_BWTR4_ADDSET_Pos)              /*!< 0x00000008 */
16687 
16688 #define FMC_BWTR4_ADDHLD_Pos       (4U)
16689 #define FMC_BWTR4_ADDHLD_Msk       (0xFU << FMC_BWTR4_ADDHLD_Pos)              /*!< 0x000000F0 */
16690 #define FMC_BWTR4_ADDHLD           FMC_BWTR4_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
16691 #define FMC_BWTR4_ADDHLD_0         (0x1U << FMC_BWTR4_ADDHLD_Pos)              /*!< 0x00000010 */
16692 #define FMC_BWTR4_ADDHLD_1         (0x2U << FMC_BWTR4_ADDHLD_Pos)              /*!< 0x00000020 */
16693 #define FMC_BWTR4_ADDHLD_2         (0x4U << FMC_BWTR4_ADDHLD_Pos)              /*!< 0x00000040 */
16694 #define FMC_BWTR4_ADDHLD_3         (0x8U << FMC_BWTR4_ADDHLD_Pos)              /*!< 0x00000080 */
16695 
16696 #define FMC_BWTR4_DATAST_Pos       (8U)
16697 #define FMC_BWTR4_DATAST_Msk       (0xFFU << FMC_BWTR4_DATAST_Pos)             /*!< 0x0000FF00 */
16698 #define FMC_BWTR4_DATAST           FMC_BWTR4_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
16699 #define FMC_BWTR4_DATAST_0         (0x01U << FMC_BWTR4_DATAST_Pos)             /*!< 0x00000100 */
16700 #define FMC_BWTR4_DATAST_1         (0x02U << FMC_BWTR4_DATAST_Pos)             /*!< 0x00000200 */
16701 #define FMC_BWTR4_DATAST_2         (0x04U << FMC_BWTR4_DATAST_Pos)             /*!< 0x00000400 */
16702 #define FMC_BWTR4_DATAST_3         (0x08U << FMC_BWTR4_DATAST_Pos)             /*!< 0x00000800 */
16703 #define FMC_BWTR4_DATAST_4         (0x10U << FMC_BWTR4_DATAST_Pos)             /*!< 0x00001000 */
16704 #define FMC_BWTR4_DATAST_5         (0x20U << FMC_BWTR4_DATAST_Pos)             /*!< 0x00002000 */
16705 #define FMC_BWTR4_DATAST_6         (0x40U << FMC_BWTR4_DATAST_Pos)             /*!< 0x00004000 */
16706 #define FMC_BWTR4_DATAST_7         (0x80U << FMC_BWTR4_DATAST_Pos)             /*!< 0x00008000 */
16707 
16708 #define FMC_BWTR4_CLKDIV_Pos       (20U)
16709 #define FMC_BWTR4_CLKDIV_Msk       (0xFU << FMC_BWTR4_CLKDIV_Pos)              /*!< 0x00F00000 */
16710 #define FMC_BWTR4_CLKDIV           FMC_BWTR4_CLKDIV_Msk                        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
16711 #define FMC_BWTR4_CLKDIV_0         (0x1U << FMC_BWTR4_CLKDIV_Pos)              /*!< 0x00100000 */
16712 #define FMC_BWTR4_CLKDIV_1         (0x2U << FMC_BWTR4_CLKDIV_Pos)              /*!< 0x00200000 */
16713 #define FMC_BWTR4_CLKDIV_2         (0x4U << FMC_BWTR4_CLKDIV_Pos)              /*!< 0x00400000 */
16714 #define FMC_BWTR4_CLKDIV_3         (0x8U << FMC_BWTR4_CLKDIV_Pos)              /*!< 0x00800000 */
16715 
16716 #define FMC_BWTR4_DATLAT_Pos       (24U)
16717 #define FMC_BWTR4_DATLAT_Msk       (0xFU << FMC_BWTR4_DATLAT_Pos)              /*!< 0x0F000000 */
16718 #define FMC_BWTR4_DATLAT           FMC_BWTR4_DATLAT_Msk                        /*!<DATLA[3:0] bits (Data latency) */
16719 #define FMC_BWTR4_DATLAT_0         (0x1U << FMC_BWTR4_DATLAT_Pos)              /*!< 0x01000000 */
16720 #define FMC_BWTR4_DATLAT_1         (0x2U << FMC_BWTR4_DATLAT_Pos)              /*!< 0x02000000 */
16721 #define FMC_BWTR4_DATLAT_2         (0x4U << FMC_BWTR4_DATLAT_Pos)              /*!< 0x04000000 */
16722 #define FMC_BWTR4_DATLAT_3         (0x8U << FMC_BWTR4_DATLAT_Pos)              /*!< 0x08000000 */
16723 
16724 #define FMC_BWTR4_ACCMOD_Pos       (28U)
16725 #define FMC_BWTR4_ACCMOD_Msk       (0x3U << FMC_BWTR4_ACCMOD_Pos)              /*!< 0x30000000 */
16726 #define FMC_BWTR4_ACCMOD           FMC_BWTR4_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
16727 #define FMC_BWTR4_ACCMOD_0         (0x1U << FMC_BWTR4_ACCMOD_Pos)              /*!< 0x10000000 */
16728 #define FMC_BWTR4_ACCMOD_1         (0x2U << FMC_BWTR4_ACCMOD_Pos)              /*!< 0x20000000 */
16729 
16730 #define FMC_BWTR4_DATAHLD_Pos       (30U)
16731 #define FMC_BWTR4_DATAHLD_Msk       (0x3U << FMC_BWTR4_DATAHLD_Pos)            /*!< 0xC0000000 */
16732 #define FMC_BWTR4_DATAHLD           FMC_BWTR4_DATAHLD_Msk                      /*!<DATAHLD[1:0] bits (Data Hold phase duration) */
16733 #define FMC_BWTR4_DATAHLD_0         (0x1U << FMC_BWTR4_DATAHLD_Pos)            /*!< 0x40000000 */
16734 #define FMC_BWTR4_DATAHLD_1         (0x2U << FMC_BWTR4_DATAHLD_Pos)            /*!< 0x80000000 */
16735 
16736 /******************  Bit definition for FMC_PCR register  *******************/
16737 #define FMC_PCR_PWAITEN_Pos        (1U)
16738 #define FMC_PCR_PWAITEN_Msk        (0x1U << FMC_PCR_PWAITEN_Pos)               /*!< 0x00000002 */
16739 #define FMC_PCR_PWAITEN            FMC_PCR_PWAITEN_Msk                         /*!<Wait feature enable bit                   */
16740 #define FMC_PCR_PBKEN_Pos          (2U)
16741 #define FMC_PCR_PBKEN_Msk          (0x1U << FMC_PCR_PBKEN_Pos)                 /*!< 0x00000004 */
16742 #define FMC_PCR_PBKEN              FMC_PCR_PBKEN_Msk                           /*!<NAND Flash memory bank enable bit         */
16743 
16744 #define FMC_PCR_PWID_Pos           (4U)
16745 #define FMC_PCR_PWID_Msk           (0x3U << FMC_PCR_PWID_Pos)                  /*!< 0x00000030 */
16746 #define FMC_PCR_PWID               FMC_PCR_PWID_Msk                            /*!<PWID[1:0] bits (NAND Flash databus width) */
16747 #define FMC_PCR_PWID_0             (0x1U << FMC_PCR_PWID_Pos)                  /*!< 0x00000010 */
16748 #define FMC_PCR_PWID_1             (0x2U << FMC_PCR_PWID_Pos)                  /*!< 0x00000020 */
16749 
16750 #define FMC_PCR_ECCEN_Pos          (6U)
16751 #define FMC_PCR_ECCEN_Msk          (0x1U << FMC_PCR_ECCEN_Pos)                 /*!< 0x00000040 */
16752 #define FMC_PCR_ECCEN              FMC_PCR_ECCEN_Msk                           /*!<ECC computation logic enable bit          */
16753 
16754 #define FMC_PCR_ECCALG_Pos         (8U)
16755 #define FMC_PCR_ECCALG_Msk         (0x1U << FMC_PCR_ECCALG_Pos)                /*!< 0x00000100 */
16756 #define FMC_PCR_ECCALG             FMC_PCR_ECCEN_Msk                           /*!<ECC algorithm                             */
16757 
16758 #define FMC_PCR_TCLR_Pos           (9U)
16759 #define FMC_PCR_TCLR_Msk           (0xFU << FMC_PCR_TCLR_Pos)                  /*!< 0x00001E00 */
16760 #define FMC_PCR_TCLR               FMC_PCR_TCLR_Msk                            /*!<TCLR[3:0] bits (CLE to RE delay)          */
16761 #define FMC_PCR_TCLR_0             (0x1U << FMC_PCR_TCLR_Pos)                  /*!< 0x00000200 */
16762 #define FMC_PCR_TCLR_1             (0x2U << FMC_PCR_TCLR_Pos)                  /*!< 0x00000400 */
16763 #define FMC_PCR_TCLR_2             (0x4U << FMC_PCR_TCLR_Pos)                  /*!< 0x00000800 */
16764 #define FMC_PCR_TCLR_3             (0x8U << FMC_PCR_TCLR_Pos)                  /*!< 0x00001000 */
16765 
16766 #define FMC_PCR_TAR_Pos            (13U)
16767 #define FMC_PCR_TAR_Msk            (0xFU << FMC_PCR_TAR_Pos)                   /*!< 0x0001E000 */
16768 #define FMC_PCR_TAR                FMC_PCR_TAR_Msk                             /*!<TAR[3:0] bits (ALE to RE delay)           */
16769 #define FMC_PCR_TAR_0              (0x1U << FMC_PCR_TAR_Pos)                   /*!< 0x00002000 */
16770 #define FMC_PCR_TAR_1              (0x2U << FMC_PCR_TAR_Pos)                   /*!< 0x00004000 */
16771 #define FMC_PCR_TAR_2              (0x4U << FMC_PCR_TAR_Pos)                   /*!< 0x00008000 */
16772 #define FMC_PCR_TAR_3              (0x8U << FMC_PCR_TAR_Pos)                   /*!< 0x00010000 */
16773 
16774 #define FMC_PCR_ECCSS_Pos          (17U)
16775 #define FMC_PCR_ECCSS_Msk          (0x7U << FMC_PCR_ECCSS_Pos)                 /*!< 0x000E0000 */
16776 #define FMC_PCR_ECCSS              FMC_PCR_ECCSS_Msk                           /*!<ECCSS[1:0] bits (ECC sector size)         */
16777 #define FMC_PCR_ECCSS_0            (0x1U << FMC_PCR_ECCSS_Pos)                 /*!< 0x00020000 */
16778 #define FMC_PCR_ECCSS_1            (0x2U << FMC_PCR_ECCSS_Pos)                 /*!< 0x00040000 */
16779 #define FMC_PCR_ECCSS_2            (0x4U << FMC_PCR_ECCSS_Pos)                 /*!< 0x00080000 */
16780 
16781 #define FMC_PCR_TCEH_Pos          (20U)
16782 #define FMC_PCR_TCEH_Msk          (0xFU << FMC_PCR_TCEH_Pos)                   /*!< 0x00F00000 */
16783 #define FMC_PCR_TCEH              FMC_PCR_TCEH_Msk                             /*!<TCEH[3:0] bits (Chip select high timing)  */
16784 
16785 #define FMC_PCR_BCHECC_Pos        (24U)
16786 #define FMC_PCR_BCHECC_Msk        (0x1U << FMC_PCR_BCHECC_Pos)                 /*!< 0x01000000 */
16787 #define FMC_PCR_BCHECC            FMC_PCR_BCHECC_Msk                           /*!<BCHECC bit (BCH error correction capability) */
16788 
16789 #define FMC_PCR_WEN_Pos           (25U)
16790 #define FMC_PCR_WEN_Msk           (0x1U << FMC_PCR_WEN_Pos)                    /*!< 0x02000000 */
16791 #define FMC_PCR_WEN               FMC_PCR_WEN_Msk                              /*!<WEN bit (Write enable)                    */
16792 
16793 /*******************  Bit definition for FMC_SR register  *******************/
16794 #define FMC_SR_ISOST_Pos          (0U)
16795 #define FMC_SR_ISOST_Msk          (0x3U << FMC_SR_ISOST_Pos)                   /*!< 0x00000003 */
16796 #define FMC_SR_ISOST              FMC_SR_ISOST_Msk                             /*!<ISOST[1:0] bits (FMC isolation state with respect to the AXI interface) */
16797 
16798 #define FMC_SR_PEF_Pos            (4U)
16799 #define FMC_SR_PEF_Msk            (0x1U << FMC_SR_PEF_Pos)                     /*!< 0x00000010 */
16800 #define FMC_SR_PEF                FMC_SR_PEF_Msk                               /*!<Pipe Empty Flag                           */
16801 
16802 #define FMC_SR_NWRF_Pos           (6U)
16803 #define FMC_SR_NWRF_Msk           (0x1U << FMC_SR_NWRF_Pos)                     /*!< 0x00000040 */
16804 #define FMC_SR_NWRF               FMC_SR_NWRF_Msk                               /*!<NAND write request flag                  */
16805 
16806 
16807 /******************  Bit definition for FMC_PMEM register  ******************/
16808 #define FMC_PMEM_MEMSET3_Pos       (0U)
16809 #define FMC_PMEM_MEMSET3_Msk       (0xFFU << FMC_PMEM_MEMSET3_Pos)             /*!< 0x000000FF */
16810 #define FMC_PMEM_MEMSET3           FMC_PMEM_MEMSET3_Msk                        /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
16811 #define FMC_PMEM_MEMSET3_0         (0x01U << FMC_PMEM_MEMSET3_Pos)             /*!< 0x00000001 */
16812 #define FMC_PMEM_MEMSET3_1         (0x02U << FMC_PMEM_MEMSET3_Pos)             /*!< 0x00000002 */
16813 #define FMC_PMEM_MEMSET3_2         (0x04U << FMC_PMEM_MEMSET3_Pos)             /*!< 0x00000004 */
16814 #define FMC_PMEM_MEMSET3_3         (0x08U << FMC_PMEM_MEMSET3_Pos)             /*!< 0x00000008 */
16815 #define FMC_PMEM_MEMSET3_4         (0x10U << FMC_PMEM_MEMSET3_Pos)             /*!< 0x00000010 */
16816 #define FMC_PMEM_MEMSET3_5         (0x20U << FMC_PMEM_MEMSET3_Pos)             /*!< 0x00000020 */
16817 #define FMC_PMEM_MEMSET3_6         (0x40U << FMC_PMEM_MEMSET3_Pos)             /*!< 0x00000040 */
16818 #define FMC_PMEM_MEMSET3_7         (0x80U << FMC_PMEM_MEMSET3_Pos)             /*!< 0x00000080 */
16819 
16820 #define FMC_PMEM_MEMWAIT3_Pos      (8U)
16821 #define FMC_PMEM_MEMWAIT3_Msk      (0xFFU << FMC_PMEM_MEMWAIT3_Pos)            /*!< 0x0000FF00 */
16822 #define FMC_PMEM_MEMWAIT3          FMC_PMEM_MEMWAIT3_Msk                       /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
16823 #define FMC_PMEM_MEMWAIT3_0        (0x01U << FMC_PMEM_MEMWAIT3_Pos)            /*!< 0x00000100 */
16824 #define FMC_PMEM_MEMWAIT3_1        (0x02U << FMC_PMEM_MEMWAIT3_Pos)            /*!< 0x00000200 */
16825 #define FMC_PMEM_MEMWAIT3_2        (0x04U << FMC_PMEM_MEMWAIT3_Pos)            /*!< 0x00000400 */
16826 #define FMC_PMEM_MEMWAIT3_3        (0x08U << FMC_PMEM_MEMWAIT3_Pos)            /*!< 0x00000800 */
16827 #define FMC_PMEM_MEMWAIT3_4        (0x10U << FMC_PMEM_MEMWAIT3_Pos)            /*!< 0x00001000 */
16828 #define FMC_PMEM_MEMWAIT3_5        (0x20U << FMC_PMEM_MEMWAIT3_Pos)            /*!< 0x00002000 */
16829 #define FMC_PMEM_MEMWAIT3_6        (0x40U << FMC_PMEM_MEMWAIT3_Pos)            /*!< 0x00004000 */
16830 #define FMC_PMEM_MEMWAIT3_7        (0x80U << FMC_PMEM_MEMWAIT3_Pos)            /*!< 0x00008000 */
16831 
16832 #define FMC_PMEM_MEMHOLD3_Pos      (16U)
16833 #define FMC_PMEM_MEMHOLD3_Msk      (0xFFU << FMC_PMEM_MEMHOLD3_Pos)            /*!< 0x00FF0000 */
16834 #define FMC_PMEM_MEMHOLD3          FMC_PMEM_MEMHOLD3_Msk                       /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
16835 #define FMC_PMEM_MEMHOLD3_0        (0x01U << FMC_PMEM_MEMHOLD3_Pos)            /*!< 0x00010000 */
16836 #define FMC_PMEM_MEMHOLD3_1        (0x02U << FMC_PMEM_MEMHOLD3_Pos)            /*!< 0x00020000 */
16837 #define FMC_PMEM_MEMHOLD3_2        (0x04U << FMC_PMEM_MEMHOLD3_Pos)            /*!< 0x00040000 */
16838 #define FMC_PMEM_MEMHOLD3_3        (0x08U << FMC_PMEM_MEMHOLD3_Pos)            /*!< 0x00080000 */
16839 #define FMC_PMEM_MEMHOLD3_4        (0x10U << FMC_PMEM_MEMHOLD3_Pos)            /*!< 0x00100000 */
16840 #define FMC_PMEM_MEMHOLD3_5        (0x20U << FMC_PMEM_MEMHOLD3_Pos)            /*!< 0x00200000 */
16841 #define FMC_PMEM_MEMHOLD3_6        (0x40U << FMC_PMEM_MEMHOLD3_Pos)            /*!< 0x00400000 */
16842 #define FMC_PMEM_MEMHOLD3_7        (0x80U << FMC_PMEM_MEMHOLD3_Pos)            /*!< 0x00800000 */
16843 
16844 #define FMC_PMEM_MEMHIZ3_Pos       (24U)
16845 #define FMC_PMEM_MEMHIZ3_Msk       (0xFFU << FMC_PMEM_MEMHIZ3_Pos)             /*!< 0xFF000000 */
16846 #define FMC_PMEM_MEMHIZ3           FMC_PMEM_MEMHIZ3_Msk                        /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
16847 #define FMC_PMEM_MEMHIZ3_0         (0x01U << FMC_PMEM_MEMHIZ3_Pos)             /*!< 0x01000000 */
16848 #define FMC_PMEM_MEMHIZ3_1         (0x02U << FMC_PMEM_MEMHIZ3_Pos)             /*!< 0x02000000 */
16849 #define FMC_PMEM_MEMHIZ3_2         (0x04U << FMC_PMEM_MEMHIZ3_Pos)             /*!< 0x04000000 */
16850 #define FMC_PMEM_MEMHIZ3_3         (0x08U << FMC_PMEM_MEMHIZ3_Pos)             /*!< 0x08000000 */
16851 #define FMC_PMEM_MEMHIZ3_4         (0x10U << FMC_PMEM_MEMHIZ3_Pos)             /*!< 0x10000000 */
16852 #define FMC_PMEM_MEMHIZ3_5         (0x20U << FMC_PMEM_MEMHIZ3_Pos)             /*!< 0x20000000 */
16853 #define FMC_PMEM_MEMHIZ3_6         (0x40U << FMC_PMEM_MEMHIZ3_Pos)             /*!< 0x40000000 */
16854 #define FMC_PMEM_MEMHIZ3_7         (0x80U << FMC_PMEM_MEMHIZ3_Pos)             /*!< 0x80000000 */
16855 
16856 /******************  Bit definition for FMC_PATT register  ******************/
16857 #define FMC_PATT_ATTSET3_Pos       (0U)
16858 #define FMC_PATT_ATTSET3_Msk       (0xFFU << FMC_PATT_ATTSET3_Pos)             /*!< 0x000000FF */
16859 #define FMC_PATT_ATTSET3           FMC_PATT_ATTSET3_Msk                        /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
16860 #define FMC_PATT_ATTSET3_0         (0x01U << FMC_PATT_ATTSET3_Pos)             /*!< 0x00000001 */
16861 #define FMC_PATT_ATTSET3_1         (0x02U << FMC_PATT_ATTSET3_Pos)             /*!< 0x00000002 */
16862 #define FMC_PATT_ATTSET3_2         (0x04U << FMC_PATT_ATTSET3_Pos)             /*!< 0x00000004 */
16863 #define FMC_PATT_ATTSET3_3         (0x08U << FMC_PATT_ATTSET3_Pos)             /*!< 0x00000008 */
16864 #define FMC_PATT_ATTSET3_4         (0x10U << FMC_PATT_ATTSET3_Pos)             /*!< 0x00000010 */
16865 #define FMC_PATT_ATTSET3_5         (0x20U << FMC_PATT_ATTSET3_Pos)             /*!< 0x00000020 */
16866 #define FMC_PATT_ATTSET3_6         (0x40U << FMC_PATT_ATTSET3_Pos)             /*!< 0x00000040 */
16867 #define FMC_PATT_ATTSET3_7         (0x80U << FMC_PATT_ATTSET3_Pos)             /*!< 0x00000080 */
16868 
16869 #define FMC_PATT_ATTWAIT3_Pos      (8U)
16870 #define FMC_PATT_ATTWAIT3_Msk      (0xFFU << FMC_PATT_ATTWAIT3_Pos)            /*!< 0x0000FF00 */
16871 #define FMC_PATT_ATTWAIT3          FMC_PATT_ATTWAIT3_Msk                       /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
16872 #define FMC_PATT_ATTWAIT3_0        (0x01U << FMC_PATT_ATTWAIT3_Pos)            /*!< 0x00000100 */
16873 #define FMC_PATT_ATTWAIT3_1        (0x02U << FMC_PATT_ATTWAIT3_Pos)            /*!< 0x00000200 */
16874 #define FMC_PATT_ATTWAIT3_2        (0x04U << FMC_PATT_ATTWAIT3_Pos)            /*!< 0x00000400 */
16875 #define FMC_PATT_ATTWAIT3_3        (0x08U << FMC_PATT_ATTWAIT3_Pos)            /*!< 0x00000800 */
16876 #define FMC_PATT_ATTWAIT3_4        (0x10U << FMC_PATT_ATTWAIT3_Pos)            /*!< 0x00001000 */
16877 #define FMC_PATT_ATTWAIT3_5        (0x20U << FMC_PATT_ATTWAIT3_Pos)            /*!< 0x00002000 */
16878 #define FMC_PATT_ATTWAIT3_6        (0x40U << FMC_PATT_ATTWAIT3_Pos)            /*!< 0x00004000 */
16879 #define FMC_PATT_ATTWAIT3_7        (0x80U << FMC_PATT_ATTWAIT3_Pos)            /*!< 0x00008000 */
16880 
16881 #define FMC_PATT_ATTHOLD3_Pos      (16U)
16882 #define FMC_PATT_ATTHOLD3_Msk      (0xFFU << FMC_PATT_ATTHOLD3_Pos)            /*!< 0x00FF0000 */
16883 #define FMC_PATT_ATTHOLD3          FMC_PATT_ATTHOLD3_Msk                       /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
16884 #define FMC_PATT_ATTHOLD3_0        (0x01U << FMC_PATT_ATTHOLD3_Pos)            /*!< 0x00010000 */
16885 #define FMC_PATT_ATTHOLD3_1        (0x02U << FMC_PATT_ATTHOLD3_Pos)            /*!< 0x00020000 */
16886 #define FMC_PATT_ATTHOLD3_2        (0x04U << FMC_PATT_ATTHOLD3_Pos)            /*!< 0x00040000 */
16887 #define FMC_PATT_ATTHOLD3_3        (0x08U << FMC_PATT_ATTHOLD3_Pos)            /*!< 0x00080000 */
16888 #define FMC_PATT_ATTHOLD3_4        (0x10U << FMC_PATT_ATTHOLD3_Pos)            /*!< 0x00100000 */
16889 #define FMC_PATT_ATTHOLD3_5        (0x20U << FMC_PATT_ATTHOLD3_Pos)            /*!< 0x00200000 */
16890 #define FMC_PATT_ATTHOLD3_6        (0x40U << FMC_PATT_ATTHOLD3_Pos)            /*!< 0x00400000 */
16891 #define FMC_PATT_ATTHOLD3_7        (0x80U << FMC_PATT_ATTHOLD3_Pos)            /*!< 0x00800000 */
16892 
16893 #define FMC_PATT_ATTHIZ3_Pos       (24U)
16894 #define FMC_PATT_ATTHIZ3_Msk       (0xFFU << FMC_PATT_ATTHIZ3_Pos)             /*!< 0xFF000000 */
16895 #define FMC_PATT_ATTHIZ3           FMC_PATT_ATTHIZ3_Msk                        /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
16896 #define FMC_PATT_ATTHIZ3_0         (0x01U << FMC_PATT_ATTHIZ3_Pos)             /*!< 0x01000000 */
16897 #define FMC_PATT_ATTHIZ3_1         (0x02U << FMC_PATT_ATTHIZ3_Pos)             /*!< 0x02000000 */
16898 #define FMC_PATT_ATTHIZ3_2         (0x04U << FMC_PATT_ATTHIZ3_Pos)             /*!< 0x04000000 */
16899 #define FMC_PATT_ATTHIZ3_3         (0x08U << FMC_PATT_ATTHIZ3_Pos)             /*!< 0x08000000 */
16900 #define FMC_PATT_ATTHIZ3_4         (0x10U << FMC_PATT_ATTHIZ3_Pos)             /*!< 0x10000000 */
16901 #define FMC_PATT_ATTHIZ3_5         (0x20U << FMC_PATT_ATTHIZ3_Pos)             /*!< 0x20000000 */
16902 #define FMC_PATT_ATTHIZ3_6         (0x40U << FMC_PATT_ATTHIZ3_Pos)             /*!< 0x40000000 */
16903 #define FMC_PATT_ATTHIZ3_7         (0x80U << FMC_PATT_ATTHIZ3_Pos)             /*!< 0x80000000 */
16904 
16905 /******************  Bit definition for FMC_PIO4 register  *******************/
16906 #define FMC_PIO4_IOSET4_Pos        (0U)
16907 #define FMC_PIO4_IOSET4_Msk        (0xFFU << FMC_PIO4_IOSET4_Pos)              /*!< 0x000000FF */
16908 #define FMC_PIO4_IOSET4            FMC_PIO4_IOSET4_Msk                         /*!<IOSET4[7:0] bits (I/O 4 setup time) */
16909 #define FMC_PIO4_IOSET4_0          (0x01U << FMC_PIO4_IOSET4_Pos)              /*!< 0x00000001 */
16910 #define FMC_PIO4_IOSET4_1          (0x02U << FMC_PIO4_IOSET4_Pos)              /*!< 0x00000002 */
16911 #define FMC_PIO4_IOSET4_2          (0x04U << FMC_PIO4_IOSET4_Pos)              /*!< 0x00000004 */
16912 #define FMC_PIO4_IOSET4_3          (0x08U << FMC_PIO4_IOSET4_Pos)              /*!< 0x00000008 */
16913 #define FMC_PIO4_IOSET4_4          (0x10U << FMC_PIO4_IOSET4_Pos)              /*!< 0x00000010 */
16914 #define FMC_PIO4_IOSET4_5          (0x20U << FMC_PIO4_IOSET4_Pos)              /*!< 0x00000020 */
16915 #define FMC_PIO4_IOSET4_6          (0x40U << FMC_PIO4_IOSET4_Pos)              /*!< 0x00000040 */
16916 #define FMC_PIO4_IOSET4_7          (0x80U << FMC_PIO4_IOSET4_Pos)              /*!< 0x00000080 */
16917 
16918 #define FMC_PIO4_IOWAIT4_Pos       (8U)
16919 #define FMC_PIO4_IOWAIT4_Msk       (0xFFU << FMC_PIO4_IOWAIT4_Pos)             /*!< 0x0000FF00 */
16920 #define FMC_PIO4_IOWAIT4           FMC_PIO4_IOWAIT4_Msk                        /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
16921 #define FMC_PIO4_IOWAIT4_0         (0x01U << FMC_PIO4_IOWAIT4_Pos)             /*!< 0x00000100 */
16922 #define FMC_PIO4_IOWAIT4_1         (0x02U << FMC_PIO4_IOWAIT4_Pos)             /*!< 0x00000200 */
16923 #define FMC_PIO4_IOWAIT4_2         (0x04U << FMC_PIO4_IOWAIT4_Pos)             /*!< 0x00000400 */
16924 #define FMC_PIO4_IOWAIT4_3         (0x08U << FMC_PIO4_IOWAIT4_Pos)             /*!< 0x00000800 */
16925 #define FMC_PIO4_IOWAIT4_4         (0x10U << FMC_PIO4_IOWAIT4_Pos)             /*!< 0x00001000 */
16926 #define FMC_PIO4_IOWAIT4_5         (0x20U << FMC_PIO4_IOWAIT4_Pos)             /*!< 0x00002000 */
16927 #define FMC_PIO4_IOWAIT4_6         (0x40U << FMC_PIO4_IOWAIT4_Pos)             /*!< 0x00004000 */
16928 #define FMC_PIO4_IOWAIT4_7         (0x80U << FMC_PIO4_IOWAIT4_Pos)             /*!< 0x00008000 */
16929 
16930 #define FMC_PIO4_IOHOLD4_Pos       (16U)
16931 #define FMC_PIO4_IOHOLD4_Msk       (0xFFU << FMC_PIO4_IOHOLD4_Pos)             /*!< 0x00FF0000 */
16932 #define FMC_PIO4_IOHOLD4           FMC_PIO4_IOHOLD4_Msk                        /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
16933 #define FMC_PIO4_IOHOLD4_0         (0x01U << FMC_PIO4_IOHOLD4_Pos)             /*!< 0x00010000 */
16934 #define FMC_PIO4_IOHOLD4_1         (0x02U << FMC_PIO4_IOHOLD4_Pos)             /*!< 0x00020000 */
16935 #define FMC_PIO4_IOHOLD4_2         (0x04U << FMC_PIO4_IOHOLD4_Pos)             /*!< 0x00040000 */
16936 #define FMC_PIO4_IOHOLD4_3         (0x08U << FMC_PIO4_IOHOLD4_Pos)             /*!< 0x00080000 */
16937 #define FMC_PIO4_IOHOLD4_4         (0x10U << FMC_PIO4_IOHOLD4_Pos)             /*!< 0x00100000 */
16938 #define FMC_PIO4_IOHOLD4_5         (0x20U << FMC_PIO4_IOHOLD4_Pos)             /*!< 0x00200000 */
16939 #define FMC_PIO4_IOHOLD4_6         (0x40U << FMC_PIO4_IOHOLD4_Pos)             /*!< 0x00400000 */
16940 #define FMC_PIO4_IOHOLD4_7         (0x80U << FMC_PIO4_IOHOLD4_Pos)             /*!< 0x00800000 */
16941 
16942 #define FMC_PIO4_IOHIZ4_Pos        (24U)
16943 #define FMC_PIO4_IOHIZ4_Msk        (0xFFU << FMC_PIO4_IOHIZ4_Pos)              /*!< 0xFF000000 */
16944 #define FMC_PIO4_IOHIZ4            FMC_PIO4_IOHIZ4_Msk                         /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
16945 #define FMC_PIO4_IOHIZ4_0          (0x01U << FMC_PIO4_IOHIZ4_Pos)              /*!< 0x01000000 */
16946 #define FMC_PIO4_IOHIZ4_1          (0x02U << FMC_PIO4_IOHIZ4_Pos)              /*!< 0x02000000 */
16947 #define FMC_PIO4_IOHIZ4_2          (0x04U << FMC_PIO4_IOHIZ4_Pos)              /*!< 0x04000000 */
16948 #define FMC_PIO4_IOHIZ4_3          (0x08U << FMC_PIO4_IOHIZ4_Pos)              /*!< 0x08000000 */
16949 #define FMC_PIO4_IOHIZ4_4          (0x10U << FMC_PIO4_IOHIZ4_Pos)              /*!< 0x10000000 */
16950 #define FMC_PIO4_IOHIZ4_5          (0x20U << FMC_PIO4_IOHIZ4_Pos)              /*!< 0x20000000 */
16951 #define FMC_PIO4_IOHIZ4_6          (0x40U << FMC_PIO4_IOHIZ4_Pos)              /*!< 0x40000000 */
16952 #define FMC_PIO4_IOHIZ4_7          (0x80U << FMC_PIO4_IOHIZ4_Pos)              /*!< 0x80000000 */
16953 
16954 /**********************  Bit definition for FMC_VERR register  *****************/
16955 #define FMC_VERR_MINREV_Pos      (0U)
16956 #define FMC_VERR_MINREV_Msk      (0xFU << FMC_VERR_MINREV_Pos)               /*!< 0x0000000F */
16957 #define FMC_VERR_MINREV          FMC_VERR_MINREV_Msk                         /*!< Minor Revision number */
16958 #define FMC_VERR_MAJREV_Pos      (4U)
16959 #define FMC_VERR_MAJREV_Msk      (0xFU << FMC_VERR_MAJREV_Pos)               /*!< 0x000000F0 */
16960 #define FMC_VERR_MAJREV          FMC_VERR_MAJREV_Msk                         /*!< Major Revision number */
16961 
16962 /**********************  Bit definition for FMC_IPIDR register  ****************/
16963 #define FMC_IPIDR_IPID_Pos       (0U)
16964 #define FMC_IPIDR_IPID_Msk       (0xFFFFFFFFU << FMC_IPIDR_IPID_Pos)         /*!< 0xFFFFFFFF */
16965 #define FMC_IPIDR_IPID           FMC_IPIDR_IPID_Msk                          /*!< IP Identification */
16966 
16967 /**********************  Bit definition for FMC_SIDR register  *****************/
16968 #define FMC_SIDR_SID_Pos         (0U)
16969 #define FMC_SIDR_SID_Msk         (0xFFFFFFFFU << FMC_SIDR_SID_Pos)           /*!< 0xFFFFFFFF */
16970 #define FMC_SIDR_SID             FMC_SIDR_SID_Msk                            /*!< IP size identification */
16971 
16972 /******************************************************************************/
16973 /*                                                                            */
16974 /*                            General Purpose I/O                             */
16975 /*                                                                            */
16976 /******************************************************************************/
16977 /******************  Bits definition for GPIO_MODER register  *****************/
16978 #define GPIO_MODER_MODER0_Pos            (0U)
16979 #define GPIO_MODER_MODER0_Msk            (0x3U << GPIO_MODER_MODER0_Pos)       /*!< 0x00000003 */
16980 #define GPIO_MODER_MODER0                GPIO_MODER_MODER0_Msk
16981 #define GPIO_MODER_MODER0_0              (0x1U << GPIO_MODER_MODER0_Pos)       /*!< 0x00000001 */
16982 #define GPIO_MODER_MODER0_1              (0x2U << GPIO_MODER_MODER0_Pos)       /*!< 0x00000002 */
16983 
16984 #define GPIO_MODER_MODER1_Pos            (2U)
16985 #define GPIO_MODER_MODER1_Msk            (0x3U << GPIO_MODER_MODER1_Pos)       /*!< 0x0000000C */
16986 #define GPIO_MODER_MODER1                GPIO_MODER_MODER1_Msk
16987 #define GPIO_MODER_MODER1_0              (0x1U << GPIO_MODER_MODER1_Pos)       /*!< 0x00000004 */
16988 #define GPIO_MODER_MODER1_1              (0x2U << GPIO_MODER_MODER1_Pos)       /*!< 0x00000008 */
16989 
16990 #define GPIO_MODER_MODER2_Pos            (4U)
16991 #define GPIO_MODER_MODER2_Msk            (0x3U << GPIO_MODER_MODER2_Pos)       /*!< 0x00000030 */
16992 #define GPIO_MODER_MODER2                GPIO_MODER_MODER2_Msk
16993 #define GPIO_MODER_MODER2_0              (0x1U << GPIO_MODER_MODER2_Pos)       /*!< 0x00000010 */
16994 #define GPIO_MODER_MODER2_1              (0x2U << GPIO_MODER_MODER2_Pos)       /*!< 0x00000020 */
16995 
16996 #define GPIO_MODER_MODER3_Pos            (6U)
16997 #define GPIO_MODER_MODER3_Msk            (0x3U << GPIO_MODER_MODER3_Pos)       /*!< 0x000000C0 */
16998 #define GPIO_MODER_MODER3                GPIO_MODER_MODER3_Msk
16999 #define GPIO_MODER_MODER3_0              (0x1U << GPIO_MODER_MODER3_Pos)       /*!< 0x00000040 */
17000 #define GPIO_MODER_MODER3_1              (0x2U << GPIO_MODER_MODER3_Pos)       /*!< 0x00000080 */
17001 
17002 #define GPIO_MODER_MODER4_Pos            (8U)
17003 #define GPIO_MODER_MODER4_Msk            (0x3U << GPIO_MODER_MODER4_Pos)       /*!< 0x00000300 */
17004 #define GPIO_MODER_MODER4                GPIO_MODER_MODER4_Msk
17005 #define GPIO_MODER_MODER4_0              (0x1U << GPIO_MODER_MODER4_Pos)       /*!< 0x00000100 */
17006 #define GPIO_MODER_MODER4_1              (0x2U << GPIO_MODER_MODER4_Pos)       /*!< 0x00000200 */
17007 
17008 #define GPIO_MODER_MODER5_Pos            (10U)
17009 #define GPIO_MODER_MODER5_Msk            (0x3U << GPIO_MODER_MODER5_Pos)       /*!< 0x00000C00 */
17010 #define GPIO_MODER_MODER5                GPIO_MODER_MODER5_Msk
17011 #define GPIO_MODER_MODER5_0              (0x1U << GPIO_MODER_MODER5_Pos)       /*!< 0x00000400 */
17012 #define GPIO_MODER_MODER5_1              (0x2U << GPIO_MODER_MODER5_Pos)       /*!< 0x00000800 */
17013 
17014 #define GPIO_MODER_MODER6_Pos            (12U)
17015 #define GPIO_MODER_MODER6_Msk            (0x3U << GPIO_MODER_MODER6_Pos)       /*!< 0x00003000 */
17016 #define GPIO_MODER_MODER6                GPIO_MODER_MODER6_Msk
17017 #define GPIO_MODER_MODER6_0              (0x1U << GPIO_MODER_MODER6_Pos)       /*!< 0x00001000 */
17018 #define GPIO_MODER_MODER6_1              (0x2U << GPIO_MODER_MODER6_Pos)       /*!< 0x00002000 */
17019 
17020 #define GPIO_MODER_MODER7_Pos            (14U)
17021 #define GPIO_MODER_MODER7_Msk            (0x3U << GPIO_MODER_MODER7_Pos)       /*!< 0x0000C000 */
17022 #define GPIO_MODER_MODER7                GPIO_MODER_MODER7_Msk
17023 #define GPIO_MODER_MODER7_0              (0x1U << GPIO_MODER_MODER7_Pos)       /*!< 0x00004000 */
17024 #define GPIO_MODER_MODER7_1              (0x2U << GPIO_MODER_MODER7_Pos)       /*!< 0x00008000 */
17025 
17026 #define GPIO_MODER_MODER8_Pos            (16U)
17027 #define GPIO_MODER_MODER8_Msk            (0x3U << GPIO_MODER_MODER8_Pos)       /*!< 0x00030000 */
17028 #define GPIO_MODER_MODER8                GPIO_MODER_MODER8_Msk
17029 #define GPIO_MODER_MODER8_0              (0x1U << GPIO_MODER_MODER8_Pos)       /*!< 0x00010000 */
17030 #define GPIO_MODER_MODER8_1              (0x2U << GPIO_MODER_MODER8_Pos)       /*!< 0x00020000 */
17031 
17032 #define GPIO_MODER_MODER9_Pos            (18U)
17033 #define GPIO_MODER_MODER9_Msk            (0x3U << GPIO_MODER_MODER9_Pos)       /*!< 0x000C0000 */
17034 #define GPIO_MODER_MODER9                GPIO_MODER_MODER9_Msk
17035 #define GPIO_MODER_MODER9_0              (0x1U << GPIO_MODER_MODER9_Pos)       /*!< 0x00040000 */
17036 #define GPIO_MODER_MODER9_1              (0x2U << GPIO_MODER_MODER9_Pos)       /*!< 0x00080000 */
17037 
17038 #define GPIO_MODER_MODER10_Pos           (20U)
17039 #define GPIO_MODER_MODER10_Msk           (0x3U << GPIO_MODER_MODER10_Pos)      /*!< 0x00300000 */
17040 #define GPIO_MODER_MODER10               GPIO_MODER_MODER10_Msk
17041 #define GPIO_MODER_MODER10_0             (0x1U << GPIO_MODER_MODER10_Pos)      /*!< 0x00100000 */
17042 #define GPIO_MODER_MODER10_1             (0x2U << GPIO_MODER_MODER10_Pos)      /*!< 0x00200000 */
17043 
17044 #define GPIO_MODER_MODER11_Pos           (22U)
17045 #define GPIO_MODER_MODER11_Msk           (0x3U << GPIO_MODER_MODER11_Pos)      /*!< 0x00C00000 */
17046 #define GPIO_MODER_MODER11               GPIO_MODER_MODER11_Msk
17047 #define GPIO_MODER_MODER11_0             (0x1U << GPIO_MODER_MODER11_Pos)      /*!< 0x00400000 */
17048 #define GPIO_MODER_MODER11_1             (0x2U << GPIO_MODER_MODER11_Pos)      /*!< 0x00800000 */
17049 
17050 #define GPIO_MODER_MODER12_Pos           (24U)
17051 #define GPIO_MODER_MODER12_Msk           (0x3U << GPIO_MODER_MODER12_Pos)      /*!< 0x03000000 */
17052 #define GPIO_MODER_MODER12               GPIO_MODER_MODER12_Msk
17053 #define GPIO_MODER_MODER12_0             (0x1U << GPIO_MODER_MODER12_Pos)      /*!< 0x01000000 */
17054 #define GPIO_MODER_MODER12_1             (0x2U << GPIO_MODER_MODER12_Pos)      /*!< 0x02000000 */
17055 
17056 #define GPIO_MODER_MODER13_Pos           (26U)
17057 #define GPIO_MODER_MODER13_Msk           (0x3U << GPIO_MODER_MODER13_Pos)      /*!< 0x0C000000 */
17058 #define GPIO_MODER_MODER13               GPIO_MODER_MODER13_Msk
17059 #define GPIO_MODER_MODER13_0             (0x1U << GPIO_MODER_MODER13_Pos)      /*!< 0x04000000 */
17060 #define GPIO_MODER_MODER13_1             (0x2U << GPIO_MODER_MODER13_Pos)      /*!< 0x08000000 */
17061 
17062 #define GPIO_MODER_MODER14_Pos           (28U)
17063 #define GPIO_MODER_MODER14_Msk           (0x3U << GPIO_MODER_MODER14_Pos)      /*!< 0x30000000 */
17064 #define GPIO_MODER_MODER14               GPIO_MODER_MODER14_Msk
17065 #define GPIO_MODER_MODER14_0             (0x1U << GPIO_MODER_MODER14_Pos)      /*!< 0x10000000 */
17066 #define GPIO_MODER_MODER14_1             (0x2U << GPIO_MODER_MODER14_Pos)      /*!< 0x20000000 */
17067 
17068 #define GPIO_MODER_MODER15_Pos           (30U)
17069 #define GPIO_MODER_MODER15_Msk           (0x3U << GPIO_MODER_MODER15_Pos)      /*!< 0xC0000000 */
17070 #define GPIO_MODER_MODER15               GPIO_MODER_MODER15_Msk
17071 #define GPIO_MODER_MODER15_0             (0x1U << GPIO_MODER_MODER15_Pos)      /*!< 0x40000000 */
17072 #define GPIO_MODER_MODER15_1             (0x2U << GPIO_MODER_MODER15_Pos)      /*!< 0x80000000 */
17073 
17074 /******************  Bits definition for GPIO_OTYPER register  ****************/
17075 #define GPIO_OTYPER_OT0_Pos            (0U)
17076 #define GPIO_OTYPER_OT0_Msk            (0x1U << GPIO_OTYPER_OT0_Pos)           /*!< 0x00000001 */
17077 #define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk
17078 #define GPIO_OTYPER_OT1_Pos            (1U)
17079 #define GPIO_OTYPER_OT1_Msk            (0x1U << GPIO_OTYPER_OT1_Pos)           /*!< 0x00000002 */
17080 #define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk
17081 #define GPIO_OTYPER_OT2_Pos            (2U)
17082 #define GPIO_OTYPER_OT2_Msk            (0x1U << GPIO_OTYPER_OT2_Pos)           /*!< 0x00000004 */
17083 #define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk
17084 #define GPIO_OTYPER_OT3_Pos            (3U)
17085 #define GPIO_OTYPER_OT3_Msk            (0x1U << GPIO_OTYPER_OT3_Pos)           /*!< 0x00000008 */
17086 #define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk
17087 #define GPIO_OTYPER_OT4_Pos            (4U)
17088 #define GPIO_OTYPER_OT4_Msk            (0x1U << GPIO_OTYPER_OT4_Pos)           /*!< 0x00000010 */
17089 #define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk
17090 #define GPIO_OTYPER_OT5_Pos            (5U)
17091 #define GPIO_OTYPER_OT5_Msk            (0x1U << GPIO_OTYPER_OT5_Pos)           /*!< 0x00000020 */
17092 #define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk
17093 #define GPIO_OTYPER_OT6_Pos            (6U)
17094 #define GPIO_OTYPER_OT6_Msk            (0x1U << GPIO_OTYPER_OT6_Pos)           /*!< 0x00000040 */
17095 #define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk
17096 #define GPIO_OTYPER_OT7_Pos            (7U)
17097 #define GPIO_OTYPER_OT7_Msk            (0x1U << GPIO_OTYPER_OT7_Pos)           /*!< 0x00000080 */
17098 #define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk
17099 #define GPIO_OTYPER_OT8_Pos            (8U)
17100 #define GPIO_OTYPER_OT8_Msk            (0x1U << GPIO_OTYPER_OT8_Pos)           /*!< 0x00000100 */
17101 #define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk
17102 #define GPIO_OTYPER_OT9_Pos            (9U)
17103 #define GPIO_OTYPER_OT9_Msk            (0x1U << GPIO_OTYPER_OT9_Pos)           /*!< 0x00000200 */
17104 #define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk
17105 #define GPIO_OTYPER_OT10_Pos           (10U)
17106 #define GPIO_OTYPER_OT10_Msk           (0x1U << GPIO_OTYPER_OT10_Pos)          /*!< 0x00000400 */
17107 #define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk
17108 #define GPIO_OTYPER_OT11_Pos           (11U)
17109 #define GPIO_OTYPER_OT11_Msk           (0x1U << GPIO_OTYPER_OT11_Pos)          /*!< 0x00000800 */
17110 #define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk
17111 #define GPIO_OTYPER_OT12_Pos           (12U)
17112 #define GPIO_OTYPER_OT12_Msk           (0x1U << GPIO_OTYPER_OT12_Pos)          /*!< 0x00001000 */
17113 #define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk
17114 #define GPIO_OTYPER_OT13_Pos           (13U)
17115 #define GPIO_OTYPER_OT13_Msk           (0x1U << GPIO_OTYPER_OT13_Pos)          /*!< 0x00002000 */
17116 #define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk
17117 #define GPIO_OTYPER_OT14_Pos           (14U)
17118 #define GPIO_OTYPER_OT14_Msk           (0x1U << GPIO_OTYPER_OT14_Pos)          /*!< 0x00004000 */
17119 #define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk
17120 #define GPIO_OTYPER_OT15_Pos           (15U)
17121 #define GPIO_OTYPER_OT15_Msk           (0x1U << GPIO_OTYPER_OT15_Pos)          /*!< 0x00008000 */
17122 #define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk
17123 
17124 /******************  Bits definition for GPIO_OSPEEDR register  ***************/
17125 #define GPIO_OSPEEDR_OSPEEDR0_Pos       (0U)
17126 #define GPIO_OSPEEDR_OSPEEDR0_Msk       (0x3U << GPIO_OSPEEDR_OSPEEDR0_Pos)  /*!< 0x00000003 */
17127 #define GPIO_OSPEEDR_OSPEEDR0           GPIO_OSPEEDR_OSPEEDR0_Msk
17128 #define GPIO_OSPEEDR_OSPEEDR0_0         (0x1U << GPIO_OSPEEDR_OSPEEDR0_Pos)  /*!< 0x00000001 */
17129 #define GPIO_OSPEEDR_OSPEEDR0_1         (0x2U << GPIO_OSPEEDR_OSPEEDR0_Pos)  /*!< 0x00000002 */
17130 
17131 #define GPIO_OSPEEDR_OSPEEDR1_Pos       (2U)
17132 #define GPIO_OSPEEDR_OSPEEDR1_Msk       (0x3U << GPIO_OSPEEDR_OSPEEDR1_Pos)  /*!< 0x0000000C */
17133 #define GPIO_OSPEEDR_OSPEEDR1           GPIO_OSPEEDR_OSPEEDR1_Msk
17134 #define GPIO_OSPEEDR_OSPEEDR1_0         (0x1U << GPIO_OSPEEDR_OSPEEDR1_Pos)  /*!< 0x00000004 */
17135 #define GPIO_OSPEEDR_OSPEEDR1_1         (0x2U << GPIO_OSPEEDR_OSPEEDR1_Pos)  /*!< 0x00000008 */
17136 
17137 #define GPIO_OSPEEDR_OSPEEDR2_Pos       (4U)
17138 #define GPIO_OSPEEDR_OSPEEDR2_Msk       (0x3U << GPIO_OSPEEDR_OSPEEDR2_Pos)  /*!< 0x00000030 */
17139 #define GPIO_OSPEEDR_OSPEEDR2           GPIO_OSPEEDR_OSPEEDR2_Msk
17140 #define GPIO_OSPEEDR_OSPEEDR2_0         (0x1U << GPIO_OSPEEDR_OSPEEDR2_Pos)  /*!< 0x00000010 */
17141 #define GPIO_OSPEEDR_OSPEEDR2_1         (0x2U << GPIO_OSPEEDR_OSPEEDR2_Pos)  /*!< 0x00000020 */
17142 
17143 #define GPIO_OSPEEDR_OSPEEDR3_Pos       (6U)
17144 #define GPIO_OSPEEDR_OSPEEDR3_Msk       (0x3U << GPIO_OSPEEDR_OSPEEDR3_Pos)  /*!< 0x000000C0 */
17145 #define GPIO_OSPEEDR_OSPEEDR3           GPIO_OSPEEDR_OSPEEDR3_Msk
17146 #define GPIO_OSPEEDR_OSPEEDR3_0         (0x1U << GPIO_OSPEEDR_OSPEEDR3_Pos)  /*!< 0x00000040 */
17147 #define GPIO_OSPEEDR_OSPEEDR3_1         (0x2U << GPIO_OSPEEDR_OSPEEDR3_Pos)  /*!< 0x00000080 */
17148 
17149 #define GPIO_OSPEEDR_OSPEEDR4_Pos       (8U)
17150 #define GPIO_OSPEEDR_OSPEEDR4_Msk       (0x3U << GPIO_OSPEEDR_OSPEEDR4_Pos)  /*!< 0x00000300 */
17151 #define GPIO_OSPEEDR_OSPEEDR4           GPIO_OSPEEDR_OSPEEDR4_Msk
17152 #define GPIO_OSPEEDR_OSPEEDR4_0         (0x1U << GPIO_OSPEEDR_OSPEEDR4_Pos)  /*!< 0x00000100 */
17153 #define GPIO_OSPEEDR_OSPEEDR4_1         (0x2U << GPIO_OSPEEDR_OSPEEDR4_Pos)  /*!< 0x00000200 */
17154 
17155 #define GPIO_OSPEEDR_OSPEEDR5_Pos       (10U)
17156 #define GPIO_OSPEEDR_OSPEEDR5_Msk       (0x3U << GPIO_OSPEEDR_OSPEEDR5_Pos)  /*!< 0x00000C00 */
17157 #define GPIO_OSPEEDR_OSPEEDR5           GPIO_OSPEEDR_OSPEEDR5_Msk
17158 #define GPIO_OSPEEDR_OSPEEDR5_0         (0x1U << GPIO_OSPEEDR_OSPEEDR5_Pos)  /*!< 0x00000400 */
17159 #define GPIO_OSPEEDR_OSPEEDR5_1         (0x2U << GPIO_OSPEEDR_OSPEEDR5_Pos)  /*!< 0x00000800 */
17160 
17161 #define GPIO_OSPEEDR_OSPEEDR6_Pos       (12U)
17162 #define GPIO_OSPEEDR_OSPEEDR6_Msk       (0x3U << GPIO_OSPEEDR_OSPEEDR6_Pos)  /*!< 0x00003000 */
17163 #define GPIO_OSPEEDR_OSPEEDR6           GPIO_OSPEEDR_OSPEEDR6_Msk
17164 #define GPIO_OSPEEDR_OSPEEDR6_0         (0x1U << GPIO_OSPEEDR_OSPEEDR6_Pos)  /*!< 0x00001000 */
17165 #define GPIO_OSPEEDR_OSPEEDR6_1         (0x2U << GPIO_OSPEEDR_OSPEEDR6_Pos)  /*!< 0x00002000 */
17166 
17167 #define GPIO_OSPEEDR_OSPEEDR7_Pos       (14U)
17168 #define GPIO_OSPEEDR_OSPEEDR7_Msk       (0x3U << GPIO_OSPEEDR_OSPEEDR7_Pos)  /*!< 0x0000C000 */
17169 #define GPIO_OSPEEDR_OSPEEDR7           GPIO_OSPEEDR_OSPEEDR7_Msk
17170 #define GPIO_OSPEEDR_OSPEEDR7_0         (0x1U << GPIO_OSPEEDR_OSPEEDR7_Pos)  /*!< 0x00004000 */
17171 #define GPIO_OSPEEDR_OSPEEDR7_1         (0x2U << GPIO_OSPEEDR_OSPEEDR7_Pos)  /*!< 0x00008000 */
17172 
17173 #define GPIO_OSPEEDR_OSPEEDR8_Pos       (16U)
17174 #define GPIO_OSPEEDR_OSPEEDR8_Msk       (0x3U << GPIO_OSPEEDR_OSPEEDR8_Pos)  /*!< 0x00030000 */
17175 #define GPIO_OSPEEDR_OSPEEDR8           GPIO_OSPEEDR_OSPEEDR8_Msk
17176 #define GPIO_OSPEEDR_OSPEEDR8_0         (0x1U << GPIO_OSPEEDR_OSPEEDR8_Pos)  /*!< 0x00010000 */
17177 #define GPIO_OSPEEDR_OSPEEDR8_1         (0x2U << GPIO_OSPEEDR_OSPEEDR8_Pos)  /*!< 0x00020000 */
17178 
17179 #define GPIO_OSPEEDR_OSPEEDR9_Pos       (18U)
17180 #define GPIO_OSPEEDR_OSPEEDR9_Msk       (0x3U << GPIO_OSPEEDR_OSPEEDR9_Pos)  /*!< 0x000C0000 */
17181 #define GPIO_OSPEEDR_OSPEEDR9           GPIO_OSPEEDR_OSPEEDR9_Msk
17182 #define GPIO_OSPEEDR_OSPEEDR9_0         (0x1U << GPIO_OSPEEDR_OSPEEDR9_Pos)  /*!< 0x00040000 */
17183 #define GPIO_OSPEEDR_OSPEEDR9_1         (0x2U << GPIO_OSPEEDR_OSPEEDR9_Pos)  /*!< 0x00080000 */
17184 
17185 #define GPIO_OSPEEDR_OSPEEDR10_Pos      (20U)
17186 #define GPIO_OSPEEDR_OSPEEDR10_Msk      (0x3U << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00300000 */
17187 #define GPIO_OSPEEDR_OSPEEDR10          GPIO_OSPEEDR_OSPEEDR10_Msk
17188 #define GPIO_OSPEEDR_OSPEEDR10_0        (0x1U << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00100000 */
17189 #define GPIO_OSPEEDR_OSPEEDR10_1        (0x2U << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00200000 */
17190 
17191 #define GPIO_OSPEEDR_OSPEEDR11_Pos      (22U)
17192 #define GPIO_OSPEEDR_OSPEEDR11_Msk      (0x3U << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00C00000 */
17193 #define GPIO_OSPEEDR_OSPEEDR11          GPIO_OSPEEDR_OSPEEDR11_Msk
17194 #define GPIO_OSPEEDR_OSPEEDR11_0        (0x1U << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00400000 */
17195 #define GPIO_OSPEEDR_OSPEEDR11_1        (0x2U << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00800000 */
17196 
17197 #define GPIO_OSPEEDR_OSPEEDR12_Pos      (24U)
17198 #define GPIO_OSPEEDR_OSPEEDR12_Msk      (0x3U << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x03000000 */
17199 #define GPIO_OSPEEDR_OSPEEDR12          GPIO_OSPEEDR_OSPEEDR12_Msk
17200 #define GPIO_OSPEEDR_OSPEEDR12_0        (0x1U << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x01000000 */
17201 #define GPIO_OSPEEDR_OSPEEDR12_1        (0x2U << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x02000000 */
17202 
17203 #define GPIO_OSPEEDR_OSPEEDR13_Pos      (26U)
17204 #define GPIO_OSPEEDR_OSPEEDR13_Msk      (0x3U << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x0C000000 */
17205 #define GPIO_OSPEEDR_OSPEEDR13          GPIO_OSPEEDR_OSPEEDR13_Msk
17206 #define GPIO_OSPEEDR_OSPEEDR13_0        (0x1U << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x04000000 */
17207 #define GPIO_OSPEEDR_OSPEEDR13_1        (0x2U << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x08000000 */
17208 
17209 #define GPIO_OSPEEDR_OSPEEDR14_Pos      (28U)
17210 #define GPIO_OSPEEDR_OSPEEDR14_Msk      (0x3U << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x30000000 */
17211 #define GPIO_OSPEEDR_OSPEEDR14          GPIO_OSPEEDR_OSPEEDR14_Msk
17212 #define GPIO_OSPEEDR_OSPEEDR14_0        (0x1U << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x10000000 */
17213 #define GPIO_OSPEEDR_OSPEEDR14_1        (0x2U << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x20000000 */
17214 
17215 #define GPIO_OSPEEDR_OSPEEDR15_Pos      (30U)
17216 #define GPIO_OSPEEDR_OSPEEDR15_Msk      (0x3U << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0xC0000000 */
17217 #define GPIO_OSPEEDR_OSPEEDR15          GPIO_OSPEEDR_OSPEEDR15_Msk
17218 #define GPIO_OSPEEDR_OSPEEDR15_0        (0x1U << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x40000000 */
17219 #define GPIO_OSPEEDR_OSPEEDR15_1        (0x2U << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x80000000 */
17220 
17221 /******************  Bits definition for GPIO_PUPDR register  *****************/
17222 #define GPIO_PUPDR_PUPDR0_Pos            (0U)
17223 #define GPIO_PUPDR_PUPDR0_Msk            (0x3U << GPIO_PUPDR_PUPDR0_Pos)       /*!< 0x00000003 */
17224 #define GPIO_PUPDR_PUPDR0                GPIO_PUPDR_PUPDR0_Msk
17225 #define GPIO_PUPDR_PUPDR0_0              (0x1U << GPIO_PUPDR_PUPDR0_Pos)       /*!< 0x00000001 */
17226 #define GPIO_PUPDR_PUPDR0_1              (0x2U << GPIO_PUPDR_PUPDR0_Pos)       /*!< 0x00000002 */
17227 
17228 #define GPIO_PUPDR_PUPDR1_Pos            (2U)
17229 #define GPIO_PUPDR_PUPDR1_Msk            (0x3U << GPIO_PUPDR_PUPDR1_Pos)       /*!< 0x0000000C */
17230 #define GPIO_PUPDR_PUPDR1                GPIO_PUPDR_PUPDR1_Msk
17231 #define GPIO_PUPDR_PUPDR1_0              (0x1U << GPIO_PUPDR_PUPDR1_Pos)       /*!< 0x00000004 */
17232 #define GPIO_PUPDR_PUPDR1_1              (0x2U << GPIO_PUPDR_PUPDR1_Pos)       /*!< 0x00000008 */
17233 
17234 #define GPIO_PUPDR_PUPDR2_Pos            (4U)
17235 #define GPIO_PUPDR_PUPDR2_Msk            (0x3U << GPIO_PUPDR_PUPDR2_Pos)       /*!< 0x00000030 */
17236 #define GPIO_PUPDR_PUPDR2                GPIO_PUPDR_PUPDR2_Msk
17237 #define GPIO_PUPDR_PUPDR2_0              (0x1U << GPIO_PUPDR_PUPDR2_Pos)       /*!< 0x00000010 */
17238 #define GPIO_PUPDR_PUPDR2_1              (0x2U << GPIO_PUPDR_PUPDR2_Pos)       /*!< 0x00000020 */
17239 
17240 #define GPIO_PUPDR_PUPDR3_Pos            (6U)
17241 #define GPIO_PUPDR_PUPDR3_Msk            (0x3U << GPIO_PUPDR_PUPDR3_Pos)       /*!< 0x000000C0 */
17242 #define GPIO_PUPDR_PUPDR3                GPIO_PUPDR_PUPDR3_Msk
17243 #define GPIO_PUPDR_PUPDR3_0              (0x1U << GPIO_PUPDR_PUPDR3_Pos)       /*!< 0x00000040 */
17244 #define GPIO_PUPDR_PUPDR3_1              (0x2U << GPIO_PUPDR_PUPDR3_Pos)       /*!< 0x00000080 */
17245 
17246 #define GPIO_PUPDR_PUPDR4_Pos            (8U)
17247 #define GPIO_PUPDR_PUPDR4_Msk            (0x3U << GPIO_PUPDR_PUPDR4_Pos)       /*!< 0x00000300 */
17248 #define GPIO_PUPDR_PUPDR4                GPIO_PUPDR_PUPDR4_Msk
17249 #define GPIO_PUPDR_PUPDR4_0              (0x1U << GPIO_PUPDR_PUPDR4_Pos)       /*!< 0x00000100 */
17250 #define GPIO_PUPDR_PUPDR4_1              (0x2U << GPIO_PUPDR_PUPDR4_Pos)       /*!< 0x00000200 */
17251 
17252 #define GPIO_PUPDR_PUPDR5_Pos            (10U)
17253 #define GPIO_PUPDR_PUPDR5_Msk            (0x3U << GPIO_PUPDR_PUPDR5_Pos)       /*!< 0x00000C00 */
17254 #define GPIO_PUPDR_PUPDR5                GPIO_PUPDR_PUPDR5_Msk
17255 #define GPIO_PUPDR_PUPDR5_0              (0x1U << GPIO_PUPDR_PUPDR5_Pos)       /*!< 0x00000400 */
17256 #define GPIO_PUPDR_PUPDR5_1              (0x2U << GPIO_PUPDR_PUPDR5_Pos)       /*!< 0x00000800 */
17257 
17258 #define GPIO_PUPDR_PUPDR6_Pos            (12U)
17259 #define GPIO_PUPDR_PUPDR6_Msk            (0x3U << GPIO_PUPDR_PUPDR6_Pos)       /*!< 0x00003000 */
17260 #define GPIO_PUPDR_PUPDR6                GPIO_PUPDR_PUPDR6_Msk
17261 #define GPIO_PUPDR_PUPDR6_0              (0x1U << GPIO_PUPDR_PUPDR6_Pos)       /*!< 0x00001000 */
17262 #define GPIO_PUPDR_PUPDR6_1              (0x2U << GPIO_PUPDR_PUPDR6_Pos)       /*!< 0x00002000 */
17263 
17264 #define GPIO_PUPDR_PUPDR7_Pos            (14U)
17265 #define GPIO_PUPDR_PUPDR7_Msk            (0x3U << GPIO_PUPDR_PUPDR7_Pos)       /*!< 0x0000C000 */
17266 #define GPIO_PUPDR_PUPDR7                GPIO_PUPDR_PUPDR7_Msk
17267 #define GPIO_PUPDR_PUPDR7_0              (0x1U << GPIO_PUPDR_PUPDR7_Pos)       /*!< 0x00004000 */
17268 #define GPIO_PUPDR_PUPDR7_1              (0x2U << GPIO_PUPDR_PUPDR7_Pos)       /*!< 0x00008000 */
17269 
17270 #define GPIO_PUPDR_PUPDR8_Pos            (16U)
17271 #define GPIO_PUPDR_PUPDR8_Msk            (0x3U << GPIO_PUPDR_PUPDR8_Pos)       /*!< 0x00030000 */
17272 #define GPIO_PUPDR_PUPDR8                GPIO_PUPDR_PUPDR8_Msk
17273 #define GPIO_PUPDR_PUPDR8_0              (0x1U << GPIO_PUPDR_PUPDR8_Pos)       /*!< 0x00010000 */
17274 #define GPIO_PUPDR_PUPDR8_1              (0x2U << GPIO_PUPDR_PUPDR8_Pos)       /*!< 0x00020000 */
17275 
17276 #define GPIO_PUPDR_PUPDR9_Pos            (18U)
17277 #define GPIO_PUPDR_PUPDR9_Msk            (0x3U << GPIO_PUPDR_PUPDR9_Pos)       /*!< 0x000C0000 */
17278 #define GPIO_PUPDR_PUPDR9                GPIO_PUPDR_PUPDR9_Msk
17279 #define GPIO_PUPDR_PUPDR9_0              (0x1U << GPIO_PUPDR_PUPDR9_Pos)       /*!< 0x00040000 */
17280 #define GPIO_PUPDR_PUPDR9_1              (0x2U << GPIO_PUPDR_PUPDR9_Pos)       /*!< 0x00080000 */
17281 
17282 #define GPIO_PUPDR_PUPDR10_Pos           (20U)
17283 #define GPIO_PUPDR_PUPDR10_Msk           (0x3U << GPIO_PUPDR_PUPDR10_Pos)      /*!< 0x00300000 */
17284 #define GPIO_PUPDR_PUPDR10               GPIO_PUPDR_PUPDR10_Msk
17285 #define GPIO_PUPDR_PUPDR10_0             (0x1U << GPIO_PUPDR_PUPDR10_Pos)      /*!< 0x00100000 */
17286 #define GPIO_PUPDR_PUPDR10_1             (0x2U << GPIO_PUPDR_PUPDR10_Pos)      /*!< 0x00200000 */
17287 
17288 #define GPIO_PUPDR_PUPDR11_Pos           (22U)
17289 #define GPIO_PUPDR_PUPDR11_Msk           (0x3U << GPIO_PUPDR_PUPDR11_Pos)      /*!< 0x00C00000 */
17290 #define GPIO_PUPDR_PUPDR11               GPIO_PUPDR_PUPDR11_Msk
17291 #define GPIO_PUPDR_PUPDR11_0             (0x1U << GPIO_PUPDR_PUPDR11_Pos)      /*!< 0x00400000 */
17292 #define GPIO_PUPDR_PUPDR11_1             (0x2U << GPIO_PUPDR_PUPDR11_Pos)      /*!< 0x00800000 */
17293 
17294 #define GPIO_PUPDR_PUPDR12_Pos           (24U)
17295 #define GPIO_PUPDR_PUPDR12_Msk           (0x3U << GPIO_PUPDR_PUPDR12_Pos)      /*!< 0x03000000 */
17296 #define GPIO_PUPDR_PUPDR12               GPIO_PUPDR_PUPDR12_Msk
17297 #define GPIO_PUPDR_PUPDR12_0             (0x1U << GPIO_PUPDR_PUPDR12_Pos)      /*!< 0x01000000 */
17298 #define GPIO_PUPDR_PUPDR12_1             (0x2U << GPIO_PUPDR_PUPDR12_Pos)      /*!< 0x02000000 */
17299 
17300 #define GPIO_PUPDR_PUPDR13_Pos           (26U)
17301 #define GPIO_PUPDR_PUPDR13_Msk           (0x3U << GPIO_PUPDR_PUPDR13_Pos)      /*!< 0x0C000000 */
17302 #define GPIO_PUPDR_PUPDR13               GPIO_PUPDR_PUPDR13_Msk
17303 #define GPIO_PUPDR_PUPDR13_0             (0x1U << GPIO_PUPDR_PUPDR13_Pos)      /*!< 0x04000000 */
17304 #define GPIO_PUPDR_PUPDR13_1             (0x2U << GPIO_PUPDR_PUPDR13_Pos)      /*!< 0x08000000 */
17305 
17306 #define GPIO_PUPDR_PUPDR14_Pos           (28U)
17307 #define GPIO_PUPDR_PUPDR14_Msk           (0x3U << GPIO_PUPDR_PUPDR14_Pos)      /*!< 0x30000000 */
17308 #define GPIO_PUPDR_PUPDR14               GPIO_PUPDR_PUPDR14_Msk
17309 #define GPIO_PUPDR_PUPDR14_0             (0x1U << GPIO_PUPDR_PUPDR14_Pos)      /*!< 0x10000000 */
17310 #define GPIO_PUPDR_PUPDR14_1             (0x2U << GPIO_PUPDR_PUPDR14_Pos)      /*!< 0x20000000 */
17311 
17312 #define GPIO_PUPDR_PUPDR15_Pos           (30U)
17313 #define GPIO_PUPDR_PUPDR15_Msk           (0x3U << GPIO_PUPDR_PUPDR15_Pos)      /*!< 0xC0000000 */
17314 #define GPIO_PUPDR_PUPDR15               GPIO_PUPDR_PUPDR15_Msk
17315 #define GPIO_PUPDR_PUPDR15_0             (0x1U << GPIO_PUPDR_PUPDR15_Pos)      /*!< 0x40000000 */
17316 #define GPIO_PUPDR_PUPDR15_1             (0x2U << GPIO_PUPDR_PUPDR15_Pos)      /*!< 0x80000000 */
17317 
17318 /******************  Bits definition for GPIO_IDR register  *******************/
17319 #define GPIO_IDR_IDR0_Pos               (0U)
17320 #define GPIO_IDR_IDR0_Msk               (0x1U << GPIO_IDR_IDR0_Pos)              /*!< 0x00000001 */
17321 #define GPIO_IDR_IDR0                   GPIO_IDR_IDR0_Msk
17322 #define GPIO_IDR_IDR1_Pos               (1U)
17323 #define GPIO_IDR_IDR1_Msk               (0x1U << GPIO_IDR_IDR1_Pos)              /*!< 0x00000002 */
17324 #define GPIO_IDR_IDR1                   GPIO_IDR_IDR1_Msk
17325 #define GPIO_IDR_IDR2_Pos               (2U)
17326 #define GPIO_IDR_IDR2_Msk               (0x1U << GPIO_IDR_IDR2_Pos)              /*!< 0x00000004 */
17327 #define GPIO_IDR_IDR2                   GPIO_IDR_IDR2_Msk
17328 #define GPIO_IDR_IDR3_Pos               (3U)
17329 #define GPIO_IDR_IDR3_Msk               (0x1U << GPIO_IDR_IDR3_Pos)              /*!< 0x00000008 */
17330 #define GPIO_IDR_IDR3                   GPIO_IDR_IDR3_Msk
17331 #define GPIO_IDR_IDR4_Pos               (4U)
17332 #define GPIO_IDR_IDR4_Msk               (0x1U << GPIO_IDR_IDR4_Pos)              /*!< 0x00000010 */
17333 #define GPIO_IDR_IDR4                   GPIO_IDR_IDR4_Msk
17334 #define GPIO_IDR_IDR5_Pos               (5U)
17335 #define GPIO_IDR_IDR5_Msk               (0x1U << GPIO_IDR_IDR5_Pos)              /*!< 0x00000020 */
17336 #define GPIO_IDR_IDR5                   GPIO_IDR_IDR5_Msk
17337 #define GPIO_IDR_IDR6_Pos               (6U)
17338 #define GPIO_IDR_IDR6_Msk               (0x1U << GPIO_IDR_IDR6_Pos)              /*!< 0x00000040 */
17339 #define GPIO_IDR_IDR6                   GPIO_IDR_IDR6_Msk
17340 #define GPIO_IDR_IDR7_Pos               (7U)
17341 #define GPIO_IDR_IDR7_Msk               (0x1U << GPIO_IDR_IDR7_Pos)              /*!< 0x00000080 */
17342 #define GPIO_IDR_IDR7                   GPIO_IDR_IDR7_Msk
17343 #define GPIO_IDR_IDR8_Pos               (8U)
17344 #define GPIO_IDR_IDR8_Msk               (0x1U << GPIO_IDR_IDR8_Pos)              /*!< 0x00000100 */
17345 #define GPIO_IDR_IDR8                   GPIO_IDR_IDR8_Msk
17346 #define GPIO_IDR_IDR9_Pos               (9U)
17347 #define GPIO_IDR_IDR9_Msk               (0x1U << GPIO_IDR_IDR9_Pos)              /*!< 0x00000200 */
17348 #define GPIO_IDR_IDR9                   GPIO_IDR_IDR9_Msk
17349 #define GPIO_IDR_IDR10_Pos              (10U)
17350 #define GPIO_IDR_IDR10_Msk              (0x1U << GPIO_IDR_IDR10_Pos)             /*!< 0x00000400 */
17351 #define GPIO_IDR_IDR10                  GPIO_IDR_IDR10_Msk
17352 #define GPIO_IDR_IDR11_Pos              (11U)
17353 #define GPIO_IDR_IDR11_Msk              (0x1U << GPIO_IDR_IDR11_Pos)             /*!< 0x00000800 */
17354 #define GPIO_IDR_IDR11                  GPIO_IDR_IDR11_Msk
17355 #define GPIO_IDR_IDR12_Pos              (12U)
17356 #define GPIO_IDR_IDR12_Msk              (0x1U << GPIO_IDR_IDR12_Pos)             /*!< 0x00001000 */
17357 #define GPIO_IDR_IDR12                  GPIO_IDR_IDR12_Msk
17358 #define GPIO_IDR_IDR13_Pos              (13U)
17359 #define GPIO_IDR_IDR13_Msk              (0x1U << GPIO_IDR_IDR13_Pos)             /*!< 0x00002000 */
17360 #define GPIO_IDR_IDR13                  GPIO_IDR_IDR13_Msk
17361 #define GPIO_IDR_IDR14_Pos              (14U)
17362 #define GPIO_IDR_IDR14_Msk              (0x1U << GPIO_IDR_IDR14_Pos)             /*!< 0x00004000 */
17363 #define GPIO_IDR_IDR14                  GPIO_IDR_IDR14_Msk
17364 #define GPIO_IDR_IDR15_Pos              (15U)
17365 #define GPIO_IDR_IDR15_Msk              (0x1U << GPIO_IDR_IDR15_Pos)             /*!< 0x00008000 */
17366 #define GPIO_IDR_IDR15                  GPIO_IDR_IDR15_Msk
17367 
17368 /******************  Bits definition for GPIO_ODR register  *******************/
17369 #define GPIO_ODR_ODR0_Pos               (0U)
17370 #define GPIO_ODR_ODR0_Msk               (0x1U << GPIO_ODR_ODR0_Pos)              /*!< 0x00000001 */
17371 #define GPIO_ODR_ODR0                   GPIO_ODR_ODR0_Msk
17372 #define GPIO_ODR_ODR1_Pos               (1U)
17373 #define GPIO_ODR_ODR1_Msk               (0x1U << GPIO_ODR_ODR1_Pos)              /*!< 0x00000002 */
17374 #define GPIO_ODR_ODR1                   GPIO_ODR_ODR1_Msk
17375 #define GPIO_ODR_ODR2_Pos               (2U)
17376 #define GPIO_ODR_ODR2_Msk               (0x1U << GPIO_ODR_ODR2_Pos)              /*!< 0x00000004 */
17377 #define GPIO_ODR_ODR2                   GPIO_ODR_ODR2_Msk
17378 #define GPIO_ODR_ODR3_Pos               (3U)
17379 #define GPIO_ODR_ODR3_Msk               (0x1U << GPIO_ODR_ODR3_Pos)              /*!< 0x00000008 */
17380 #define GPIO_ODR_ODR3                   GPIO_ODR_ODR3_Msk
17381 #define GPIO_ODR_ODR4_Pos               (4U)
17382 #define GPIO_ODR_ODR4_Msk               (0x1U << GPIO_ODR_ODR4_Pos)              /*!< 0x00000010 */
17383 #define GPIO_ODR_ODR4                   GPIO_ODR_ODR4_Msk
17384 #define GPIO_ODR_ODR5_Pos               (5U)
17385 #define GPIO_ODR_ODR5_Msk               (0x1U << GPIO_ODR_ODR5_Pos)              /*!< 0x00000020 */
17386 #define GPIO_ODR_ODR5                   GPIO_ODR_ODR5_Msk
17387 #define GPIO_ODR_ODR6_Pos               (6U)
17388 #define GPIO_ODR_ODR6_Msk               (0x1U << GPIO_ODR_ODR6_Pos)              /*!< 0x00000040 */
17389 #define GPIO_ODR_ODR6                   GPIO_ODR_ODR6_Msk
17390 #define GPIO_ODR_ODR7_Pos               (7U)
17391 #define GPIO_ODR_ODR7_Msk               (0x1U << GPIO_ODR_ODR7_Pos)              /*!< 0x00000080 */
17392 #define GPIO_ODR_ODR7                   GPIO_ODR_ODR7_Msk
17393 #define GPIO_ODR_ODR8_Pos               (8U)
17394 #define GPIO_ODR_ODR8_Msk               (0x1U << GPIO_ODR_ODR8_Pos)              /*!< 0x00000100 */
17395 #define GPIO_ODR_ODR8                   GPIO_ODR_ODR8_Msk
17396 #define GPIO_ODR_ODR9_Pos               (9U)
17397 #define GPIO_ODR_ODR9_Msk               (0x1U << GPIO_ODR_ODR9_Pos)              /*!< 0x00000200 */
17398 #define GPIO_ODR_ODR9                   GPIO_ODR_ODR9_Msk
17399 #define GPIO_ODR_ODR10_Pos              (10U)
17400 #define GPIO_ODR_ODR10_Msk              (0x1U << GPIO_ODR_ODR10_Pos)             /*!< 0x00000400 */
17401 #define GPIO_ODR_ODR10                  GPIO_ODR_ODR10_Msk
17402 #define GPIO_ODR_ODR11_Pos              (11U)
17403 #define GPIO_ODR_ODR11_Msk              (0x1U << GPIO_ODR_ODR11_Pos)             /*!< 0x00000800 */
17404 #define GPIO_ODR_ODR11                  GPIO_ODR_ODR11_Msk
17405 #define GPIO_ODR_ODR12_Pos              (12U)
17406 #define GPIO_ODR_ODR12_Msk              (0x1U << GPIO_ODR_ODR12_Pos)             /*!< 0x00001000 */
17407 #define GPIO_ODR_ODR12                  GPIO_ODR_ODR12_Msk
17408 #define GPIO_ODR_ODR13_Pos              (13U)
17409 #define GPIO_ODR_ODR13_Msk              (0x1U << GPIO_ODR_ODR13_Pos)             /*!< 0x00002000 */
17410 #define GPIO_ODR_ODR13                  GPIO_ODR_ODR13_Msk
17411 #define GPIO_ODR_ODR14_Pos              (14U)
17412 #define GPIO_ODR_ODR14_Msk              (0x1U << GPIO_ODR_ODR14_Pos)             /*!< 0x00004000 */
17413 #define GPIO_ODR_ODR14                  GPIO_ODR_ODR14_Msk
17414 #define GPIO_ODR_ODR15_Pos              (15U)
17415 #define GPIO_ODR_ODR15_Msk              (0x1U << GPIO_ODR_ODR15_Pos)             /*!< 0x00008000 */
17416 #define GPIO_ODR_ODR15                  GPIO_ODR_ODR15_Msk
17417 
17418 /******************  Bits definition for GPIO_BSRR register  ******************/
17419 #define GPIO_BSRR_BS0_Pos              (0U)
17420 #define GPIO_BSRR_BS0_Msk              (0x1U << GPIO_BSRR_BS0_Pos)             /*!< 0x00000001 */
17421 #define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk
17422 #define GPIO_BSRR_BS1_Pos              (1U)
17423 #define GPIO_BSRR_BS1_Msk              (0x1U << GPIO_BSRR_BS1_Pos)             /*!< 0x00000002 */
17424 #define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk
17425 #define GPIO_BSRR_BS2_Pos              (2U)
17426 #define GPIO_BSRR_BS2_Msk              (0x1U << GPIO_BSRR_BS2_Pos)             /*!< 0x00000004 */
17427 #define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk
17428 #define GPIO_BSRR_BS3_Pos              (3U)
17429 #define GPIO_BSRR_BS3_Msk              (0x1U << GPIO_BSRR_BS3_Pos)             /*!< 0x00000008 */
17430 #define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk
17431 #define GPIO_BSRR_BS4_Pos              (4U)
17432 #define GPIO_BSRR_BS4_Msk              (0x1U << GPIO_BSRR_BS4_Pos)             /*!< 0x00000010 */
17433 #define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk
17434 #define GPIO_BSRR_BS5_Pos              (5U)
17435 #define GPIO_BSRR_BS5_Msk              (0x1U << GPIO_BSRR_BS5_Pos)             /*!< 0x00000020 */
17436 #define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk
17437 #define GPIO_BSRR_BS6_Pos              (6U)
17438 #define GPIO_BSRR_BS6_Msk              (0x1U << GPIO_BSRR_BS6_Pos)             /*!< 0x00000040 */
17439 #define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk
17440 #define GPIO_BSRR_BS7_Pos              (7U)
17441 #define GPIO_BSRR_BS7_Msk              (0x1U << GPIO_BSRR_BS7_Pos)             /*!< 0x00000080 */
17442 #define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk
17443 #define GPIO_BSRR_BS8_Pos              (8U)
17444 #define GPIO_BSRR_BS8_Msk              (0x1U << GPIO_BSRR_BS8_Pos)             /*!< 0x00000100 */
17445 #define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk
17446 #define GPIO_BSRR_BS9_Pos              (9U)
17447 #define GPIO_BSRR_BS9_Msk              (0x1U << GPIO_BSRR_BS9_Pos)             /*!< 0x00000200 */
17448 #define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk
17449 #define GPIO_BSRR_BS10_Pos             (10U)
17450 #define GPIO_BSRR_BS10_Msk             (0x1U << GPIO_BSRR_BS10_Pos)            /*!< 0x00000400 */
17451 #define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk
17452 #define GPIO_BSRR_BS11_Pos             (11U)
17453 #define GPIO_BSRR_BS11_Msk             (0x1U << GPIO_BSRR_BS11_Pos)            /*!< 0x00000800 */
17454 #define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk
17455 #define GPIO_BSRR_BS12_Pos             (12U)
17456 #define GPIO_BSRR_BS12_Msk             (0x1U << GPIO_BSRR_BS12_Pos)            /*!< 0x00001000 */
17457 #define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk
17458 #define GPIO_BSRR_BS13_Pos             (13U)
17459 #define GPIO_BSRR_BS13_Msk             (0x1U << GPIO_BSRR_BS13_Pos)            /*!< 0x00002000 */
17460 #define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk
17461 #define GPIO_BSRR_BS14_Pos             (14U)
17462 #define GPIO_BSRR_BS14_Msk             (0x1U << GPIO_BSRR_BS14_Pos)            /*!< 0x00004000 */
17463 #define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk
17464 #define GPIO_BSRR_BS15_Pos             (15U)
17465 #define GPIO_BSRR_BS15_Msk             (0x1U << GPIO_BSRR_BS15_Pos)            /*!< 0x00008000 */
17466 #define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk
17467 #define GPIO_BSRR_BR0_Pos              (16U)
17468 #define GPIO_BSRR_BR0_Msk              (0x1U << GPIO_BSRR_BR0_Pos)             /*!< 0x00010000 */
17469 #define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk
17470 #define GPIO_BSRR_BR1_Pos              (17U)
17471 #define GPIO_BSRR_BR1_Msk              (0x1U << GPIO_BSRR_BR1_Pos)             /*!< 0x00020000 */
17472 #define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk
17473 #define GPIO_BSRR_BR2_Pos              (18U)
17474 #define GPIO_BSRR_BR2_Msk              (0x1U << GPIO_BSRR_BR2_Pos)             /*!< 0x00040000 */
17475 #define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk
17476 #define GPIO_BSRR_BR3_Pos              (19U)
17477 #define GPIO_BSRR_BR3_Msk              (0x1U << GPIO_BSRR_BR3_Pos)             /*!< 0x00080000 */
17478 #define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk
17479 #define GPIO_BSRR_BR4_Pos              (20U)
17480 #define GPIO_BSRR_BR4_Msk              (0x1U << GPIO_BSRR_BR4_Pos)             /*!< 0x00100000 */
17481 #define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk
17482 #define GPIO_BSRR_BR5_Pos              (21U)
17483 #define GPIO_BSRR_BR5_Msk              (0x1U << GPIO_BSRR_BR5_Pos)             /*!< 0x00200000 */
17484 #define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk
17485 #define GPIO_BSRR_BR6_Pos              (22U)
17486 #define GPIO_BSRR_BR6_Msk              (0x1U << GPIO_BSRR_BR6_Pos)             /*!< 0x00400000 */
17487 #define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk
17488 #define GPIO_BSRR_BR7_Pos              (23U)
17489 #define GPIO_BSRR_BR7_Msk              (0x1U << GPIO_BSRR_BR7_Pos)             /*!< 0x00800000 */
17490 #define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk
17491 #define GPIO_BSRR_BR8_Pos              (24U)
17492 #define GPIO_BSRR_BR8_Msk              (0x1U << GPIO_BSRR_BR8_Pos)             /*!< 0x01000000 */
17493 #define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk
17494 #define GPIO_BSRR_BR9_Pos              (25U)
17495 #define GPIO_BSRR_BR9_Msk              (0x1U << GPIO_BSRR_BR9_Pos)             /*!< 0x02000000 */
17496 #define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk
17497 #define GPIO_BSRR_BR10_Pos             (26U)
17498 #define GPIO_BSRR_BR10_Msk             (0x1U << GPIO_BSRR_BR10_Pos)            /*!< 0x04000000 */
17499 #define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk
17500 #define GPIO_BSRR_BR11_Pos             (27U)
17501 #define GPIO_BSRR_BR11_Msk             (0x1U << GPIO_BSRR_BR11_Pos)            /*!< 0x08000000 */
17502 #define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk
17503 #define GPIO_BSRR_BR12_Pos             (28U)
17504 #define GPIO_BSRR_BR12_Msk             (0x1U << GPIO_BSRR_BR12_Pos)            /*!< 0x10000000 */
17505 #define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk
17506 #define GPIO_BSRR_BR13_Pos             (29U)
17507 #define GPIO_BSRR_BR13_Msk             (0x1U << GPIO_BSRR_BR13_Pos)            /*!< 0x20000000 */
17508 #define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk
17509 #define GPIO_BSRR_BR14_Pos             (30U)
17510 #define GPIO_BSRR_BR14_Msk             (0x1U << GPIO_BSRR_BR14_Pos)            /*!< 0x40000000 */
17511 #define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk
17512 #define GPIO_BSRR_BR15_Pos             (31U)
17513 #define GPIO_BSRR_BR15_Msk             (0x1U << GPIO_BSRR_BR15_Pos)            /*!< 0x80000000 */
17514 #define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk
17515 
17516 /****************** Bit definition for GPIO_LCKR register *********************/
17517 #define GPIO_LCKR_LCK0_Pos             (0U)
17518 #define GPIO_LCKR_LCK0_Msk             (0x1U << GPIO_LCKR_LCK0_Pos)            /*!< 0x00000001 */
17519 #define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk
17520 #define GPIO_LCKR_LCK1_Pos             (1U)
17521 #define GPIO_LCKR_LCK1_Msk             (0x1U << GPIO_LCKR_LCK1_Pos)            /*!< 0x00000002 */
17522 #define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk
17523 #define GPIO_LCKR_LCK2_Pos             (2U)
17524 #define GPIO_LCKR_LCK2_Msk             (0x1U << GPIO_LCKR_LCK2_Pos)            /*!< 0x00000004 */
17525 #define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk
17526 #define GPIO_LCKR_LCK3_Pos             (3U)
17527 #define GPIO_LCKR_LCK3_Msk             (0x1U << GPIO_LCKR_LCK3_Pos)            /*!< 0x00000008 */
17528 #define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk
17529 #define GPIO_LCKR_LCK4_Pos             (4U)
17530 #define GPIO_LCKR_LCK4_Msk             (0x1U << GPIO_LCKR_LCK4_Pos)            /*!< 0x00000010 */
17531 #define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk
17532 #define GPIO_LCKR_LCK5_Pos             (5U)
17533 #define GPIO_LCKR_LCK5_Msk             (0x1U << GPIO_LCKR_LCK5_Pos)            /*!< 0x00000020 */
17534 #define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk
17535 #define GPIO_LCKR_LCK6_Pos             (6U)
17536 #define GPIO_LCKR_LCK6_Msk             (0x1U << GPIO_LCKR_LCK6_Pos)            /*!< 0x00000040 */
17537 #define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk
17538 #define GPIO_LCKR_LCK7_Pos             (7U)
17539 #define GPIO_LCKR_LCK7_Msk             (0x1U << GPIO_LCKR_LCK7_Pos)            /*!< 0x00000080 */
17540 #define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk
17541 #define GPIO_LCKR_LCK8_Pos             (8U)
17542 #define GPIO_LCKR_LCK8_Msk             (0x1U << GPIO_LCKR_LCK8_Pos)            /*!< 0x00000100 */
17543 #define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk
17544 #define GPIO_LCKR_LCK9_Pos             (9U)
17545 #define GPIO_LCKR_LCK9_Msk             (0x1U << GPIO_LCKR_LCK9_Pos)            /*!< 0x00000200 */
17546 #define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk
17547 #define GPIO_LCKR_LCK10_Pos            (10U)
17548 #define GPIO_LCKR_LCK10_Msk            (0x1U << GPIO_LCKR_LCK10_Pos)           /*!< 0x00000400 */
17549 #define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk
17550 #define GPIO_LCKR_LCK11_Pos            (11U)
17551 #define GPIO_LCKR_LCK11_Msk            (0x1U << GPIO_LCKR_LCK11_Pos)           /*!< 0x00000800 */
17552 #define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk
17553 #define GPIO_LCKR_LCK12_Pos            (12U)
17554 #define GPIO_LCKR_LCK12_Msk            (0x1U << GPIO_LCKR_LCK12_Pos)           /*!< 0x00001000 */
17555 #define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk
17556 #define GPIO_LCKR_LCK13_Pos            (13U)
17557 #define GPIO_LCKR_LCK13_Msk            (0x1U << GPIO_LCKR_LCK13_Pos)           /*!< 0x00002000 */
17558 #define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk
17559 #define GPIO_LCKR_LCK14_Pos            (14U)
17560 #define GPIO_LCKR_LCK14_Msk            (0x1U << GPIO_LCKR_LCK14_Pos)           /*!< 0x00004000 */
17561 #define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk
17562 #define GPIO_LCKR_LCK15_Pos            (15U)
17563 #define GPIO_LCKR_LCK15_Msk            (0x1U << GPIO_LCKR_LCK15_Pos)           /*!< 0x00008000 */
17564 #define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk
17565 #define GPIO_LCKR_LCKK_Pos             (16U)
17566 #define GPIO_LCKR_LCKK_Msk             (0x1U << GPIO_LCKR_LCKK_Pos)            /*!< 0x00010000 */
17567 #define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk
17568 
17569 /****************** Bit definition for GPIO_AFRL register *********************/
17570 #define GPIO_AFRL_AFR0_Pos           (0U)
17571 #define GPIO_AFRL_AFR0_Msk           (0xFU << GPIO_AFRL_AFR0_Pos)          /*!< 0x0000000F */
17572 #define GPIO_AFRL_AFR0               GPIO_AFRL_AFR0_Msk
17573 #define GPIO_AFRL_AFR0_0             (0x1U << GPIO_AFRL_AFR0_Pos)          /*!< 0x00000001 */
17574 #define GPIO_AFRL_AFR0_1             (0x2U << GPIO_AFRL_AFR0_Pos)          /*!< 0x00000002 */
17575 #define GPIO_AFRL_AFR0_2             (0x4U << GPIO_AFRL_AFR0_Pos)          /*!< 0x00000004 */
17576 #define GPIO_AFRL_AFR0_3             (0x8U << GPIO_AFRL_AFR0_Pos)          /*!< 0x00000008 */
17577 #define GPIO_AFRL_AFR1_Pos           (4U)
17578 #define GPIO_AFRL_AFR1_Msk           (0xFU << GPIO_AFRL_AFR1_Pos)          /*!< 0x000000F0 */
17579 #define GPIO_AFRL_AFR1               GPIO_AFRL_AFR1_Msk
17580 #define GPIO_AFRL_AFR1_0             (0x1U << GPIO_AFRL_AFR1_Pos)          /*!< 0x00000010 */
17581 #define GPIO_AFRL_AFR1_1             (0x2U << GPIO_AFRL_AFR1_Pos)          /*!< 0x00000020 */
17582 #define GPIO_AFRL_AFR1_2             (0x4U << GPIO_AFRL_AFR1_Pos)          /*!< 0x00000040 */
17583 #define GPIO_AFRL_AFR1_3             (0x8U << GPIO_AFRL_AFR1_Pos)          /*!< 0x00000080 */
17584 #define GPIO_AFRL_AFR2_Pos           (8U)
17585 #define GPIO_AFRL_AFR2_Msk           (0xFU << GPIO_AFRL_AFR2_Pos)          /*!< 0x00000F00 */
17586 #define GPIO_AFRL_AFR2               GPIO_AFRL_AFR2_Msk
17587 #define GPIO_AFRL_AFR2_0             (0x1U << GPIO_AFRL_AFR2_Pos)          /*!< 0x00000100 */
17588 #define GPIO_AFRL_AFR2_1             (0x2U << GPIO_AFRL_AFR2_Pos)          /*!< 0x00000200 */
17589 #define GPIO_AFRL_AFR2_2             (0x4U << GPIO_AFRL_AFR2_Pos)          /*!< 0x00000400 */
17590 #define GPIO_AFRL_AFR2_3             (0x8U << GPIO_AFRL_AFR2_Pos)          /*!< 0x00000800 */
17591 #define GPIO_AFRL_AFR3_Pos           (12U)
17592 #define GPIO_AFRL_AFR3_Msk           (0xFU << GPIO_AFRL_AFR3_Pos)          /*!< 0x0000F000 */
17593 #define GPIO_AFRL_AFR3               GPIO_AFRL_AFR3_Msk
17594 #define GPIO_AFRL_AFR3_0             (0x1U << GPIO_AFRL_AFR3_Pos)          /*!< 0x00001000 */
17595 #define GPIO_AFRL_AFR3_1             (0x2U << GPIO_AFRL_AFR3_Pos)          /*!< 0x00002000 */
17596 #define GPIO_AFRL_AFR3_2             (0x4U << GPIO_AFRL_AFR3_Pos)          /*!< 0x00004000 */
17597 #define GPIO_AFRL_AFR3_3             (0x8U << GPIO_AFRL_AFR3_Pos)          /*!< 0x00008000 */
17598 #define GPIO_AFRL_AFR4_Pos           (16U)
17599 #define GPIO_AFRL_AFR4_Msk           (0xFU << GPIO_AFRL_AFR4_Pos)          /*!< 0x000F0000 */
17600 #define GPIO_AFRL_AFR4               GPIO_AFRL_AFR4_Msk
17601 #define GPIO_AFRL_AFR4_0             (0x1U << GPIO_AFRL_AFR4_Pos)          /*!< 0x00010000 */
17602 #define GPIO_AFRL_AFR4_1             (0x2U << GPIO_AFRL_AFR4_Pos)          /*!< 0x00020000 */
17603 #define GPIO_AFRL_AFR4_2             (0x4U << GPIO_AFRL_AFR4_Pos)          /*!< 0x00040000 */
17604 #define GPIO_AFRL_AFR4_3             (0x8U << GPIO_AFRL_AFR4_Pos)          /*!< 0x00080000 */
17605 #define GPIO_AFRL_AFR5_Pos           (20U)
17606 #define GPIO_AFRL_AFR5_Msk           (0xFU << GPIO_AFRL_AFR5_Pos)          /*!< 0x00F00000 */
17607 #define GPIO_AFRL_AFR5               GPIO_AFRL_AFR5_Msk
17608 #define GPIO_AFRL_AFR5_0             (0x1U << GPIO_AFRL_AFR5_Pos)          /*!< 0x00100000 */
17609 #define GPIO_AFRL_AFR5_1             (0x2U << GPIO_AFRL_AFR5_Pos)          /*!< 0x00200000 */
17610 #define GPIO_AFRL_AFR5_2             (0x4U << GPIO_AFRL_AFR5_Pos)          /*!< 0x00400000 */
17611 #define GPIO_AFRL_AFR5_3             (0x8U << GPIO_AFRL_AFR5_Pos)          /*!< 0x00800000 */
17612 #define GPIO_AFRL_AFR6_Pos           (24U)
17613 #define GPIO_AFRL_AFR6_Msk           (0xFU << GPIO_AFRL_AFR6_Pos)          /*!< 0x0F000000 */
17614 #define GPIO_AFRL_AFR6               GPIO_AFRL_AFR6_Msk
17615 #define GPIO_AFRL_AFR6_0             (0x1U << GPIO_AFRL_AFR6_Pos)          /*!< 0x01000000 */
17616 #define GPIO_AFRL_AFR6_1             (0x2U << GPIO_AFRL_AFR6_Pos)          /*!< 0x02000000 */
17617 #define GPIO_AFRL_AFR6_2             (0x4U << GPIO_AFRL_AFR6_Pos)          /*!< 0x04000000 */
17618 #define GPIO_AFRL_AFR6_3             (0x8U << GPIO_AFRL_AFR6_Pos)          /*!< 0x08000000 */
17619 #define GPIO_AFRL_AFR7_Pos           (28U)
17620 #define GPIO_AFRL_AFR7_Msk           (0xFU << GPIO_AFRL_AFR7_Pos)          /*!< 0xF0000000 */
17621 #define GPIO_AFRL_AFR7               GPIO_AFRL_AFR7_Msk
17622 #define GPIO_AFRL_AFR7_0             (0x1U << GPIO_AFRL_AFR7_Pos)          /*!< 0x10000000 */
17623 #define GPIO_AFRL_AFR7_1             (0x2U << GPIO_AFRL_AFR7_Pos)          /*!< 0x20000000 */
17624 #define GPIO_AFRL_AFR7_2             (0x4U << GPIO_AFRL_AFR7_Pos)          /*!< 0x40000000 */
17625 #define GPIO_AFRL_AFR7_3             (0x8U << GPIO_AFRL_AFR7_Pos)          /*!< 0x80000000 */
17626 
17627 /****************** Bit definition for GPIO_AFRH register *********************/
17628 #define GPIO_AFRH_AFR8_Pos           (0U)
17629 #define GPIO_AFRH_AFR8_Msk           (0xFU << GPIO_AFRH_AFR8_Pos)          /*!< 0x0000000F */
17630 #define GPIO_AFRH_AFR8               GPIO_AFRH_AFR8_Msk
17631 #define GPIO_AFRH_AFR8_0             (0x1U << GPIO_AFRH_AFR8_Pos)          /*!< 0x00000001 */
17632 #define GPIO_AFRH_AFR8_1             (0x2U << GPIO_AFRH_AFR8_Pos)          /*!< 0x00000002 */
17633 #define GPIO_AFRH_AFR8_2             (0x4U << GPIO_AFRH_AFR8_Pos)          /*!< 0x00000004 */
17634 #define GPIO_AFRH_AFR8_3             (0x8U << GPIO_AFRH_AFR8_Pos)          /*!< 0x00000008 */
17635 #define GPIO_AFRH_AFR9_Pos           (4U)
17636 #define GPIO_AFRH_AFR9_Msk           (0xFU << GPIO_AFRH_AFR9_Pos)          /*!< 0x000000F0 */
17637 #define GPIO_AFRH_AFR9               GPIO_AFRH_AFR9_Msk
17638 #define GPIO_AFRH_AFR9_0             (0x1U << GPIO_AFRH_AFR9_Pos)          /*!< 0x00000010 */
17639 #define GPIO_AFRH_AFR9_1             (0x2U << GPIO_AFRH_AFR9_Pos)          /*!< 0x00000020 */
17640 #define GPIO_AFRH_AFR9_2             (0x4U << GPIO_AFRH_AFR9_Pos)          /*!< 0x00000040 */
17641 #define GPIO_AFRH_AFR9_3             (0x8U << GPIO_AFRH_AFR9_Pos)          /*!< 0x00000080 */
17642 #define GPIO_AFRH_AFR10_Pos          (8U)
17643 #define GPIO_AFRH_AFR10_Msk          (0xFU << GPIO_AFRH_AFR10_Pos)         /*!< 0x00000F00 */
17644 #define GPIO_AFRH_AFR10              GPIO_AFRH_AFR10_Msk
17645 #define GPIO_AFRH_AFR10_0            (0x1U << GPIO_AFRH_AFR10_Pos)         /*!< 0x00000100 */
17646 #define GPIO_AFRH_AFR10_1            (0x2U << GPIO_AFRH_AFR10_Pos)         /*!< 0x00000200 */
17647 #define GPIO_AFRH_AFR10_2            (0x4U << GPIO_AFRH_AFR10_Pos)         /*!< 0x00000400 */
17648 #define GPIO_AFRH_AFR10_3            (0x8U << GPIO_AFRH_AFR10_Pos)         /*!< 0x00000800 */
17649 #define GPIO_AFRH_AFR11_Pos          (12U)
17650 #define GPIO_AFRH_AFR11_Msk          (0xFU << GPIO_AFRH_AFR11_Pos)         /*!< 0x0000F000 */
17651 #define GPIO_AFRH_AFR11              GPIO_AFRH_AFR11_Msk
17652 #define GPIO_AFRH_AFR11_0            (0x1U << GPIO_AFRH_AFR11_Pos)         /*!< 0x00001000 */
17653 #define GPIO_AFRH_AFR11_1            (0x2U << GPIO_AFRH_AFR11_Pos)         /*!< 0x00002000 */
17654 #define GPIO_AFRH_AFR11_2            (0x4U << GPIO_AFRH_AFR11_Pos)         /*!< 0x00004000 */
17655 #define GPIO_AFRH_AFR11_3            (0x8U << GPIO_AFRH_AFR11_Pos)         /*!< 0x00008000 */
17656 #define GPIO_AFRH_AFR12_Pos          (16U)
17657 #define GPIO_AFRH_AFR12_Msk          (0xFU << GPIO_AFRH_AFR12_Pos)         /*!< 0x000F0000 */
17658 #define GPIO_AFRH_AFR12              GPIO_AFRH_AFR12_Msk
17659 #define GPIO_AFRH_AFR12_0            (0x1U << GPIO_AFRH_AFR12_Pos)         /*!< 0x00010000 */
17660 #define GPIO_AFRH_AFR12_1            (0x2U << GPIO_AFRH_AFR12_Pos)         /*!< 0x00020000 */
17661 #define GPIO_AFRH_AFR12_2            (0x4U << GPIO_AFRH_AFR12_Pos)         /*!< 0x00040000 */
17662 #define GPIO_AFRH_AFR12_3            (0x8U << GPIO_AFRH_AFR12_Pos)         /*!< 0x00080000 */
17663 #define GPIO_AFRH_AFR13_Pos          (20U)
17664 #define GPIO_AFRH_AFR13_Msk          (0xFU << GPIO_AFRH_AFR13_Pos)         /*!< 0x00F00000 */
17665 #define GPIO_AFRH_AFR13              GPIO_AFRH_AFR13_Msk
17666 #define GPIO_AFRH_AFR13_0            (0x1U << GPIO_AFRH_AFR13_Pos)         /*!< 0x00100000 */
17667 #define GPIO_AFRH_AFR13_1            (0x2U << GPIO_AFRH_AFR13_Pos)         /*!< 0x00200000 */
17668 #define GPIO_AFRH_AFR13_2            (0x4U << GPIO_AFRH_AFR13_Pos)         /*!< 0x00400000 */
17669 #define GPIO_AFRH_AFR13_3            (0x8U << GPIO_AFRH_AFR13_Pos)         /*!< 0x00800000 */
17670 #define GPIO_AFRH_AFR14_Pos          (24U)
17671 #define GPIO_AFRH_AFR14_Msk          (0xFU << GPIO_AFRH_AFR14_Pos)         /*!< 0x0F000000 */
17672 #define GPIO_AFRH_AFR14              GPIO_AFRH_AFR14_Msk
17673 #define GPIO_AFRH_AFR14_0            (0x1U << GPIO_AFRH_AFR14_Pos)         /*!< 0x01000000 */
17674 #define GPIO_AFRH_AFR14_1            (0x2U << GPIO_AFRH_AFR14_Pos)         /*!< 0x02000000 */
17675 #define GPIO_AFRH_AFR14_2            (0x4U << GPIO_AFRH_AFR14_Pos)         /*!< 0x04000000 */
17676 #define GPIO_AFRH_AFR14_3            (0x8U << GPIO_AFRH_AFR14_Pos)         /*!< 0x08000000 */
17677 #define GPIO_AFRH_AFR15_Pos          (28U)
17678 #define GPIO_AFRH_AFR15_Msk          (0xFU << GPIO_AFRH_AFR15_Pos)         /*!< 0xF0000000 */
17679 #define GPIO_AFRH_AFR15              GPIO_AFRH_AFR15_Msk
17680 #define GPIO_AFRH_AFR15_0            (0x1U << GPIO_AFRH_AFR15_Pos)         /*!< 0x10000000 */
17681 #define GPIO_AFRH_AFR15_1            (0x2U << GPIO_AFRH_AFR15_Pos)         /*!< 0x20000000 */
17682 #define GPIO_AFRH_AFR15_2            (0x4U << GPIO_AFRH_AFR15_Pos)         /*!< 0x40000000 */
17683 #define GPIO_AFRH_AFR15_3            (0x8U << GPIO_AFRH_AFR15_Pos)         /*!< 0x80000000 */
17684 
17685 /******************  Bits definition for GPIO_BRR register  ******************/
17686 #define GPIO_BRR_BR0_Pos               (0U)
17687 #define GPIO_BRR_BR0_Msk               (0x1U << GPIO_BRR_BR0_Pos)              /*!< 0x00000001 */
17688 #define GPIO_BRR_BR0                   GPIO_BRR_BR0_Msk
17689 #define GPIO_BRR_BR1_Pos               (1U)
17690 #define GPIO_BRR_BR1_Msk               (0x1U << GPIO_BRR_BR1_Pos)              /*!< 0x00000002 */
17691 #define GPIO_BRR_BR1                   GPIO_BRR_BR1_Msk
17692 #define GPIO_BRR_BR2_Pos               (2U)
17693 #define GPIO_BRR_BR2_Msk               (0x1U << GPIO_BRR_BR2_Pos)              /*!< 0x00000004 */
17694 #define GPIO_BRR_BR2                   GPIO_BRR_BR2_Msk
17695 #define GPIO_BRR_BR3_Pos               (3U)
17696 #define GPIO_BRR_BR3_Msk               (0x1U << GPIO_BRR_BR3_Pos)              /*!< 0x00000008 */
17697 #define GPIO_BRR_BR3                   GPIO_BRR_BR3_Msk
17698 #define GPIO_BRR_BR4_Pos               (4U)
17699 #define GPIO_BRR_BR4_Msk               (0x1U << GPIO_BRR_BR4_Pos)              /*!< 0x00000010 */
17700 #define GPIO_BRR_BR4                   GPIO_BRR_BR4_Msk
17701 #define GPIO_BRR_BR5_Pos               (5U)
17702 #define GPIO_BRR_BR5_Msk               (0x1U << GPIO_BRR_BR5_Pos)              /*!< 0x00000020 */
17703 #define GPIO_BRR_BR5                   GPIO_BRR_BR5_Msk
17704 #define GPIO_BRR_BR6_Pos               (6U)
17705 #define GPIO_BRR_BR6_Msk               (0x1U << GPIO_BRR_BR6_Pos)              /*!< 0x00000040 */
17706 #define GPIO_BRR_BR6                   GPIO_BRR_BR6_Msk
17707 #define GPIO_BRR_BR7_Pos               (7U)
17708 #define GPIO_BRR_BR7_Msk               (0x1U << GPIO_BRR_BR7_Pos)              /*!< 0x00000080 */
17709 #define GPIO_BRR_BR7                   GPIO_BRR_BR7_Msk
17710 #define GPIO_BRR_BR8_Pos               (8U)
17711 #define GPIO_BRR_BR8_Msk               (0x1U << GPIO_BRR_BR8_Pos)              /*!< 0x00000100 */
17712 #define GPIO_BRR_BR8                   GPIO_BRR_BR8_Msk
17713 #define GPIO_BRR_BR9_Pos               (9U)
17714 #define GPIO_BRR_BR9_Msk               (0x1U << GPIO_BRR_BR9_Pos)              /*!< 0x00000200 */
17715 #define GPIO_BRR_BR9                   GPIO_BRR_BR9_Msk
17716 #define GPIO_BRR_BR10_Pos              (10U)
17717 #define GPIO_BRR_BR10_Msk              (0x1U << GPIO_BRR_BR10_Pos)             /*!< 0x00000400 */
17718 #define GPIO_BRR_BR10                  GPIO_BRR_BR10_Msk
17719 #define GPIO_BRR_BR11_Pos              (11U)
17720 #define GPIO_BRR_BR11_Msk              (0x1U << GPIO_BRR_BR11_Pos)             /*!< 0x00000800 */
17721 #define GPIO_BRR_BR11                  GPIO_BRR_BR11_Msk
17722 #define GPIO_BRR_BR12_Pos              (12U)
17723 #define GPIO_BRR_BR12_Msk              (0x1U << GPIO_BRR_BR12_Pos)             /*!< 0x00001000 */
17724 #define GPIO_BRR_BR12                  GPIO_BRR_BR12_Msk
17725 #define GPIO_BRR_BR13_Pos              (13U)
17726 #define GPIO_BRR_BR13_Msk              (0x1U << GPIO_BRR_BR13_Pos)             /*!< 0x00002000 */
17727 #define GPIO_BRR_BR13                  GPIO_BRR_BR13_Msk
17728 #define GPIO_BRR_BR14_Pos              (14U)
17729 #define GPIO_BRR_BR14_Msk              (0x1U << GPIO_BRR_BR14_Pos)             /*!< 0x00004000 */
17730 #define GPIO_BRR_BR14                  GPIO_BRR_BR14_Msk
17731 #define GPIO_BRR_BR15_Pos              (15U)
17732 #define GPIO_BRR_BR15_Msk              (0x1U << GPIO_BRR_BR15_Pos)             /*!< 0x00008000 */
17733 #define GPIO_BRR_BR15                  GPIO_BRR_BR15_Msk
17734 
17735 /******************  Bits definition for GPIO_SECCFGR register  ******************/
17736 #define GPIO_SECCFGR_SEC0_Pos            (0U)
17737 #define GPIO_SECCFGR_SEC0_Msk            (0x1U << GPIO_SECCFGR_SEC0_Pos)           /*!< 0x00000001 */
17738 #define GPIO_SECCFGR_SEC0                GPIO_SECCFGR_SEC0_Msk
17739 #define GPIO_SECCFGR_SEC1_Pos            (1U)
17740 #define GPIO_SECCFGR_SEC1_Msk            (0x1U << GPIO_SECCFGR_SEC1_Pos)           /*!< 0x00000002 */
17741 #define GPIO_SECCFGR_SEC1                GPIO_SECCFGR_SEC1_Msk
17742 #define GPIO_SECCFGR_SEC2_Pos            (2U)
17743 #define GPIO_SECCFGR_SEC2_Msk            (0x1U << GPIO_SECCFGR_SEC2_Pos)           /*!< 0x00000004 */
17744 #define GPIO_SECCFGR_SEC2                GPIO_SECCFGR_SEC2_Msk
17745 #define GPIO_SECCFGR_SEC3_Pos            (3U)
17746 #define GPIO_SECCFGR_SEC3_Msk            (0x1U << GPIO_SECCFGR_SEC3_Pos)           /*!< 0x00000008 */
17747 #define GPIO_SECCFGR_SEC3                GPIO_SECCFGR_SEC3_Msk
17748 #define GPIO_SECCFGR_SEC4_Pos            (4U)
17749 #define GPIO_SECCFGR_SEC4_Msk            (0x1U << GPIO_SECCFGR_SEC4_Pos)           /*!< 0x00000010 */
17750 #define GPIO_SECCFGR_SEC4                GPIO_SECCFGR_SEC4_Msk
17751 #define GPIO_SECCFGR_SEC5_Pos            (5U)
17752 #define GPIO_SECCFGR_SEC5_Msk            (0x1U << GPIO_SECCFGR_SEC5_Pos)           /*!< 0x00000020 */
17753 #define GPIO_SECCFGR_SEC5                GPIO_SECCFGR_SEC5_Msk
17754 #define GPIO_SECCFGR_SEC6_Pos            (6U)
17755 #define GPIO_SECCFGR_SEC6_Msk            (0x1U << GPIO_SECCFGR_SEC6_Pos)           /*!< 0x00000040 */
17756 #define GPIO_SECCFGR_SEC6                GPIO_SECCFGR_SEC6_Msk
17757 #define GPIO_SECCFGR_SEC7_Pos            (7U)
17758 #define GPIO_SECCFGR_SEC7_Msk            (0x1U << GPIO_SECCFGR_SEC7_Pos)           /*!< 0x00000080 */
17759 #define GPIO_SECCFGR_SEC7                GPIO_SECCFGR_SEC7_Msk
17760 
17761 /***************  Bit definition for GPIO_HWCFGR10 register  ****************/
17762 #define GPIO_HWCFGR10_AHB_IOP_Pos     (0U)
17763 #define GPIO_HWCFGR10_AHB_IOP_Msk     (0xFU << GPIO_HWCFGR10_AHB_IOP_Pos)   /*!< 0x0000000F */
17764 #define GPIO_HWCFGR10_AHB_IOP         GPIO_HWCFGR10_AHB_IOP_Msk             /*!< Bus interface configuration */
17765 #define GPIO_HWCFGR10_AHB_IOP_0       (0x1U << GPIO_HWCFGR10_AHB_IOP_Pos)   /*!< 0x00000001 */
17766 #define GPIO_HWCFGR10_AHB_IOP_1       (0x2U << GPIO_HWCFGR10_AHB_IOP_Pos)   /*!< 0x00000002 */
17767 #define GPIO_HWCFGR10_AHB_IOP_2       (0x4U << GPIO_HWCFGR10_AHB_IOP_Pos)   /*!< 0x00000004 */
17768 #define GPIO_HWCFGR10_AHB_IOP_3       (0x8U << GPIO_HWCFGR10_AHB_IOP_Pos)   /*!< 0x00000008 */
17769 #define GPIO_HWCFGR10_AF_SIZE_Pos     (4U)
17770 #define GPIO_HWCFGR10_AF_SIZE_Msk     (0xFU << GPIO_HWCFGR10_AF_SIZE_Pos)   /*!< 0x000000F0 */
17771 #define GPIO_HWCFGR10_AF_SIZE         GPIO_HWCFGR10_AF_SIZE_Msk             /*!< Number of AF available for each I/O */
17772 #define GPIO_HWCFGR10_AF_SIZE_0       (0x1U << GPIO_HWCFGR10_AF_SIZE_Pos)   /*!< 0x00000010 */
17773 #define GPIO_HWCFGR10_AF_SIZE_1       (0x2U << GPIO_HWCFGR10_AF_SIZE_Pos)   /*!< 0x00000020 */
17774 #define GPIO_HWCFGR10_AF_SIZE_2       (0x4U << GPIO_HWCFGR10_AF_SIZE_Pos)   /*!< 0x00000040 */
17775 #define GPIO_HWCFGR10_AF_SIZE_3       (0x8U << GPIO_HWCFGR10_AF_SIZE_Pos)   /*!< 0x00000080 */
17776 #define GPIO_HWCFGR10_SPEED_CFG_Pos   (8U)
17777 #define GPIO_HWCFGR10_SPEED_CFG_Msk   (0xFU << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000F00 */
17778 #define GPIO_HWCFGR10_SPEED_CFG       GPIO_HWCFGR10_SPEED_CFG_Msk           /*!< Number of speed lines for each I/O */
17779 #define GPIO_HWCFGR10_SPEED_CFG_0     (0x1U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000100 */
17780 #define GPIO_HWCFGR10_SPEED_CFG_1     (0x2U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000200 */
17781 #define GPIO_HWCFGR10_SPEED_CFG_2     (0x4U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000400 */
17782 #define GPIO_HWCFGR10_SPEED_CFG_3     (0x8U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000800 */
17783 #define GPIO_HWCFGR10_LOCK_CFG_Pos    (12U)
17784 #define GPIO_HWCFGR10_LOCK_CFG_Msk    (0xFU << GPIO_HWCFGR10_LOCK_CFG_Pos)  /*!< 0x0000F000 */
17785 #define GPIO_HWCFGR10_LOCK_CFG        GPIO_HWCFGR10_LOCK_CFG_Msk            /*!< Lock mechanism activation */
17786 #define GPIO_HWCFGR10_LOCK_CFG_0      (0x1U << GPIO_HWCFGR10_LOCK_CFG_Pos)  /*!< 0x00001000 */
17787 #define GPIO_HWCFGR10_LOCK_CFG_1      (0x2U << GPIO_HWCFGR10_LOCK_CFG_Pos)  /*!< 0x00002000 */
17788 #define GPIO_HWCFGR10_LOCK_CFG_2      (0x4U << GPIO_HWCFGR10_LOCK_CFG_Pos)  /*!< 0x00004000 */
17789 #define GPIO_HWCFGR10_LOCK_CFG_3      (0x8U << GPIO_HWCFGR10_LOCK_CFG_Pos)  /*!< 0x00008000 */
17790 #define GPIO_HWCFGR10_SEC_CFG_Pos     (16U)
17791 #define GPIO_HWCFGR10_SEC_CFG_Msk     (0xFU << GPIO_HWCFGR10_SEC_CFG_Pos)   /*!< 0x000F0000 */
17792 #define GPIO_HWCFGR10_SEC_CFG         GPIO_HWCFGR10_SEC_CFG_Msk             /*!< Security mechanism activation */
17793 #define GPIO_HWCFGR10_SEC_CFG_0       (0x1U << GPIO_HWCFGR10_SEC_CFG_Pos)   /*!< 0x00010000 */
17794 #define GPIO_HWCFGR10_SEC_CFG_1       (0x2U << GPIO_HWCFGR10_SEC_CFG_Pos)   /*!< 0x00020000 */
17795 #define GPIO_HWCFGR10_SEC_CFG_2       (0x4U << GPIO_HWCFGR10_SEC_CFG_Pos)   /*!< 0x00040000 */
17796 #define GPIO_HWCFGR10_SEC_CFG_3       (0x8U << GPIO_HWCFGR10_SEC_CFG_Pos)   /*!< 0x00080000 */
17797 #define GPIO_HWCFGR10_OR_CFG_Pos      (20U)
17798 #define GPIO_HWCFGR10_OR_CFG_Msk      (0xFU << GPIO_HWCFGR10_OR_CFG_Pos)    /*!< 0x00F00000 */
17799 #define GPIO_HWCFGR10_OR_CFG          GPIO_HWCFGR10_OR_CFG_Msk              /*!< Option register configuration */
17800 #define GPIO_HWCFGR10_OR_CFG_0        (0x1U << GPIO_HWCFGR10_OR_CFG_Pos)    /*!< 0x00100000 */
17801 #define GPIO_HWCFGR10_OR_CFG_1        (0x2U << GPIO_HWCFGR10_OR_CFG_Pos)    /*!< 0x00200000 */
17802 #define GPIO_HWCFGR10_OR_CFG_2        (0x4U << GPIO_HWCFGR10_OR_CFG_Pos)    /*!< 0x00400000 */
17803 #define GPIO_HWCFGR10_OR_CFG_3        (0x8U << GPIO_HWCFGR10_OR_CFG_Pos)    /*!< 0x00800000 */
17804 
17805 /****************  Bit definition for GPIO_HWCFGR9 register  ****************/
17806 #define GPIO_HWCFGR9_EN_IO_Pos        (0U)
17807 #define GPIO_HWCFGR9_EN_IO_Msk        (0xFFFFU << GPIO_HWCFGR9_EN_IO_Pos)       /*!< 0x0000FFFF */
17808 #define GPIO_HWCFGR9_EN_IO            GPIO_HWCFGR9_EN_IO_Msk                    /*!< Presence granularity, each bit indicate the presence of the IO */
17809 #define GPIO_HWCFGR9_EN_IO_0          (0x1U << GPIO_HWCFGR9_EN_IO_Pos)          /*!< 0x00000001 */
17810 #define GPIO_HWCFGR9_EN_IO_1          (0x2U << GPIO_HWCFGR9_EN_IO_Pos)          /*!< 0x00000002 */
17811 #define GPIO_HWCFGR9_EN_IO_2          (0x4U << GPIO_HWCFGR9_EN_IO_Pos)          /*!< 0x00000004 */
17812 #define GPIO_HWCFGR9_EN_IO_3          (0x8U << GPIO_HWCFGR9_EN_IO_Pos)          /*!< 0x00000008 */
17813 #define GPIO_HWCFGR9_EN_IO_4          (0x10U << GPIO_HWCFGR9_EN_IO_Pos)         /*!< 0x00000010 */
17814 #define GPIO_HWCFGR9_EN_IO_5          (0x20U << GPIO_HWCFGR9_EN_IO_Pos)         /*!< 0x00000020 */
17815 #define GPIO_HWCFGR9_EN_IO_6          (0x40U << GPIO_HWCFGR9_EN_IO_Pos)         /*!< 0x00000040 */
17816 #define GPIO_HWCFGR9_EN_IO_7          (0x80U << GPIO_HWCFGR9_EN_IO_Pos)         /*!< 0x00000080 */
17817 #define GPIO_HWCFGR9_EN_IO_8          (0x100U << GPIO_HWCFGR9_EN_IO_Pos)        /*!< 0x00000100 */
17818 #define GPIO_HWCFGR9_EN_IO_9          (0x200U << GPIO_HWCFGR9_EN_IO_Pos)        /*!< 0x00000200 */
17819 #define GPIO_HWCFGR9_EN_IO_10         (0x400U << GPIO_HWCFGR9_EN_IO_Pos)        /*!< 0x00000400 */
17820 #define GPIO_HWCFGR9_EN_IO_11         (0x800U << GPIO_HWCFGR9_EN_IO_Pos)        /*!< 0x00000800 */
17821 #define GPIO_HWCFGR9_EN_IO_12         (0x1000U << GPIO_HWCFGR9_EN_IO_Pos)       /*!< 0x00001000 */
17822 #define GPIO_HWCFGR9_EN_IO_13         (0x2000U << GPIO_HWCFGR9_EN_IO_Pos)       /*!< 0x00002000 */
17823 #define GPIO_HWCFGR9_EN_IO_14         (0x4000U << GPIO_HWCFGR9_EN_IO_Pos)       /*!< 0x00004000 */
17824 #define GPIO_HWCFGR9_EN_IO_15         (0x8000U << GPIO_HWCFGR9_EN_IO_Pos)       /*!< 0x00008000 */
17825 
17826 /****************  Bit definition for GPIO_HWCFGR8 register  ****************/
17827 #define GPIO_HWCFGR8_AF_PRIO8_Pos     (0U)
17828 #define GPIO_HWCFGR8_AF_PRIO8_Msk     (0xFU << GPIO_HWCFGR8_AF_PRIO8_Pos)  /*!< 0x0000000F */
17829 #define GPIO_HWCFGR8_AF_PRIO8         GPIO_HWCFGR8_AF_PRIO8_Msk            /*!< Indicate the priority AF for I/O8 (0 to F) */
17830 #define GPIO_HWCFGR8_AF_PRIO8_0       (0x1U << GPIO_HWCFGR8_AF_PRIO8_Pos)  /*!< 0x00000001 */
17831 #define GPIO_HWCFGR8_AF_PRIO8_1       (0x2U << GPIO_HWCFGR8_AF_PRIO8_Pos)  /*!< 0x00000002 */
17832 #define GPIO_HWCFGR8_AF_PRIO8_2       (0x4U << GPIO_HWCFGR8_AF_PRIO8_Pos)  /*!< 0x00000004 */
17833 #define GPIO_HWCFGR8_AF_PRIO8_3       (0x8U << GPIO_HWCFGR8_AF_PRIO8_Pos)  /*!< 0x00000008 */
17834 #define GPIO_HWCFGR8_AF_PRIO9_Pos     (4U)
17835 #define GPIO_HWCFGR8_AF_PRIO9_Msk     (0xFU << GPIO_HWCFGR8_AF_PRIO9_Pos)  /*!< 0x000000F0 */
17836 #define GPIO_HWCFGR8_AF_PRIO9         GPIO_HWCFGR8_AF_PRIO9_Msk            /*!< Indicate the priority AF for I/O9 (0 to F) */
17837 #define GPIO_HWCFGR8_AF_PRIO9_0       (0x1U << GPIO_HWCFGR8_AF_PRIO9_Pos)  /*!< 0x00000010 */
17838 #define GPIO_HWCFGR8_AF_PRIO9_1       (0x2U << GPIO_HWCFGR8_AF_PRIO9_Pos)  /*!< 0x00000020 */
17839 #define GPIO_HWCFGR8_AF_PRIO9_2       (0x4U << GPIO_HWCFGR8_AF_PRIO9_Pos)  /*!< 0x00000040 */
17840 #define GPIO_HWCFGR8_AF_PRIO9_3       (0x8U << GPIO_HWCFGR8_AF_PRIO9_Pos)  /*!< 0x00000080 */
17841 #define GPIO_HWCFGR8_AF_PRIO10_Pos    (8U)
17842 #define GPIO_HWCFGR8_AF_PRIO10_Msk    (0xFU << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000F00 */
17843 #define GPIO_HWCFGR8_AF_PRIO10        GPIO_HWCFGR8_AF_PRIO10_Msk           /*!< Indicate the priority AF for I/O10 (0 to F) */
17844 #define GPIO_HWCFGR8_AF_PRIO10_0      (0x1U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000100 */
17845 #define GPIO_HWCFGR8_AF_PRIO10_1      (0x2U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000200 */
17846 #define GPIO_HWCFGR8_AF_PRIO10_2      (0x4U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000400 */
17847 #define GPIO_HWCFGR8_AF_PRIO10_3      (0x8U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000800 */
17848 #define GPIO_HWCFGR8_AF_PRIO11_Pos    (12U)
17849 #define GPIO_HWCFGR8_AF_PRIO11_Msk    (0xFU << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x0000F000 */
17850 #define GPIO_HWCFGR8_AF_PRIO11        GPIO_HWCFGR8_AF_PRIO11_Msk           /*!< Indicate the priority AF for I/O11 (0 to F) */
17851 #define GPIO_HWCFGR8_AF_PRIO11_0      (0x1U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00001000 */
17852 #define GPIO_HWCFGR8_AF_PRIO11_1      (0x2U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00002000 */
17853 #define GPIO_HWCFGR8_AF_PRIO11_2      (0x4U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00004000 */
17854 #define GPIO_HWCFGR8_AF_PRIO11_3      (0x8U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00008000 */
17855 #define GPIO_HWCFGR8_AF_PRIO12_Pos    (16U)
17856 #define GPIO_HWCFGR8_AF_PRIO12_Msk    (0xFU << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x000F0000 */
17857 #define GPIO_HWCFGR8_AF_PRIO12        GPIO_HWCFGR8_AF_PRIO12_Msk           /*!< Indicate the priority AF for I/O12 (0 to F) */
17858 #define GPIO_HWCFGR8_AF_PRIO12_0      (0x1U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00010000 */
17859 #define GPIO_HWCFGR8_AF_PRIO12_1      (0x2U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00020000 */
17860 #define GPIO_HWCFGR8_AF_PRIO12_2      (0x4U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00040000 */
17861 #define GPIO_HWCFGR8_AF_PRIO12_3      (0x8U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00080000 */
17862 #define GPIO_HWCFGR8_AF_PRIO13_Pos    (20U)
17863 #define GPIO_HWCFGR8_AF_PRIO13_Msk    (0xFU << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00F00000 */
17864 #define GPIO_HWCFGR8_AF_PRIO13        GPIO_HWCFGR8_AF_PRIO13_Msk           /*!< Indicate the priority AF for I/O13 (0 to F) */
17865 #define GPIO_HWCFGR8_AF_PRIO13_0      (0x1U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00100000 */
17866 #define GPIO_HWCFGR8_AF_PRIO13_1      (0x2U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00200000 */
17867 #define GPIO_HWCFGR8_AF_PRIO13_2      (0x4U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00400000 */
17868 #define GPIO_HWCFGR8_AF_PRIO13_3      (0x8U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00800000 */
17869 #define GPIO_HWCFGR8_AF_PRIO14_Pos    (24U)
17870 #define GPIO_HWCFGR8_AF_PRIO14_Msk    (0xFU << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x0F000000 */
17871 #define GPIO_HWCFGR8_AF_PRIO14        GPIO_HWCFGR8_AF_PRIO14_Msk           /*!< Indicate the priority AF for I/O14 (0 to F) */
17872 #define GPIO_HWCFGR8_AF_PRIO14_0      (0x1U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x01000000 */
17873 #define GPIO_HWCFGR8_AF_PRIO14_1      (0x2U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x02000000 */
17874 #define GPIO_HWCFGR8_AF_PRIO14_2      (0x4U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x04000000 */
17875 #define GPIO_HWCFGR8_AF_PRIO14_3      (0x8U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x08000000 */
17876 #define GPIO_HWCFGR8_AF_PRIO15_Pos    (28U)
17877 #define GPIO_HWCFGR8_AF_PRIO15_Msk    (0xFU << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0xF0000000 */
17878 #define GPIO_HWCFGR8_AF_PRIO15        GPIO_HWCFGR8_AF_PRIO15_Msk           /*!< Indicate the priority AF for I/O15 (0 to F) */
17879 #define GPIO_HWCFGR8_AF_PRIO15_0      (0x1U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x10000000 */
17880 #define GPIO_HWCFGR8_AF_PRIO15_1      (0x2U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x20000000 */
17881 #define GPIO_HWCFGR8_AF_PRIO15_2      (0x4U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x40000000 */
17882 #define GPIO_HWCFGR8_AF_PRIO15_3      (0x8U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x80000000 */
17883 
17884 /****************  Bit definition for GPIO_HWCFGR7 register  ****************/
17885 #define GPIO_HWCFGR7_AF_PRIO0_Pos     (0U)
17886 #define GPIO_HWCFGR7_AF_PRIO0_Msk     (0xFU << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x0000000F */
17887 #define GPIO_HWCFGR7_AF_PRIO0         GPIO_HWCFGR7_AF_PRIO0_Msk           /*!< Indicate the priority AF for I/O0 (0 to F) */
17888 #define GPIO_HWCFGR7_AF_PRIO0_0       (0x1U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000001 */
17889 #define GPIO_HWCFGR7_AF_PRIO0_1       (0x2U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000002 */
17890 #define GPIO_HWCFGR7_AF_PRIO0_2       (0x4U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000004 */
17891 #define GPIO_HWCFGR7_AF_PRIO0_3       (0x8U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000008 */
17892 #define GPIO_HWCFGR7_AF_PRIO1_Pos     (4U)
17893 #define GPIO_HWCFGR7_AF_PRIO1_Msk     (0xFU << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x000000F0 */
17894 #define GPIO_HWCFGR7_AF_PRIO1         GPIO_HWCFGR7_AF_PRIO1_Msk           /*!< Indicate the priority AF for I/O1 (0 to F) */
17895 #define GPIO_HWCFGR7_AF_PRIO1_0       (0x1U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000010 */
17896 #define GPIO_HWCFGR7_AF_PRIO1_1       (0x2U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000020 */
17897 #define GPIO_HWCFGR7_AF_PRIO1_2       (0x4U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000040 */
17898 #define GPIO_HWCFGR7_AF_PRIO1_3       (0x8U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000080 */
17899 #define GPIO_HWCFGR7_AF_PRIO2_Pos     (8U)
17900 #define GPIO_HWCFGR7_AF_PRIO2_Msk     (0xFU << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000F00 */
17901 #define GPIO_HWCFGR7_AF_PRIO2         GPIO_HWCFGR7_AF_PRIO2_Msk           /*!< Indicate the priority AF for I/O2 (0 to F) */
17902 #define GPIO_HWCFGR7_AF_PRIO2_0       (0x1U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000100 */
17903 #define GPIO_HWCFGR7_AF_PRIO2_1       (0x2U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000200 */
17904 #define GPIO_HWCFGR7_AF_PRIO2_2       (0x4U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000400 */
17905 #define GPIO_HWCFGR7_AF_PRIO2_3       (0x8U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000800 */
17906 #define GPIO_HWCFGR7_AF_PRIO3_Pos     (12U)
17907 #define GPIO_HWCFGR7_AF_PRIO3_Msk     (0xFU << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x0000F000 */
17908 #define GPIO_HWCFGR7_AF_PRIO3         GPIO_HWCFGR7_AF_PRIO3_Msk           /*!< Indicate the priority AF for I/O3 (0 to F) */
17909 #define GPIO_HWCFGR7_AF_PRIO3_0       (0x1U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00001000 */
17910 #define GPIO_HWCFGR7_AF_PRIO3_1       (0x2U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00002000 */
17911 #define GPIO_HWCFGR7_AF_PRIO3_2       (0x4U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00004000 */
17912 #define GPIO_HWCFGR7_AF_PRIO3_3       (0x8U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00008000 */
17913 #define GPIO_HWCFGR7_AF_PRIO4_Pos     (16U)
17914 #define GPIO_HWCFGR7_AF_PRIO4_Msk     (0xFU << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x000F0000 */
17915 #define GPIO_HWCFGR7_AF_PRIO4         GPIO_HWCFGR7_AF_PRIO4_Msk           /*!< Indicate the priority AF for I/O4 (0 to F) */
17916 #define GPIO_HWCFGR7_AF_PRIO4_0       (0x1U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00010000 */
17917 #define GPIO_HWCFGR7_AF_PRIO4_1       (0x2U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00020000 */
17918 #define GPIO_HWCFGR7_AF_PRIO4_2       (0x4U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00040000 */
17919 #define GPIO_HWCFGR7_AF_PRIO4_3       (0x8U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00080000 */
17920 #define GPIO_HWCFGR7_AF_PRIO5_Pos     (20U)
17921 #define GPIO_HWCFGR7_AF_PRIO5_Msk     (0xFU << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00F00000 */
17922 #define GPIO_HWCFGR7_AF_PRIO5         GPIO_HWCFGR7_AF_PRIO5_Msk           /*!< Indicate the priority AF for I/O5 (0 to F) */
17923 #define GPIO_HWCFGR7_AF_PRIO5_0       (0x1U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00100000 */
17924 #define GPIO_HWCFGR7_AF_PRIO5_1       (0x2U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00200000 */
17925 #define GPIO_HWCFGR7_AF_PRIO5_2       (0x4U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00400000 */
17926 #define GPIO_HWCFGR7_AF_PRIO5_3       (0x8U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00800000 */
17927 #define GPIO_HWCFGR7_AF_PRIO6_Pos     (24U)
17928 #define GPIO_HWCFGR7_AF_PRIO6_Msk     (0xFU << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x0F000000 */
17929 #define GPIO_HWCFGR7_AF_PRIO6         GPIO_HWCFGR7_AF_PRIO6_Msk           /*!< Indicate the priority AF for I/O6 (0 to F) */
17930 #define GPIO_HWCFGR7_AF_PRIO6_0       (0x1U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x01000000 */
17931 #define GPIO_HWCFGR7_AF_PRIO6_1       (0x2U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x02000000 */
17932 #define GPIO_HWCFGR7_AF_PRIO6_2       (0x4U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x04000000 */
17933 #define GPIO_HWCFGR7_AF_PRIO6_3       (0x8U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x08000000 */
17934 #define GPIO_HWCFGR7_AF_PRIO7_Pos     (28U)
17935 #define GPIO_HWCFGR7_AF_PRIO7_Msk     (0xFU << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0xF0000000 */
17936 #define GPIO_HWCFGR7_AF_PRIO7         GPIO_HWCFGR7_AF_PRIO7_Msk           /*!< Indicate the priority AF for I/O7 (0 to F) */
17937 #define GPIO_HWCFGR7_AF_PRIO7_0       (0x1U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x10000000 */
17938 #define GPIO_HWCFGR7_AF_PRIO7_1       (0x2U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x20000000 */
17939 #define GPIO_HWCFGR7_AF_PRIO7_2       (0x4U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x40000000 */
17940 #define GPIO_HWCFGR7_AF_PRIO7_3       (0x8U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x80000000 */
17941 
17942 /****************  Bit definition for GPIO_HWCFGR6 register  ****************/
17943 #define GPIO_HWCFGR6_MODER_RES_Pos    (0U)
17944 #define GPIO_HWCFGR6_MODER_RES_Msk    (0xFFFFFFFFU << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0xFFFFFFFF */
17945 #define GPIO_HWCFGR6_MODER_RES        GPIO_HWCFGR6_MODER_RES_Msk                  /*!< MODER register reset value */
17946 #define GPIO_HWCFGR6_MODER_RES_0      (0x1U << GPIO_HWCFGR6_MODER_RES_Pos)        /*!< 0x00000001 */
17947 #define GPIO_HWCFGR6_MODER_RES_1      (0x2U << GPIO_HWCFGR6_MODER_RES_Pos)        /*!< 0x00000002 */
17948 #define GPIO_HWCFGR6_MODER_RES_2      (0x4U << GPIO_HWCFGR6_MODER_RES_Pos)        /*!< 0x00000004 */
17949 #define GPIO_HWCFGR6_MODER_RES_3      (0x8U << GPIO_HWCFGR6_MODER_RES_Pos)        /*!< 0x00000008 */
17950 #define GPIO_HWCFGR6_MODER_RES_4      (0x10U << GPIO_HWCFGR6_MODER_RES_Pos)       /*!< 0x00000010 */
17951 #define GPIO_HWCFGR6_MODER_RES_5      (0x20U << GPIO_HWCFGR6_MODER_RES_Pos)       /*!< 0x00000020 */
17952 #define GPIO_HWCFGR6_MODER_RES_6      (0x40U << GPIO_HWCFGR6_MODER_RES_Pos)       /*!< 0x00000040 */
17953 #define GPIO_HWCFGR6_MODER_RES_7      (0x80U << GPIO_HWCFGR6_MODER_RES_Pos)       /*!< 0x00000080 */
17954 #define GPIO_HWCFGR6_MODER_RES_8      (0x100U << GPIO_HWCFGR6_MODER_RES_Pos)      /*!< 0x00000100 */
17955 #define GPIO_HWCFGR6_MODER_RES_9      (0x200U << GPIO_HWCFGR6_MODER_RES_Pos)      /*!< 0x00000200 */
17956 #define GPIO_HWCFGR6_MODER_RES_10     (0x400U << GPIO_HWCFGR6_MODER_RES_Pos)      /*!< 0x00000400 */
17957 #define GPIO_HWCFGR6_MODER_RES_11     (0x800U << GPIO_HWCFGR6_MODER_RES_Pos)      /*!< 0x00000800 */
17958 #define GPIO_HWCFGR6_MODER_RES_12     (0x1000U << GPIO_HWCFGR6_MODER_RES_Pos)     /*!< 0x00001000 */
17959 #define GPIO_HWCFGR6_MODER_RES_13     (0x2000U << GPIO_HWCFGR6_MODER_RES_Pos)     /*!< 0x00002000 */
17960 #define GPIO_HWCFGR6_MODER_RES_14     (0x4000U << GPIO_HWCFGR6_MODER_RES_Pos)     /*!< 0x00004000 */
17961 #define GPIO_HWCFGR6_MODER_RES_15     (0x8000U << GPIO_HWCFGR6_MODER_RES_Pos)     /*!< 0x00008000 */
17962 #define GPIO_HWCFGR6_MODER_RES_16     (0x10000U << GPIO_HWCFGR6_MODER_RES_Pos)    /*!< 0x00010000 */
17963 #define GPIO_HWCFGR6_MODER_RES_17     (0x20000U << GPIO_HWCFGR6_MODER_RES_Pos)    /*!< 0x00020000 */
17964 #define GPIO_HWCFGR6_MODER_RES_18     (0x40000U << GPIO_HWCFGR6_MODER_RES_Pos)    /*!< 0x00040000 */
17965 #define GPIO_HWCFGR6_MODER_RES_19     (0x80000U << GPIO_HWCFGR6_MODER_RES_Pos)    /*!< 0x00080000 */
17966 #define GPIO_HWCFGR6_MODER_RES_20     (0x100000U << GPIO_HWCFGR6_MODER_RES_Pos)   /*!< 0x00100000 */
17967 #define GPIO_HWCFGR6_MODER_RES_21     (0x200000U << GPIO_HWCFGR6_MODER_RES_Pos)   /*!< 0x00200000 */
17968 #define GPIO_HWCFGR6_MODER_RES_22     (0x400000U << GPIO_HWCFGR6_MODER_RES_Pos)   /*!< 0x00400000 */
17969 #define GPIO_HWCFGR6_MODER_RES_23     (0x800000U << GPIO_HWCFGR6_MODER_RES_Pos)   /*!< 0x00800000 */
17970 #define GPIO_HWCFGR6_MODER_RES_24     (0x1000000U << GPIO_HWCFGR6_MODER_RES_Pos)  /*!< 0x01000000 */
17971 #define GPIO_HWCFGR6_MODER_RES_25     (0x2000000U << GPIO_HWCFGR6_MODER_RES_Pos)  /*!< 0x02000000 */
17972 #define GPIO_HWCFGR6_MODER_RES_26     (0x4000000U << GPIO_HWCFGR6_MODER_RES_Pos)  /*!< 0x04000000 */
17973 #define GPIO_HWCFGR6_MODER_RES_27     (0x8000000U << GPIO_HWCFGR6_MODER_RES_Pos)  /*!< 0x08000000 */
17974 #define GPIO_HWCFGR6_MODER_RES_28     (0x10000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x10000000 */
17975 #define GPIO_HWCFGR6_MODER_RES_29     (0x20000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x20000000 */
17976 #define GPIO_HWCFGR6_MODER_RES_30     (0x40000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x40000000 */
17977 #define GPIO_HWCFGR6_MODER_RES_31     (0x80000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x80000000 */
17978 
17979 /****************  Bit definition for GPIO_HWCFGR5 register  ****************/
17980 #define GPIO_HWCFGR5_PUPDR_RES_Pos    (0U)
17981 #define GPIO_HWCFGR5_PUPDR_RES_Msk    (0xFFFFFFFFU << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0xFFFFFFFF */
17982 #define GPIO_HWCFGR5_PUPDR_RES        GPIO_HWCFGR5_PUPDR_RES_Msk                  /*!< Pull-up / pull-down register reset value */
17983 #define GPIO_HWCFGR5_PUPDR_RES_0      (0x1U << GPIO_HWCFGR5_PUPDR_RES_Pos)        /*!< 0x00000001 */
17984 #define GPIO_HWCFGR5_PUPDR_RES_1      (0x2U << GPIO_HWCFGR5_PUPDR_RES_Pos)        /*!< 0x00000002 */
17985 #define GPIO_HWCFGR5_PUPDR_RES_2      (0x4U << GPIO_HWCFGR5_PUPDR_RES_Pos)        /*!< 0x00000004 */
17986 #define GPIO_HWCFGR5_PUPDR_RES_3      (0x8U << GPIO_HWCFGR5_PUPDR_RES_Pos)        /*!< 0x00000008 */
17987 #define GPIO_HWCFGR5_PUPDR_RES_4      (0x10U << GPIO_HWCFGR5_PUPDR_RES_Pos)       /*!< 0x00000010 */
17988 #define GPIO_HWCFGR5_PUPDR_RES_5      (0x20U << GPIO_HWCFGR5_PUPDR_RES_Pos)       /*!< 0x00000020 */
17989 #define GPIO_HWCFGR5_PUPDR_RES_6      (0x40U << GPIO_HWCFGR5_PUPDR_RES_Pos)       /*!< 0x00000040 */
17990 #define GPIO_HWCFGR5_PUPDR_RES_7      (0x80U << GPIO_HWCFGR5_PUPDR_RES_Pos)       /*!< 0x00000080 */
17991 #define GPIO_HWCFGR5_PUPDR_RES_8      (0x100U << GPIO_HWCFGR5_PUPDR_RES_Pos)      /*!< 0x00000100 */
17992 #define GPIO_HWCFGR5_PUPDR_RES_9      (0x200U << GPIO_HWCFGR5_PUPDR_RES_Pos)      /*!< 0x00000200 */
17993 #define GPIO_HWCFGR5_PUPDR_RES_10     (0x400U << GPIO_HWCFGR5_PUPDR_RES_Pos)      /*!< 0x00000400 */
17994 #define GPIO_HWCFGR5_PUPDR_RES_11     (0x800U << GPIO_HWCFGR5_PUPDR_RES_Pos)      /*!< 0x00000800 */
17995 #define GPIO_HWCFGR5_PUPDR_RES_12     (0x1000U << GPIO_HWCFGR5_PUPDR_RES_Pos)     /*!< 0x00001000 */
17996 #define GPIO_HWCFGR5_PUPDR_RES_13     (0x2000U << GPIO_HWCFGR5_PUPDR_RES_Pos)     /*!< 0x00002000 */
17997 #define GPIO_HWCFGR5_PUPDR_RES_14     (0x4000U << GPIO_HWCFGR5_PUPDR_RES_Pos)     /*!< 0x00004000 */
17998 #define GPIO_HWCFGR5_PUPDR_RES_15     (0x8000U << GPIO_HWCFGR5_PUPDR_RES_Pos)     /*!< 0x00008000 */
17999 #define GPIO_HWCFGR5_PUPDR_RES_16     (0x10000U << GPIO_HWCFGR5_PUPDR_RES_Pos)    /*!< 0x00010000 */
18000 #define GPIO_HWCFGR5_PUPDR_RES_17     (0x20000U << GPIO_HWCFGR5_PUPDR_RES_Pos)    /*!< 0x00020000 */
18001 #define GPIO_HWCFGR5_PUPDR_RES_18     (0x40000U << GPIO_HWCFGR5_PUPDR_RES_Pos)    /*!< 0x00040000 */
18002 #define GPIO_HWCFGR5_PUPDR_RES_19     (0x80000U << GPIO_HWCFGR5_PUPDR_RES_Pos)    /*!< 0x00080000 */
18003 #define GPIO_HWCFGR5_PUPDR_RES_20     (0x100000U << GPIO_HWCFGR5_PUPDR_RES_Pos)   /*!< 0x00100000 */
18004 #define GPIO_HWCFGR5_PUPDR_RES_21     (0x200000U << GPIO_HWCFGR5_PUPDR_RES_Pos)   /*!< 0x00200000 */
18005 #define GPIO_HWCFGR5_PUPDR_RES_22     (0x400000U << GPIO_HWCFGR5_PUPDR_RES_Pos)   /*!< 0x00400000 */
18006 #define GPIO_HWCFGR5_PUPDR_RES_23     (0x800000U << GPIO_HWCFGR5_PUPDR_RES_Pos)   /*!< 0x00800000 */
18007 #define GPIO_HWCFGR5_PUPDR_RES_24     (0x1000000U << GPIO_HWCFGR5_PUPDR_RES_Pos)  /*!< 0x01000000 */
18008 #define GPIO_HWCFGR5_PUPDR_RES_25     (0x2000000U << GPIO_HWCFGR5_PUPDR_RES_Pos)  /*!< 0x02000000 */
18009 #define GPIO_HWCFGR5_PUPDR_RES_26     (0x4000000U << GPIO_HWCFGR5_PUPDR_RES_Pos)  /*!< 0x04000000 */
18010 #define GPIO_HWCFGR5_PUPDR_RES_27     (0x8000000U << GPIO_HWCFGR5_PUPDR_RES_Pos)  /*!< 0x08000000 */
18011 #define GPIO_HWCFGR5_PUPDR_RES_28     (0x10000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x10000000 */
18012 #define GPIO_HWCFGR5_PUPDR_RES_29     (0x20000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x20000000 */
18013 #define GPIO_HWCFGR5_PUPDR_RES_30     (0x40000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x40000000 */
18014 #define GPIO_HWCFGR5_PUPDR_RES_31     (0x80000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x80000000 */
18015 
18016 /****************  Bit definition for GPIO_HWCFGR4 register  ****************/
18017 #define GPIO_HWCFGR4_OSPEED_RES_Pos   (0U)
18018 #define GPIO_HWCFGR4_OSPEED_RES_Msk   (0xFFFFFFFFU << GPIO_HWCFGR4_OSPEED_RES_Pos)  /*!< 0xFFFFFFFF */
18019 #define GPIO_HWCFGR4_OSPEED_RES       GPIO_HWCFGR4_OSPEED_RES_Msk                   /*!< OSPEED register reset value */
18020 #define GPIO_HWCFGR4_OSPEED_RES_0     (0x1U << GPIO_HWCFGR4_OSPEED_RES_Pos)         /*!< 0x00000001 */
18021 #define GPIO_HWCFGR4_OSPEED_RES_1     (0x2U << GPIO_HWCFGR4_OSPEED_RES_Pos)         /*!< 0x00000002 */
18022 #define GPIO_HWCFGR4_OSPEED_RES_2     (0x4U << GPIO_HWCFGR4_OSPEED_RES_Pos)         /*!< 0x00000004 */
18023 #define GPIO_HWCFGR4_OSPEED_RES_3     (0x8U << GPIO_HWCFGR4_OSPEED_RES_Pos)         /*!< 0x00000008 */
18024 #define GPIO_HWCFGR4_OSPEED_RES_4     (0x10U << GPIO_HWCFGR4_OSPEED_RES_Pos)        /*!< 0x00000010 */
18025 #define GPIO_HWCFGR4_OSPEED_RES_5     (0x20U << GPIO_HWCFGR4_OSPEED_RES_Pos)        /*!< 0x00000020 */
18026 #define GPIO_HWCFGR4_OSPEED_RES_6     (0x40U << GPIO_HWCFGR4_OSPEED_RES_Pos)        /*!< 0x00000040 */
18027 #define GPIO_HWCFGR4_OSPEED_RES_7     (0x80U << GPIO_HWCFGR4_OSPEED_RES_Pos)        /*!< 0x00000080 */
18028 #define GPIO_HWCFGR4_OSPEED_RES_8     (0x100U << GPIO_HWCFGR4_OSPEED_RES_Pos)       /*!< 0x00000100 */
18029 #define GPIO_HWCFGR4_OSPEED_RES_9     (0x200U << GPIO_HWCFGR4_OSPEED_RES_Pos)       /*!< 0x00000200 */
18030 #define GPIO_HWCFGR4_OSPEED_RES_10    (0x400U << GPIO_HWCFGR4_OSPEED_RES_Pos)       /*!< 0x00000400 */
18031 #define GPIO_HWCFGR4_OSPEED_RES_11    (0x800U << GPIO_HWCFGR4_OSPEED_RES_Pos)       /*!< 0x00000800 */
18032 #define GPIO_HWCFGR4_OSPEED_RES_12    (0x1000U << GPIO_HWCFGR4_OSPEED_RES_Pos)      /*!< 0x00001000 */
18033 #define GPIO_HWCFGR4_OSPEED_RES_13    (0x2000U << GPIO_HWCFGR4_OSPEED_RES_Pos)      /*!< 0x00002000 */
18034 #define GPIO_HWCFGR4_OSPEED_RES_14    (0x4000U << GPIO_HWCFGR4_OSPEED_RES_Pos)      /*!< 0x00004000 */
18035 #define GPIO_HWCFGR4_OSPEED_RES_15    (0x8000U << GPIO_HWCFGR4_OSPEED_RES_Pos)      /*!< 0x00008000 */
18036 #define GPIO_HWCFGR4_OSPEED_RES_16    (0x10000U << GPIO_HWCFGR4_OSPEED_RES_Pos)     /*!< 0x00010000 */
18037 #define GPIO_HWCFGR4_OSPEED_RES_17    (0x20000U << GPIO_HWCFGR4_OSPEED_RES_Pos)     /*!< 0x00020000 */
18038 #define GPIO_HWCFGR4_OSPEED_RES_18    (0x40000U << GPIO_HWCFGR4_OSPEED_RES_Pos)     /*!< 0x00040000 */
18039 #define GPIO_HWCFGR4_OSPEED_RES_19    (0x80000U << GPIO_HWCFGR4_OSPEED_RES_Pos)     /*!< 0x00080000 */
18040 #define GPIO_HWCFGR4_OSPEED_RES_20    (0x100000U << GPIO_HWCFGR4_OSPEED_RES_Pos)    /*!< 0x00100000 */
18041 #define GPIO_HWCFGR4_OSPEED_RES_21    (0x200000U << GPIO_HWCFGR4_OSPEED_RES_Pos)    /*!< 0x00200000 */
18042 #define GPIO_HWCFGR4_OSPEED_RES_22    (0x400000U << GPIO_HWCFGR4_OSPEED_RES_Pos)    /*!< 0x00400000 */
18043 #define GPIO_HWCFGR4_OSPEED_RES_23    (0x800000U << GPIO_HWCFGR4_OSPEED_RES_Pos)    /*!< 0x00800000 */
18044 #define GPIO_HWCFGR4_OSPEED_RES_24    (0x1000000U << GPIO_HWCFGR4_OSPEED_RES_Pos)   /*!< 0x01000000 */
18045 #define GPIO_HWCFGR4_OSPEED_RES_25    (0x2000000U << GPIO_HWCFGR4_OSPEED_RES_Pos)   /*!< 0x02000000 */
18046 #define GPIO_HWCFGR4_OSPEED_RES_26    (0x4000000U << GPIO_HWCFGR4_OSPEED_RES_Pos)   /*!< 0x04000000 */
18047 #define GPIO_HWCFGR4_OSPEED_RES_27    (0x8000000U << GPIO_HWCFGR4_OSPEED_RES_Pos)   /*!< 0x08000000 */
18048 #define GPIO_HWCFGR4_OSPEED_RES_28    (0x10000000U << GPIO_HWCFGR4_OSPEED_RES_Pos)  /*!< 0x10000000 */
18049 #define GPIO_HWCFGR4_OSPEED_RES_29    (0x20000000U << GPIO_HWCFGR4_OSPEED_RES_Pos)  /*!< 0x20000000 */
18050 #define GPIO_HWCFGR4_OSPEED_RES_30    (0x40000000U << GPIO_HWCFGR4_OSPEED_RES_Pos)  /*!< 0x40000000 */
18051 #define GPIO_HWCFGR4_OSPEED_RES_31    (0x80000000U << GPIO_HWCFGR4_OSPEED_RES_Pos)  /*!< 0x80000000 */
18052 
18053 /****************  Bit definition for GPIO_HWCFGR3 register  ****************/
18054 #define GPIO_HWCFGR3_ODR_RES_Pos      (0U)
18055 #define GPIO_HWCFGR3_ODR_RES_Msk      (0xFFFFU << GPIO_HWCFGR3_ODR_RES_Pos)     /*!< 0x0000FFFF */
18056 #define GPIO_HWCFGR3_ODR_RES          GPIO_HWCFGR3_ODR_RES_Msk                  /*!< Output data register reset value */
18057 #define GPIO_HWCFGR3_ODR_RES_0        (0x1U << GPIO_HWCFGR3_ODR_RES_Pos)        /*!< 0x00000001 */
18058 #define GPIO_HWCFGR3_ODR_RES_1        (0x2U << GPIO_HWCFGR3_ODR_RES_Pos)        /*!< 0x00000002 */
18059 #define GPIO_HWCFGR3_ODR_RES_2        (0x4U << GPIO_HWCFGR3_ODR_RES_Pos)        /*!< 0x00000004 */
18060 #define GPIO_HWCFGR3_ODR_RES_3        (0x8U << GPIO_HWCFGR3_ODR_RES_Pos)        /*!< 0x00000008 */
18061 #define GPIO_HWCFGR3_ODR_RES_4        (0x10U << GPIO_HWCFGR3_ODR_RES_Pos)       /*!< 0x00000010 */
18062 #define GPIO_HWCFGR3_ODR_RES_5        (0x20U << GPIO_HWCFGR3_ODR_RES_Pos)       /*!< 0x00000020 */
18063 #define GPIO_HWCFGR3_ODR_RES_6        (0x40U << GPIO_HWCFGR3_ODR_RES_Pos)       /*!< 0x00000040 */
18064 #define GPIO_HWCFGR3_ODR_RES_7        (0x80U << GPIO_HWCFGR3_ODR_RES_Pos)       /*!< 0x00000080 */
18065 #define GPIO_HWCFGR3_ODR_RES_8        (0x100U << GPIO_HWCFGR3_ODR_RES_Pos)      /*!< 0x00000100 */
18066 #define GPIO_HWCFGR3_ODR_RES_9        (0x200U << GPIO_HWCFGR3_ODR_RES_Pos)      /*!< 0x00000200 */
18067 #define GPIO_HWCFGR3_ODR_RES_10       (0x400U << GPIO_HWCFGR3_ODR_RES_Pos)      /*!< 0x00000400 */
18068 #define GPIO_HWCFGR3_ODR_RES_11       (0x800U << GPIO_HWCFGR3_ODR_RES_Pos)      /*!< 0x00000800 */
18069 #define GPIO_HWCFGR3_ODR_RES_12       (0x1000U << GPIO_HWCFGR3_ODR_RES_Pos)     /*!< 0x00001000 */
18070 #define GPIO_HWCFGR3_ODR_RES_13       (0x2000U << GPIO_HWCFGR3_ODR_RES_Pos)     /*!< 0x00002000 */
18071 #define GPIO_HWCFGR3_ODR_RES_14       (0x4000U << GPIO_HWCFGR3_ODR_RES_Pos)     /*!< 0x00004000 */
18072 #define GPIO_HWCFGR3_ODR_RES_15       (0x8000U << GPIO_HWCFGR3_ODR_RES_Pos)     /*!< 0x00008000 */
18073 #define GPIO_HWCFGR3_OTYPER_RES_Pos   (16U)
18074 #define GPIO_HWCFGR3_OTYPER_RES_Msk   (0xFFFFU << GPIO_HWCFGR3_OTYPER_RES_Pos)  /*!< 0xFFFF0000 */
18075 #define GPIO_HWCFGR3_OTYPER_RES       GPIO_HWCFGR3_OTYPER_RES_Msk               /*!< Output type register reset value */
18076 #define GPIO_HWCFGR3_OTYPER_RES_0     (0x1U << GPIO_HWCFGR3_OTYPER_RES_Pos)     /*!< 0x00010000 */
18077 #define GPIO_HWCFGR3_OTYPER_RES_1     (0x2U << GPIO_HWCFGR3_OTYPER_RES_Pos)     /*!< 0x00020000 */
18078 #define GPIO_HWCFGR3_OTYPER_RES_2     (0x4U << GPIO_HWCFGR3_OTYPER_RES_Pos)     /*!< 0x00040000 */
18079 #define GPIO_HWCFGR3_OTYPER_RES_3     (0x8U << GPIO_HWCFGR3_OTYPER_RES_Pos)     /*!< 0x00080000 */
18080 #define GPIO_HWCFGR3_OTYPER_RES_4     (0x10U << GPIO_HWCFGR3_OTYPER_RES_Pos)    /*!< 0x00100000 */
18081 #define GPIO_HWCFGR3_OTYPER_RES_5     (0x20U << GPIO_HWCFGR3_OTYPER_RES_Pos)    /*!< 0x00200000 */
18082 #define GPIO_HWCFGR3_OTYPER_RES_6     (0x40U << GPIO_HWCFGR3_OTYPER_RES_Pos)    /*!< 0x00400000 */
18083 #define GPIO_HWCFGR3_OTYPER_RES_7     (0x80U << GPIO_HWCFGR3_OTYPER_RES_Pos)    /*!< 0x00800000 */
18084 #define GPIO_HWCFGR3_OTYPER_RES_8     (0x100U << GPIO_HWCFGR3_OTYPER_RES_Pos)   /*!< 0x01000000 */
18085 #define GPIO_HWCFGR3_OTYPER_RES_9     (0x200U << GPIO_HWCFGR3_OTYPER_RES_Pos)   /*!< 0x02000000 */
18086 #define GPIO_HWCFGR3_OTYPER_RES_10    (0x400U << GPIO_HWCFGR3_OTYPER_RES_Pos)   /*!< 0x04000000 */
18087 #define GPIO_HWCFGR3_OTYPER_RES_11    (0x800U << GPIO_HWCFGR3_OTYPER_RES_Pos)   /*!< 0x08000000 */
18088 #define GPIO_HWCFGR3_OTYPER_RES_12    (0x1000U << GPIO_HWCFGR3_OTYPER_RES_Pos)  /*!< 0x10000000 */
18089 #define GPIO_HWCFGR3_OTYPER_RES_13    (0x2000U << GPIO_HWCFGR3_OTYPER_RES_Pos)  /*!< 0x20000000 */
18090 #define GPIO_HWCFGR3_OTYPER_RES_14    (0x4000U << GPIO_HWCFGR3_OTYPER_RES_Pos)  /*!< 0x40000000 */
18091 #define GPIO_HWCFGR3_OTYPER_RES_15    (0x8000U << GPIO_HWCFGR3_OTYPER_RES_Pos)  /*!< 0x80000000 */
18092 
18093 /****************  Bit definition for GPIO_HWCFGR2 register  ****************/
18094 #define GPIO_HWCFGR2_AFRL_RES_Pos     (0U)
18095 #define GPIO_HWCFGR2_AFRL_RES_Msk     (0xFFFFFFFFU << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0xFFFFFFFF */
18096 #define GPIO_HWCFGR2_AFRL_RES         GPIO_HWCFGR2_AFRL_RES_Msk                  /*!< AF register low reset value */
18097 #define GPIO_HWCFGR2_AFRL_RES_0       (0x1U << GPIO_HWCFGR2_AFRL_RES_Pos)        /*!< 0x00000001 */
18098 #define GPIO_HWCFGR2_AFRL_RES_1       (0x2U << GPIO_HWCFGR2_AFRL_RES_Pos)        /*!< 0x00000002 */
18099 #define GPIO_HWCFGR2_AFRL_RES_2       (0x4U << GPIO_HWCFGR2_AFRL_RES_Pos)        /*!< 0x00000004 */
18100 #define GPIO_HWCFGR2_AFRL_RES_3       (0x8U << GPIO_HWCFGR2_AFRL_RES_Pos)        /*!< 0x00000008 */
18101 #define GPIO_HWCFGR2_AFRL_RES_4       (0x10U << GPIO_HWCFGR2_AFRL_RES_Pos)       /*!< 0x00000010 */
18102 #define GPIO_HWCFGR2_AFRL_RES_5       (0x20U << GPIO_HWCFGR2_AFRL_RES_Pos)       /*!< 0x00000020 */
18103 #define GPIO_HWCFGR2_AFRL_RES_6       (0x40U << GPIO_HWCFGR2_AFRL_RES_Pos)       /*!< 0x00000040 */
18104 #define GPIO_HWCFGR2_AFRL_RES_7       (0x80U << GPIO_HWCFGR2_AFRL_RES_Pos)       /*!< 0x00000080 */
18105 #define GPIO_HWCFGR2_AFRL_RES_8       (0x100U << GPIO_HWCFGR2_AFRL_RES_Pos)      /*!< 0x00000100 */
18106 #define GPIO_HWCFGR2_AFRL_RES_9       (0x200U << GPIO_HWCFGR2_AFRL_RES_Pos)      /*!< 0x00000200 */
18107 #define GPIO_HWCFGR2_AFRL_RES_10      (0x400U << GPIO_HWCFGR2_AFRL_RES_Pos)      /*!< 0x00000400 */
18108 #define GPIO_HWCFGR2_AFRL_RES_11      (0x800U << GPIO_HWCFGR2_AFRL_RES_Pos)      /*!< 0x00000800 */
18109 #define GPIO_HWCFGR2_AFRL_RES_12      (0x1000U << GPIO_HWCFGR2_AFRL_RES_Pos)     /*!< 0x00001000 */
18110 #define GPIO_HWCFGR2_AFRL_RES_13      (0x2000U << GPIO_HWCFGR2_AFRL_RES_Pos)     /*!< 0x00002000 */
18111 #define GPIO_HWCFGR2_AFRL_RES_14      (0x4000U << GPIO_HWCFGR2_AFRL_RES_Pos)     /*!< 0x00004000 */
18112 #define GPIO_HWCFGR2_AFRL_RES_15      (0x8000U << GPIO_HWCFGR2_AFRL_RES_Pos)     /*!< 0x00008000 */
18113 #define GPIO_HWCFGR2_AFRL_RES_16      (0x10000U << GPIO_HWCFGR2_AFRL_RES_Pos)    /*!< 0x00010000 */
18114 #define GPIO_HWCFGR2_AFRL_RES_17      (0x20000U << GPIO_HWCFGR2_AFRL_RES_Pos)    /*!< 0x00020000 */
18115 #define GPIO_HWCFGR2_AFRL_RES_18      (0x40000U << GPIO_HWCFGR2_AFRL_RES_Pos)    /*!< 0x00040000 */
18116 #define GPIO_HWCFGR2_AFRL_RES_19      (0x80000U << GPIO_HWCFGR2_AFRL_RES_Pos)    /*!< 0x00080000 */
18117 #define GPIO_HWCFGR2_AFRL_RES_20      (0x100000U << GPIO_HWCFGR2_AFRL_RES_Pos)   /*!< 0x00100000 */
18118 #define GPIO_HWCFGR2_AFRL_RES_21      (0x200000U << GPIO_HWCFGR2_AFRL_RES_Pos)   /*!< 0x00200000 */
18119 #define GPIO_HWCFGR2_AFRL_RES_22      (0x400000U << GPIO_HWCFGR2_AFRL_RES_Pos)   /*!< 0x00400000 */
18120 #define GPIO_HWCFGR2_AFRL_RES_23      (0x800000U << GPIO_HWCFGR2_AFRL_RES_Pos)   /*!< 0x00800000 */
18121 #define GPIO_HWCFGR2_AFRL_RES_24      (0x1000000U << GPIO_HWCFGR2_AFRL_RES_Pos)  /*!< 0x01000000 */
18122 #define GPIO_HWCFGR2_AFRL_RES_25      (0x2000000U << GPIO_HWCFGR2_AFRL_RES_Pos)  /*!< 0x02000000 */
18123 #define GPIO_HWCFGR2_AFRL_RES_26      (0x4000000U << GPIO_HWCFGR2_AFRL_RES_Pos)  /*!< 0x04000000 */
18124 #define GPIO_HWCFGR2_AFRL_RES_27      (0x8000000U << GPIO_HWCFGR2_AFRL_RES_Pos)  /*!< 0x08000000 */
18125 #define GPIO_HWCFGR2_AFRL_RES_28      (0x10000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x10000000 */
18126 #define GPIO_HWCFGR2_AFRL_RES_29      (0x20000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x20000000 */
18127 #define GPIO_HWCFGR2_AFRL_RES_30      (0x40000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x40000000 */
18128 #define GPIO_HWCFGR2_AFRL_RES_31      (0x80000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x80000000 */
18129 
18130 /****************  Bit definition for GPIO_HWCFGR1 register  ****************/
18131 #define GPIO_HWCFGR1_AFRH_RES_Pos     (0U)
18132 #define GPIO_HWCFGR1_AFRH_RES_Msk     (0xFFFFFFFFU << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0xFFFFFFFF */
18133 #define GPIO_HWCFGR1_AFRH_RES         GPIO_HWCFGR1_AFRH_RES_Msk                  /*!< AF register high reset value */
18134 #define GPIO_HWCFGR1_AFRH_RES_0       (0x1U << GPIO_HWCFGR1_AFRH_RES_Pos)        /*!< 0x00000001 */
18135 #define GPIO_HWCFGR1_AFRH_RES_1       (0x2U << GPIO_HWCFGR1_AFRH_RES_Pos)        /*!< 0x00000002 */
18136 #define GPIO_HWCFGR1_AFRH_RES_2       (0x4U << GPIO_HWCFGR1_AFRH_RES_Pos)        /*!< 0x00000004 */
18137 #define GPIO_HWCFGR1_AFRH_RES_3       (0x8U << GPIO_HWCFGR1_AFRH_RES_Pos)        /*!< 0x00000008 */
18138 #define GPIO_HWCFGR1_AFRH_RES_4       (0x10U << GPIO_HWCFGR1_AFRH_RES_Pos)       /*!< 0x00000010 */
18139 #define GPIO_HWCFGR1_AFRH_RES_5       (0x20U << GPIO_HWCFGR1_AFRH_RES_Pos)       /*!< 0x00000020 */
18140 #define GPIO_HWCFGR1_AFRH_RES_6       (0x40U << GPIO_HWCFGR1_AFRH_RES_Pos)       /*!< 0x00000040 */
18141 #define GPIO_HWCFGR1_AFRH_RES_7       (0x80U << GPIO_HWCFGR1_AFRH_RES_Pos)       /*!< 0x00000080 */
18142 #define GPIO_HWCFGR1_AFRH_RES_8       (0x100U << GPIO_HWCFGR1_AFRH_RES_Pos)      /*!< 0x00000100 */
18143 #define GPIO_HWCFGR1_AFRH_RES_9       (0x200U << GPIO_HWCFGR1_AFRH_RES_Pos)      /*!< 0x00000200 */
18144 #define GPIO_HWCFGR1_AFRH_RES_10      (0x400U << GPIO_HWCFGR1_AFRH_RES_Pos)      /*!< 0x00000400 */
18145 #define GPIO_HWCFGR1_AFRH_RES_11      (0x800U << GPIO_HWCFGR1_AFRH_RES_Pos)      /*!< 0x00000800 */
18146 #define GPIO_HWCFGR1_AFRH_RES_12      (0x1000U << GPIO_HWCFGR1_AFRH_RES_Pos)     /*!< 0x00001000 */
18147 #define GPIO_HWCFGR1_AFRH_RES_13      (0x2000U << GPIO_HWCFGR1_AFRH_RES_Pos)     /*!< 0x00002000 */
18148 #define GPIO_HWCFGR1_AFRH_RES_14      (0x4000U << GPIO_HWCFGR1_AFRH_RES_Pos)     /*!< 0x00004000 */
18149 #define GPIO_HWCFGR1_AFRH_RES_15      (0x8000U << GPIO_HWCFGR1_AFRH_RES_Pos)     /*!< 0x00008000 */
18150 #define GPIO_HWCFGR1_AFRH_RES_16      (0x10000U << GPIO_HWCFGR1_AFRH_RES_Pos)    /*!< 0x00010000 */
18151 #define GPIO_HWCFGR1_AFRH_RES_17      (0x20000U << GPIO_HWCFGR1_AFRH_RES_Pos)    /*!< 0x00020000 */
18152 #define GPIO_HWCFGR1_AFRH_RES_18      (0x40000U << GPIO_HWCFGR1_AFRH_RES_Pos)    /*!< 0x00040000 */
18153 #define GPIO_HWCFGR1_AFRH_RES_19      (0x80000U << GPIO_HWCFGR1_AFRH_RES_Pos)    /*!< 0x00080000 */
18154 #define GPIO_HWCFGR1_AFRH_RES_20      (0x100000U << GPIO_HWCFGR1_AFRH_RES_Pos)   /*!< 0x00100000 */
18155 #define GPIO_HWCFGR1_AFRH_RES_21      (0x200000U << GPIO_HWCFGR1_AFRH_RES_Pos)   /*!< 0x00200000 */
18156 #define GPIO_HWCFGR1_AFRH_RES_22      (0x400000U << GPIO_HWCFGR1_AFRH_RES_Pos)   /*!< 0x00400000 */
18157 #define GPIO_HWCFGR1_AFRH_RES_23      (0x800000U << GPIO_HWCFGR1_AFRH_RES_Pos)   /*!< 0x00800000 */
18158 #define GPIO_HWCFGR1_AFRH_RES_24      (0x1000000U << GPIO_HWCFGR1_AFRH_RES_Pos)  /*!< 0x01000000 */
18159 #define GPIO_HWCFGR1_AFRH_RES_25      (0x2000000U << GPIO_HWCFGR1_AFRH_RES_Pos)  /*!< 0x02000000 */
18160 #define GPIO_HWCFGR1_AFRH_RES_26      (0x4000000U << GPIO_HWCFGR1_AFRH_RES_Pos)  /*!< 0x04000000 */
18161 #define GPIO_HWCFGR1_AFRH_RES_27      (0x8000000U << GPIO_HWCFGR1_AFRH_RES_Pos)  /*!< 0x08000000 */
18162 #define GPIO_HWCFGR1_AFRH_RES_28      (0x10000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x10000000 */
18163 #define GPIO_HWCFGR1_AFRH_RES_29      (0x20000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x20000000 */
18164 #define GPIO_HWCFGR1_AFRH_RES_30      (0x40000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x40000000 */
18165 #define GPIO_HWCFGR1_AFRH_RES_31      (0x80000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x80000000 */
18166 
18167 /****************  Bit definition for GPIO_HWCFGR0 register  ****************/
18168 #define GPIO_HWCFGR0_OR_RES_Pos       (0U)
18169 #define GPIO_HWCFGR0_OR_RES_Msk       (0xFFFFU << GPIO_HWCFGR0_OR_RES_Pos)      /*!< 0x0000FFFF */
18170 #define GPIO_HWCFGR0_OR_RES           GPIO_HWCFGR0_OR_RES_Msk                   /*!< Option register reset value */
18171 #define GPIO_HWCFGR0_OR_RES_0         (0x1U << GPIO_HWCFGR0_OR_RES_Pos)         /*!< 0x00000001 */
18172 #define GPIO_HWCFGR0_OR_RES_1         (0x2U << GPIO_HWCFGR0_OR_RES_Pos)         /*!< 0x00000002 */
18173 #define GPIO_HWCFGR0_OR_RES_2         (0x4U << GPIO_HWCFGR0_OR_RES_Pos)         /*!< 0x00000004 */
18174 #define GPIO_HWCFGR0_OR_RES_3         (0x8U << GPIO_HWCFGR0_OR_RES_Pos)         /*!< 0x00000008 */
18175 #define GPIO_HWCFGR0_OR_RES_4         (0x10U << GPIO_HWCFGR0_OR_RES_Pos)        /*!< 0x00000010 */
18176 #define GPIO_HWCFGR0_OR_RES_5         (0x20U << GPIO_HWCFGR0_OR_RES_Pos)        /*!< 0x00000020 */
18177 #define GPIO_HWCFGR0_OR_RES_6         (0x40U << GPIO_HWCFGR0_OR_RES_Pos)        /*!< 0x00000040 */
18178 #define GPIO_HWCFGR0_OR_RES_7         (0x80U << GPIO_HWCFGR0_OR_RES_Pos)        /*!< 0x00000080 */
18179 #define GPIO_HWCFGR0_OR_RES_8         (0x100U << GPIO_HWCFGR0_OR_RES_Pos)       /*!< 0x00000100 */
18180 #define GPIO_HWCFGR0_OR_RES_9         (0x200U << GPIO_HWCFGR0_OR_RES_Pos)       /*!< 0x00000200 */
18181 #define GPIO_HWCFGR0_OR_RES_10        (0x400U << GPIO_HWCFGR0_OR_RES_Pos)       /*!< 0x00000400 */
18182 #define GPIO_HWCFGR0_OR_RES_11        (0x800U << GPIO_HWCFGR0_OR_RES_Pos)       /*!< 0x00000800 */
18183 #define GPIO_HWCFGR0_OR_RES_12        (0x1000U << GPIO_HWCFGR0_OR_RES_Pos)      /*!< 0x00001000 */
18184 #define GPIO_HWCFGR0_OR_RES_13        (0x2000U << GPIO_HWCFGR0_OR_RES_Pos)      /*!< 0x00002000 */
18185 #define GPIO_HWCFGR0_OR_RES_14        (0x4000U << GPIO_HWCFGR0_OR_RES_Pos)      /*!< 0x00004000 */
18186 #define GPIO_HWCFGR0_OR_RES_15        (0x8000U << GPIO_HWCFGR0_OR_RES_Pos)      /*!< 0x00008000 */
18187 
18188 /**********************  Bit definition for GPIO_VERR register  *****************/
18189 #define GPIO_VERR_MINREV_Pos      (0U)
18190 #define GPIO_VERR_MINREV_Msk      (0xFU << GPIO_VERR_MINREV_Pos)               /*!< 0x0000000F */
18191 #define GPIO_VERR_MINREV          GPIO_VERR_MINREV_Msk                         /*!< Minor Revision number */
18192 #define GPIO_VERR_MAJREV_Pos      (4U)
18193 #define GPIO_VERR_MAJREV_Msk      (0xFU << GPIO_VERR_MAJREV_Pos)               /*!< 0x000000F0 */
18194 #define GPIO_VERR_MAJREV          GPIO_VERR_MAJREV_Msk                         /*!< Major Revision number */
18195 
18196 /**********************  Bit definition for GPIO_IPIDR register  ****************/
18197 #define GPIO_IPIDR_IPID_Pos       (0U)
18198 #define GPIO_IPIDR_IPID_Msk       (0xFFFFFFFFU << GPIO_IPIDR_IPID_Pos)         /*!< 0xFFFFFFFF */
18199 #define GPIO_IPIDR_IPID           GPIO_IPIDR_IPID_Msk                          /*!< IP Identification */
18200 
18201 /**********************  Bit definition for GPIO_SIDR register  *****************/
18202 #define GPIO_SIDR_SID_Pos         (0U)
18203 #define GPIO_SIDR_SID_Msk         (0xFFFFFFFFU << GPIO_SIDR_SID_Pos)           /*!< 0xFFFFFFFF */
18204 #define GPIO_SIDR_SID             GPIO_SIDR_SID_Msk                            /*!< IP size identification */
18205 
18206 /******************************************************************************/
18207 /*                                                                            */
18208 /*                        HSEM HW Semaphore                                   */
18209 /*                                                                            */
18210 /******************************************************************************/
18211 /********************  Bit definition for HSEM_R register  ********************/
18212 #define HSEM_R_PROCID_Pos         (0U)
18213 #define HSEM_R_PROCID_Msk         (0xFFUL << HSEM_R_PROCID_Pos)                /*!< 0x000000FF */
18214 #define HSEM_R_PROCID             HSEM_R_PROCID_Msk                             /*!<Semaphore ProcessID */
18215 #define HSEM_R_COREID_Pos         (8U)
18216 #define HSEM_R_COREID_Msk         (0xFFUL << HSEM_R_COREID_Pos)                /*!< 0x0000FF00 */
18217 #define HSEM_R_COREID             HSEM_R_COREID_Msk                             /*!<Semaphore CoreID. */
18218 #define HSEM_R_LOCK_Pos           (31U)
18219 #define HSEM_R_LOCK_Msk           (0x1UL << HSEM_R_LOCK_Pos)                   /*!< 0x80000000 */
18220 #define HSEM_R_LOCK               HSEM_R_LOCK_Msk                               /*!<Lock indication. */
18221 
18222 /********************  Bit definition for HSEM_RLR register  ******************/
18223 #define HSEM_RLR_PROCID_Pos       (0U)
18224 #define HSEM_RLR_PROCID_Msk       (0xFFUL << HSEM_RLR_PROCID_Pos)              /*!< 0x000000FF */
18225 #define HSEM_RLR_PROCID           HSEM_RLR_PROCID_Msk                           /*!<Semaphore ProcessID */
18226 #define HSEM_RLR_COREID_Pos       (8U)
18227 #define HSEM_RLR_COREID_Msk       (0xFFUL << HSEM_RLR_COREID_Pos)              /*!< 0x0000FF00 */
18228 #define HSEM_RLR_COREID           HSEM_RLR_COREID_Msk                           /*!<Semaphore CoreID. */
18229 #define HSEM_RLR_LOCK_Pos         (31U)
18230 #define HSEM_RLR_LOCK_Msk         (0x1UL << HSEM_RLR_LOCK_Pos)                 /*!< 0x80000000 */
18231 #define HSEM_RLR_LOCK             HSEM_RLR_LOCK_Msk                             /*!<Lock indication. */
18232 
18233 /********************  Bit definition for HSEM_C1IER register  *****************/
18234 #define HSEM_C1IER_ISE0_Pos       (0U)
18235 #define HSEM_C1IER_ISE0_Msk       (0x1UL << HSEM_C1IER_ISE0_Pos)               /*!< 0x00000001 */
18236 #define HSEM_C1IER_ISE0           HSEM_C1IER_ISE0_Msk                          /*!<semaphore 0 , interrupt 0 enable bit.  */
18237 #define HSEM_C1IER_ISE1_Pos       (1U)
18238 #define HSEM_C1IER_ISE1_Msk       (0x1UL << HSEM_C1IER_ISE1_Pos)               /*!< 0x00000002 */
18239 #define HSEM_C1IER_ISE1           HSEM_C1IER_ISE1_Msk                          /*!<semaphore 1 , interrupt 0 enable bit.  */
18240 #define HSEM_C1IER_ISE2_Pos       (2U)
18241 #define HSEM_C1IER_ISE2_Msk       (0x1UL << HSEM_C1IER_ISE2_Pos)               /*!< 0x00000004 */
18242 #define HSEM_C1IER_ISE2           HSEM_C1IER_ISE2_Msk                          /*!<semaphore 2 , interrupt 0 enable bit.  */
18243 #define HSEM_C1IER_ISE3_Pos       (3U)
18244 #define HSEM_C1IER_ISE3_Msk       (0x1UL << HSEM_C1IER_ISE3_Pos)               /*!< 0x00000008 */
18245 #define HSEM_C1IER_ISE3           HSEM_C1IER_ISE3_Msk                          /*!<semaphore 3 , interrupt 0 enable bit.  */
18246 #define HSEM_C1IER_ISE4_Pos       (4U)
18247 #define HSEM_C1IER_ISE4_Msk       (0x1UL << HSEM_C1IER_ISE4_Pos)               /*!< 0x00000010 */
18248 #define HSEM_C1IER_ISE4           HSEM_C1IER_ISE4_Msk                          /*!<semaphore 4 , interrupt 0 enable bit.  */
18249 #define HSEM_C1IER_ISE5_Pos       (5U)
18250 #define HSEM_C1IER_ISE5_Msk       (0x1UL << HSEM_C1IER_ISE5_Pos)               /*!< 0x00000020 */
18251 #define HSEM_C1IER_ISE5           HSEM_C1IER_ISE5_Msk                          /*!<semaphore 5 interrupt 0 enable bit.    */
18252 #define HSEM_C1IER_ISE6_Pos       (6U)
18253 #define HSEM_C1IER_ISE6_Msk       (0x1UL << HSEM_C1IER_ISE6_Pos)               /*!< 0x00000040 */
18254 #define HSEM_C1IER_ISE6           HSEM_C1IER_ISE6_Msk                          /*!<semaphore 6 interrupt 0 enable bit.    */
18255 #define HSEM_C1IER_ISE7_Pos       (7U)
18256 #define HSEM_C1IER_ISE7_Msk       (0x1UL << HSEM_C1IER_ISE7_Pos)               /*!< 0x00000080 */
18257 #define HSEM_C1IER_ISE7           HSEM_C1IER_ISE7_Msk                          /*!<semaphore 7 interrupt 0 enable bit.    */
18258 #define HSEM_C1IER_ISE8_Pos       (8U)
18259 #define HSEM_C1IER_ISE8_Msk       (0x1UL << HSEM_C1IER_ISE8_Pos)               /*!< 0x00000100 */
18260 #define HSEM_C1IER_ISE8           HSEM_C1IER_ISE8_Msk                          /*!<semaphore 8 interrupt 0 enable bit.    */
18261 #define HSEM_C1IER_ISE9_Pos       (9U)
18262 #define HSEM_C1IER_ISE9_Msk       (0x1UL << HSEM_C1IER_ISE9_Pos)               /*!< 0x00000200 */
18263 #define HSEM_C1IER_ISE9           HSEM_C1IER_ISE9_Msk                          /*!<semaphore 9 interrupt 0 enable bit.    */
18264 #define HSEM_C1IER_ISE10_Pos      (10U)
18265 #define HSEM_C1IER_ISE10_Msk      (0x1UL << HSEM_C1IER_ISE10_Pos)              /*!< 0x00000400 */
18266 #define HSEM_C1IER_ISE10          HSEM_C1IER_ISE10_Msk                         /*!<semaphore 10 interrupt 0 enable bit.   */
18267 #define HSEM_C1IER_ISE11_Pos      (11U)
18268 #define HSEM_C1IER_ISE11_Msk      (0x1UL << HSEM_C1IER_ISE11_Pos)              /*!< 0x00000800 */
18269 #define HSEM_C1IER_ISE11          HSEM_C1IER_ISE11_Msk                         /*!<semaphore 11 interrupt 0 enable bit.   */
18270 #define HSEM_C1IER_ISE12_Pos      (12U)
18271 #define HSEM_C1IER_ISE12_Msk      (0x1UL << HSEM_C1IER_ISE12_Pos)              /*!< 0x00001000 */
18272 #define HSEM_C1IER_ISE12          HSEM_C1IER_ISE12_Msk                         /*!<semaphore 12 interrupt 0 enable bit.   */
18273 #define HSEM_C1IER_ISE13_Pos      (13U)
18274 #define HSEM_C1IER_ISE13_Msk      (0x1UL << HSEM_C1IER_ISE13_Pos)              /*!< 0x00002000 */
18275 #define HSEM_C1IER_ISE13          HSEM_C1IER_ISE13_Msk                         /*!<semaphore 13 interrupt 0 enable bit.   */
18276 #define HSEM_C1IER_ISE14_Pos      (14U)
18277 #define HSEM_C1IER_ISE14_Msk      (0x1UL << HSEM_C1IER_ISE14_Pos)              /*!< 0x00004000 */
18278 #define HSEM_C1IER_ISE14          HSEM_C1IER_ISE14_Msk                         /*!<semaphore 14 interrupt 0 enable bit.   */
18279 #define HSEM_C1IER_ISE15_Pos      (15U)
18280 #define HSEM_C1IER_ISE15_Msk      (0x1UL << HSEM_C1IER_ISE15_Pos)              /*!< 0x00008000 */
18281 #define HSEM_C1IER_ISE15          HSEM_C1IER_ISE15_Msk                         /*!<semaphore 15 interrupt 0 enable bit. */
18282 #define HSEM_C1IER_ISE16_Pos      (16U)
18283 #define HSEM_C1IER_ISE16_Msk      (0x1UL << HSEM_C1IER_ISE16_Pos)              /*!< 0x00010000 */
18284 #define HSEM_C1IER_ISE16          HSEM_C1IER_ISE16_Msk                         /*!<semaphore 16 interrupt 0 enable bit. */
18285 #define HSEM_C1IER_ISE17_Pos      (17U)
18286 #define HSEM_C1IER_ISE17_Msk      (0x1UL << HSEM_C1IER_ISE17_Pos)              /*!< 0x00020000 */
18287 #define HSEM_C1IER_ISE17          HSEM_C1IER_ISE17_Msk                         /*!<semaphore 17 interrupt 0 enable bit. */
18288 #define HSEM_C1IER_ISE18_Pos      (18U)
18289 #define HSEM_C1IER_ISE18_Msk      (0x1UL << HSEM_C1IER_ISE18_Pos)              /*!< 0x00040000 */
18290 #define HSEM_C1IER_ISE18          HSEM_C1IER_ISE18_Msk                         /*!<semaphore 18 interrupt 0 enable bit. */
18291 #define HSEM_C1IER_ISE19_Pos      (19U)
18292 #define HSEM_C1IER_ISE19_Msk      (0x1UL << HSEM_C1IER_ISE19_Pos)              /*!< 0x00080000 */
18293 #define HSEM_C1IER_ISE19          HSEM_C1IER_ISE19_Msk                         /*!<semaphore 19 interrupt 0 enable bit. */
18294 #define HSEM_C1IER_ISE20_Pos      (20U)
18295 #define HSEM_C1IER_ISE20_Msk      (0x1UL << HSEM_C1IER_ISE20_Pos)              /*!< 0x00100000 */
18296 #define HSEM_C1IER_ISE20          HSEM_C1IER_ISE20_Msk                         /*!<semaphore 20 interrupt 0 enable bit. */
18297 #define HSEM_C1IER_ISE21_Pos      (21U)
18298 #define HSEM_C1IER_ISE21_Msk      (0x1UL << HSEM_C1IER_ISE21_Pos)              /*!< 0x00200000 */
18299 #define HSEM_C1IER_ISE21          HSEM_C1IER_ISE21_Msk                         /*!<semaphore 21 interrupt 0 enable bit. */
18300 #define HSEM_C1IER_ISE22_Pos      (22U)
18301 #define HSEM_C1IER_ISE22_Msk      (0x1UL << HSEM_C1IER_ISE22_Pos)              /*!< 0x00400000 */
18302 #define HSEM_C1IER_ISE22          HSEM_C1IER_ISE22_Msk                         /*!<semaphore 22 interrupt 0 enable bit. */
18303 #define HSEM_C1IER_ISE23_Pos      (23U)
18304 #define HSEM_C1IER_ISE23_Msk      (0x1UL << HSEM_C1IER_ISE23_Pos)              /*!< 0x00800000 */
18305 #define HSEM_C1IER_ISE23          HSEM_C1IER_ISE23_Msk                         /*!<semaphore 23 interrupt 0 enable bit. */
18306 #define HSEM_C1IER_ISE24_Pos      (24U)
18307 #define HSEM_C1IER_ISE24_Msk      (0x1UL << HSEM_C1IER_ISE24_Pos)              /*!< 0x01000000 */
18308 #define HSEM_C1IER_ISE24          HSEM_C1IER_ISE24_Msk                         /*!<semaphore 24 interrupt 0 enable bit. */
18309 #define HSEM_C1IER_ISE25_Pos      (25U)
18310 #define HSEM_C1IER_ISE25_Msk      (0x1UL << HSEM_C1IER_ISE25_Pos)              /*!< 0x02000000 */
18311 #define HSEM_C1IER_ISE25          HSEM_C1IER_ISE25_Msk                         /*!<semaphore 25 interrupt 0 enable bit. */
18312 #define HSEM_C1IER_ISE26_Pos      (26U)
18313 #define HSEM_C1IER_ISE26_Msk      (0x1UL << HSEM_C1IER_ISE26_Pos)              /*!< 0x04000000 */
18314 #define HSEM_C1IER_ISE26          HSEM_C1IER_ISE26_Msk                         /*!<semaphore 26 interrupt 0 enable bit. */
18315 #define HSEM_C1IER_ISE27_Pos      (27U)
18316 #define HSEM_C1IER_ISE27_Msk      (0x1UL << HSEM_C1IER_ISE27_Pos)              /*!< 0x08000000 */
18317 #define HSEM_C1IER_ISE27          HSEM_C1IER_ISE27_Msk                         /*!<semaphore 27 interrupt 0 enable bit. */
18318 #define HSEM_C1IER_ISE28_Pos      (28U)
18319 #define HSEM_C1IER_ISE28_Msk      (0x1UL << HSEM_C1IER_ISE28_Pos)              /*!< 0x10000000 */
18320 #define HSEM_C1IER_ISE28          HSEM_C1IER_ISE28_Msk                         /*!<semaphore 28 interrupt 0 enable bit. */
18321 #define HSEM_C1IER_ISE29_Pos      (29U)
18322 #define HSEM_C1IER_ISE29_Msk      (0x1UL << HSEM_C1IER_ISE29_Pos)              /*!< 0x20000000 */
18323 #define HSEM_C1IER_ISE29          HSEM_C1IER_ISE29_Msk                         /*!<semaphore 29 interrupt 0 enable bit. */
18324 #define HSEM_C1IER_ISE30_Pos      (30U)
18325 #define HSEM_C1IER_ISE30_Msk      (0x1UL << HSEM_C1IER_ISE30_Pos)              /*!< 0x40000000 */
18326 #define HSEM_C1IER_ISE30          HSEM_C1IER_ISE30_Msk                         /*!<semaphore 30 interrupt 0 enable bit. */
18327 #define HSEM_C1IER_ISE31_Pos      (31U)
18328 #define HSEM_C1IER_ISE31_Msk      (0x1UL << HSEM_C1IER_ISE31_Pos)              /*!< 0x80000000 */
18329 #define HSEM_C1IER_ISE31          HSEM_C1IER_ISE31_Msk                         /*!<semaphore 31 interrupt 0 enable bit. */
18330 
18331 /********************  Bit definition for HSEM_C1ICR register  *****************/
18332 #define HSEM_C1ICR_ISC0_Pos       (0U)
18333 #define HSEM_C1ICR_ISC0_Msk       (0x1UL << HSEM_C1ICR_ISC0_Pos)               /*!< 0x00000001 */
18334 #define HSEM_C1ICR_ISC0           HSEM_C1ICR_ISC0_Msk                          /*!<semaphore 0 , interrupt 0 clear bit.  */
18335 #define HSEM_C1ICR_ISC1_Pos       (1U)
18336 #define HSEM_C1ICR_ISC1_Msk       (0x1UL << HSEM_C1ICR_ISC1_Pos)               /*!< 0x00000002 */
18337 #define HSEM_C1ICR_ISC1           HSEM_C1ICR_ISC1_Msk                          /*!<semaphore 1 , interrupt 0 clear bit.  */
18338 #define HSEM_C1ICR_ISC2_Pos       (2U)
18339 #define HSEM_C1ICR_ISC2_Msk       (0x1UL << HSEM_C1ICR_ISC2_Pos)               /*!< 0x00000004 */
18340 #define HSEM_C1ICR_ISC2           HSEM_C1ICR_ISC2_Msk                          /*!<semaphore 2 , interrupt 0 clear bit.  */
18341 #define HSEM_C1ICR_ISC3_Pos       (3U)
18342 #define HSEM_C1ICR_ISC3_Msk       (0x1UL << HSEM_C1ICR_ISC3_Pos)               /*!< 0x00000008 */
18343 #define HSEM_C1ICR_ISC3           HSEM_C1ICR_ISC3_Msk                          /*!<semaphore 3 , interrupt 0 clear bit.  */
18344 #define HSEM_C1ICR_ISC4_Pos       (4U)
18345 #define HSEM_C1ICR_ISC4_Msk       (0x1UL << HSEM_C1ICR_ISC4_Pos)               /*!< 0x00000010 */
18346 #define HSEM_C1ICR_ISC4           HSEM_C1ICR_ISC4_Msk                          /*!<semaphore 4 , interrupt 0 clear bit.  */
18347 #define HSEM_C1ICR_ISC5_Pos       (5U)
18348 #define HSEM_C1ICR_ISC5_Msk       (0x1UL << HSEM_C1ICR_ISC5_Pos)               /*!< 0x00000020 */
18349 #define HSEM_C1ICR_ISC5           HSEM_C1ICR_ISC5_Msk                          /*!<semaphore 5 interrupt 0 clear bit.  */
18350 #define HSEM_C1ICR_ISC6_Pos       (6U)
18351 #define HSEM_C1ICR_ISC6_Msk       (0x1UL << HSEM_C1ICR_ISC6_Pos)               /*!< 0x00000040 */
18352 #define HSEM_C1ICR_ISC6           HSEM_C1ICR_ISC6_Msk                          /*!<semaphore 6 interrupt 0 clear bit.  */
18353 #define HSEM_C1ICR_ISC7_Pos       (7U)
18354 #define HSEM_C1ICR_ISC7_Msk       (0x1UL << HSEM_C1ICR_ISC7_Pos)               /*!< 0x00000080 */
18355 #define HSEM_C1ICR_ISC7           HSEM_C1ICR_ISC7_Msk                          /*!<semaphore 7 interrupt 0 clear bit.  */
18356 #define HSEM_C1ICR_ISC8_Pos       (8U)
18357 #define HSEM_C1ICR_ISC8_Msk       (0x1UL << HSEM_C1ICR_ISC8_Pos)               /*!< 0x00000100 */
18358 #define HSEM_C1ICR_ISC8           HSEM_C1ICR_ISC8_Msk                          /*!<semaphore 8 interrupt 0 clear bit.  */
18359 #define HSEM_C1ICR_ISC9_Pos       (9U)
18360 #define HSEM_C1ICR_ISC9_Msk       (0x1UL << HSEM_C1ICR_ISC9_Pos)               /*!< 0x00000200 */
18361 #define HSEM_C1ICR_ISC9           HSEM_C1ICR_ISC9_Msk                          /*!<semaphore 9 interrupt 0 clear bit.  */
18362 #define HSEM_C1ICR_ISC10_Pos      (10U)
18363 #define HSEM_C1ICR_ISC10_Msk      (0x1UL << HSEM_C1ICR_ISC10_Pos)              /*!< 0x00000400 */
18364 #define HSEM_C1ICR_ISC10          HSEM_C1ICR_ISC10_Msk                         /*!<semaphore 10 interrupt 0 clear bit. */
18365 #define HSEM_C1ICR_ISC11_Pos      (11U)
18366 #define HSEM_C1ICR_ISC11_Msk      (0x1UL << HSEM_C1ICR_ISC11_Pos)              /*!< 0x00000800 */
18367 #define HSEM_C1ICR_ISC11          HSEM_C1ICR_ISC11_Msk                         /*!<semaphore 11 interrupt 0 clear bit. */
18368 #define HSEM_C1ICR_ISC12_Pos      (12U)
18369 #define HSEM_C1ICR_ISC12_Msk      (0x1UL << HSEM_C1ICR_ISC12_Pos)              /*!< 0x00001000 */
18370 #define HSEM_C1ICR_ISC12          HSEM_C1ICR_ISC12_Msk                         /*!<semaphore 12 interrupt 0 clear bit. */
18371 #define HSEM_C1ICR_ISC13_Pos      (13U)
18372 #define HSEM_C1ICR_ISC13_Msk      (0x1UL << HSEM_C1ICR_ISC13_Pos)              /*!< 0x00002000 */
18373 #define HSEM_C1ICR_ISC13          HSEM_C1ICR_ISC13_Msk                         /*!<semaphore 13 interrupt 0 clear bit. */
18374 #define HSEM_C1ICR_ISC14_Pos      (14U)
18375 #define HSEM_C1ICR_ISC14_Msk      (0x1UL << HSEM_C1ICR_ISC14_Pos)              /*!< 0x00004000 */
18376 #define HSEM_C1ICR_ISC14          HSEM_C1ICR_ISC14_Msk                         /*!<semaphore 14 interrupt 0 clear bit. */
18377 #define HSEM_C1ICR_ISC15_Pos      (15U)
18378 #define HSEM_C1ICR_ISC15_Msk      (0x1UL << HSEM_C1ICR_ISC15_Pos)              /*!< 0x00008000 */
18379 #define HSEM_C1ICR_ISC15          HSEM_C1ICR_ISC15_Msk                         /*!<semaphore 15 interrupt 0 clear bit. */
18380 #define HSEM_C1ICR_ISC16_Pos      (16U)
18381 #define HSEM_C1ICR_ISC16_Msk      (0x1UL << HSEM_C1ICR_ISC16_Pos)              /*!< 0x00010000 */
18382 #define HSEM_C1ICR_ISC16          HSEM_C1ICR_ISC16_Msk                         /*!<semaphore 16 interrupt 0 clear bit. */
18383 #define HSEM_C1ICR_ISC17_Pos      (17U)
18384 #define HSEM_C1ICR_ISC17_Msk      (0x1UL << HSEM_C1ICR_ISC17_Pos)              /*!< 0x00020000 */
18385 #define HSEM_C1ICR_ISC17          HSEM_C1ICR_ISC17_Msk                         /*!<semaphore 17 interrupt 0 clear bit. */
18386 #define HSEM_C1ICR_ISC18_Pos      (18U)
18387 #define HSEM_C1ICR_ISC18_Msk      (0x1UL << HSEM_C1ICR_ISC18_Pos)              /*!< 0x00040000 */
18388 #define HSEM_C1ICR_ISC18          HSEM_C1ICR_ISC18_Msk                         /*!<semaphore 18 interrupt 0 clear bit. */
18389 #define HSEM_C1ICR_ISC19_Pos      (19U)
18390 #define HSEM_C1ICR_ISC19_Msk      (0x1UL << HSEM_C1ICR_ISC19_Pos)              /*!< 0x00080000 */
18391 #define HSEM_C1ICR_ISC19          HSEM_C1ICR_ISC19_Msk                         /*!<semaphore 19 interrupt 0 clear bit. */
18392 #define HSEM_C1ICR_ISC20_Pos      (20U)
18393 #define HSEM_C1ICR_ISC20_Msk      (0x1UL << HSEM_C1ICR_ISC20_Pos)              /*!< 0x00100000 */
18394 #define HSEM_C1ICR_ISC20          HSEM_C1ICR_ISC20_Msk                         /*!<semaphore 20 interrupt 0 clear bit. */
18395 #define HSEM_C1ICR_ISC21_Pos      (21U)
18396 #define HSEM_C1ICR_ISC21_Msk      (0x1UL << HSEM_C1ICR_ISC21_Pos)              /*!< 0x00200000 */
18397 #define HSEM_C1ICR_ISC21          HSEM_C1ICR_ISC21_Msk                         /*!<semaphore 21 interrupt 0 clear bit. */
18398 #define HSEM_C1ICR_ISC22_Pos      (22U)
18399 #define HSEM_C1ICR_ISC22_Msk      (0x1UL << HSEM_C1ICR_ISC22_Pos)              /*!< 0x00400000 */
18400 #define HSEM_C1ICR_ISC22          HSEM_C1ICR_ISC22_Msk                         /*!<semaphore 22 interrupt 0 clear bit. */
18401 #define HSEM_C1ICR_ISC23_Pos      (23U)
18402 #define HSEM_C1ICR_ISC23_Msk      (0x1UL << HSEM_C1ICR_ISC23_Pos)              /*!< 0x00800000 */
18403 #define HSEM_C1ICR_ISC23          HSEM_C1ICR_ISC23_Msk                         /*!<semaphore 23 interrupt 0 clear bit. */
18404 #define HSEM_C1ICR_ISC24_Pos      (24U)
18405 #define HSEM_C1ICR_ISC24_Msk      (0x1UL << HSEM_C1ICR_ISC24_Pos)              /*!< 0x01000000 */
18406 #define HSEM_C1ICR_ISC24          HSEM_C1ICR_ISC24_Msk                         /*!<semaphore 24 interrupt 0 clear bit. */
18407 #define HSEM_C1ICR_ISC25_Pos      (25U)
18408 #define HSEM_C1ICR_ISC25_Msk      (0x1UL << HSEM_C1ICR_ISC25_Pos)              /*!< 0x02000000 */
18409 #define HSEM_C1ICR_ISC25          HSEM_C1ICR_ISC25_Msk                         /*!<semaphore 25 interrupt 0 clear bit. */
18410 #define HSEM_C1ICR_ISC26_Pos      (26U)
18411 #define HSEM_C1ICR_ISC26_Msk      (0x1UL << HSEM_C1ICR_ISC26_Pos)              /*!< 0x04000000 */
18412 #define HSEM_C1ICR_ISC26          HSEM_C1ICR_ISC26_Msk                         /*!<semaphore 26 interrupt 0 clear bit. */
18413 #define HSEM_C1ICR_ISC27_Pos      (27U)
18414 #define HSEM_C1ICR_ISC27_Msk      (0x1UL << HSEM_C1ICR_ISC27_Pos)              /*!< 0x08000000 */
18415 #define HSEM_C1ICR_ISC27          HSEM_C1ICR_ISC27_Msk                         /*!<semaphore 27 interrupt 0 clear bit. */
18416 #define HSEM_C1ICR_ISC28_Pos      (28U)
18417 #define HSEM_C1ICR_ISC28_Msk      (0x1UL << HSEM_C1ICR_ISC28_Pos)              /*!< 0x10000000 */
18418 #define HSEM_C1ICR_ISC28          HSEM_C1ICR_ISC28_Msk                         /*!<semaphore 28 interrupt 0 clear bit. */
18419 #define HSEM_C1ICR_ISC29_Pos      (29U)
18420 #define HSEM_C1ICR_ISC29_Msk      (0x1UL << HSEM_C1ICR_ISC29_Pos)              /*!< 0x20000000 */
18421 #define HSEM_C1ICR_ISC29          HSEM_C1ICR_ISC29_Msk                         /*!<semaphore 29 interrupt 0 clear bit. */
18422 #define HSEM_C1ICR_ISC30_Pos      (30U)
18423 #define HSEM_C1ICR_ISC30_Msk      (0x1UL << HSEM_C1ICR_ISC30_Pos)              /*!< 0x40000000 */
18424 #define HSEM_C1ICR_ISC30          HSEM_C1ICR_ISC30_Msk                         /*!<semaphore 30 interrupt 0 clear bit. */
18425 #define HSEM_C1ICR_ISC31_Pos      (31U)
18426 #define HSEM_C1ICR_ISC31_Msk      (0x1UL << HSEM_C1ICR_ISC31_Pos)              /*!< 0x80000000 */
18427 #define HSEM_C1ICR_ISC31          HSEM_C1ICR_ISC31_Msk                         /*!<semaphore 31 interrupt 0 clear bit. */
18428 
18429 /********************  Bit definition for HSEM_C1ISR register  *****************/
18430 #define HSEM_C1ISR_ISF0_Pos       (0U)
18431 #define HSEM_C1ISR_ISF0_Msk       (0x1UL << HSEM_C1ISR_ISF0_Pos)               /*!< 0x00000001 */
18432 #define HSEM_C1ISR_ISF0           HSEM_C1ISR_ISF0_Msk                          /*!<semaphore 0 interrupt 0 status bit.  */
18433 #define HSEM_C1ISR_ISF1_Pos       (1U)
18434 #define HSEM_C1ISR_ISF1_Msk       (0x1UL << HSEM_C1ISR_ISF1_Pos)               /*!< 0x00000002 */
18435 #define HSEM_C1ISR_ISF1           HSEM_C1ISR_ISF1_Msk                          /*!<semaphore 1 interrupt 0 status bit.  */
18436 #define HSEM_C1ISR_ISF2_Pos       (2U)
18437 #define HSEM_C1ISR_ISF2_Msk       (0x1UL << HSEM_C1ISR_ISF2_Pos)               /*!< 0x00000004 */
18438 #define HSEM_C1ISR_ISF2           HSEM_C1ISR_ISF2_Msk                          /*!<semaphore 2 interrupt 0 status bit.  */
18439 #define HSEM_C1ISR_ISF3_Pos       (3U)
18440 #define HSEM_C1ISR_ISF3_Msk       (0x1UL << HSEM_C1ISR_ISF3_Pos)               /*!< 0x00000008 */
18441 #define HSEM_C1ISR_ISF3           HSEM_C1ISR_ISF3_Msk                          /*!<semaphore 3 interrupt 0 status bit.  */
18442 #define HSEM_C1ISR_ISF4_Pos       (4U)
18443 #define HSEM_C1ISR_ISF4_Msk       (0x1UL << HSEM_C1ISR_ISF4_Pos)               /*!< 0x00000010 */
18444 #define HSEM_C1ISR_ISF4           HSEM_C1ISR_ISF4_Msk                          /*!<semaphore 4 interrupt 0 status bit.  */
18445 #define HSEM_C1ISR_ISF5_Pos       (5U)
18446 #define HSEM_C1ISR_ISF5_Msk       (0x1UL << HSEM_C1ISR_ISF5_Pos)               /*!< 0x00000020 */
18447 #define HSEM_C1ISR_ISF5           HSEM_C1ISR_ISF5_Msk                          /*!<semaphore 5 interrupt 0 status bit.  */
18448 #define HSEM_C1ISR_ISF6_Pos       (6U)
18449 #define HSEM_C1ISR_ISF6_Msk       (0x1UL << HSEM_C1ISR_ISF6_Pos)               /*!< 0x00000040 */
18450 #define HSEM_C1ISR_ISF6           HSEM_C1ISR_ISF6_Msk                          /*!<semaphore 6 interrupt 0 status bit.  */
18451 #define HSEM_C1ISR_ISF7_Pos       (7U)
18452 #define HSEM_C1ISR_ISF7_Msk       (0x1UL << HSEM_C1ISR_ISF7_Pos)               /*!< 0x00000080 */
18453 #define HSEM_C1ISR_ISF7           HSEM_C1ISR_ISF7_Msk                          /*!<semaphore 7 interrupt 0 status bit.  */
18454 #define HSEM_C1ISR_ISF8_Pos       (8U)
18455 #define HSEM_C1ISR_ISF8_Msk       (0x1UL << HSEM_C1ISR_ISF8_Pos)               /*!< 0x00000100 */
18456 #define HSEM_C1ISR_ISF8           HSEM_C1ISR_ISF8_Msk                          /*!<semaphore 8 interrupt 0 status bit.  */
18457 #define HSEM_C1ISR_ISF9_Pos       (9U)
18458 #define HSEM_C1ISR_ISF9_Msk       (0x1UL << HSEM_C1ISR_ISF9_Pos)               /*!< 0x00000200 */
18459 #define HSEM_C1ISR_ISF9           HSEM_C1ISR_ISF9_Msk                          /*!<semaphore 9 interrupt 0 status bit.  */
18460 #define HSEM_C1ISR_ISF10_Pos      (10U)
18461 #define HSEM_C1ISR_ISF10_Msk      (0x1UL << HSEM_C1ISR_ISF10_Pos)              /*!< 0x00000400 */
18462 #define HSEM_C1ISR_ISF10          HSEM_C1ISR_ISF10_Msk                         /*!<semaphore 10 interrupt 0 status bit. */
18463 #define HSEM_C1ISR_ISF11_Pos      (11U)
18464 #define HSEM_C1ISR_ISF11_Msk      (0x1UL << HSEM_C1ISR_ISF11_Pos)              /*!< 0x00000800 */
18465 #define HSEM_C1ISR_ISF11          HSEM_C1ISR_ISF11_Msk                         /*!<semaphore 11 interrupt 0 status bit. */
18466 #define HSEM_C1ISR_ISF12_Pos      (12U)
18467 #define HSEM_C1ISR_ISF12_Msk      (0x1UL << HSEM_C1ISR_ISF12_Pos)              /*!< 0x00001000 */
18468 #define HSEM_C1ISR_ISF12          HSEM_C1ISR_ISF12_Msk                         /*!<semaphore 12 interrupt 0 status bit. */
18469 #define HSEM_C1ISR_ISF13_Pos      (13U)
18470 #define HSEM_C1ISR_ISF13_Msk      (0x1UL << HSEM_C1ISR_ISF13_Pos)              /*!< 0x00002000 */
18471 #define HSEM_C1ISR_ISF13          HSEM_C1ISR_ISF13_Msk                         /*!<semaphore 13 interrupt 0 status bit. */
18472 #define HSEM_C1ISR_ISF14_Pos      (14U)
18473 #define HSEM_C1ISR_ISF14_Msk      (0x1UL << HSEM_C1ISR_ISF14_Pos)              /*!< 0x00004000 */
18474 #define HSEM_C1ISR_ISF14          HSEM_C1ISR_ISF14_Msk                         /*!<semaphore 14 interrupt 0 status bit. */
18475 #define HSEM_C1ISR_ISF15_Pos      (15U)
18476 #define HSEM_C1ISR_ISF15_Msk      (0x1UL << HSEM_C1ISR_ISF15_Pos)              /*!< 0x00008000 */
18477 #define HSEM_C1ISR_ISF15          HSEM_C1ISR_ISF15_Msk                         /*!<semaphore 15 interrupt 0 status bit. */
18478 #define HSEM_C1ISR_ISF16_Pos      (16U)
18479 #define HSEM_C1ISR_ISF16_Msk      (0x1UL << HSEM_C1ISR_ISF16_Pos)              /*!< 0x00010000 */
18480 #define HSEM_C1ISR_ISF16          HSEM_C1ISR_ISF16_Msk                         /*!<semaphore 16 interrupt 0 status bit. */
18481 #define HSEM_C1ISR_ISF17_Pos      (17U)
18482 #define HSEM_C1ISR_ISF17_Msk      (0x1UL << HSEM_C1ISR_ISF17_Pos)              /*!< 0x00020000 */
18483 #define HSEM_C1ISR_ISF17          HSEM_C1ISR_ISF17_Msk                         /*!<semaphore 17 interrupt 0 status bit. */
18484 #define HSEM_C1ISR_ISF18_Pos      (18U)
18485 #define HSEM_C1ISR_ISF18_Msk      (0x1UL << HSEM_C1ISR_ISF18_Pos)              /*!< 0x00040000 */
18486 #define HSEM_C1ISR_ISF18          HSEM_C1ISR_ISF18_Msk                         /*!<semaphore 18 interrupt 0 status bit. */
18487 #define HSEM_C1ISR_ISF19_Pos      (19U)
18488 #define HSEM_C1ISR_ISF19_Msk      (0x1UL << HSEM_C1ISR_ISF19_Pos)              /*!< 0x00080000 */
18489 #define HSEM_C1ISR_ISF19          HSEM_C1ISR_ISF19_Msk                         /*!<semaphore 19 interrupt 0 status bit. */
18490 #define HSEM_C1ISR_ISF20_Pos      (20U)
18491 #define HSEM_C1ISR_ISF20_Msk      (0x1UL << HSEM_C1ISR_ISF20_Pos)              /*!< 0x00100000 */
18492 #define HSEM_C1ISR_ISF20          HSEM_C1ISR_ISF20_Msk                         /*!<semaphore 20 interrupt 0 status bit. */
18493 #define HSEM_C1ISR_ISF21_Pos      (21U)
18494 #define HSEM_C1ISR_ISF21_Msk      (0x1UL << HSEM_C1ISR_ISF21_Pos)              /*!< 0x00200000 */
18495 #define HSEM_C1ISR_ISF21          HSEM_C1ISR_ISF21_Msk                         /*!<semaphore 21 interrupt 0 status bit. */
18496 #define HSEM_C1ISR_ISF22_Pos      (22U)
18497 #define HSEM_C1ISR_ISF22_Msk      (0x1UL << HSEM_C1ISR_ISF22_Pos)              /*!< 0x00400000 */
18498 #define HSEM_C1ISR_ISF22          HSEM_C1ISR_ISF22_Msk                         /*!<semaphore 22 interrupt 0 status bit. */
18499 #define HSEM_C1ISR_ISF23_Pos      (23U)
18500 #define HSEM_C1ISR_ISF23_Msk      (0x1UL << HSEM_C1ISR_ISF23_Pos)              /*!< 0x00800000 */
18501 #define HSEM_C1ISR_ISF23          HSEM_C1ISR_ISF23_Msk                         /*!<semaphore 23 interrupt 0 status bit. */
18502 #define HSEM_C1ISR_ISF24_Pos      (24U)
18503 #define HSEM_C1ISR_ISF24_Msk      (0x1UL << HSEM_C1ISR_ISF24_Pos)              /*!< 0x01000000 */
18504 #define HSEM_C1ISR_ISF24          HSEM_C1ISR_ISF24_Msk                         /*!<semaphore 24 interrupt 0 status bit. */
18505 #define HSEM_C1ISR_ISF25_Pos      (25U)
18506 #define HSEM_C1ISR_ISF25_Msk      (0x1UL << HSEM_C1ISR_ISF25_Pos)              /*!< 0x02000000 */
18507 #define HSEM_C1ISR_ISF25          HSEM_C1ISR_ISF25_Msk                         /*!<semaphore 25 interrupt 0 status bit. */
18508 #define HSEM_C1ISR_ISF26_Pos      (26U)
18509 #define HSEM_C1ISR_ISF26_Msk      (0x1UL << HSEM_C1ISR_ISF26_Pos)              /*!< 0x04000000 */
18510 #define HSEM_C1ISR_ISF26          HSEM_C1ISR_ISF26_Msk                         /*!<semaphore 26 interrupt 0 status bit. */
18511 #define HSEM_C1ISR_ISF27_Pos      (27U)
18512 #define HSEM_C1ISR_ISF27_Msk      (0x1UL << HSEM_C1ISR_ISF27_Pos)              /*!< 0x08000000 */
18513 #define HSEM_C1ISR_ISF27          HSEM_C1ISR_ISF27_Msk                         /*!<semaphore 27 interrupt 0 status bit. */
18514 #define HSEM_C1ISR_ISF28_Pos      (28U)
18515 #define HSEM_C1ISR_ISF28_Msk      (0x1UL << HSEM_C1ISR_ISF28_Pos)              /*!< 0x10000000 */
18516 #define HSEM_C1ISR_ISF28          HSEM_C1ISR_ISF28_Msk                         /*!<semaphore 28 interrupt 0 status bit. */
18517 #define HSEM_C1ISR_ISF29_Pos      (29U)
18518 #define HSEM_C1ISR_ISF29_Msk      (0x1UL << HSEM_C1ISR_ISF29_Pos)              /*!< 0x20000000 */
18519 #define HSEM_C1ISR_ISF29          HSEM_C1ISR_ISF29_Msk                         /*!<semaphore 29 interrupt 0 status bit. */
18520 #define HSEM_C1ISR_ISF30_Pos      (30U)
18521 #define HSEM_C1ISR_ISF30_Msk      (0x1UL << HSEM_C1ISR_ISF30_Pos)              /*!< 0x40000000 */
18522 #define HSEM_C1ISR_ISF30          HSEM_C1ISR_ISF30_Msk                         /*!<semaphore 30 interrupt 0 status bit. */
18523 #define HSEM_C1ISR_ISF31_Pos      (31U)
18524 #define HSEM_C1ISR_ISF31_Msk      (0x1UL << HSEM_C1ISR_ISF31_Pos)              /*!< 0x80000000 */
18525 #define HSEM_C1ISR_ISF31          HSEM_C1ISR_ISF31_Msk                         /*!<semaphore 31 interrupt 0 status bit. */
18526 
18527 /********************  Bit definition for HSEM_C1MISR register  *****************/
18528 #define HSEM_C1MISR_MISF0_Pos     (0U)
18529 #define HSEM_C1MISR_MISF0_Msk     (0x1UL << HSEM_C1MISR_MISF0_Pos)             /*!< 0x00000001 */
18530 #define HSEM_C1MISR_MISF0         HSEM_C1MISR_MISF0_Msk                        /*!<semaphore 0 interrupt 0 masked status bit.  */
18531 #define HSEM_C1MISR_MISF1_Pos     (1U)
18532 #define HSEM_C1MISR_MISF1_Msk     (0x1UL << HSEM_C1MISR_MISF1_Pos)             /*!< 0x00000002 */
18533 #define HSEM_C1MISR_MISF1         HSEM_C1MISR_MISF1_Msk                        /*!<semaphore 1 interrupt 0 masked status bit.  */
18534 #define HSEM_C1MISR_MISF2_Pos     (2U)
18535 #define HSEM_C1MISR_MISF2_Msk     (0x1UL << HSEM_C1MISR_MISF2_Pos)             /*!< 0x00000004 */
18536 #define HSEM_C1MISR_MISF2         HSEM_C1MISR_MISF2_Msk                        /*!<semaphore 2 interrupt 0 masked status bit.  */
18537 #define HSEM_C1MISR_MISF3_Pos     (3U)
18538 #define HSEM_C1MISR_MISF3_Msk     (0x1UL << HSEM_C1MISR_MISF3_Pos)             /*!< 0x00000008 */
18539 #define HSEM_C1MISR_MISF3         HSEM_C1MISR_MISF3_Msk                        /*!<semaphore 3 interrupt 0 masked status bit.  */
18540 #define HSEM_C1MISR_MISF4_Pos     (4U)
18541 #define HSEM_C1MISR_MISF4_Msk     (0x1UL << HSEM_C1MISR_MISF4_Pos)             /*!< 0x00000010 */
18542 #define HSEM_C1MISR_MISF4         HSEM_C1MISR_MISF4_Msk                        /*!<semaphore 4 interrupt 0 masked status bit.  */
18543 #define HSEM_C1MISR_MISF5_Pos     (5U)
18544 #define HSEM_C1MISR_MISF5_Msk     (0x1UL << HSEM_C1MISR_MISF5_Pos)             /*!< 0x00000020 */
18545 #define HSEM_C1MISR_MISF5         HSEM_C1MISR_MISF5_Msk                        /*!<semaphore 5 interrupt 0 masked status bit.  */
18546 #define HSEM_C1MISR_MISF6_Pos     (6U)
18547 #define HSEM_C1MISR_MISF6_Msk     (0x1UL << HSEM_C1MISR_MISF6_Pos)             /*!< 0x00000040 */
18548 #define HSEM_C1MISR_MISF6         HSEM_C1MISR_MISF6_Msk                        /*!<semaphore 6 interrupt 0 masked status bit.  */
18549 #define HSEM_C1MISR_MISF7_Pos     (7U)
18550 #define HSEM_C1MISR_MISF7_Msk     (0x1UL << HSEM_C1MISR_MISF7_Pos)             /*!< 0x00000080 */
18551 #define HSEM_C1MISR_MISF7         HSEM_C1MISR_MISF7_Msk                        /*!<semaphore 7 interrupt 0 masked status bit.  */
18552 #define HSEM_C1MISR_MISF8_Pos     (8U)
18553 #define HSEM_C1MISR_MISF8_Msk     (0x1UL << HSEM_C1MISR_MISF8_Pos)             /*!< 0x00000100 */
18554 #define HSEM_C1MISR_MISF8         HSEM_C1MISR_MISF8_Msk                        /*!<semaphore 8 interrupt 0 masked status bit.  */
18555 #define HSEM_C1MISR_MISF9_Pos     (9U)
18556 #define HSEM_C1MISR_MISF9_Msk     (0x1UL << HSEM_C1MISR_MISF9_Pos)             /*!< 0x00000200 */
18557 #define HSEM_C1MISR_MISF9         HSEM_C1MISR_MISF9_Msk                        /*!<semaphore 9 interrupt 0 masked status bit.  */
18558 #define HSEM_C1MISR_MISF10_Pos    (10U)
18559 #define HSEM_C1MISR_MISF10_Msk    (0x1UL << HSEM_C1MISR_MISF10_Pos)            /*!< 0x00000400 */
18560 #define HSEM_C1MISR_MISF10        HSEM_C1MISR_MISF10_Msk                       /*!<semaphore 10 interrupt 0 masked status bit. */
18561 #define HSEM_C1MISR_MISF11_Pos    (11U)
18562 #define HSEM_C1MISR_MISF11_Msk    (0x1UL << HSEM_C1MISR_MISF11_Pos)            /*!< 0x00000800 */
18563 #define HSEM_C1MISR_MISF11        HSEM_C1MISR_MISF11_Msk                       /*!<semaphore 11 interrupt 0 masked status bit. */
18564 #define HSEM_C1MISR_MISF12_Pos    (12U)
18565 #define HSEM_C1MISR_MISF12_Msk    (0x1UL << HSEM_C1MISR_MISF12_Pos)            /*!< 0x00001000 */
18566 #define HSEM_C1MISR_MISF12        HSEM_C1MISR_MISF12_Msk                       /*!<semaphore 12 interrupt 0 masked status bit. */
18567 #define HSEM_C1MISR_MISF13_Pos    (13U)
18568 #define HSEM_C1MISR_MISF13_Msk    (0x1UL << HSEM_C1MISR_MISF13_Pos)            /*!< 0x00002000 */
18569 #define HSEM_C1MISR_MISF13        HSEM_C1MISR_MISF13_Msk                       /*!<semaphore 13 interrupt 0 masked status bit. */
18570 #define HSEM_C1MISR_MISF14_Pos    (14U)
18571 #define HSEM_C1MISR_MISF14_Msk    (0x1UL << HSEM_C1MISR_MISF14_Pos)            /*!< 0x00004000 */
18572 #define HSEM_C1MISR_MISF14        HSEM_C1MISR_MISF14_Msk                       /*!<semaphore 14 interrupt 0 masked status bit. */
18573 #define HSEM_C1MISR_MISF15_Pos    (15U)
18574 #define HSEM_C1MISR_MISF15_Msk    (0x1UL << HSEM_C1MISR_MISF15_Pos)            /*!< 0x00008000 */
18575 #define HSEM_C1MISR_MISF15        HSEM_C1MISR_MISF15_Msk                       /*!<semaphore 15 interrupt 0 masked status bit. */
18576 #define HSEM_C1MISR_MISF16_Pos    (16U)
18577 #define HSEM_C1MISR_MISF16_Msk    (0x1UL << HSEM_C1MISR_MISF16_Pos)            /*!< 0x00010000 */
18578 #define HSEM_C1MISR_MISF16        HSEM_C1MISR_MISF16_Msk                       /*!<semaphore 16 interrupt 0 masked status bit. */
18579 #define HSEM_C1MISR_MISF17_Pos    (17U)
18580 #define HSEM_C1MISR_MISF17_Msk    (0x1UL << HSEM_C1MISR_MISF17_Pos)            /*!< 0x00020000 */
18581 #define HSEM_C1MISR_MISF17        HSEM_C1MISR_MISF17_Msk                       /*!<semaphore 17 interrupt 0 masked status bit. */
18582 #define HSEM_C1MISR_MISF18_Pos    (18U)
18583 #define HSEM_C1MISR_MISF18_Msk    (0x1UL << HSEM_C1MISR_MISF18_Pos)            /*!< 0x00040000 */
18584 #define HSEM_C1MISR_MISF18        HSEM_C1MISR_MISF18_Msk                       /*!<semaphore 18 interrupt 0 masked status bit. */
18585 #define HSEM_C1MISR_MISF19_Pos    (19U)
18586 #define HSEM_C1MISR_MISF19_Msk    (0x1UL << HSEM_C1MISR_MISF19_Pos)            /*!< 0x00080000 */
18587 #define HSEM_C1MISR_MISF19        HSEM_C1MISR_MISF19_Msk                       /*!<semaphore 19 interrupt 0 masked status bit. */
18588 #define HSEM_C1MISR_MISF20_Pos    (20U)
18589 #define HSEM_C1MISR_MISF20_Msk    (0x1UL << HSEM_C1MISR_MISF20_Pos)            /*!< 0x00100000 */
18590 #define HSEM_C1MISR_MISF20        HSEM_C1MISR_MISF20_Msk                       /*!<semaphore 20 interrupt 0 masked status bit. */
18591 #define HSEM_C1MISR_MISF21_Pos    (21U)
18592 #define HSEM_C1MISR_MISF21_Msk    (0x1UL << HSEM_C1MISR_MISF21_Pos)            /*!< 0x00200000 */
18593 #define HSEM_C1MISR_MISF21        HSEM_C1MISR_MISF21_Msk                       /*!<semaphore 21 interrupt 0 masked status bit. */
18594 #define HSEM_C1MISR_MISF22_Pos    (22U)
18595 #define HSEM_C1MISR_MISF22_Msk    (0x1UL << HSEM_C1MISR_MISF22_Pos)            /*!< 0x00400000 */
18596 #define HSEM_C1MISR_MISF22        HSEM_C1MISR_MISF22_Msk                       /*!<semaphore 22 interrupt 0 masked status bit. */
18597 #define HSEM_C1MISR_MISF23_Pos    (23U)
18598 #define HSEM_C1MISR_MISF23_Msk    (0x1UL << HSEM_C1MISR_MISF23_Pos)            /*!< 0x00800000 */
18599 #define HSEM_C1MISR_MISF23        HSEM_C1MISR_MISF23_Msk                       /*!<semaphore 23 interrupt 0 masked status bit. */
18600 #define HSEM_C1MISR_MISF24_Pos    (24U)
18601 #define HSEM_C1MISR_MISF24_Msk    (0x1UL << HSEM_C1MISR_MISF24_Pos)            /*!< 0x01000000 */
18602 #define HSEM_C1MISR_MISF24        HSEM_C1MISR_MISF24_Msk                       /*!<semaphore 24 interrupt 0 masked status bit. */
18603 #define HSEM_C1MISR_MISF25_Pos    (25U)
18604 #define HSEM_C1MISR_MISF25_Msk    (0x1UL << HSEM_C1MISR_MISF25_Pos)            /*!< 0x02000000 */
18605 #define HSEM_C1MISR_MISF25        HSEM_C1MISR_MISF25_Msk                       /*!<semaphore 25 interrupt 0 masked status bit. */
18606 #define HSEM_C1MISR_MISF26_Pos    (26U)
18607 #define HSEM_C1MISR_MISF26_Msk    (0x1UL << HSEM_C1MISR_MISF26_Pos)            /*!< 0x04000000 */
18608 #define HSEM_C1MISR_MISF26        HSEM_C1MISR_MISF26_Msk                       /*!<semaphore 26 interrupt 0 masked status bit. */
18609 #define HSEM_C1MISR_MISF27_Pos    (27U)
18610 #define HSEM_C1MISR_MISF27_Msk    (0x1UL << HSEM_C1MISR_MISF27_Pos)            /*!< 0x08000000 */
18611 #define HSEM_C1MISR_MISF27        HSEM_C1MISR_MISF27_Msk                       /*!<semaphore 27 interrupt 0 masked status bit. */
18612 #define HSEM_C1MISR_MISF28_Pos    (28U)
18613 #define HSEM_C1MISR_MISF28_Msk    (0x1UL << HSEM_C1MISR_MISF28_Pos)            /*!< 0x10000000 */
18614 #define HSEM_C1MISR_MISF28        HSEM_C1MISR_MISF28_Msk                       /*!<semaphore 28 interrupt 0 masked status bit. */
18615 #define HSEM_C1MISR_MISF29_Pos    (29U)
18616 #define HSEM_C1MISR_MISF29_Msk    (0x1UL << HSEM_C1MISR_MISF29_Pos)            /*!< 0x20000000 */
18617 #define HSEM_C1MISR_MISF29        HSEM_C1MISR_MISF29_Msk                       /*!<semaphore 29 interrupt 0 masked status bit. */
18618 #define HSEM_C1MISR_MISF30_Pos    (30U)
18619 #define HSEM_C1MISR_MISF30_Msk    (0x1UL << HSEM_C1MISR_MISF30_Pos)            /*!< 0x40000000 */
18620 #define HSEM_C1MISR_MISF30        HSEM_C1MISR_MISF30_Msk                       /*!<semaphore 30 interrupt 0 masked status bit. */
18621 #define HSEM_C1MISR_MISF31_Pos    (31U)
18622 #define HSEM_C1MISR_MISF31_Msk    (0x1UL << HSEM_C1MISR_MISF31_Pos)            /*!< 0x80000000 */
18623 #define HSEM_C1MISR_MISF31        HSEM_C1MISR_MISF31_Msk                       /*!<semaphore 31 interrupt 0 masked status bit. */
18624 
18625 /********************  Bit definition for HSEM_CR register  *****************/
18626 #define HSEM_CR_COREID_Pos        (8U)
18627 #define HSEM_CR_COREID_Msk        (0xFFUL << HSEM_CR_COREID_Pos)               /*!< 0x0000FF00 */
18628 #define HSEM_CR_COREID            HSEM_CR_COREID_Msk                            /*!<CoreID of semaphores to be cleared. */
18629 #define HSEM_CR_KEY_Pos           (16U)
18630 #define HSEM_CR_KEY_Msk           (0xFFFFUL << HSEM_CR_KEY_Pos)                /*!< 0xFFFF0000 */
18631 #define HSEM_CR_KEY               HSEM_CR_KEY_Msk                               /*!<semaphores clear key. */
18632 
18633 /********************  Bit definition for HSEM_KEYR register  *****************/
18634 #define HSEM_KEYR_KEY_Pos         (16U)
18635 #define HSEM_KEYR_KEY_Msk         (0xFFFFUL << HSEM_KEYR_KEY_Pos)              /*!< 0xFFFF0000 */
18636 #define HSEM_KEYR_KEY             HSEM_KEYR_KEY_Msk                             /*!<semaphores clear key. */
18637 
18638 /**********************  Bit definition for HSEM_HWCFGR2 register  ***************/
18639 #define HSEM_HWCFGR2_MASTERID1_Pos  (0U)
18640 #define HSEM_HWCFGR2_MASTERID1_Msk  (0xFU << HSEM_HWCFGR2_MASTERID1_Pos)        /*!< 0x0000000F */
18641 #define HSEM_HWCFGR2_MASTERID1      HSEM_HWCFGR2_MASTERID1_Msk                  /*!< HW Config valid bus masters ID1 */
18642 #define HSEM_HWCFGR2_MASTERID2_Pos  (4U)
18643 #define HSEM_HWCFGR2_MASTERID2_Msk  (0xFU << HSEM_HWCFGR2_MASTERID2_Pos)        /*!< 0x000000F0 */
18644 #define HSEM_HWCFGR2_MASTERID2      HSEM_HWCFGR2_MASTERID2_Msk                  /*!< HW Config valid bus masters ID2 */
18645 #define HSEM_HWCFGR2_MASTERID3_Pos  (8U)
18646 #define HSEM_HWCFGR2_MASTERID3_Msk  (0xFU << HSEM_HWCFGR2_MASTERID3_Pos)        /*!< 0x00000F00 */
18647 #define HSEM_HWCFGR2_MASTERID3      HSEM_HWCFGR2_MASTERID3_Msk                  /*!< HW Config valid bus masters ID3 */
18648 #define HSEM_HWCFGR2_MASTERID4_Pos  (12U)
18649 #define HSEM_HWCFGR2_MASTERID4_Msk  (0xFU << HSEM_HWCFGR2_MASTERID4_Pos)        /*!< 0x0000F000 */
18650 #define HSEM_HWCFGR2_MASTERID4      HSEM_HWCFGR2_MASTERID4_Msk                  /*!< HW Config valid bus masters ID4 */
18651 
18652 /**********************  Bit definition for HSEM_HWCFGR1 register  ***************/
18653 #define HSEM_HWCFGR1_NBSEM_Pos  (0U)
18654 #define HSEM_HWCFGR1_NBSEM_Msk  (0xFFU << HSEM_HWCFGR1_NBSEM_Pos)        /*!< 0x000000FF */
18655 #define HSEM_HWCFGR1_NBSEM      HSEM_HWCFGR1_NBSEM_Msk                  /*!< HW Config number of semaphores */
18656 #define HSEM_HWCFGR1_NBINT_Pos  (8U)
18657 #define HSEM_HWCFGR1_NBINT_Msk  (0xFU << HSEM_HWCFGR1_NBINT_Pos)        /*!< 0x00000F00 */
18658 #define HSEM_HWCFGR1_NBINT      HSEM_HWCFGR1_NBINT_Msk                  /*!< HW Config number of interrupts/ supported number of master IDs */
18659 
18660 
18661 /**********************  Bit definition for HSEM_VERR register  *****************/
18662 #define HSEM_VERR_MINREV_Pos      (0U)
18663 #define HSEM_VERR_MINREV_Msk      (0xFU << HSEM_VERR_MINREV_Pos)               /*!< 0x0000000F */
18664 #define HSEM_VERR_MINREV          HSEM_VERR_MINREV_Msk                         /*!< Minor Revision number */
18665 #define HSEM_VERR_MAJREV_Pos      (4U)
18666 #define HSEM_VERR_MAJREV_Msk      (0xFU << HSEM_VERR_MAJREV_Pos)               /*!< 0x000000F0 */
18667 #define HSEM_VERR_MAJREV          HSEM_VERR_MAJREV_Msk                         /*!< Major Revision number */
18668 
18669 /**********************  Bit definition for HSEM_IPIDR register  ****************/
18670 #define HSEM_IPIDR_IPID_Pos       (0U)
18671 #define HSEM_IPIDR_IPID_Msk       (0xFFFFFFFFU << HSEM_IPIDR_IPID_Pos)         /*!< 0xFFFFFFFF */
18672 #define HSEM_IPIDR_IPID           HSEM_IPIDR_IPID_Msk                          /*!< IP Identification */
18673 
18674 /**********************  Bit definition for HSEM_SIDR register  *****************/
18675 #define HSEM_SIDR_SID_Pos         (0U)
18676 #define HSEM_SIDR_SID_Msk         (0xFFFFFFFFU << HSEM_SIDR_SID_Pos)           /*!< 0xFFFFFFFF */
18677 #define HSEM_SIDR_SID             HSEM_SIDR_SID_Msk                            /*!< IP size identification */
18678 
18679 /******************************************************************************/
18680 /*                                                                            */
18681 /*                                    HASH                                    */
18682 /*                                                                            */
18683 /******************************************************************************/
18684 /******************  Bits definition for HASH_CR register  ********************/
18685 #define HASH_CR_INIT_Pos          (2U)
18686 #define HASH_CR_INIT_Msk          (0x1U << HASH_CR_INIT_Pos)                   /*!< 0x00000004 */
18687 #define HASH_CR_INIT              HASH_CR_INIT_Msk
18688 #define HASH_CR_DMAE_Pos          (3U)
18689 #define HASH_CR_DMAE_Msk          (0x1U << HASH_CR_DMAE_Pos)                   /*!< 0x00000008 */
18690 #define HASH_CR_DMAE              HASH_CR_DMAE_Msk
18691 #define HASH_CR_DATATYPE_Pos      (4U)
18692 #define HASH_CR_DATATYPE_Msk      (0x3U << HASH_CR_DATATYPE_Pos)               /*!< 0x00000030 */
18693 #define HASH_CR_DATATYPE          HASH_CR_DATATYPE_Msk
18694 #define HASH_CR_DATATYPE_0        (0x1U << HASH_CR_DATATYPE_Pos)               /*!< 0x00000010 */
18695 #define HASH_CR_DATATYPE_1        (0x2U << HASH_CR_DATATYPE_Pos)               /*!< 0x00000020 */
18696 #define HASH_CR_MODE_Pos          (6U)
18697 #define HASH_CR_MODE_Msk          (0x1U << HASH_CR_MODE_Pos)                   /*!< 0x00000040 */
18698 #define HASH_CR_MODE              HASH_CR_MODE_Msk
18699 #define HASH_CR_ALGO_Pos          (7U)
18700 #define HASH_CR_ALGO_Msk          (0x801U << HASH_CR_ALGO_Pos)                 /*!< 0x00040080 */
18701 #define HASH_CR_ALGO              HASH_CR_ALGO_Msk
18702 #define HASH_CR_ALGO_0            (0x001U << HASH_CR_ALGO_Pos)                 /*!< 0x00000080 */
18703 #define HASH_CR_ALGO_1            (0x800U << HASH_CR_ALGO_Pos)                 /*!< 0x00040000 */
18704 #define HASH_CR_NBW_Pos           (8U)
18705 #define HASH_CR_NBW_Msk           (0xFU << HASH_CR_NBW_Pos)                    /*!< 0x00000F00 */
18706 #define HASH_CR_NBW               HASH_CR_NBW_Msk
18707 #define HASH_CR_NBW_0             (0x1U << HASH_CR_NBW_Pos)                    /*!< 0x00000100 */
18708 #define HASH_CR_NBW_1             (0x2U << HASH_CR_NBW_Pos)                    /*!< 0x00000200 */
18709 #define HASH_CR_NBW_2             (0x4U << HASH_CR_NBW_Pos)                    /*!< 0x00000400 */
18710 #define HASH_CR_NBW_3             (0x8U << HASH_CR_NBW_Pos)                    /*!< 0x00000800 */
18711 #define HASH_CR_DINNE_Pos         (12U)
18712 #define HASH_CR_DINNE_Msk         (0x1U << HASH_CR_DINNE_Pos)                  /*!< 0x00001000 */
18713 #define HASH_CR_DINNE             HASH_CR_DINNE_Msk
18714 #define HASH_CR_MDMAT_Pos         (13U)
18715 #define HASH_CR_MDMAT_Msk         (0x1U << HASH_CR_MDMAT_Pos)                  /*!< 0x00002000 */
18716 #define HASH_CR_MDMAT             HASH_CR_MDMAT_Msk
18717 #define HASH_CR_DMAA_Pos          (14U)
18718 #define HASH_CR_DMAA_Msk          (0x1U << HASH_CR_DMAA_Pos)                   /*!< 0x00004000 */
18719 #define HASH_CR_DMAA              HASH_CR_DMAA_Msk
18720 #define HASH_CR_LKEY_Pos          (16U)
18721 #define HASH_CR_LKEY_Msk          (0x1U << HASH_CR_LKEY_Pos)                   /*!< 0x00010000 */
18722 #define HASH_CR_LKEY              HASH_CR_LKEY_Msk
18723 
18724 /******************  Bits definition for HASH_STR register  *******************/
18725 #define HASH_STR_NBLW_Pos         (0U)
18726 #define HASH_STR_NBLW_Msk         (0x1FU << HASH_STR_NBLW_Pos)                 /*!< 0x0000001F */
18727 #define HASH_STR_NBLW             HASH_STR_NBLW_Msk
18728 #define HASH_STR_NBLW_0           (0x01U << HASH_STR_NBLW_Pos)                 /*!< 0x00000001 */
18729 #define HASH_STR_NBLW_1           (0x02U << HASH_STR_NBLW_Pos)                 /*!< 0x00000002 */
18730 #define HASH_STR_NBLW_2           (0x04U << HASH_STR_NBLW_Pos)                 /*!< 0x00000004 */
18731 #define HASH_STR_NBLW_3           (0x08U << HASH_STR_NBLW_Pos)                 /*!< 0x00000008 */
18732 #define HASH_STR_NBLW_4           (0x10U << HASH_STR_NBLW_Pos)                 /*!< 0x00000010 */
18733 #define HASH_STR_DCAL_Pos         (8U)
18734 #define HASH_STR_DCAL_Msk         (0x1U << HASH_STR_DCAL_Pos)                  /*!< 0x00000100 */
18735 #define HASH_STR_DCAL             HASH_STR_DCAL_Msk
18736 
18737 /******************  Bits definition for HASH_IMR register  *******************/
18738 #define HASH_IMR_DINIE_Pos        (0U)
18739 #define HASH_IMR_DINIE_Msk        (0x1U << HASH_IMR_DINIE_Pos)                 /*!< 0x00000001 */
18740 #define HASH_IMR_DINIE            HASH_IMR_DINIE_Msk
18741 #define HASH_IMR_DCIE_Pos         (1U)
18742 #define HASH_IMR_DCIE_Msk         (0x1U << HASH_IMR_DCIE_Pos)                  /*!< 0x00000002 */
18743 #define HASH_IMR_DCIE             HASH_IMR_DCIE_Msk
18744 
18745 /******************  Bits definition for HASH_SR register  ********************/
18746 #define HASH_SR_DINIS_Pos         (0U)
18747 #define HASH_SR_DINIS_Msk         (0x1U << HASH_SR_DINIS_Pos)                  /*!< 0x00000001 */
18748 #define HASH_SR_DINIS             HASH_SR_DINIS_Msk
18749 #define HASH_SR_DCIS_Pos          (1U)
18750 #define HASH_SR_DCIS_Msk          (0x1U << HASH_SR_DCIS_Pos)                   /*!< 0x00000002 */
18751 #define HASH_SR_DCIS              HASH_SR_DCIS_Msk
18752 #define HASH_SR_DMAS_Pos          (2U)
18753 #define HASH_SR_DMAS_Msk          (0x1U << HASH_SR_DMAS_Pos)                   /*!< 0x00000004 */
18754 #define HASH_SR_DMAS              HASH_SR_DMAS_Msk
18755 #define HASH_SR_BUSY_Pos          (3U)
18756 #define HASH_SR_BUSY_Msk          (0x1U << HASH_SR_BUSY_Pos)                   /*!< 0x00000008 */
18757 #define HASH_SR_BUSY              HASH_SR_BUSY_Msk
18758 
18759 /**********************  Bit definition for HASH_HWCFGR register  ***************/
18760 #define HASH_HWCFGR_CFG1_Pos  (0U)
18761 #define HASH_HWCFGR_CFG1_Msk  (0xFU << HASH_HWCFGR_CFG1_Pos)           /*!< 0x0000000F */
18762 #define HASH_HWCFGR_CFG1      HASH_HWCFGR_CFG1_Msk                     /*!< use_mdma generic value (0x1) */
18763 
18764 /**********************  Bit definition for HASH_VERR register  *****************/
18765 #define HASH_VERR_VER_Pos      (0U)
18766 #define HASH_VERR_VER_Msk      (0xFFU << HASH_VERR_VER_Pos)               /*!< 0x0000000FF */
18767 #define HASH_VERR_VER          HASH_VERR_VER_Msk                         /*!<  Revision number */
18768 
18769 /**********************  Bit definition for HASH_IPIDR register  ****************/
18770 #define HASH_IPIDR_IPID_Pos       (0U)
18771 #define HASH_IPIDR_IPID_Msk       (0xFFFFFFFFU << HASH_IPIDR_IPID_Pos)         /*!< 0xFFFFFFFF */
18772 #define HASH_IPIDR_IPID           HASH_IPIDR_IPID_Msk                          /*!< IP Identification */
18773 
18774 /**********************  Bit definition for HASH_SIDR register  *****************/
18775 #define HASH_MID_MID_Pos         (0U)
18776 #define HASH_MID_MID_Msk         (0xFFFFFFFFU << HASH_MID_MID_Pos)           /*!< 0xFFFFFFFF */
18777 #define HASH_MID_MID             HASH_MID_MID_Msk                            /*!< Magic identification */
18778 
18779 /******************************************************************************/
18780 /*                                                                            */
18781 /*                      Inter-integrated Circuit Interface (I2C)              */
18782 /*                                                                            */
18783 /******************************************************************************/
18784 /*******************  Bit definition for I2C_CR1 register  *******************/
18785 #define I2C_CR1_PE_Pos               (0U)
18786 #define I2C_CR1_PE_Msk               (0x1U << I2C_CR1_PE_Pos)                  /*!< 0x00000001 */
18787 #define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */
18788 #define I2C_CR1_TXIE_Pos             (1U)
18789 #define I2C_CR1_TXIE_Msk             (0x1U << I2C_CR1_TXIE_Pos)                /*!< 0x00000002 */
18790 #define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */
18791 #define I2C_CR1_RXIE_Pos             (2U)
18792 #define I2C_CR1_RXIE_Msk             (0x1U << I2C_CR1_RXIE_Pos)                /*!< 0x00000004 */
18793 #define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */
18794 #define I2C_CR1_ADDRIE_Pos           (3U)
18795 #define I2C_CR1_ADDRIE_Msk           (0x1U << I2C_CR1_ADDRIE_Pos)              /*!< 0x00000008 */
18796 #define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */
18797 #define I2C_CR1_NACKIE_Pos           (4U)
18798 #define I2C_CR1_NACKIE_Msk           (0x1U << I2C_CR1_NACKIE_Pos)              /*!< 0x00000010 */
18799 #define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */
18800 #define I2C_CR1_STOPIE_Pos           (5U)
18801 #define I2C_CR1_STOPIE_Msk           (0x1U << I2C_CR1_STOPIE_Pos)              /*!< 0x00000020 */
18802 #define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */
18803 #define I2C_CR1_TCIE_Pos             (6U)
18804 #define I2C_CR1_TCIE_Msk             (0x1U << I2C_CR1_TCIE_Pos)                /*!< 0x00000040 */
18805 #define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */
18806 #define I2C_CR1_ERRIE_Pos            (7U)
18807 #define I2C_CR1_ERRIE_Msk            (0x1U << I2C_CR1_ERRIE_Pos)               /*!< 0x00000080 */
18808 #define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */
18809 #define I2C_CR1_DNF_Pos              (8U)
18810 #define I2C_CR1_DNF_Msk              (0xFU << I2C_CR1_DNF_Pos)                 /*!< 0x00000F00 */
18811 #define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */
18812 #define I2C_CR1_ANFOFF_Pos           (12U)
18813 #define I2C_CR1_ANFOFF_Msk           (0x1U << I2C_CR1_ANFOFF_Pos)              /*!< 0x00001000 */
18814 #define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */
18815 #define I2C_CR1_SWRST_Pos            (13U)
18816 #define I2C_CR1_SWRST_Msk            (0x1U << I2C_CR1_SWRST_Pos)               /*!< 0x00002000 */
18817 #define I2C_CR1_SWRST                I2C_CR1_SWRST_Msk                         /*!< Software reset */
18818 #define I2C_CR1_TXDMAEN_Pos          (14U)
18819 #define I2C_CR1_TXDMAEN_Msk          (0x1U << I2C_CR1_TXDMAEN_Pos)             /*!< 0x00004000 */
18820 #define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */
18821 #define I2C_CR1_RXDMAEN_Pos          (15U)
18822 #define I2C_CR1_RXDMAEN_Msk          (0x1U << I2C_CR1_RXDMAEN_Pos)             /*!< 0x00008000 */
18823 #define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */
18824 #define I2C_CR1_SBC_Pos              (16U)
18825 #define I2C_CR1_SBC_Msk              (0x1U << I2C_CR1_SBC_Pos)                 /*!< 0x00010000 */
18826 #define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */
18827 #define I2C_CR1_NOSTRETCH_Pos        (17U)
18828 #define I2C_CR1_NOSTRETCH_Msk        (0x1U << I2C_CR1_NOSTRETCH_Pos)           /*!< 0x00020000 */
18829 #define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */
18830 #define I2C_CR1_WUPEN_Pos            (18U)
18831 #define I2C_CR1_WUPEN_Msk            (0x1U << I2C_CR1_WUPEN_Pos)               /*!< 0x00040000 */
18832 #define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */
18833 #define I2C_CR1_GCEN_Pos             (19U)
18834 #define I2C_CR1_GCEN_Msk             (0x1U << I2C_CR1_GCEN_Pos)                /*!< 0x00080000 */
18835 #define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */
18836 #define I2C_CR1_SMBHEN_Pos           (20U)
18837 #define I2C_CR1_SMBHEN_Msk           (0x1U << I2C_CR1_SMBHEN_Pos)              /*!< 0x00100000 */
18838 #define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */
18839 #define I2C_CR1_SMBDEN_Pos           (21U)
18840 #define I2C_CR1_SMBDEN_Msk           (0x1U << I2C_CR1_SMBDEN_Pos)              /*!< 0x00200000 */
18841 #define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
18842 #define I2C_CR1_ALERTEN_Pos          (22U)
18843 #define I2C_CR1_ALERTEN_Msk          (0x1U << I2C_CR1_ALERTEN_Pos)             /*!< 0x00400000 */
18844 #define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */
18845 #define I2C_CR1_PECEN_Pos            (23U)
18846 #define I2C_CR1_PECEN_Msk            (0x1U << I2C_CR1_PECEN_Pos)               /*!< 0x00800000 */
18847 #define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */
18848 
18849 /******************  Bit definition for I2C_CR2 register  ********************/
18850 #define I2C_CR2_SADD_Pos             (0U)
18851 #define I2C_CR2_SADD_Msk             (0x3FFU << I2C_CR2_SADD_Pos)              /*!< 0x000003FF */
18852 #define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */
18853 #define I2C_CR2_RD_WRN_Pos           (10U)
18854 #define I2C_CR2_RD_WRN_Msk           (0x1U << I2C_CR2_RD_WRN_Pos)              /*!< 0x00000400 */
18855 #define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */
18856 #define I2C_CR2_ADD10_Pos            (11U)
18857 #define I2C_CR2_ADD10_Msk            (0x1U << I2C_CR2_ADD10_Pos)               /*!< 0x00000800 */
18858 #define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */
18859 #define I2C_CR2_HEAD10R_Pos          (12U)
18860 #define I2C_CR2_HEAD10R_Msk          (0x1U << I2C_CR2_HEAD10R_Pos)             /*!< 0x00001000 */
18861 #define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
18862 #define I2C_CR2_START_Pos            (13U)
18863 #define I2C_CR2_START_Msk            (0x1U << I2C_CR2_START_Pos)               /*!< 0x00002000 */
18864 #define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */
18865 #define I2C_CR2_STOP_Pos             (14U)
18866 #define I2C_CR2_STOP_Msk             (0x1U << I2C_CR2_STOP_Pos)                /*!< 0x00004000 */
18867 #define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */
18868 #define I2C_CR2_NACK_Pos             (15U)
18869 #define I2C_CR2_NACK_Msk             (0x1U << I2C_CR2_NACK_Pos)                /*!< 0x00008000 */
18870 #define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */
18871 #define I2C_CR2_NBYTES_Pos           (16U)
18872 #define I2C_CR2_NBYTES_Msk           (0xFFU << I2C_CR2_NBYTES_Pos)             /*!< 0x00FF0000 */
18873 #define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */
18874 #define I2C_CR2_RELOAD_Pos           (24U)
18875 #define I2C_CR2_RELOAD_Msk           (0x1U << I2C_CR2_RELOAD_Pos)              /*!< 0x01000000 */
18876 #define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */
18877 #define I2C_CR2_AUTOEND_Pos          (25U)
18878 #define I2C_CR2_AUTOEND_Msk          (0x1U << I2C_CR2_AUTOEND_Pos)             /*!< 0x02000000 */
18879 #define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */
18880 #define I2C_CR2_PECBYTE_Pos          (26U)
18881 #define I2C_CR2_PECBYTE_Msk          (0x1U << I2C_CR2_PECBYTE_Pos)             /*!< 0x04000000 */
18882 #define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */
18883 
18884 /*******************  Bit definition for I2C_OAR1 register  ******************/
18885 #define I2C_OAR1_OA1_Pos             (0U)
18886 #define I2C_OAR1_OA1_Msk             (0x3FFU << I2C_OAR1_OA1_Pos)              /*!< 0x000003FF */
18887 #define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */
18888 #define I2C_OAR1_OA1MODE_Pos         (10U)
18889 #define I2C_OAR1_OA1MODE_Msk         (0x1U << I2C_OAR1_OA1MODE_Pos)            /*!< 0x00000400 */
18890 #define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
18891 #define I2C_OAR1_OA1EN_Pos           (15U)
18892 #define I2C_OAR1_OA1EN_Msk           (0x1U << I2C_OAR1_OA1EN_Pos)              /*!< 0x00008000 */
18893 #define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */
18894 
18895 /*******************  Bit definition for I2C_OAR2 register  ******************/
18896 #define I2C_OAR2_OA2_Pos             (1U)
18897 #define I2C_OAR2_OA2_Msk             (0x7FU << I2C_OAR2_OA2_Pos)               /*!< 0x000000FE */
18898 #define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2 */
18899 #define I2C_OAR2_OA2MSK_Pos          (8U)
18900 #define I2C_OAR2_OA2MSK_Msk          (0x7U << I2C_OAR2_OA2MSK_Pos)             /*!< 0x00000700 */
18901 #define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks */
18902 #define I2C_OAR2_OA2NOMASK           0x00000000UL                              /*!< No mask */
18903 #define I2C_OAR2_OA2MASK01_Pos       (8U)
18904 #define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)         /*!< 0x00000100 */
18905 #define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared */
18906 #define I2C_OAR2_OA2MASK02_Pos       (9U)
18907 #define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)         /*!< 0x00000200 */
18908 #define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
18909 #define I2C_OAR2_OA2MASK03_Pos       (8U)
18910 #define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)         /*!< 0x00000300 */
18911 #define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
18912 #define I2C_OAR2_OA2MASK04_Pos       (10U)
18913 #define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)         /*!< 0x00000400 */
18914 #define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
18915 #define I2C_OAR2_OA2MASK05_Pos       (8U)
18916 #define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)         /*!< 0x00000500 */
18917 #define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
18918 #define I2C_OAR2_OA2MASK06_Pos       (9U)
18919 #define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)         /*!< 0x00000600 */
18920 #define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared */
18921 #define I2C_OAR2_OA2MASK07_Pos       (8U)
18922 #define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)         /*!< 0x00000700 */
18923 #define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done */
18924 #define I2C_OAR2_OA2EN_Pos           (15U)
18925 #define I2C_OAR2_OA2EN_Msk           (0x1U << I2C_OAR2_OA2EN_Pos)              /*!< 0x00008000 */
18926 #define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable */
18927 
18928 /*******************  Bit definition for I2C_TIMINGR register *******************/
18929 #define I2C_TIMINGR_SCLL_Pos         (0U)
18930 #define I2C_TIMINGR_SCLL_Msk         (0xFFU << I2C_TIMINGR_SCLL_Pos)           /*!< 0x000000FF */
18931 #define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */
18932 #define I2C_TIMINGR_SCLH_Pos         (8U)
18933 #define I2C_TIMINGR_SCLH_Msk         (0xFFU << I2C_TIMINGR_SCLH_Pos)           /*!< 0x0000FF00 */
18934 #define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
18935 #define I2C_TIMINGR_SDADEL_Pos       (16U)
18936 #define I2C_TIMINGR_SDADEL_Msk       (0xFU << I2C_TIMINGR_SDADEL_Pos)          /*!< 0x000F0000 */
18937 #define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */
18938 #define I2C_TIMINGR_SCLDEL_Pos       (20U)
18939 #define I2C_TIMINGR_SCLDEL_Msk       (0xFU << I2C_TIMINGR_SCLDEL_Pos)          /*!< 0x00F00000 */
18940 #define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */
18941 #define I2C_TIMINGR_PRESC_Pos        (28U)
18942 #define I2C_TIMINGR_PRESC_Msk        (0xFU << I2C_TIMINGR_PRESC_Pos)           /*!< 0xF0000000 */
18943 #define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */
18944 
18945 /******************* Bit definition for I2C_TIMEOUTR register *******************/
18946 #define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)
18947 #define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos)     /*!< 0x00000FFF */
18948 #define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */
18949 #define I2C_TIMEOUTR_TIDLE_Pos       (12U)
18950 #define I2C_TIMEOUTR_TIDLE_Msk       (0x1U << I2C_TIMEOUTR_TIDLE_Pos)          /*!< 0x00001000 */
18951 #define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */
18952 #define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)
18953 #define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos)       /*!< 0x00008000 */
18954 #define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */
18955 #define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)
18956 #define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos)     /*!< 0x0FFF0000 */
18957 #define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/
18958 #define I2C_TIMEOUTR_TEXTEN_Pos      (31U)
18959 #define I2C_TIMEOUTR_TEXTEN_Msk      (0x1U << I2C_TIMEOUTR_TEXTEN_Pos)         /*!< 0x80000000 */
18960 #define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
18961 
18962 /******************  Bit definition for I2C_ISR register  *********************/
18963 #define I2C_ISR_TXE_Pos              (0U)
18964 #define I2C_ISR_TXE_Msk              (0x1U << I2C_ISR_TXE_Pos)                 /*!< 0x00000001 */
18965 #define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */
18966 #define I2C_ISR_TXIS_Pos             (1U)
18967 #define I2C_ISR_TXIS_Msk             (0x1U << I2C_ISR_TXIS_Pos)                /*!< 0x00000002 */
18968 #define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */
18969 #define I2C_ISR_RXNE_Pos             (2U)
18970 #define I2C_ISR_RXNE_Msk             (0x1U << I2C_ISR_RXNE_Pos)                /*!< 0x00000004 */
18971 #define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
18972 #define I2C_ISR_ADDR_Pos             (3U)
18973 #define I2C_ISR_ADDR_Msk             (0x1U << I2C_ISR_ADDR_Pos)                /*!< 0x00000008 */
18974 #define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/
18975 #define I2C_ISR_NACKF_Pos            (4U)
18976 #define I2C_ISR_NACKF_Msk            (0x1U << I2C_ISR_NACKF_Pos)               /*!< 0x00000010 */
18977 #define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */
18978 #define I2C_ISR_STOPF_Pos            (5U)
18979 #define I2C_ISR_STOPF_Msk            (0x1U << I2C_ISR_STOPF_Pos)               /*!< 0x00000020 */
18980 #define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */
18981 #define I2C_ISR_TC_Pos               (6U)
18982 #define I2C_ISR_TC_Msk               (0x1U << I2C_ISR_TC_Pos)                  /*!< 0x00000040 */
18983 #define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
18984 #define I2C_ISR_TCR_Pos              (7U)
18985 #define I2C_ISR_TCR_Msk              (0x1U << I2C_ISR_TCR_Pos)                 /*!< 0x00000080 */
18986 #define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */
18987 #define I2C_ISR_BERR_Pos             (8U)
18988 #define I2C_ISR_BERR_Msk             (0x1U << I2C_ISR_BERR_Pos)                /*!< 0x00000100 */
18989 #define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */
18990 #define I2C_ISR_ARLO_Pos             (9U)
18991 #define I2C_ISR_ARLO_Msk             (0x1U << I2C_ISR_ARLO_Pos)                /*!< 0x00000200 */
18992 #define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */
18993 #define I2C_ISR_OVR_Pos              (10U)
18994 #define I2C_ISR_OVR_Msk              (0x1U << I2C_ISR_OVR_Pos)                 /*!< 0x00000400 */
18995 #define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */
18996 #define I2C_ISR_PECERR_Pos           (11U)
18997 #define I2C_ISR_PECERR_Msk           (0x1U << I2C_ISR_PECERR_Pos)              /*!< 0x00000800 */
18998 #define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */
18999 #define I2C_ISR_TIMEOUT_Pos          (12U)
19000 #define I2C_ISR_TIMEOUT_Msk          (0x1U << I2C_ISR_TIMEOUT_Pos)             /*!< 0x00001000 */
19001 #define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */
19002 #define I2C_ISR_ALERT_Pos            (13U)
19003 #define I2C_ISR_ALERT_Msk            (0x1U << I2C_ISR_ALERT_Pos)               /*!< 0x00002000 */
19004 #define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */
19005 #define I2C_ISR_BUSY_Pos             (15U)
19006 #define I2C_ISR_BUSY_Msk             (0x1U << I2C_ISR_BUSY_Pos)                /*!< 0x00008000 */
19007 #define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */
19008 #define I2C_ISR_DIR_Pos              (16U)
19009 #define I2C_ISR_DIR_Msk              (0x1U << I2C_ISR_DIR_Pos)                 /*!< 0x00010000 */
19010 #define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
19011 #define I2C_ISR_ADDCODE_Pos          (17U)
19012 #define I2C_ISR_ADDCODE_Msk          (0x7FU << I2C_ISR_ADDCODE_Pos)            /*!< 0x00FE0000 */
19013 #define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
19014 
19015 /******************  Bit definition for I2C_ICR register  *********************/
19016 #define I2C_ICR_ADDRCF_Pos           (3U)
19017 #define I2C_ICR_ADDRCF_Msk           (0x1U << I2C_ICR_ADDRCF_Pos)              /*!< 0x00000008 */
19018 #define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */
19019 #define I2C_ICR_NACKCF_Pos           (4U)
19020 #define I2C_ICR_NACKCF_Msk           (0x1U << I2C_ICR_NACKCF_Pos)              /*!< 0x00000010 */
19021 #define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */
19022 #define I2C_ICR_STOPCF_Pos           (5U)
19023 #define I2C_ICR_STOPCF_Msk           (0x1U << I2C_ICR_STOPCF_Pos)              /*!< 0x00000020 */
19024 #define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */
19025 #define I2C_ICR_BERRCF_Pos           (8U)
19026 #define I2C_ICR_BERRCF_Msk           (0x1U << I2C_ICR_BERRCF_Pos)              /*!< 0x00000100 */
19027 #define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */
19028 #define I2C_ICR_ARLOCF_Pos           (9U)
19029 #define I2C_ICR_ARLOCF_Msk           (0x1U << I2C_ICR_ARLOCF_Pos)              /*!< 0x00000200 */
19030 #define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
19031 #define I2C_ICR_OVRCF_Pos            (10U)
19032 #define I2C_ICR_OVRCF_Msk            (0x1U << I2C_ICR_OVRCF_Pos)               /*!< 0x00000400 */
19033 #define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
19034 #define I2C_ICR_PECCF_Pos            (11U)
19035 #define I2C_ICR_PECCF_Msk            (0x1U << I2C_ICR_PECCF_Pos)               /*!< 0x00000800 */
19036 #define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */
19037 #define I2C_ICR_TIMOUTCF_Pos         (12U)
19038 #define I2C_ICR_TIMOUTCF_Msk         (0x1U << I2C_ICR_TIMOUTCF_Pos)            /*!< 0x00001000 */
19039 #define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */
19040 #define I2C_ICR_ALERTCF_Pos          (13U)
19041 #define I2C_ICR_ALERTCF_Msk          (0x1U << I2C_ICR_ALERTCF_Pos)             /*!< 0x00002000 */
19042 #define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */
19043 
19044 /******************  Bit definition for I2C_PECR register  *********************/
19045 #define I2C_PECR_PEC_Pos             (0U)
19046 #define I2C_PECR_PEC_Msk             (0xFFU << I2C_PECR_PEC_Pos)               /*!< 0x000000FF */
19047 #define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
19048 
19049 /******************  Bit definition for I2C_RXDR register  *********************/
19050 #define I2C_RXDR_RXDATA_Pos          (0U)
19051 #define I2C_RXDR_RXDATA_Msk          (0xFFU << I2C_RXDR_RXDATA_Pos)            /*!< 0x000000FF */
19052 #define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
19053 
19054 /******************  Bit definition for I2C_TXDR register  *********************/
19055 #define I2C_TXDR_TXDATA_Pos          (0U)
19056 #define I2C_TXDR_TXDATA_Msk          (0xFFU << I2C_TXDR_TXDATA_Pos)            /*!< 0x000000FF */
19057 #define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
19058 
19059 /**********************  Bit definition for I2C_HWCFGR register  ***************/
19060 #define I2C_HWCFGR_SMBUS_Pos  (0U)
19061 #define I2C_HWCFGR_SMBUS_Msk  (0xFU << I2C_HWCFGR_SMBUS_Pos)          /*!< 0x0000000F */
19062 #define I2C_HWCFGR_SMBUS      I2C_HWCFGR_SMBUS_Msk                    /*!< SMBus mode */
19063 #define I2C_HWCFGR_ASYN_Pos   (4U)
19064 #define I2C_HWCFGR_ASYN_Msk   (0xFU << I2C_HWCFGR_ASYN_Pos)           /*!< 0x000000F0 */
19065 #define I2C_HWCFGR_ASYN       I2C_HWCFGR_ASYN_Msk                     /*!< Independent kernel clock */
19066 #define I2C_HWCFGR_WKP_Pos    (8U)
19067 #define I2C_HWCFGR_WKP_Msk    (0xFU << I2C_HWCFGR_WKP_Pos)            /*!< 0x00000F00 */
19068 #define I2C_HWCFGR_WKP        I2C_HWCFGR_WKP_Msk                      /*!< Wakeup from Stop mode */
19069 
19070 /********************  Bit definition for I2C_VERR register***********************/
19071 #define I2C_VERR_MINREV_Pos          (0U)
19072 #define I2C_VERR_MINREV_Msk          (0xFU << I2C_VERR_MINREV_Pos)             /*!< 0x0000000F */
19073 #define I2C_VERR_MINREV              I2C_VERR_MINREV_Msk                       /*Minor Revision of the IP*/
19074 #define I2C_VERR_MAJREV_Pos          (4U)
19075 #define I2C_VERR_MAJREV_Msk          (0xFU << I2C_VERR_MAJREV_Pos)             /*!< 0x000000F0 */
19076 #define I2C_VERR_MAJREV              I2C_VERR_MAJREV_Msk                       /*Major Revision of the IP*/
19077 
19078 /********************  Bit definition for I2C_IPIDR register**********************/
19079 #define I2C_IPIDR_ID_Pos             (0U)
19080 #define I2C_IPIDR_ID_Msk             (0xFFFFFFFFU << I2C_IPIDR_ID_Pos)         /*!< 0xFFFFFFFF */
19081 #define I2C_IPIDR_ID                 I2C_IPIDR_ID_Msk                          /*IP Identifier*/
19082 
19083 /********************  Bit definition for I2C_SIDR register**********************/
19084 #define I2C_SIDR_SID_Pos             (0U)
19085 #define I2C_SIDR_SID_Msk             (0xFFFFFFFFU << I2C_SIDR_SID_Pos)         /*!< 0xFFFFFFFF */
19086 #define I2C_SIDR_SID                 I2C_SIDR_SID_Msk                          /*Size Identifier*/
19087 
19088 /******************************************************************************/
19089 /*                                                                            */
19090 /*                        Independent WATCHDOG (IWDG)                         */
19091 /*                                                                            */
19092 /******************************************************************************/
19093 /*******************  Bit definition for IWDG_KR register  ********************/
19094 #define IWDG_KR_KEY_Pos      (0U)
19095 #define IWDG_KR_KEY_Msk      (0xFFFFU << IWDG_KR_KEY_Pos)                      /*!< 0x0000FFFF */
19096 #define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */
19097 
19098 /*******************  Bit definition for IWDG_PR register  ********************/
19099 #define IWDG_PR_PR_Pos       (0U)
19100 #define IWDG_PR_PR_Msk       (0xFU << IWDG_PR_PR_Pos)                          /*!< 0x00000007 */
19101 #define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */
19102 #define IWDG_PR_PR_0         (0x1U << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */
19103 #define IWDG_PR_PR_1         (0x2U << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */
19104 #define IWDG_PR_PR_2         (0x4U << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */
19105 #define IWDG_PR_PR_3         (0x8U << IWDG_PR_PR_Pos)                          /*!< 0x00000008 */
19106 
19107 /*******************  Bit definition for IWDG_RLR register  *******************/
19108 #define IWDG_RLR_RL_Pos      (0U)
19109 #define IWDG_RLR_RL_Msk      (0xFFFU << IWDG_RLR_RL_Pos)                       /*!< 0x00000FFF */
19110 #define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */
19111 
19112 /*******************  Bit definition for IWDG_SR register  ********************/
19113 #define IWDG_SR_PVU_Pos      (0U)
19114 #define IWDG_SR_PVU_Msk      (0x1U << IWDG_SR_PVU_Pos)                         /*!< 0x00000001 */
19115 #define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
19116 #define IWDG_SR_RVU_Pos      (1U)
19117 #define IWDG_SR_RVU_Msk      (0x1U << IWDG_SR_RVU_Pos)                         /*!< 0x00000002 */
19118 #define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
19119 #define IWDG_SR_WVU_Pos      (2U)
19120 #define IWDG_SR_WVU_Msk      (0x1U << IWDG_SR_WVU_Pos)                         /*!< 0x00000004 */
19121 #define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
19122 #define IWDG_SR_EWU_Pos      (3U)
19123 #define IWDG_SR_EWU_Msk      (0x1U << IWDG_SR_EWU_Pos)                         /*!< 0x00000008 */
19124 #define IWDG_SR_EWU          IWDG_SR_EWU_Msk                                   /*!< Watchdog interrupt comparator value update */
19125 #define IWDG_SR_EWIF_Pos     (14U)
19126 #define IWDG_SR_EWIF_Msk     (0x1U << IWDG_SR_EWIF_Pos)                         /*!< 0x00004000 */
19127 #define IWDG_SR_EWIF         IWDG_SR_EWIF_Msk                                   /*!< Watchdog early interrupt flag */
19128 
19129 /*******************  Bit definition for IWDG_KR register  ********************/
19130 #define IWDG_WINR_WIN_Pos    (0U)
19131 #define IWDG_WINR_WIN_Msk    (0xFFFU << IWDG_WINR_WIN_Pos)                     /*!< 0x00000FFF */
19132 #define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
19133 
19134 /*******************  Bit definition for IWDG_EWCR register  ********************/
19135 #define IWDG_EWCR_EWIT_Pos   (0U)
19136 #define IWDG_EWCR_EWIT_Msk   (0xFFFU << IWDG_EWCR_EWIT_Pos)                     /*!< 0x00000FFF */
19137 #define IWDG_EWCR_EWIT       IWDG_EWCR_EWIT_Msk                                 /*!< Watchdog early wakeup comparator value */
19138 #define IWDG_EWCR_EWIC_Pos   (14U)
19139 #define IWDG_EWCR_EWIC_Msk   (0x1U << IWDG_EWCR_EWIC_Pos)                       /*!< 0x00004000 */
19140 #define IWDG_EWCR_EWIC       IWDG_EWCR_EWIC_Msk                                 /*!< Watchdog early interrupt acknowledge */
19141 #define IWDG_EWCR_EWIE_Pos   (15U)
19142 #define IWDG_EWCR_EWIE_Msk   (0x1U << IWDG_EWCR_EWIE_Pos)                       /*!< 0x00008000 */
19143 #define IWDG_EWCR_EWIE       IWDG_EWCR_EWIE_Msk                                 /*!< Watchdog early interrupt enable */
19144 
19145 /**********************  Bit definition for IWDG_HWCFGR register  ***************/
19146 #define IWDG_HWCFGR_WINDOW_Pos      (0U)
19147 #define IWDG_HWCFGR_WINDOW_Msk      (0xFU << IWDG_HWCFGR_WINDOW_Pos)            /*!< 0x0000000F */
19148 #define IWDG_HWCFGR_WINDOW          IWDG_HWCFGR_WINDOW_Msk                      /*!< Support of Window function */
19149 #define IWDG_HWCFGR_PR_DEFAULT_Pos  (4U)
19150 #define IWDG_HWCFGR_PR_DEFAULT_Msk  (0xFU << IWDG_HWCFGR_PR_DEFAULT_Pos)        /*!< 0x000000F0 */
19151 #define IWDG_HWCFGR_PR_DEFAULT      IWDG_HWCFGR_PR_DEFAULT_Msk                  /*!< Prescaler default value */
19152 
19153 /**********************  Bit definition for IWDG_VERR register  *****************/
19154 #define IWDG_VERR_MINREV_Pos      (0U)
19155 #define IWDG_VERR_MINREV_Msk      (0xFU << IWDG_VERR_MINREV_Pos)               /*!< 0x0000000F */
19156 #define IWDG_VERR_MINREV          IWDG_VERR_MINREV_Msk                         /*!< Minor Revision number */
19157 #define IWDG_VERR_MAJREV_Pos      (4U)
19158 #define IWDG_VERR_MAJREV_Msk      (0xFU << IWDG_VERR_MAJREV_Pos)               /*!< 0x000000F0 */
19159 #define IWDG_VERR_MAJREV          IWDG_VERR_MAJREV_Msk                         /*!< Major Revision number */
19160 
19161 /**********************  Bit definition for IWDG_IDR register  ****************/
19162 #define IWDG_IDR_IPID_Pos       (0U)
19163 #define IWDG_IDR_IPID_Msk       (0xFFFFFFFFU << IWDG_IDR_IPID_Pos)         /*!< 0xFFFFFFFF */
19164 #define IWDG_IDR_IPID           IWDG_IDR_IPID_Msk                          /*!< IP Identification */
19165 
19166 /**********************  Bit definition for IWDG_SIDR register  *****************/
19167 #define IWDG_SIDR_SID_Pos         (0U)
19168 #define IWDG_SIDR_SID_Msk         (0xFFFFFFFFU << IWDG_SIDR_SID_Pos)           /*!< 0xFFFFFFFF */
19169 #define IWDG_SIDR_SID             IWDG_SIDR_SID_Msk                            /*!< IP size identification */
19170 
19171 /******************************************************************************/
19172 /*                                                                            */
19173 /*                      LCD-TFT Display Controller (LTDC)                     */
19174 /*                                                                            */
19175 /******************************************************************************/
19176 
19177 /********************  Bit definition for LTDC_SSCR register  *****************/
19178 
19179 #define LTDC_SSCR_VSH_Pos            (0U)
19180 #define LTDC_SSCR_VSH_Msk            (0x7FFU << LTDC_SSCR_VSH_Pos)             /*!< 0x000007FF */
19181 #define LTDC_SSCR_VSH                LTDC_SSCR_VSH_Msk                         /*!< Vertical Synchronization Height  */
19182 #define LTDC_SSCR_HSW_Pos            (16U)
19183 #define LTDC_SSCR_HSW_Msk            (0xFFFU << LTDC_SSCR_HSW_Pos)             /*!< 0x0FFF0000 */
19184 #define LTDC_SSCR_HSW                LTDC_SSCR_HSW_Msk                         /*!< Horizontal Synchronization Width */
19185 
19186 /********************  Bit definition for LTDC_BPCR register  *****************/
19187 
19188 #define LTDC_BPCR_AVBP_Pos           (0U)
19189 #define LTDC_BPCR_AVBP_Msk           (0x7FFU << LTDC_BPCR_AVBP_Pos)            /*!< 0x000007FF */
19190 #define LTDC_BPCR_AVBP               LTDC_BPCR_AVBP_Msk                        /*!< Accumulated Vertical Back Porch   */
19191 #define LTDC_BPCR_AHBP_Pos           (16U)
19192 #define LTDC_BPCR_AHBP_Msk           (0xFFFU << LTDC_BPCR_AHBP_Pos)            /*!< 0x0FFF0000 */
19193 #define LTDC_BPCR_AHBP               LTDC_BPCR_AHBP_Msk                        /*!< Accumulated Horizontal Back Porch */
19194 
19195 /********************  Bit definition for LTDC_AWCR register  *****************/
19196 
19197 #define LTDC_AWCR_AAH_Pos            (0U)
19198 #define LTDC_AWCR_AAH_Msk            (0x7FFU << LTDC_AWCR_AAH_Pos)             /*!< 0x000007FF */
19199 #define LTDC_AWCR_AAH                LTDC_AWCR_AAH_Msk                         /*!< Accumulated Active heigh */
19200 #define LTDC_AWCR_AAW_Pos            (16U)
19201 #define LTDC_AWCR_AAW_Msk            (0xFFFU << LTDC_AWCR_AAW_Pos)             /*!< 0x0FFF0000 */
19202 #define LTDC_AWCR_AAW                LTDC_AWCR_AAW_Msk                         /*!< Accumulated Active Width */
19203 
19204 /********************  Bit definition for LTDC_TWCR register  *****************/
19205 
19206 #define LTDC_TWCR_TOTALH_Pos         (0U)
19207 #define LTDC_TWCR_TOTALH_Msk         (0x7FFU << LTDC_TWCR_TOTALH_Pos)          /*!< 0x000007FF */
19208 #define LTDC_TWCR_TOTALH             LTDC_TWCR_TOTALH_Msk                      /*!< Total Heigh */
19209 #define LTDC_TWCR_TOTALW_Pos         (16U)
19210 #define LTDC_TWCR_TOTALW_Msk         (0xFFFU << LTDC_TWCR_TOTALW_Pos)          /*!< 0x0FFF0000 */
19211 #define LTDC_TWCR_TOTALW             LTDC_TWCR_TOTALW_Msk                      /*!< Total Width */
19212 
19213 /********************  Bit definition for LTDC_GCR register  ******************/
19214 
19215 #define LTDC_GCR_LTDCEN_Pos          (0U)
19216 #define LTDC_GCR_LTDCEN_Msk          (0x1U << LTDC_GCR_LTDCEN_Pos)             /*!< 0x00000001 */
19217 #define LTDC_GCR_LTDCEN              LTDC_GCR_LTDCEN_Msk                       /*!< LCD-TFT controller enable bit       */
19218 #define LTDC_GCR_DBW_Pos             (4U)
19219 #define LTDC_GCR_DBW_Msk             (0x7U << LTDC_GCR_DBW_Pos)                /*!< 0x00000070 */
19220 #define LTDC_GCR_DBW                 LTDC_GCR_DBW_Msk                          /*!< Dither Blue Width                   */
19221 #define LTDC_GCR_DGW_Pos             (8U)
19222 #define LTDC_GCR_DGW_Msk             (0x7U << LTDC_GCR_DGW_Pos)                /*!< 0x00000700 */
19223 #define LTDC_GCR_DGW                 LTDC_GCR_DGW_Msk                          /*!< Dither Green Width                  */
19224 #define LTDC_GCR_DRW_Pos             (12U)
19225 #define LTDC_GCR_DRW_Msk             (0x7U << LTDC_GCR_DRW_Pos)                /*!< 0x00007000 */
19226 #define LTDC_GCR_DRW                 LTDC_GCR_DRW_Msk                          /*!< Dither Red Width                    */
19227 #define LTDC_GCR_DEN_Pos             (16U)
19228 #define LTDC_GCR_DEN_Msk             (0x1U << LTDC_GCR_DEN_Pos)                /*!< 0x00010000 */
19229 #define LTDC_GCR_DEN                 LTDC_GCR_DEN_Msk                          /*!< Dither Enable                       */
19230 #define LTDC_GCR_PCPOL_Pos           (28U)
19231 #define LTDC_GCR_PCPOL_Msk           (0x1U << LTDC_GCR_PCPOL_Pos)              /*!< 0x10000000 */
19232 #define LTDC_GCR_PCPOL               LTDC_GCR_PCPOL_Msk                        /*!< Pixel Clock Polarity                */
19233 #define LTDC_GCR_DEPOL_Pos           (29U)
19234 #define LTDC_GCR_DEPOL_Msk           (0x1U << LTDC_GCR_DEPOL_Pos)              /*!< 0x20000000 */
19235 #define LTDC_GCR_DEPOL               LTDC_GCR_DEPOL_Msk                        /*!< Data Enable Polarity                */
19236 #define LTDC_GCR_VSPOL_Pos           (30U)
19237 #define LTDC_GCR_VSPOL_Msk           (0x1U << LTDC_GCR_VSPOL_Pos)              /*!< 0x40000000 */
19238 #define LTDC_GCR_VSPOL               LTDC_GCR_VSPOL_Msk                        /*!< Vertical Synchronization Polarity   */
19239 #define LTDC_GCR_HSPOL_Pos           (31U)
19240 #define LTDC_GCR_HSPOL_Msk           (0x1U << LTDC_GCR_HSPOL_Pos)              /*!< 0x80000000 */
19241 #define LTDC_GCR_HSPOL               LTDC_GCR_HSPOL_Msk                        /*!< Horizontal Synchronization Polarity */
19242 
19243 
19244 /********************  Bit definition for LTDC_SRCR register  *****************/
19245 
19246 #define LTDC_SRCR_IMR_Pos            (0U)
19247 #define LTDC_SRCR_IMR_Msk            (0x1U << LTDC_SRCR_IMR_Pos)               /*!< 0x00000001 */
19248 #define LTDC_SRCR_IMR                LTDC_SRCR_IMR_Msk                         /*!< Immediate Reload         */
19249 #define LTDC_SRCR_VBR_Pos            (1U)
19250 #define LTDC_SRCR_VBR_Msk            (0x1U << LTDC_SRCR_VBR_Pos)               /*!< 0x00000002 */
19251 #define LTDC_SRCR_VBR                LTDC_SRCR_VBR_Msk                         /*!< Vertical Blanking Reload */
19252 
19253 /********************  Bit definition for LTDC_BCCR register  *****************/
19254 
19255 #define LTDC_BCCR_BCBLUE_Pos         (0U)
19256 #define LTDC_BCCR_BCBLUE_Msk         (0xFFU << LTDC_BCCR_BCBLUE_Pos)           /*!< 0x000000FF */
19257 #define LTDC_BCCR_BCBLUE             LTDC_BCCR_BCBLUE_Msk                      /*!< Background Blue value  */
19258 #define LTDC_BCCR_BCGREEN_Pos        (8U)
19259 #define LTDC_BCCR_BCGREEN_Msk        (0xFFU << LTDC_BCCR_BCGREEN_Pos)          /*!< 0x0000FF00 */
19260 #define LTDC_BCCR_BCGREEN            LTDC_BCCR_BCGREEN_Msk                     /*!< Background Green value */
19261 #define LTDC_BCCR_BCRED_Pos          (16U)
19262 #define LTDC_BCCR_BCRED_Msk          (0xFFU << LTDC_BCCR_BCRED_Pos)            /*!< 0x00FF0000 */
19263 #define LTDC_BCCR_BCRED              LTDC_BCCR_BCRED_Msk                       /*!< Background Red value   */
19264 
19265 /********************  Bit definition for LTDC_IER register  ******************/
19266 
19267 #define LTDC_IER_LIE_Pos             (0U)
19268 #define LTDC_IER_LIE_Msk             (0x1U << LTDC_IER_LIE_Pos)                /*!< 0x00000001 */
19269 #define LTDC_IER_LIE                 LTDC_IER_LIE_Msk                          /*!< Line Interrupt Enable            */
19270 #define LTDC_IER_FUIE_Pos            (1U)
19271 #define LTDC_IER_FUIE_Msk            (0x1U << LTDC_IER_FUIE_Pos)               /*!< 0x00000002 */
19272 #define LTDC_IER_FUIE                LTDC_IER_FUIE_Msk                         /*!< FIFO Underrun Interrupt Enable   */
19273 #define LTDC_IER_TERRIE_Pos          (2U)
19274 #define LTDC_IER_TERRIE_Msk          (0x1U << LTDC_IER_TERRIE_Pos)             /*!< 0x00000004 */
19275 #define LTDC_IER_TERRIE              LTDC_IER_TERRIE_Msk                       /*!< Transfer Error Interrupt Enable  */
19276 #define LTDC_IER_RRIE_Pos            (3U)
19277 #define LTDC_IER_RRIE_Msk            (0x1U << LTDC_IER_RRIE_Pos)               /*!< 0x00000008 */
19278 #define LTDC_IER_RRIE                LTDC_IER_RRIE_Msk                         /*!< Register Reload interrupt enable */
19279 
19280 /********************  Bit definition for LTDC_ISR register  ******************/
19281 
19282 #define LTDC_ISR_LIF_Pos             (0U)
19283 #define LTDC_ISR_LIF_Msk             (0x1U << LTDC_ISR_LIF_Pos)                /*!< 0x00000001 */
19284 #define LTDC_ISR_LIF                 LTDC_ISR_LIF_Msk                          /*!< Line Interrupt Flag */
19285 #define LTDC_ISR_FUIF_Pos            (1U)
19286 #define LTDC_ISR_FUIF_Msk            (0x1U << LTDC_ISR_FUIF_Pos)               /*!< 0x00000002 */
19287 #define LTDC_ISR_FUIF                LTDC_ISR_FUIF_Msk                         /*!< FIFO Underrun Interrupt Flag */
19288 #define LTDC_ISR_TERRIF_Pos          (2U)
19289 #define LTDC_ISR_TERRIF_Msk          (0x1U << LTDC_ISR_TERRIF_Pos)             /*!< 0x00000004 */
19290 #define LTDC_ISR_TERRIF              LTDC_ISR_TERRIF_Msk                       /*!< Transfer Error Interrupt Flag */
19291 #define LTDC_ISR_RRIF_Pos            (3U)
19292 #define LTDC_ISR_RRIF_Msk            (0x1U << LTDC_ISR_RRIF_Pos)               /*!< 0x00000008 */
19293 #define LTDC_ISR_RRIF                LTDC_ISR_RRIF_Msk                         /*!< Register Reload interrupt Flag */
19294 
19295 /********************  Bit definition for LTDC_ICR register  ******************/
19296 
19297 #define LTDC_ICR_CLIF_Pos            (0U)
19298 #define LTDC_ICR_CLIF_Msk            (0x1U << LTDC_ICR_CLIF_Pos)               /*!< 0x00000001 */
19299 #define LTDC_ICR_CLIF                LTDC_ICR_CLIF_Msk                         /*!< Clears the Line Interrupt Flag */
19300 #define LTDC_ICR_CFUIF_Pos           (1U)
19301 #define LTDC_ICR_CFUIF_Msk           (0x1U << LTDC_ICR_CFUIF_Pos)              /*!< 0x00000002 */
19302 #define LTDC_ICR_CFUIF               LTDC_ICR_CFUIF_Msk                        /*!< Clears the FIFO Underrun Interrupt Flag */
19303 #define LTDC_ICR_CTERRIF_Pos         (2U)
19304 #define LTDC_ICR_CTERRIF_Msk         (0x1U << LTDC_ICR_CTERRIF_Pos)            /*!< 0x00000004 */
19305 #define LTDC_ICR_CTERRIF             LTDC_ICR_CTERRIF_Msk                      /*!< Clears the Transfer Error Interrupt Flag */
19306 #define LTDC_ICR_CRRIF_Pos           (3U)
19307 #define LTDC_ICR_CRRIF_Msk           (0x1U << LTDC_ICR_CRRIF_Pos)              /*!< 0x00000008 */
19308 #define LTDC_ICR_CRRIF               LTDC_ICR_CRRIF_Msk                        /*!< Clears Register Reload interrupt Flag */
19309 
19310 /********************  Bit definition for LTDC_LIPCR register  ****************/
19311 
19312 #define LTDC_LIPCR_LIPOS_Pos         (0U)
19313 #define LTDC_LIPCR_LIPOS_Msk         (0x7FFU << LTDC_LIPCR_LIPOS_Pos)          /*!< 0x000007FF */
19314 #define LTDC_LIPCR_LIPOS             LTDC_LIPCR_LIPOS_Msk                      /*!< Line Interrupt Position */
19315 
19316 /********************  Bit definition for LTDC_CPSR register  *****************/
19317 
19318 #define LTDC_CPSR_CYPOS_Pos          (0U)
19319 #define LTDC_CPSR_CYPOS_Msk          (0xFFFFU << LTDC_CPSR_CYPOS_Pos)          /*!< 0x0000FFFF */
19320 #define LTDC_CPSR_CYPOS              LTDC_CPSR_CYPOS_Msk                       /*!< Current Y Position */
19321 #define LTDC_CPSR_CXPOS_Pos          (16U)
19322 #define LTDC_CPSR_CXPOS_Msk          (0xFFFFU << LTDC_CPSR_CXPOS_Pos)          /*!< 0xFFFF0000 */
19323 #define LTDC_CPSR_CXPOS              LTDC_CPSR_CXPOS_Msk                       /*!< Current X Position */
19324 
19325 /********************  Bit definition for LTDC_CDSR register  *****************/
19326 
19327 #define LTDC_CDSR_VDES_Pos           (0U)
19328 #define LTDC_CDSR_VDES_Msk           (0x1U << LTDC_CDSR_VDES_Pos)              /*!< 0x00000001 */
19329 #define LTDC_CDSR_VDES               LTDC_CDSR_VDES_Msk                        /*!< Vertical Data Enable Status       */
19330 #define LTDC_CDSR_HDES_Pos           (1U)
19331 #define LTDC_CDSR_HDES_Msk           (0x1U << LTDC_CDSR_HDES_Pos)              /*!< 0x00000002 */
19332 #define LTDC_CDSR_HDES               LTDC_CDSR_HDES_Msk                        /*!< Horizontal Data Enable Status     */
19333 #define LTDC_CDSR_VSYNCS_Pos         (2U)
19334 #define LTDC_CDSR_VSYNCS_Msk         (0x1U << LTDC_CDSR_VSYNCS_Pos)            /*!< 0x00000004 */
19335 #define LTDC_CDSR_VSYNCS             LTDC_CDSR_VSYNCS_Msk                      /*!< Vertical Synchronization Status   */
19336 #define LTDC_CDSR_HSYNCS_Pos         (3U)
19337 #define LTDC_CDSR_HSYNCS_Msk         (0x1U << LTDC_CDSR_HSYNCS_Pos)            /*!< 0x00000008 */
19338 #define LTDC_CDSR_HSYNCS             LTDC_CDSR_HSYNCS_Msk                      /*!< Horizontal Synchronization Status */
19339 
19340 /********************  Bit definition for LTDC_LxCR register  *****************/
19341 
19342 #define LTDC_LxCR_LEN_Pos            (0U)
19343 #define LTDC_LxCR_LEN_Msk            (0x1U << LTDC_LxCR_LEN_Pos)               /*!< 0x00000001 */
19344 #define LTDC_LxCR_LEN                LTDC_LxCR_LEN_Msk                         /*!< Layer Enable              */
19345 #define LTDC_LxCR_COLKEN_Pos         (1U)
19346 #define LTDC_LxCR_COLKEN_Msk         (0x1U << LTDC_LxCR_COLKEN_Pos)            /*!< 0x00000002 */
19347 #define LTDC_LxCR_COLKEN             LTDC_LxCR_COLKEN_Msk                      /*!< Color Keying Enable       */
19348 #define LTDC_LxCR_CLUTEN_Pos         (4U)
19349 #define LTDC_LxCR_CLUTEN_Msk         (0x1U << LTDC_LxCR_CLUTEN_Pos)            /*!< 0x00000010 */
19350 #define LTDC_LxCR_CLUTEN             LTDC_LxCR_CLUTEN_Msk                      /*!< Color Lockup Table Enable */
19351 
19352 /********************  Bit definition for LTDC_LxWHPCR register  **************/
19353 
19354 #define LTDC_LxWHPCR_WHSTPOS_Pos     (0U)
19355 #define LTDC_LxWHPCR_WHSTPOS_Msk     (0xFFFU << LTDC_LxWHPCR_WHSTPOS_Pos)      /*!< 0x00000FFF */
19356 #define LTDC_LxWHPCR_WHSTPOS         LTDC_LxWHPCR_WHSTPOS_Msk                  /*!< Window Horizontal Start Position */
19357 #define LTDC_LxWHPCR_WHSPPOS_Pos     (16U)
19358 #define LTDC_LxWHPCR_WHSPPOS_Msk     (0xFFFFU << LTDC_LxWHPCR_WHSPPOS_Pos)     /*!< 0xFFFF0000 */
19359 #define LTDC_LxWHPCR_WHSPPOS         LTDC_LxWHPCR_WHSPPOS_Msk                  /*!< Window Horizontal Stop Position  */
19360 
19361 /********************  Bit definition for LTDC_LxWVPCR register  **************/
19362 
19363 #define LTDC_LxWVPCR_WVSTPOS_Pos     (0U)
19364 #define LTDC_LxWVPCR_WVSTPOS_Msk     (0xFFFU << LTDC_LxWVPCR_WVSTPOS_Pos)      /*!< 0x00000FFF */
19365 #define LTDC_LxWVPCR_WVSTPOS         LTDC_LxWVPCR_WVSTPOS_Msk                  /*!< Window Vertical Start Position */
19366 #define LTDC_LxWVPCR_WVSPPOS_Pos     (16U)
19367 #define LTDC_LxWVPCR_WVSPPOS_Msk     (0xFFFFU << LTDC_LxWVPCR_WVSPPOS_Pos)     /*!< 0xFFFF0000 */
19368 #define LTDC_LxWVPCR_WVSPPOS         LTDC_LxWVPCR_WVSPPOS_Msk                  /*!< Window Vertical Stop Position  */
19369 
19370 /********************  Bit definition for LTDC_LxCKCR register  ***************/
19371 
19372 #define LTDC_LxCKCR_CKBLUE_Pos       (0U)
19373 #define LTDC_LxCKCR_CKBLUE_Msk       (0xFFU << LTDC_LxCKCR_CKBLUE_Pos)         /*!< 0x000000FF */
19374 #define LTDC_LxCKCR_CKBLUE           LTDC_LxCKCR_CKBLUE_Msk                    /*!< Color Key Blue value  */
19375 #define LTDC_LxCKCR_CKGREEN_Pos      (8U)
19376 #define LTDC_LxCKCR_CKGREEN_Msk      (0xFFU << LTDC_LxCKCR_CKGREEN_Pos)        /*!< 0x0000FF00 */
19377 #define LTDC_LxCKCR_CKGREEN          LTDC_LxCKCR_CKGREEN_Msk                   /*!< Color Key Green value */
19378 #define LTDC_LxCKCR_CKRED_Pos        (16U)
19379 #define LTDC_LxCKCR_CKRED_Msk        (0xFFU << LTDC_LxCKCR_CKRED_Pos)          /*!< 0x00FF0000 */
19380 #define LTDC_LxCKCR_CKRED            LTDC_LxCKCR_CKRED_Msk                     /*!< Color Key Red value   */
19381 
19382 /********************  Bit definition for LTDC_LxPFCR register  ***************/
19383 
19384 #define LTDC_LxPFCR_PF_Pos           (0U)
19385 #define LTDC_LxPFCR_PF_Msk           (0x7U << LTDC_LxPFCR_PF_Pos)              /*!< 0x00000007 */
19386 #define LTDC_LxPFCR_PF               LTDC_LxPFCR_PF_Msk                        /*!< Pixel Format */
19387 
19388 /********************  Bit definition for LTDC_LxCACR register  ***************/
19389 
19390 #define LTDC_LxCACR_CONSTA_Pos       (0U)
19391 #define LTDC_LxCACR_CONSTA_Msk       (0xFFU << LTDC_LxCACR_CONSTA_Pos)         /*!< 0x000000FF */
19392 #define LTDC_LxCACR_CONSTA           LTDC_LxCACR_CONSTA_Msk                    /*!< Constant Alpha */
19393 
19394 /********************  Bit definition for LTDC_LxDCCR register  ***************/
19395 
19396 #define LTDC_LxDCCR_DCBLUE_Pos       (0U)
19397 #define LTDC_LxDCCR_DCBLUE_Msk       (0xFFU << LTDC_LxDCCR_DCBLUE_Pos)         /*!< 0x000000FF */
19398 #define LTDC_LxDCCR_DCBLUE           LTDC_LxDCCR_DCBLUE_Msk                    /*!< Default Color Blue  */
19399 #define LTDC_LxDCCR_DCGREEN_Pos      (8U)
19400 #define LTDC_LxDCCR_DCGREEN_Msk      (0xFFU << LTDC_LxDCCR_DCGREEN_Pos)        /*!< 0x0000FF00 */
19401 #define LTDC_LxDCCR_DCGREEN          LTDC_LxDCCR_DCGREEN_Msk                   /*!< Default Color Green */
19402 #define LTDC_LxDCCR_DCRED_Pos        (16U)
19403 #define LTDC_LxDCCR_DCRED_Msk        (0xFFU << LTDC_LxDCCR_DCRED_Pos)          /*!< 0x00FF0000 */
19404 #define LTDC_LxDCCR_DCRED            LTDC_LxDCCR_DCRED_Msk                     /*!< Default Color Red   */
19405 #define LTDC_LxDCCR_DCALPHA_Pos      (24U)
19406 #define LTDC_LxDCCR_DCALPHA_Msk      (0xFFU << LTDC_LxDCCR_DCALPHA_Pos)        /*!< 0xFF000000 */
19407 #define LTDC_LxDCCR_DCALPHA          LTDC_LxDCCR_DCALPHA_Msk                   /*!< Default Color Alpha */
19408 
19409 /********************  Bit definition for LTDC_LxBFCR register  ***************/
19410 
19411 #define LTDC_LxBFCR_BF2_Pos          (0U)
19412 #define LTDC_LxBFCR_BF2_Msk          (0x7U << LTDC_LxBFCR_BF2_Pos)             /*!< 0x00000007 */
19413 #define LTDC_LxBFCR_BF2              LTDC_LxBFCR_BF2_Msk                       /*!< Blending Factor 2 */
19414 #define LTDC_LxBFCR_BF1_Pos          (8U)
19415 #define LTDC_LxBFCR_BF1_Msk          (0x7U << LTDC_LxBFCR_BF1_Pos)             /*!< 0x00000700 */
19416 #define LTDC_LxBFCR_BF1              LTDC_LxBFCR_BF1_Msk                       /*!< Blending Factor 1 */
19417 
19418 /********************  Bit definition for LTDC_LxCFBAR register  **************/
19419 
19420 #define LTDC_LxCFBAR_CFBADD_Pos      (0U)
19421 #define LTDC_LxCFBAR_CFBADD_Msk      (0xFFFFFFFFU << LTDC_LxCFBAR_CFBADD_Pos)  /*!< 0xFFFFFFFF */
19422 #define LTDC_LxCFBAR_CFBADD          LTDC_LxCFBAR_CFBADD_Msk                   /*!< Color Frame Buffer Start Address */
19423 
19424 /********************  Bit definition for LTDC_LxCFBLR register  **************/
19425 
19426 #define LTDC_LxCFBLR_CFBLL_Pos       (0U)
19427 #define LTDC_LxCFBLR_CFBLL_Msk       (0x1FFFU << LTDC_LxCFBLR_CFBLL_Pos)       /*!< 0x00001FFF */
19428 #define LTDC_LxCFBLR_CFBLL           LTDC_LxCFBLR_CFBLL_Msk                    /*!< Color Frame Buffer Line Length    */
19429 #define LTDC_LxCFBLR_CFBP_Pos        (16U)
19430 #define LTDC_LxCFBLR_CFBP_Msk        (0x1FFFU << LTDC_LxCFBLR_CFBP_Pos)        /*!< 0x1FFF0000 */
19431 #define LTDC_LxCFBLR_CFBP            LTDC_LxCFBLR_CFBP_Msk                     /*!< Color Frame Buffer Pitch in bytes */
19432 
19433 /********************  Bit definition for LTDC_LxCFBLNR register  *************/
19434 
19435 #define LTDC_LxCFBLNR_CFBLNBR_Pos    (0U)
19436 #define LTDC_LxCFBLNR_CFBLNBR_Msk    (0x7FFU << LTDC_LxCFBLNR_CFBLNBR_Pos)     /*!< 0x000007FF */
19437 #define LTDC_LxCFBLNR_CFBLNBR        LTDC_LxCFBLNR_CFBLNBR_Msk                 /*!< Frame Buffer Line Number */
19438 
19439 /********************  Bit definition for LTDC_LxCLUTWR register  *************/
19440 
19441 #define LTDC_LxCLUTWR_BLUE_Pos       (0U)
19442 #define LTDC_LxCLUTWR_BLUE_Msk       (0xFFU << LTDC_LxCLUTWR_BLUE_Pos)         /*!< 0x000000FF */
19443 #define LTDC_LxCLUTWR_BLUE           LTDC_LxCLUTWR_BLUE_Msk                    /*!< Blue value   */
19444 #define LTDC_LxCLUTWR_GREEN_Pos      (8U)
19445 #define LTDC_LxCLUTWR_GREEN_Msk      (0xFFU << LTDC_LxCLUTWR_GREEN_Pos)        /*!< 0x0000FF00 */
19446 #define LTDC_LxCLUTWR_GREEN          LTDC_LxCLUTWR_GREEN_Msk                   /*!< Green value  */
19447 #define LTDC_LxCLUTWR_RED_Pos        (16U)
19448 #define LTDC_LxCLUTWR_RED_Msk        (0xFFU << LTDC_LxCLUTWR_RED_Pos)          /*!< 0x00FF0000 */
19449 #define LTDC_LxCLUTWR_RED            LTDC_LxCLUTWR_RED_Msk                     /*!< Red value    */
19450 #define LTDC_LxCLUTWR_CLUTADD_Pos    (24U)
19451 #define LTDC_LxCLUTWR_CLUTADD_Msk    (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos)      /*!< 0xFF000000 */
19452 #define LTDC_LxCLUTWR_CLUTADD        LTDC_LxCLUTWR_CLUTADD_Msk                 /*!< CLUT address */
19453 
19454 /******************************************************************************/
19455 /*                                                                            */
19456 /*         Inter-Processor Communication Controller (IPCC)                    */
19457 /*                                                                            */
19458 /******************************************************************************/
19459 
19460 /**********************  Bit definition for IPCC_C1CR register  ***************/
19461 #define IPCC_C1CR_RXOIE_Pos      (0U)
19462 #define IPCC_C1CR_RXOIE_Msk      (0x1U << IPCC_C1CR_RXOIE_Pos)                 /*!< 0x00000001 */
19463 #define IPCC_C1CR_RXOIE          IPCC_C1CR_RXOIE_Msk                           /*!< Processor M4 Receive channel occupied interrupt enable */
19464 #define IPCC_C1CR_TXFIE_Pos      (16U)
19465 #define IPCC_C1CR_TXFIE_Msk      (0x1U << IPCC_C1CR_TXFIE_Pos)                 /*!< 0x00010000 */
19466 #define IPCC_C1CR_TXFIE          IPCC_C1CR_TXFIE_Msk                           /*!< Processor M4 Transmit channel free interrupt enable */
19467 
19468 /**********************  Bit definition for IPCC_C1MR register  **************/
19469 #define IPCC_C1MR_CH1OM_Pos      (0U)
19470 #define IPCC_C1MR_CH1OM_Msk      (0x1U << IPCC_C1MR_CH1OM_Pos)                 /*!< 0x00000001 */
19471 #define IPCC_C1MR_CH1OM          IPCC_C1MR_CH1OM_Msk                           /*!< M4 Channel1 occupied interrupt mask */
19472 #define IPCC_C1MR_CH2OM_Pos      (1U)
19473 #define IPCC_C1MR_CH2OM_Msk      (0x1U << IPCC_C1MR_CH2OM_Pos)                 /*!< 0x00000002 */
19474 #define IPCC_C1MR_CH2OM          IPCC_C1MR_CH2OM_Msk                           /*!< M4 Channel2 occupied interrupt mask */
19475 #define IPCC_C1MR_CH3OM_Pos      (2U)
19476 #define IPCC_C1MR_CH3OM_Msk      (0x1U << IPCC_C1MR_CH3OM_Pos)                 /*!< 0x00000004 */
19477 #define IPCC_C1MR_CH3OM          IPCC_C1MR_CH3OM_Msk                           /*!< M4 Channel3 occupied interrupt mask */
19478 #define IPCC_C1MR_CH4OM_Pos      (3U)
19479 #define IPCC_C1MR_CH4OM_Msk      (0x1U << IPCC_C1MR_CH4OM_Pos)                 /*!< 0x00000008 */
19480 #define IPCC_C1MR_CH4OM          IPCC_C1MR_CH4OM_Msk                           /*!< M4 Channel4 occupied interrupt mask */
19481 #define IPCC_C1MR_CH5OM_Pos      (4U)
19482 #define IPCC_C1MR_CH5OM_Msk      (0x1U << IPCC_C1MR_CH5OM_Pos)                 /*!< 0x00000010 */
19483 #define IPCC_C1MR_CH5OM          IPCC_C1MR_CH5OM_Msk                           /*!< M4 Channel5 occupied interrupt mask */
19484 #define IPCC_C1MR_CH6OM_Pos      (5U)
19485 #define IPCC_C1MR_CH6OM_Msk      (0x1U << IPCC_C1MR_CH6OM_Pos)                 /*!< 0x00000020 */
19486 #define IPCC_C1MR_CH6OM          IPCC_C1MR_CH6OM_Msk                           /*!< M4 Channel6 occupied interrupt mask */
19487 
19488 #define IPCC_C1MR_CH1FM_Pos      (16U)
19489 #define IPCC_C1MR_CH1FM_Msk      (0x1U << IPCC_C1MR_CH1FM_Pos)                 /*!< 0x00010000 */
19490 #define IPCC_C1MR_CH1FM          IPCC_C1MR_CH1FM_Msk                           /*!< M4 Transmit Channel1 free interrupt mask */
19491 #define IPCC_C1MR_CH2FM_Pos      (17U)
19492 #define IPCC_C1MR_CH2FM_Msk      (0x1U << IPCC_C1MR_CH2FM_Pos)                 /*!< 0x00020000 */
19493 #define IPCC_C1MR_CH2FM          IPCC_C1MR_CH2FM_Msk                           /*!< M4 Transmit Channel2 free interrupt mask */
19494 #define IPCC_C1MR_CH3FM_Pos      (18U)
19495 #define IPCC_C1MR_CH3FM_Msk      (0x1U << IPCC_C1MR_CH3FM_Pos)                 /*!< 0x00040000 */
19496 #define IPCC_C1MR_CH3FM          IPCC_C1MR_CH3FM_Msk                           /*!< M4 Transmit Channel3 free interrupt mask */
19497 #define IPCC_C1MR_CH4FM_Pos      (19U)
19498 #define IPCC_C1MR_CH4FM_Msk      (0x1U << IPCC_C1MR_CH4FM_Pos)                 /*!< 0x00080000 */
19499 #define IPCC_C1MR_CH4FM          IPCC_C1MR_CH4FM_Msk                           /*!< M4 Transmit Channel4 free interrupt mask */
19500 #define IPCC_C1MR_CH5FM_Pos      (20U)
19501 #define IPCC_C1MR_CH5FM_Msk      (0x1U << IPCC_C1MR_CH5FM_Pos)                 /*!< 0x00100000 */
19502 #define IPCC_C1MR_CH5FM          IPCC_C1MR_CH5FM_Msk                           /*!< M4 Transmit Channel5 free interrupt mask */
19503 #define IPCC_C1MR_CH6FM_Pos      (21U)
19504 #define IPCC_C1MR_CH6FM_Msk      (0x1U << IPCC_C1MR_CH6FM_Pos)                 /*!< 0x00200000 */
19505 #define IPCC_C1MR_CH6FM          IPCC_C1MR_CH6FM_Msk                           /*!< M4 Transmit Channel6 free interrupt mask */
19506 
19507 /**********************  Bit definition for IPCC_C1SCR register  ***************/
19508 #define IPCC_C1SCR_CH1C_Pos      (0U)
19509 #define IPCC_C1SCR_CH1C_Msk      (0x1U << IPCC_C1SCR_CH1C_Pos)                 /*!< 0x00000001 */
19510 #define IPCC_C1SCR_CH1C          IPCC_C1SCR_CH1C_Msk                           /*!< M4 receive Channel1 status clear */
19511 #define IPCC_C1SCR_CH2C_Pos      (1U)
19512 #define IPCC_C1SCR_CH2C_Msk      (0x1U << IPCC_C1SCR_CH2C_Pos)                 /*!< 0x00000002 */
19513 #define IPCC_C1SCR_CH2C          IPCC_C1SCR_CH2C_Msk                           /*!< M4 receive Channel2 status clear */
19514 #define IPCC_C1SCR_CH3C_Pos      (2U)
19515 #define IPCC_C1SCR_CH3C_Msk      (0x1U << IPCC_C1SCR_CH3C_Pos)                 /*!< 0x00000004 */
19516 #define IPCC_C1SCR_CH3C          IPCC_C1SCR_CH3C_Msk                           /*!< M4 receive Channel3 status clear */
19517 #define IPCC_C1SCR_CH4C_Pos      (3U)
19518 #define IPCC_C1SCR_CH4C_Msk      (0x1U << IPCC_C1SCR_CH4C_Pos)                 /*!< 0x00000008 */
19519 #define IPCC_C1SCR_CH4C          IPCC_C1SCR_CH4C_Msk                           /*!< M4 receive Channel4 status clear */
19520 #define IPCC_C1SCR_CH5C_Pos      (4U)
19521 #define IPCC_C1SCR_CH5C_Msk      (0x1U << IPCC_C1SCR_CH5C_Pos)                 /*!< 0x00000010 */
19522 #define IPCC_C1SCR_CH5C          IPCC_C1SCR_CH5C_Msk                           /*!< M4 receive Channel5 status clear */
19523 #define IPCC_C1SCR_CH6C_Pos      (5U)
19524 #define IPCC_C1SCR_CH6C_Msk      (0x1U << IPCC_C1SCR_CH6C_Pos)                 /*!< 0x00000020 */
19525 #define IPCC_C1SCR_CH6C          IPCC_C1SCR_CH6C_Msk                           /*!< M4 receive Channel6 status clear */
19526 
19527 #define IPCC_C1SCR_CH1S_Pos      (16U)
19528 #define IPCC_C1SCR_CH1S_Msk      (0x1U << IPCC_C1SCR_CH1S_Pos)                 /*!< 0x00010000 */
19529 #define IPCC_C1SCR_CH1S          IPCC_C1SCR_CH1S_Msk                           /*!< M4 transmit Channel1 status set */
19530 #define IPCC_C1SCR_CH2S_Pos      (17U)
19531 #define IPCC_C1SCR_CH2S_Msk      (0x1U << IPCC_C1SCR_CH2S_Pos)                 /*!< 0x00020000 */
19532 #define IPCC_C1SCR_CH2S          IPCC_C1SCR_CH2S_Msk                           /*!< M4 transmit Channel2 status set  */
19533 #define IPCC_C1SCR_CH3S_Pos      (18U)
19534 #define IPCC_C1SCR_CH3S_Msk      (0x1U << IPCC_C1SCR_CH3S_Pos)                 /*!< 0x00040000 */
19535 #define IPCC_C1SCR_CH3S          IPCC_C1SCR_CH3S_Msk                           /*!< M4 transmit Channel3 status set  */
19536 #define IPCC_C1SCR_CH4S_Pos      (19U)
19537 #define IPCC_C1SCR_CH4S_Msk      (0x1U << IPCC_C1SCR_CH4S_Pos)                 /*!< 0x00080000 */
19538 #define IPCC_C1SCR_CH4S          IPCC_C1SCR_CH4S_Msk                           /*!< M4 transmit Channel4 status set  */
19539 #define IPCC_C1SCR_CH5S_Pos      (20U)
19540 #define IPCC_C1SCR_CH5S_Msk      (0x1U << IPCC_C1SCR_CH5S_Pos)                 /*!< 0x00100000 */
19541 #define IPCC_C1SCR_CH5S          IPCC_C1SCR_CH5S_Msk                           /*!< M4 transmit Channel5 status set  */
19542 #define IPCC_C1SCR_CH6S_Pos      (21U)
19543 #define IPCC_C1SCR_CH6S_Msk      (0x1U << IPCC_C1SCR_CH6S_Pos)                 /*!< 0x00200000 */
19544 #define IPCC_C1SCR_CH6S          IPCC_C1SCR_CH6S_Msk                           /*!< M4 transmit Channel6 status set  */
19545 
19546 /**********************  Bit definition for IPCC_C1TOC2SR register  ***************/
19547 #define IPCC_C1TOC2SR_CH1F_Pos    (0U)
19548 #define IPCC_C1TOC2SR_CH1F_Msk    (0x1U << IPCC_C1TOC2SR_CH1F_Pos)             /*!< 0x00000001 */
19549 #define IPCC_C1TOC2SR_CH1F        IPCC_C1TOC2SR_CH1F_Msk                       /*!< M4 transmit to M4 receive Channel1 status flag before masking */
19550 #define IPCC_C1TOC2SR_CH2F_Pos    (1U)
19551 #define IPCC_C1TOC2SR_CH2F_Msk    (0x1U << IPCC_C1TOC2SR_CH2F_Pos)             /*!< 0x00000002 */
19552 #define IPCC_C1TOC2SR_CH2F        IPCC_C1TOC2SR_CH2F_Msk                       /*!< M4 transmit to M4 receive Channel2 status flag before masking */
19553 #define IPCC_C1TOC2SR_CH3F_Pos    (2U)
19554 #define IPCC_C1TOC2SR_CH3F_Msk    (0x1U << IPCC_C1TOC2SR_CH3F_Pos)             /*!< 0x00000004 */
19555 #define IPCC_C1TOC2SR_CH3F        IPCC_C1TOC2SR_CH3F_Msk                       /*!< M4 transmit to M4 receive Channel3 status flag before masking */
19556 #define IPCC_C1TOC2SR_CH4F_Pos    (3U)
19557 #define IPCC_C1TOC2SR_CH4F_Msk    (0x1U << IPCC_C1TOC2SR_CH4F_Pos)             /*!< 0x00000008 */
19558 #define IPCC_C1TOC2SR_CH4F        IPCC_C1TOC2SR_CH4F_Msk                       /*!< M4 transmit to M4 receive Channel4 status flag before masking */
19559 #define IPCC_C1TOC2SR_CH5F_Pos    (4U)
19560 #define IPCC_C1TOC2SR_CH5F_Msk    (0x1U << IPCC_C1TOC2SR_CH5F_Pos)             /*!< 0x00000010 */
19561 #define IPCC_C1TOC2SR_CH5F        IPCC_C1TOC2SR_CH5F_Msk                       /*!< M4 transmit to M4 receive Channel5 status flag before masking */
19562 #define IPCC_C1TOC2SR_CH6F_Pos    (5U)
19563 #define IPCC_C1TOC2SR_CH6F_Msk    (0x1U << IPCC_C1TOC2SR_CH6F_Pos)             /*!< 0x00000020 */
19564 #define IPCC_C1TOC2SR_CH6F        IPCC_C1TOC2SR_CH6F_Msk                       /*!< M4 transmit to M4 receive Channel6 status flag before masking */
19565 
19566 /**********************  Bit definition for IPCC_C2CR register  ***************/
19567 #define IPCC_C2CR_RXOIE_Pos      (0U)
19568 #define IPCC_C2CR_RXOIE_Msk      (0x1U << IPCC_C2CR_RXOIE_Pos)                 /*!< 0x00000001 */
19569 #define IPCC_C2CR_RXOIE          IPCC_C2CR_RXOIE_Msk                           /*!< Processor M0+ Receive channel occupied interrupt enable */
19570 #define IPCC_C2CR_TXFIE_Pos      (16U)
19571 #define IPCC_C2CR_TXFIE_Msk      (0x1U << IPCC_C2CR_TXFIE_Pos)                 /*!< 0x00010000 */
19572 #define IPCC_C2CR_TXFIE          IPCC_C2CR_TXFIE_Msk                           /*!< Processor M0+ Transmit channel free interrupt enable */
19573 
19574 /**********************  Bit definition for IPCC_C2MR register  ***************/
19575 #define IPCC_C2MR_CH1OM_Pos      (0U)
19576 #define IPCC_C2MR_CH1OM_Msk      (0x1U << IPCC_C2MR_CH1OM_Pos)                 /*!< 0x00000001 */
19577 #define IPCC_C2MR_CH1OM          IPCC_C2MR_CH1OM_Msk                           /*!< M0+ Channel1 occupied interrupt mask */
19578 #define IPCC_C2MR_CH2OM_Pos      (1U)
19579 #define IPCC_C2MR_CH2OM_Msk      (0x1U << IPCC_C2MR_CH2OM_Pos)                 /*!< 0x00000002 */
19580 #define IPCC_C2MR_CH2OM          IPCC_C2MR_CH2OM_Msk                           /*!< M0+ Channel2 occupied interrupt mask */
19581 #define IPCC_C2MR_CH3OM_Pos      (2U)
19582 #define IPCC_C2MR_CH3OM_Msk      (0x1U << IPCC_C2MR_CH3OM_Pos)                 /*!< 0x00000004 */
19583 #define IPCC_C2MR_CH3OM          IPCC_C2MR_CH3OM_Msk                           /*!< M0+ Channel3 occupied interrupt mask */
19584 #define IPCC_C2MR_CH4OM_Pos      (3U)
19585 #define IPCC_C2MR_CH4OM_Msk      (0x1U << IPCC_C2MR_CH4OM_Pos)                 /*!< 0x00000008 */
19586 #define IPCC_C2MR_CH4OM          IPCC_C2MR_CH4OM_Msk                           /*!< M0+ Channel4 occupied interrupt mask */
19587 #define IPCC_C2MR_CH5OM_Pos      (4U)
19588 #define IPCC_C2MR_CH5OM_Msk      (0x1U << IPCC_C2MR_CH5OM_Pos)                 /*!< 0x00000010 */
19589 #define IPCC_C2MR_CH5OM          IPCC_C2MR_CH5OM_Msk                           /*!< M0+ Channel5 occupied interrupt mask */
19590 #define IPCC_C2MR_CH6OM_Pos      (5U)
19591 #define IPCC_C2MR_CH6OM_Msk      (0x1U << IPCC_C2MR_CH6OM_Pos)                 /*!< 0x00000020 */
19592 #define IPCC_C2MR_CH6OM          IPCC_C2MR_CH6OM_Msk                           /*!< M0+ Channel6 occupied interrupt mask */
19593 
19594 #define IPCC_C2MR_CH1FM_Pos      (16U)
19595 #define IPCC_C2MR_CH1FM_Msk      (0x1U << IPCC_C2MR_CH1FM_Pos)                 /*!< 0x00010000 */
19596 #define IPCC_C2MR_CH1FM          IPCC_C2MR_CH1FM_Msk                           /*!< M0+ Transmit Channel1 free interrupt mask */
19597 #define IPCC_C2MR_CH2FM_Pos      (17U)
19598 #define IPCC_C2MR_CH2FM_Msk      (0x1U << IPCC_C2MR_CH2FM_Pos)                 /*!< 0x00020000 */
19599 #define IPCC_C2MR_CH2FM          IPCC_C2MR_CH2FM_Msk                           /*!< M0+ Transmit Channel2 free interrupt mask */
19600 #define IPCC_C2MR_CH3FM_Pos      (18U)
19601 #define IPCC_C2MR_CH3FM_Msk      (0x1U << IPCC_C2MR_CH3FM_Pos)                 /*!< 0x00040000 */
19602 #define IPCC_C2MR_CH3FM          IPCC_C2MR_CH3FM_Msk                           /*!< M0+ Transmit Channel3 free interrupt mask */
19603 #define IPCC_C2MR_CH4FM_Pos      (19U)
19604 #define IPCC_C2MR_CH4FM_Msk      (0x1U << IPCC_C2MR_CH4FM_Pos)                 /*!< 0x00080000 */
19605 #define IPCC_C2MR_CH4FM          IPCC_C2MR_CH4FM_Msk                           /*!< M0+ Transmit Channel4 free interrupt mask */
19606 #define IPCC_C2MR_CH5FM_Pos      (20U)
19607 #define IPCC_C2MR_CH5FM_Msk      (0x1U << IPCC_C2MR_CH5FM_Pos)                 /*!< 0x00100000 */
19608 #define IPCC_C2MR_CH5FM          IPCC_C2MR_CH5FM_Msk                           /*!< M0+ Transmit Channel5 free interrupt mask */
19609 #define IPCC_C2MR_CH6FM_Pos      (21U)
19610 #define IPCC_C2MR_CH6FM_Msk      (0x1U << IPCC_C2MR_CH6FM_Pos)                 /*!< 0x00200000 */
19611 #define IPCC_C2MR_CH6FM          IPCC_C2MR_CH6FM_Msk                           /*!< M0+ Transmit Channel6 free interrupt mask */
19612 
19613 /**********************  Bit definition for IPCC_C2SCR register  ***************/
19614 #define IPCC_C2SCR_CH1C_Pos      (0U)
19615 #define IPCC_C2SCR_CH1C_Msk      (0x1U << IPCC_C2SCR_CH1C_Pos)                 /*!< 0x00000001 */
19616 #define IPCC_C2SCR_CH1C          IPCC_C2SCR_CH1C_Msk                           /*!< M0+ receive Channel1 status clear */
19617 #define IPCC_C2SCR_CH2C_Pos      (1U)
19618 #define IPCC_C2SCR_CH2C_Msk      (0x1U << IPCC_C2SCR_CH2C_Pos)                 /*!< 0x00000002 */
19619 #define IPCC_C2SCR_CH2C          IPCC_C2SCR_CH2C_Msk                           /*!< M0+ receive Channel2 status clear */
19620 #define IPCC_C2SCR_CH3C_Pos      (2U)
19621 #define IPCC_C2SCR_CH3C_Msk      (0x1U << IPCC_C2SCR_CH3C_Pos)                 /*!< 0x00000004 */
19622 #define IPCC_C2SCR_CH3C          IPCC_C2SCR_CH3C_Msk                           /*!< M0+ receive Channel3 status clear */
19623 #define IPCC_C2SCR_CH4C_Pos      (3U)
19624 #define IPCC_C2SCR_CH4C_Msk      (0x1U << IPCC_C2SCR_CH4C_Pos)                 /*!< 0x00000008 */
19625 #define IPCC_C2SCR_CH4C          IPCC_C2SCR_CH4C_Msk                           /*!< M0+ receive Channel4 status clear */
19626 #define IPCC_C2SCR_CH5C_Pos      (4U)
19627 #define IPCC_C2SCR_CH5C_Msk      (0x1U << IPCC_C2SCR_CH5C_Pos)                 /*!< 0x00000010 */
19628 #define IPCC_C2SCR_CH5C          IPCC_C2SCR_CH5C_Msk                           /*!< M0+ receive Channel5 status clear */
19629 #define IPCC_C2SCR_CH6C_Pos      (5U)
19630 #define IPCC_C2SCR_CH6C_Msk      (0x1U << IPCC_C2SCR_CH6C_Pos)                 /*!< 0x00000020 */
19631 #define IPCC_C2SCR_CH6C          IPCC_C2SCR_CH6C_Msk                           /*!< M0+ receive Channel6 status clear */
19632 
19633 #define IPCC_C2SCR_CH1S_Pos      (16U)
19634 #define IPCC_C2SCR_CH1S_Msk      (0x1U << IPCC_C2SCR_CH1S_Pos)                 /*!< 0x00010000 */
19635 #define IPCC_C2SCR_CH1S          IPCC_C2SCR_CH1S_Msk                           /*!< M0+ transmit Channel1 status set  */
19636 #define IPCC_C2SCR_CH2S_Pos      (17U)
19637 #define IPCC_C2SCR_CH2S_Msk      (0x1U << IPCC_C2SCR_CH2S_Pos)                 /*!< 0x00020000 */
19638 #define IPCC_C2SCR_CH2S          IPCC_C2SCR_CH2S_Msk                           /*!< M0+ transmit Channel2 status set  */
19639 #define IPCC_C2SCR_CH3S_Pos      (18U)
19640 #define IPCC_C2SCR_CH3S_Msk      (0x1U << IPCC_C2SCR_CH3S_Pos)                 /*!< 0x00040000 */
19641 #define IPCC_C2SCR_CH3S          IPCC_C2SCR_CH3S_Msk                           /*!< M0+ transmit Channel3 status set  */
19642 #define IPCC_C2SCR_CH4S_Pos      (19U)
19643 #define IPCC_C2SCR_CH4S_Msk      (0x1U << IPCC_C2SCR_CH4S_Pos)                 /*!< 0x00080000 */
19644 #define IPCC_C2SCR_CH4S          IPCC_C2SCR_CH4S_Msk                           /*!< M0+ transmit Channel4 status set  */
19645 #define IPCC_C2SCR_CH5S_Pos      (20U)
19646 #define IPCC_C2SCR_CH5S_Msk      (0x1U << IPCC_C2SCR_CH5S_Pos)                 /*!< 0x00100000 */
19647 #define IPCC_C2SCR_CH5S          IPCC_C2SCR_CH5S_Msk                           /*!< M0+ transmit Channel5 status set  */
19648 #define IPCC_C2SCR_CH6S_Pos      (21U)
19649 #define IPCC_C2SCR_CH6S_Msk      (0x1U << IPCC_C2SCR_CH6S_Pos)                 /*!< 0x00200000 */
19650 #define IPCC_C2SCR_CH6S          IPCC_C2SCR_CH6S_Msk                           /*!< M0+ transmit Channel6 status set  */
19651 
19652 /**********************  Bit definition for IPCC_C2TOC1SR register  ***************/
19653 #define IPCC_C2TOC1SR_CH1F_Pos    (0U)
19654 #define IPCC_C2TOC1SR_CH1F_Msk    (0x1U << IPCC_C2TOC1SR_CH1F_Pos)             /*!< 0x00000001 */
19655 #define IPCC_C2TOC1SR_CH1F        IPCC_C2TOC1SR_CH1F_Msk                       /*!< M0+ transmit to M0 receive Channel1 status flag before masking */
19656 #define IPCC_C2TOC1SR_CH2F_Pos    (1U)
19657 #define IPCC_C2TOC1SR_CH2F_Msk    (0x1U << IPCC_C2TOC1SR_CH2F_Pos)             /*!< 0x00000002 */
19658 #define IPCC_C2TOC1SR_CH2F        IPCC_C2TOC1SR_CH2F_Msk                       /*!< M0+ transmit to M0 receive Channel2 status flag before masking */
19659 #define IPCC_C2TOC1SR_CH3F_Pos    (2U)
19660 #define IPCC_C2TOC1SR_CH3F_Msk    (0x1U << IPCC_C2TOC1SR_CH3F_Pos)             /*!< 0x00000004 */
19661 #define IPCC_C2TOC1SR_CH3F        IPCC_C2TOC1SR_CH3F_Msk                       /*!< M0+ transmit to M0 receive Channel3 status flag before masking */
19662 #define IPCC_C2TOC1SR_CH4F_Pos    (3U)
19663 #define IPCC_C2TOC1SR_CH4F_Msk    (0x1U << IPCC_C2TOC1SR_CH4F_Pos)             /*!< 0x00000008 */
19664 #define IPCC_C2TOC1SR_CH4F        IPCC_C2TOC1SR_CH4F_Msk                       /*!< M0+ transmit to M0 receive Channel4 status flag before masking */
19665 #define IPCC_C2TOC1SR_CH5F_Pos    (4U)
19666 #define IPCC_C2TOC1SR_CH5F_Msk    (0x1U << IPCC_C2TOC1SR_CH5F_Pos)             /*!< 0x00000010 */
19667 #define IPCC_C2TOC1SR_CH5F        IPCC_C2TOC1SR_CH5F_Msk                       /*!< M0+ transmit to M0 receive Channel5 status flag before masking */
19668 #define IPCC_C2TOC1SR_CH6F_Pos    (5U)
19669 #define IPCC_C2TOC1SR_CH6F_Msk    (0x1U << IPCC_C2TOC1SR_CH6F_Pos)             /*!< 0x00000020 */
19670 #define IPCC_C2TOC1SR_CH6F        IPCC_C2TOC1SR_CH6F_Msk                       /*!< M0+ transmit to M0 receive Channel6 status flag before masking */
19671 
19672 /**********************  Bit definition for IPCC_HWCFGR register  ***************/
19673 #define IPCC_HWCFGR_CHANNELS_Pos  (0U)
19674 #define IPCC_HWCFGR_CHANNELS_Msk  (0xFFU << IPCC_HWCFGR_CHANNELS_Pos)          /*!< 0x000000FF */
19675 #define IPCC_HWCFGR_CHANNELS      IPCC_HWCFGR_CHANNELS_Msk                     /*!< Number of channels per CPU */
19676 
19677 /**********************  Bit definition for IPCC_VERR register  *****************/
19678 #define IPCC_VERR_MINREV_Pos      (0U)
19679 #define IPCC_VERR_MINREV_Msk      (0xFU << IPCC_VERR_MINREV_Pos)               /*!< 0x0000000F */
19680 #define IPCC_VERR_MINREV          IPCC_VERR_MINREV_Msk                         /*!< Minor Revision number */
19681 #define IPCC_VERR_MAJREV_Pos      (4U)
19682 #define IPCC_VERR_MAJREV_Msk      (0xFU << IPCC_VERR_MAJREV_Pos)               /*!< 0x000000F0 */
19683 #define IPCC_VERR_MAJREV          IPCC_VERR_MAJREV_Msk                         /*!< Major Revision number */
19684 
19685 /**********************  Bit definition for IPCC_IPIDR register  ****************/
19686 #define IPCC_IPIDR_IPID_Pos       (0U)
19687 #define IPCC_IPIDR_IPID_Msk       (0xFFFFFFFFU << IPCC_IPIDR_IPID_Pos)         /*!< 0xFFFFFFFF */
19688 #define IPCC_IPIDR_IPID           IPCC_IPIDR_IPID_Msk                          /*!< IP Identification */
19689 
19690 /**********************  Bit definition for IPCC_SIDR register  *****************/
19691 #define IPCC_SIDR_SID_Pos         (0U)
19692 #define IPCC_SIDR_SID_Msk         (0xFFFFFFFFU << IPCC_SIDR_SID_Pos)           /*!< 0xFFFFFFFF */
19693 #define IPCC_SIDR_SID             IPCC_SIDR_SID_Msk                            /*!< IP size identification */
19694 
19695 /**********************  Bit definition for IPCC_C1CR register  ***************/
19696 #define IPCC_CR_RXOIE_Pos         IPCC_C1CR_RXOIE_Pos
19697 #define IPCC_CR_RXOIE_Msk         IPCC_C1CR_RXOIE_Msk
19698 #define IPCC_CR_RXOIE             IPCC_C1CR_RXOIE
19699 #define IPCC_CR_TXFIE_Pos         IPCC_C1CR_TXFIE_Pos
19700 #define IPCC_CR_TXFIE_Msk         IPCC_C1CR_TXFIE_Msk
19701 #define IPCC_CR_TXFIE             IPCC_C1CR_TXFIE
19702 
19703 /**********************  Bit definition for IPCC_C1MR register  **************/
19704 #define IPCC_MR_CH1OM_Pos         IPCC_C1MR_CH1OM_Pos
19705 #define IPCC_MR_CH1OM_Msk         IPCC_C1MR_CH1OM_Msk
19706 #define IPCC_MR_CH1OM             IPCC_C1MR_CH1OM
19707 #define IPCC_MR_CH2OM_Pos         IPCC_C1MR_CH2OM_Pos
19708 #define IPCC_MR_CH2OM_Msk         IPCC_C1MR_CH2OM_Msk
19709 #define IPCC_MR_CH2OM             IPCC_C1MR_CH2OM
19710 #define IPCC_MR_CH3OM_Pos         IPCC_C1MR_CH3OM_Pos
19711 #define IPCC_MR_CH3OM_Msk         IPCC_C1MR_CH3OM_Msk
19712 #define IPCC_MR_CH3OM             IPCC_C1MR_CH3OM
19713 #define IPCC_MR_CH4OM_Pos         IPCC_C1MR_CH4OM_Pos
19714 #define IPCC_MR_CH4OM_Msk         IPCC_C1MR_CH4OM_Msk
19715 #define IPCC_MR_CH4OM             IPCC_C1MR_CH4OM
19716 #define IPCC_MR_CH5OM_Pos         IPCC_C1MR_CH5OM_Pos
19717 #define IPCC_MR_CH5OM_Msk         IPCC_C1MR_CH5OM_Msk
19718 #define IPCC_MR_CH5OM             IPCC_C1MR_CH5OM
19719 #define IPCC_MR_CH6OM_Pos         IPCC_C1MR_CH6OM_Pos
19720 #define IPCC_MR_CH6OM_Msk         IPCC_C1MR_CH6OM_Msk
19721 #define IPCC_MR_CH6OM             IPCC_C1MR_CH6OM
19722 
19723 #define IPCC_MR_CH1FM_Pos         IPCC_C1MR_CH1FM_Pos
19724 #define IPCC_MR_CH1FM_Msk         IPCC_C1MR_CH1FM_Msk
19725 #define IPCC_MR_CH1FM             IPCC_C1MR_CH1FM
19726 #define IPCC_MR_CH2FM_Pos         IPCC_C1MR_CH2FM_Pos
19727 #define IPCC_MR_CH2FM_Msk         IPCC_C1MR_CH2FM_Msk
19728 #define IPCC_MR_CH2FM             IPCC_C1MR_CH2FM
19729 #define IPCC_MR_CH3FM_Pos         IPCC_C1MR_CH3FM_Pos
19730 #define IPCC_MR_CH3FM_Msk         IPCC_C1MR_CH3FM_Msk
19731 #define IPCC_MR_CH3FM             IPCC_C1MR_CH3FM
19732 #define IPCC_MR_CH4FM_Pos         IPCC_C1MR_CH4FM_Pos
19733 #define IPCC_MR_CH4FM_Msk         IPCC_C1MR_CH4FM_Msk
19734 #define IPCC_MR_CH4FM             IPCC_C1MR_CH4FM
19735 #define IPCC_MR_CH5FM_Pos         IPCC_C1MR_CH5FM_Pos
19736 #define IPCC_MR_CH5FM_Msk         IPCC_C1MR_CH5FM_Msk
19737 #define IPCC_MR_CH5FM             IPCC_C1MR_CH5FM
19738 #define IPCC_MR_CH6FM_Pos         IPCC_C1MR_CH6FM_Pos
19739 #define IPCC_MR_CH6FM_Msk         IPCC_C1MR_CH6FM_Msk
19740 #define IPCC_MR_CH6FM             IPCC_C1MR_CH6FM
19741 
19742 /**********************  Bit definition for IPCC_C1SCR register  ***************/
19743 #define IPCC_SCR_CH1C_Pos         IPCC_C1SCR_CH1C_Pos
19744 #define IPCC_SCR_CH1C_Msk         IPCC_C1SCR_CH1C_Msk
19745 #define IPCC_SCR_CH1C             IPCC_C1SCR_CH1C
19746 #define IPCC_SCR_CH2C_Pos         IPCC_C1SCR_CH2C_Pos
19747 #define IPCC_SCR_CH2C_Msk         IPCC_C1SCR_CH2C_Msk
19748 #define IPCC_SCR_CH2C             IPCC_C1SCR_CH2C
19749 #define IPCC_SCR_CH3C_Pos         IPCC_C1SCR_CH3C_Pos
19750 #define IPCC_SCR_CH3C_Msk         IPCC_C1SCR_CH3C_Msk
19751 #define IPCC_SCR_CH3C             IPCC_C1SCR_CH3C
19752 #define IPCC_SCR_CH4C_Pos         IPCC_C1SCR_CH4C_Pos
19753 #define IPCC_SCR_CH4C_Msk         IPCC_C1SCR_CH4C_Msk
19754 #define IPCC_SCR_CH4C             IPCC_C1SCR_CH4C
19755 #define IPCC_SCR_CH5C_Pos         IPCC_C1SCR_CH5C_Pos
19756 #define IPCC_SCR_CH5C_Msk         IPCC_C1SCR_CH5C_Msk
19757 #define IPCC_SCR_CH5C             IPCC_C1SCR_CH5C
19758 #define IPCC_SCR_CH6C_Pos         IPCC_C1SCR_CH6C_Pos
19759 #define IPCC_SCR_CH6C_Msk         IPCC_C1SCR_CH6C_Msk
19760 #define IPCC_SCR_CH6C             IPCC_C1SCR_CH6C
19761 
19762 #define IPCC_SCR_CH1S_Pos         IPCC_C1SCR_CH1S_Pos
19763 #define IPCC_SCR_CH1S_Msk         IPCC_C1SCR_CH1S_Msk
19764 #define IPCC_SCR_CH1S             IPCC_C1SCR_CH1S
19765 #define IPCC_SCR_CH2S_Pos         IPCC_C1SCR_CH2S_Pos
19766 #define IPCC_SCR_CH2S_Msk         IPCC_C1SCR_CH2S_Msk
19767 #define IPCC_SCR_CH2S             IPCC_C1SCR_CH2S
19768 #define IPCC_SCR_CH3S_Pos         IPCC_C1SCR_CH3S_Pos
19769 #define IPCC_SCR_CH3S_Msk         IPCC_C1SCR_CH3S_Msk
19770 #define IPCC_SCR_CH3S             IPCC_C1SCR_CH3S
19771 #define IPCC_SCR_CH4S_Pos         IPCC_C1SCR_CH4S_Pos
19772 #define IPCC_SCR_CH4S_Msk         IPCC_C1SCR_CH4S_Msk
19773 #define IPCC_SCR_CH4S             IPCC_C1SCR_CH4S
19774 #define IPCC_SCR_CH5S_Pos         IPCC_C1SCR_CH5S_Pos
19775 #define IPCC_SCR_CH5S_Msk         IPCC_C1SCR_CH5S_Msk
19776 #define IPCC_SCR_CH5S             IPCC_C1SCR_CH5S
19777 #define IPCC_SCR_CH6S_Pos         IPCC_C1SCR_CH6S_Pos
19778 #define IPCC_SCR_CH6S_Msk         IPCC_C1SCR_CH6S_Msk
19779 #define IPCC_SCR_CH6S             IPCC_C1SCR_CH6S
19780 
19781 /**********************  Bit definition for IPCC_C1TOC2SR register  ***************/
19782 #define IPCC_SR_CH1F_Pos          IPCC_C1TOC2SR_CH1F_Pos
19783 #define IPCC_SR_CH1F_Msk          IPCC_C1TOC2SR_CH1F_Msk
19784 #define IPCC_SR_CH1F              IPCC_C1TOC2SR_CH1F
19785 #define IPCC_SR_CH2F_Pos          IPCC_C1TOC2SR_CH2F_Pos
19786 #define IPCC_SR_CH2F_Msk          IPCC_C1TOC2SR_CH2F_Msk
19787 #define IPCC_SR_CH2F              IPCC_C1TOC2SR_CH2F
19788 #define IPCC_SR_CH3F_Pos          IPCC_C1TOC2SR_CH3F_Pos
19789 #define IPCC_SR_CH3F_Msk          IPCC_C1TOC2SR_CH3F_Msk
19790 #define IPCC_SR_CH3F              IPCC_C1TOC2SR_CH3F
19791 #define IPCC_SR_CH4F_Pos          IPCC_C1TOC2SR_CH4F_Pos
19792 #define IPCC_SR_CH4F_Msk          IPCC_C1TOC2SR_CH4F_Msk
19793 #define IPCC_SR_CH4F              IPCC_C1TOC2SR_CH4F
19794 #define IPCC_SR_CH5F_Pos          IPCC_C1TOC2SR_CH5F_Pos
19795 #define IPCC_SR_CH5F_Msk          IPCC_C1TOC2SR_CH5F_Msk
19796 #define IPCC_SR_CH5F              IPCC_C1TOC2SR_CH5F
19797 #define IPCC_SR_CH6F_Pos          IPCC_C1TOC2SR_CH6F_Pos
19798 #define IPCC_SR_CH6F_Msk          IPCC_C1TOC2SR_CH6F_Msk
19799 #define IPCC_SR_CH6F              IPCC_C1TOC2SR_CH6F
19800 
19801 /******************** Number of IPCC channels ******************************/
19802 #define IPCC_CHANNEL_NUMBER       6U
19803 
19804 /******************************************************************************/
19805 /*                                                                            */
19806 /*                                     MDMA                                   */
19807 /*                                                                            */
19808 /******************************************************************************/
19809 /********************  Bit definition for MDMA_GISR0 register  ****************/
19810 #define MDMA_GISR0_GIF0_Pos       (0U)
19811 #define MDMA_GISR0_GIF0_Msk       (0x1U << MDMA_GISR0_GIF0_Pos)                /*!< 0x00000001 */
19812 #define MDMA_GISR0_GIF0           MDMA_GISR0_GIF0_Msk                          /*!< Channel 0 global interrupt flag */
19813 #define MDMA_GISR0_GIF1_Pos       (1U)
19814 #define MDMA_GISR0_GIF1_Msk       (0x1U << MDMA_GISR0_GIF1_Pos)                /*!< 0x00000002 */
19815 #define MDMA_GISR0_GIF1           MDMA_GISR0_GIF1_Msk                          /*!< Channel 1 global interrupt flag */
19816 #define MDMA_GISR0_GIF2_Pos       (2U)
19817 #define MDMA_GISR0_GIF2_Msk       (0x1U << MDMA_GISR0_GIF2_Pos)                /*!< 0x00000004 */
19818 #define MDMA_GISR0_GIF2           MDMA_GISR0_GIF2_Msk                          /*!< Channel 2 global interrupt flag */
19819 #define MDMA_GISR0_GIF3_Pos       (3U)
19820 #define MDMA_GISR0_GIF3_Msk       (0x1U << MDMA_GISR0_GIF3_Pos)                /*!< 0x00000008 */
19821 #define MDMA_GISR0_GIF3           MDMA_GISR0_GIF3_Msk                          /*!< Channel 3 global interrupt flag */
19822 #define MDMA_GISR0_GIF4_Pos       (4U)
19823 #define MDMA_GISR0_GIF4_Msk       (0x1U << MDMA_GISR0_GIF4_Pos)                /*!< 0x00000010 */
19824 #define MDMA_GISR0_GIF4           MDMA_GISR0_GIF4_Msk                          /*!< Channel 4 global interrupt flag */
19825 #define MDMA_GISR0_GIF5_Pos       (5U)
19826 #define MDMA_GISR0_GIF5_Msk       (0x1U << MDMA_GISR0_GIF5_Pos)                /*!< 0x00000020 */
19827 #define MDMA_GISR0_GIF5           MDMA_GISR0_GIF5_Msk                          /*!< Channel 5 global interrupt flag */
19828 #define MDMA_GISR0_GIF6_Pos       (6U)
19829 #define MDMA_GISR0_GIF6_Msk       (0x1U << MDMA_GISR0_GIF6_Pos)                /*!< 0x00000040 */
19830 #define MDMA_GISR0_GIF6           MDMA_GISR0_GIF6_Msk                          /*!< Channel 6 global interrupt flag */
19831 #define MDMA_GISR0_GIF7_Pos       (7U)
19832 #define MDMA_GISR0_GIF7_Msk       (0x1U << MDMA_GISR0_GIF7_Pos)                /*!< 0x00000080 */
19833 #define MDMA_GISR0_GIF7           MDMA_GISR0_GIF7_Msk                          /*!< Channel 7 global interrupt flag */
19834 #define MDMA_GISR0_GIF8_Pos       (8U)
19835 #define MDMA_GISR0_GIF8_Msk       (0x1U << MDMA_GISR0_GIF8_Pos)                /*!< 0x00000100 */
19836 #define MDMA_GISR0_GIF8           MDMA_GISR0_GIF8_Msk                          /*!< Channel 8 global interrupt flag */
19837 #define MDMA_GISR0_GIF9_Pos       (9U)
19838 #define MDMA_GISR0_GIF9_Msk       (0x1U << MDMA_GISR0_GIF9_Pos)                /*!< 0x00000200 */
19839 #define MDMA_GISR0_GIF9           MDMA_GISR0_GIF9_Msk                          /*!< Channel 9 global interrupt flag */
19840 #define MDMA_GISR0_GIF10_Pos      (10U)
19841 #define MDMA_GISR0_GIF10_Msk      (0x1U << MDMA_GISR0_GIF10_Pos)               /*!< 0x00000400 */
19842 #define MDMA_GISR0_GIF10          MDMA_GISR0_GIF10_Msk                         /*!< Channel 10 global interrupt flag */
19843 #define MDMA_GISR0_GIF11_Pos      (11U)
19844 #define MDMA_GISR0_GIF11_Msk      (0x1U << MDMA_GISR0_GIF11_Pos)               /*!< 0x00000800 */
19845 #define MDMA_GISR0_GIF11          MDMA_GISR0_GIF11_Msk                         /*!< Channel 11 global interrupt flag */
19846 #define MDMA_GISR0_GIF12_Pos      (12U)
19847 #define MDMA_GISR0_GIF12_Msk      (0x1U << MDMA_GISR0_GIF12_Pos)               /*!< 0x00001000 */
19848 #define MDMA_GISR0_GIF12          MDMA_GISR0_GIF12_Msk                         /*!< Channel 12 global interrupt flag */
19849 #define MDMA_GISR0_GIF13_Pos      (13U)
19850 #define MDMA_GISR0_GIF13_Msk      (0x1U << MDMA_GISR0_GIF13_Pos)               /*!< 0x00002000 */
19851 #define MDMA_GISR0_GIF13          MDMA_GISR0_GIF13_Msk                         /*!< Channel 13 global interrupt flag */
19852 #define MDMA_GISR0_GIF14_Pos      (14U)
19853 #define MDMA_GISR0_GIF14_Msk      (0x1U << MDMA_GISR0_GIF14_Pos)               /*!< 0x00004000 */
19854 #define MDMA_GISR0_GIF14          MDMA_GISR0_GIF14_Msk                         /*!< Channel 14 global interrupt flag */
19855 #define MDMA_GISR0_GIF15_Pos      (15U)
19856 #define MDMA_GISR0_GIF15_Msk      (0x1U << MDMA_GISR0_GIF15_Pos)               /*!< 0x00008000 */
19857 #define MDMA_GISR0_GIF15          MDMA_GISR0_GIF15_Msk                         /*!< Channel 15 global interrupt flag */
19858 #define MDMA_GISR0_GIF16_Pos      (16U)
19859 #define MDMA_GISR0_GIF16_Msk      (0x1U << MDMA_GISR0_GIF16_Pos)               /*!< 0x00010000 */
19860 #define MDMA_GISR0_GIF16          MDMA_GISR0_GIF16_Msk                         /*!< Channel 16 global interrupt flag */
19861 #define MDMA_GISR0_GIF17_Pos      (17U)
19862 #define MDMA_GISR0_GIF17_Msk      (0x1U << MDMA_GISR0_GIF17_Pos)               /*!< 0x00020000 */
19863 #define MDMA_GISR0_GIF17          MDMA_GISR0_GIF17_Msk                         /*!< Channel 17 global interrupt flag */
19864 #define MDMA_GISR0_GIF18_Pos      (18U)
19865 #define MDMA_GISR0_GIF18_Msk      (0x1U << MDMA_GISR0_GIF18_Pos)               /*!< 0x00040000 */
19866 #define MDMA_GISR0_GIF18          MDMA_GISR0_GIF18_Msk                         /*!< Channel 18 global interrupt flag */
19867 #define MDMA_GISR0_GIF19_Pos      (19U)
19868 #define MDMA_GISR0_GIF19_Msk      (0x1U << MDMA_GISR0_GIF19_Pos)               /*!< 0x00080000 */
19869 #define MDMA_GISR0_GIF19          MDMA_GISR0_GIF19_Msk                         /*!< Channel 19 global interrupt flag */
19870 #define MDMA_GISR0_GIF20_Pos      (20U)
19871 #define MDMA_GISR0_GIF20_Msk      (0x1U << MDMA_GISR0_GIF20_Pos)               /*!< 0x00100000 */
19872 #define MDMA_GISR0_GIF20          MDMA_GISR0_GIF20_Msk                         /*!< Channel 20 global interrupt flag */
19873 #define MDMA_GISR0_GIF21_Pos      (21U)
19874 #define MDMA_GISR0_GIF21_Msk      (0x1U << MDMA_GISR0_GIF21_Pos)               /*!< 0x00200000 */
19875 #define MDMA_GISR0_GIF21          MDMA_GISR0_GIF21_Msk                         /*!< Channel 21 global interrupt flag */
19876 #define MDMA_GISR0_GIF22_Pos      (22U)
19877 #define MDMA_GISR0_GIF22_Msk      (0x1U << MDMA_GISR0_GIF22_Pos)               /*!< 0x00400000 */
19878 #define MDMA_GISR0_GIF22          MDMA_GISR0_GIF22_Msk                         /*!< Channel 22 global interrupt flag */
19879 #define MDMA_GISR0_GIF23_Pos      (23U)
19880 #define MDMA_GISR0_GIF23_Msk      (0x1U << MDMA_GISR0_GIF23_Pos)               /*!< 0x00800000 */
19881 #define MDMA_GISR0_GIF23          MDMA_GISR0_GIF23_Msk                         /*!< Channel 23 global interrupt flag */
19882 #define MDMA_GISR0_GIF24_Pos      (24U)
19883 #define MDMA_GISR0_GIF24_Msk      (0x1U << MDMA_GISR0_GIF24_Pos)               /*!< 0x01000000 */
19884 #define MDMA_GISR0_GIF24          MDMA_GISR0_GIF24_Msk                         /*!< Channel 24 global interrupt flag */
19885 #define MDMA_GISR0_GIF25_Pos      (25U)
19886 #define MDMA_GISR0_GIF25_Msk      (0x1U << MDMA_GISR0_GIF25_Pos)               /*!< 0x02000000 */
19887 #define MDMA_GISR0_GIF25          MDMA_GISR0_GIF25_Msk                         /*!< Channel 25 global interrupt flag */
19888 #define MDMA_GISR0_GIF26_Pos      (26U)
19889 #define MDMA_GISR0_GIF26_Msk      (0x1U << MDMA_GISR0_GIF26_Pos)               /*!< 0x04000000 */
19890 #define MDMA_GISR0_GIF26          MDMA_GISR0_GIF26_Msk                         /*!< Channel 26 global interrupt flag */
19891 #define MDMA_GISR0_GIF27_Pos      (27U)
19892 #define MDMA_GISR0_GIF27_Msk      (0x1U << MDMA_GISR0_GIF27_Pos)               /*!< 0x08000000 */
19893 #define MDMA_GISR0_GIF27          MDMA_GISR0_GIF27_Msk                         /*!< Channel 27 global interrupt flag */
19894 #define MDMA_GISR0_GIF28_Pos      (28U)
19895 #define MDMA_GISR0_GIF28_Msk      (0x1U << MDMA_GISR0_GIF28_Pos)               /*!< 0x10000000 */
19896 #define MDMA_GISR0_GIF28          MDMA_GISR0_GIF28_Msk                         /*!< Channel 28 global interrupt flag */
19897 #define MDMA_GISR0_GIF29_Pos      (29U)
19898 #define MDMA_GISR0_GIF29_Msk      (0x1U << MDMA_GISR0_GIF29_Pos)               /*!< 0x20000000 */
19899 #define MDMA_GISR0_GIF29          MDMA_GISR0_GIF29_Msk                         /*!< Channel 29 global interrupt flag */
19900 #define MDMA_GISR0_GIF30_Pos      (30U)
19901 #define MDMA_GISR0_GIF30_Msk      (0x1U << MDMA_GISR0_GIF30_Pos)               /*!< 0x40000000 */
19902 #define MDMA_GISR0_GIF30          MDMA_GISR0_GIF30_Msk                         /*!< Channel 30 global interrupt flag */
19903 #define MDMA_GISR0_GIF31_Pos      (31U)
19904 #define MDMA_GISR0_GIF31_Msk      (0x1U << MDMA_GISR0_GIF31_Pos)               /*!< 0x80000000 */
19905 #define MDMA_GISR0_GIF31          MDMA_GISR0_GIF31_Msk                         /*!< Channel 31 global interrupt flag */
19906 
19907 /********************  Bit definition for MDMA_GISR1 register  ****************/
19908 #define MDMA_GISR1_GIF32_Pos      (0U)
19909 #define MDMA_GISR1_GIF32_Msk      (0x1U << MDMA_GISR1_GIF32_Pos)               /*!< 0x00000001 */
19910 #define MDMA_GISR1_GIF32          MDMA_GISR1_GIF32_Msk                         /*!< Channel 32 global interrupt flag */
19911 #define MDMA_GISR1_GIF33_Pos      (1U)
19912 #define MDMA_GISR1_GIF33_Msk      (0x1U << MDMA_GISR1_GIF33_Pos)               /*!< 0x00000002 */
19913 #define MDMA_GISR1_GIF33          MDMA_GISR1_GIF33_Msk                         /*!< Channel 33 global interrupt flag */
19914 #define MDMA_GISR1_GIF34_Pos      (2U)
19915 #define MDMA_GISR1_GIF34_Msk      (0x1U << MDMA_GISR1_GIF34_Pos)               /*!< 0x00000004 */
19916 #define MDMA_GISR1_GIF34          MDMA_GISR1_GIF34_Msk                         /*!< Channel 34 global interrupt flag */
19917 #define MDMA_GISR1_GIF35_Pos      (3U)
19918 #define MDMA_GISR1_GIF35_Msk      (0x1U << MDMA_GISR1_GIF35_Pos)               /*!< 0x00000008 */
19919 #define MDMA_GISR1_GIF35          MDMA_GISR1_GIF35_Msk                         /*!< Channel 35 global interrupt flag */
19920 #define MDMA_GISR1_GIF36_Pos      (4U)
19921 #define MDMA_GISR1_GIF36_Msk      (0x1U << MDMA_GISR1_GIF36_Pos)               /*!< 0x00000010 */
19922 #define MDMA_GISR1_GIF36          MDMA_GISR1_GIF36_Msk                         /*!< Channel 36 global interrupt flag */
19923 #define MDMA_GISR1_GIF37_Pos      (5U)
19924 #define MDMA_GISR1_GIF37_Msk      (0x1U << MDMA_GISR1_GIF37_Pos)               /*!< 0x00000020 */
19925 #define MDMA_GISR1_GIF37          MDMA_GISR1_GIF37_Msk                         /*!< Channel 37 global interrupt flag */
19926 #define MDMA_GISR1_GIF38_Pos      (6U)
19927 #define MDMA_GISR1_GIF38_Msk      (0x1U << MDMA_GISR1_GIF38_Pos)               /*!< 0x00000040 */
19928 #define MDMA_GISR1_GIF38          MDMA_GISR1_GIF38_Msk                         /*!< Channel 38 global interrupt flag */
19929 #define MDMA_GISR1_GIF39_Pos      (7U)
19930 #define MDMA_GISR1_GIF39_Msk      (0x1U << MDMA_GISR1_GIF39_Pos)               /*!< 0x00000080 */
19931 #define MDMA_GISR1_GIF39          MDMA_GISR1_GIF39_Msk                         /*!< Channel 39 global interrupt flag */
19932 #define MDMA_GISR1_GIF40_Pos      (8U)
19933 #define MDMA_GISR1_GIF40_Msk      (0x1U << MDMA_GISR1_GIF40_Pos)               /*!< 0x00000100 */
19934 #define MDMA_GISR1_GIF40          MDMA_GISR1_GIF40_Msk                         /*!< Channel 40 global interrupt flag */
19935 #define MDMA_GISR1_GIF41_Pos      (9U)
19936 #define MDMA_GISR1_GIF41_Msk      (0x1U << MDMA_GISR1_GIF41_Pos)               /*!< 0x00000200 */
19937 #define MDMA_GISR1_GIF41          MDMA_GISR1_GIF41_Msk                         /*!< Channel 41 global interrupt flag */
19938 #define MDMA_GISR1_GIF42_Pos      (10U)
19939 #define MDMA_GISR1_GIF42_Msk      (0x1U << MDMA_GISR1_GIF42_Pos)               /*!< 0x00000400 */
19940 #define MDMA_GISR1_GIF42          MDMA_GISR1_GIF42_Msk                         /*!< Channel 42 global interrupt flag */
19941 #define MDMA_GISR1_GIF43_Pos      (11U)
19942 #define MDMA_GISR1_GIF43_Msk      (0x1U << MDMA_GISR1_GIF43_Pos)               /*!< 0x00000800 */
19943 #define MDMA_GISR1_GIF43          MDMA_GISR1_GIF43_Msk                         /*!< Channel 43 global interrupt flag */
19944 #define MDMA_GISR1_GIF44_Pos      (12U)
19945 #define MDMA_GISR1_GIF44_Msk      (0x1U << MDMA_GISR1_GIF44_Pos)               /*!< 0x00001000 */
19946 #define MDMA_GISR1_GIF44          MDMA_GISR1_GIF44_Msk                         /*!< Channel 44 global interrupt flag */
19947 #define MDMA_GISR1_GIF45_Pos      (13U)
19948 #define MDMA_GISR1_GIF45_Msk      (0x1U << MDMA_GISR1_GIF45_Pos)               /*!< 0x00002000 */
19949 #define MDMA_GISR1_GIF45          MDMA_GISR1_GIF45_Msk                         /*!< Channel 45 global interrupt flag */
19950 #define MDMA_GISR1_GIF46_Pos      (14U)
19951 #define MDMA_GISR1_GIF46_Msk      (0x1U << MDMA_GISR1_GIF46_Pos)               /*!< 0x00004000 */
19952 #define MDMA_GISR1_GIF46          MDMA_GISR1_GIF46_Msk                         /*!< Channel 46 global interrupt flag */
19953 #define MDMA_GISR1_GIF47_Pos      (15U)
19954 #define MDMA_GISR1_GIF47_Msk      (0x1U << MDMA_GISR1_GIF47_Pos)               /*!< 0x00008000 */
19955 #define MDMA_GISR1_GIF47          MDMA_GISR1_GIF47_Msk                         /*!< Channel 47 global interrupt flag */
19956 #define MDMA_GISR1_GIF48_Pos      (16U)
19957 #define MDMA_GISR1_GIF48_Msk      (0x1U << MDMA_GISR1_GIF48_Pos)               /*!< 0x00010000 */
19958 #define MDMA_GISR1_GIF48          MDMA_GISR1_GIF48_Msk                         /*!< Channel 48 global interrupt flag */
19959 #define MDMA_GISR1_GIF49_Pos      (17U)
19960 #define MDMA_GISR1_GIF49_Msk      (0x1U << MDMA_GISR1_GIF49_Pos)               /*!< 0x00020000 */
19961 #define MDMA_GISR1_GIF49          MDMA_GISR1_GIF49_Msk                         /*!< Channel 49 global interrupt flag */
19962 #define MDMA_GISR1_GIF50_Pos      (18U)
19963 #define MDMA_GISR1_GIF50_Msk      (0x1U << MDMA_GISR1_GIF50_Pos)               /*!< 0x00040000 */
19964 #define MDMA_GISR1_GIF50          MDMA_GISR1_GIF50_Msk                         /*!< Channel 50 global interrupt flag */
19965 #define MDMA_GISR1_GIF51_Pos      (19U)
19966 #define MDMA_GISR1_GIF51_Msk      (0x1U << MDMA_GISR1_GIF51_Pos)               /*!< 0x00080000 */
19967 #define MDMA_GISR1_GIF51          MDMA_GISR1_GIF51_Msk                         /*!< Channel 51 global interrupt flag */
19968 #define MDMA_GISR1_GIF52_Pos      (20U)
19969 #define MDMA_GISR1_GIF52_Msk      (0x1U << MDMA_GISR1_GIF52_Pos)               /*!< 0x00100000 */
19970 #define MDMA_GISR1_GIF52          MDMA_GISR1_GIF52_Msk                         /*!< Channel 52 global interrupt flag */
19971 #define MDMA_GISR1_GIF53_Pos      (21U)
19972 #define MDMA_GISR1_GIF53_Msk      (0x1U << MDMA_GISR1_GIF53_Pos)               /*!< 0x00200000 */
19973 #define MDMA_GISR1_GIF53          MDMA_GISR1_GIF53_Msk                         /*!< Channel 53 global interrupt flag */
19974 #define MDMA_GISR1_GIF54_Pos      (22U)
19975 #define MDMA_GISR1_GIF54_Msk      (0x1U << MDMA_GISR1_GIF54_Pos)               /*!< 0x00400000 */
19976 #define MDMA_GISR1_GIF54          MDMA_GISR1_GIF54_Msk                         /*!< Channel 54 global interrupt flag */
19977 #define MDMA_GISR1_GIF55_Pos      (23U)
19978 #define MDMA_GISR1_GIF55_Msk      (0x1U << MDMA_GISR1_GIF55_Pos)               /*!< 0x00800000 */
19979 #define MDMA_GISR1_GIF55          MDMA_GISR1_GIF55_Msk                         /*!< Channel 55 global interrupt flag */
19980 #define MDMA_GISR1_GIF56_Pos      (24U)
19981 #define MDMA_GISR1_GIF56_Msk      (0x1U << MDMA_GISR1_GIF56_Pos)               /*!< 0x01000000 */
19982 #define MDMA_GISR1_GIF56          MDMA_GISR1_GIF56_Msk                         /*!< Channel 56 global interrupt flag */
19983 #define MDMA_GISR1_GIF57_Pos      (25U)
19984 #define MDMA_GISR1_GIF57_Msk      (0x1U << MDMA_GISR1_GIF57_Pos)               /*!< 0x02000000 */
19985 #define MDMA_GISR1_GIF57          MDMA_GISR1_GIF57_Msk                         /*!< Channel 57 global interrupt flag */
19986 #define MDMA_GISR1_GIF58_Pos      (26U)
19987 #define MDMA_GISR1_GIF58_Msk      (0x1U << MDMA_GISR1_GIF58_Pos)               /*!< 0x04000000 */
19988 #define MDMA_GISR1_GIF58          MDMA_GISR1_GIF58_Msk                         /*!< Channel 58 global interrupt flag */
19989 #define MDMA_GISR1_GIF59_Pos      (27U)
19990 #define MDMA_GISR1_GIF59_Msk      (0x1U << MDMA_GISR1_GIF59_Pos)               /*!< 0x08000000 */
19991 #define MDMA_GISR1_GIF59          MDMA_GISR1_GIF59_Msk                         /*!< Channel 59 global interrupt flag */
19992 #define MDMA_GISR1_GIF60_Pos      (28U)
19993 #define MDMA_GISR1_GIF60_Msk      (0x1U << MDMA_GISR1_GIF60_Pos)               /*!< 0x10000000 */
19994 #define MDMA_GISR1_GIF60          MDMA_GISR1_GIF60_Msk                         /*!< Channel 60 global interrupt flag */
19995 #define MDMA_GISR1_GIF61_Pos      (29U)
19996 #define MDMA_GISR1_GIF61_Msk      (0x1U << MDMA_GISR1_GIF61_Pos)               /*!< 0x20000000 */
19997 #define MDMA_GISR1_GIF61          MDMA_GISR1_GIF61_Msk                         /*!< Channel 61 global interrupt flag */
19998 #define MDMA_GISR1_GIF62_Pos      (30U)
19999 #define MDMA_GISR1_GIF62_Msk      (0x1U << MDMA_GISR1_GIF62_Pos)               /*!< 0x40000000 */
20000 #define MDMA_GISR1_GIF62          MDMA_GISR1_GIF62_Msk                         /*!< Channel 62 global interrupt flag */
20001 
20002 /********************  Bit definition for MDMA_CxISR register  ****************/
20003 #define MDMA_CISR_TEIF_Pos        (0U)
20004 #define MDMA_CISR_TEIF_Msk        (0x1U << MDMA_CISR_TEIF_Pos)                 /*!< 0x00000001 */
20005 #define MDMA_CISR_TEIF            MDMA_CISR_TEIF_Msk                           /*!< Channel x transfer error interrupt flag */
20006 #define MDMA_CISR_CTCIF_Pos       (1U)
20007 #define MDMA_CISR_CTCIF_Msk       (0x1U << MDMA_CISR_CTCIF_Pos)                /*!< 0x00000002 */
20008 #define MDMA_CISR_CTCIF           MDMA_CISR_CTCIF_Msk                          /*!< Channel x Channel Transfer Complete interrupt flag */
20009 #define MDMA_CISR_BRTIF_Pos       (2U)
20010 #define MDMA_CISR_BRTIF_Msk       (0x1U << MDMA_CISR_BRTIF_Pos)                /*!< 0x00000004 */
20011 #define MDMA_CISR_BRTIF           MDMA_CISR_BRTIF_Msk                          /*!< Channel x block repeat transfer complete interrupt flag */
20012 #define MDMA_CISR_BTIF_Pos        (3U)
20013 #define MDMA_CISR_BTIF_Msk        (0x1U << MDMA_CISR_BTIF_Pos)                 /*!< 0x00000008 */
20014 #define MDMA_CISR_BTIF            MDMA_CISR_BTIF_Msk                           /*!< Channel x block transfer complete interrupt flag */
20015 #define MDMA_CISR_TCIF_Pos        (4U)
20016 #define MDMA_CISR_TCIF_Msk        (0x1U << MDMA_CISR_TCIF_Pos)                 /*!< 0x00000010 */
20017 #define MDMA_CISR_TCIF            MDMA_CISR_TCIF_Msk                           /*!< Channel x buffer transfer complete interrupt flag */
20018 #define MDMA_CISR_CRQA_Pos        (16U)
20019 #define MDMA_CISR_CRQA_Msk        (0x1U << MDMA_CISR_CRQA_Pos)                 /*!< 0x00010000 */
20020 #define MDMA_CISR_CRQA            MDMA_CISR_CRQA_Msk                           /*!< Channel x ReQest Active flag */
20021 
20022 /********************  Bit definition for MDMA_CxIFCR register  ****************/
20023 #define MDMA_CIFCR_CTEIF_Pos      (0U)
20024 #define MDMA_CIFCR_CTEIF_Msk      (0x1U << MDMA_CIFCR_CTEIF_Pos)               /*!< 0x00000001 */
20025 #define MDMA_CIFCR_CTEIF          MDMA_CIFCR_CTEIF_Msk                         /*!< Channel x clear transfer error interrupt flag */
20026 #define MDMA_CIFCR_CCTCIF_Pos     (1U)
20027 #define MDMA_CIFCR_CCTCIF_Msk     (0x1U << MDMA_CIFCR_CCTCIF_Pos)              /*!< 0x00000002 */
20028 #define MDMA_CIFCR_CCTCIF         MDMA_CIFCR_CCTCIF_Msk                        /*!< Clear Channel transfer complete interrupt flag for channel x */
20029 #define MDMA_CIFCR_CBRTIF_Pos     (2U)
20030 #define MDMA_CIFCR_CBRTIF_Msk     (0x1U << MDMA_CIFCR_CBRTIF_Pos)              /*!< 0x00000004 */
20031 #define MDMA_CIFCR_CBRTIF         MDMA_CIFCR_CBRTIF_Msk                        /*!< Channel x clear block repeat transfer complete interrupt flag */
20032 #define MDMA_CIFCR_CBTIF_Pos      (3U)
20033 #define MDMA_CIFCR_CBTIF_Msk      (0x1U << MDMA_CIFCR_CBTIF_Pos)               /*!< 0x00000008 */
20034 #define MDMA_CIFCR_CBTIF          MDMA_CIFCR_CBTIF_Msk                         /*!< Channel x Clear block transfer complete interrupt flag */
20035 #define MDMA_CIFCR_CLTCIF_Pos     (4U)
20036 #define MDMA_CIFCR_CLTCIF_Msk     (0x1U << MDMA_CIFCR_CLTCIF_Pos)              /*!< 0x00000010 */
20037 #define MDMA_CIFCR_CLTCIF         MDMA_CIFCR_CLTCIF_Msk                        /*!< CLear Transfer buffer Complete Interrupt Flag for channel */
20038 
20039 /********************  Bit definition for MDMA_CxESR register  ****************/
20040 #define MDMA_CESR_TEA_Pos         (0U)
20041 #define MDMA_CESR_TEA_Msk         (0x7FU << MDMA_CESR_TEA_Pos)                 /*!< 0x0000007F */
20042 #define MDMA_CESR_TEA             MDMA_CESR_TEA_Msk                            /*!< Transfer Error Address */
20043 #define MDMA_CESR_TED_Pos         (7U)
20044 #define MDMA_CESR_TED_Msk         (0x1U << MDMA_CESR_TED_Pos)                  /*!< 0x00000080 */
20045 #define MDMA_CESR_TED             MDMA_CESR_TED_Msk                            /*!< Transfer Error Direction */
20046 #define MDMA_CESR_TELD_Pos        (8U)
20047 #define MDMA_CESR_TELD_Msk        (0x1U << MDMA_CESR_TELD_Pos)                 /*!< 0x00000100 */
20048 #define MDMA_CESR_TELD            MDMA_CESR_TELD_Msk                           /*!< Transfer Error Link Data */
20049 #define MDMA_CESR_TEMD_Pos        (9U)
20050 #define MDMA_CESR_TEMD_Msk        (0x1U << MDMA_CESR_TEMD_Pos)                 /*!< 0x00000200 */
20051 #define MDMA_CESR_TEMD            MDMA_CESR_TEMD_Msk                           /*!< Transfer Error Mask Data */
20052 #define MDMA_CESR_ASE_Pos         (10U)
20053 #define MDMA_CESR_ASE_Msk         (0x1U << MDMA_CESR_ASE_Pos)                  /*!< 0x00000400 */
20054 #define MDMA_CESR_ASE             MDMA_CESR_ASE_Msk                            /*!< Address/Size Error       */
20055 #define MDMA_CESR_BSE_Pos         (11U)
20056 #define MDMA_CESR_BSE_Msk         (0x1U << MDMA_CESR_BSE_Pos)                  /*!< 0x00000800 */
20057 #define MDMA_CESR_BSE             MDMA_CESR_BSE_Msk                            /*!< Block Size Error         */
20058 
20059 /********************  Bit definition for MDMA_CxCR register  ****************/
20060 #define MDMA_CCR_EN_Pos           (0U)
20061 #define MDMA_CCR_EN_Msk           (0x1U << MDMA_CCR_EN_Pos)                    /*!< 0x00000001 */
20062 #define MDMA_CCR_EN               MDMA_CCR_EN_Msk                              /*!< Channel enable / flag channel ready when read low */
20063 #define MDMA_CCR_TEIE_Pos         (1U)
20064 #define MDMA_CCR_TEIE_Msk         (0x1U << MDMA_CCR_TEIE_Pos)                  /*!< 0x00000002 */
20065 #define MDMA_CCR_TEIE             MDMA_CCR_TEIE_Msk                            /*!< Transfer error interrupt enable */
20066 #define MDMA_CCR_CTCIE_Pos        (2U)
20067 #define MDMA_CCR_CTCIE_Msk        (0x1U << MDMA_CCR_CTCIE_Pos)                 /*!< 0x00000004 */
20068 #define MDMA_CCR_CTCIE            MDMA_CCR_CTCIE_Msk                           /*!< Channel Transfer Complete interrupt enable */
20069 #define MDMA_CCR_BRTIE_Pos        (3U)
20070 #define MDMA_CCR_BRTIE_Msk        (0x1U << MDMA_CCR_BRTIE_Pos)                 /*!< 0x00000008 */
20071 #define MDMA_CCR_BRTIE            MDMA_CCR_BRTIE_Msk                           /*!< Block Repeat transfer interrupt enable */
20072 #define MDMA_CCR_BTIE_Pos         (4U)
20073 #define MDMA_CCR_BTIE_Msk         (0x1U << MDMA_CCR_BTIE_Pos)                  /*!< 0x00000010 */
20074 #define MDMA_CCR_BTIE             MDMA_CCR_BTIE_Msk                            /*!< Block Transfer interrupt enable */
20075 #define MDMA_CCR_TCIE_Pos         (5U)
20076 #define MDMA_CCR_TCIE_Msk         (0x1U << MDMA_CCR_TCIE_Pos)                  /*!< 0x00000020 */
20077 #define MDMA_CCR_TCIE             MDMA_CCR_TCIE_Msk                            /*!< buffer Transfer Complete interrupt enable */
20078 #define MDMA_CCR_PL_Pos           (6U)
20079 #define MDMA_CCR_PL_Msk           (0x3U << MDMA_CCR_PL_Pos)                    /*!< 0x000000C0 */
20080 #define MDMA_CCR_PL               MDMA_CCR_PL_Msk                              /*!< Priority level */
20081 #define MDMA_CCR_PL_0             (0x1U << MDMA_CCR_PL_Pos)                    /*!< 0x00000040 */
20082 #define MDMA_CCR_PL_1             (0x2U << MDMA_CCR_PL_Pos)                    /*!< 0x00000080 */
20083 #define MDMA_CCR_SM_Pos           (8U)
20084 #define MDMA_CCR_SM_Msk           (0x1U << MDMA_CCR_SM_Pos)                    /*!< 0x00000100 */
20085 #define MDMA_CCR_SM               MDMA_CCR_SM_Msk                              /*!< Secure Mode Eanble */
20086 #define MDMA_CCR_BEX_Pos          (12U)
20087 #define MDMA_CCR_BEX_Msk          (0x1U << MDMA_CCR_BEX_Pos)                   /*!< 0x00001000 */
20088 #define MDMA_CCR_BEX              MDMA_CCR_BEX_Msk                             /*!< Byte Endianess eXchange */
20089 #define MDMA_CCR_HEX_Pos          (13U)
20090 #define MDMA_CCR_HEX_Msk          (0x1U << MDMA_CCR_HEX_Pos)                   /*!< 0x00002000 */
20091 #define MDMA_CCR_HEX              MDMA_CCR_HEX_Msk                             /*!< Half word Endianess eXchange */
20092 #define MDMA_CCR_WEX_Pos          (14U)
20093 #define MDMA_CCR_WEX_Msk          (0x1U << MDMA_CCR_WEX_Pos)                   /*!< 0x00004000 */
20094 #define MDMA_CCR_WEX              MDMA_CCR_WEX_Msk                             /*!< Word Endianess eXchange */
20095 #define MDMA_CCR_SWRQ_Pos         (16U)
20096 #define MDMA_CCR_SWRQ_Msk         (0x1U << MDMA_CCR_SWRQ_Pos)                  /*!< 0x00010000 */
20097 #define MDMA_CCR_SWRQ             MDMA_CCR_SWRQ_Msk                            /*!< SW ReQuest */
20098 
20099 /********************  Bit definition for MDMA_CxTCR register  ****************/
20100 #define MDMA_CTCR_SINC_Pos        (0U)
20101 #define MDMA_CTCR_SINC_Msk        (0x3U << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000003 */
20102 #define MDMA_CTCR_SINC            MDMA_CTCR_SINC_Msk                           /*!< Source increment mode */
20103 #define MDMA_CTCR_SINC_0          (0x1U << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000001 */
20104 #define MDMA_CTCR_SINC_1          (0x2U << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000002 */
20105 #define MDMA_CTCR_DINC_Pos        (2U)
20106 #define MDMA_CTCR_DINC_Msk        (0x3U << MDMA_CTCR_DINC_Pos)                 /*!< 0x0000000C */
20107 #define MDMA_CTCR_DINC            MDMA_CTCR_DINC_Msk                           /*!< Source increment mode */
20108 #define MDMA_CTCR_DINC_0          (0x1U << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000004 */
20109 #define MDMA_CTCR_DINC_1          (0x2U << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000008 */
20110 #define MDMA_CTCR_SSIZE_Pos       (4U)
20111 #define MDMA_CTCR_SSIZE_Msk       (0x3U << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000030 */
20112 #define MDMA_CTCR_SSIZE           MDMA_CTCR_SSIZE_Msk                          /*!< Source data size */
20113 #define MDMA_CTCR_SSIZE_0         (0x1U << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000010 */
20114 #define MDMA_CTCR_SSIZE_1         (0x2U << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000020 */
20115 #define MDMA_CTCR_DSIZE_Pos       (6U)
20116 #define MDMA_CTCR_DSIZE_Msk       (0x3U << MDMA_CTCR_DSIZE_Pos)                /*!< 0x000000C0 */
20117 #define MDMA_CTCR_DSIZE           MDMA_CTCR_DSIZE_Msk                          /*!< Destination data size */
20118 #define MDMA_CTCR_DSIZE_0         (0x1U << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000040 */
20119 #define MDMA_CTCR_DSIZE_1         (0x2U << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000080 */
20120 #define MDMA_CTCR_SINCOS_Pos      (8U)
20121 #define MDMA_CTCR_SINCOS_Msk      (0x3U << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000300 */
20122 #define MDMA_CTCR_SINCOS          MDMA_CTCR_SINCOS_Msk                         /*!< Source increment offset size */
20123 #define MDMA_CTCR_SINCOS_0        (0x1U << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000100 */
20124 #define MDMA_CTCR_SINCOS_1        (0x2U << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000200 */
20125 #define MDMA_CTCR_DINCOS_Pos      (10U)
20126 #define MDMA_CTCR_DINCOS_Msk      (0x3U << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000C00 */
20127 #define MDMA_CTCR_DINCOS          MDMA_CTCR_DINCOS_Msk                         /*!< Destination increment offset size */
20128 #define MDMA_CTCR_DINCOS_0        (0x1U << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000400 */
20129 #define MDMA_CTCR_DINCOS_1        (0x2U << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000800 */
20130 #define MDMA_CTCR_SBURST_Pos      (12U)
20131 #define MDMA_CTCR_SBURST_Msk      (0x7U << MDMA_CTCR_SBURST_Pos)               /*!< 0x00007000 */
20132 #define MDMA_CTCR_SBURST          MDMA_CTCR_SBURST_Msk                         /*!< Source burst transfer configuration */
20133 #define MDMA_CTCR_SBURST_0        (0x1U << MDMA_CTCR_SBURST_Pos)               /*!< 0x00001000 */
20134 #define MDMA_CTCR_SBURST_1        (0x2U << MDMA_CTCR_SBURST_Pos)               /*!< 0x00002000 */
20135 #define MDMA_CTCR_SBURST_2        (0x3U << MDMA_CTCR_SBURST_Pos)               /*!< 0x00003000 */
20136 #define MDMA_CTCR_DBURST_Pos      (15U)
20137 #define MDMA_CTCR_DBURST_Msk      (0x7U << MDMA_CTCR_DBURST_Pos)               /*!< 0x00038000 */
20138 #define MDMA_CTCR_DBURST          MDMA_CTCR_DBURST_Msk                         /*!< Destination burst transfer configuration */
20139 #define MDMA_CTCR_DBURST_0        (0x1U << MDMA_CTCR_DBURST_Pos)               /*!< 0x00008000 */
20140 #define MDMA_CTCR_DBURST_1        (0x2U << MDMA_CTCR_DBURST_Pos)               /*!< 0x00010000 */
20141 #define MDMA_CTCR_DBURST_2        (0x4U << MDMA_CTCR_DBURST_Pos)               /*!< 0x00020000 */
20142 #define MDMA_CTCR_TLEN_Pos        (18U)
20143 #define MDMA_CTCR_TLEN_Msk        (0x7FU << MDMA_CTCR_TLEN_Pos)                /*!< 0x01FC0000 */
20144 #define MDMA_CTCR_TLEN            MDMA_CTCR_TLEN_Msk                           /*!< buffer Transfer Length (number of bytes - 1) */
20145 #define MDMA_CTCR_PKE_Pos         (25U)
20146 #define MDMA_CTCR_PKE_Msk         (0x1U << MDMA_CTCR_PKE_Pos)                  /*!< 0x02000000 */
20147 #define MDMA_CTCR_PKE             MDMA_CTCR_PKE_Msk                            /*!< PacK Enable */
20148 #define MDMA_CTCR_PAM_Pos         (26U)
20149 #define MDMA_CTCR_PAM_Msk         (0x3U << MDMA_CTCR_PAM_Pos)                  /*!< 0x0C000000 */
20150 #define MDMA_CTCR_PAM             MDMA_CTCR_PAM_Msk                            /*!< Padding/Alignement Mode */
20151 #define MDMA_CTCR_PAM_0           (0x1U << MDMA_CTCR_PAM_Pos)                  /*!< 0x4000000 */
20152 #define MDMA_CTCR_PAM_1           (0x2U << MDMA_CTCR_PAM_Pos)                  /*!< 0x8000000 */
20153 #define MDMA_CTCR_TRGM_Pos        (28U)
20154 #define MDMA_CTCR_TRGM_Msk        (0x3U << MDMA_CTCR_TRGM_Pos)                 /*!< 0x30000000 */
20155 #define MDMA_CTCR_TRGM            MDMA_CTCR_TRGM_Msk                           /*!< Trigger Mode */
20156 #define MDMA_CTCR_TRGM_0          (0x1U << MDMA_CTCR_TRGM_Pos)                 /*!< 0x10000000 */
20157 #define MDMA_CTCR_TRGM_1          (0x2U << MDMA_CTCR_TRGM_Pos)                 /*!< 0x20000000 */
20158 #define MDMA_CTCR_SWRM_Pos        (30U)
20159 #define MDMA_CTCR_SWRM_Msk        (0x1U << MDMA_CTCR_SWRM_Pos)                 /*!< 0x40000000 */
20160 #define MDMA_CTCR_SWRM            MDMA_CTCR_SWRM_Msk                           /*!< SW Request Mode */
20161 #define MDMA_CTCR_BWM_Pos         (31U)
20162 #define MDMA_CTCR_BWM_Msk         (0x1U << MDMA_CTCR_BWM_Pos)                  /*!< 0x80000000 */
20163 #define MDMA_CTCR_BWM             MDMA_CTCR_BWM_Msk                            /*!< Bufferable Write Mode */
20164 
20165 /********************  Bit definition for MDMA_CxBNDTR register  ****************/
20166 #define MDMA_CBNDTR_BNDT_Pos      (0U)
20167 #define MDMA_CBNDTR_BNDT_Msk      (0x1FFFFU << MDMA_CBNDTR_BNDT_Pos)           /*!< 0x0001FFFF */
20168 #define MDMA_CBNDTR_BNDT          MDMA_CBNDTR_BNDT_Msk                         /*!< Block Number of data bytes to transfer */
20169 #define MDMA_CBNDTR_BRSUM_Pos     (18U)
20170 #define MDMA_CBNDTR_BRSUM_Msk     (0x1U << MDMA_CBNDTR_BRSUM_Pos)              /*!< 0x00040000 */
20171 #define MDMA_CBNDTR_BRSUM         MDMA_CBNDTR_BRSUM_Msk                        /*!< Block Repeat Source address Update Mode */
20172 #define MDMA_CBNDTR_BRDUM_Pos     (19U)
20173 #define MDMA_CBNDTR_BRDUM_Msk     (0x1U << MDMA_CBNDTR_BRDUM_Pos)              /*!< 0x00080000 */
20174 #define MDMA_CBNDTR_BRDUM         MDMA_CBNDTR_BRDUM_Msk                        /*!< Block Repeat Destination address Update Mode */
20175 #define MDMA_CBNDTR_BRC_Pos       (20U)
20176 #define MDMA_CBNDTR_BRC_Msk       (0xFFFU << MDMA_CBNDTR_BRC_Pos)              /*!< 0xFFF00000 */
20177 #define MDMA_CBNDTR_BRC           MDMA_CBNDTR_BRC_Msk                          /*!< Block Repeat Count */
20178 
20179 /********************  Bit definition for MDMA_CxSAR register  ****************/
20180 #define MDMA_CSAR_SAR_Pos         (0U)
20181 #define MDMA_CSAR_SAR_Msk         (0xFFFFFFFFU << MDMA_CSAR_SAR_Pos)           /*!< 0xFFFFFFFF */
20182 #define MDMA_CSAR_SAR             MDMA_CSAR_SAR_Msk                            /*!< Source address */
20183 
20184 /********************  Bit definition for MDMA_CxDAR register  ****************/
20185 #define MDMA_CDAR_DAR_Pos         (0U)
20186 #define MDMA_CDAR_DAR_Msk         (0xFFFFFFFFU << MDMA_CDAR_DAR_Pos)           /*!< 0xFFFFFFFF */
20187 #define MDMA_CDAR_DAR             MDMA_CDAR_DAR_Msk                            /*!< Destination address */
20188 
20189 /********************  Bit definition for MDMA_CxBRUR  ************************/
20190 #define MDMA_CBRUR_SUV_Pos        (0U)
20191 #define MDMA_CBRUR_SUV_Msk        (0xFFFFU << MDMA_CBRUR_SUV_Pos)              /*!< 0x0000FFFF */
20192 #define MDMA_CBRUR_SUV            MDMA_CBRUR_SUV_Msk                           /*!< Source address Update Value */
20193 #define MDMA_CBRUR_DUV_Pos        (16U)
20194 #define MDMA_CBRUR_DUV_Msk        (0xFFFFU << MDMA_CBRUR_DUV_Pos)              /*!< 0xFFFF0000 */
20195 #define MDMA_CBRUR_DUV            MDMA_CBRUR_DUV_Msk                           /*!< Destination address Update Value */
20196 
20197 /********************  Bit definition for MDMA_CxLAR  *************************/
20198 #define MDMA_CLAR_LAR_Pos         (0U)
20199 #define MDMA_CLAR_LAR_Msk         (0xFFFFFFFFU << MDMA_CLAR_LAR_Pos)           /*!< 0xFFFFFFFF */
20200 #define MDMA_CLAR_LAR             MDMA_CLAR_LAR_Msk                            /*!< Link Address Register */
20201 
20202 /********************  Bit definition for MDMA_CxTBR)  ************************/
20203 #define MDMA_CTBR_TSEL_Pos        (0U)
20204 #define MDMA_CTBR_TSEL_Msk        (0xFFU << MDMA_CTBR_TSEL_Pos)                /*!< 0x000000FF */
20205 #define MDMA_CTBR_TSEL            MDMA_CTBR_TSEL_Msk                           /*!< Trigger SELection */
20206 #define MDMA_CTBR_SBUS_Pos        (16U)
20207 #define MDMA_CTBR_SBUS_Msk        (0x1U << MDMA_CTBR_SBUS_Pos)                 /*!< 0x00010000 */
20208 #define MDMA_CTBR_SBUS            MDMA_CTBR_SBUS_Msk                           /*!< Source BUS select */
20209 #define MDMA_CTBR_DBUS_Pos        (17U)
20210 #define MDMA_CTBR_DBUS_Msk        (0x1U << MDMA_CTBR_DBUS_Pos)                 /*!< 0x00020000 */
20211 #define MDMA_CTBR_DBUS            MDMA_CTBR_DBUS_Msk                           /*!< Destination BUS select */
20212 
20213 /********************  Bit definition for MDMA_CxMAR)  ************************/
20214 #define MDMA_CMAR_MAR_Pos         (0U)
20215 #define MDMA_CMAR_MAR_Msk         (0xFFFFFFFFU << MDMA_CMAR_MAR_Pos)           /*!< 0xFFFFFFFF */
20216 #define MDMA_CMAR_MAR             MDMA_CMAR_MAR_Msk                            /*!< Mask address */
20217 
20218 /********************  Bit definition for MDMA_CxMDR)  ************************/
20219 #define MDMA_CMDR_MDR_Pos         (0U)
20220 #define MDMA_CMDR_MDR_Msk         (0xFFFFFFFFU << MDMA_CMDR_MDR_Pos)           /*!< 0xFFFFFFFF */
20221 #define MDMA_CMDR_MDR             MDMA_CMDR_MDR_Msk                            /*!< Mask address */
20222 
20223 /******************************************************************************/
20224 /*                                                                            */
20225 /*                         Operational Amplifier (OPAMP)                      */
20226 /*                                                                            */
20227 /******************************************************************************/
20228 /*********************  Bit definition for OPAMPx_CSR register  ***************/
20229 #define OPAMP_CSR_OPAMPxEN_Pos           (0U)
20230 #define OPAMP_CSR_OPAMPxEN_Msk           (0x1U << OPAMP_CSR_OPAMPxEN_Pos)      /*!< 0x00000001 */
20231 #define OPAMP_CSR_OPAMPxEN               OPAMP_CSR_OPAMPxEN_Msk                /*!< OPAMP enable */
20232 #define OPAMP_CSR_FORCEVP_Pos            (1U)
20233 #define OPAMP_CSR_FORCEVP_Msk            (0x1U << OPAMP_CSR_FORCEVP_Pos)       /*!< 0x00000002 */
20234 #define OPAMP_CSR_FORCEVP                OPAMP_CSR_FORCEVP_Msk                 /*!< Force internal reference on VP */
20235 
20236 #define OPAMP_CSR_VPSEL_Pos              (2U)
20237 #define OPAMP_CSR_VPSEL_Msk              (0x3U << OPAMP_CSR_VPSEL_Pos)         /*!< 0x0000000C */
20238 #define OPAMP_CSR_VPSEL                  OPAMP_CSR_VPSEL_Msk                   /*!< Non inverted input selection */
20239 #define OPAMP_CSR_VPSEL_0                (0x1U << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000004 */
20240 #define OPAMP_CSR_VPSEL_1                (0x2U << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000008 */
20241 
20242 #define OPAMP_CSR_VMSEL_Pos              (5U)
20243 #define OPAMP_CSR_VMSEL_Msk              (0x3U << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000060 */
20244 #define OPAMP_CSR_VMSEL                  OPAMP_CSR_VMSEL_Msk                   /*!< Inverting input selection */
20245 #define OPAMP_CSR_VMSEL_0                (0x1U << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000020 */
20246 #define OPAMP_CSR_VMSEL_1                (0x2U << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000040 */
20247 
20248 #define OPAMP_CSR_OPAHSM_Pos             (8U)
20249 #define OPAMP_CSR_OPAHSM_Msk             (0x1U << OPAMP_CSR_OPAHSM_Pos)        /*!< 0x00000100 */
20250 #define OPAMP_CSR_OPAHSM                 OPAMP_CSR_OPAHSM_Msk                  /*!< Operational amplifier high speed mode */
20251 #define OPAMP_CSR_CALON_Pos              (11U)
20252 #define OPAMP_CSR_CALON_Msk              (0x1U << OPAMP_CSR_CALON_Pos)         /*!< 0x00000800 */
20253 #define OPAMP_CSR_CALON                  OPAMP_CSR_CALON_Msk                   /*!< Calibration mode enable */
20254 
20255 #define OPAMP_CSR_CALSEL_Pos             (12U)
20256 #define OPAMP_CSR_CALSEL_Msk             (0x3U << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00003000 */
20257 #define OPAMP_CSR_CALSEL                 OPAMP_CSR_CALSEL_Msk                  /*!< Calibration selection */
20258 #define OPAMP_CSR_CALSEL_0               (0x1U << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00001000 */
20259 #define OPAMP_CSR_CALSEL_1               (0x2U << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00002000 */
20260 
20261 #define OPAMP_CSR_PGGAIN_Pos             (14U)
20262 #define OPAMP_CSR_PGGAIN_Msk             (0xFU << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x0003C000 */
20263 #define OPAMP_CSR_PGGAIN                 OPAMP_CSR_PGGAIN_Msk                  /*!< Operational amplifier Programmable amplifier gain value */
20264 #define OPAMP_CSR_PGGAIN_0               (0x1U << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00004000 */
20265 #define OPAMP_CSR_PGGAIN_1               (0x2U << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00008000 */
20266 #define OPAMP_CSR_PGGAIN_2               (0x4U << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00010000 */
20267 #define OPAMP_CSR_PGGAIN_3               (0x8U << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00020000 */
20268 
20269 #define OPAMP_CSR_USERTRIM_Pos           (18U)
20270 #define OPAMP_CSR_USERTRIM_Msk           (0x1U << OPAMP_CSR_USERTRIM_Pos)      /*!< 0x00040000 */
20271 #define OPAMP_CSR_USERTRIM               OPAMP_CSR_USERTRIM_Msk                /*!< User trimming enable */
20272 #define OPAMP_CSR_TSTREF_Pos             (29U)
20273 #define OPAMP_CSR_TSTREF_Msk             (0x1U << OPAMP_CSR_TSTREF_Pos)        /*!< 0x20000000 */
20274 #define OPAMP_CSR_TSTREF                 OPAMP_CSR_TSTREF_Msk                  /*!< OpAmp calibration reference voltage output control */
20275 #define OPAMP_CSR_CALOUT_Pos             (30U)
20276 #define OPAMP_CSR_CALOUT_Msk             (0x1U << OPAMP_CSR_CALOUT_Pos)        /*!< 0x40000000 */
20277 #define OPAMP_CSR_CALOUT                 OPAMP_CSR_CALOUT_Msk                  /*!< Operational amplifier calibration output */
20278 
20279 /*********************  Bit definition for OPAMP1_CSR register  ***************/
20280 #define OPAMP1_CSR_OPAEN_Pos              (0U)
20281 #define OPAMP1_CSR_OPAEN_Msk              (0x1U << OPAMP1_CSR_OPAEN_Pos)       /*!< 0x00000001 */
20282 #define OPAMP1_CSR_OPAEN                  OPAMP1_CSR_OPAEN_Msk                 /*!< Operational amplifier1 Enable */
20283 #define OPAMP1_CSR_FORCEVP_Pos            (1U)
20284 #define OPAMP1_CSR_FORCEVP_Msk            (0x1U << OPAMP1_CSR_FORCEVP_Pos)     /*!< 0x00000002 */
20285 #define OPAMP1_CSR_FORCEVP                OPAMP1_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */
20286 
20287 #define OPAMP1_CSR_VPSEL_Pos              (2U)
20288 #define OPAMP1_CSR_VPSEL_Msk              (0x3U << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x0000000C */
20289 #define OPAMP1_CSR_VPSEL                  OPAMP1_CSR_VPSEL_Msk                 /*!< Non inverted input selection */
20290 #define OPAMP1_CSR_VPSEL_0                (0x1U << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000004 */
20291 #define OPAMP1_CSR_VPSEL_1                (0x2U << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000008 */
20292 
20293 #define OPAMP1_CSR_VMSEL_Pos              (5U)
20294 #define OPAMP1_CSR_VMSEL_Msk              (0x3U << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000060 */
20295 #define OPAMP1_CSR_VMSEL                  OPAMP1_CSR_VMSEL_Msk                 /*!< Inverting input selection */
20296 #define OPAMP1_CSR_VMSEL_0                (0x1U << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000020 */
20297 #define OPAMP1_CSR_VMSEL_1                (0x2U << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000040 */
20298 
20299 #define OPAMP1_CSR_OPAHSM_Pos             (8U)
20300 #define OPAMP1_CSR_OPAHSM_Msk             (0x1U << OPAMP1_CSR_OPAHSM_Pos)      /*!< 0x00000100 */
20301 #define OPAMP1_CSR_OPAHSM                 OPAMP1_CSR_OPAHSM_Msk                /*!< Operational amplifier1 high speed mode */
20302 #define OPAMP1_CSR_CALON_Pos              (11U)
20303 #define OPAMP1_CSR_CALON_Msk              (0x1U << OPAMP1_CSR_CALON_Pos)       /*!< 0x00000800 */
20304 #define OPAMP1_CSR_CALON                  OPAMP1_CSR_CALON_Msk                 /*!< Calibration mode enable */
20305 
20306 #define OPAMP1_CSR_CALSEL_Pos             (12U)
20307 #define OPAMP1_CSR_CALSEL_Msk             (0x3U << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00003000 */
20308 #define OPAMP1_CSR_CALSEL                 OPAMP1_CSR_CALSEL_Msk                /*!< Calibration selection */
20309 #define OPAMP1_CSR_CALSEL_0               (0x1U << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00001000 */
20310 #define OPAMP1_CSR_CALSEL_1               (0x2U << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00002000 */
20311 
20312 #define OPAMP1_CSR_PGGAIN_Pos             (14U)
20313 #define OPAMP1_CSR_PGGAIN_Msk             (0xFU << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x0003C000 */
20314 #define OPAMP1_CSR_PGGAIN                 OPAMP1_CSR_PGGAIN_Msk                /*!< Operational amplifier1 Programmable amplifier gain value */
20315 #define OPAMP1_CSR_PGGAIN_0               (0x1U << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00004000 */
20316 #define OPAMP1_CSR_PGGAIN_1               (0x2U << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00008000 */
20317 #define OPAMP1_CSR_PGGAIN_2               (0x4U << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00010000 */
20318 #define OPAMP1_CSR_PGGAIN_3               (0x8U << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00020000 */
20319 
20320 #define OPAMP1_CSR_USERTRIM_Pos           (18U)
20321 #define OPAMP1_CSR_USERTRIM_Msk           (0x1U << OPAMP1_CSR_USERTRIM_Pos)    /*!< 0x00040000 */
20322 #define OPAMP1_CSR_USERTRIM               OPAMP1_CSR_USERTRIM_Msk              /*!< User trimming enable */
20323 #define OPAMP1_CSR_TSTREF_Pos             (29U)
20324 #define OPAMP1_CSR_TSTREF_Msk             (0x1U << OPAMP1_CSR_TSTREF_Pos)      /*!< 0x20000000 */
20325 #define OPAMP1_CSR_TSTREF                 OPAMP1_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */
20326 #define OPAMP1_CSR_CALOUT_Pos             (30U)
20327 #define OPAMP1_CSR_CALOUT_Msk             (0x1U << OPAMP1_CSR_CALOUT_Pos)      /*!< 0x40000000 */
20328 #define OPAMP1_CSR_CALOUT                 OPAMP1_CSR_CALOUT_Msk                /*!< Operational amplifier1 calibration output */
20329 
20330 /*********************  Bit definition for OPAMP2_CSR register  ***************/
20331 #define OPAMP2_CSR_OPAEN_Pos              (0U)
20332 #define OPAMP2_CSR_OPAEN_Msk              (0x1U << OPAMP2_CSR_OPAEN_Pos)       /*!< 0x00000001 */
20333 #define OPAMP2_CSR_OPAEN                  OPAMP2_CSR_OPAEN_Msk                 /*!< Operational amplifier2 Enable */
20334 #define OPAMP2_CSR_FORCEVP_Pos            (1U)
20335 #define OPAMP2_CSR_FORCEVP_Msk            (0x1U << OPAMP2_CSR_FORCEVP_Pos)     /*!< 0x00000002 */
20336 #define OPAMP2_CSR_FORCEVP                OPAMP2_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */
20337 
20338 #define OPAMP2_CSR_VPSEL_Pos              (2U)
20339 #define OPAMP2_CSR_VPSEL_Msk              (0x3U << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x0000000C */
20340 #define OPAMP2_CSR_VPSEL                  OPAMP2_CSR_VPSEL_Msk                 /*!< Non inverted input selection */
20341 #define OPAMP2_CSR_VPSEL_0                (0x1U << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000004 */
20342 #define OPAMP2_CSR_VPSEL_1                (0x2U << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000008 */
20343 
20344 #define OPAMP2_CSR_VMSEL_Pos              (5U)
20345 #define OPAMP2_CSR_VMSEL_Msk              (0x3U << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000060 */
20346 #define OPAMP2_CSR_VMSEL                  OPAMP2_CSR_VMSEL_Msk                 /*!< Inverting input selection */
20347 #define OPAMP2_CSR_VMSEL_0                (0x1U << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000020 */
20348 #define OPAMP2_CSR_VMSEL_1                (0x2U << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000040 */
20349 
20350 #define OPAMP2_CSR_OPAHSM_Pos             (8U)
20351 #define OPAMP2_CSR_OPAHSM_Msk             (0x1U << OPAMP2_CSR_OPAHSM_Pos)      /*!< 0x00000100 */
20352 #define OPAMP2_CSR_OPAHSM                 OPAMP2_CSR_OPAHSM_Msk                /*!< Operational amplifier2 high speed mode */
20353 #define OPAMP2_CSR_CALON_Pos              (11U)
20354 #define OPAMP2_CSR_CALON_Msk              (0x1U << OPAMP2_CSR_CALON_Pos)       /*!< 0x00000800 */
20355 #define OPAMP2_CSR_CALON                  OPAMP2_CSR_CALON_Msk                 /*!< Calibration mode enable */
20356 
20357 #define OPAMP2_CSR_CALSEL_Pos             (12U)
20358 #define OPAMP2_CSR_CALSEL_Msk             (0x3U << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00003000 */
20359 #define OPAMP2_CSR_CALSEL                 OPAMP2_CSR_CALSEL_Msk                /*!< Calibration selection */
20360 #define OPAMP2_CSR_CALSEL_0               (0x1U << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00001000 */
20361 #define OPAMP2_CSR_CALSEL_1               (0x2U << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00002000 */
20362 
20363 #define OPAMP2_CSR_PGGAIN_Pos             (14U)
20364 #define OPAMP2_CSR_PGGAIN_Msk             (0xFU << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x0003C000 */
20365 #define OPAMP2_CSR_PGGAIN                 OPAMP2_CSR_PGGAIN_Msk                /*!< Operational amplifier2 Programmable amplifier gain value */
20366 #define OPAMP2_CSR_PGGAIN_0               (0x1U << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00004000 */
20367 #define OPAMP2_CSR_PGGAIN_1               (0x2U << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00008000 */
20368 #define OPAMP2_CSR_PGGAIN_2               (0x4U << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00010000 */
20369 #define OPAMP2_CSR_PGGAIN_3               (0x8U << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00020000 */
20370 
20371 #define OPAMP2_CSR_USERTRIM_Pos           (18U)
20372 #define OPAMP2_CSR_USERTRIM_Msk           (0x1U << OPAMP2_CSR_USERTRIM_Pos)    /*!< 0x00040000 */
20373 #define OPAMP2_CSR_USERTRIM               OPAMP2_CSR_USERTRIM_Msk              /*!< User trimming enable */
20374 #define OPAMP2_CSR_TSTREF_Pos             (29U)
20375 #define OPAMP2_CSR_TSTREF_Msk             (0x1U << OPAMP2_CSR_TSTREF_Pos)      /*!< 0x20000000 */
20376 #define OPAMP2_CSR_TSTREF                 OPAMP2_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */
20377 #define OPAMP2_CSR_CALOUT_Pos             (30U)
20378 #define OPAMP2_CSR_CALOUT_Msk             (0x1U << OPAMP2_CSR_CALOUT_Pos)      /*!< 0x40000000 */
20379 #define OPAMP2_CSR_CALOUT                 OPAMP2_CSR_CALOUT_Msk                /*!< Operational amplifier2 calibration output */
20380 
20381 /*******************  Bit definition for OPAMP_OTR register  ******************/
20382 #define OPAMP_OTR_TRIMOFFSETN_Pos        (0U)
20383 #define OPAMP_OTR_TRIMOFFSETN_Msk        (0x1FU << OPAMP_OTR_TRIMOFFSETN_Pos)  /*!< 0x0000001F */
20384 #define OPAMP_OTR_TRIMOFFSETN            OPAMP_OTR_TRIMOFFSETN_Msk             /*!< Trim for NMOS differential pairs */
20385 #define OPAMP_OTR_TRIMOFFSETP_Pos        (8U)
20386 #define OPAMP_OTR_TRIMOFFSETP_Msk        (0x1FU << OPAMP_OTR_TRIMOFFSETP_Pos)  /*!< 0x00001F00 */
20387 #define OPAMP_OTR_TRIMOFFSETP            OPAMP_OTR_TRIMOFFSETP_Msk             /*!< Trim for PMOS differential pairs */
20388 
20389 /*******************  Bit definition for OPAMP1_OTR register  ******************/
20390 #define OPAMP1_OTR_TRIMOFFSETN_Pos        (0U)
20391 #define OPAMP1_OTR_TRIMOFFSETN_Msk        (0x1FU << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
20392 #define OPAMP1_OTR_TRIMOFFSETN            OPAMP1_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */
20393 #define OPAMP1_OTR_TRIMOFFSETP_Pos        (8U)
20394 #define OPAMP1_OTR_TRIMOFFSETP_Msk        (0x1FU << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
20395 #define OPAMP1_OTR_TRIMOFFSETP            OPAMP1_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */
20396 
20397 /*******************  Bit definition for OPAMP2_OTR register  ******************/
20398 #define OPAMP2_OTR_TRIMOFFSETN_Pos        (0U)
20399 #define OPAMP2_OTR_TRIMOFFSETN_Msk        (0x1FU << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
20400 #define OPAMP2_OTR_TRIMOFFSETN            OPAMP2_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */
20401 #define OPAMP2_OTR_TRIMOFFSETP_Pos        (8U)
20402 #define OPAMP2_OTR_TRIMOFFSETP_Msk        (0x1FU << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
20403 #define OPAMP2_OTR_TRIMOFFSETP            OPAMP2_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */
20404 
20405 /*******************  Bit definition for OPAMP_HSOTR register  ****************/
20406 #define OPAMP_HSOTR_TRIMHSOFFSETN_Pos    (0U)
20407 #define OPAMP_HSOTR_TRIMHSOFFSETN_Msk    (0x1FU << OPAMP_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
20408 #define OPAMP_HSOTR_TRIMHSOFFSETN        OPAMP_HSOTR_TRIMHSOFFSETN_Msk         /*!< Trim for NMOS differential pairs */
20409 #define OPAMP_HSOTR_TRIMHSOFFSETP_Pos    (8U)
20410 #define OPAMP_HSOTR_TRIMHSOFFSETP_Msk    (0x1FU << OPAMP_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
20411 #define OPAMP_HSOTR_TRIMHSOFFSETP        OPAMP_HSOTR_TRIMHSOFFSETP_Msk         /*!< Trim for PMOS differential pairs */
20412 
20413 /*******************  Bit definition for OPAMP1_HSOTR register  ****************/
20414 #define OPAMP1_HSOTR_TRIMHSOFFSETN_Pos    (0U)
20415 #define OPAMP1_HSOTR_TRIMHSOFFSETN_Msk    (0x1FU << OPAMP1_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
20416 #define OPAMP1_HSOTR_TRIMHSOFFSETN        OPAMP1_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */
20417 #define OPAMP1_HSOTR_TRIMHSOFFSETP_Pos    (8U)
20418 #define OPAMP1_HSOTR_TRIMHSOFFSETP_Msk    (0x1FU << OPAMP1_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
20419 #define OPAMP1_HSOTR_TRIMHSOFFSETP        OPAMP1_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */
20420 
20421 /*******************  Bit definition for OPAMP2_HSOTR register  ****************/
20422 #define OPAMP2_HSOTR_TRIMHSOFFSETN_Pos    (0U)
20423 #define OPAMP2_HSOTR_TRIMHSOFFSETN_Msk    (0x1FU << OPAMP2_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
20424 #define OPAMP2_HSOTR_TRIMHSOFFSETN        OPAMP2_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */
20425 #define OPAMP2_HSOTR_TRIMHSOFFSETP_Pos    (8U)
20426 #define OPAMP2_HSOTR_TRIMHSOFFSETP_Msk    (0x1FU << OPAMP2_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
20427 #define OPAMP2_HSOTR_TRIMHSOFFSETP        OPAMP2_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */
20428 
20429 /******************************************************************************/
20430 /*                                                                            */
20431 /*                             Power Control                                  */
20432 /*                                                                            */
20433 /******************************************************************************/
20434 
20435 /********************  Bit definition for PWR_CR1 register  ********************/
20436 #define PWR_CR1_RESERVED3_Pos          (19U)
20437 #define PWR_CR1_RESERVED3_Msk          (0x1FFFU << PWR_CR1_RESERVED3_Pos)      /*!< 0xFFF80000 */
20438 #define PWR_CR1_RESERVED3              PWR_CR1_RESERVED3_Msk                   /*!< Reserved, must be kept at reset value */
20439 #define PWR_CR1_ALS_Pos                (17U)
20440 #define PWR_CR1_ALS_Msk                (0x3U << PWR_CR1_ALS_Pos)               /*!< 0x00060000 */
20441 #define PWR_CR1_ALS                    PWR_CR1_ALS_Msk                         /*!< Analog Voltage Detector level selection */
20442 #define PWR_CR1_AVDEN_Pos              (16U)
20443 #define PWR_CR1_AVDEN_Msk              (0x1U << PWR_CR1_AVDEN_Pos)             /*!< 0x00010000 */
20444 #define PWR_CR1_AVDEN                  PWR_CR1_AVDEN_Msk                       /*!< Peripheral Voltage Monitor on VDDA enable */
20445 #define PWR_CR1_RESERVED2_Pos          (11U)
20446 #define PWR_CR1_RESERVED2_Msk          (0x1FU << PWR_CR1_RESERVED2_Pos)        /*!< 0x0000F800 */
20447 #define PWR_CR1_RESERVED2              PWR_CR1_RESERVED2_Msk                   /*!< Reserved, must be kept at reset value */
20448 #define PWR_CR1_RESERVED1_Pos          (9U)
20449 #define PWR_CR1_RESERVED1_Msk          (0x1U << PWR_CR1_RESERVED1_Pos)         /*!< 0x00000200 */
20450 #define PWR_CR1_RESERVED1              PWR_CR1_RESERVED1_Msk                   /*!< Reserved, must be kept at reset value */
20451 #define PWR_CR1_DBP_Pos                (8U)
20452 #define PWR_CR1_DBP_Msk                (0x1U << PWR_CR1_DBP_Pos)               /*!< 0x00000100 */
20453 #define PWR_CR1_DBP                    PWR_CR1_DBP_Msk                         /*!< Disable Back-up domain Protection */
20454 #define PWR_CR1_PLS_Pos                (5U)
20455 #define PWR_CR1_PLS_Msk                (0x7U << PWR_CR1_PLS_Pos)               /*!< 0x000000E0 */
20456 #define PWR_CR1_PLS                    PWR_CR1_PLS_Msk                         /*!< Programmable Voltage Detector level selection */
20457 #define PWR_CR1_PVDEN_Pos              (4U)
20458 #define PWR_CR1_PVDEN_Msk              (0x1U << PWR_CR1_PVDEN_Pos)             /*!< 0x00000010 */
20459 #define PWR_CR1_PVDEN                  PWR_CR1_PVDEN_Msk                       /*!< Programmable Voltage detector enable */
20460 #define PWR_CR1_RESERVED0_Pos          (3U)
20461 #define PWR_CR1_RESERVED0_Msk          (0x1U << PWR_CR1_RESERVED0_Pos)         /*!< 0x00000008 */
20462 #define PWR_CR1_RESERVED0              PWR_CR1_RESERVED0_Msk                   /*!< Reserved, must be kept at reset value */
20463 #define PWR_CR1_LVDS_Pos               (2U)
20464 #define PWR_CR1_LVDS_Msk               (0x1U << PWR_CR1_LVDS_Pos)              /*!< 0x00000004 */
20465 #define PWR_CR1_LVDS                   PWR_CR1_LVDS_Msk                        /*!< Low Voltage Deepsleep LP-STOP mode selection */
20466 #define PWR_CR1_LPCFG_Pos              (1U)
20467 #define PWR_CR1_LPCFG_Msk              (0x1U << PWR_CR1_LPCFG_Pos)             /*!< 0x00000002 */
20468 #define PWR_CR1_LPCFG                  PWR_CR1_LPCFG_Msk                       /*!< PWR_ON pin configuration */
20469 #define PWR_CR1_LPDS_Pos               (0U)
20470 #define PWR_CR1_LPDS_Msk               (0x1U << PWR_CR1_LPDS_Pos)              /*!< 0x00000001 */
20471 #define PWR_CR1_LPDS                   PWR_CR1_LPDS_Msk                        /*!< Low Power Deepsleep STOP mode selection */
20472 
20473 /*!< AVD level configuration */
20474 #define PWR_CR1_ALS_LEV0               ((uint32_t)0x00000000)                  /*!< AVD level 0 */
20475 #define PWR_CR1_ALS_LEV1_Pos           (17U)
20476 #define PWR_CR1_ALS_LEV1_Msk           (0x1U << PWR_CR1_ALS_LEV1_Pos)          /*!< 0x00020000 */
20477 #define PWR_CR1_ALS_LEV1               PWR_CR1_ALS_LEV1_Msk                    /*!< AVD level 1 */
20478 #define PWR_CR1_ALS_LEV2_Pos           (18U)
20479 #define PWR_CR1_ALS_LEV2_Msk           (0x1U << PWR_CR1_ALS_LEV2_Pos)          /*!< 0x00040000 */
20480 #define PWR_CR1_ALS_LEV2               PWR_CR1_ALS_LEV2_Msk                    /*!< AVD level 2 */
20481 #define PWR_CR1_ALS_LEV3_Pos           (17U)
20482 #define PWR_CR1_ALS_LEV3_Msk           (0x3U << PWR_CR1_ALS_LEV3_Pos)          /*!< 0x00060000 */
20483 #define PWR_CR1_ALS_LEV3               PWR_CR1_ALS_LEV3_Msk                    /*!< AVD level 3 */
20484 
20485 /*!< PVD level configuration */
20486 #define PWR_CR1_PLS_LEV0               ((uint32_t)0x00000000)                  /*!< PVD level 0 */
20487 #define PWR_CR1_PLS_LEV1_Pos           (5U)
20488 #define PWR_CR1_PLS_LEV1_Msk           (0x1U << PWR_CR1_PLS_LEV1_Pos)          /*!< 0x00000020 */
20489 #define PWR_CR1_PLS_LEV1               PWR_CR1_PLS_LEV1_Msk                    /*!< PVD level 1 */
20490 #define PWR_CR1_PLS_LEV2_Pos           (6U)
20491 #define PWR_CR1_PLS_LEV2_Msk           (0x1U << PWR_CR1_PLS_LEV2_Pos)          /*!< 0x00000040 */
20492 #define PWR_CR1_PLS_LEV2               PWR_CR1_PLS_LEV2_Msk                    /*!< PVD level 2 */
20493 #define PWR_CR1_PLS_LEV3_Pos           (5U)
20494 #define PWR_CR1_PLS_LEV3_Msk           (0x3U << PWR_CR1_PLS_LEV3_Pos)          /*!< 0x00000060 */
20495 #define PWR_CR1_PLS_LEV3               PWR_CR1_PLS_LEV3_Msk                    /*!< PVD level 3 */
20496 #define PWR_CR1_PLS_LEV4_Pos           (7U)
20497 #define PWR_CR1_PLS_LEV4_Msk           (0x1U << PWR_CR1_PLS_LEV4_Pos)          /*!< 0x00000080 */
20498 #define PWR_CR1_PLS_LEV4               PWR_CR1_PLS_LEV4_Msk                    /*!< PVD level 4 */
20499 #define PWR_CR1_PLS_LEV5_Pos           (5U)
20500 #define PWR_CR1_PLS_LEV5_Msk           (0x5U << PWR_CR1_PLS_LEV5_Pos)          /*!< 0x000000A0 */
20501 #define PWR_CR1_PLS_LEV5               PWR_CR1_PLS_LEV5_Msk                    /*!< PVD level 5 */
20502 #define PWR_CR1_PLS_LEV6_Pos           (6U)
20503 #define PWR_CR1_PLS_LEV6_Msk           (0x3U << PWR_CR1_PLS_LEV6_Pos)          /*!< 0x000000C0 */
20504 #define PWR_CR1_PLS_LEV6               PWR_CR1_PLS_LEV6_Msk                    /*!< PVD level 6 */
20505 #define PWR_CR1_PLS_LEV7_Pos           (5U)
20506 #define PWR_CR1_PLS_LEV7_Msk           (0x7U << PWR_CR1_PLS_LEV7_Pos)          /*!< 0x000000E0 */
20507 #define PWR_CR1_PLS_LEV7               PWR_CR1_PLS_LEV7_Msk                    /*!< PVD level 7 */
20508 
20509 /********************  Bit definition for PWR_CSR1 register  ********************/
20510 #define PWR_CSR1_AVDO_Pos              (16U)
20511 #define PWR_CSR1_AVDO_Msk              (0x1U << PWR_CSR1_AVDO_Pos)             /*!< 0x00010000 */
20512 #define PWR_CSR1_AVDO                  PWR_CSR1_AVDO_Msk                       /*!< Analog Voltage detector Output on VDDA */
20513 #define PWR_CSR1_PVDO_Pos              (4U)
20514 #define PWR_CSR1_PVDO_Msk              (0x1U << PWR_CSR1_PVDO_Pos)             /*!< 0x00000010 */
20515 #define PWR_CSR1_PVDO                  PWR_CSR1_PVDO_Msk                       /*!< Programmable Voltage Detect Output */
20516 
20517 /********************  Bit definition for PWR_CR2 register  ********************/
20518 #define PWR_CR2_BREN_Pos        (0U)
20519 #define PWR_CR2_BREN_Msk        (0x1U << PWR_CR2_BREN_Pos)                     /*!< 0x00000001 */
20520 #define PWR_CR2_BREN            PWR_CR2_BREN_Msk                               /*!< Backup regulator enable */
20521 #define PWR_CR2_RREN_Pos        (1U)
20522 #define PWR_CR2_RREN_Msk        (0x1U << PWR_CR2_RREN_Pos)                     /*!< 0x00000002 */
20523 #define PWR_CR2_RREN            PWR_CR2_RREN_Msk                               /*!< Retention Regulator enable */
20524 #define PWR_CR2_MONEN_Pos       (4U)
20525 #define PWR_CR2_MONEN_Msk       (0x1U << PWR_CR2_MONEN_Pos)                    /*!< 0x00000010 */
20526 #define PWR_CR2_MONEN           PWR_CR2_MONEN_Msk                              /*!< VBAT and temperature monitoring enable */
20527 #define PWR_CR2_BRRDY_Pos       (16U)
20528 #define PWR_CR2_BRRDY_Msk       (0x1U << PWR_CR2_BRRDY_Pos)                    /*!< 0x00010000 */
20529 #define PWR_CR2_BRRDY           PWR_CR2_BRRDY_Msk                              /*!< Backup Regulator ready */
20530 #define PWR_CR2_RRRDY_Pos       (17U)
20531 #define PWR_CR2_RRRDY_Msk       (0x1U << PWR_CR2_RRRDY_Pos)                    /*!< 0x00020000 */
20532 #define PWR_CR2_RRRDY           PWR_CR2_RRRDY_Msk                              /*!< Retention Regulator ready */
20533 #define PWR_CR2_VBATL_Pos       (20U)
20534 #define PWR_CR2_VBATL_Msk       (0x1U << PWR_CR2_VBATL_Pos)                    /*!< 0x00100000 */
20535 #define PWR_CR2_VBATL           PWR_CR2_VBATL_Msk                              /*!< Monitored VBAT level equal or below low threshold */
20536 #define PWR_CR2_VBATH_Pos       (21U)
20537 #define PWR_CR2_VBATH_Msk       (0x1U << PWR_CR2_VBATH_Pos)                    /*!< 0x00200000 */
20538 #define PWR_CR2_VBATH           PWR_CR2_VBATH_Msk                              /*!< Monitored VBAT level equal or above high threshold */
20539 #define PWR_CR2_TEMPL_Pos       (22U)
20540 #define PWR_CR2_TEMPL_Msk       (0x1U << PWR_CR2_TEMPL_Pos)                    /*!< 0x00300000 */
20541 #define PWR_CR2_TEMPL           PWR_CR2_TEMPL_Msk                              /*!< Monitored temperature level equal or below low threshold */
20542 #define PWR_CR2_TEMPH_Pos       (23U)
20543 #define PWR_CR2_TEMPH_Msk       (0x1U << PWR_CR2_TEMPH_Pos)                    /*!< 0x00400000 */
20544 #define PWR_CR2_TEMPH           PWR_CR2_TEMPH_Msk                              /*!< Monitored temperature level equal or below high threshold */
20545 
20546 /********************  Bit definition for PWR_CR3 register  ********************/
20547 #define PWR_CR3_VBE_Pos               (8U)
20548 #define PWR_CR3_VBE_Msk               (0x1U << PWR_CR3_VBE_Pos)                /*!< 0x00000100 */
20549 #define PWR_CR3_VBE                   PWR_CR3_VBE_Msk                          /*!< VBAT charging enable */
20550 #define PWR_CR3_VBRS_Pos              (9U)
20551 #define PWR_CR3_VBRS_Msk              (0x1U << PWR_CR3_VBRS_Pos)               /*!< 0x00000200 */
20552 #define PWR_CR3_VBRS                  PWR_CR3_VBRS_Msk                         /*!< VBAT charging resistor selection */
20553 #define PWR_CR3_DDRSREN_Pos           (10U)
20554 #define PWR_CR3_DDRSREN_Msk           (0x1U << PWR_CR3_DDRSREN_Pos)            /*!< 0x00000400 */
20555 #define PWR_CR3_DDRSREN               PWR_CR3_DDRSREN_Msk                      /*!< DDR self-refresh in standby mode enable */
20556 #define PWR_CR3_DDRSRDIS_Pos          (11U)
20557 #define PWR_CR3_DDRSRDIS_Msk          (0x1U << PWR_CR3_DDRSRDIS_Pos)           /*!< 0x00000800 */
20558 #define PWR_CR3_DDRSRDIS              PWR_CR3_DDRSRDIS_Msk                     /*!< DDR self-refresh retention after standby disable */
20559 #define PWR_CR3_DDRRETEN_Pos          (12U)
20560 #define PWR_CR3_DDRRETEN_Msk          (0x1U << PWR_CR3_DDRRETEN_Pos)           /*!< 0x00001000 */
20561 #define PWR_CR3_DDRRETEN              PWR_CR3_DDRRETEN_Msk                     /*!< DDR retention enable */
20562 #define PWR_CR3_POPL_Pos              (17U)
20563 #define PWR_CR3_POPL_Msk              (0x1FU << PWR_CR3_POPL_Pos)              /*!< 0x003E0000 */
20564 #define PWR_CR3_POPL                  PWR_CR3_POPL_Msk                         /*!< PWR_ON pulse low configuration */
20565 #define PWR_CR3_USB33DEN_Pos          (24U)
20566 #define PWR_CR3_USB33DEN_Msk          (0x1U << PWR_CR3_USB33DEN_Pos)           /*!< 0x01000000 */
20567 #define PWR_CR3_USB33DEN              PWR_CR3_USB33DEN_Msk                     /*!< USB33DEN: USB 3.3V voltage level detector enable */
20568 #define PWR_CR3_USB33RDY_Pos          (26U)
20569 #define PWR_CR3_USB33RDY_Msk          (0x1U << PWR_CR3_USB33RDY_Pos)           /*!< 0x04000000 */
20570 #define PWR_CR3_USB33RDY              PWR_CR3_USB33RDY_Msk                     /*!< USB 3.3V supply ready */
20571 #define PWR_CR3_REG18EN_Pos           (28U)
20572 #define PWR_CR3_REG18EN_Msk           (0x1U << PWR_CR3_REG18EN_Pos)            /*!< 0x10000000 */
20573 #define PWR_CR3_REG18EN               PWR_CR3_REG18EN_Msk                      /*!< 1V8 regulator enable */
20574 #define PWR_CR3_REG18RDY_Pos          (29U)
20575 #define PWR_CR3_REG18RDY_Msk          (0x1U << PWR_CR3_REG18RDY_Pos)           /*!< 0x20000000 */
20576 #define PWR_CR3_REG18RDY              PWR_CR3_REG18RDY_Msk                     /*!< 1V8 regulator supply ready */
20577 #define PWR_CR3_REG11EN_Pos           (30U)
20578 #define PWR_CR3_REG11EN_Msk           (0x1U << PWR_CR3_REG11EN_Pos)            /*!< 0x40000000 */
20579 #define PWR_CR3_REG11EN               PWR_CR3_REG11EN_Msk                      /*!< 1V1 regulator enable  */
20580 #define PWR_CR3_REG11RDY_Pos          (31U)
20581 #define PWR_CR3_REG11RDY_Msk          (0x1U << PWR_CR3_REG11RDY_Pos)           /*!< 0x80000000 */
20582 #define PWR_CR3_REG11RDY              PWR_CR3_REG11RDY_Msk                     /*!< 1V1 regulator supply ready */
20583 
20584 /********************  Bit definition for PWR_MPUCR register  ********************/
20585 #define PWR_MPUCR_PDDS_Pos            (0U)
20586 #define PWR_MPUCR_PDDS_Msk            (0x1U << PWR_MPUCR_PDDS_Pos)             /*!< 0x00000001 */
20587 #define PWR_MPUCR_PDDS                PWR_MPUCR_PDDS_Msk                       /*!< System Power Down Deepsleep selection */
20588 #define PWR_MPUCR_CSTBYDIS_Pos        (3U)
20589 #define PWR_MPUCR_CSTBYDIS_Msk        (0x1U << PWR_MPUCR_CSTBYDIS_Pos)         /*!< 0x00000008 */
20590 #define PWR_MPUCR_CSTBYDIS            PWR_MPUCR_CSTBYDIS_Msk                   /*!< MPU CStandby mode disable */
20591 #define PWR_MPUCR_STOPF_Pos           (5U)
20592 #define PWR_MPUCR_STOPF_Msk           (0x1U << PWR_MPUCR_STOPF_Pos)            /*!< 0x00000020 */
20593 #define PWR_MPUCR_STOPF               PWR_MPUCR_STOPF_Msk                      /*!< Stop Flag */
20594 #define PWR_MPUCR_SBF_Pos             (6U)
20595 #define PWR_MPUCR_SBF_Msk             (0x1U << PWR_MPUCR_SBF_Pos)              /*!< 0x00000040 */
20596 #define PWR_MPUCR_SBF                 PWR_MPUCR_SBF_Msk                        /*!< System Standby Flag */
20597 #define PWR_MPUCR_SBF_MPU_Pos         (7U)
20598 #define PWR_MPUCR_SBF_MPU_Msk         (0x1U << PWR_MPUCR_SBF_MPU_Pos)          /*!< 0x00000080 */
20599 #define PWR_MPUCR_SBF_MPU             PWR_MPUCR_SBF_MPU_Msk                    /*!< MPU Standby Flag */
20600 #define PWR_MPUCR_CSSF_Pos            (9U)
20601 #define PWR_MPUCR_CSSF_Msk            (0x1U << PWR_MPUCR_CSSF_Pos)             /*!< 0x00000200 */
20602 #define PWR_MPUCR_CSSF                PWR_MPUCR_CSSF_Msk                       /*!< Clear MCU STANDBY, STOP and HOLD flags.(always read as 0) */
20603 #define PWR_MPUCR_STANDBYWFIL2_Pos    (15U)
20604 #define PWR_MPUCR_STANDBYWFIL2_Msk    (0x1U << PWR_MPUCR_STANDBYWFIL2_Pos)     /*!< 0x00008000 */
20605 #define PWR_MPUCR_STANDBYWFIL2        PWR_MPUCR_STANDBYWFIL2_Msk               /*!< MPU system idle indication */
20606 
20607 /********************  Bit definition for PWR_MCUCR register  ********************/
20608 #define PWR_MCUCR_PDDS_Pos            (0U)
20609 #define PWR_MCUCR_PDDS_Msk            (0x1U << PWR_MCUCR_PDDS_Pos)             /*!< 0x00000001 */
20610 #define PWR_MCUCR_PDDS                PWR_MCUCR_PDDS_Msk                       /*!< System Power Down Deepsleep selection */
20611 #define PWR_MCUCR_STOPF_Pos           (5U)
20612 #define PWR_MCUCR_STOPF_Msk           (0x1U << PWR_MCUCR_STOPF_Pos)            /*!< 0x00000020 */
20613 #define PWR_MCUCR_STOPF               PWR_MCUCR_STOPF_Msk                      /*!< Stop Flag */
20614 #define PWR_MCUCR_SBF_Pos             (6U)
20615 #define PWR_MCUCR_SBF_Msk             (0x1U << PWR_MCUCR_SBF_Pos)              /*!< 0x00000040 */
20616 #define PWR_MCUCR_SBF                 PWR_MCUCR_SBF_Msk                        /*!< System Standby Flag */
20617 #define PWR_MCUCR_CSSF_Pos            (9U)
20618 #define PWR_MCUCR_CSSF_Msk            (0x1U << PWR_MCUCR_CSSF_Pos)             /*!< 0x00000200 */
20619 #define PWR_MCUCR_CSSF                PWR_MCUCR_CSSF_Msk                       /*!< Clear MCU Standby, Stop flags */
20620 #define PWR_MCUCR_DEEPSLEEP_Pos       (15U)
20621 #define PWR_MCUCR_DEEPSLEEP_Msk       (0x1U << PWR_MCUCR_DEEPSLEEP_Pos)        /*!< 0x00008000 */
20622 #define PWR_MCUCR_DEEPSLEEP           PWR_MCUCR_DEEPSLEEP_Msk                  /*!< MCU system idle indication */
20623 
20624 /********************  Bit definition for PWR_WKUPCR register  ********************/
20625 #define PWR_WKUPCR_WKUPPUPD_Pos        (16U)
20626 #define PWR_WKUPCR_WKUPPUPD_Msk        (0xFFFU << PWR_WKUPCR_WKUPPUPD_Pos)     /*!< 0x0FFF0000 */
20627 #define PWR_WKUPCR_WKUPPUPD            PWR_WKUPCR_WKUPPUPD_Msk                 /*!< Wakeup Pin pull configuration mask*/
20628 #define PWR_WKUPCR_WKUPPUPD6_Pos       (26U)
20629 #define PWR_WKUPCR_WKUPPUPD6_Msk       (0x3U << PWR_WKUPCR_WKUPPUPD6_Pos)      /*!< 0x0C000000 */
20630 #define PWR_WKUPCR_WKUPPUPD6           PWR_WKUPCR_WKUPPUPD6_Msk                /*!< Wakeup Pin pull configuration for WKUP6 */
20631 #define PWR_WKUPCR_WKUPPUPD6_0         (0x1U << PWR_WKUPCR_WKUPPUPD6_Pos)      /*!< 0x04000000 */
20632 #define PWR_WKUPCR_WKUPPUPD6_1         (0x2U << PWR_WKUPCR_WKUPPUPD6_Pos)      /*!< 0x08000000 */
20633 #define PWR_WKUPCR_WKUPPUPD5_Pos       (24U)
20634 #define PWR_WKUPCR_WKUPPUPD5_Msk       (0x3U << PWR_WKUPCR_WKUPPUPD5_Pos)      /*!< 0x03000000 */
20635 #define PWR_WKUPCR_WKUPPUPD5           PWR_WKUPCR_WKUPPUPD5_Msk                /*!< Wakeup Pin pull configuration for WKUP5 */
20636 #define PWR_WKUPCR_WKUPPUPD5_0         (0x1U << PWR_WKUPCR_WKUPPUPD5_Pos)      /*!< 0x01000000 */
20637 #define PWR_WKUPCR_WKUPPUPD5_1         (0x2U << PWR_WKUPCR_WKUPPUPD5_Pos)      /*!< 0x02000000 */
20638 #define PWR_WKUPCR_WKUPPUPD4_Pos       (22U)
20639 #define PWR_WKUPCR_WKUPPUPD4_Msk       (0x3U << PWR_WKUPCR_WKUPPUPD4_Pos)      /*!< 0x00C00000 */
20640 #define PWR_WKUPCR_WKUPPUPD4           PWR_WKUPCR_WKUPPUPD4_Msk                /*!< Wakeup Pin pull configuration for WKUP4 */
20641 #define PWR_WKUPCR_WKUPPUPD4_0         (0x1U << PWR_WKUPCR_WKUPPUPD4_Pos)      /*!< 0x00400000 */
20642 #define PWR_WKUPCR_WKUPPUPD4_1         (0x2U << PWR_WKUPCR_WKUPPUPD4_Pos)      /*!< 0x00800000 */
20643 #define PWR_WKUPCR_WKUPPUPD3_Pos       (20U)
20644 #define PWR_WKUPCR_WKUPPUPD3_Msk       (0x3U << PWR_WKUPCR_WKUPPUPD3_Pos)      /*!< 0x00300000 */
20645 #define PWR_WKUPCR_WKUPPUPD3           PWR_WKUPCR_WKUPPUPD3_Msk                /*!< Wakeup Pin pull configuration for WKUP3 */
20646 #define PWR_WKUPCR_WKUPPUPD3_0         (0x1U << PWR_WKUPCR_WKUPPUPD3_Pos)      /*!< 0x00100000 */
20647 #define PWR_WKUPCR_WKUPPUPD3_1         (0x2U << PWR_WKUPCR_WKUPPUPD3_Pos)      /*!< 0x00200000 */
20648 #define PWR_WKUPCR_WKUPPUPD2_Pos       (18U)
20649 #define PWR_WKUPCR_WKUPPUPD2_Msk       (0x3U << PWR_WKUPCR_WKUPPUPD2_Pos)      /*!< 0x000C0000 */
20650 #define PWR_WKUPCR_WKUPPUPD2           PWR_WKUPCR_WKUPPUPD2_Msk                /*!< Wakeup Pin pull configuration for WKUP2 */
20651 #define PWR_WKUPCR_WKUPPUPD2_0         (0x1U << PWR_WKUPCR_WKUPPUPD2_Pos)      /*!< 0x00040000 */
20652 #define PWR_WKUPCR_WKUPPUPD2_1         (0x2U << PWR_WKUPCR_WKUPPUPD2_Pos)      /*!< 0x00080000 */
20653 #define PWR_WKUPCR_WKUPPUPD1_Pos       (16U)
20654 #define PWR_WKUPCR_WKUPPUPD1_Msk       (0x3U << PWR_WKUPCR_WKUPPUPD1_Pos)      /*!< 0x00030000 */
20655 #define PWR_WKUPCR_WKUPPUPD1           PWR_WKUPCR_WKUPPUPD1_Msk                /*!< Wakeup Pin pull configuration for WKUP1 */
20656 #define PWR_WKUPCR_WKUPPUPD1_0         (0x1U << PWR_WKUPCR_WKUPPUPD1_Pos)      /*!< 0x00010000 */
20657 #define PWR_WKUPCR_WKUPPUPD1_1         (0x2U << PWR_WKUPCR_WKUPPUPD1_Pos)      /*!< 0x00020000 */
20658 
20659 #define PWR_WKUPCR_WKUPP_Pos           (8U)
20660 #define PWR_WKUPCR_WKUPP_Msk           (0x3FU << PWR_WKUPCR_WKUPP_Pos)         /*!< 0x00003F00 */
20661 #define PWR_WKUPCR_WKUPP               PWR_WKUPCR_WKUPP_Msk                    /*!< Wakeup Pin Polarity mask*/
20662 #define PWR_WKUPCR_WKUPP_6             (0x20U << PWR_WKUPCR_WKUPP_Pos)         /*!< 0x00002000 */
20663 #define PWR_WKUPCR_WKUPP_5             (0x10U << PWR_WKUPCR_WKUPP_Pos)         /*!< 0x00001000 */
20664 #define PWR_WKUPCR_WKUPP_4             (0x08U << PWR_WKUPCR_WKUPP_Pos)         /*!< 0x00000800 */
20665 #define PWR_WKUPCR_WKUPP_3             (0x04U << PWR_WKUPCR_WKUPP_Pos)         /*!< 0x00000400 */
20666 #define PWR_WKUPCR_WKUPP_2             (0x02U << PWR_WKUPCR_WKUPP_Pos)         /*!< 0x00000200 */
20667 #define PWR_WKUPCR_WKUPP_1             (0x01U << PWR_WKUPCR_WKUPP_Pos)         /*!< 0x00000100 */
20668 
20669 #define PWR_WKUPCR_WKUPC_Pos           (0U)
20670 #define PWR_WKUPCR_WKUPC_Msk           (0x3FU << PWR_WKUPCR_WKUPC_Pos)         /*!< 0x0000003F */
20671 #define PWR_WKUPCR_WKUPC               PWR_WKUPCR_WKUPC_Msk                    /*!< Wakeup Pin Mask */
20672 #define PWR_WKUPCR_WKUPC6_Pos          (5U)
20673 #define PWR_WKUPCR_WKUPC6_Msk          (0x1U << PWR_WKUPCR_WKUPC6_Pos)         /*!< 0x00000020 */
20674 #define PWR_WKUPCR_WKUPC6              PWR_WKUPCR_WKUPC6_Msk                   /*!< Clear Wakeup Pin Flag 6 */
20675 #define PWR_WKUPCR_WKUPC5_Pos          (4U)
20676 #define PWR_WKUPCR_WKUPC5_Msk          (0x1U << PWR_WKUPCR_WKUPC5_Pos)         /*!< 0x00000010 */
20677 #define PWR_WKUPCR_WKUPC5              PWR_WKUPCR_WKUPC5_Msk                   /*!< Clear Wakeup Pin Flag 5 */
20678 #define PWR_WKUPCR_WKUPC4_Pos          (3U)
20679 #define PWR_WKUPCR_WKUPC4_Msk          (0x1U << PWR_WKUPCR_WKUPC4_Pos)         /*!< 0x00000008 */
20680 #define PWR_WKUPCR_WKUPC4              PWR_WKUPCR_WKUPC4_Msk                   /*!< Clear Wakeup Pin Flag 4 */
20681 #define PWR_WKUPCR_WKUPC3_Pos          (2U)
20682 #define PWR_WKUPCR_WKUPC3_Msk          (0x1U << PWR_WKUPCR_WKUPC3_Pos)         /*!< 0x00000004 */
20683 #define PWR_WKUPCR_WKUPC3              PWR_WKUPCR_WKUPC3_Msk                   /*!< Clear Wakeup Pin Flag 3 */
20684 #define PWR_WKUPCR_WKUPC2_Pos          (1U)
20685 #define PWR_WKUPCR_WKUPC2_Msk          (0x1U << PWR_WKUPCR_WKUPC2_Pos)         /*!< 0x00000002 */
20686 #define PWR_WKUPCR_WKUPC2              PWR_WKUPCR_WKUPC2_Msk                   /*!< Clear Wakeup Pin Flag 2 */
20687 #define PWR_WKUPCR_WKUPC1_Pos          (0U)
20688 #define PWR_WKUPCR_WKUPC1_Msk          (0x1U << PWR_WKUPCR_WKUPC1_Pos)         /*!< 0x00000001 */
20689 #define PWR_WKUPCR_WKUPC1              PWR_WKUPCR_WKUPC1_Msk                   /*!< Clear Wakeup Pin Flag 1 */
20690 
20691 /********************  Bit definition for PWR_WKUPFR register  ********************/
20692 #define PWR_WKUPFR_WKUPF6_Pos          (5U)
20693 #define PWR_WKUPFR_WKUPF6_Msk          (0x1U << PWR_WKUPFR_WKUPF6_Pos)         /*!< 0x00000020 */
20694 #define PWR_WKUPFR_WKUPF6              PWR_WKUPFR_WKUPF6_Msk                   /*!< Wakeup Pin Flag 6 */
20695 #define PWR_WKUPFR_WKUPF5_Pos          (4U)
20696 #define PWR_WKUPFR_WKUPF5_Msk          (0x1U << PWR_WKUPFR_WKUPF5_Pos)         /*!< 0x00000010 */
20697 #define PWR_WKUPFR_WKUPF5              PWR_WKUPFR_WKUPF5_Msk                   /*!< Wakeup Pin Flag 5 */
20698 #define PWR_WKUPFR_WKUPF4_Pos          (3U)
20699 #define PWR_WKUPFR_WKUPF4_Msk          (0x1U << PWR_WKUPFR_WKUPF4_Pos)         /*!< 0x00000008 */
20700 #define PWR_WKUPFR_WKUPF4              PWR_WKUPFR_WKUPF4_Msk                   /*!< Wakeup Pin Flag 4 */
20701 #define PWR_WKUPFR_WKUPF3_Pos          (2U)
20702 #define PWR_WKUPFR_WKUPF3_Msk          (0x1U << PWR_WKUPFR_WKUPF3_Pos)         /*!< 0x00000004 */
20703 #define PWR_WKUPFR_WKUPF3              PWR_WKUPFR_WKUPF3_Msk                   /*!< Wakeup Pin Flag 3 */
20704 #define PWR_WKUPFR_WKUPF2_Pos          (1U)
20705 #define PWR_WKUPFR_WKUPF2_Msk          (0x1U << PWR_WKUPFR_WKUPF2_Pos)         /*!< 0x00000002 */
20706 #define PWR_WKUPFR_WKUPF2              PWR_WKUPFR_WKUPF2_Msk                   /*!< Wakeup Pin Flag 2 */
20707 #define PWR_WKUPFR_WKUPF1_Pos          (0U)
20708 #define PWR_WKUPFR_WKUPF1_Msk          (0x1U << PWR_WKUPFR_WKUPF1_Pos)         /*!< 0x00000001 */
20709 #define PWR_WKUPFR_WKUPF1              PWR_WKUPFR_WKUPF1_Msk                   /*!< Wakeup Pin Flag 1 */
20710 
20711 /********************  Bit definition for PWR_MPUWKUPENR register  ********************/
20712 #define PWR_MPUWKUPENR_WKUPEN_Pos      (0U)
20713 #define PWR_MPUWKUPENR_WKUPEN_Msk      (0x3FU << PWR_MPUWKUPENR_WKUPEN_Pos)    /*!< 0x0000003F */
20714 #define PWR_MPUWKUPENR_WKUPEN          PWR_MPUWKUPENR_WKUPEN_Msk               /*!< Enable Wakeup and interrupt for CPU1 */
20715 #define PWR_MPUWKUPENR_WKUPEN_6        (0x20U << PWR_MPUWKUPENR_WKUPEN_Pos)    /*!< 0x00000020 */
20716 #define PWR_MPUWKUPENR_WKUPEN_5        (0x10U << PWR_MPUWKUPENR_WKUPEN_Pos)    /*!< 0x00000010 */
20717 #define PWR_MPUWKUPENR_WKUPEN_4        (0x08U << PWR_MPUWKUPENR_WKUPEN_Pos)    /*!< 0x00000008 */
20718 #define PWR_MPUWKUPENR_WKUPEN_3        (0x04U << PWR_MPUWKUPENR_WKUPEN_Pos)    /*!< 0x00000004 */
20719 #define PWR_MPUWKUPENR_WKUPEN_2        (0x02U << PWR_MPUWKUPENR_WKUPEN_Pos)    /*!< 0x00000002 */
20720 #define PWR_MPUWKUPENR_WKUPEN_1        (0x01U << PWR_MPUWKUPENR_WKUPEN_Pos)    /*!< 0x00000001 */
20721 
20722 /********************  Bit definition for PWR_MCUWKUPENR register  ********************/
20723 #define PWR_MCUWKUPENR_WKUPEN_Pos      (0U)
20724 #define PWR_MCUWKUPENR_WKUPEN_Msk      (0x3FU << PWR_MCUWKUPENR_WKUPEN_Pos)    /*!< 0x0000003F */
20725 #define PWR_MCUWKUPENR_WKUPEN          PWR_MCUWKUPENR_WKUPEN_Msk               /*!< Enable Wakeup and interrupt for CPU2 */
20726 #define PWR_MCUWKUPENR_WKUPEN6_Pos     (5U)
20727 #define PWR_MCUWKUPENR_WKUPEN6_Msk     (0x1U << PWR_MCUWKUPENR_WKUPEN6_Pos)    /*!< 0x00000020 */
20728 #define PWR_MCUWKUPENR_WKUPEN6         PWR_MCUWKUPENR_WKUPEN6_Msk              /*!< Enable Wakeup WKUP6 pin and interrupt for CPU2 */
20729 #define PWR_MCUWKUPENR_WKUPEN5_Pos     (4U)
20730 #define PWR_MCUWKUPENR_WKUPEN5_Msk     (0x1U << PWR_MCUWKUPENR_WKUPEN5_Pos)    /*!< 0x00000010 */
20731 #define PWR_MCUWKUPENR_WKUPEN5         PWR_MCUWKUPENR_WKUPEN5_Msk              /*!< Enable Wakeup WKUP5 pin and interrupt for CPU2 */
20732 #define PWR_MCUWKUPENR_WKUPEN4_Pos     (3U)
20733 #define PWR_MCUWKUPENR_WKUPEN4_Msk     (0x1U << PWR_MCUWKUPENR_WKUPEN4_Pos)    /*!< 0x00000008 */
20734 #define PWR_MCUWKUPENR_WKUPEN4         PWR_MCUWKUPENR_WKUPEN4_Msk              /*!< Enable Wakeup WKUP4 pin and interrupt for CPU2 */
20735 #define PWR_MCUWKUPENR_WKUPEN3_Pos     (2U)
20736 #define PWR_MCUWKUPENR_WKUPEN3_Msk     (0x1U << PWR_MCUWKUPENR_WKUPEN3_Pos)    /*!< 0x00000004 */
20737 #define PWR_MCUWKUPENR_WKUPEN3         PWR_MCUWKUPENR_WKUPEN3_Msk              /*!< Enable Wakeup WKUP3 pin and interrupt for CPU2 */
20738 #define PWR_MCUWKUPENR_WKUPEN2_Pos     (1U)
20739 #define PWR_MCUWKUPENR_WKUPEN2_Msk     (0x1U << PWR_MCUWKUPENR_WKUPEN2_Pos)    /*!< 0x00000002 */
20740 #define PWR_MCUWKUPENR_WKUPEN2         PWR_MCUWKUPENR_WKUPEN2_Msk              /*!< Enable Wakeup WKUP2 pin and interrupt for CPU2 */
20741 #define PWR_MCUWKUPENR_WKUPEN1_Pos     (0U)
20742 #define PWR_MCUWKUPENR_WKUPEN1_Msk     (0x1U << PWR_MCUWKUPENR_WKUPEN1_Pos)    /*!< 0x00000001 */
20743 #define PWR_MCUWKUPENR_WKUPEN1         PWR_MCUWKUPENR_WKUPEN1_Msk              /*!< Enable Wakeup WKUP1 pin and interrupt for CPU2 */
20744 
20745 /********************  Bit definition for PWR_VER register  ********************/
20746 #define PWR_VER_MAJREV_Pos             (4U)
20747 #define PWR_VER_MAJREV_Msk             (0xFU << PWR_VER_MAJREV_Pos)            /*!< 0x000000F0 */
20748 #define PWR_VER_MAJREV                 PWR_VER_MAJREV_Msk                      /*!< Major Revision number */
20749 #define PWR_VER_MINREV_Pos             (0U)
20750 #define PWR_VER_MINREV_Msk             (0xFU << PWR_VER_MINREV_Pos)            /*!< 0x0000000F */
20751 #define PWR_VER_MINREV                 PWR_VER_MINREV_Msk                      /*!< Minor Revision number */
20752 
20753 /********************  Bit definition for PWR_ID register  ********************/
20754 #define PWR_ID_IPID_Pos                (0U)
20755 #define PWR_ID_IPID_Msk                (0xFFFFFFFFU << PWR_ID_IPID_Pos)        /*!< 0xFFFFFFFF */
20756 #define PWR_ID_IPID                    PWR_ID_IPID_Msk                         /*!< IP identification */
20757 
20758 /********************  Bit definition for PWR_SID register  ********************/
20759 #define PWR_SID_SID_Pos                (0U)
20760 #define PWR_SID_SID_Msk                (0xFFFFFFFFU << PWR_SID_SID_Pos)        /*!< 0xFFFFFFFF */
20761 #define PWR_SID_SID                    PWR_SID_SID_Msk                         /*!< Size identification */
20762 
20763 
20764 /******************************************************************************/
20765 /*                                                                            */
20766 /*                   Boot and Security and OTP Control (BSEC)                 */
20767 /*                                                                            */
20768 /******************************************************************************/
20769 /******************  Bit definition for BSEC_OTP_CONFIG register  *****************/
20770 #define BSEC_OTP_CONFIG_PWRUP_Pos          (0U)
20771 #define BSEC_OTP_CONFIG_PWRUP_Msk          (0x1U << BSEC_OTP_CONFIG_PWRUP_Pos) /*!< 0x00000001 */
20772 #define BSEC_OTP_CONFIG_PWRUP              BSEC_OTP_CONFIG_PWRUP_Msk           /*!< OTP power-up control */
20773 #define BSEC_OTP_CONFIG_FRC_Pos            (1U)
20774 #define BSEC_OTP_CONFIG_FRC_Msk            (0x3U << BSEC_OTP_CONFIG_FRC_Pos)   /*!< 0x00000006 */
20775 #define BSEC_OTP_CONFIG_FRC                BSEC_OTP_CONFIG_FRC_Msk             /*!< OTP clock frequency range selection */
20776 #define BSEC_OTP_CONFIG_FRC_0              (0x1U << BSEC_OTP_CONFIG_FRC_Pos)   /*!< 0x00000002 */
20777 #define BSEC_OTP_CONFIG_FRC_1              (0x2U << BSEC_OTP_CONFIG_FRC_Pos)   /*!< 0x00000004 */
20778 #define BSEC_OTP_CONFIG_PRGWIDTH_Pos       (3U)
20779 #define BSEC_OTP_CONFIG_PRGWIDTH_Msk       (0xFU << BSEC_OTP_CONFIG_PRGWIDTH_Pos) /*!< 0x00000078 */
20780 #define BSEC_OTP_CONFIG_PRGWIDTH           BSEC_OTP_CONFIG_PRGWIDTH_Msk        /*!< OTP programming pulse width */
20781 #define BSEC_OTP_CONFIG_PRGWIDTH_0         (0x1U << BSEC_OTP_CONFIG_PRGWIDTH_Pos) /*!< 0x00000008 */
20782 #define BSEC_OTP_CONFIG_PRGWIDTH_1         (0x2U << BSEC_OTP_CONFIG_PRGWIDTH_Pos) /*!< 0x00000010 */
20783 #define BSEC_OTP_CONFIG_PRGWIDTH_2         (0x4U << BSEC_OTP_CONFIG_PRGWIDTH_Pos) /*!< 0x00000020 */
20784 #define BSEC_OTP_CONFIG_PRGWIDTH_3         (0x8U << BSEC_OTP_CONFIG_PRGWIDTH_Pos) /*!< 0x00000040 */
20785 #define BSEC_OTP_CONFIG_TREAD_Pos          (7U)
20786 #define BSEC_OTP_CONFIG_TREAD_Msk          (0x3U << BSEC_OTP_CONFIG_TREAD_Pos) /*!< 0x00000180 */
20787 #define BSEC_OTP_CONFIG_TREAD              BSEC_OTP_CONFIG_TREAD_Msk           /*!< set OTP reading current level */
20788 #define BSEC_OTP_CONFIG_TREAD_0            (0x1U << BSEC_OTP_CONFIG_TREAD_Pos) /*!< 0x00000080 */
20789 #define BSEC_OTP_CONFIG_TREAD_1            (0x2U << BSEC_OTP_CONFIG_TREAD_Pos) /*!< 0x00000100 */
20790 
20791 /******************  Bit definition for BSEC_OTP_CONTROL register  ****************/
20792 #define BSEC_OTP_CONTROL_ADDR_Pos          (0U)
20793 #define BSEC_OTP_CONTROL_ADDR_Msk          (0x7FU << BSEC_OTP_CONTROL_ADDR_Pos) /*!< 0x0000007F */
20794 #define BSEC_OTP_CONTROL_ADDR              BSEC_OTP_CONTROL_ADDR_Msk           /*!< OTP word address */
20795 #define BSEC_OTP_CONTROL_PROG_Pos          (8U)
20796 #define BSEC_OTP_CONTROL_PROG_Msk          (0x1U << BSEC_OTP_CONTROL_PROG_Pos) /*!< 0x00000100 */
20797 #define BSEC_OTP_CONTROL_PROG              BSEC_OTP_CONTROL_PROG_Msk           /*!< OTP operation control */
20798 #define BSEC_OTP_CONTROL_LOCK_Pos          (9U)
20799 #define BSEC_OTP_CONTROL_LOCK_Msk          (0x1U << BSEC_OTP_CONTROL_LOCK_Pos) /*!< 0x00000200 */
20800 #define BSEC_OTP_CONTROL_LOCK              BSEC_OTP_CONTROL_LOCK_Msk           /*!< OTP permanent word lock control */
20801 
20802 /******************  Bit definition for BSEC_OTP_STATUS register  *****************/
20803 #define BSEC_OTP_STATUS_SECURE_Pos         (0U)
20804 #define BSEC_OTP_STATUS_SECURE_Msk         (0x1U << BSEC_OTP_STATUS_SECURE_Pos) /*!< 0x00000001 */
20805 #define BSEC_OTP_STATUS_SECURE             BSEC_OTP_STATUS_SECURE_Msk          /*!< OTP secured mode */
20806 #define BSEC_OTP_STATUS_FULLDBG_Pos        (1U)
20807 #define BSEC_OTP_STATUS_FULLDBG_Msk        (0x1U << BSEC_OTP_STATUS_FULLDBG_Pos) /*!< 0x00000002 */
20808 #define BSEC_OTP_STATUS_FULLDBG            BSEC_OTP_STATUS_FULLDBG_Msk         /*!< OTP mode in full debug */
20809 #define BSEC_OTP_STATUS_INVALID_Pos        (2U)
20810 #define BSEC_OTP_STATUS_INVALID_Msk        (0x1U << BSEC_OTP_STATUS_INVALID_Pos) /*!< 0x00000004 */
20811 #define BSEC_OTP_STATUS_INVALID            BSEC_OTP_STATUS_INVALID_Msk         /*!< OTP invalid mode */
20812 #define BSEC_OTP_STATUS_BUSY_Pos           (3U)
20813 #define BSEC_OTP_STATUS_BUSY_Msk           (0x1U << BSEC_OTP_STATUS_BUSY_Pos)  /*!< 0x00000008 */
20814 #define BSEC_OTP_STATUS_BUSY               BSEC_OTP_STATUS_BUSY_Msk            /*!< OTP operation status */
20815 #define BSEC_OTP_STATUS_PROGFAIL_Pos       (4U)
20816 #define BSEC_OTP_STATUS_PROGFAIL_Msk       (0x1U << BSEC_OTP_STATUS_PROGFAIL_Pos) /*!< 0x00000010 */
20817 #define BSEC_OTP_STATUS_PROGFAIL           BSEC_OTP_STATUS_PROGFAIL_Msk        /*!< last programming status */
20818 #define BSEC_OTP_STATUS_PWRON_Pos          (5U)
20819 #define BSEC_OTP_STATUS_PWRON_Msk          (0x1U << BSEC_OTP_STATUS_PWRON_Pos) /*!< 0x00000020 */
20820 #define BSEC_OTP_STATUS_PWRON              BSEC_OTP_STATUS_PWRON_Msk           /*!< OTP power status */
20821 #define BSEC_OTP_STATUS_BIST1LOCK_Pos      (6U)
20822 #define BSEC_OTP_STATUS_BIST1LOCK_Msk      (0x1U << BSEC_OTP_STATUS_BIST1LOCK_Pos) /*!< 0x00000040 */
20823 #define BSEC_OTP_STATUS_BIST1LOCK          BSEC_OTP_STATUS_BIST1LOCK_Msk       /*!< BIST1 locked */
20824 #define BSEC_OTP_STATUS_BIST2LOCK_Pos      (7U)
20825 #define BSEC_OTP_STATUS_BIST2LOCK_Msk      (0x1U << BSEC_OTP_STATUS_BIST2LOCK_Pos) /*!< 0x00000080 */
20826 #define BSEC_OTP_STATUS_BIST2LOCK          BSEC_OTP_STATUS_BIST2LOCK_Msk       /*!< BIST2 locked */
20827 
20828 /******************  Bit definition for BSEC_OTP_LOCK register  ********************/
20829 #define BSEC_OTP_LOCK_OTP_Pos              (0U)
20830 #define BSEC_OTP_LOCK_OTP_Msk              (0x1U << BSEC_OTP_LOCK_OTP_Pos)     /*!< 0x00000001 */
20831 #define BSEC_OTP_LOCK_OTP                  BSEC_OTP_LOCK_OTP_Msk               /*!< upper OTP read lock */
20832 #define BSEC_OTP_LOCK_DENREG_Pos           (2U)
20833 #define BSEC_OTP_LOCK_DENREG_Msk           (0x1U << BSEC_OTP_LOCK_DENREG_Pos)  /*!< 0x00000004 */
20834 #define BSEC_OTP_LOCK_DENREG               BSEC_OTP_LOCK_DENREG_Msk            /*!< debug enable register sticky lock */
20835 #define BSEC_OTP_LOCK_FENREG_Pos           (3U)
20836 #define BSEC_OTP_LOCK_FENREG_Msk           (0x1U << BSEC_OTP_LOCK_FENREG_Pos)  /*!< 0x00000008 */
20837 #define BSEC_OTP_LOCK_FENREG               BSEC_OTP_LOCK_FENREG_Msk            /*!< feature enable register sticky lock */
20838 #define BSEC_OTP_LOCK_GPLOCK_Pos           (4U)
20839 #define BSEC_OTP_LOCK_GPLOCK_Msk           (0x1U << BSEC_OTP_LOCK_GPLOCK_Pos)  /*!< 0x00000010 */
20840 #define BSEC_OTP_LOCK_GPLOCK               BSEC_OTP_LOCK_GPLOCK_Msk            /*!< programming sticky lock */
20841 
20842 /********************  Bit definition for BSEC_DENABLE register********************/
20843 #define BSEC_DENABLE_DFTEN_Pos             (0U)
20844 #define BSEC_DENABLE_DFTEN_Msk             (0x1U << BSEC_DENABLE_DFTEN_Pos)    /*!< 0x00000001 */
20845 #define BSEC_DENABLE_DFTEN                 BSEC_DENABLE_DFTEN_Msk              /*!< DFT enable with signal dften */
20846 #define BSEC_DENABLE_DBGEN_Pos             (1U)
20847 #define BSEC_DENABLE_DBGEN_Msk             (0x1U << BSEC_DENABLE_DBGEN_Pos)    /*!< 0x00000002 */
20848 #define BSEC_DENABLE_DBGEN                 BSEC_DENABLE_DBGEN_Msk              /*!< debug enable with signal dbgen */
20849 #define BSEC_DENABLE_NIDEN_Pos             (2U)
20850 #define BSEC_DENABLE_NIDEN_Msk             (0x1U << BSEC_DENABLE_NIDEN_Pos)    /*!< 0x00000004 */
20851 #define BSEC_DENABLE_NIDEN                 BSEC_DENABLE_NIDEN_Msk              /*!< non-invasive debug enable with signal niden */
20852 #define BSEC_DENABLE_DEVICEEN_Pos          (3U)
20853 #define BSEC_DENABLE_DEVICEEN_Msk          (0x1U << BSEC_DENABLE_DEVICEEN_Pos) /*!< 0x00000008 */
20854 #define BSEC_DENABLE_DEVICEEN              BSEC_DENABLE_DEVICEEN_Msk           /*!< controls access to debug component via external debug port by signal deviceen */
20855 #define BSEC_DENABLE_HDPEN_Pos             (4U)
20856 #define BSEC_DENABLE_HDPEN_Msk             (0x1U << BSEC_DENABLE_HDPEN_Pos)    /*!< 0x00000010 */
20857 #define BSEC_DENABLE_HDPEN                 BSEC_DENABLE_HDPEN_Msk              /*!< hardware debug port enable with signal hdpen */
20858 #define BSEC_DENABLE_SPIDEN_Pos            (5U)
20859 #define BSEC_DENABLE_SPIDEN_Msk            (0x1U << BSEC_DENABLE_SPIDEN_Pos)   /*!< 0x00000020 */
20860 #define BSEC_DENABLE_SPIDEN                BSEC_DENABLE_SPIDEN_Msk             /*!< secure privilege invasive debug enable with signal spniden */
20861 #define BSEC_DENABLE_SPNIDEN_Pos           (6U)
20862 #define BSEC_DENABLE_SPNIDEN_Msk           (0x1U << BSEC_DENABLE_SPNIDEN_Pos)  /*!< 0x00000040 */
20863 #define BSEC_DENABLE_SPNIDEN               BSEC_DENABLE_SPNIDEN_Msk            /*!< secure privilege non-invasive debug enable with signal spiden */
20864 #define BSEC_DENABLE_CP15SDISABLE_Pos      (7U)
20865 #define BSEC_DENABLE_CP15SDISABLE_Msk      (0x3U << BSEC_DENABLE_CP15SDISABLE_Pos) /*!< 0x00000180 */
20866 #define BSEC_DENABLE_CP15SDISABLE          BSEC_DENABLE_CP15SDISABLE_Msk       /*!< write access to some secure Cortex®-A7 CP15 registers disable CPDISABLE[0] applies to CPU0. CPDISABLE[1] applies to CPU1 */
20867 #define BSEC_DENABLE_CP15SDISABLE_0        (0x1U << BSEC_DENABLE_CP15SDISABLE_Pos) /*!< 0x00000080 */
20868 #define BSEC_DENABLE_CP15SDISABLE_1        (0x2U << BSEC_DENABLE_CP15SDISABLE_Pos) /*!< 0x00000100 */
20869 #define BSEC_DENABLE_CFGSDISABLE_Pos       (9U)
20870 #define BSEC_DENABLE_CFGSDISABLE_Msk       (0x1U << BSEC_DENABLE_CFGSDISABLE_Pos) /*!< 0x00000200 */
20871 #define BSEC_DENABLE_CFGSDISABLE           BSEC_DENABLE_CFGSDISABLE_Msk        /*!< write access to secure GIC registers disable with signal cfgsdisable */
20872 #define BSEC_DENABLE_DBGSWENABLE_Pos       (10U)
20873 #define BSEC_DENABLE_DBGSWENABLE_Msk       (0x1U << BSEC_DENABLE_DBGSWENABLE_Pos) /*!< 0x00000400 */
20874 #define BSEC_DENABLE_DBGSWENABLE           BSEC_DENABLE_DBGSWENABLE_Msk        /*!< control self hosted debug enable with signal dbgswenable */
20875 
20876 /********************  Bit definition for BSEC_HWCFGR register  ***************/
20877 #define BSEC_HWCFGR_SIZE_Pos       (0U)
20878 #define BSEC_HWCFGR_SIZE_Msk       (0xFU << BSEC_HWCFGR_SIZE_Pos)            /*!< 0x0000000F */
20879 #define BSEC_HWCFGR_SIZE            BSEC_HWCFGR_SIZE_Msk                     /*!< OTP Block Size */
20880 #define BSEC_HWCFGR_ECC_USE_Pos    (4U)
20881 #define BSEC_HWCFGR_ECC_USE_Msk    (0xFU << BSEC_HWCFGR_ECC_USE_Pos)         /*!< 0x000000F0 */
20882 #define BSEC_HWCFGR_ECC_USE         BSEC_HWCFGR_ECC_USE_Msk                  /*!< protection / redundancy scheme used */
20883 
20884 /********************  Bit definition for BSEC_VERR register********************/
20885 #define BSEC_VERR_MINREV_Pos        (0U)
20886 #define BSEC_VERR_MINREV_Msk        (0xFU << BSEC_VERR_MINREV_Pos)           /*!< 0x0000000F */
20887 #define BSEC_VERR_MINREV            BSEC_VERR_MINREV_Msk                     /*!< MAJREV[3:0] bits (Minor revision) */
20888 #define BSEC_VERR_MAJREV_Pos        (4U)
20889 #define BSEC_VERR_MAJREV_Msk        (0xFU << BSEC_VERR_MAJREV_Pos)           /*!< 0x000000F0 */
20890 #define BSEC_VERR_MAJREV            BSEC_VERR_MAJREV_Msk                     /*!< MINREV[3:0] bits (Major revision) */
20891 
20892 /**********************  Bit definition for BSEC_IPIDR register  ****************/
20893 #define BSEC_IPIDR_IPID_Pos       (0U)
20894 #define BSEC_IPIDR_IPID_Msk       (0xFFFFFFFFU << BSEC_IPIDR_IPID_Pos)         /*!< 0xFFFFFFFF */
20895 #define BSEC_IPIDR_IPID           BSEC_IPIDR_IPID_Msk                          /*!< IP Identification */
20896 
20897 /**********************  Bit definition for BSEC_SIDR register  *****************/
20898 #define BSEC_SIDR_SID_Pos         (0U)
20899 #define BSEC_SIDR_SID_Msk         (0xFFFFFFFFU << BSEC_SIDR_SID_Pos)           /*!< 0xFFFFFFFF */
20900 #define BSEC_SIDR_SID             BSEC_SIDR_SID_Msk                            /*!< IP size identification */
20901 
20902 /******************************************************************************/
20903 /*                                                                            */
20904 /*                         Hardware Debug Port                                */
20905 /*                                                                            */
20906 /******************************************************************************/
20907 
20908 /********************  Bit definition for HDP_CTRL register********************/
20909 #define HDP_CTRL_EN_Pos             (0U)
20910 #define HDP_CTRL_EN_Msk             (0x1U << HDP_CTRL_EN_Pos)                  /*!< 0x00000001 */
20911 #define HDP_CTRL_EN                 HDP_CTRL_EN_Msk                            /*Enable HDP, valid if enabled in BSEC*/
20912 
20913 /********************  Bit definition for HDP_MUX register*********************/
20914 #define HDP_MUX_MUX0_Pos            (0U)
20915 #define HDP_MUX_MUX0_Msk            (0xFU << HDP_MUX_MUX0_Pos)                 /*!< 0x0000000F */
20916 #define HDP_MUX_MUX0                HDP_MUX_MUX0_Msk                           /*Select the HDP0 output among the 16 available signals*/
20917 #define HDP_MUX_MUX0_0              (0x1U << HDP_MUX_MUX0_Pos)                 /*!< 0x00000001 */
20918 #define HDP_MUX_MUX0_1              (0x2U << HDP_MUX_MUX0_Pos)                 /*!< 0x00000002 */
20919 #define HDP_MUX_MUX0_2              (0x4U << HDP_MUX_MUX0_Pos)                 /*!< 0x00000004 */
20920 #define HDP_MUX_MUX0_3              (0x8U << HDP_MUX_MUX0_Pos)                 /*!< 0x00000008 */
20921 #define HDP_MUX_MUX1_Pos            (4U)
20922 #define HDP_MUX_MUX1_Msk            (0xFU << HDP_MUX_MUX1_Pos)                 /*!< 0x000000F0 */
20923 #define HDP_MUX_MUX1                HDP_MUX_MUX1_Msk                           /*Select the HDP1 output among the 16 available signals*/
20924 #define HDP_MUX_MUX1_0              (0x1U << HDP_MUX_MUX1_Pos)                 /*!< 0x00000010 */
20925 #define HDP_MUX_MUX1_1              (0x2U << HDP_MUX_MUX1_Pos)                 /*!< 0x00000020 */
20926 #define HDP_MUX_MUX1_2              (0x4U << HDP_MUX_MUX1_Pos)                 /*!< 0x00000040 */
20927 #define HDP_MUX_MUX1_3              (0x8U << HDP_MUX_MUX1_Pos)                 /*!< 0x00000080 */
20928 #define HDP_MUX_MUX2_Pos            (8U)
20929 #define HDP_MUX_MUX2_Msk            (0xFU << HDP_MUX_MUX2_Pos)                 /*!< 0x00000F00 */
20930 #define HDP_MUX_MUX2                HDP_MUX_MUX2_Msk                           /*Select the HDP2 output among the 16 available signals*/
20931 #define HDP_MUX_MUX2_0              (0x1U << HDP_MUX_MUX2_Pos)                 /*!< 0x00000100 */
20932 #define HDP_MUX_MUX2_1              (0x2U << HDP_MUX_MUX2_Pos)                 /*!< 0x00000200 */
20933 #define HDP_MUX_MUX2_2              (0x4U << HDP_MUX_MUX2_Pos)                 /*!< 0x00000400 */
20934 #define HDP_MUX_MUX2_3              (0x8U << HDP_MUX_MUX2_Pos)                 /*!< 0x00000800 */
20935 #define HDP_MUX_MUX3_Pos            (12U)
20936 #define HDP_MUX_MUX3_Msk            (0xFU << HDP_MUX_MUX3_Pos)                 /*!< 0x0000F000 */
20937 #define HDP_MUX_MUX3                HDP_MUX_MUX3_Msk                           /*Select the HDP3 output among the 16 available signals*/
20938 #define HDP_MUX_MUX3_0              (0x1U << HDP_MUX_MUX3_Pos)                 /*!< 0x00001000 */
20939 #define HDP_MUX_MUX3_1              (0x2U << HDP_MUX_MUX3_Pos)                 /*!< 0x00002000 */
20940 #define HDP_MUX_MUX3_2              (0x4U << HDP_MUX_MUX3_Pos)                 /*!< 0x00004000 */
20941 #define HDP_MUX_MUX3_3              (0x8U << HDP_MUX_MUX3_Pos)                 /*!< 0x00008000 */
20942 #define HDP_MUX_MUX4_Pos            (16U)
20943 #define HDP_MUX_MUX4_Msk            (0xFU << HDP_MUX_MUX4_Pos)                 /*!< 0x000F0000 */
20944 #define HDP_MUX_MUX4                HDP_MUX_MUX4_Msk                           /*Select the HDP4 output among the 16 available signals*/
20945 #define HDP_MUX_MUX4_0              (0x1U << HDP_MUX_MUX4_Pos)                 /*!< 0x00010000 */
20946 #define HDP_MUX_MUX4_1              (0x2U << HDP_MUX_MUX4_Pos)                 /*!< 0x00020000 */
20947 #define HDP_MUX_MUX4_2              (0x4U << HDP_MUX_MUX4_Pos)                 /*!< 0x00040000 */
20948 #define HDP_MUX_MUX4_3              (0x8U << HDP_MUX_MUX4_Pos)                 /*!< 0x00080000 */
20949 #define HDP_MUX_MUX5_Pos            (20U)
20950 #define HDP_MUX_MUX5_Msk            (0xFU << HDP_MUX_MUX5_Pos)                 /*!< 0x00F00000 */
20951 #define HDP_MUX_MUX5                HDP_MUX_MUX5_Msk                           /*Select the HDP5 output among the 16 available signals*/
20952 #define HDP_MUX_MUX5_0              (0x1U << HDP_MUX_MUX5_Pos)                 /*!< 0x00100000 */
20953 #define HDP_MUX_MUX5_1              (0x2U << HDP_MUX_MUX5_Pos)                 /*!< 0x00200000 */
20954 #define HDP_MUX_MUX5_2              (0x4U << HDP_MUX_MUX5_Pos)                 /*!< 0x00400000 */
20955 #define HDP_MUX_MUX5_3              (0x8U << HDP_MUX_MUX5_Pos)                 /*!< 0x00800000 */
20956 #define HDP_MUX_MUX6_Pos            (24U)
20957 #define HDP_MUX_MUX6_Msk            (0xFU << HDP_MUX_MUX6_Pos)                 /*!< 0x0F000000 */
20958 #define HDP_MUX_MUX6                HDP_MUX_MUX6_Msk                           /*Select the HDP6 output among the 16 available signals*/
20959 #define HDP_MUX_MUX6_0              (0x1U << HDP_MUX_MUX6_Pos)                 /*!< 0x01000000 */
20960 #define HDP_MUX_MUX6_1              (0x2U << HDP_MUX_MUX6_Pos)                 /*!< 0x02000000 */
20961 #define HDP_MUX_MUX6_2              (0x4U << HDP_MUX_MUX6_Pos)                 /*!< 0x04000000 */
20962 #define HDP_MUX_MUX6_3              (0x8U << HDP_MUX_MUX6_Pos)                 /*!< 0x08000000 */
20963 #define HDP_MUX_MUX7_Pos            (28U)
20964 #define HDP_MUX_MUX7_Msk            (0xFU << HDP_MUX_MUX7_Pos)                 /*!< 0xF0000000 */
20965 #define HDP_MUX_MUX7                HDP_MUX_MUX7_Msk                           /*Select the HDP7 output among the 16 available signals*/
20966 #define HDP_MUX_MUX7_0              (0x1U << HDP_MUX_MUX7_Pos)                 /*!< 0x10000000 */
20967 #define HDP_MUX_MUX7_1              (0x2U << HDP_MUX_MUX7_Pos)                 /*!< 0x20000000 */
20968 #define HDP_MUX_MUX7_2              (0x4U << HDP_MUX_MUX7_Pos)                 /*!< 0x40000000 */
20969 #define HDP_MUX_MUX7_3              (0x8U << HDP_MUX_MUX7_Pos)                 /*!< 0x80000000 */
20970 
20971 /********************  Bit definition for HDP_VAL register*********************/
20972 #define HDP_VAL_HDPVAL_Pos          (0U)
20973 #define HDP_VAL_HDPVAL_Msk          (0xFFU << HDP_VAL_HDPVAL_Pos)              /*!< 0x000000FF */
20974 #define HDP_VAL_HDPVAL              HDP_VAL_HDPVAL_Msk                         /*Provide the value of the HDP signals*/
20975 
20976 /********************  Bit definition for HDP_GPOSET register*********************/
20977 #define HDP_GPOSET_HDPGPOSET_Pos    (0U)
20978 #define HDP_GPOSET_HDPGPOSET_Msk    (0xFFU << HDP_GPOSET_HDPGPOSET_Pos)        /*!< 0x000000FF */
20979 #define HDP_GPOSET_HDPGPOSET        HDP_GPOSET_HDPGPOSET_Msk                   /*When a bit is written to 1, the corresponding HDP GPO is seT*/
20980 
20981 /********************  Bit definition for HDP_GPOCLR register*********************/
20982 #define HDP_GPOCLR_HDPGPOCLR_Pos    (0U)
20983 #define HDP_GPOCLR_HDPGPOCLR_Msk    (0xFFU << HDP_GPOCLR_HDPGPOCLR_Pos)        /*!< 0x000000FF */
20984 #define HDP_GPOCLR_HDPGPOCLR        HDP_GPOCLR_HDPGPOCLR_Msk                   /*When a bit is written to 1, the corresponding HDP GPO is cleared*/
20985 
20986 /********************  Bit definition for HDP_GPOVAL register*********************/
20987 #define HDP_GPOVAL_HDPGPOVAL_Pos    (0U)
20988 #define HDP_GPOVAL_HDPGPOVAL_Msk    (0xFFU << HDP_GPOVAL_HDPGPOVAL_Pos)        /*!< 0x000000FF */
20989 #define HDP_GPOVAL_HDPGPOVAL        HDP_GPOVAL_HDPGPOVAL_Msk                   /*When written, define the value of the HDP GPO*/
20990 
20991 /********************  Bit definition for HDP_VERR register***********************/
20992 #define HDP_VERR_MINREV_Pos         (0U)
20993 #define HDP_VERR_MINREV_Msk         (0xFU << HDP_VERR_MINREV_Pos)              /*!< 0x0000000F */
20994 #define HDP_VERR_MINREV             HDP_VERR_MINREV_Msk                        /*Minor Revision of the IP*/
20995 #define HDP_VERR_MAJREV_Pos         (4U)
20996 #define HDP_VERR_MAJREV_Msk         (0xFU << HDP_VERR_MAJREV_Pos)              /*!< 0x000000F0 */
20997 #define HDP_VERR_MAJREV             HDP_VERR_MAJREV_Msk                        /*Major Revision of the IP*/
20998 
20999 /********************  Bit definition for HDP_IPIDR register**********************/
21000 #define HDP_IPIDR_ID_Pos            (0U)
21001 #define HDP_IPIDR_ID_Msk            (0xFFFFFFFFU << HDP_IPIDR_ID_Pos)          /*!< 0xFFFFFFFF */
21002 #define HDP_IPIDR_ID                HDP_IPIDR_ID_Msk                           /*IP Identifier*/
21003 
21004 /********************  Bit definition for HDP_SIDR register**********************/
21005 #define HDP_SIDR_SID_Pos            (0U)
21006 #define HDP_SIDR_SID_Msk            (0xFFFFFFFFU << HDP_SIDR_SID_Pos)          /*!< 0xFFFFFFFF */
21007 #define HDP_SIDR_SID                HDP_SIDR_SID_Msk                           /*Size Identifier*/
21008 
21009 
21010 /******************************************************************************/
21011 /*                                                                            */
21012 /*                         Reset and Clock Control                            */
21013 /*                                                                            */
21014 /******************************************************************************/
21015 /********************  Bit definition for RCC_TZCR register********************/
21016 #define RCC_TZCR_TZEN_Pos                     (0U)
21017 #define RCC_TZCR_TZEN_Msk                     (0x1U << RCC_TZCR_TZEN_Pos)      /*!< 0x00000001 */
21018 #define RCC_TZCR_TZEN                         RCC_TZCR_TZEN_Msk                /*TrustZone Enable*/
21019 #define RCC_TZCR_MCKPROT_Pos                  (1U)
21020 #define RCC_TZCR_MCKPROT_Msk                  (0x1U << RCC_TZCR_MCKPROT_Pos)   /*!< 0x00000002 */
21021 #define RCC_TZCR_MCKPROT                      RCC_TZCR_MCKPROT_Msk             /*Protection of the generation of ck_mcuss Enable*/
21022 
21023 /********************  Bit definition for RCC_OCENSETR register********************/
21024 #define RCC_OCENSETR_HSION_Pos                (0U)
21025 #define RCC_OCENSETR_HSION_Msk                (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */
21026 #define RCC_OCENSETR_HSION                    RCC_OCENSETR_HSION_Msk           /*Internal High Speed enable clock*/
21027 #define RCC_OCENSETR_HSIKERON_Pos             (1U)
21028 #define RCC_OCENSETR_HSIKERON_Msk             (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */
21029 #define RCC_OCENSETR_HSIKERON                 RCC_OCENSETR_HSIKERON_Msk        /*Force HSI to ON,even in stop mode ,in order to be quickly available*/
21030 #define RCC_OCENSETR_CSION_Pos                (4U)
21031 #define RCC_OCENSETR_CSION_Msk                (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */
21032 #define RCC_OCENSETR_CSION                    RCC_OCENSETR_CSION_Msk           /*CSI enable clock*/
21033 #define RCC_OCENSETR_CSIKERON_Pos             (5U)
21034 #define RCC_OCENSETR_CSIKERON_Msk             (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */
21035 #define RCC_OCENSETR_CSIKERON                 RCC_OCENSETR_CSIKERON_Msk        /*Force CSI to ON,eve in stop mode ,in order to be quickly available*/
21036 #define RCC_OCENSETR_DIGBYP_Pos               (7U)
21037 #define RCC_OCENSETR_DIGBYP_Msk               (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000040 */
21038 #define RCC_OCENSETR_DIGBYP                   RCC_OCENSETR_DIGBYP_Msk          /*Digital Bypass*/
21039 #define RCC_OCENSETR_HSEON_Pos                (8U)
21040 #define RCC_OCENSETR_HSEON_Msk                (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */
21041 #define RCC_OCENSETR_HSEON                    RCC_OCENSETR_HSEON_Msk           /*External High Speed enable clock*/
21042 #define RCC_OCENSETR_HSEKERON_Pos             (9U)
21043 #define RCC_OCENSETR_HSEKERON_Msk             (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */
21044 #define RCC_OCENSETR_HSEKERON                 RCC_OCENSETR_HSEKERON_Msk        /*Force HSE to ON,evne in stop mode ,in order to be quickly available*/
21045 #define RCC_OCENSETR_HSEBYP_Pos               (10U)
21046 #define RCC_OCENSETR_HSEBYP_Msk               (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */
21047 #define RCC_OCENSETR_HSEBYP                   RCC_OCENSETR_HSEBYP_Msk          /*HSE Bypass*/
21048 #define RCC_OCENSETR_HSECSSON_Pos             (11U)
21049 #define RCC_OCENSETR_HSECSSON_Msk             (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */
21050 #define RCC_OCENSETR_HSECSSON                 RCC_OCENSETR_HSECSSON_Msk        /*Clock Security System on HSE enable*/
21051 
21052 /********************  Bit definition for RCC_OCENCLRR register********************/
21053 #define RCC_OCENCLRR_HSION_Pos                (0U)
21054 #define RCC_OCENCLRR_HSION_Msk                (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */
21055 #define RCC_OCENCLRR_HSION                    RCC_OCENCLRR_HSION_Msk           /*clear of HSION bit*/
21056 #define RCC_OCENCLRR_HSIKERON_Pos             (1U)
21057 #define RCC_OCENCLRR_HSIKERON_Msk             (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */
21058 #define RCC_OCENCLRR_HSIKERON                 RCC_OCENCLRR_HSIKERON_Msk        /*clear of HSIKERON bit*/
21059 #define RCC_OCENCLRR_CSION_Pos                (4U)
21060 #define RCC_OCENCLRR_CSION_Msk                (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */
21061 #define RCC_OCENCLRR_CSION                    RCC_OCENCLRR_CSION_Msk           /*clear of CSION bit*/
21062 #define RCC_OCENCLRR_CSIKERON_Pos             (5U)
21063 #define RCC_OCENCLRR_CSIKERON_Msk             (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */
21064 #define RCC_OCENCLRR_CSIKERON                 RCC_OCENCLRR_CSIKERON_Msk        /*clear of CSIKERON bit*/
21065 #define RCC_OCENCLRR_DIGBYP_Pos               (7U)
21066 #define RCC_OCENCLRR_DIGBYP_Msk               (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000040 */
21067 #define RCC_OCENCLRR_DIGBYP                   RCC_OCENCLRR_DIGBYP_Msk          /*clear of DIGBYP bit*/
21068 #define RCC_OCENCLRR_HSEON_Pos                (8U)
21069 #define RCC_OCENCLRR_HSEON_Msk                (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */
21070 #define RCC_OCENCLRR_HSEON                    RCC_OCENCLRR_HSEON_Msk           /*clear of HSEON bit*/
21071 #define RCC_OCENCLRR_HSEKERON_Pos             (9U)
21072 #define RCC_OCENCLRR_HSEKERON_Msk             (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */
21073 #define RCC_OCENCLRR_HSEKERON                 RCC_OCENCLRR_HSEKERON_Msk        /*clear of HSEKERON bit*/
21074 #define RCC_OCENCLRR_HSEBYP_Pos               (10U)
21075 #define RCC_OCENCLRR_HSEBYP_Msk               (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */
21076 #define RCC_OCENCLRR_HSEBYP                   RCC_OCENCLRR_HSEBYP_Msk          /*clear the HSE Bypass bit*/
21077 
21078 /********************  Bit definition for RCC_OCRDYR register********************/
21079 #define RCC_OCRDYR_HSIRDY_Pos                 (0U)
21080 #define RCC_OCRDYR_HSIRDY_Msk                 (0x1U << RCC_OCRDYR_HSIRDY_Pos)  /*!< 0x00000001 */
21081 #define RCC_OCRDYR_HSIRDY                     RCC_OCRDYR_HSIRDY_Msk            /*HSI clock ready flag*/
21082 #define RCC_OCRDYR_HSIDIVRDY_Pos              (2U)
21083 #define RCC_OCRDYR_HSIDIVRDY_Msk              (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */
21084 #define RCC_OCRDYR_HSIDIVRDY                  RCC_OCRDYR_HSIDIVRDY_Msk         /*HSI divider ready flag*/
21085 #define RCC_OCRDYR_CSIRDY_Pos                 (4U)
21086 #define RCC_OCRDYR_CSIRDY_Msk                 (0x1U << RCC_OCRDYR_CSIRDY_Pos)  /*!< 0x00000010 */
21087 #define RCC_OCRDYR_CSIRDY                     RCC_OCRDYR_CSIRDY_Msk            /*CSI clock ready flag*/
21088 #define RCC_OCRDYR_HSERDY_Pos                 (8U)
21089 #define RCC_OCRDYR_HSERDY_Msk                 (0x1U << RCC_OCRDYR_HSERDY_Pos)  /*!< 0x00000100 */
21090 #define RCC_OCRDYR_HSERDY                     RCC_OCRDYR_HSERDY_Msk            /*HSE clock ready flag*/
21091 #define RCC_OCRDYR_AXICKRDY_Pos               (24U)
21092 #define RCC_OCRDYR_AXICKRDY_Msk               (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */
21093 #define RCC_OCRDYR_AXICKRDY                   RCC_OCRDYR_AXICKRDY_Msk          /*AXI sub-system clock ready flag*/
21094 #define RCC_OCRDYR_CKREST_Pos                 (25U)
21095 #define RCC_OCRDYR_CKREST_Msk                 (0x1U << RCC_OCRDYR_CKREST_Pos)  /*!< 0x02000000 */
21096 #define RCC_OCRDYR_CKREST                     RCC_OCRDYR_CKREST_Msk            /*Clock Restore State Machine Status*/
21097 
21098 /********************  Bit definition for RCC_DBGCFGR register********************/
21099 #define RCC_DBGCFGR_TRACEDIV_Pos              (0U)
21100 #define RCC_DBGCFGR_TRACEDIV_Msk              (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */
21101 #define RCC_DBGCFGR_TRACEDIV                  RCC_DBGCFGR_TRACEDIV_Msk         /*clock divider for the trace clock*/
21102 #define RCC_DBGCFGR_DBGCKEN_Pos               (8U)
21103 #define RCC_DBGCFGR_DBGCKEN_Msk               (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */
21104 #define RCC_DBGCFGR_DBGCKEN                   RCC_DBGCFGR_DBGCKEN_Msk          /*clock enable for debug function*/
21105 #define RCC_DBGCFGR_TRACECKEN_Pos             (9U)
21106 #define RCC_DBGCFGR_TRACECKEN_Msk             (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */
21107 #define RCC_DBGCFGR_TRACECKEN                 RCC_DBGCFGR_TRACECKEN_Msk        /*clock enable for trace function*/
21108 #define RCC_DBGCFGR_DBGRST_Pos                (12U)
21109 #define RCC_DBGCFGR_DBGRST_Msk                (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */
21110 #define RCC_DBGCFGR_DBGRST                    RCC_DBGCFGR_DBGRST_Msk           /*Reset of the debug function*/
21111 
21112 /********************  Bit definition for RCC_HSICFGR register********************/
21113 #define RCC_HSICFGR_HSIDIV_Pos                (0U)
21114 #define RCC_HSICFGR_HSIDIV_Msk                (0x3U << RCC_HSICFGR_HSIDIV_Pos)
21115 #define RCC_HSICFGR_HSIDIV                    RCC_HSICFGR_HSIDIV_Msk           /* HSI clock divider*/
21116 #define RCC_HSICFGR_HSIDIV_0                  (0x0U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 1 (default after reset)*/
21117 #define RCC_HSICFGR_HSIDIV_1                  (0x1U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 2 */
21118 #define RCC_HSICFGR_HSIDIV_2                  (0x2U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 4 */
21119 #define RCC_HSICFGR_HSIDIV_3                  (0x3U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 8 */
21120 
21121 #define RCC_HSICFGR_HSITRIM_Pos               (8U)
21122 #define RCC_HSICFGR_HSITRIM_Msk               (0x3FU << RCC_HSICFGR_HSITRIM_Pos)
21123 #define RCC_HSICFGR_HSITRIM                   RCC_HSICFGR_HSITRIM_Msk           /*HSI clock trimming*/
21124 
21125 #define RCC_HSICFGR_HSICAL_Pos                (16U)
21126 #define RCC_HSICFGR_HSICAL_Msk                (0xFFFU << RCC_HSICFGR_HSICAL_Pos)
21127 #define RCC_HSICFGR_HSICAL                    RCC_HSICFGR_HSICAL_Msk            /*HSI clock calibration*/
21128 
21129 /********************  Bit definition for RCC_CSICFGR register********************/
21130 #define RCC_CSICFGR_CSITRIM_Pos               (8U)
21131 #define RCC_CSICFGR_CSITRIM_Msk               (0x1FU << RCC_CSICFGR_CSITRIM_Pos)
21132 #define RCC_CSICFGR_CSITRIM                   RCC_CSICFGR_CSITRIM_Msk           /*CSI clock trimming*/
21133 
21134 #define RCC_CSICFGR_CSICAL_Pos                (16U)
21135 #define RCC_CSICFGR_CSICAL_Msk                (0xFFU << RCC_CSICFGR_CSICAL_Pos)
21136 #define RCC_CSICFGR_CSICAL                    RCC_CSICFGR_CSICAL_Msk            /*CSI clock calibration*/
21137 
21138 /********************  Bit definition for RCC_MCO1CFGR register********************/
21139 #define RCC_MCO1CFGR_MCO1SEL_Pos              (0U)
21140 #define RCC_MCO1CFGR_MCO1SEL_Msk              (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */
21141 #define RCC_MCO1CFGR_MCO1SEL                  RCC_MCO1CFGR_MCO1SEL_Msk         /*MCO1 clock output selection*/
21142 #define RCC_MCO1CFGR_MCO1SEL_0                (0x0U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000000 */
21143 #define RCC_MCO1CFGR_MCO1SEL_1                (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */
21144 #define RCC_MCO1CFGR_MCO1SEL_2                (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */
21145 #define RCC_MCO1CFGR_MCO1SEL_3                (0x3U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000003 */
21146 #define RCC_MCO1CFGR_MCO1SEL_4                (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */
21147 
21148 #define RCC_MCO1CFGR_MCO1DIV_Pos              (4U)
21149 #define RCC_MCO1CFGR_MCO1DIV_Msk              (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */
21150 #define RCC_MCO1CFGR_MCO1DIV                  RCC_MCO1CFGR_MCO1DIV_Msk         /*MCO1 prescaler*/
21151 #define RCC_MCO1CFGR_MCO1DIV_0                (0x0U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000000 */
21152 #define RCC_MCO1CFGR_MCO1DIV_1                (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */
21153 #define RCC_MCO1CFGR_MCO1DIV_2                (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */
21154 #define RCC_MCO1CFGR_MCO1DIV_3                (0x3U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000030 */
21155 #define RCC_MCO1CFGR_MCO1DIV_4                (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */
21156 #define RCC_MCO1CFGR_MCO1DIV_5                (0x5U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000050 */
21157 #define RCC_MCO1CFGR_MCO1DIV_6                (0x6U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000060 */
21158 #define RCC_MCO1CFGR_MCO1DIV_7                (0x7U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000070 */
21159 #define RCC_MCO1CFGR_MCO1DIV_8                (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */
21160 #define RCC_MCO1CFGR_MCO1DIV_9                (0x9U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000090 */
21161 #define RCC_MCO1CFGR_MCO1DIV_10               (0xAU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000A0 */
21162 #define RCC_MCO1CFGR_MCO1DIV_11               (0xBU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000B0 */
21163 #define RCC_MCO1CFGR_MCO1DIV_12               (0xCU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000C0 */
21164 #define RCC_MCO1CFGR_MCO1DIV_13               (0xDU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000D0 */
21165 #define RCC_MCO1CFGR_MCO1DIV_14               (0xEU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000E0 */
21166 #define RCC_MCO1CFGR_MCO1DIV_15               (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */
21167 
21168 #define RCC_MCO1CFGR_MCO1ON_Pos               (12U)
21169 #define RCC_MCO1CFGR_MCO1ON_Msk               (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */
21170 #define RCC_MCO1CFGR_MCO1ON                   RCC_MCO1CFGR_MCO1ON_Msk          /*Control the MCO1 output*/
21171 
21172 /********************  Bit definition for RCC_MCO2CFGR register********************/
21173 #define RCC_MCO2CFGR_MCO2SEL_Pos              (0U)
21174 #define RCC_MCO2CFGR_MCO2SEL_Msk              (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */
21175 #define RCC_MCO2CFGR_MCO2SEL                  RCC_MCO2CFGR_MCO2SEL_Msk         /*MCO2 clock output selection*/
21176 #define RCC_MCO2CFGR_MCO2SEL_0                (0x0U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000000 */
21177 #define RCC_MCO2CFGR_MCO2SEL_1                (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */
21178 #define RCC_MCO2CFGR_MCO2SEL_2                (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */
21179 #define RCC_MCO2CFGR_MCO2SEL_3                (0x3U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000003 */
21180 #define RCC_MCO2CFGR_MCO2SEL_4                (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */
21181 #define RCC_MCO2CFGR_MCO2SEL_5                (0x5U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000005 */
21182 
21183 #define RCC_MCO2CFGR_MCO2DIV_Pos              (4U)
21184 #define RCC_MCO2CFGR_MCO2DIV_Msk              (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */
21185 #define RCC_MCO2CFGR_MCO2DIV                  RCC_MCO2CFGR_MCO2DIV_Msk         /*MCO2 prescaler*/
21186 #define RCC_MCO2CFGR_MCO2DIV_0                (0x0U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000000 */
21187 #define RCC_MCO2CFGR_MCO2DIV_1                (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */
21188 #define RCC_MCO2CFGR_MCO2DIV_2                (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */
21189 #define RCC_MCO2CFGR_MCO2DIV_3                (0x3U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000030 */
21190 #define RCC_MCO2CFGR_MCO2DIV_4                (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */
21191 #define RCC_MCO2CFGR_MCO2DIV_5                (0x5U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000050 */
21192 #define RCC_MCO2CFGR_MCO2DIV_6                (0x6U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000060 */
21193 #define RCC_MCO2CFGR_MCO2DIV_7                (0x7U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000070 */
21194 #define RCC_MCO2CFGR_MCO2DIV_8                (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */
21195 #define RCC_MCO2CFGR_MCO2DIV_9                (0x9U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000090 */
21196 #define RCC_MCO2CFGR_MCO2DIV_10               (0xAU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000A0 */
21197 #define RCC_MCO2CFGR_MCO2DIV_11               (0xBU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000B0 */
21198 #define RCC_MCO2CFGR_MCO2DIV_12               (0xCU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000C0 */
21199 #define RCC_MCO2CFGR_MCO2DIV_13               (0xDU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000D0 */
21200 #define RCC_MCO2CFGR_MCO2DIV_14               (0xEU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000E0 */
21201 #define RCC_MCO2CFGR_MCO2DIV_15               (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */
21202 
21203 #define RCC_MCO2CFGR_MCO2ON_Pos               (12U)
21204 #define RCC_MCO2CFGR_MCO2ON_Msk               (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */
21205 #define RCC_MCO2CFGR_MCO2ON                   RCC_MCO2CFGR_MCO2ON_Msk          /*contorl the MCO2 output*/
21206 
21207 /********************  Bit definition for RCC_MPCKSELR register********************/
21208 #define RCC_MPCKSELR_MPUSRC_Pos               (0U)
21209 #define RCC_MPCKSELR_MPUSRC_Msk               (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */
21210 #define RCC_MPCKSELR_MPUSRC                   RCC_MPCKSELR_MPUSRC_Msk          /*MPU clock switch*/
21211 #define RCC_MPCKSELR_MPUSRC_0                 (0x0U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000000 */
21212 #define RCC_MPCKSELR_MPUSRC_1                 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */
21213 #define RCC_MPCKSELR_MPUSRC_2                 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */
21214 #define RCC_MPCKSELR_MPUSRC_3                 (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */
21215 
21216 
21217 #define RCC_MPCKSELR_MPUSRCRDY_Pos            (31U)
21218 #define RCC_MPCKSELR_MPUSRCRDY_Msk            (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */
21219 #define RCC_MPCKSELR_MPUSRCRDY                RCC_MPCKSELR_MPUSRCRDY_Msk       /*MPU clock switch status*/
21220 
21221 /********************  Bit definition for RCC_ASSCKSELR register********************/
21222 #define RCC_ASSCKSELR_AXISSRC_Pos             (0U)
21223 #define RCC_ASSCKSELR_AXISSRC_Msk             (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */
21224 #define RCC_ASSCKSELR_AXISSRC                 RCC_ASSCKSELR_AXISSRC_Msk        /*AXI sub-system clock switch*/
21225 #define RCC_ASSCKSELR_AXISSRC_0               (0x0U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000000 */
21226 #define RCC_ASSCKSELR_AXISSRC_1               (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */
21227 #define RCC_ASSCKSELR_AXISSRC_2               (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */
21228 #define RCC_ASSCKSELR_AXISSRC_3               (0x3U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000003 */
21229 #define RCC_ASSCKSELR_AXISSRC_4               (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */
21230 #define RCC_ASSCKSELR_AXISSRC_5               (0x5U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000005 */
21231 #define RCC_ASSCKSELR_AXISSRC_6               (0x6U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000006 */
21232 #define RCC_ASSCKSELR_AXISSRC_7               (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */
21233 
21234 #define RCC_ASSCKSELR_AXISSRCRDY_Pos          (31U)
21235 #define RCC_ASSCKSELR_AXISSRCRDY_Msk          (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */
21236 #define RCC_ASSCKSELR_AXISSRCRDY              RCC_ASSCKSELR_AXISSRCRDY_Msk     /*AXI sub-system clock switch status*/
21237 
21238 /********************  Bit definition for RCC_MSSCKSELR register********************/
21239 #define RCC_MSSCKSELR_MCUSSRC_Pos             (0U)
21240 #define RCC_MSSCKSELR_MCUSSRC_Msk             (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */
21241 #define RCC_MSSCKSELR_MCUSSRC                 RCC_MSSCKSELR_MCUSSRC_Msk        /*MCU sub-system clock switch*/
21242 #define RCC_MSSCKSELR_MCUSSRC_0               (0x0U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000000 */
21243 #define RCC_MSSCKSELR_MCUSSRC_1               (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */
21244 #define RCC_MSSCKSELR_MCUSSRC_2               (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */
21245 #define RCC_MSSCKSELR_MCUSSRC_3               (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */
21246 
21247 #define RCC_MSSCKSELR_MCUSSRCRDY_Pos          (31U)
21248 #define RCC_MSSCKSELR_MCUSSRCRDY_Msk          (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */
21249 #define RCC_MSSCKSELR_MCUSSRCRDY              RCC_MSSCKSELR_MCUSSRCRDY_Msk     /*MCU sub-system clock switch status*/
21250 
21251 /********************  Bit definition for RCC_RCK12SELR register********************/
21252 #define RCC_RCK12SELR_PLL12SRC_Pos            (0U)
21253 #define RCC_RCK12SELR_PLL12SRC_Msk            (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */
21254 #define RCC_RCK12SELR_PLL12SRC                RCC_RCK12SELR_PLL12SRC_Msk       /*Reference clock selection for PLL1 and PLL2*/
21255 #define RCC_RCK12SELR_PLL12SRC_0              (0x0U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000000 */
21256 #define RCC_RCK12SELR_PLL12SRC_1              (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */
21257 #define RCC_RCK12SELR_PLL12SRC_2              (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */
21258 #define RCC_RCK12SELR_PLL12SRC_3              (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */
21259 #define RCC_RCK12SELR_PLL12SRC_4              (0x4U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000004 */
21260 #define RCC_RCK12SELR_PLL12SRC_5              (0x5U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000005 */
21261 #define RCC_RCK12SELR_PLL12SRC_6              (0x6U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000006 */
21262 #define RCC_RCK12SELR_PLL12SRC_7              (0x7U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000007 */
21263 
21264 #define RCC_RCK12SELR_PLL12SRCRDY_Pos         (31U)
21265 #define RCC_RCK12SELR_PLL12SRCRDY_Msk         (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */
21266 #define RCC_RCK12SELR_PLL12SRCRDY             RCC_RCK12SELR_PLL12SRCRDY_Msk    /*PLL12 reference clock switch status*/
21267 
21268 /********************  Bit definition for RCC_RCK3SELR register********************/
21269 #define RCC_RCK3SELR_PLL3SRC_Pos              (0U)
21270 #define RCC_RCK3SELR_PLL3SRC_Msk              (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */
21271 #define RCC_RCK3SELR_PLL3SRC                  RCC_RCK3SELR_PLL3SRC_Msk         /*Reference clock selection for PLL3*/
21272 #define RCC_RCK3SELR_PLL3SRC_0                (0x0U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000000 */
21273 #define RCC_RCK3SELR_PLL3SRC_1                (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */
21274 #define RCC_RCK3SELR_PLL3SRC_2                (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */
21275 #define RCC_RCK3SELR_PLL3SRC_3                (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */
21276 
21277 #define RCC_RCK3SELR_PLL3SRCRDY_Pos           (31U)
21278 #define RCC_RCK3SELR_PLL3SRCRDY_Msk           (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */
21279 #define RCC_RCK3SELR_PLL3SRCRDY               RCC_RCK3SELR_PLL3SRCRDY_Msk      /*PLL3 reference clock switch status*/
21280 
21281 /********************  Bit definition for RCC_RCK4SELR register********************/
21282 #define RCC_RCK4SELR_PLL4SRC_Pos              (0U)
21283 #define RCC_RCK4SELR_PLL4SRC_Msk              (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */
21284 #define RCC_RCK4SELR_PLL4SRC                  RCC_RCK4SELR_PLL4SRC_Msk         /*Reference clock selection for PLL4*/
21285 #define RCC_RCK4SELR_PLL4SRC_0                (0x0U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000000 */
21286 #define RCC_RCK4SELR_PLL4SRC_1                (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */
21287 #define RCC_RCK4SELR_PLL4SRC_2                (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */
21288 #define RCC_RCK4SELR_PLL4SRC_3                (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */
21289 
21290 #define RCC_RCK4SELR_PLL4SRCRDY_Pos           (31U)
21291 #define RCC_RCK4SELR_PLL4SRCRDY_Msk           (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */
21292 #define RCC_RCK4SELR_PLL4SRCRDY               RCC_RCK4SELR_PLL4SRCRDY_Msk      /*PLL4 reference clock switch status*/
21293 
21294 /********************  Bit definition for RCC_TIMG1PRER register********************/
21295 #define RCC_TIMG1PRER_TIMG1PRE_Pos            (0U)
21296 #define RCC_TIMG1PRER_TIMG1PRE_Msk            (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */
21297 #define RCC_TIMG1PRER_TIMG1PRE                RCC_TIMG1PRER_TIMG1PRE_Msk       /*Timers clocks prescaler selection*/
21298 #define RCC_TIMG1PRER_TIMG1PRE_0              (0x0U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000000 */
21299                                                                               /*corresponding to a division by 1 or 2, else it is equal to
21300                                                                               2 x Fck_pclk1 (default after reset)*/
21301 #define RCC_TIMG1PRER_TIMG1PRE_1              ((uint32_t)0x00000001)           /*The Timers kernel clock is equal to ck_hclk if APB1DIV is
21302                                                                               corresponding to division by 1, 2 or 4, else it is equal to
21303                                                                               4 x Fck_pclk1 */
21304 
21305 #define RCC_TIMG1PRER_TIMG1PRERDY_Pos         (31U)
21306 #define RCC_TIMG1PRER_TIMG1PRERDY_Msk         (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */
21307 #define RCC_TIMG1PRER_TIMG1PRERDY             RCC_TIMG1PRER_TIMG1PRERDY_Msk    /*Timers clocks prescaler status*/
21308 
21309 /********************  Bit definition for RCC_TIMG2PRER register********************/
21310 #define RCC_TIMG2PRER_TIMG2PRE_Pos            (0U)
21311 #define RCC_TIMG2PRER_TIMG2PRE_Msk            (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */
21312 #define RCC_TIMG2PRER_TIMG2PRE                RCC_TIMG2PRER_TIMG2PRE_Msk       /*Timers clocks prescaler selection*/
21313 #define RCC_TIMG2PRER_TIMG2PRE_0              (0x0U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000000 */
21314                                                                               /*corresponding to a division by 1 or 2, else it is equal
21315                                                                               to 2 x Fck_pclk2 (default after reset)*/
21316 #define RCC_TIMG2PRER_TIMG2PRE_1              ((uint32_t)0x00000001)           /*The Timers kernel clock is equal to ck_hclk if APB2DIV is
21317                                                                               corresponding to division by 1, 2 or 4, else it is equal to
21318                                                                               4 x Fck_pclk2 */
21319 
21320 #define RCC_TIMG2PRER_TIMG2PRERDY_Pos         (31U)
21321 #define RCC_TIMG2PRER_TIMG2PRERDY_Msk         (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */
21322 #define RCC_TIMG2PRER_TIMG2PRERDY             RCC_TIMG2PRER_TIMG2PRERDY_Msk    /*Timers clocks prescaler status*/
21323 
21324 /********************  Bit definition for RCC_RTCDIVR register********************/
21325 #define RCC_RTCDIVR_RTCDIV_Pos                (0U)
21326 #define RCC_RTCDIVR_RTCDIV_Msk                (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */
21327 #define RCC_RTCDIVR_RTCDIV                    RCC_RTCDIVR_RTCDIV_Msk           /*HSE division factor for RTC clock*/
21328 #define RCC_RTCDIVR_RTCDIV_1                  (0x0U << RCC_RTCDIVR_RTCDIV_Pos)
21329 #define RCC_RTCDIVR_RTCDIV_2                  (0x1U << RCC_RTCDIVR_RTCDIV_Pos)
21330 #define RCC_RTCDIVR_RTCDIV_3                  (0x2U << RCC_RTCDIVR_RTCDIV_Pos)
21331 #define RCC_RTCDIVR_RTCDIV_4                  (0x3U << RCC_RTCDIVR_RTCDIV_Pos)
21332 #define RCC_RTCDIVR_RTCDIV_5                  (0x4U << RCC_RTCDIVR_RTCDIV_Pos)
21333 #define RCC_RTCDIVR_RTCDIV_6                  (0x5U << RCC_RTCDIVR_RTCDIV_Pos)
21334 #define RCC_RTCDIVR_RTCDIV_7                  (0x6U << RCC_RTCDIVR_RTCDIV_Pos)
21335 #define RCC_RTCDIVR_RTCDIV_8                  (0x7U << RCC_RTCDIVR_RTCDIV_Pos)
21336 #define RCC_RTCDIVR_RTCDIV_9                  (0x8U << RCC_RTCDIVR_RTCDIV_Pos)
21337 #define RCC_RTCDIVR_RTCDIV_10                 (0x9U << RCC_RTCDIVR_RTCDIV_Pos)
21338 #define RCC_RTCDIVR_RTCDIV_11                 (0xAU << RCC_RTCDIVR_RTCDIV_Pos)
21339 #define RCC_RTCDIVR_RTCDIV_12                 (0xBU << RCC_RTCDIVR_RTCDIV_Pos)
21340 #define RCC_RTCDIVR_RTCDIV_13                 (0xCU << RCC_RTCDIVR_RTCDIV_Pos)
21341 #define RCC_RTCDIVR_RTCDIV_14                 (0xDU << RCC_RTCDIVR_RTCDIV_Pos)
21342 #define RCC_RTCDIVR_RTCDIV_15                 (0xEU << RCC_RTCDIVR_RTCDIV_Pos)
21343 #define RCC_RTCDIVR_RTCDIV_16                 (0xFU << RCC_RTCDIVR_RTCDIV_Pos)
21344 #define RCC_RTCDIVR_RTCDIV_17                 (0x10U << RCC_RTCDIVR_RTCDIV_Pos)
21345 #define RCC_RTCDIVR_RTCDIV_18                 (0x11U << RCC_RTCDIVR_RTCDIV_Pos)
21346 #define RCC_RTCDIVR_RTCDIV_19                 (0x12U << RCC_RTCDIVR_RTCDIV_Pos)
21347 #define RCC_RTCDIVR_RTCDIV_20                 (0x13U << RCC_RTCDIVR_RTCDIV_Pos)
21348 #define RCC_RTCDIVR_RTCDIV_21                 (0x14U << RCC_RTCDIVR_RTCDIV_Pos)
21349 #define RCC_RTCDIVR_RTCDIV_22                 (0x15U << RCC_RTCDIVR_RTCDIV_Pos)
21350 #define RCC_RTCDIVR_RTCDIV_23                 (0x16U << RCC_RTCDIVR_RTCDIV_Pos)
21351 #define RCC_RTCDIVR_RTCDIV_24                 (0x17U << RCC_RTCDIVR_RTCDIV_Pos)
21352 #define RCC_RTCDIVR_RTCDIV_25                 (0x18U << RCC_RTCDIVR_RTCDIV_Pos)
21353 #define RCC_RTCDIVR_RTCDIV_26                 (0x19U << RCC_RTCDIVR_RTCDIV_Pos)
21354 #define RCC_RTCDIVR_RTCDIV_27                 (0x1AU << RCC_RTCDIVR_RTCDIV_Pos)
21355 #define RCC_RTCDIVR_RTCDIV_28                 (0x1BU << RCC_RTCDIVR_RTCDIV_Pos)
21356 #define RCC_RTCDIVR_RTCDIV_29                 (0x1CU << RCC_RTCDIVR_RTCDIV_Pos)
21357 #define RCC_RTCDIVR_RTCDIV_30                 (0x1DU << RCC_RTCDIVR_RTCDIV_Pos)
21358 #define RCC_RTCDIVR_RTCDIV_31                 (0x1EU << RCC_RTCDIVR_RTCDIV_Pos)
21359 #define RCC_RTCDIVR_RTCDIV_32                 (0x1FU << RCC_RTCDIVR_RTCDIV_Pos)
21360 #define RCC_RTCDIVR_RTCDIV_33                 (0x20U << RCC_RTCDIVR_RTCDIV_Pos)
21361 #define RCC_RTCDIVR_RTCDIV_34                 (0x21U << RCC_RTCDIVR_RTCDIV_Pos)
21362 #define RCC_RTCDIVR_RTCDIV_35                 (0x22U << RCC_RTCDIVR_RTCDIV_Pos)
21363 #define RCC_RTCDIVR_RTCDIV_36                 (0x23U << RCC_RTCDIVR_RTCDIV_Pos)
21364 #define RCC_RTCDIVR_RTCDIV_37                 (0x24U << RCC_RTCDIVR_RTCDIV_Pos)
21365 #define RCC_RTCDIVR_RTCDIV_38                 (0x25U << RCC_RTCDIVR_RTCDIV_Pos)
21366 #define RCC_RTCDIVR_RTCDIV_39                 (0x26U << RCC_RTCDIVR_RTCDIV_Pos)
21367 #define RCC_RTCDIVR_RTCDIV_40                 (0x27U << RCC_RTCDIVR_RTCDIV_Pos)
21368 #define RCC_RTCDIVR_RTCDIV_41                 (0x28U << RCC_RTCDIVR_RTCDIV_Pos)
21369 #define RCC_RTCDIVR_RTCDIV_42                 (0x29U << RCC_RTCDIVR_RTCDIV_Pos)
21370 #define RCC_RTCDIVR_RTCDIV_43                 (0x2AU << RCC_RTCDIVR_RTCDIV_Pos)
21371 #define RCC_RTCDIVR_RTCDIV_44                 (0x2BU << RCC_RTCDIVR_RTCDIV_Pos)
21372 #define RCC_RTCDIVR_RTCDIV_45                 (0x2CU << RCC_RTCDIVR_RTCDIV_Pos)
21373 #define RCC_RTCDIVR_RTCDIV_46                 (0x2DU << RCC_RTCDIVR_RTCDIV_Pos)
21374 #define RCC_RTCDIVR_RTCDIV_47                 (0x2EU << RCC_RTCDIVR_RTCDIV_Pos)
21375 #define RCC_RTCDIVR_RTCDIV_48                 (0x2FU << RCC_RTCDIVR_RTCDIV_Pos)
21376 #define RCC_RTCDIVR_RTCDIV_49                 (0x30U << RCC_RTCDIVR_RTCDIV_Pos)
21377 #define RCC_RTCDIVR_RTCDIV_50                 (0x31U << RCC_RTCDIVR_RTCDIV_Pos)
21378 #define RCC_RTCDIVR_RTCDIV_51                 (0x32U << RCC_RTCDIVR_RTCDIV_Pos)
21379 #define RCC_RTCDIVR_RTCDIV_52                 (0x33U << RCC_RTCDIVR_RTCDIV_Pos)
21380 #define RCC_RTCDIVR_RTCDIV_53                 (0x34U << RCC_RTCDIVR_RTCDIV_Pos)
21381 #define RCC_RTCDIVR_RTCDIV_54                 (0x35U << RCC_RTCDIVR_RTCDIV_Pos)
21382 #define RCC_RTCDIVR_RTCDIV_55                 (0x36U << RCC_RTCDIVR_RTCDIV_Pos)
21383 #define RCC_RTCDIVR_RTCDIV_56                 (0x37U << RCC_RTCDIVR_RTCDIV_Pos)
21384 #define RCC_RTCDIVR_RTCDIV_57                 (0x38U << RCC_RTCDIVR_RTCDIV_Pos)
21385 #define RCC_RTCDIVR_RTCDIV_58                 (0x39U << RCC_RTCDIVR_RTCDIV_Pos)
21386 #define RCC_RTCDIVR_RTCDIV_59                 (0x3AU << RCC_RTCDIVR_RTCDIV_Pos)
21387 #define RCC_RTCDIVR_RTCDIV_60                 (0x3BU << RCC_RTCDIVR_RTCDIV_Pos)
21388 #define RCC_RTCDIVR_RTCDIV_61                 (0x3CU << RCC_RTCDIVR_RTCDIV_Pos)
21389 #define RCC_RTCDIVR_RTCDIV_62                 (0x3DU << RCC_RTCDIVR_RTCDIV_Pos)
21390 #define RCC_RTCDIVR_RTCDIV_63                 (0x3EU << RCC_RTCDIVR_RTCDIV_Pos)
21391 #define RCC_RTCDIVR_RTCDIV_64                 (0x3FU << RCC_RTCDIVR_RTCDIV_Pos)
21392 
21393 #define  RCC_RTCDIVR_RTCDIV_(y)              ( (uint32_t)  (y-1) )         /*00:HSE, 01:HSE/2... 63: HSE/64*/
21394 
21395 /********************  Bit definition for RCC_MPCKDIVR register********************/
21396 #define RCC_MPCKDIVR_MPUDIV_Pos               (0U)
21397 #define RCC_MPCKDIVR_MPUDIV_Msk               (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */
21398 #define RCC_MPCKDIVR_MPUDIV                   RCC_MPCKDIVR_MPUDIV_Msk          /*MPU Core clock divider*/
21399 #define RCC_MPCKDIVR_MPUDIV_0                 (0x0U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000000 */
21400 #define RCC_MPCKDIVR_MPUDIV_1                 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */
21401 #define RCC_MPCKDIVR_MPUDIV_2                 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */
21402 #define RCC_MPCKDIVR_MPUDIV_3                 (0x3U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000003 */
21403 #define RCC_MPCKDIVR_MPUDIV_4                 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */
21404 #define RCC_MPCKDIVR_MPUDIV_5                 (0x5U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000005 */
21405 #define RCC_MPCKDIVR_MPUDIV_6                 (0x6U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000006 */
21406 #define RCC_MPCKDIVR_MPUDIV_7                 (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */
21407 
21408 #define RCC_MPCKDIVR_MPUDIVRDY_Pos            (31U)
21409 #define RCC_MPCKDIVR_MPUDIVRDY_Msk            (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */
21410 #define RCC_MPCKDIVR_MPUDIVRDY                RCC_MPCKDIVR_MPUDIVRDY_Msk       /*MPU sub-system clock divider status*/
21411 
21412 /********************  Bit definition for RCC_AXIDIVR register********************/
21413 #define RCC_AXIDIVR_AXIDIV_Pos                (0U)
21414 #define RCC_AXIDIVR_AXIDIV_Msk                (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */
21415 #define RCC_AXIDIVR_AXIDIV                    RCC_AXIDIVR_AXIDIV_Msk           /*AXI, AHB5 and AHB6 clock divider*/
21416 #define RCC_AXIDIVR_AXIDIV_0                  (0x0U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000000 */
21417 #define RCC_AXIDIVR_AXIDIV_1                  (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */
21418 #define RCC_AXIDIVR_AXIDIV_2                  (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */
21419 #define RCC_AXIDIVR_AXIDIV_3                  (0x3U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000003 */
21420 #define RCC_AXIDIVR_AXIDIV_4                  (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */
21421 #define RCC_AXIDIVR_AXIDIV_5                  (0x5U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000005 */
21422 #define RCC_AXIDIVR_AXIDIV_6                  (0x6U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000006 */
21423 #define RCC_AXIDIVR_AXIDIV_7                  (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */
21424 
21425 #define RCC_AXIDIVR_AXIDIVRDY_Pos             (31U)
21426 #define RCC_AXIDIVR_AXIDIVRDY_Msk             (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */
21427 #define RCC_AXIDIVR_AXIDIVRDY                 RCC_AXIDIVR_AXIDIVRDY_Msk        /*AXI sub-system clock divider status*/
21428 
21429 /********************  Bit definition for RCC_APB4DIVR register********************/
21430 #define RCC_APB4DIVR_APB4DIV_Pos              (0U)
21431 #define RCC_APB4DIVR_APB4DIV_Msk              (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */
21432 #define RCC_APB4DIVR_APB4DIV                  RCC_APB4DIVR_APB4DIV_Msk         /*APB4 clock divider */
21433 #define RCC_APB4DIVR_APB4DIV_0                (0x0U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000000 */
21434 #define RCC_APB4DIVR_APB4DIV_1                (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */
21435 #define RCC_APB4DIVR_APB4DIV_2                (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */
21436 #define RCC_APB4DIVR_APB4DIV_3                (0x3U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000003 */
21437 #define RCC_APB4DIVR_APB4DIV_4                (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */
21438 #define RCC_APB4DIVR_APB4DIV_5                (0x5U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000005 */
21439 #define RCC_APB4DIVR_APB4DIV_6                (0x6U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000006 */
21440 #define RCC_APB4DIVR_APB4DIV_7                (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */
21441 
21442 #define RCC_APB4DIVR_APB4DIVRDY_Pos           (31U)
21443 #define RCC_APB4DIVR_APB4DIVRDY_Msk           (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */
21444 #define RCC_APB4DIVR_APB4DIVRDY               RCC_APB4DIVR_APB4DIVRDY_Msk      /*APB4 clock divider status*/
21445 
21446 /********************  Bit definition for RCC_APB5DIVR register********************/
21447 #define RCC_APB5DIVR_APB5DIV_Pos              (0U)
21448 #define RCC_APB5DIVR_APB5DIV_Msk              (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */
21449 #define RCC_APB5DIVR_APB5DIV                  RCC_APB5DIVR_APB5DIV_Msk         /*APB5 clock divider*/
21450 #define RCC_APB5DIVR_APB5DIV_0                (0x0U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000000 */
21451 #define RCC_APB5DIVR_APB5DIV_1                (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */
21452 #define RCC_APB5DIVR_APB5DIV_2                (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */
21453 #define RCC_APB5DIVR_APB5DIV_3                (0x3U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000003 */
21454 #define RCC_APB5DIVR_APB5DIV_4                (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */
21455 #define RCC_APB5DIVR_APB5DIV_5                (0x5U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000005 */
21456 #define RCC_APB5DIVR_APB5DIV_6                (0x6U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000006 */
21457 #define RCC_APB5DIVR_APB5DIV_7                (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */
21458 
21459 #define RCC_APB5DIVR_APB5DIVRDY_Pos           (31U)
21460 #define RCC_APB5DIVR_APB5DIVRDY_Msk           (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */
21461 #define RCC_APB5DIVR_APB5DIVRDY               RCC_APB5DIVR_APB5DIVRDY_Msk      /*APB5 clock divider status*/
21462 
21463 /********************  Bit definition for RCC_MCUDIVR register********************/
21464 #define RCC_MCUDIVR_MCUDIV_Pos                (0U)
21465 #define RCC_MCUDIVR_MCUDIV_Msk                (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */
21466 #define RCC_MCUDIVR_MCUDIV                    RCC_MCUDIVR_MCUDIV_Msk           /*MCU clock divider*/
21467 #define RCC_MCUDIVR_MCUDIV_0                  (0x0U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000000 */
21468 #define RCC_MCUDIVR_MCUDIV_1                  (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */
21469 #define RCC_MCUDIVR_MCUDIV_2                  (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */
21470 #define RCC_MCUDIVR_MCUDIV_3                  (0x3U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000003 */
21471 #define RCC_MCUDIVR_MCUDIV_4                  (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */
21472 #define RCC_MCUDIVR_MCUDIV_5                  (0x5U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000005 */
21473 #define RCC_MCUDIVR_MCUDIV_6                  (0x6U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000006 */
21474 #define RCC_MCUDIVR_MCUDIV_7                  (0x7U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000007 */
21475 #define RCC_MCUDIVR_MCUDIV_8                  (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */
21476 #define RCC_MCUDIVR_MCUDIV_9                  (0x9U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000009 */
21477 /* @note  others: ck_mcuss divided by 512 */
21478 
21479 #define RCC_MCUDIVR_MCUDIVRDY_Pos             (31U)
21480 #define RCC_MCUDIVR_MCUDIVRDY_Msk             (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */
21481 #define RCC_MCUDIVR_MCUDIVRDY                 RCC_MCUDIVR_MCUDIVRDY_Msk        /*MCU clock prescaler status*/
21482 /********************  Bit definition for RCC_APB1DIVR register********************/
21483 #define RCC_APB1DIVR_APB1DIV_Pos              (0U)
21484 #define RCC_APB1DIVR_APB1DIV_Msk              (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */
21485 #define RCC_APB1DIVR_APB1DIV                  RCC_APB1DIVR_APB1DIV_Msk         /*APB1 clock prescaler*/
21486 #define RCC_APB1DIVR_APB1DIV_0                (0x0U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000000 */
21487 #define RCC_APB1DIVR_APB1DIV_1                (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */
21488 #define RCC_APB1DIVR_APB1DIV_2                (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */
21489 #define RCC_APB1DIVR_APB1DIV_3                (0x3U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000003 */
21490 #define RCC_APB1DIVR_APB1DIV_4                (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */
21491 /* @note others: ck_hclk/16 */
21492 
21493 #define RCC_APB1DIVR_APB1DIVRDY_Pos           (31U)
21494 #define RCC_APB1DIVR_APB1DIVRDY_Msk           (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */
21495 #define RCC_APB1DIVR_APB1DIVRDY               RCC_APB1DIVR_APB1DIVRDY_Msk      /*APB1 clock prescaler status*/
21496 
21497 /********************  Bit definition for RCC_APB2DIV register********************/
21498 #define RCC_APB2DIVR_APB2DIV_Pos              (0U)
21499 #define RCC_APB2DIVR_APB2DIV_Msk              (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */
21500 #define RCC_APB2DIVR_APB2DIV                  RCC_APB2DIVR_APB2DIV_Msk         /*APB2 clock prescaler*/
21501 #define RCC_APB2DIVR_APB2DIV_0                (0x0U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000000 */
21502 #define RCC_APB2DIVR_APB2DIV_1                (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */
21503 #define RCC_APB2DIVR_APB2DIV_2                (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */
21504 #define RCC_APB2DIVR_APB2DIV_3                (0x3U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000003 */
21505 #define RCC_APB2DIVR_APB2DIV_4                (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */
21506 /* @note others: ck_hclk/16 */
21507 
21508 #define RCC_APB2DIVR_APB2DIVRDY_Pos           (31U)
21509 #define RCC_APB2DIVR_APB2DIVRDY_Msk           (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */
21510 #define RCC_APB2DIVR_APB2DIVRDY               RCC_APB2DIVR_APB2DIVRDY_Msk      /*APB2 clock prescaler status*/
21511 
21512 /********************  Bit definition for RCC_APB3DIV register********************/
21513 #define RCC_APB3DIVR_APB3DIV_Pos              (0U)
21514 #define RCC_APB3DIVR_APB3DIV_Msk              (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */
21515 #define RCC_APB3DIVR_APB3DIV                  RCC_APB3DIVR_APB3DIV_Msk         /*APB3 clock prescaler*/
21516 #define RCC_APB3DIVR_APB3DIV_0                (0x0U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000000 */
21517 #define RCC_APB3DIVR_APB3DIV_1                (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */
21518 #define RCC_APB3DIVR_APB3DIV_2                (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */
21519 #define RCC_APB3DIVR_APB3DIV_3                (0x3U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000003 */
21520 #define RCC_APB3DIVR_APB3DIV_4                (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */
21521 /* @note others: ck_hclk/16 */
21522 
21523 #define RCC_APB3DIVR_APB3DIVRDY_Pos           (31U)
21524 #define RCC_APB3DIVR_APB3DIVRDY_Msk           (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */
21525 #define RCC_APB3DIVR_APB3DIVRDY               RCC_APB3DIVR_APB3DIVRDY_Msk      /*APB3 clock prescaler status*/
21526 
21527 /********************  Bit definition for RCC_PLL1CR register********************/
21528 #define RCC_PLL1CR_PLLON_Pos                  (0U)
21529 #define RCC_PLL1CR_PLLON_Msk                  (0x1U << RCC_PLL1CR_PLLON_Pos)   /*!< 0x00000001 */
21530 #define RCC_PLL1CR_PLLON                      RCC_PLL1CR_PLLON_Msk             /*PLL1 enable*/
21531 #define RCC_PLL1CR_PLL1RDY_Pos                (1U)
21532 #define RCC_PLL1CR_PLL1RDY_Msk                (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */
21533 #define RCC_PLL1CR_PLL1RDY                    RCC_PLL1CR_PLL1RDY_Msk           /*PLL1 clock ready flag*/
21534 #define RCC_PLL1CR_SSCG_CTRL_Pos              (2U)
21535 #define RCC_PLL1CR_SSCG_CTRL_Msk              (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */
21536 #define RCC_PLL1CR_SSCG_CTRL                  RCC_PLL1CR_SSCG_CTRL_Msk         /*Spread Spectrum Clock Generator of PLL1 enable*/
21537 #define RCC_PLL1CR_DIVPEN_Pos                 (4U)
21538 #define RCC_PLL1CR_DIVPEN_Msk                 (0x1U << RCC_PLL1CR_DIVPEN_Pos)  /*!< 0x00000010 */
21539 #define RCC_PLL1CR_DIVPEN                     RCC_PLL1CR_DIVPEN_Msk            /*PLL1 DIVP divider output enable*/
21540 #define RCC_PLL1CR_DIVQEN_Pos                 (5U)
21541 #define RCC_PLL1CR_DIVQEN_Msk                 (0x1U << RCC_PLL1CR_DIVQEN_Pos)  /*!< 0x00000020 */
21542 #define RCC_PLL1CR_DIVQEN                     RCC_PLL1CR_DIVQEN_Msk            /*PLL1 DIVQ divider output enable*/
21543 #define RCC_PLL1CR_DIVREN_Pos                 (6U)
21544 #define RCC_PLL1CR_DIVREN_Msk                 (0x1U << RCC_PLL1CR_DIVREN_Pos)  /*!< 0x00000040 */
21545 #define RCC_PLL1CR_DIVREN                     RCC_PLL1CR_DIVREN_Msk            /*PLL1 DIVR divider output enable*/
21546 
21547 /********************  Bit definition for RCC_PLL1CFGR1 register********************/
21548 #define RCC_PLL1CFGR1_DIVN_Pos                (0U)
21549 #define RCC_PLL1CFGR1_DIVN_Msk                (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */
21550 #define RCC_PLL1CFGR1_DIVN                    RCC_PLL1CFGR1_DIVN_Msk           /*Multiplication factor for PLL1 VCO*/
21551 /* @note Valid division rations for DIVN: between 25 and 100 */
21552 #define RCC_PLL1CFGR1_DIVN_25                 ((uint32_t)0x00000018)           /* Division ratio is 25 */
21553 #define RCC_PLL1CFGR1_DIVN_26                 ((uint32_t)0x00000019)           /* Division ratio is 26 */
21554 #define RCC_PLL1CFGR1_DIVN_100                ((uint32_t)0x00000063)           /* Division ratio is 100 */
21555 
21556 #define RCC_PLL1CFGR1_DIVM1_Pos               (16U)
21557 #define RCC_PLL1CFGR1_DIVM1_Msk               (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */
21558 #define RCC_PLL1CFGR1_DIVM1                   RCC_PLL1CFGR1_DIVM1_Msk          /*Prescaler for PLL1*/
21559 
21560 /* @note "y" division factor must be an integer value between 1 and 64 */
21561 #define  RCC_PLL1CFGR1_DIVM1_(y)             ((uint32_t)(0x003F0000) & ((y-1) << 4))
21562 
21563 /********************  Bit definition for RCC_PLL1CFGR2 register********************/
21564 /* @TODO To compleate as needed */
21565 #define RCC_PLL1CFGR2_DIVP_Pos                (0U)
21566 #define RCC_PLL1CFGR2_DIVP_Msk                (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */
21567 #define RCC_PLL1CFGR2_DIVP                    RCC_PLL1CFGR2_DIVP_Msk           /*PLL1 DIVP division factor*/
21568 #define RCC_PLL1CFGR2_DIVP_0                  (0x00U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000000 */
21569 #define RCC_PLL1CFGR2_DIVP_1                  (0x01U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */
21570 #define RCC_PLL1CFGR2_DIVP_128                (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */
21571 
21572 #define RCC_PLL1CFGR2_DIVQ_Pos                (8U)
21573 #define RCC_PLL1CFGR2_DIVQ_Msk                (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */
21574 #define RCC_PLL1CFGR2_DIVQ                    RCC_PLL1CFGR2_DIVQ_Msk           /*PLL1 DIVQ division factor*/
21575 #define RCC_PLL1CFGR2_DIVQ_0                  (0x00U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000000 */
21576 #define RCC_PLL1CFGR2_DIVQ_1                  (0x01U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */
21577 #define RCC_PLL1CFGR2_DIVQ_128                (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */
21578 
21579 #define RCC_PLL1CFGR2_DIVR_Pos                (16U)
21580 #define RCC_PLL1CFGR2_DIVR_Msk                (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */
21581 #define RCC_PLL1CFGR2_DIVR                    RCC_PLL1CFGR2_DIVR_Msk           /*PLL1 DIVR division factor*/
21582 #define RCC_PLL1CFGR2_DIVR_0                  (0x00U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00000000 */
21583 #define RCC_PLL1CFGR2_DIVR_1                  (0x01U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */
21584 #define RCC_PLL1CFGR2_DIVR_128                (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */
21585 
21586 /********************  Bit definition for RCC_PLL1FRACR register********************/
21587 #define RCC_PLL1FRACR_FRACV_Pos               (3U)
21588 #define RCC_PLL1FRACR_FRACV_Msk               (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */
21589 #define RCC_PLL1FRACR_FRACV                   RCC_PLL1FRACR_FRACV_Msk          /*Fractional part of the multiplication factor for PLL1 VCO*/
21590 /* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */
21591 
21592 #define RCC_PLL1FRACR_FRACLE_Pos              (16U)
21593 #define RCC_PLL1FRACR_FRACLE_Msk              (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */
21594 #define RCC_PLL1FRACR_FRACLE                  RCC_PLL1FRACR_FRACLE_Msk         /*PLL1 fractional latch enable*/
21595 
21596 /********************  Bit definition for RCC_PLL1CSGR register********************/
21597 #define RCC_PLL1CSGR_MOD_PER_Pos              (0U)
21598 #define RCC_PLL1CSGR_MOD_PER_Msk              (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */
21599 #define RCC_PLL1CSGR_MOD_PER                  RCC_PLL1CSGR_MOD_PER_Msk         /*Modulation Period Adjustment for PLL1*/
21600 #define RCC_PLL1CSGR_TPDFN_DIS_Pos            (13U)
21601 #define RCC_PLL1CSGR_TPDFN_DIS_Msk            (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */
21602 #define RCC_PLL1CSGR_TPDFN_DIS                RCC_PLL1CSGR_TPDFN_DIS_Msk       /*Dithering TPDF noise control*/
21603 #define RCC_PLL1CSGR_RPDFN_DIS_Pos            (14U)
21604 #define RCC_PLL1CSGR_RPDFN_DIS_Msk            (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */
21605 #define RCC_PLL1CSGR_RPDFN_DIS                RCC_PLL1CSGR_RPDFN_DIS_Msk       /*Dithering RPDF noise control*/
21606 #define RCC_PLL1CSGR_SSCG_MODE_Pos            (15U)
21607 #define RCC_PLL1CSGR_SSCG_MODE_Msk            (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */
21608 #define RCC_PLL1CSGR_SSCG_MODE                RCC_PLL1CSGR_SSCG_MODE_Msk       /*Spread spectrum clock generator mode*/
21609 #define RCC_PLL1CSGR_INC_STEP_Pos             (16U)
21610 #define RCC_PLL1CSGR_INC_STEP_Msk             (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */
21611 #define RCC_PLL1CSGR_INC_STEP                 RCC_PLL1CSGR_INC_STEP_Msk        /*Modulation Depth Adjustment for PLL1*/
21612 
21613 /********************  Bit definition for RCC_PLL2CR register********************/
21614 #define RCC_PLL2CR_PLLON_Pos                  (0U)
21615 #define RCC_PLL2CR_PLLON_Msk                  (0x1U << RCC_PLL2CR_PLLON_Pos)   /*!< 0x00000001 */
21616 #define RCC_PLL2CR_PLLON                      RCC_PLL2CR_PLLON_Msk             /*PLL2 enable*/
21617 #define RCC_PLL2CR_PLL2RDY_Pos                (1U)
21618 #define RCC_PLL2CR_PLL2RDY_Msk                (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */
21619 #define RCC_PLL2CR_PLL2RDY                    RCC_PLL2CR_PLL2RDY_Msk           /*PLL2 clock ready flag*/
21620 #define RCC_PLL2CR_SSCG_CTRL_Pos              (2U)
21621 #define RCC_PLL2CR_SSCG_CTRL_Msk              (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */
21622 #define RCC_PLL2CR_SSCG_CTRL                  RCC_PLL2CR_SSCG_CTRL_Msk         /*Spread Spectrum Clock Generator of PLL2 enable*/
21623 #define RCC_PLL2CR_DIVPEN_Pos                 (4U)
21624 #define RCC_PLL2CR_DIVPEN_Msk                 (0x1U << RCC_PLL2CR_DIVPEN_Pos)  /*!< 0x00000010 */
21625 #define RCC_PLL2CR_DIVPEN                     RCC_PLL2CR_DIVPEN_Msk            /*PLL2 DIVP divider output enable*/
21626 #define RCC_PLL2CR_DIVQEN_Pos                 (5U)
21627 #define RCC_PLL2CR_DIVQEN_Msk                 (0x1U << RCC_PLL2CR_DIVQEN_Pos)  /*!< 0x00000020 */
21628 #define RCC_PLL2CR_DIVQEN                     RCC_PLL2CR_DIVQEN_Msk            /*PLL2 DIVQ divider output enable*/
21629 #define RCC_PLL2CR_DIVREN_Pos                 (6U)
21630 #define RCC_PLL2CR_DIVREN_Msk                 (0x1U << RCC_PLL2CR_DIVREN_Pos)  /*!< 0x00000040 */
21631 #define RCC_PLL2CR_DIVREN                     RCC_PLL2CR_DIVREN_Msk            /*PLL2 DIVR divider output enable*/
21632 /********************  Bit definition for RCC_PLL2CFGR1 register********************/
21633 #define RCC_PLL2CFGR1_DIVN_Pos                (0U)
21634 #define RCC_PLL2CFGR1_DIVN_Msk                (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */
21635 #define RCC_PLL2CFGR1_DIVN                    RCC_PLL2CFGR1_DIVN_Msk           /*Multiplication factor for PLL2*/
21636 /* @note Valid division rations for DIVN: between 25 and 100 */
21637 #define RCC_PLL2CFGR1_DIVN_25                 ((uint32_t)0x00000018)           /* Division ratio is 25 */
21638 #define RCC_PLL2CFGR1_DIVN_26                 ((uint32_t)0x00000019)           /* Division ratio is 26 */
21639 #define RCC_PLL2CFGR1_DIVN_100                ((uint32_t)0x00000063)           /* Division ratio is 100 */
21640 
21641 #define  RCC_PLL2CFGR1_DIVM2_Pos              (16U)
21642 #define RCC_PLL2CFGR1_DIVM2_Pos               (16U)
21643 #define RCC_PLL2CFGR1_DIVM2_Msk               (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */
21644 #define RCC_PLL2CFGR1_DIVM2                   RCC_PLL2CFGR1_DIVM2_Msk          /*Prescaler for PLL2*/
21645 /* @note "y" division factor must be an integer value between 1 and 64 */
21646 #define  RCC_PLL2CFGR1_DIVM2_(y)              ((uint32_t)(0x003F0000) & ((y-1) << 4))
21647 
21648 /********************  Bit definition for RCC_PLL2CFGR2 register********************/
21649 /* @TODO To compleate as needed */
21650 #define RCC_PLL2CFGR2_DIVP_Pos                (0U)
21651 #define RCC_PLL2CFGR2_DIVP_Msk                (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */
21652 #define RCC_PLL2CFGR2_DIVP                    RCC_PLL2CFGR2_DIVP_Msk           /*PLL2 DIVP division factor*/
21653 #define RCC_PLL2CFGR2_DIVP_0                  (0x00U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000000 */
21654 #define RCC_PLL2CFGR2_DIVP_1                  (0x01U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */
21655 #define RCC_PLL2CFGR2_DIVP_128                (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */
21656 
21657 #define RCC_PLL2CFGR2_DIVQ_Pos                (8U)
21658 #define RCC_PLL2CFGR2_DIVQ_Msk                (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */
21659 #define RCC_PLL2CFGR2_DIVQ                    RCC_PLL2CFGR2_DIVQ_Msk           /*PLL2 DIVQ division factor*/
21660 #define RCC_PLL2CFGR2_DIVQ_0                  (0x00U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000000 */
21661 #define RCC_PLL2CFGR2_DIVQ_1                  (0x01U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */
21662 #define RCC_PLL2CFGR2_DIVQ_128                (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */
21663 
21664 #define RCC_PLL2CFGR2_DIVR_Pos                (16U)
21665 #define RCC_PLL2CFGR2_DIVR_Msk                (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */
21666 #define RCC_PLL2CFGR2_DIVR                    RCC_PLL2CFGR2_DIVR_Msk           /*PLL2 DIVR division factor*/
21667 #define RCC_PLL2CFGR2_DIVR_0                  (0x00U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00000000 */
21668 #define RCC_PLL2CFGR2_DIVR_1                  (0x01U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */
21669 #define RCC_PLL2CFGR2_DIVR_128                (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */
21670 
21671 /********************  Bit definition for RCC_PLL2FRACR register********************/
21672 #define RCC_PLL2FRACR_FRACV_Pos               (3U)
21673 #define RCC_PLL2FRACR_FRACV_Msk               (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */
21674 #define RCC_PLL2FRACR_FRACV                   RCC_PLL2FRACR_FRACV_Msk          /*Fractional part of the multiplication factor for PLL2 VCO*/
21675 /* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */
21676 
21677 #define RCC_PLL2FRACR_FRACLE_Pos              (16U)
21678 #define RCC_PLL2FRACR_FRACLE_Msk              (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */
21679 #define RCC_PLL2FRACR_FRACLE                  RCC_PLL2FRACR_FRACLE_Msk         /*PLL2 fractional latch enable*/
21680 
21681 /********************  Bit definition for RCC_PLL2CSGR register********************/
21682 #define RCC_PLL2CSGR_MOD_PER_Pos              (0U)
21683 #define RCC_PLL2CSGR_MOD_PER_Msk              (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */
21684 #define RCC_PLL2CSGR_MOD_PER                  RCC_PLL2CSGR_MOD_PER_Msk         /*Modulation Period Adjustment for PLL2*/
21685 #define RCC_PLL2CSGR_TPDFN_DIS_Pos            (13U)
21686 #define RCC_PLL2CSGR_TPDFN_DIS_Msk            (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */
21687 #define RCC_PLL2CSGR_TPDFN_DIS                RCC_PLL2CSGR_TPDFN_DIS_Msk       /*Dithering TPDF noise control*/
21688 #define RCC_PLL2CSGR_RPDFN_DIS_Pos            (14U)
21689 #define RCC_PLL2CSGR_RPDFN_DIS_Msk            (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */
21690 #define RCC_PLL2CSGR_RPDFN_DIS                RCC_PLL2CSGR_RPDFN_DIS_Msk       /*Dithering RPDF noise control*/
21691 #define RCC_PLL2CSGR_SSCG_MODE_Pos            (15U)
21692 #define RCC_PLL2CSGR_SSCG_MODE_Msk            (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */
21693 #define RCC_PLL2CSGR_SSCG_MODE                RCC_PLL2CSGR_SSCG_MODE_Msk       /*Spread spectrum clock generator mode*/
21694 #define RCC_PLL2CSGR_INC_STEP_Pos             (16U)
21695 #define RCC_PLL2CSGR_INC_STEP_Msk             (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */
21696 #define RCC_PLL2CSGR_INC_STEP                 RCC_PLL2CSGR_INC_STEP_Msk        /*Modulation Depth Adjustment for PLL2*/
21697 
21698 /********************  Bit definition for RCC_PLL3CR register********************/
21699 #define RCC_PLL3CR_PLLON_Pos                  (0U)
21700 #define RCC_PLL3CR_PLLON_Msk                  (0x1U << RCC_PLL3CR_PLLON_Pos)   /*!< 0x00000001 */
21701 #define RCC_PLL3CR_PLLON                      RCC_PLL3CR_PLLON_Msk             /*PLL3 enable*/
21702 #define RCC_PLL3CR_PLL3RDY_Pos                (1U)
21703 #define RCC_PLL3CR_PLL3RDY_Msk                (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */
21704 #define RCC_PLL3CR_PLL3RDY                    RCC_PLL3CR_PLL3RDY_Msk           /*PLL3 clock ready flag*/
21705 #define RCC_PLL3CR_SSCG_CTRL_Pos              (2U)
21706 #define RCC_PLL3CR_SSCG_CTRL_Msk              (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */
21707 #define RCC_PLL3CR_SSCG_CTRL                  RCC_PLL3CR_SSCG_CTRL_Msk         /*Spread Spectrum Clock Generator of PLL3 enable*/
21708 #define RCC_PLL3CR_DIVPEN_Pos                 (4U)
21709 #define RCC_PLL3CR_DIVPEN_Msk                 (0x1U << RCC_PLL3CR_DIVPEN_Pos)  /*!< 0x00000010 */
21710 #define RCC_PLL3CR_DIVPEN                     RCC_PLL3CR_DIVPEN_Msk            /*PLL3 DIVP divider output enable*/
21711 #define RCC_PLL3CR_DIVQEN_Pos                 (5U)
21712 #define RCC_PLL3CR_DIVQEN_Msk                 (0x1U << RCC_PLL3CR_DIVQEN_Pos)  /*!< 0x00000020 */
21713 #define RCC_PLL3CR_DIVQEN                     RCC_PLL3CR_DIVQEN_Msk            /*PLL3 DIVQ divider output enable*/
21714 #define RCC_PLL3CR_DIVREN_Pos                 (6U)
21715 #define RCC_PLL3CR_DIVREN_Msk                 (0x1U << RCC_PLL3CR_DIVREN_Pos)  /*!< 0x00000040 */
21716 #define RCC_PLL3CR_DIVREN                     RCC_PLL3CR_DIVREN_Msk            /*PLL3 DIVR divider output enable*/
21717 
21718 /********************  Bit definition for RCC_PLL3CFGR1 register********************/
21719 #define RCC_PLL3CFGR1_DIVN_Pos                (0U)
21720 #define RCC_PLL3CFGR1_DIVN_Msk                (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */
21721 #define RCC_PLL3CFGR1_DIVN                    RCC_PLL3CFGR1_DIVN_Msk           /*Multiplication factor for PLL3*/
21722 /* @note Valid division rations for DIVN: between 25 and 200 */
21723 #define RCC_PLL3CFGR1_DIVN_25                 ((uint32_t)0x00000018)           /* Division ratio is 25 */
21724 #define RCC_PLL3CFGR1_DIVN_26                 ((uint32_t)0x00000019)           /* Division ratio is 26 */
21725 #define RCC_PLL3CFGR1_DIVN_200                ((uint32_t)0x000000C7)           /* Division ratio is 200 */
21726 
21727 
21728 #define  RCC_PLL3CFGR1_DIVM3_Pos              (16U)
21729 #define RCC_PLL3CFGR1_DIVM3_Pos               (16U)
21730 #define RCC_PLL3CFGR1_DIVM3_Msk               (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */
21731 #define RCC_PLL3CFGR1_DIVM3                   RCC_PLL3CFGR1_DIVM3_Msk          /*Prescaler for PLL3*/
21732 /* @note "y" division factor must be an integer value between 1 and 64 */
21733 #define  RCC_PLL3CFGR1_DIVM3_(y)              ((uint32_t)(0x003F0000) & ((y-1) << 4))
21734 
21735 #define RCC_PLL3CFGR1_IFRGE_Pos               (24U)
21736 #define RCC_PLL3CFGR1_IFRGE_Msk               (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */
21737 #define RCC_PLL3CFGR1_IFRGE                   RCC_PLL3CFGR1_IFRGE_Msk          /*PLL3 input frequency range*/
21738 #define RCC_PLL3CFGR1_IFRGE_0                 (0x0U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x00000000 */
21739                                                                                /* between 4 and 8 MHz (default after reset) */
21740 #define RCC_PLL3CFGR1_IFRGE_1                 ((uint32_t)0x01000000)           /*The PLL3 input (ck_ref3) clock range frequency is
21741                                                                                 between 8 and 16 MHz */
21742 /* @note other IFRGE values are reserved */
21743 
21744 /********************  Bit definition for RCC_PLL3CFGR2 register********************/
21745 /* @TODO To compleate as needed */
21746 #define RCC_PLL3CFGR2_DIVP_Pos                (0U)
21747 #define RCC_PLL3CFGR2_DIVP_Msk                (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */
21748 #define RCC_PLL3CFGR2_DIVP                    RCC_PLL3CFGR2_DIVP_Msk           /*PLL3 DIVP division factor*/
21749 #define RCC_PLL3CFGR2_DIVP_0                  (0x00U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000000 */
21750 #define RCC_PLL3CFGR2_DIVP_1                  (0x01U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */
21751 #define RCC_PLL3CFGR2_DIVP_128                (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */
21752 
21753 #define RCC_PLL3CFGR2_DIVQ_Pos                (8U)
21754 #define RCC_PLL3CFGR2_DIVQ_Msk                (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */
21755 #define RCC_PLL3CFGR2_DIVQ                    RCC_PLL3CFGR2_DIVQ_Msk           /*PLL3 DIVQ division factor*/
21756 #define RCC_PLL3CFGR2_DIVQ_0                  (0x00U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000000 */
21757 #define RCC_PLL3CFGR2_DIVQ_1                  (0x01U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */
21758 #define RCC_PLL3CFGR2_DIVQ_128                (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */
21759 
21760 #define RCC_PLL3CFGR2_DIVR_Pos                (16U)
21761 #define RCC_PLL3CFGR2_DIVR_Msk                (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */
21762 #define RCC_PLL3CFGR2_DIVR                    RCC_PLL3CFGR2_DIVR_Msk           /*PLL3 DIVR division factor*/
21763 #define RCC_PLL3CFGR2_DIVR_0                  (0x00U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00000000 */
21764 #define RCC_PLL3CFGR2_DIVR_1                  (0x01U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */
21765 #define RCC_PLL3CFGR2_DIVR_128                (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */
21766 
21767 /********************  Bit definition for RCC_PLL3FRACR register********************/
21768 #define RCC_PLL3FRACR_FRACV_Pos               (3U)
21769 #define RCC_PLL3FRACR_FRACV_Msk               (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */
21770 #define RCC_PLL3FRACR_FRACV                   RCC_PLL3FRACR_FRACV_Msk          /*Fractional part of the multiplication factor for PLL3 VCO*/
21771 /* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */
21772 
21773 #define RCC_PLL3FRACR_FRACLE_Pos              (16U)
21774 #define RCC_PLL3FRACR_FRACLE_Msk              (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */
21775 #define RCC_PLL3FRACR_FRACLE                  RCC_PLL3FRACR_FRACLE_Msk         /*PLL3 fractional latch enable*/
21776 
21777 /********************  Bit definition for RCC_PLL3CSGR register********************/
21778 #define RCC_PLL3CSGR_MOD_PER_Pos              (0U)
21779 #define RCC_PLL3CSGR_MOD_PER_Msk              (0x1FFFU << RCC_PLL3CSGR_MOD_PER_Pos) /*!< 0x00001FFF */
21780 #define RCC_PLL3CSGR_MOD_PER                  RCC_PLL3CSGR_MOD_PER_Msk         /*Modulation Period Adjustment for PLL3*/
21781 #define RCC_PLL3CSGR_TPDFN_DIS_Pos            (13U)
21782 #define RCC_PLL3CSGR_TPDFN_DIS_Msk            (0x1U << RCC_PLL3CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */
21783 #define RCC_PLL3CSGR_TPDFN_DIS                RCC_PLL3CSGR_TPDFN_DIS_Msk       /*Dithering TPDF noise control*/
21784 #define RCC_PLL3CSGR_RPDFN_DIS_Pos            (14U)
21785 #define RCC_PLL3CSGR_RPDFN_DIS_Msk            (0x1U << RCC_PLL3CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */
21786 #define RCC_PLL3CSGR_RPDFN_DIS                RCC_PLL3CSGR_RPDFN_DIS_Msk       /*Dithering RPDF noise control*/
21787 #define RCC_PLL3CSGR_SSCG_MODE_Pos            (15U)
21788 #define RCC_PLL3CSGR_SSCG_MODE_Msk            (0x1U << RCC_PLL3CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */
21789 #define RCC_PLL3CSGR_SSCG_MODE                RCC_PLL3CSGR_SSCG_MODE_Msk       /*Spread spectrum clock generator mode*/
21790 #define RCC_PLL3CSGR_INC_STEP_Pos             (16U)
21791 #define RCC_PLL3CSGR_INC_STEP_Msk             (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */
21792 #define RCC_PLL3CSGR_INC_STEP                 RCC_PLL3CSGR_INC_STEP_Msk        /*Modulation Depth Adjustment for PLL3*/
21793 
21794 /********************  Bit definition for RCC_PLL4CR register********************/
21795 #define RCC_PLL4CR_PLLON_Pos                  (0U)
21796 #define RCC_PLL4CR_PLLON_Msk                  (0x1U << RCC_PLL4CR_PLLON_Pos)   /*!< 0x00000001 */
21797 #define RCC_PLL4CR_PLLON                      RCC_PLL4CR_PLLON_Msk             /*PLL4 enable*/
21798 #define RCC_PLL4CR_PLL4RDY_Pos                (1U)
21799 #define RCC_PLL4CR_PLL4RDY_Msk                (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */
21800 #define RCC_PLL4CR_PLL4RDY                    RCC_PLL4CR_PLL4RDY_Msk           /*PLL4 clock ready flag*/
21801 #define RCC_PLL4CR_SSCG_CTRL_Pos              (2U)
21802 #define RCC_PLL4CR_SSCG_CTRL_Msk              (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */
21803 #define RCC_PLL4CR_SSCG_CTRL                  RCC_PLL4CR_SSCG_CTRL_Msk         /*Spread Spectrum Clock Generator of PLL4 enable*/
21804 #define RCC_PLL4CR_DIVPEN_Pos                 (4U)
21805 #define RCC_PLL4CR_DIVPEN_Msk                 (0x1U << RCC_PLL4CR_DIVPEN_Pos)  /*!< 0x00000010 */
21806 #define RCC_PLL4CR_DIVPEN                     RCC_PLL4CR_DIVPEN_Msk            /*PLL4 DIVP divider output enable*/
21807 #define RCC_PLL4CR_DIVQEN_Pos                 (5U)
21808 #define RCC_PLL4CR_DIVQEN_Msk                 (0x1U << RCC_PLL4CR_DIVQEN_Pos)  /*!< 0x00000020 */
21809 #define RCC_PLL4CR_DIVQEN                     RCC_PLL4CR_DIVQEN_Msk            /*PLL4 DIVQ divider output enable*/
21810 #define RCC_PLL4CR_DIVREN_Pos                 (6U)
21811 #define RCC_PLL4CR_DIVREN_Msk                 (0x1U << RCC_PLL4CR_DIVREN_Pos)  /*!< 0x00000040 */
21812 #define RCC_PLL4CR_DIVREN                     RCC_PLL4CR_DIVREN_Msk            /*PLL4 DIVR divider output enable*/
21813 
21814 /********************  Bit definition for RCC_PLL4CFGR1 register********************/
21815 #define RCC_PLL4CFGR1_DIVN_Pos                (0U)
21816 #define RCC_PLL4CFGR1_DIVN_Msk                (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */
21817 #define RCC_PLL4CFGR1_DIVN                    RCC_PLL4CFGR1_DIVN_Msk           /*Multiplication factor for PLL4*/
21818 /* @note Valid division rations for DIVN: between 25 and 200 */
21819 #define RCC_PLL4CFGR1_DIVN_25                 ((uint32_t)0x00000018)           /* Division ratio is 25 */
21820 #define RCC_PLL4CFGR1_DIVN_26                 ((uint32_t)0x00000019)           /* Division ratio is 26 */
21821 #define RCC_PLL4CFGR1_DIVN_200                ((uint32_t)0x000000C7)           /* Division ratio is 200 */
21822 
21823 #define  RCC_PLL4CFGR1_DIVM4_Pos              (16U)
21824 #define RCC_PLL4CFGR1_DIVM4_Pos               (16U)
21825 #define RCC_PLL4CFGR1_DIVM4_Msk               (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */
21826 #define RCC_PLL4CFGR1_DIVM4                   RCC_PLL4CFGR1_DIVM4_Msk          /*Prescaler for PLL4*/
21827 /* @note "y" division factor must be an integer value between 1 and 64 */
21828 #define  RCC_PLL4CFGR1_DIVM4_(y)              ((uint32_t)(0x003F0000) & ((y-1) << 4))
21829 
21830 #define RCC_PLL4CFGR1_IFRGE_Pos               (24U)
21831 #define RCC_PLL4CFGR1_IFRGE_Msk               (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */
21832 #define RCC_PLL4CFGR1_IFRGE                   RCC_PLL4CFGR1_IFRGE_Msk          /*PLL4 input frequency range*/
21833 #define RCC_PLL4CFGR1_IFRGE_0                 (0x0U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x00000000 */
21834                                                                                /*between 4 and 8 MHz (default after reset) */
21835 #define RCC_PLL4CFGR1_IFRGE_1                 ((uint32_t)0x01000000)           /*The PLL4 input (ck_ref4) clock range frequency is
21836                                                                                between 8 and 16 MHz */
21837 /* @note other IFRGE values are reserved */
21838 
21839 /********************  Bit definition for RCC_PLL4CFGR2 register********************/
21840 /* @TODO To compleate as needed */
21841 #define RCC_PLL4CFGR2_DIVP_Pos                (0U)
21842 #define RCC_PLL4CFGR2_DIVP_Msk                (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */
21843 #define RCC_PLL4CFGR2_DIVP                    RCC_PLL4CFGR2_DIVP_Msk           /*PLL4 DIVP division factor*/
21844 #define RCC_PLL4CFGR2_DIVP_0                  (0x00U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000000 */
21845 #define RCC_PLL4CFGR2_DIVP_1                  (0x01U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */
21846 #define RCC_PLL4CFGR2_DIVP_128                (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */
21847 
21848 #define RCC_PLL4CFGR2_DIVQ_Pos                (8U)
21849 #define RCC_PLL4CFGR2_DIVQ_Msk                (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */
21850 #define RCC_PLL4CFGR2_DIVQ                    RCC_PLL4CFGR2_DIVQ_Msk           /*PLL4 DIVQ division factor*/
21851 #define RCC_PLL4CFGR2_DIVQ_0                  (0x00U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000000 */
21852 #define RCC_PLL4CFGR2_DIVQ_1                  (0x01U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */
21853 #define RCC_PLL4CFGR2_DIVQ_128                (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */
21854 
21855 #define RCC_PLL4CFGR2_DIVR_Pos                (16U)
21856 #define RCC_PLL4CFGR2_DIVR_Msk                (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */
21857 #define RCC_PLL4CFGR2_DIVR                    RCC_PLL4CFGR2_DIVR_Msk           /*PLL4 DIVR division factor*/
21858 #define RCC_PLL4CFGR2_DIVR_0                  (0x00U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00000000 */
21859 #define RCC_PLL4CFGR2_DIVR_1                  (0x01U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */
21860 #define RCC_PLL4CFGR2_DIVR_128                (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */
21861 
21862 /********************  Bit definition for RCC_PLL4FRACR register********************/
21863 #define RCC_PLL4FRACR_FRACV_Pos               (3U)
21864 #define RCC_PLL4FRACR_FRACV_Msk               (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */
21865 #define RCC_PLL4FRACR_FRACV                   RCC_PLL4FRACR_FRACV_Msk          /*Fractional part of the multiplication factor for PLL4 VCO*/
21866 /* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */
21867 
21868 #define RCC_PLL4FRACR_FRACLE_Pos              (16U)
21869 #define RCC_PLL4FRACR_FRACLE_Msk              (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */
21870 #define RCC_PLL4FRACR_FRACLE                  RCC_PLL4FRACR_FRACLE_Msk         /*PLL4 fractional latch enable*/
21871 
21872 /********************  Bit definition for RCC_PLL4CSGR register********************/
21873 #define RCC_PLL4CSGR_MOD_PER_Pos              (0U)
21874 #define RCC_PLL4CSGR_MOD_PER_Msk              (0x1FFFU << RCC_PLL4CSGR_MOD_PER_Pos) /*!< 0x00001FFF */
21875 #define RCC_PLL4CSGR_MOD_PER                  RCC_PLL4CSGR_MOD_PER_Msk         /*Modulation Period Adjustment for PLL4*/
21876 #define RCC_PLL4CSGR_TPDFN_DIS_Pos            (13U)
21877 #define RCC_PLL4CSGR_TPDFN_DIS_Msk            (0x1U << RCC_PLL4CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */
21878 #define RCC_PLL4CSGR_TPDFN_DIS                RCC_PLL4CSGR_TPDFN_DIS_Msk       /*Dithering TPDF noise control*/
21879 #define RCC_PLL4CSGR_RPDFN_DIS_Pos            (14U)
21880 #define RCC_PLL4CSGR_RPDFN_DIS_Msk            (0x1U << RCC_PLL4CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */
21881 #define RCC_PLL4CSGR_RPDFN_DIS                RCC_PLL4CSGR_RPDFN_DIS_Msk       /*Dithering RPDF noise control*/
21882 #define RCC_PLL4CSGR_SSCG_MODE_Pos            (15U)
21883 #define RCC_PLL4CSGR_SSCG_MODE_Msk            (0x1U << RCC_PLL4CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */
21884 #define RCC_PLL4CSGR_SSCG_MODE                RCC_PLL4CSGR_SSCG_MODE_Msk       /*Spread spectrum clock generator mode*/
21885 #define RCC_PLL4CSGR_INC_STEP_Pos             (16U)
21886 #define RCC_PLL4CSGR_INC_STEP_Msk             (0x7FFFU << RCC_PLL4CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */
21887 #define RCC_PLL4CSGR_INC_STEP                 RCC_PLL4CSGR_INC_STEP_Msk        /*Modulation Depth Adjustment for PLL4*/
21888 
21889 /********************  Bit definition for RCC_I2C12CKSELR register********************/
21890 #define RCC_I2C12CKSELR_I2C12SRC_Pos          (0U)
21891 #define RCC_I2C12CKSELR_I2C12SRC_Msk          (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */
21892 #define RCC_I2C12CKSELR_I2C12SRC              RCC_I2C12CKSELR_I2C12SRC_Msk     /*I2C1 and I2C2 kernel clock source selection*/
21893 #define RCC_I2C12CKSELR_I2C12SRC_0            (0x0U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000000 */
21894 #define RCC_I2C12CKSELR_I2C12SRC_1            (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */
21895 #define RCC_I2C12CKSELR_I2C12SRC_2            (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */
21896 #define RCC_I2C12CKSELR_I2C12SRC_3            (0x3U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000003 */
21897 
21898 /********************  Bit definition for RCC_I2C35CKSELR register********************/
21899 #define RCC_I2C35CKSELR_I2C35SRC_Pos          (0U)
21900 #define RCC_I2C35CKSELR_I2C35SRC_Msk          (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */
21901 #define RCC_I2C35CKSELR_I2C35SRC              RCC_I2C35CKSELR_I2C35SRC_Msk     /*I2C3 and I2C5 kernel clock source selection*/
21902 #define RCC_I2C35CKSELR_I2C35SRC_0            (0x0U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000000 */
21903 #define RCC_I2C35CKSELR_I2C35SRC_1            (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */
21904 #define RCC_I2C35CKSELR_I2C35SRC_2            (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */
21905 #define RCC_I2C35CKSELR_I2C35SRC_3            (0x3U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000003 */
21906 
21907 /********************  Bit definition for RCC_I2C46CKSELR register********************/
21908 #define RCC_I2C46CKSELR_I2C46SRC_Pos          (0U)
21909 #define RCC_I2C46CKSELR_I2C46SRC_Msk          (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */
21910 #define RCC_I2C46CKSELR_I2C46SRC              RCC_I2C46CKSELR_I2C46SRC_Msk      /*I2C4 kernel clock source selection*/
21911 #define RCC_I2C46CKSELR_I2C46SRC_0            (0x0U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000000 */
21912 #define RCC_I2C46CKSELR_I2C46SRC_1            (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */
21913 #define RCC_I2C46CKSELR_I2C46SRC_2            (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */
21914 #define RCC_I2C46CKSELR_I2C46SRC_3            (0x3U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000003 */
21915 
21916 /********************  Bit definition for RCC_SAI1CKSELR register********************/
21917 #define RCC_SAI1CKSELR_SAI1SRC_Pos            (0U)
21918 #define RCC_SAI1CKSELR_SAI1SRC_Msk            (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */
21919 #define RCC_SAI1CKSELR_SAI1SRC                RCC_SAI1CKSELR_SAI1SRC_Msk       /*SAI1 kernel clock source selection*/
21920 #define RCC_SAI1CKSELR_SAI1SRC_0              (0x0U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000000 */
21921 #define RCC_SAI1CKSELR_SAI1SRC_1              (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */
21922 #define RCC_SAI1CKSELR_SAI1SRC_2              (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */
21923 #define RCC_SAI1CKSELR_SAI1SRC_3              (0x3U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000003 */
21924 #define RCC_SAI1CKSELR_SAI1SRC_4              (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */
21925 
21926 /********************  Bit definition for RCC_SAI2CKSELR register********************/
21927 #define RCC_SAI2CKSELR_SAI2SRC_Pos            (0U)
21928 #define RCC_SAI2CKSELR_SAI2SRC_Msk            (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */
21929 #define RCC_SAI2CKSELR_SAI2SRC                RCC_SAI2CKSELR_SAI2SRC_Msk       /*SAI2 kernel clock source selection*/
21930 #define RCC_SAI2CKSELR_SAI2SRC_0              (0x0U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000000 */
21931 #define RCC_SAI2CKSELR_SAI2SRC_1              (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */
21932 #define RCC_SAI2CKSELR_SAI2SRC_2              (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */
21933 #define RCC_SAI2CKSELR_SAI2SRC_3              (0x3U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000003 */
21934 #define RCC_SAI2CKSELR_SAI2SRC_4              (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */
21935 #define RCC_SAI2CKSELR_SAI2SRC_5              (0x5U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000005 */
21936 
21937 /********************  Bit definition for RCC_SAI3CKSELR register********************/
21938 #define RCC_SAI3CKSELR_SAI3SRC_Pos            (0U)
21939 #define RCC_SAI3CKSELR_SAI3SRC_Msk            (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */
21940 #define RCC_SAI3CKSELR_SAI3SRC                RCC_SAI3CKSELR_SAI3SRC_Msk       /*SAI3 kernel clock source selection*/
21941 #define RCC_SAI3CKSELR_SAI3SRC_0              (0x0U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000000 */
21942 #define RCC_SAI3CKSELR_SAI3SRC_1              (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */
21943 #define RCC_SAI3CKSELR_SAI3SRC_2              (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */
21944 #define RCC_SAI3CKSELR_SAI3SRC_3              (0x3U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000003 */
21945 #define RCC_SAI3CKSELR_SAI3SRC_4              (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */
21946 
21947 /********************  Bit definition for RCC_SAI4CKSELR register********************/
21948 #define RCC_SAI4CKSELR_SAI4SRC_Pos            (0U)
21949 #define RCC_SAI4CKSELR_SAI4SRC_Msk            (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */
21950 #define RCC_SAI4CKSELR_SAI4SRC                RCC_SAI4CKSELR_SAI4SRC_Msk       /*SAI4 kernel clock source selection*/
21951 #define RCC_SAI4CKSELR_SAI4SRC_0              (0x0U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000000 */
21952 #define RCC_SAI4CKSELR_SAI4SRC_1              (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */
21953 #define RCC_SAI4CKSELR_SAI4SRC_2              (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */
21954 #define RCC_SAI4CKSELR_SAI4SRC_3              (0x3U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000003 */
21955 #define RCC_SAI4CKSELR_SAI4SRC_4              (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */
21956 
21957 /********************  Bit definition for RCC_SPI2S1CKSELR register********************/
21958 #define RCC_SPI2S1CKSELR_SPI1SRC_Pos          (0U)
21959 #define RCC_SPI2S1CKSELR_SPI1SRC_Msk          (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */
21960 #define RCC_SPI2S1CKSELR_SPI1SRC              RCC_SPI2S1CKSELR_SPI1SRC_Msk     /*SPI/I2S1 kernel clock source selection*/
21961 #define RCC_SPI2S1CKSELR_SPI1SRC_0            (0x0U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000000 */
21962 #define RCC_SPI2S1CKSELR_SPI1SRC_1            (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */
21963 #define RCC_SPI2S1CKSELR_SPI1SRC_2            (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */
21964 #define RCC_SPI2S1CKSELR_SPI1SRC_3            (0x3U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000003 */
21965 #define RCC_SPI2S1CKSELR_SPI1SRC_4            (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */
21966 
21967 /********************  Bit definition for RCC_SPI2S23CKSELR register********************/
21968 #define RCC_SPI2S23CKSELR_SPI23SRC_Pos        (0U)
21969 #define RCC_SPI2S23CKSELR_SPI23SRC_Msk        (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */
21970 #define RCC_SPI2S23CKSELR_SPI23SRC            RCC_SPI2S23CKSELR_SPI23SRC_Msk   /*SPI/I2S2,3 kernel clock source selection*/
21971 #define RCC_SPI2S23CKSELR_SPI23SRC_0          (0x0U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000000 */
21972 #define RCC_SPI2S23CKSELR_SPI23SRC_1          (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */
21973 #define RCC_SPI2S23CKSELR_SPI23SRC_2          (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */
21974 #define RCC_SPI2S23CKSELR_SPI23SRC_3          (0x3U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000003 */
21975 #define RCC_SPI2S23CKSELR_SPI23SRC_4          (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */
21976 
21977 /********************  Bit definition for RCC_SPI45CKSELR register********************/
21978 #define RCC_SPI45CKSELR_SPI45SRC_Pos          (0U)
21979 #define RCC_SPI45CKSELR_SPI45SRC_Msk          (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */
21980 #define RCC_SPI45CKSELR_SPI45SRC              RCC_SPI45CKSELR_SPI45SRC_Msk     /*SPI4,5 kernel clock source selection*/
21981 #define RCC_SPI45CKSELR_SPI45SRC_0            (0x0U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000000 */
21982 #define RCC_SPI45CKSELR_SPI45SRC_1            (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */
21983 #define RCC_SPI45CKSELR_SPI45SRC_2            (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */
21984 #define RCC_SPI45CKSELR_SPI45SRC_3            (0x3U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000003 */
21985 #define RCC_SPI45CKSELR_SPI45SRC_4            (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */
21986 
21987 /********************  Bit definition for RCC_SPI6CKSELR register********************/
21988 #define RCC_SPI6CKSELR_SPI6SRC_Pos            (0U)
21989 #define RCC_SPI6CKSELR_SPI6SRC_Msk            (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */
21990 #define RCC_SPI6CKSELR_SPI6SRC                RCC_SPI6CKSELR_SPI6SRC_Msk       /*SPI6 kernel clock source selection*/
21991 #define RCC_SPI6CKSELR_SPI6SRC_0              (0x0U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000000 */
21992 #define RCC_SPI6CKSELR_SPI6SRC_1              (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */
21993 #define RCC_SPI6CKSELR_SPI6SRC_2              (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */
21994 #define RCC_SPI6CKSELR_SPI6SRC_3              (0x3U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000003 */
21995 #define RCC_SPI6CKSELR_SPI6SRC_4              (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */
21996 #define RCC_SPI6CKSELR_SPI6SRC_5              (0x5U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000005 */
21997 
21998 /********************  Bit definition for RCC_UART6CKSELR register********************/
21999 #define RCC_UART6CKSELR_UART6SRC_Pos          (0U)
22000 #define RCC_UART6CKSELR_UART6SRC_Msk          (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */
22001 #define RCC_UART6CKSELR_UART6SRC              RCC_UART6CKSELR_UART6SRC_Msk     /*UART6 kernel clock source selection*/
22002 #define RCC_UART6CKSELR_UART6SRC_0            (0x0U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000000 */
22003 #define RCC_UART6CKSELR_UART6SRC_1            (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */
22004 #define RCC_UART6CKSELR_UART6SRC_2            (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */
22005 #define RCC_UART6CKSELR_UART6SRC_3            (0x3U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000003 */
22006 #define RCC_UART6CKSELR_UART6SRC_4            (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */
22007 
22008 /********************  Bit definition for RCC_UART24CKSELR register********************/
22009 #define RCC_UART24CKSELR_UART24SRC_Pos        (0U)
22010 #define RCC_UART24CKSELR_UART24SRC_Msk        (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */
22011 #define RCC_UART24CKSELR_UART24SRC            RCC_UART24CKSELR_UART24SRC_Msk   /*UART2,4 kernel clock source selection*/
22012 #define RCC_UART24CKSELR_UART24SRC_0          (0x0U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000000 */
22013 #define RCC_UART24CKSELR_UART24SRC_1          (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */
22014 #define RCC_UART24CKSELR_UART24SRC_2          (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */
22015 #define RCC_UART24CKSELR_UART24SRC_3          (0x3U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000003 */
22016 #define RCC_UART24CKSELR_UART24SRC_4          (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */
22017 
22018 /********************  Bit definition for RCC_UART35CKSELR register********************/
22019 #define RCC_UART35CKSELR_UART35SRC_Pos        (0U)
22020 #define RCC_UART35CKSELR_UART35SRC_Msk        (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */
22021 #define RCC_UART35CKSELR_UART35SRC            RCC_UART35CKSELR_UART35SRC_Msk   /*UART3,5 kernel clock source selection*/
22022 #define RCC_UART35CKSELR_UART35SRC_0          (0x0U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000000 */
22023 #define RCC_UART35CKSELR_UART35SRC_1          (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */
22024 #define RCC_UART35CKSELR_UART35SRC_2          (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */
22025 #define RCC_UART35CKSELR_UART35SRC_3          (0x3U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000003 */
22026 #define RCC_UART35CKSELR_UART35SRC_4          (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */
22027 
22028 /********************  Bit definition for RCC_UART78CKSELR register********************/
22029 #define RCC_UART78CKSELR_UART78SRC_Pos        (0U)
22030 #define RCC_UART78CKSELR_UART78SRC_Msk        (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */
22031 #define RCC_UART78CKSELR_UART78SRC            RCC_UART78CKSELR_UART78SRC_Msk   /*UART7,8 kernel clock source selection*/
22032 #define RCC_UART78CKSELR_UART78SRC_0          (0x0U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000000 */
22033 #define RCC_UART78CKSELR_UART78SRC_1          (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */
22034 #define RCC_UART78CKSELR_UART78SRC_2          (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */
22035 #define RCC_UART78CKSELR_UART78SRC_3          (0x3U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000003 */
22036 #define RCC_UART78CKSELR_UART78SRC_4          (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */
22037 
22038 /********************  Bit definition for RCC_UART1CKSELR register********************/
22039 #define RCC_UART1CKSELR_UART1SRC_Pos          (0U)
22040 #define RCC_UART1CKSELR_UART1SRC_Msk          (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */
22041 #define RCC_UART1CKSELR_UART1SRC              RCC_UART1CKSELR_UART1SRC_Msk     /*UART1 kernel clock source selection*/
22042 #define RCC_UART1CKSELR_UART1SRC_0            (0x0U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000000 */
22043 #define RCC_UART1CKSELR_UART1SRC_1            (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */
22044 #define RCC_UART1CKSELR_UART1SRC_2            (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */
22045 #define RCC_UART1CKSELR_UART1SRC_3            (0x3U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000003 */
22046 #define RCC_UART1CKSELR_UART1SRC_4            (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */
22047 #define RCC_UART1CKSELR_UART1SRC_5            (0x5U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000005 */
22048 
22049 /********************  Bit definition for RCC_SDMMC12CKSELR register********************/
22050 #define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos      (0U)
22051 #define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk      (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */
22052 #define RCC_SDMMC12CKSELR_SDMMC12SRC          RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*SDMMC1 and SDMMC2 kernel clock source selection*/
22053 #define RCC_SDMMC12CKSELR_SDMMC12SRC_0        (0x0U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000000 */
22054 #define RCC_SDMMC12CKSELR_SDMMC12SRC_1        (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */
22055 #define RCC_SDMMC12CKSELR_SDMMC12SRC_2        (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */
22056 #define RCC_SDMMC12CKSELR_SDMMC12SRC_3        (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */
22057 
22058 /********************  Bit definition for RCC_SDMMC3CKSELR register********************/
22059 #define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos        (0U)
22060 #define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk        (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */
22061 #define RCC_SDMMC3CKSELR_SDMMC3SRC            RCC_SDMMC3CKSELR_SDMMC3SRC_Msk   /*SDMMC3 kernel clock source selection*/
22062 #define RCC_SDMMC3CKSELR_SDMMC3SRC_0          (0x0U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000000 */
22063 #define RCC_SDMMC3CKSELR_SDMMC3SRC_1          (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */
22064 #define RCC_SDMMC3CKSELR_SDMMC3SRC_2          (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */
22065 #define RCC_SDMMC3CKSELR_SDMMC3SRC_3          (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */
22066 
22067 /********************  Bit definition for RCC_ETHCKSELR register********************/
22068 #define RCC_ETHCKSELR_ETHSRC_Pos              (0U)
22069 #define RCC_ETHCKSELR_ETHSRC_Msk              (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */
22070 #define RCC_ETHCKSELR_ETHSRC                  RCC_ETHCKSELR_ETHSRC_Msk         /*ETH kernel clock source selection*/
22071 #define RCC_ETHCKSELR_ETHSRC_0                (0x0U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000000 */
22072 #define RCC_ETHCKSELR_ETHSRC_1                (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */
22073 #define RCC_ETHCKSELR_ETHSRC_2                (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */
22074 
22075 #define RCC_ETHCKSELR_ETHPTPDIV_Pos           (4U)
22076 #define RCC_ETHCKSELR_ETHPTPDIV_Msk           (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */
22077 #define RCC_ETHCKSELR_ETHPTPDIV               RCC_ETHCKSELR_ETHPTPDIV_Msk      /*Clock divider for Ethernet Precision Time Protocol (PTP)*/
22078 #define RCC_ETHCKSELR_ETHPTPDIV_0             (0x0U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000000 */
22079 #define RCC_ETHCKSELR_ETHPTPDIV_1             (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */
22080 #define RCC_ETHCKSELR_ETHPTPDIV_2             (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */
22081 #define RCC_ETHCKSELR_ETHPTPDIV_3             (0x3U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000030 */
22082 #define RCC_ETHCKSELR_ETHPTPDIV_4             (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */
22083 #define RCC_ETHCKSELR_ETHPTPDIV_5             (0x5U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000050 */
22084 #define RCC_ETHCKSELR_ETHPTPDIV_6             (0x6U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000060 */
22085 #define RCC_ETHCKSELR_ETHPTPDIV_7             (0x7U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000070 */
22086 #define RCC_ETHCKSELR_ETHPTPDIV_8             (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */
22087 #define RCC_ETHCKSELR_ETHPTPDIV_9             (0x9U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000090 */
22088 #define RCC_ETHCKSELR_ETHPTPDIV_10            (0xAU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000A0 */
22089 #define RCC_ETHCKSELR_ETHPTPDIV_11            (0xBU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000B0 */
22090 #define RCC_ETHCKSELR_ETHPTPDIV_12            (0xCU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000C0 */
22091 #define RCC_ETHCKSELR_ETHPTPDIV_13            (0xDU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000D0 */
22092 #define RCC_ETHCKSELR_ETHPTPDIV_14            (0xEU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000E0 */
22093 #define RCC_ETHCKSELR_ETHPTPDIV_15            (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */
22094 
22095 /********************  Bit definition for RCC_QSPICKSELR register********************/
22096 #define RCC_QSPICKSELR_QSPISRC_Pos            (0U)
22097 #define RCC_QSPICKSELR_QSPISRC_Msk            (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */
22098 #define RCC_QSPICKSELR_QSPISRC                RCC_QSPICKSELR_QSPISRC_Msk       /*QUADSPI kernel clock source selection*/
22099 #define RCC_QSPICKSELR_QSPISRC_0              (0x0U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000000 */
22100 #define RCC_QSPICKSELR_QSPISRC_1              (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */
22101 #define RCC_QSPICKSELR_QSPISRC_2              (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */
22102 #define RCC_QSPICKSELR_QSPISRC_3              (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */
22103 
22104 /********************  Bit definition for RCC_FMCCKSELR register********************/
22105 #define RCC_FMCCKSELR_FMCSRC_Pos              (0U)
22106 #define RCC_FMCCKSELR_FMCSRC_Msk              (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */
22107 #define RCC_FMCCKSELR_FMCSRC                  RCC_FMCCKSELR_FMCSRC_Msk         /*FMC kernel clock source selection*/
22108 #define RCC_FMCCKSELR_FMCSRC_0                (0x0U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000000 */
22109 #define RCC_FMCCKSELR_FMCSRC_1                (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */
22110 #define RCC_FMCCKSELR_FMCSRC_2                (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */
22111 #define RCC_FMCCKSELR_FMCSRC_3                (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */
22112 
22113 /********************  Bit definition for RCC_FDCANCKSELR register********************/
22114 #define RCC_FDCANCKSELR_FDCANSRC_Pos          (0U)
22115 #define RCC_FDCANCKSELR_FDCANSRC_Msk          (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */
22116 #define RCC_FDCANCKSELR_FDCANSRC              RCC_FDCANCKSELR_FDCANSRC_Msk     /*FDCAN kernel clock source selection*/
22117 #define RCC_FDCANCKSELR_FDCANSRC_0            (0x0U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000000 */
22118 #define RCC_FDCANCKSELR_FDCANSRC_1            (0x1U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000001 */
22119 #define RCC_FDCANCKSELR_FDCANSRC_2            (0x2U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000002 */
22120 #define RCC_FDCANCKSELR_FDCANSRC_3            (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */
22121 
22122 /********************  Bit definition for RCC_SPDIFCKSELR register********************/
22123 #define RCC_SPDIFCKSELR_SPDIFSRC_Pos          (0U)
22124 #define RCC_SPDIFCKSELR_SPDIFSRC_Msk          (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */
22125 #define RCC_SPDIFCKSELR_SPDIFSRC              RCC_SPDIFCKSELR_SPDIFSRC_Msk     /*SPDIF-RX kernel clock source selection*/
22126 #define RCC_SPDIFCKSELR_SPDIFSRC_0            (0x0U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000000 */
22127 #define RCC_SPDIFCKSELR_SPDIFSRC_1            (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */
22128 #define RCC_SPDIFCKSELR_SPDIFSRC_2            (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */
22129 
22130 /********************  Bit definition for RCC_CECCKSELR register********************/
22131 #define RCC_CECCKSELR_CECSRC_Pos              (0U)
22132 #define RCC_CECCKSELR_CECSRC_Msk              (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */
22133 #define RCC_CECCKSELR_CECSRC                  RCC_CECCKSELR_CECSRC_Msk         /*CEC-HDMI kernel clock source selection*/
22134 #define RCC_CECCKSELR_CECSRC_0                (0x0U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000000 */
22135 #define RCC_CECCKSELR_CECSRC_1                (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */
22136 #define RCC_CECCKSELR_CECSRC_2                (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */
22137 
22138 /********************  Bit definition for RCC_USBCKSELR register********************/
22139 #define RCC_USBCKSELR_USBPHYSRC_Pos           (0U)
22140 #define RCC_USBCKSELR_USBPHYSRC_Msk           (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */
22141 #define RCC_USBCKSELR_USBPHYSRC               RCC_USBCKSELR_USBPHYSRC_Msk      /*USB PHY kernel clock source selection*/
22142 #define RCC_USBCKSELR_USBPHYSRC_0             (0x0U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000000 */
22143 #define RCC_USBCKSELR_USBPHYSRC_1             (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */
22144 #define RCC_USBCKSELR_USBPHYSRC_2             (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */
22145 
22146 #define RCC_USBCKSELR_USBOSRC_Pos             (4U)
22147 #define RCC_USBCKSELR_USBOSRC_Msk             (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */
22148 #define RCC_USBCKSELR_USBOSRC                 RCC_USBCKSELR_USBOSRC_Msk        /*USB OTG kernel clock source selection*/
22149 #define RCC_USBCKSELR_USBOSRC_0               (0x0U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000000 */
22150 #define RCC_USBCKSELR_USBOSRC_1               (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */
22151 
22152 /********************  Bit definition for RCC_RNG1CKSELR register********************/
22153 #define RCC_RNG1CKSELR_RNG1SRC_Pos            (0U)
22154 #define RCC_RNG1CKSELR_RNG1SRC_Msk            (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */
22155 #define RCC_RNG1CKSELR_RNG1SRC                RCC_RNG1CKSELR_RNG1SRC_Msk       /*RNG1 kernel clock source selection*/
22156 #define RCC_RNG1CKSELR_RNG1SRC_0              (0x0U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000000 */
22157 #define RCC_RNG1CKSELR_RNG1SRC_1              (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */
22158 #define RCC_RNG1CKSELR_RNG1SRC_2              (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */
22159 #define RCC_RNG1CKSELR_RNG1SRC_3              (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */
22160 
22161 /********************  Bit definition for RCC_RNG2CKSELR register********************/
22162 #define RCC_RNG2CKSELR_RNG2SRC_Pos            (0U)
22163 #define RCC_RNG2CKSELR_RNG2SRC_Msk            (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */
22164 #define RCC_RNG2CKSELR_RNG2SRC                RCC_RNG2CKSELR_RNG2SRC_Msk       /*RNG2 kernel clock source selection*/
22165 #define RCC_RNG2CKSELR_RNG2SRC_0              (0x0U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000000 */
22166 #define RCC_RNG2CKSELR_RNG2SRC_1              (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */
22167 #define RCC_RNG2CKSELR_RNG2SRC_2              (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */
22168 #define RCC_RNG2CKSELR_RNG2SRC_3              (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */
22169 
22170 /********************  Bit definition for RCC_CPERCKSELR register********************/
22171 #define RCC_CPERCKSELR_CKPERSRC_Pos           (0U)
22172 #define RCC_CPERCKSELR_CKPERSRC_Msk           (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */
22173 #define RCC_CPERCKSELR_CKPERSRC               RCC_CPERCKSELR_CKPERSRC_Msk      /*Oscillator selection for kernel clock*/
22174 #define RCC_CPERCKSELR_CKPERSRC_0             (0x0U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000000 */
22175 #define RCC_CPERCKSELR_CKPERSRC_1             (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */
22176 #define RCC_CPERCKSELR_CKPERSRC_2             (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */
22177 #define RCC_CPERCKSELR_CKPERSRC_3             (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */
22178 
22179 /********************  Bit definition for RCC_CSTGENCKSELR register******************/
22180 #define RCC_STGENCKSELR_STGENSRC_Pos          (0U)
22181 #define RCC_STGENCKSELR_STGENSRC_Msk          (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */
22182 #define RCC_STGENCKSELR_STGENSRC              RCC_STGENCKSELR_STGENSRC_Msk     /*Oscillator selection for kernel clock*/
22183 #define RCC_STGENCKSELR_STGENSRC_0            (0x0U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000000 */
22184 #define RCC_STGENCKSELR_STGENSRC_1            (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */
22185 #define RCC_STGENCKSELR_STGENSRC_2            (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */
22186 
22187 /********************  Bit definition for RCC_DDRITFCR register*********************/
22188 #define  RCC_DDRITFCR_DDRC1EN                  B(0)
22189 #define  RCC_DDRITFCR_DDRC1LPEN                B(1)
22190 #define  RCC_DDRITFCR_DDRC2EN                  B(2)
22191 #define  RCC_DDRITFCR_DDRC2LPEN                B(3)
22192 #define  RCC_DDRITFCR_DDRPHYCEN                B(4)
22193 #define  RCC_DDRITFCR_DDRPHYCLPEN              B(5)
22194 #define  RCC_DDRITFCR_DDRCAPBEN                B(6)
22195 #define  RCC_DDRITFCR_DDRCAPBLPEN              B(7)
22196 #define  RCC_DDRITFCR_AXIDCGEN                 B(8)
22197 #define  RCC_DDRITFCR_DDRPHYCAPBEN             B(9)
22198 #define  RCC_DDRITFCR_DDRPHYCAPBLPEN           B(10)
22199 
22200 #define RCC_DDRITFCR_KERDCG_DLY_Pos           (10U)
22201 #define RCC_DDRITFCR_KERDCG_DLY_Msk           (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */
22202 #define RCC_DDRITFCR_KERDCG_DLY               RCC_DDRITFCR_KERDCG_DLY_Msk      /*AXIDCG delay*/
22203 #define RCC_DDRITFCR_KERDCG_DLY_0             (0x0U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000000 */
22204 #define RCC_DDRITFCR_KERDCG_DLY_1             (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000400 */
22205 #define RCC_DDRITFCR_KERDCG_DLY_2             (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */
22206 #define RCC_DDRITFCR_KERDCG_DLY_3             (0x3U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000C00 */
22207 #define RCC_DDRITFCR_KERDCG_DLY_4             (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */
22208 #define RCC_DDRITFCR_KERDCG_DLY_5             (0x5U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001400 */
22209 #define RCC_DDRITFCR_KERDCG_DLY_6             (0x6U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001800 */
22210 #define RCC_DDRITFCR_KERDCG_DLY_7             (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001C00 */
22211 #define RCC_DDRITFCR_KERDCG_DLY_8             (0x8U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */
22212 #define RCC_DDRITFCR_KERDCG_DLY_9             (0x9U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002400 */
22213 #define RCC_DDRITFCR_KERDCG_DLY_10            (0xAU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002800 */
22214 #define RCC_DDRITFCR_KERDCG_DLY_11            (0xBU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002C00 */
22215 #define RCC_DDRITFCR_KERDCG_DLY_12            (0xCU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003000 */
22216 #define RCC_DDRITFCR_KERDCG_DLY_13            (0xDU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003400 */
22217 #define RCC_DDRITFCR_KERDCG_DLY_14            (0xEU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */
22218 #define RCC_DDRITFCR_KERDCG_DLY_15            (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */
22219 
22220 #define  RCC_DDRITFCR_DDRCAPBRST                B(14)
22221 #define  RCC_DDRITFCR_DDRCAXIRST                B(15)
22222 #define  RCC_DDRITFCR_DDRCORERST                B(16)
22223 #define  RCC_DDRITFCR_DPHYAPBRST                B(17)
22224 #define  RCC_DDRITFCR_DPHYRST                   B(18)
22225 #define  RCC_DDRITFCR_DPHYCTLRST                B(19)
22226 
22227 #define RCC_DDRITFCR_DDRCKMOD_Pos             (20U)
22228 #define RCC_DDRITFCR_DDRCKMOD_Msk             (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */
22229 #define RCC_DDRITFCR_DDRCKMOD                 RCC_DDRITFCR_DDRCKMOD_Msk        /*RCC mode for DDR clock control*/
22230 #define RCC_DDRITFCR_DDRCKMOD_0               (0x0U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00000000 */
22231 #define RCC_DDRITFCR_DDRCKMOD_1               (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */
22232 #define RCC_DDRITFCR_DDRCKMOD_2               (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */
22233 #define RCC_DDRITFCR_DDRCKMOD_5               (0x5U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00500000 */
22234 #define RCC_DDRITFCR_DDRCKMOD_6               (0x6U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00600000 */
22235 
22236 /********************  Bit definition for RCC_DSICKSELR register********************/
22237 #define RCC_DSICKSELR_DSISRC_Pos              (0U)
22238 #define RCC_DSICKSELR_DSISRC_Msk              (0x1U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000001 */
22239 #define RCC_DSICKSELR_DSISRC                  RCC_DSICKSELR_DSISRC_Msk         /*DSIHOST kernel clock source selection*/
22240 #define RCC_DSICKSELR_DSISRC_0                (0x0U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000000 */
22241 #define RCC_DSICKSELR_DSISRC_1                (0x1U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000001 */
22242 
22243 /********************  Bit definition for RCC_ADCCKSELR register********************/
22244 #define RCC_ADCCKSELR_ADCSRC_Pos              (0U)
22245 #define RCC_ADCCKSELR_ADCSRC_Msk              (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */
22246 #define RCC_ADCCKSELR_ADCSRC                  RCC_ADCCKSELR_ADCSRC_Msk         /*ADC1&2 kernel clock source selection*/
22247 #define RCC_ADCCKSELR_ADCSRC_0                (0x0U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000000 */
22248 #define RCC_ADCCKSELR_ADCSRC_1                (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */
22249 #define RCC_ADCCKSELR_ADCSRC_2                (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */
22250 
22251 /********************  Bit definition for RCC_LPTIM45CKSELR register********************/
22252 #define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos      (0U)
22253 #define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk      (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */
22254 #define RCC_LPTIM45CKSELR_LPTIM45SRC          RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*LPTIM4 and LPTIM5 kernel clock source selection*/
22255 #define RCC_LPTIM45CKSELR_LPTIM45SRC_0        (0x0U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000000 */
22256 #define RCC_LPTIM45CKSELR_LPTIM45SRC_1        (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */
22257 #define RCC_LPTIM45CKSELR_LPTIM45SRC_2        (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */
22258 #define RCC_LPTIM45CKSELR_LPTIM45SRC_3        (0x3U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000003 */
22259 #define RCC_LPTIM45CKSELR_LPTIM45SRC_4        (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */
22260 #define RCC_LPTIM45CKSELR_LPTIM45SRC_5        (0x5U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000005 */
22261 #define RCC_LPTIM45CKSELR_LPTIM45SRC_6        (0x6U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000006 */
22262 
22263 /********************  Bit definition for RCC_LPTIM23CKSELR register********************/
22264 #define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos      (0U)
22265 #define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk      (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */
22266 #define RCC_LPTIM23CKSELR_LPTIM23SRC          RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*LPTIM2 and LPTIM3 kernel clock source selection*/
22267 #define RCC_LPTIM23CKSELR_LPTIM23SRC_0        (0x0U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000000 */
22268 #define RCC_LPTIM23CKSELR_LPTIM23SRC_1        (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */
22269 #define RCC_LPTIM23CKSELR_LPTIM23SRC_2        (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */
22270 #define RCC_LPTIM23CKSELR_LPTIM23SRC_3        (0x3U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000003 */
22271 #define RCC_LPTIM23CKSELR_LPTIM23SRC_4        (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */
22272 #define RCC_LPTIM23CKSELR_LPTIM23SRC_5        (0x5U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000005 */
22273 
22274 /********************  Bit definition for RCC_LPTIM1CKSELR register********************/
22275 #define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos        (0U)
22276 #define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk        (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */
22277 #define RCC_LPTIM1CKSELR_LPTIM1SRC            RCC_LPTIM1CKSELR_LPTIM1SRC_Msk   /*LPTIM1 kernel clock source selection*/
22278 #define RCC_LPTIM1CKSELR_LPTIM1SRC_0          (0x0U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000000 */
22279 #define RCC_LPTIM1CKSELR_LPTIM1SRC_1          (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */
22280 #define RCC_LPTIM1CKSELR_LPTIM1SRC_2          (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */
22281 #define RCC_LPTIM1CKSELR_LPTIM1SRC_3          (0x3U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000003 */
22282 #define RCC_LPTIM1CKSELR_LPTIM1SRC_4          (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */
22283 #define RCC_LPTIM1CKSELR_LPTIM1SRC_5          (0x5U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000005 */
22284 #define RCC_LPTIM1CKSELR_LPTIM1SRC_6          (0x6U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000006 */
22285 
22286 /********************  Bit definition for RCC_MP_BOOTCR register*********************/
22287 #define RCC_MP_BOOTCR_MCU_BEN_Pos             (0U)
22288 #define RCC_MP_BOOTCR_MCU_BEN_Msk             (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */
22289 #define RCC_MP_BOOTCR_MCU_BEN                 RCC_MP_BOOTCR_MCU_BEN_Msk        /*MCU Boot Enable after STANDBY*/
22290 #define RCC_MP_BOOTCR_MPU_BEN_Pos             (1U)
22291 #define RCC_MP_BOOTCR_MPU_BEN_Msk             (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */
22292 #define RCC_MP_BOOTCR_MPU_BEN                 RCC_MP_BOOTCR_MPU_BEN_Msk        /*MPU Boot Enable after STANDBY*/
22293 
22294 /********************  Bit definition for RCC_MP_SREQSETR register********************/
22295 /* @note The MCU cannot access to this register */
22296 #define RCC_MP_SREQSETR_STPREQ_P0_Pos         (0U)
22297 #define RCC_MP_SREQSETR_STPREQ_P0_Msk         (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */
22298 #define RCC_MP_SREQSETR_STPREQ_P0             RCC_MP_SREQSETR_STPREQ_P0_Msk    /*Stop Request for MPU processor number 0*/
22299 #define RCC_MP_SREQSETR_STPREQ_P1_Pos         (1U)
22300 #define RCC_MP_SREQSETR_STPREQ_P1_Msk         (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */
22301 #define RCC_MP_SREQSETR_STPREQ_P1             RCC_MP_SREQSETR_STPREQ_P1_Msk    /*Stop Request for MPU processor number 1*/
22302 
22303 /********************  Bit definition for RCC_MP_SREQCLRR register********************/
22304 /* @note The MCU cannot access to this register */
22305 #define RCC_MP_SREQCLRR_STPREQ_P0_Pos         (0U)
22306 #define RCC_MP_SREQCLRR_STPREQ_P0_Msk         (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */
22307 #define RCC_MP_SREQCLRR_STPREQ_P0             RCC_MP_SREQCLRR_STPREQ_P0_Msk    /*Stop Request for MPU processor number 0*/
22308 #define RCC_MP_SREQCLRR_STPREQ_P1_Pos         (1U)
22309 #define RCC_MP_SREQCLRR_STPREQ_P1_Msk         (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */
22310 #define RCC_MP_SREQCLRR_STPREQ_P1             RCC_MP_SREQCLRR_STPREQ_P1_Msk    /*Stop Request for MPU processor number 1*/
22311 
22312 /********************  Bit definition for RCC_MP_GCR register********************/
22313 #define RCC_MP_GCR_BOOT_MCU_Pos               (0U)
22314 #define RCC_MP_GCR_BOOT_MCU_Msk               (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */
22315 #define RCC_MP_GCR_BOOT_MCU                   RCC_MP_GCR_BOOT_MCU_Msk          /*Allows the MCU to boot*/
22316 #define RCC_MP_GCR_BOOT_MCU_0                 (0x0U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000000 */
22317 #define RCC_MP_GCR_BOOT_MCU_1                 (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */
22318 
22319 /********************  Bit definition for RCC_MP_APRSTCR register ********************/
22320 #define RCC_MP_APRSTCR_RDCTLEN_Pos            (0U)
22321 #define RCC_MP_APRSTCR_RDCTLEN_Msk            (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */
22322 #define RCC_MP_APRSTCR_RDCTLEN                RCC_MP_APRSTCR_RDCTLEN_Msk           /*Reset Delay Control Enable*/
22323 #define RCC_MP_APRSTCR_RSTTO_Pos              (8U)
22324 #define RCC_MP_APRSTCR_RSTTO_Msk              (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */
22325 #define RCC_MP_APRSTCR_RSTTO                  RCC_MP_APRSTCR_RSTTO_Msk            /*Reset Timeout Delay Adjust*/
22326 
22327 /********************  Bit definition for RCC_MP_APRSTSR register ********************/
22328 #define RCC_MP_APRSTSR_RSTTOV_Pos             (8U)
22329 #define RCC_MP_APRSTSR_RSTTOV_Msk             (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */
22330 #define RCC_MP_APRSTSR_RSTTOV                 RCC_MP_APRSTSR_RSTTOV_Msk            /*Reset Timeout Delay Value*/
22331 
22332 /*******************  Bit definition for RCC_BDCR register  ********************/
22333 #define RCC_BDCR_LSEON_Pos                    (0U)
22334 #define RCC_BDCR_LSEON_Msk                    (0x1U << RCC_BDCR_LSEON_Pos)     /*!< 0x00000001 */
22335 #define RCC_BDCR_LSEON                        RCC_BDCR_LSEON_Msk               /*LSE oscillator enabled*/
22336 #define RCC_BDCR_LSEBYP_Pos                   (1U)
22337 #define RCC_BDCR_LSEBYP_Msk                   (0x1U << RCC_BDCR_LSEBYP_Pos)    /*!< 0x00000002 */
22338 #define RCC_BDCR_LSEBYP                       RCC_BDCR_LSEBYP_Msk              /*LSE oscillator bypass*/
22339 #define RCC_BDCR_LSERDY_Pos                   (2U)
22340 #define RCC_BDCR_LSERDY_Msk                   (0x1U << RCC_BDCR_LSERDY_Pos)    /*!< 0x00000004 */
22341 #define RCC_BDCR_LSERDY                       RCC_BDCR_LSERDY_Msk              /*LSE oscillator ready*/
22342 
22343 #define RCC_BDCR_DIGBYP_Pos                   (3U)
22344 #define RCC_BDCR_DIGBYP_Msk                   (0x1U << RCC_BDCR_DIGBYP_Pos)    /*!< 0x00000008 */
22345 #define RCC_BDCR_DIGBYP                       RCC_BDCR_DIGBYP_Msk              /*LSE digital bypass */
22346 
22347 #define RCC_BDCR_LSEDRV_Pos                   (4U)
22348 #define RCC_BDCR_LSEDRV_Msk                   (0x3U << RCC_BDCR_LSEDRV_Pos)    /*!< 0x00000030 */
22349 #define RCC_BDCR_LSEDRV                       RCC_BDCR_LSEDRV_Msk              /*LSE oscillator driving capability*/
22350 #define RCC_BDCR_LSEDRV_0                     (0x0U << RCC_BDCR_LSEDRV_Pos)    /*!< 0x00000000 */
22351 #define RCC_BDCR_LSEDRV_1                     (0x1U << RCC_BDCR_LSEDRV_Pos)    /*!< 0x00000010 */
22352 #define RCC_BDCR_LSEDRV_2                     (0x2U << RCC_BDCR_LSEDRV_Pos)    /*!< 0x00000020 */
22353 #define RCC_BDCR_LSEDRV_3                     (0x3U << RCC_BDCR_LSEDRV_Pos)    /*!< 0x00000030 */
22354 
22355 #define RCC_BDCR_LSECSSON_Pos                 (8U)
22356 #define RCC_BDCR_LSECSSON_Msk                 (0x1U << RCC_BDCR_LSECSSON_Pos)  /*!< 0x00000100 */
22357 #define RCC_BDCR_LSECSSON                     RCC_BDCR_LSECSSON_Msk            /*LSE clock security system enable*/
22358 #define RCC_BDCR_LSECSSD_Pos                  (9U)
22359 #define RCC_BDCR_LSECSSD_Msk                  (0x1U << RCC_BDCR_LSECSSD_Pos)   /*!< 0x00000200 */
22360 #define RCC_BDCR_LSECSSD                      RCC_BDCR_LSECSSD_Msk             /*LSE clock security system failure detection*/
22361 
22362 #define RCC_BDCR_RTCSRC_Pos                   (16U)
22363 #define RCC_BDCR_RTCSRC_Msk                   (0x3U << RCC_BDCR_RTCSRC_Pos)    /*!< 0x00030000 */
22364 #define RCC_BDCR_RTCSRC                       RCC_BDCR_RTCSRC_Msk              /* RTC clock source selection*/
22365 #define RCC_BDCR_RTCSRC_0                     (0x0U << RCC_BDCR_RTCSRC_Pos)    /*!< 0x00000000 */
22366 #define RCC_BDCR_RTCSRC_1                     (0x1U << RCC_BDCR_RTCSRC_Pos)    /*!< 0x00010000 */
22367 #define RCC_BDCR_RTCSRC_2                     (0x2U << RCC_BDCR_RTCSRC_Pos)    /*!< 0x00020000 */
22368 #define RCC_BDCR_RTCSRC_3                     (0x3U << RCC_BDCR_RTCSRC_Pos)    /*!< 0x00030000 */
22369 
22370 #define RCC_BDCR_RTCCKEN_Pos                  (20U)
22371 #define RCC_BDCR_RTCCKEN_Msk                  (0x1U << RCC_BDCR_RTCCKEN_Pos)   /*!< 0x00100000 */
22372 #define RCC_BDCR_RTCCKEN                      RCC_BDCR_RTCCKEN_Msk             /*RTC clock enable*/
22373 #define RCC_BDCR_VSWRST_Pos                   (31U)
22374 #define RCC_BDCR_VSWRST_Msk                   (0x1U << RCC_BDCR_VSWRST_Pos)    /*!< 0x80000000 */
22375 #define RCC_BDCR_VSWRST                       RCC_BDCR_VSWRST_Msk              /*V Switch domain software reset*/
22376 
22377 /*******************  Bit definition for RCC_RDLSICR register  ********************/
22378 #define RCC_RDLSICR_LSION_Pos                 (0U)
22379 #define RCC_RDLSICR_LSION_Msk                 (0x1U << RCC_RDLSICR_LSION_Pos)  /*!< 0x00000001 */
22380 #define RCC_RDLSICR_LSION                     RCC_RDLSICR_LSION_Msk            /*LSI oscillator enabled*/
22381 #define RCC_RDLSICR_LSIRDY_Pos                (1U)
22382 #define RCC_RDLSICR_LSIRDY_Msk                (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */
22383 #define RCC_RDLSICR_LSIRDY                    RCC_RDLSICR_LSIRDY_Msk           /*LSI oscillator ready*/
22384 #define RCC_RDLSICR_MRD_Pos                   (16U)
22385 #define RCC_RDLSICR_MRD_Msk                   (0x1FU << RCC_RDLSICR_MRD_Pos)   /*!< 0x001F0000 */
22386 #define RCC_RDLSICR_MRD                       RCC_RDLSICR_MRD_Msk              /*Minimum Reset Duration*/
22387 #define RCC_RDLSICR_EADLY_Pos                 (24U)
22388 #define RCC_RDLSICR_EADLY_Msk                 (0x7U << RCC_RDLSICR_EADLY_Pos)   /*!< 0x07000000 */
22389 #define RCC_RDLSICR_EADLY                     RCC_RDLSICR_EADLY_Msk             /*External access delays*/
22390 #define RCC_RDLSICR_SPARE_Pos                 (27U)
22391 #define RCC_RDLSICR_SPARE_Msk                 (0x1FU << RCC_RDLSICR_SPARE_Pos)  /*!< 0xF8000000 */
22392 #define RCC_RDLSICR_SPARE                     RCC_RDLSICR_SPARE_Msk             /*Spare bits*/
22393 
22394 /*******************  Bit definition for RCC_MP_CIER register *******************/
22395 #define RCC_MP_CIER_LSIRDYIE_Pos              (0U)
22396 #define RCC_MP_CIER_LSIRDYIE_Msk              (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
22397 #define RCC_MP_CIER_LSIRDYIE                  RCC_MP_CIER_LSIRDYIE_Msk         /*LSI ready Interrupt Enable*/
22398 #define RCC_MP_CIER_LSERDYIE_Pos              (1U)
22399 #define RCC_MP_CIER_LSERDYIE_Msk              (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
22400 #define RCC_MP_CIER_LSERDYIE                  RCC_MP_CIER_LSERDYIE_Msk         /*LSE ready Interrupt Enable*/
22401 #define RCC_MP_CIER_HSIRDYIE_Pos              (2U)
22402 #define RCC_MP_CIER_HSIRDYIE_Msk              (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */
22403 #define RCC_MP_CIER_HSIRDYIE                  RCC_MP_CIER_HSIRDYIE_Msk         /*HSI ready Interrupt Enable*/
22404 #define RCC_MP_CIER_HSERDYIE_Pos              (3U)
22405 #define RCC_MP_CIER_HSERDYIE_Msk              (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */
22406 #define RCC_MP_CIER_HSERDYIE                  RCC_MP_CIER_HSERDYIE_Msk         /*HSE ready Interrupt Enable*/
22407 #define RCC_MP_CIER_CSIRDYIE_Pos              (4U)
22408 #define RCC_MP_CIER_CSIRDYIE_Msk              (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */
22409 #define RCC_MP_CIER_CSIRDYIE                  RCC_MP_CIER_CSIRDYIE_Msk         /*CSI ready Interrupt Enable*/
22410 #define RCC_MP_CIER_PLL1DYIE_Pos              (8U)
22411 #define RCC_MP_CIER_PLL1DYIE_Msk              (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */
22412 #define RCC_MP_CIER_PLL1DYIE                  RCC_MP_CIER_PLL1DYIE_Msk         /*PLL1DYIE ready Interrupt Enable*/
22413 #define RCC_MP_CIER_PLL2DYIE_Pos              (9U)
22414 #define RCC_MP_CIER_PLL2DYIE_Msk              (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */
22415 #define RCC_MP_CIER_PLL2DYIE                  RCC_MP_CIER_PLL2DYIE_Msk         /*PLL2DYIE ready Interrupt Enable*/
22416 #define RCC_MP_CIER_PLL3DYIE_Pos              (10U)
22417 #define RCC_MP_CIER_PLL3DYIE_Msk              (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */
22418 #define RCC_MP_CIER_PLL3DYIE                  RCC_MP_CIER_PLL3DYIE_Msk         /*PLL3DYIE ready Interrupt Enable*/
22419 #define RCC_MP_CIER_PLL4DYIE_Pos              (11U)
22420 #define RCC_MP_CIER_PLL4DYIE_Msk              (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */
22421 #define RCC_MP_CIER_PLL4DYIE                  RCC_MP_CIER_PLL4DYIE_Msk         /*PLL4DYIE ready Interrupt Enable*/
22422 #define RCC_MP_CIER_LSECSSIE_Pos              (16U)
22423 #define RCC_MP_CIER_LSECSSIE_Msk              (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */
22424 #define RCC_MP_CIER_LSECSSIE                  RCC_MP_CIER_LSECSSIE_Msk         /*LSE clock security system Interrupt Enable*/
22425 #define RCC_MP_CIER_WKUPIE_Pos                (20U)
22426 #define RCC_MP_CIER_WKUPIE_Msk                (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */
22427 #define RCC_MP_CIER_WKUPIE                    RCC_MP_CIER_WKUPIE_Msk           /*Wake-up from CSTOP Interrupt Enable*/
22428 
22429 /*******************  Bit definition for RCC_MP_CIFR register  ********************/
22430 #define RCC_MP_CIFR_LSIRDYF_Pos               (0U)
22431 #define RCC_MP_CIFR_LSIRDYF_Msk               (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
22432 #define RCC_MP_CIFR_LSIRDYF                   RCC_MP_CIFR_LSIRDYF_Msk          /*LSI ready Interrupt Flag*/
22433 #define RCC_MP_CIFR_LSERDYF_Pos               (1U)
22434 #define RCC_MP_CIFR_LSERDYF_Msk               (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
22435 #define RCC_MP_CIFR_LSERDYF                   RCC_MP_CIFR_LSERDYF_Msk          /*LSE ready Interrupt Flag*/
22436 #define RCC_MP_CIFR_HSIRDYF_Pos               (2U)
22437 #define RCC_MP_CIFR_HSIRDYF_Msk               (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */
22438 #define RCC_MP_CIFR_HSIRDYF                   RCC_MP_CIFR_HSIRDYF_Msk          /*HSI ready Interrupt Flag*/
22439 #define RCC_MP_CIFR_HSERDYF_Pos               (3U)
22440 #define RCC_MP_CIFR_HSERDYF_Msk               (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */
22441 #define RCC_MP_CIFR_HSERDYF                   RCC_MP_CIFR_HSERDYF_Msk          /*HSE ready Interrupt Flag*/
22442 #define RCC_MP_CIFR_CSIRDYF_Pos               (4U)
22443 #define RCC_MP_CIFR_CSIRDYF_Msk               (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */
22444 #define RCC_MP_CIFR_CSIRDYF                   RCC_MP_CIFR_CSIRDYF_Msk          /*CSI ready Interrupt Flag*/
22445 #define RCC_MP_CIFR_PLL1DYF_Pos               (8U)
22446 #define RCC_MP_CIFR_PLL1DYF_Msk               (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */
22447 #define RCC_MP_CIFR_PLL1DYF                   RCC_MP_CIFR_PLL1DYF_Msk          /*PLL1 ready Interrupt Flag*/
22448 #define RCC_MP_CIFR_PLL2DYF_Pos               (9U)
22449 #define RCC_MP_CIFR_PLL2DYF_Msk               (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */
22450 #define RCC_MP_CIFR_PLL2DYF                   RCC_MP_CIFR_PLL2DYF_Msk          /*PLL2 ready Interrupt Flag*/
22451 #define RCC_MP_CIFR_PLL3DYF_Pos               (10U)
22452 #define RCC_MP_CIFR_PLL3DYF_Msk               (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */
22453 #define RCC_MP_CIFR_PLL3DYF                   RCC_MP_CIFR_PLL3DYF_Msk          /*PLL3 ready Interrupt Flag*/
22454 #define RCC_MP_CIFR_PLL4DYF_Pos               (11U)
22455 #define RCC_MP_CIFR_PLL4DYF_Msk               (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */
22456 #define RCC_MP_CIFR_PLL4DYF                   RCC_MP_CIFR_PLL4DYF_Msk          /*PLL4 ready Interrupt Flag*/
22457 #define RCC_MP_CIFR_LSECSSF_Pos               (16U)
22458 #define RCC_MP_CIFR_LSECSSF_Msk               (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */
22459 #define RCC_MP_CIFR_LSECSSF                   RCC_MP_CIFR_LSECSSF_Msk          /*LSE clock security system Interrupt Flag*/
22460 #define RCC_MP_CIFR_WKUPF_Pos                 (20U)
22461 #define RCC_MP_CIFR_WKUPF_Msk                 (0x1U << RCC_MP_CIFR_WKUPF_Pos)  /*!< 0x00100000 */
22462 #define RCC_MP_CIFR_WKUPF                     RCC_MP_CIFR_WKUPF_Msk            /*Wake-up from CSTOP Interrupt Flag*/
22463 
22464 /*******************  Bit definition for RCC_MC_CIER register *******************/
22465 #define RCC_MC_CIER_LSIRDYIE_Pos              (0U)
22466 #define RCC_MC_CIER_LSIRDYIE_Msk              (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
22467 #define RCC_MC_CIER_LSIRDYIE                  RCC_MC_CIER_LSIRDYIE_Msk         /*LSI ready Interrupt Enable*/
22468 #define RCC_MC_CIER_LSERDYIE_Pos              (1U)
22469 #define RCC_MC_CIER_LSERDYIE_Msk              (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
22470 #define RCC_MC_CIER_LSERDYIE                  RCC_MC_CIER_LSERDYIE_Msk         /*LSE ready Interrupt Enable*/
22471 #define RCC_MC_CIER_HSIRDYIE_Pos              (2U)
22472 #define RCC_MC_CIER_HSIRDYIE_Msk              (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */
22473 #define RCC_MC_CIER_HSIRDYIE                  RCC_MC_CIER_HSIRDYIE_Msk         /*HSI ready Interrupt Enable*/
22474 #define RCC_MC_CIER_HSERDYIE_Pos              (3U)
22475 #define RCC_MC_CIER_HSERDYIE_Msk              (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */
22476 #define RCC_MC_CIER_HSERDYIE                  RCC_MC_CIER_HSERDYIE_Msk         /*HSE ready Interrupt Enable*/
22477 #define RCC_MC_CIER_CSIRDYIE_Pos              (4U)
22478 #define RCC_MC_CIER_CSIRDYIE_Msk              (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */
22479 #define RCC_MC_CIER_CSIRDYIE                  RCC_MC_CIER_CSIRDYIE_Msk         /*CSI ready Interrupt Enable*/
22480 #define RCC_MC_CIER_PLL1DYIE_Pos              (8U)
22481 #define RCC_MC_CIER_PLL1DYIE_Msk              (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */
22482 #define RCC_MC_CIER_PLL1DYIE                  RCC_MC_CIER_PLL1DYIE_Msk         /*PLL1DYIE ready Interrupt Enable*/
22483 #define RCC_MC_CIER_PLL2DYIE_Pos              (9U)
22484 #define RCC_MC_CIER_PLL2DYIE_Msk              (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */
22485 #define RCC_MC_CIER_PLL2DYIE                  RCC_MC_CIER_PLL2DYIE_Msk         /*PLL2DYIE ready Interrupt Enable*/
22486 #define RCC_MC_CIER_PLL3DYIE_Pos              (10U)
22487 #define RCC_MC_CIER_PLL3DYIE_Msk              (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */
22488 #define RCC_MC_CIER_PLL3DYIE                  RCC_MC_CIER_PLL3DYIE_Msk         /*PLL3DYIE ready Interrupt Enable*/
22489 #define RCC_MC_CIER_PLL4DYIE_Pos              (11U)
22490 #define RCC_MC_CIER_PLL4DYIE_Msk              (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */
22491 #define RCC_MC_CIER_PLL4DYIE                  RCC_MC_CIER_PLL4DYIE_Msk         /*PLL4DYIE ready Interrupt Enable*/
22492 #define RCC_MC_CIER_LSECSSIE_Pos              (16U)
22493 #define RCC_MC_CIER_LSECSSIE_Msk              (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */
22494 #define RCC_MC_CIER_LSECSSIE                  RCC_MC_CIER_LSECSSIE_Msk         /*LSE clock security system Interrupt Enable*/
22495 #define RCC_MC_CIER_WKUPIE_Pos                (20U)
22496 #define RCC_MC_CIER_WKUPIE_Msk                (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */
22497 #define RCC_MC_CIER_WKUPIE                    RCC_MC_CIER_WKUPIE_Msk           /*Wake-up from CSTOP Interrupt Enable*/
22498 
22499 /*******************  Bit definition for RCC_MC_CIFR register  ********************/
22500 #define RCC_MC_CIFR_LSIRDYF_Pos               (0U)
22501 #define RCC_MC_CIFR_LSIRDYF_Msk               (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
22502 #define RCC_MC_CIFR_LSIRDYF                   RCC_MC_CIFR_LSIRDYF_Msk          /*LSI ready Interrupt Flag*/
22503 #define RCC_MC_CIFR_LSERDYF_Pos               (1U)
22504 #define RCC_MC_CIFR_LSERDYF_Msk               (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
22505 #define RCC_MC_CIFR_LSERDYF                   RCC_MC_CIFR_LSERDYF_Msk          /*LSE ready Interrupt Flag*/
22506 #define RCC_MC_CIFR_HSIRDYF_Pos               (2U)
22507 #define RCC_MC_CIFR_HSIRDYF_Msk               (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */
22508 #define RCC_MC_CIFR_HSIRDYF                   RCC_MC_CIFR_HSIRDYF_Msk          /*HSI ready Interrupt Flag*/
22509 #define RCC_MC_CIFR_HSERDYF_Pos               (3U)
22510 #define RCC_MC_CIFR_HSERDYF_Msk               (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */
22511 #define RCC_MC_CIFR_HSERDYF                   RCC_MC_CIFR_HSERDYF_Msk          /*HSE ready Interrupt Flag*/
22512 #define RCC_MC_CIFR_CSIRDYF_Pos               (4U)
22513 #define RCC_MC_CIFR_CSIRDYF_Msk               (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */
22514 #define RCC_MC_CIFR_CSIRDYF                   RCC_MC_CIFR_CSIRDYF_Msk          /*CSI ready Interrupt Flag*/
22515 #define RCC_MC_CIFR_PLL1DYF_Pos               (8U)
22516 #define RCC_MC_CIFR_PLL1DYF_Msk               (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */
22517 #define RCC_MC_CIFR_PLL1DYF                   RCC_MC_CIFR_PLL1DYF_Msk          /*PLL1 ready Interrupt Flag*/
22518 #define RCC_MC_CIFR_PLL2DYF_Pos               (9U)
22519 #define RCC_MC_CIFR_PLL2DYF_Msk               (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */
22520 #define RCC_MC_CIFR_PLL2DYF                   RCC_MC_CIFR_PLL2DYF_Msk          /*PLL2 ready Interrupt Flag*/
22521 #define RCC_MC_CIFR_PLL3DYF_Pos               (10U)
22522 #define RCC_MC_CIFR_PLL3DYF_Msk               (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */
22523 #define RCC_MC_CIFR_PLL3DYF                   RCC_MC_CIFR_PLL3DYF_Msk          /*PLL3 ready Interrupt Flag*/
22524 #define RCC_MC_CIFR_PLL4DYF_Pos               (11U)
22525 #define RCC_MC_CIFR_PLL4DYF_Msk               (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */
22526 #define RCC_MC_CIFR_PLL4DYF                   RCC_MC_CIFR_PLL4DYF_Msk          /*PLL4 ready Interrupt Flag*/
22527 #define RCC_MC_CIFR_LSECSSF_Pos               (16U)
22528 #define RCC_MC_CIFR_LSECSSF_Msk               (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */
22529 #define RCC_MC_CIFR_LSECSSF                   RCC_MC_CIFR_LSECSSF_Msk          /*LSE clock security system Interrupt Flag*/
22530 #define RCC_MC_CIFR_WKUPF_Pos                 (20U)
22531 #define RCC_MC_CIFR_WKUPF_Msk                 (0x1U << RCC_MC_CIFR_WKUPF_Pos)  /*!< 0x00100000 */
22532 #define RCC_MC_CIFR_WKUPF                     RCC_MC_CIFR_WKUPF_Msk            /*Wake-up from CSTOP Interrupt Flag*/
22533 
22534 
22535 /*******************  Bit definition for RCC_PWRLPDLYCR register  ********************/
22536 #define RCC_PWRLPDLYCR_PWRLP_DLY_Pos          (0U)
22537 #define RCC_PWRLPDLYCR_PWRLP_DLY_Msk          (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */
22538 #define RCC_PWRLPDLYCR_PWRLP_DLY              RCC_PWRLPDLYCR_PWRLP_DLY_Msk     /*PWR_LP Delay value*/
22539 #define RCC_PWRLPDLYCR_PWRLP_DLY_0            (0x000000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000000 */
22540 #define RCC_PWRLPDLYCR_PWRLP_DLY_1            (0x000001U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */
22541 #define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos     (0U)
22542 #define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk     (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos) /*!< 0x003FFFFF */
22543 #define RCC_PWRLPDLYCR_PWRLP_DLY_LAST         RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk /*A PWR_LP delay of about 65.5 milliseconds is observed*/
22544 
22545 #define RCC_PWRLPDLYCR_MCTMPSKP                B(24)                           /*Skip the PWR_LP Delay for MCU*/
22546 
22547 
22548 /*******************  Bit definition for RCC_MP_RSTSSETR register  *********************/
22549 /*!< This register is dedicated to the BOOTROM code in order to update the reset source.
22550  *   This register is updated by the BOOTROM code, after a power-on reset (por_rst), a
22551  *   system reset (nreset), or an exit from Standby or CStandby.
22552  *@note The application software shall not use this register. In order to identify the
22553  *      reset source, the MPU application must use RCC MPU Reset Status Clear Register
22554  *      (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status
22555  *      Clear Register (RCC_MC_RSTSCLRR).
22556  *@note Writing '0' has no effect, reading will return the effective values of the
22557  *      corresponding bits. Writing a '1' sets the corresponding bit to '1'.
22558  *@note The register is located in VDDCORE.
22559  *@note If TZEN = '1', this register can only be modified in secure mode.
22560  */
22561 #define RCC_MP_RSTSSETR_PORRSTF_Pos           (0U)
22562 #define RCC_MP_RSTSSETR_PORRSTF_Msk           (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos)   /*!< 0x00000001 */
22563 #define RCC_MP_RSTSSETR_PORRSTF               RCC_MP_RSTSSETR_PORRSTF_Msk             /*POR/PDR reset flag*/
22564 
22565 #define RCC_MP_RSTSSETR_BORRSTF_Pos           (1U)
22566 #define RCC_MP_RSTSSETR_BORRSTF_Msk           (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos)   /*!< 0x00000002 */
22567 #define RCC_MP_RSTSSETR_BORRSTF               RCC_MP_RSTSSETR_BORRSTF_Msk             /*BOR reset flag*/
22568 
22569 #define RCC_MP_RSTSSETR_PADRSTF_Pos           (2U)
22570 #define RCC_MP_RSTSSETR_PADRSTF_Msk           (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos)   /*!< 0x00000004 */
22571 #define RCC_MP_RSTSSETR_PADRSTF               RCC_MP_RSTSSETR_PADRSTF_Msk             /*NRST reset flag*/
22572 
22573 #define RCC_MP_RSTSSETR_HCSSRSTF_Pos          (3U)
22574 #define RCC_MP_RSTSSETR_HCSSRSTF_Msk          (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos)  /*!< 0x00000008 */
22575 #define RCC_MP_RSTSSETR_HCSSRSTF              RCC_MP_RSTSSETR_HCSSRSTF_Msk            /*HSE CSS reset flag*/
22576 
22577 #define RCC_MP_RSTSSETR_VCORERSTF_Pos         (4U)
22578 #define RCC_MP_RSTSSETR_VCORERSTF_Msk         (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */
22579 #define RCC_MP_RSTSSETR_VCORERSTF             RCC_MP_RSTSSETR_VCORERSTF_Msk           /*VDDCORE reset flag*/
22580 
22581 #define RCC_MP_RSTSSETR_MPSYSRSTF_Pos         (6U)
22582 #define RCC_MP_RSTSSETR_MPSYSRSTF_Msk         (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */
22583 #define RCC_MP_RSTSSETR_MPSYSRSTF             RCC_MP_RSTSSETR_MPSYSRSTF_Msk           /*MPU System reset flag*/
22584 
22585 #define RCC_MP_RSTSSETR_MCSYSRSTF_Pos         (7U)
22586 #define RCC_MP_RSTSSETR_MCSYSRSTF_Msk         (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */
22587 #define RCC_MP_RSTSSETR_MCSYSRSTF             RCC_MP_RSTSSETR_MCSYSRSTF_Msk           /*MCU System reset flag*/
22588 
22589 #define RCC_MP_RSTSSETR_IWDG1RSTF_Pos         (8U)
22590 #define RCC_MP_RSTSSETR_IWDG1RSTF_Msk         (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */
22591 #define RCC_MP_RSTSSETR_IWDG1RSTF             RCC_MP_RSTSSETR_IWDG1RSTF_Msk           /*IWDG1 reset flag*/
22592 
22593 #define RCC_MP_RSTSSETR_IWDG2RSTF_Pos         (9U)
22594 #define RCC_MP_RSTSSETR_IWDG2RSTF_Msk         (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */
22595 #define RCC_MP_RSTSSETR_IWDG2RSTF             RCC_MP_RSTSSETR_IWDG2RSTF_Msk           /*IWDG2 reset flag*/
22596 
22597 #define RCC_MP_RSTSSETR_STDBYRSTF_Pos         (11U)
22598 #define RCC_MP_RSTSSETR_STDBYRSTF_Msk         (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */
22599 #define RCC_MP_RSTSSETR_STDBYRSTF             RCC_MP_RSTSSETR_STDBYRSTF_Msk           /*System Standby reset flag*/
22600 
22601 #define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos        (12U)
22602 #define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk        (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */
22603 #define RCC_MP_RSTSSETR_CSTDBYRSTF            RCC_MP_RSTSSETR_CSTDBYRSTF_Msk           /*MPU CStandby reset flag*/
22604 
22605 #define RCC_MP_RSTSSETR_MPUP0RSTF_Pos         (13U)
22606 #define RCC_MP_RSTSSETR_MPUP0RSTF_Msk         (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */
22607 #define RCC_MP_RSTSSETR_MPUP0RSTF             RCC_MP_RSTSSETR_MPUP0RSTF_Msk           /*MPU processor 0 reset flag*/
22608 
22609 #define RCC_MP_RSTSSETR_MPUP1RSTF_Pos         (14U)
22610 #define RCC_MP_RSTSSETR_MPUP1RSTF_Msk         (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */
22611 #define RCC_MP_RSTSSETR_MPUP1RSTF             RCC_MP_RSTSSETR_MPUP1RSTF_Msk           /*MPU processor 1 reset flag*/
22612 
22613 #define RCC_MP_RSTSSETR_SPARE_Pos             (15U)
22614 #define RCC_MP_RSTSSETR_SPARE_Msk             (0x1U << RCC_MP_RSTSSETR_SPARE_Pos)     /*!< 0x00008000 */
22615 #define RCC_MP_RSTSSETR_SPARE                 RCC_MP_RSTSSETR_SPARE_Msk               /*Spare bits*/
22616 
22617 /*******************  Bit definition for RCC_APB1RSTSETR register  ************/
22618 /*!< This register is used to activate the reset of the corresponding peripheral */
22619 #define RCC_APB1RSTSETR_TIM2RST               B(0)
22620 #define RCC_APB1RSTSETR_TIM3RST               B(1)
22621 #define RCC_APB1RSTSETR_TIM4RST               B(2)
22622 #define RCC_APB1RSTSETR_TIM5RST               B(3)
22623 #define RCC_APB1RSTSETR_TIM6RST               B(4)
22624 #define RCC_APB1RSTSETR_TIM7RST               B(5)
22625 #define RCC_APB1RSTSETR_TIM12RST              B(6)
22626 #define RCC_APB1RSTSETR_TIM13RST              B(7)
22627 #define RCC_APB1RSTSETR_TIM14RST              B(8)
22628 #define RCC_APB1RSTSETR_LPTIM1RST             B(9)
22629 #define RCC_APB1RSTSETR_SPI2RST               B(11)
22630 #define RCC_APB1RSTSETR_SPI3RST               B(12)
22631 #define RCC_APB1RSTSETR_USART2RST             B(14)
22632 #define RCC_APB1RSTSETR_USART3RST             B(15)
22633 #define RCC_APB1RSTSETR_UART4RST              B(16)
22634 #define RCC_APB1RSTSETR_UART5RST              B(17)
22635 #define RCC_APB1RSTSETR_UART7RST              B(18)
22636 #define RCC_APB1RSTSETR_UART8RST              B(19)
22637 #define RCC_APB1RSTSETR_I2C1RST               B(21)
22638 #define RCC_APB1RSTSETR_I2C2RST               B(22)
22639 #define RCC_APB1RSTSETR_I2C3RST               B(23)
22640 #define RCC_APB1RSTSETR_I2C5RST               B(24)
22641 #define RCC_APB1RSTSETR_SPDIFRST              B(26)
22642 #define RCC_APB1RSTSETR_CECRST                B(27)
22643 #define RCC_APB1RSTSETR_DAC12RST              B(29)
22644 #define RCC_APB1RSTSETR_MDIOSRST              B(31)
22645 
22646 /*******************  Bit definition for RCC_APB1RSTCLRR register  ************/
22647 /*!< This register is used to release the reset of the corresponding peripheral */
22648 #define RCC_APB1RSTCLRR_TIM2RST               B(0)
22649 #define RCC_APB1RSTCLRR_TIM3RST               B(1)
22650 #define RCC_APB1RSTCLRR_TIM4RST               B(2)
22651 #define RCC_APB1RSTCLRR_TIM5RST               B(3)
22652 #define RCC_APB1RSTCLRR_TIM6RST               B(4)
22653 #define RCC_APB1RSTCLRR_TIM7RST               B(5)
22654 #define RCC_APB1RSTCLRR_TIM12RST              B(6)
22655 #define RCC_APB1RSTCLRR_TIM13RST              B(7)
22656 #define RCC_APB1RSTCLRR_TIM14RST              B(8)
22657 #define RCC_APB1RSTCLRR_LPTIM1RST             B(9)
22658 #define RCC_APB1RSTCLRR_SPI2RST               B(11)
22659 #define RCC_APB1RSTCLRR_SPI3RST               B(12)
22660 #define RCC_APB1RSTCLRR_USART2RST             B(14)
22661 #define RCC_APB1RSTCLRR_USART3RST             B(15)
22662 #define RCC_APB1RSTCLRR_UART4RST              B(16)
22663 #define RCC_APB1RSTCLRR_UART5RST              B(17)
22664 #define RCC_APB1RSTCLRR_UART7RST              B(18)
22665 #define RCC_APB1RSTCLRR_UART8RST              B(19)
22666 #define RCC_APB1RSTCLRR_I2C1RST               B(21)
22667 #define RCC_APB1RSTCLRR_I2C2RST               B(22)
22668 #define RCC_APB1RSTCLRR_I2C3RST               B(23)
22669 #define RCC_APB1RSTCLRR_I2C5RST               B(24)
22670 #define RCC_APB1RSTCLRR_SPDIFRST              B(26)
22671 #define RCC_APB1RSTCLRR_CECRST                B(27)
22672 #define RCC_APB1RSTCLRR_DAC12RST              B(29)
22673 #define RCC_APB1RSTCLRR_MDIOSRST              B(31)
22674 
22675 /*******************  Bit definition for RCC_APB2RSTSETR register  ************/
22676 /*!< This register is used to activate the reset of the corresponding peripheral */
22677 #define RCC_APB2RSTSETR_TIM1RST               B(0)
22678 #define RCC_APB2RSTSETR_TIM8RST               B(1)
22679 #define RCC_APB2RSTSETR_TIM15RST              B(2)
22680 #define RCC_APB2RSTSETR_TIM16RST              B(3)
22681 #define RCC_APB2RSTSETR_TIM17RST              B(4)
22682 #define RCC_APB2RSTSETR_SPI1RST               B(8)
22683 #define RCC_APB2RSTSETR_SPI4RST               B(9)
22684 #define RCC_APB2RSTSETR_SPI5RST               B(10)
22685 #define RCC_APB2RSTSETR_USART6RST             B(13)
22686 #define RCC_APB2RSTSETR_SAI1RST               B(16)
22687 #define RCC_APB2RSTSETR_SAI2RST               B(17)
22688 #define RCC_APB2RSTSETR_SAI3RST               B(18)
22689 #define RCC_APB2RSTSETR_DFSDMRST              B(20)
22690 #define RCC_APB2RSTSETR_FDCANRST              B(24)
22691 
22692 /*******************  Bit definition for RCC_APB2RSTCLRR register  ************/
22693 /*!< This register is used to release the reset of the corresponding peripheral */
22694 #define RCC_APB2RSTCLRR_TIM1RST               B(0)
22695 #define RCC_APB2RSTCLRR_TIM8RST               B(1)
22696 #define RCC_APB2RSTCLRR_TIM15RST              B(2)
22697 #define RCC_APB2RSTCLRR_TIM16RST              B(3)
22698 #define RCC_APB2RSTCLRR_TIM17RST              B(4)
22699 #define RCC_APB2RSTCLRR_SPI1RST               B(8)
22700 #define RCC_APB2RSTCLRR_SPI4RST               B(9)
22701 #define RCC_APB2RSTCLRR_SPI5RST               B(10)
22702 #define RCC_APB2RSTCLRR_USART6RST             B(13)
22703 #define RCC_APB2RSTCLRR_SAI1RST               B(16)
22704 #define RCC_APB2RSTCLRR_SAI2RST               B(17)
22705 #define RCC_APB2RSTCLRR_SAI3RST               B(18)
22706 #define RCC_APB2RSTCLRR_DFSDMRST              B(20)
22707 #define RCC_APB2RSTCLRR_FDCANRST              B(24)
22708 
22709 /*******************  Bit definition for RCC_APB3RSTSETR register  ************/
22710 /*!< This register is used to activate the reset of the corresponding peripheral */
22711 #define RCC_APB3RSTSETR_LPTIM2RST             B(0)
22712 #define RCC_APB3RSTSETR_LPTIM3RST             B(1)
22713 #define RCC_APB3RSTSETR_LPTIM4RST             B(2)
22714 #define RCC_APB3RSTSETR_LPTIM5RST             B(3)
22715 #define RCC_APB3RSTSETR_SAI4RST               B(8)
22716 #define RCC_APB3RSTSETR_SYSCFGRST             B(11)
22717 #define RCC_APB3RSTSETR_VREFRST               B(13)
22718 #define RCC_APB3RSTSETR_DTSRST                B(16)
22719 #define RCC_APB3RSTSETR_PMBCTRLRST            B(17)
22720 
22721 /*******************  Bit definition for RCC_APB3RSTCLRR register  ************/
22722 /*!< This register is used to release the reset of the corresponding peripheral */
22723 #define RCC_APB3RSTCLRR_LPTIM2RST             B(0)
22724 #define RCC_APB3RSTCLRR_LPTIM3RST             B(1)
22725 #define RCC_APB3RSTCLRR_LPTIM4RST             B(2)
22726 #define RCC_APB3RSTCLRR_LPTIM5RST             B(3)
22727 #define RCC_APB3RSTCLRR_SAI4RST               B(8)
22728 #define RCC_APB3RSTCLRR_SYSCFGRST             B(11)
22729 #define RCC_APB3RSTCLRR_VREFRST               B(13)
22730 #define RCC_APB3RSTCLRR_DTSRST                B(16)
22731 #define RCC_APB3RSTCLRR_PMBCTRLRST            B(17)
22732 
22733 /*******************  Bit definition for RCC_AHB2RSTSETR register  ************/
22734 /*!< This register is used to activate the reset of the corresponding peripheral */
22735 #define RCC_AHB2RSTSETR_DMA1RST               B(0)
22736 #define RCC_AHB2RSTSETR_DMA2RST               B(1)
22737 #define RCC_AHB2RSTSETR_DMAMUXRST             B(2)
22738 #define RCC_AHB2RSTSETR_ADC12RST              B(5)
22739 #define RCC_AHB2RSTSETR_USBORST               B(8)
22740 #define RCC_AHB2RSTSETR_SDMMC3RST             B(16)
22741 
22742 /*******************  Bit definition for RCC_AHB2RSTCLRR register  ************/
22743 /*!< This register is used to release the reset of the corresponding peripheral */
22744 #define RCC_AHB2RSTCLRR_DMA1RST               B(0)
22745 #define RCC_AHB2RSTCLRR_DMA2RST               B(1)
22746 #define RCC_AHB2RSTCLRR_DMAMUXRST             B(2)
22747 #define RCC_AHB2RSTCLRR_ADC12RST              B(5)
22748 #define RCC_AHB2RSTCLRR_USBORST               B(8)
22749 #define RCC_AHB2RSTCLRR_SDMMC3RST             B(16)
22750 
22751 /*******************  Bit definition for RCC_AHB3RSTSETR register  ************/
22752 /*!< This register is used to activate the reset of the corresponding peripheral */
22753 #define RCC_AHB3RSTSETR_DCMIRST               B(0)
22754 #define RCC_AHB3RSTSETR_HASH2RST              B(5)
22755 #define RCC_AHB3RSTSETR_RNG2RST               B(6)
22756 #define RCC_AHB3RSTSETR_CRC2RST               B(7)
22757 #define RCC_AHB3RSTSETR_HSEMRST               B(11)
22758 #define RCC_AHB3RSTSETR_IPCCRST               B(12)
22759 
22760 /*******************  Bit definition for RCC_AHB3RSTCLRR register  ************/
22761 /*!< This register is used to release the reset of the corresponding peripheral */
22762 #define RCC_AHB3RSTCLRR_DCMIRST               B(0)
22763 #define RCC_AHB3RSTCLRR_HASH2RST              B(5)
22764 #define RCC_AHB3RSTCLRR_RNG2RST               B(6)
22765 #define RCC_AHB3RSTCLRR_CRC2RST               B(7)
22766 #define RCC_AHB3RSTCLRR_HSEMRST               B(11)
22767 #define RCC_AHB3RSTCLRR_IPCCRST               B(12)
22768 
22769 /*******************  Bit definition for RCC_AHB4RSTSETR register  ************/
22770 /*!< This register is used to activate the reset of the corresponding peripheral */
22771 #define RCC_AHB4RSTSETR_GPIOARST              B(0)
22772 #define RCC_AHB4RSTSETR_GPIOBRST              B(1)
22773 #define RCC_AHB4RSTSETR_GPIOCRST              B(2)
22774 #define RCC_AHB4RSTSETR_GPIODRST              B(3)
22775 #define RCC_AHB4RSTSETR_GPIOERST              B(4)
22776 #define RCC_AHB4RSTSETR_GPIOFRST              B(5)
22777 #define RCC_AHB4RSTSETR_GPIOGRST              B(6)
22778 #define RCC_AHB4RSTSETR_GPIOHRST              B(7)
22779 #define RCC_AHB4RSTSETR_GPIOIRST              B(8)
22780 #define RCC_AHB4RSTSETR_GPIOJRST              B(9)
22781 #define RCC_AHB4RSTSETR_GPIOKRST              B(10)
22782 
22783 /*******************  Bit definition for RCC_AHB4RSTCLRR register  ************/
22784 /*!< This register is used to release the reset of the corresponding peripheral */
22785 #define RCC_AHB4RSTCLRR_GPIOARST              B(0)
22786 #define RCC_AHB4RSTCLRR_GPIOBRST              B(1)
22787 #define RCC_AHB4RSTCLRR_GPIOCRST              B(2)
22788 #define RCC_AHB4RSTCLRR_GPIODRST              B(3)
22789 #define RCC_AHB4RSTCLRR_GPIOERST              B(4)
22790 #define RCC_AHB4RSTCLRR_GPIOFRST              B(5)
22791 #define RCC_AHB4RSTCLRR_GPIOGRST              B(6)
22792 #define RCC_AHB4RSTCLRR_GPIOHRST              B(7)
22793 #define RCC_AHB4RSTCLRR_GPIOIRST              B(8)
22794 #define RCC_AHB4RSTCLRR_GPIOJRST              B(9)
22795 #define RCC_AHB4RSTCLRR_GPIOKRST              B(10)
22796 
22797 /*******************  Bit definition for RCC_APB4RSTSETR register  ************/
22798 /*!< This register is used to activate the reset of the corresponding peripheral */
22799 #define RCC_APB4RSTSETR_LTDCRST               B(0)
22800 #define RCC_APB4RSTSETR_DSIRST                B(4)
22801 #define RCC_APB4RSTSETR_DDRPERFMRST           B(8)
22802 #define RCC_APB4RSTSETR_USBPHYRST             B(16)
22803 
22804 /*******************  Bit definition for RCC_APB4RSTCLRR register  ************/
22805 /*!< This register is used to release the reset of the corresponding peripheral */
22806 #define RCC_APB4RSTCLRR_LTDCRST               B(0)
22807 #define RCC_APB4RSTCLRR_DSIRST                B(4)
22808 #define RCC_APB4RSTCLRR_DDRPERFMRST           B(8)
22809 #define RCC_APB4RSTCLRR_USBPHYRST             B(16)
22810 
22811 /*******************  Bit definition for RCC_APB5RSTSETR register  ************/
22812 /*!< This register is used to activate the reset of the corresponding peripheral */
22813 #define RCC_APB5RSTSETR_SPI6RST               B(0)
22814 #define RCC_APB5RSTSETR_I2C4RST               B(2)
22815 #define RCC_APB5RSTSETR_I2C6RST               B(3)
22816 #define RCC_APB5RSTSETR_USART1RST             B(4)
22817 #define RCC_APB5RSTSETR_STGENRST              B(20)
22818 
22819 /*******************  Bit definition for RCC_APB5RSTCLRR register  ************/
22820 /*!< This register is used to release the reset of the corresponding peripheral */
22821 #define RCC_APB5RSTCLRR_SPI6RST               B(0)
22822 #define RCC_APB5RSTCLRR_I2C4RST               B(2)
22823 #define RCC_APB5RSTCLRR_I2C6RST               B(3)
22824 #define RCC_APB5RSTCLRR_USART1RST             B(4)
22825 #define RCC_APB5RSTCLRR_STGENRST              B(20)
22826 
22827 /*******************  Bit definition for RCC_AHB5RSTSETR register  ************/
22828 /*!< This register is used to activate the reset of the corresponding peripheral */
22829 #define RCC_AHB5RSTSETR_GPIOZRST              B(0)
22830 #define RCC_AHB5RSTSETR_HASH1RST              B(5)
22831 #define RCC_AHB5RSTSETR_RNG1RST               B(6)
22832 #define RCC_AHB5RSTSETR_AXIMCRST              B(16)
22833 
22834 /*******************  Bit definition for RCC_AHB5RSTCLRR register  ************/
22835 /*!< This register is used to release the reset of the corresponding peripheral */
22836 #define RCC_AHB5RSTCLRR_GPIOZRST              B(0)
22837 #define RCC_AHB5RSTCLRR_HASH1RST              B(5)
22838 #define RCC_AHB5RSTCLRR_RNG1RST               B(6)
22839 #define RCC_AHB5RSTCLRR_AXIMCRST              B(16)
22840 
22841 /*******************  Bit definition for RCC_AHB6RSTSETR register  ************/
22842 /*!< This register is used to activate the reset of the corresponding peripheral */
22843 #define RCC_AHB6RSTSETR_GPURST                B(5)
22844 #define RCC_AHB6RSTSETR_ETHMACRST             B(10)
22845 #define RCC_AHB6RSTSETR_FMCRST                B(12)
22846 #define RCC_AHB6RSTSETR_QSPIRST               B(14)
22847 #define RCC_AHB6RSTSETR_SDMMC1RST             B(16)
22848 #define RCC_AHB6RSTSETR_SDMMC2RST             B(17)
22849 #define RCC_AHB6RSTSETR_CRC1RST               B(20)
22850 #define RCC_AHB6RSTSETR_USBHRST               B(24)
22851 
22852 /*******************  Bit definition for RCC_AHB6RSTCLRR register  ************/
22853 /*!< This register is used to release the reset of the corresponding peripheral */
22854 #define RCC_AHB6RSTCLRR_ETHMACRST             B(10)
22855 #define RCC_AHB6RSTCLRR_FMCRST                B(12)
22856 #define RCC_AHB6RSTCLRR_QSPIRST               B(14)
22857 #define RCC_AHB6RSTCLRR_SDMMC1RST             B(16)
22858 #define RCC_AHB6RSTCLRR_SDMMC2RST             B(17)
22859 #define RCC_AHB6RSTCLRR_CRC1RST               B(20)
22860 #define RCC_AHB6RSTCLRR_USBHRST               B(24)
22861 
22862 /*******************  Bit definition for RCC_TZAHB6RSTSETR register  ************/
22863 /*!< This register is used to activate the reset of the corresponding peripheral */
22864 #define RCC_TZAHB6RSTSETR_MDMARST             B(0)
22865 
22866 /*******************  Bit definition for RCC_TZAHB6RSTCLRR register  ************/
22867 /*!< This register is used to release the reset of the corresponding peripheral */
22868 #define RCC_TZAHB6RSTCLRR_MDMARST             B(0)
22869 
22870 /*******************  Bit definition for RCC_MP_GRSTCSETR register  ************/
22871 /*!< This register is used by the MPU in order to generate either a MCU reset
22872  * or a system reset or a reset of one of the two MPU processors. Writing '0' has
22873  * no effect, reading will return the effective values of the corresponding bits.
22874  * Writing a '1' activates the reset */
22875 #define RCC_MP_GRSTCSETR_MPSYSRST_Pos         (0U)
22876 #define RCC_MP_GRSTCSETR_MPSYSRST_Msk         (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */
22877 #define RCC_MP_GRSTCSETR_MPSYSRST             RCC_MP_GRSTCSETR_MPSYSRST_Msk           /*System reset */
22878 #define RCC_MP_GRSTCSETR_MCURST_Pos           (1U)
22879 #define RCC_MP_GRSTCSETR_MCURST_Msk           (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos)   /*!< 0x00000002 */
22880 #define RCC_MP_GRSTCSETR_MCURST               RCC_MP_GRSTCSETR_MCURST_Msk             /*MCU reset */
22881 #define RCC_MP_GRSTCSETR_MPUP0RST_Pos         (4U)
22882 #define RCC_MP_GRSTCSETR_MPUP0RST_Msk         (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */
22883 #define RCC_MP_GRSTCSETR_MPUP0RST             RCC_MP_GRSTCSETR_MPUP0RST_Msk           /*MPU processor 0 reset*/
22884 #define RCC_MP_GRSTCSETR_MPUP1RST_Pos         (5U)
22885 #define RCC_MP_GRSTCSETR_MPUP1RST_Msk         (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */
22886 #define RCC_MP_GRSTCSETR_MPUP1RST             RCC_MP_GRSTCSETR_MPUP1RST_Msk           /*MPU processor 1 reset*/
22887 
22888 /*******************  Bit definition for RCC_MC_APB1ENSETR register  ***********/
22889 /*!<  This register is used to set the peripheral clock enable bit of the corresponding
22890  * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */
22891 #define RCC_MC_APB1ENSETR_TIM2EN              B(0)
22892 #define RCC_MC_APB1ENSETR_TIM3EN              B(1)
22893 #define RCC_MC_APB1ENSETR_TIM4EN              B(2)
22894 #define RCC_MC_APB1ENSETR_TIM5EN              B(3)
22895 #define RCC_MC_APB1ENSETR_TIM6EN              B(4)
22896 #define RCC_MC_APB1ENSETR_TIM7EN              B(5)
22897 #define RCC_MC_APB1ENSETR_TIM12EN             B(6)
22898 #define RCC_MC_APB1ENSETR_TIM13EN             B(7)
22899 #define RCC_MC_APB1ENSETR_TIM14EN             B(8)
22900 #define RCC_MC_APB1ENSETR_LPTIM1EN            B(9)
22901 #define RCC_MC_APB1ENSETR_SPI2EN              B(11)
22902 #define RCC_MC_APB1ENSETR_SPI3EN              B(12)
22903 #define RCC_MC_APB1ENSETR_USART2EN            B(14)
22904 #define RCC_MC_APB1ENSETR_USART3EN            B(15)
22905 #define RCC_MC_APB1ENSETR_UART4EN             B(16)
22906 #define RCC_MC_APB1ENSETR_UART5EN             B(17)
22907 #define RCC_MC_APB1ENSETR_UART7EN             B(18)
22908 #define RCC_MC_APB1ENSETR_UART8EN             B(19)
22909 #define RCC_MC_APB1ENSETR_I2C1EN              B(21)
22910 #define RCC_MC_APB1ENSETR_I2C2EN              B(22)
22911 #define RCC_MC_APB1ENSETR_I2C3EN              B(23)
22912 #define RCC_MC_APB1ENSETR_I2C5EN              B(24)
22913 #define RCC_MC_APB1ENSETR_SPDIFEN             B(26)
22914 #define RCC_MC_APB1ENSETR_CECEN               B(27)
22915 #define RCC_MC_APB1ENSETR_WWDG1EN             B(28)
22916 #define RCC_MC_APB1ENSETR_DAC12EN             B(29)
22917 #define RCC_MC_APB1ENSETR_MDIOSEN             B(31)
22918 
22919 /*******************  Bit definition for RCC_MC_APB1ENCLRR register  ************/
22920 /*!< This register is used to clear the peripheral clock enable bit of the corresponding
22921 peripheral. It shall be used to deallocate a peripheral from MCU */
22922 #define RCC_MC_APB1ENCLRR_TIM2EN              B(0)
22923 #define RCC_MC_APB1ENCLRR_TIM3EN              B(1)
22924 #define RCC_MC_APB1ENCLRR_TIM4EN              B(2)
22925 #define RCC_MC_APB1ENCLRR_TIM5EN              B(3)
22926 #define RCC_MC_APB1ENCLRR_TIM6EN              B(4)
22927 #define RCC_MC_APB1ENCLRR_TIM7EN              B(5)
22928 #define RCC_MC_APB1ENCLRR_TIM12EN             B(6)
22929 #define RCC_MC_APB1ENCLRR_TIM13EN             B(7)
22930 #define RCC_MC_APB1ENCLRR_TIM14EN             B(8)
22931 #define RCC_MC_APB1ENCLRR_LPTIM1EN            B(9)
22932 #define RCC_MC_APB1ENCLRR_SPI2EN              B(11)
22933 #define RCC_MC_APB1ENCLRR_SPI3EN              B(12)
22934 #define RCC_MC_APB1ENCLRR_USART2EN            B(14)
22935 #define RCC_MC_APB1ENCLRR_USART3EN            B(15)
22936 #define RCC_MC_APB1ENCLRR_UART4EN             B(16)
22937 #define RCC_MC_APB1ENCLRR_UART5EN             B(17)
22938 #define RCC_MC_APB1ENCLRR_UART7EN             B(18)
22939 #define RCC_MC_APB1ENCLRR_UART8EN             B(19)
22940 #define RCC_MC_APB1ENCLRR_I2C1EN              B(21)
22941 #define RCC_MC_APB1ENCLRR_I2C2EN              B(22)
22942 #define RCC_MC_APB1ENCLRR_I2C3EN              B(23)
22943 #define RCC_MC_APB1ENCLRR_I2C5EN              B(24)
22944 #define RCC_MC_APB1ENCLRR_SPDIFEN             B(26)
22945 #define RCC_MC_APB1ENCLRR_CECEN               B(27)
22946 #define RCC_MC_APB1ENCLRR_WWDG1EN             B(28)
22947 #define RCC_MC_APB1ENCLRR_DAC12EN             B(29)
22948 #define RCC_MC_APB1ENCLRR_MDIOSEN             B(31)
22949 
22950 /*******************  Bit definition for RCC_MC_APB2ENSETR register  ***********/
22951 /*!<  This register is used to set the peripheral clock enable bit of the corresponding
22952  * peripheral to 1.  It shall be used to allocate a peripheral to the MCU. */
22953 #define RCC_MC_APB2ENSETR_TIM1EN              B(0)
22954 #define RCC_MC_APB2ENSETR_TIM8EN              B(1)
22955 #define RCC_MC_APB2ENSETR_TIM15EN             B(2)
22956 #define RCC_MC_APB2ENSETR_TIM16EN             B(3)
22957 #define RCC_MC_APB2ENSETR_TIM17EN             B(4)
22958 #define RCC_MC_APB2ENSETR_SPI1EN              B(8)
22959 #define RCC_MC_APB2ENSETR_SPI4EN              B(9)
22960 #define RCC_MC_APB2ENSETR_SPI5EN              B(10)
22961 #define RCC_MC_APB2ENSETR_USART6EN            B(13)
22962 #define RCC_MC_APB2ENSETR_SAI1EN              B(16)
22963 #define RCC_MC_APB2ENSETR_SAI2EN              B(17)
22964 #define RCC_MC_APB2ENSETR_SAI3EN              B(18)
22965 #define RCC_MC_APB2ENSETR_DFSDMEN             B(20)
22966 #define RCC_MC_APB2ENSETR_ADFSDMEN            B(21)
22967 #define RCC_MC_APB2ENSETR_FDCANEN             B(24)
22968 
22969 /*******************  Bit definition for RCC_MC_APB2ENCLRR register  ************/
22970 /*!< This register is used to clear the peripheral clock enable bit of the corresponding
22971  * peripheral. It shall be used to deallocate a peripheral from MCU */
22972 #define RCC_MC_APB2ENCLRR_TIM1EN              B(0)
22973 #define RCC_MC_APB2ENCLRR_TIM8EN              B(1)
22974 #define RCC_MC_APB2ENCLRR_TIM15EN             B(2)
22975 #define RCC_MC_APB2ENCLRR_TIM16EN             B(3)
22976 #define RCC_MC_APB2ENCLRR_TIM17EN             B(4)
22977 #define RCC_MC_APB2ENCLRR_SPI1EN              B(8)
22978 #define RCC_MC_APB2ENCLRR_SPI4EN              B(9)
22979 #define RCC_MC_APB2ENCLRR_SPI5EN              B(10)
22980 #define RCC_MC_APB2ENCLRR_USART6EN            B(13)
22981 #define RCC_MC_APB2ENCLRR_SAI1EN              B(16)
22982 #define RCC_MC_APB2ENCLRR_SAI2EN              B(17)
22983 #define RCC_MC_APB2ENCLRR_SAI3EN              B(18)
22984 #define RCC_MC_APB2ENCLRR_DFSDMEN             B(20)
22985 #define RCC_MC_APB2ENCLRR_ADFSDMEN            B(21)
22986 #define RCC_MC_APB2ENCLRR_FDCANEN             B(24)
22987 
22988 /*******************  Bit definition for RCC_MC_APB3ENSETR register  ***********/
22989 /*!<  This register is used to set the peripheral clock enable bit of the corresponding
22990  * peripheral to 1.  It shall be used to allocate a peripheral to the MCU. */
22991 #define RCC_MC_APB3ENSETR_LPTIM2EN            B(0)
22992 #define RCC_MC_APB3ENSETR_LPTIM3EN            B(1)
22993 #define RCC_MC_APB3ENSETR_LPTIM4EN            B(2)
22994 #define RCC_MC_APB3ENSETR_LPTIM5EN            B(3)
22995 #define RCC_MC_APB3ENSETR_SAI4EN              B(8)
22996 #define RCC_MC_APB3ENSETR_SYSCFGEN            B(11)
22997 #define RCC_MC_APB3ENSETR_VREFEN              B(13)
22998 #define RCC_MC_APB3ENSETR_DTSEN               B(16)
22999 #define RCC_MC_APB3ENSETR_PMBCTRLEN           B(17)
23000 #define RCC_MC_APB3ENSETR_HDPEN               B(20)
23001 
23002 /*******************  Bit definition for RCC_MC_APB3ENCLRR register  ************/
23003 /*!< This register is used to clear the peripheral clock enable bit of the corresponding
23004  * peripheral. It shall be used to deallocate a peripheral from MCU */
23005 #define RCC_MC_APB3ENCLRR_LPTIM2EN            B(0)
23006 #define RCC_MC_APB3ENCLRR_LPTIM3EN            B(1)
23007 #define RCC_MC_APB3ENCLRR_LPTIM4EN            B(2)
23008 #define RCC_MC_APB3ENCLRR_LPTIM5EN            B(3)
23009 #define RCC_MC_APB3ENCLRR_SAI4EN              B(8)
23010 #define RCC_MC_APB3ENCLRR_SYSCFGEN            B(11)
23011 #define RCC_MC_APB3ENCLRR_VREFEN              B(13)
23012 #define RCC_MC_APB3ENCLRR_DTSEN               B(16)
23013 #define RCC_MC_APB3ENCLRR_PMBCTRLEN           B(17)
23014 #define RCC_MC_APB3ENCLRR_HDPEN               B(20)
23015 
23016 /*******************  Bit definition for RCC_MC_APB4ENSETR register  ***********/
23017 /*!<  This register is used to set the peripheral clock enable bit of the corresponding
23018  * peripheral to 1.  It shall be used to allocate a peripheral to the MCU. */
23019 #define RCC_MC_APB4ENSETR_LTDCEN              B(0)
23020 #define RCC_MC_APB4ENSETR_DSIEN               B(4)
23021 #define RCC_MC_APB4ENSETR_DDRPERFMEN          B(8)
23022 #define RCC_MC_APB4ENSETR_USBPHYEN            B(16)
23023 #define RCC_MC_APB4ENSETR_STGENROEN           B(20)
23024 
23025 /*******************  Bit definition for RCC_MP_APB4ENSETR register  ***********/
23026 /*!<  This register is used to set the peripheral clock enable bit of the corresponding
23027  * peripheral to 1.  It shall be used to allocate a peripheral to the MPU. */
23028 #define RCC_MP_APB4ENSETR_LTDCEN              B(0)
23029 #define RCC_MP_APB4ENSETR_DSIEN               B(4)
23030 #define RCC_MP_APB4ENSETR_IWDG2APBEN          B(15)
23031 #define RCC_MP_APB4ENSETR_USBPHYEN            B(16)
23032 #define RCC_MP_APB4ENSETR_STGENROEN           B(20)
23033 
23034 /*******************  Bit definition for RCC_MC_APB4ENCLRR register  ************/
23035 /*!< This register is used to clear the peripheral clock enable bit of the corresponding
23036  * peripheral. It shall be used to deallocate a peripheral from MCU */
23037 #define RCC_MC_APB4ENCLRR_LTDCEN              B(0)
23038 #define RCC_MC_APB4ENCLRR_DSIEN               B(4)
23039 #define RCC_MC_APB4ENCLRR_USBPHYEN            B(16)
23040 #define RCC_MC_APB4ENCLRR_STGENROEN           B(20)
23041 
23042 /*******************  Bit definition for RCC_MP_APB4ENCLRR register  ************/
23043 /*!< This register is used to clear the peripheral clock enable bit of the corresponding
23044  * peripheral. It shall be used to deallocate a peripheral from MCU */
23045 #define RCC_MP_APB4ENCLRR_LTDCEN              B(0)
23046 #define RCC_MP_APB4ENCLRR_DSIEN               B(4)
23047 #define RCC_MP_APB4ENCLRR_IWDG2APBEN          B(15)
23048 #define RCC_MP_APB4ENCLRR_USBPHYEN            B(16)
23049 #define RCC_MP_APB4ENCLRR_STGENROEN           B(20)
23050 
23051 /*******************  Bit definition for RCC_MC_APB5ENSETR register  ***********/
23052 /*!<  This register is used to set the peripheral clock enable bit of the corresponding
23053  * peripheral to 1.  It shall be used to allocate a peripheral to the MCU. */
23054 #define RCC_MC_APB5ENSETR_SPI6EN              B(0)
23055 #define RCC_MC_APB5ENSETR_I2C4EN              B(2)
23056 #define RCC_MC_APB5ENSETR_I2C6EN              B(3)
23057 #define RCC_MC_APB5ENSETR_USART1EN            B(4)
23058 #define RCC_MC_APB5ENSETR_RTCAPBEN            B(8)
23059 #define RCC_MC_APB5ENSETR_TZC1EN              B(11)
23060 #define RCC_MC_APB5ENSETR_TZC2EN              B(12)
23061 #define RCC_MC_APB5ENSETR_TZPCEN              B(13)
23062 #define RCC_MC_APB5ENSETR_BSECEN              B(16)
23063 #define RCC_MC_APB5ENSETR_STGENEN             B(20)
23064 
23065 /*******************  Bit definition for RCC_MP_APB5ENSETR register  ***********/
23066 /*!<  This register is used to set the peripheral clock enable bit of the corresponding
23067  * peripheral to 1.  It shall be used to allocate a peripheral to the MPU.
23068  * This bit can also be used to test if IWDG1 peripheral clock is enabled
23069  * If TZEN = 1, this register can only be modified in secure mode. */
23070 #define RCC_MP_APB5ENSETR_IWDG1APBEN          B(15)
23071 
23072 /*******************  Bit definition for RCC_MC_APB5ENCLRR register  ************/
23073 /*!< This register is used to clear the peripheral clock enable bit of the corresponding
23074  * peripheral. It shall be used to deallocate a peripheral from MCU */
23075 #define RCC_MC_APB5ENCLRR_SPI6EN              B(0)
23076 #define RCC_MC_APB5ENCLRR_I2C4EN              B(2)
23077 #define RCC_MC_APB5ENCLRR_I2C6EN              B(3)
23078 #define RCC_MC_APB5ENCLRR_USART1EN            B(4)
23079 #define RCC_MC_APB5ENCLRR_RTCAPBEN            B(8)
23080 #define RCC_MC_APB5ENCLRR_TZC1EN              B(11)
23081 #define RCC_MC_APB5ENCLRR_TZC2EN              B(12)
23082 #define RCC_MC_APB5ENCLRR_TZPCEN              B(13)
23083 #define RCC_MC_APB5ENCLRR_BSECEN              B(16)
23084 #define RCC_MC_APB5ENCLRR_STGENEN             B(20)
23085 
23086 /*******************  Bit definition for RCC_MC_AHB5ENSETR register  ***********/
23087 /*!<  This register is used to set the peripheral clock enable bit of the corresponding
23088  * peripheral to 1.  It shall be used to allocate a peripheral to the MCU. */
23089 #define RCC_MC_AHB5ENSETR_GPIOZEN             B(0)
23090 #define RCC_MC_AHB5ENSETR_HASH1EN             B(5)
23091 #define RCC_MC_AHB5ENSETR_RNG1EN              B(6)
23092 #define RCC_MC_AHB5ENSETR_BKPSRAMEN           B(8)
23093 #define RCC_MC_AHB5ENSETR_AXIMC               B(16)
23094 
23095 /*******************  Bit definition for RCC_MC_AHB5ENCLRR register  ************/
23096 /*!< This register is used to clear the peripheral clock enable bit of the corresponding
23097  * peripheral. It shall be used to deallocate a peripheral from MCU */
23098 #define RCC_MC_AHB5ENCLRR_GPIOZEN             B(0)
23099 #define RCC_MC_AHB5ENCLRR_HASH1EN             B(5)
23100 #define RCC_MC_AHB5ENCLRR_RNG1EN              B(6)
23101 #define RCC_MC_AHB5ENCLRR_BKPSRAMEN           B(8)
23102 
23103 /*******************  Bit definition for RCC_MC_AHB6ENSETR register  ***********/
23104 /*!<  This register is used to set the peripheral clock enable bit of the corresponding
23105  * peripheral to 1.  It shall be used to allocate a peripheral to the MCU. */
23106 #define RCC_MC_AHB6ENSETR_MDMAEN              B(0)
23107 #define RCC_MC_AHB6ENSETR_GPUEN               B(5)
23108 #define RCC_MC_AHB6ENSETR_ETHCKEN             B(7)
23109 #define RCC_MC_AHB6ENSETR_ETHTXEN             B(8)
23110 #define RCC_MC_AHB6ENSETR_ETHRXEN             B(9)
23111 #define RCC_MC_AHB6ENSETR_ETHMACEN            B(10)
23112 #define RCC_MC_AHB6ENSETR_FMCEN               B(12)
23113 #define RCC_MC_AHB6ENSETR_QSPIEN              B(14)
23114 #define RCC_MC_AHB6ENSETR_SDMMC1EN            B(16)
23115 #define RCC_MC_AHB6ENSETR_SDMMC2EN            B(17)
23116 #define RCC_MC_AHB6ENSETR_CRC1EN              B(20)
23117 #define RCC_MC_AHB6ENSETR_USBHEN              B(24)
23118 
23119 /*******************  Bit definition for RCC_MC_AHB6ENCLRR register  ************/
23120 /*!< This register is used to clear the peripheral clock enable bit of the corresponding
23121  * peripheral. It shall be used to deallocate a peripheral from MCU */
23122 #define RCC_MC_AHB6ENCLRR_MDMAEN              B(0)
23123 #define RCC_MC_AHB6ENCLRR_GPUEN               B(5)
23124 #define RCC_MC_AHB6ENCLRR_ETHCKEN             B(7)
23125 #define RCC_MC_AHB6ENCLRR_ETHTXEN             B(8)
23126 #define RCC_MC_AHB6ENCLRR_ETHRXEN             B(9)
23127 #define RCC_MC_AHB6ENCLRR_ETHMACEN            B(10)
23128 #define RCC_MC_AHB6ENCLRR_FMCEN               B(12)
23129 #define RCC_MC_AHB6ENCLRR_QSPIEN              B(14)
23130 #define RCC_MC_AHB6ENCLRR_SDMMC1EN            B(16)
23131 #define RCC_MC_AHB6ENCLRR_SDMMC2EN            B(17)
23132 #define RCC_MC_AHB6ENCLRR_CRC1EN              B(20)
23133 #define RCC_MC_AHB6ENCLRR_USBHEN              B(24)
23134 
23135 /*******************  Bit definition for RCC_MP_TZAHB6ENSETR register  ***********/
23136 /*!<  This register is used to set the peripheral clock enable bit of the corresponding
23137  * peripheral to 1.  It shall be used to allocate a peripheral to the MPU. */
23138 #define RCC_MP_TZAHB6ENSETR_MDMAEN            B(0)
23139 
23140 /*******************  Bit definition for RCC_MP_TZAHB6ENCLRR register  ************/
23141 /*!< This register is used to clear the peripheral clock enable bit of the corresponding
23142  * peripheral. It shall be used to deallocate a peripheral from MPU */
23143 #define RCC_MP_TZAHB6ENCLRR_MDMAEN            B(0)
23144 
23145 /*******************  Bit definition for RCC_MC_AHB2ENSETR register  ***********/
23146 /*!<  This register is used to set the peripheral clock enable bit of the corresponding
23147  * peripheral to 1.  It shall be used to allocate a peripheral to the MCU. */
23148 #define RCC_MC_AHB2ENSETR_DMA1EN              B(0)
23149 #define RCC_MC_AHB2ENSETR_DMA2EN              B(1)
23150 #define RCC_MC_AHB2ENSETR_DMAMUXEN            B(2)
23151 #define RCC_MC_AHB2ENSETR_ADC12EN             B(5)
23152 #define RCC_MC_AHB2ENSETR_USBOEN              B(8)
23153 #define RCC_MC_AHB2ENSETR_SDMMC3EN            B(16)
23154 
23155 /*******************  Bit definition for RCC_MC_AHB2ENCLRR register  ************/
23156 /*!< This register is used to clear the peripheral clock enable bit of the corresponding
23157  * peripheral. It shall be used to deallocate a peripheral from MCU */
23158 #define RCC_MC_AHB2ENCLRR_DMA1EN              B(0)
23159 #define RCC_MC_AHB2ENCLRR_DMA2EN              B(1)
23160 #define RCC_MC_AHB2ENCLRR_DMAMUXEN            B(2)
23161 #define RCC_MC_AHB2ENCLRR_ADC12EN             B(5)
23162 #define RCC_MC_AHB2ENCLRR_USBOEN              B(8)
23163 #define RCC_MC_AHB2ENCLRR_SDMMC3EN            B(16)
23164 
23165 /*******************  Bit definition for RCC_MC_AHB3ENSETR register  ***********/
23166 /*!<  This register is used to set the peripheral clock enable bit of the corresponding
23167  * peripheral to 1.  It shall be used to allocate a peripheral to the MCU. */
23168 #define RCC_MC_AHB3ENSETR_DCMIEN              B(0)
23169 #define RCC_MC_AHB3ENSETR_HASH2EN             B(5)
23170 #define RCC_MC_AHB3ENSETR_RNG2EN              B(6)
23171 #define RCC_MC_AHB3ENSETR_CRC2EN              B(7)
23172 #define RCC_MC_AHB3ENSETR_HSEMEN              B(11)
23173 #define RCC_MC_AHB3ENSETR_IPCCEN              B(12)
23174 
23175 /*******************  Bit definition for RCC_MC_AHB3ENCLRR register  ************/
23176 /*!< This register is used to clear the peripheral clock enable bit of the corresponding
23177  * peripheral. It shall be used to deallocate a peripheral from MCU */
23178 #define RCC_MC_AHB3ENCLRR_DCMIEN              B(0)
23179 #define RCC_MC_AHB3ENCLRR_HASH2EN             B(5)
23180 #define RCC_MC_AHB3ENCLRR_RNG2EN              B(6)
23181 #define RCC_MC_AHB3ENCLRR_CRC2EN              B(7)
23182 #define RCC_MC_AHB3ENCLRR_HSEMEN              B(11)
23183 #define RCC_MC_AHB3ENCLRR_IPCCEN              B(12)
23184 
23185 /*******************  Bit definition for RCC_MC_AHB4ENSETR register  ***********/
23186 /*!<  This register is used to set the peripheral clock enable bit of the corresponding
23187  * peripheral to 1.  It shall be used to allocate a peripheral to the MCU. */
23188 #define RCC_MC_AHB4ENSETR_GPIOAEN             B(0)
23189 #define RCC_MC_AHB4ENSETR_GPIOBEN             B(1)
23190 #define RCC_MC_AHB4ENSETR_GPIOCEN             B(2)
23191 #define RCC_MC_AHB4ENSETR_GPIODEN             B(3)
23192 #define RCC_MC_AHB4ENSETR_GPIOEEN             B(4)
23193 #define RCC_MC_AHB4ENSETR_GPIOFEN             B(5)
23194 #define RCC_MC_AHB4ENSETR_GPIOGEN             B(6)
23195 #define RCC_MC_AHB4ENSETR_GPIOHEN             B(7)
23196 #define RCC_MC_AHB4ENSETR_GPIOIEN             B(8)
23197 #define RCC_MC_AHB4ENSETR_GPIOJEN             B(9)
23198 #define RCC_MC_AHB4ENSETR_GPIOKEN             B(10)
23199 
23200 /*******************  Bit definition for RCC_MC_AHB4ENCLRR register  ************/
23201 /*!< This register is used to clear the peripheral clock enable bit of the corresponding
23202  * peripheral. It shall be used to deallocate a peripheral from MCU */
23203 #define RCC_MC_AHB4ENCLRR_GPIOAEN             B(0)
23204 #define RCC_MC_AHB4ENCLRR_GPIOBEN             B(1)
23205 #define RCC_MC_AHB4ENCLRR_GPIOCEN             B(2)
23206 #define RCC_MC_AHB4ENCLRR_GPIODEN             B(3)
23207 #define RCC_MC_AHB4ENCLRR_GPIOEEN             B(4)
23208 #define RCC_MC_AHB4ENCLRR_GPIOFEN             B(5)
23209 #define RCC_MC_AHB4ENCLRR_GPIOGEN             B(6)
23210 #define RCC_MC_AHB4ENCLRR_GPIOHEN             B(7)
23211 #define RCC_MC_AHB4ENCLRR_GPIOIEN             B(8)
23212 #define RCC_MC_AHB4ENCLRR_GPIOJEN             B(9)
23213 #define RCC_MC_AHB4ENCLRR_GPIOKEN             B(10)
23214 
23215 /*******************  Bit definition for RCC_MC_AXIMENSETR register  ***********/
23216 /*!<  This register is used to set the peripheral clock enable bit of the corresponding
23217  * peripheral to 1.  It shall be used to allocate a peripheral to the MCU. */
23218 #define RCC_MC_AXIMENSETR_SYSRAMEN            B(0)
23219 
23220 /*******************  Bit definition for RCC_MC_AXIMENCLRR register  ************/
23221 /*!< This register is used to clear the peripheral clock enable bit of the corresponding
23222  * peripheral. It shall be used to deallocate a peripheral from MCU */
23223 #define RCC_MC_AXIMENCLRR_SYSRAMEN            B(0)
23224 
23225 /*******************  Bit definition for RCC_MC_MLAHBENSETR register  ***********/
23226 /*!<  This register is used to set the peripheral clock enable bit of the corresponding
23227  * peripheral to 1.  It shall be used to allocate a peripheral to the MCU. */
23228 #define RCC_MC_MLAHBENSETR_RETRAMEN           B(4)
23229 
23230 /*******************  Bit definition for RCC_MC_MLAHBENCLRR register  ************/
23231 /*!< This register is used to clear the peripheral clock enable bit of the corresponding
23232  * peripheral. It shall be used to deallocate a peripheral from MCU */
23233 #define RCC_MC_MLAHBENCLRR_RETRAMEN           B(4)
23234 
23235 
23236 /*******************  Bit definition for RCC_MC_APB1LPENSETR register  ***********/
23237 /*!<  This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
23238  * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
23239  * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
23240 #define RCC_MC_APB1LPENSETR_TIM2LPEN              B(0)
23241 #define RCC_MC_APB1LPENSETR_TIM3LPEN              B(1)
23242 #define RCC_MC_APB1LPENSETR_TIM4LPEN              B(2)
23243 #define RCC_MC_APB1LPENSETR_TIM5LPEN              B(3)
23244 #define RCC_MC_APB1LPENSETR_TIM6LPEN              B(4)
23245 #define RCC_MC_APB1LPENSETR_TIM7LPEN              B(5)
23246 #define RCC_MC_APB1LPENSETR_TIM12LPEN             B(6)
23247 #define RCC_MC_APB1LPENSETR_TIM13LPEN             B(7)
23248 #define RCC_MC_APB1LPENSETR_TIM14LPEN             B(8)
23249 #define RCC_MC_APB1LPENSETR_LPTIM1LPEN            B(9)
23250 #define RCC_MC_APB1LPENSETR_SPI2LPEN              B(11)
23251 #define RCC_MC_APB1LPENSETR_SPI3LPEN              B(12)
23252 #define RCC_MC_APB1LPENSETR_USART2LPEN            B(14)
23253 #define RCC_MC_APB1LPENSETR_USART3LPEN            B(15)
23254 #define RCC_MC_APB1LPENSETR_UART4LPEN             B(16)
23255 #define RCC_MC_APB1LPENSETR_UART5LPEN             B(17)
23256 #define RCC_MC_APB1LPENSETR_UART7LPEN             B(18)
23257 #define RCC_MC_APB1LPENSETR_UART8LPEN             B(19)
23258 #define RCC_MC_APB1LPENSETR_I2C1LPEN              B(21)
23259 #define RCC_MC_APB1LPENSETR_I2C2LPEN              B(22)
23260 #define RCC_MC_APB1LPENSETR_I2C3LPEN              B(23)
23261 #define RCC_MC_APB1LPENSETR_I2C5LPEN              B(24)
23262 #define RCC_MC_APB1LPENSETR_SPDIFLPEN             B(26)
23263 #define RCC_MC_APB1LPENSETR_CECLPEN               B(27)
23264 #define RCC_MC_APB1LPENSETR_WWDG1LPEN             B(28)
23265 #define RCC_MC_APB1LPENSETR_DAC12LPEN             B(29)
23266 #define RCC_MC_APB1LPENSETR_MDIOSLPEN             B(31)
23267 
23268 /*******************  Bit definition for RCC_MC_APB1LPENCLRR register  ************/
23269 /*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
23270  * peripheral. Writing '0' has no effect, reading will return the effective values of the
23271  * corresponding bits. Writing a '1' sets the corresponding bit to '0' */
23272 #define RCC_MC_APB1LPENCLRR_TIM2LPEN              B(0)
23273 #define RCC_MC_APB1LPENCLRR_TIM3LPEN              B(1)
23274 #define RCC_MC_APB1LPENCLRR_TIM4LPEN              B(2)
23275 #define RCC_MC_APB1LPENCLRR_TIM5LPEN              B(3)
23276 #define RCC_MC_APB1LPENCLRR_TIM6LPEN              B(4)
23277 #define RCC_MC_APB1LPENCLRR_TIM7LPEN              B(5)
23278 #define RCC_MC_APB1LPENCLRR_TIM12LPEN             B(6)
23279 #define RCC_MC_APB1LPENCLRR_TIM13LPEN             B(7)
23280 #define RCC_MC_APB1LPENCLRR_TIM14LPEN             B(8)
23281 #define RCC_MC_APB1LPENCLRR_LPTIM1LPEN            B(9)
23282 #define RCC_MC_APB1LPENCLRR_SPI2LPEN              B(11)
23283 #define RCC_MC_APB1LPENCLRR_SPI3LPEN              B(12)
23284 #define RCC_MC_APB1LPENCLRR_USART2LPEN            B(14)
23285 #define RCC_MC_APB1LPENCLRR_USART3LPEN            B(15)
23286 #define RCC_MC_APB1LPENCLRR_UART4LPEN             B(16)
23287 #define RCC_MC_APB1LPENCLRR_UART5LPEN             B(17)
23288 #define RCC_MC_APB1LPENCLRR_UART7LPEN             B(18)
23289 #define RCC_MC_APB1LPENCLRR_UART8LPEN             B(19)
23290 #define RCC_MC_APB1LPENCLRR_I2C1LPEN              B(21)
23291 #define RCC_MC_APB1LPENCLRR_I2C2LPEN              B(22)
23292 #define RCC_MC_APB1LPENCLRR_I2C3LPEN              B(23)
23293 #define RCC_MC_APB1LPENCLRR_I2C5LPEN              B(24)
23294 #define RCC_MC_APB1LPENCLRR_SPDIFLPEN             B(26)
23295 #define RCC_MC_APB1LPENCLRR_CECLPEN               B(27)
23296 #define RCC_MC_APB1LPENCLRR_WWDG1LPEN             B(28)
23297 #define RCC_MC_APB1LPENCLRR_DAC12LPEN             B(29)
23298 #define RCC_MC_APB1LPENCLRR_MDIOSLPEN             B(31)
23299 
23300 /*******************  Bit definition for RCC_MC_APB2LPENSETR register  ***********/
23301 /*!<  This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
23302  * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
23303  * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
23304 #define RCC_MC_APB2LPENSETR_TIM1LPEN              B(0)
23305 #define RCC_MC_APB2LPENSETR_TIM8LPEN              B(1)
23306 #define RCC_MC_APB2LPENSETR_TIM15LPEN             B(2)
23307 #define RCC_MC_APB2LPENSETR_TIM16LPEN             B(3)
23308 #define RCC_MC_APB2LPENSETR_TIM17LPEN             B(4)
23309 #define RCC_MC_APB2LPENSETR_SPI1LPEN              B(8)
23310 #define RCC_MC_APB2LPENSETR_SPI4LPEN              B(9)
23311 #define RCC_MC_APB2LPENSETR_SPI5LPEN              B(10)
23312 #define RCC_MC_APB2LPENSETR_USART6LPEN            B(13)
23313 #define RCC_MC_APB2LPENSETR_SAI1LPEN              B(16)
23314 #define RCC_MC_APB2LPENSETR_SAI2LPEN              B(17)
23315 #define RCC_MC_APB2LPENSETR_SAI3LPEN              B(18)
23316 #define RCC_MC_APB2LPENSETR_DFSDMLPEN             B(20)
23317 #define RCC_MC_APB2LPENSETR_ADFSDMLPEN            B(21)
23318 #define RCC_MC_APB2LPENSETR_FDCANLPEN             B(24)
23319 
23320 /*******************  Bit definition for RCC_MC_APB2LPENCLRR register  ************/
23321 /*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
23322  * peripheral. Writing '0' has no effect, reading will return the effective values of the
23323  * corresponding bits. Writing a '1' sets the corresponding bit to '0' */
23324 #define RCC_MC_APB2LPENCLRR_TIM1LPEN              B(0)
23325 #define RCC_MC_APB2LPENCLRR_TIM8LPEN              B(1)
23326 #define RCC_MC_APB2LPENCLRR_TIM15LPEN             B(2)
23327 #define RCC_MC_APB2LPENCLRR_TIM16LPEN             B(3)
23328 #define RCC_MC_APB2LPENCLRR_TIM17LPEN             B(4)
23329 #define RCC_MC_APB2LPENCLRR_SPI1LPEN              B(8)
23330 #define RCC_MC_APB2LPENCLRR_SPI4LPEN              B(9)
23331 #define RCC_MC_APB2LPENCLRR_SPI5LPEN              B(10)
23332 #define RCC_MC_APB2LPENCLRR_USART6LPEN            B(13)
23333 #define RCC_MC_APB2LPENCLRR_SAI1LPEN              B(16)
23334 #define RCC_MC_APB2LPENCLRR_SAI2LPEN              B(17)
23335 #define RCC_MC_APB2LPENCLRR_SAI3LPEN              B(18)
23336 #define RCC_MC_APB2LPENCLRR_DFSDMLPEN             B(20)
23337 #define RCC_MC_APB2LPENCLRR_ADFSDMLPEN            B(21)
23338 #define RCC_MC_APB2LPENCLRR_FDCANLPEN             B(24)
23339 
23340 /*******************  Bit definition for RCC_MC_APB3LPENSETR register  ***********/
23341 /*!<  This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
23342  * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
23343  * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
23344 #define RCC_MC_APB3LPENSETR_LPTIM2LPEN            B(0)
23345 #define RCC_MC_APB3LPENSETR_LPTIM3LPEN            B(1)
23346 #define RCC_MC_APB3LPENSETR_LPTIM4LPEN            B(2)
23347 #define RCC_MC_APB3LPENSETR_LPTIM5LPEN            B(3)
23348 #define RCC_MC_APB3LPENSETR_SAI4LPEN              B(8)
23349 #define RCC_MC_APB3LPENSETR_SYSCFGLPEN            B(11)
23350 #define RCC_MC_APB3LPENSETR_VREFLPEN              B(13)
23351 #define RCC_MC_APB3LPENSETR_DTSLPEN               B(16)
23352 #define RCC_MC_APB3LPENSETR_PMBCTRLLPEN           B(17)
23353 
23354 /*******************  Bit definition for RCC_MC_APB3LPENCLRR register  ************/
23355 /*!<  This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
23356  * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
23357  * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
23358 #define RCC_MC_APB3LPENCLRR_LPTIM2LPEN            B(0)
23359 #define RCC_MC_APB3LPENCLRR_LPTIM3LPEN            B(1)
23360 #define RCC_MC_APB3LPENCLRR_LPTIM4LPEN            B(2)
23361 #define RCC_MC_APB3LPENCLRR_LPTIM5LPEN            B(3)
23362 #define RCC_MC_APB3LPENCLRR_SAI4LPEN              B(8)
23363 #define RCC_MC_APB3LPENCLRR_SYSCFGLPEN            B(11)
23364 #define RCC_MC_APB3LPENCLRR_VREFLPEN              B(13)
23365 #define RCC_MC_APB3LPENCLRR_DTSLPEN               B(16)
23366 #define RCC_MC_APB3LPENCLRR_PMBCTRLLPEN           B(17)
23367 
23368 /*******************  Bit definition for RCC_MC_APB4LPENSETR register  ***********/
23369 /*!<  This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
23370  * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
23371  * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
23372 #define RCC_MC_APB4LPENSETR_LTDCLPEN              B(0)
23373 #define RCC_MC_APB4LPENSETR_DSILPEN               B(4)
23374 #define RCC_MC_APB4LPENSETR_USBPHYLPEN            B(16)
23375 #define RCC_MC_APB4LPENSETR_STGENROLPEN           B(20)
23376 #define RCC_MC_APB4LPENSETR_STGENROSTPEN          B(21)
23377 
23378 /*******************  Bit definition for RCC_MP_APB4LPENSETR register  ***********/
23379 /*!<  This register is used by the MPU in order to set the PERxLPEN bit of the corresponding
23380  * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
23381  * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
23382 #define RCC_MP_APB4LPENSETR_LTDCLPEN              B(0)
23383 #define RCC_MP_APB4LPENSETR_DSILPEN               B(4)
23384 #define RCC_MP_APB4LPENSETR_IWDG2APBLPEN          B(15)
23385 #define RCC_MP_APB4LPENSETR_USBPHYLPEN            B(16)
23386 #define RCC_MP_APB4LPENSETR_STGENROLPEN           B(20)
23387 #define RCC_MP_APB4LPENSETR_STGENROSTPEN          B(21)
23388 
23389 /*******************  Bit definition for RCC_MC_APB4LPENCLRR register  ************/
23390 /*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
23391  * peripheral. Writing '0' has no effect, reading will return the effective values of the
23392  * corresponding bits. Writing a '1' sets the corresponding bit to '0' */
23393 #define RCC_MC_APB4LPENCLRR_LTDCLPEN              B(0)
23394 #define RCC_MC_APB4LPENCLRR_DSILPEN               B(4)
23395 #define RCC_MC_APB4LPENCLRR_USBPHYLPEN            B(16)
23396 #define RCC_MC_APB4LPENCLRR_STGENROLPEN           B(20)
23397 #define RCC_MC_APB4LPENCLRR_STGENROSTPEN          B(21)
23398 
23399 /*******************  Bit definition for RCC_MP_APB4LPENCLRR register  ************/
23400 /*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
23401  * peripheral. Writing '0' has no effect, reading will return the effective values of the
23402  * corresponding bits. Writing a '1' sets the corresponding bit to '0' */
23403 #define RCC_MP_APB4LPENCLRR_LTDCLPEN              B(0)
23404 #define RCC_MP_APB4LPENCLRR_DSILPEN               B(4)
23405 #define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN          B(15)
23406 #define RCC_MP_APB4LPENCLRR_USBPHYLPEN            B(16)
23407 #define RCC_MP_APB4LPENCLRR_STGENROLPEN           B(20)
23408 #define RCC_MP_APB4LPENCLRR_STGENROSTPEN          B(21)
23409 
23410 /*******************  Bit definition for RCC_MC_APB5LPENSETR register  ***********/
23411 /*!<  This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
23412  * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
23413  * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
23414 #define RCC_MC_APB5LPENSETR_SPI6LPEN              B(0)
23415 #define RCC_MC_APB5LPENSETR_I2C4LPEN              B(2)
23416 #define RCC_MC_APB5LPENSETR_I2C6LPEN              B(3)
23417 #define RCC_MC_APB5LPENSETR_USART1LPEN            B(4)
23418 #define RCC_MC_APB5LPENSETR_RTCAPBLPEN            B(8)
23419 #define RCC_MC_APB5LPENSETR_TZC1LPEN              B(11)
23420 #define RCC_MC_APB5LPENSETR_TZC2LPEN              B(12)
23421 #define RCC_MC_APB5LPENSETR_TZPCLPEN              B(13)
23422 #define RCC_MC_APB5LPENSETR_BSECLPEN              B(16)
23423 #define RCC_MC_APB5LPENSETR_STGENLPEN             B(20)
23424 #define RCC_MC_APB5LPENSETR_STGENSTPEN            B(21)
23425 
23426 
23427 /*******************  Bit definition for RCC_MC_APB5LPENCLRR register  ************/
23428 /*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
23429  * peripheral. Writing '0' has no effect, reading will return the effective values of the
23430  * corresponding bits. Writing a '1' sets the corresponding bit to '0' */
23431 #define RCC_MC_APB5LPENCLRR_SPI6LPEN              B(0)
23432 #define RCC_MC_APB5LPENCLRR_I2C4LPEN              B(2)
23433 #define RCC_MC_APB5LPENCLRR_I2C6LPEN              B(3)
23434 #define RCC_MC_APB5LPENCLRR_USART1LPEN            B(4)
23435 #define RCC_MC_APB5LPENCLRR_RTCAPBLPEN            B(8)
23436 #define RCC_MC_APB5LPENCLRR_TZC1LPEN              B(11)
23437 #define RCC_MC_APB5LPENCLRR_TZC2LPEN              B(12)
23438 #define RCC_MC_APB5LPENCLRR_TZPCLPEN              B(13)
23439 #define RCC_MC_APB5LPENCLRR_BSECLPEN              B(16)
23440 #define RCC_MC_APB5LPENCLRR_STGENLPEN             B(20)
23441 #define RCC_MC_APB5LPENCLRR_STGENSTPEN            B(21)
23442 
23443 /*******************  Bit definition for RCC_MC_AHB5LPENSETR register  ***********/
23444 /*!<  This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
23445  * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
23446  * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
23447 #define RCC_MC_AHB5LPENSETR_GPIOZLPEN             B(0)
23448 #define RCC_MC_AHB5LPENSETR_HASH1LPEN             B(5)
23449 #define RCC_MC_AHB5LPENSETR_RNG1LPEN              B(6)
23450 #define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN           B(8)
23451 
23452 /*******************  Bit definition for RCC_MC_AHB5LPENCLRR register  ************/
23453 /*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
23454  * peripheral. Writing '0' has no effect, reading will return the effective values of the
23455  * corresponding bits. Writing a '1' sets the corresponding bit to '0' */
23456 #define RCC_MC_AHB5LPENCLRR_GPIOZLPEN             B(0)
23457 #define RCC_MC_AHB5LPENCLRR_HASH1LPEN             B(5)
23458 #define RCC_MC_AHB5LPENCLRR_RNG1LPEN              B(6)
23459 #define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN           B(8)
23460 
23461 /*******************  Bit definition for RCC_MC_AHB6LPENSETR register  ***********/
23462 /*!<  This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
23463  * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
23464  * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
23465 #define RCC_MC_AHB6LPENSETR_MDMALPEN              B(0)
23466 #define RCC_MC_AHB6LPENSETR_GPULPEN               B(5)
23467 #define RCC_MC_AHB6LPENSETR_ETHCKLPEN             B(7)
23468 #define RCC_MC_AHB6LPENSETR_ETHTXLPEN             B(8)
23469 #define RCC_MC_AHB6LPENSETR_ETHRXLPEN             B(9)
23470 #define RCC_MC_AHB6LPENSETR_ETHMACLPEN            B(10)
23471 #define RCC_MC_AHB6LPENSETR_ETHSTPEN              B(11)
23472 #define RCC_MC_AHB6LPENSETR_FMCLPEN               B(12)
23473 #define RCC_MC_AHB6LPENSETR_QSPILPEN              B(14)
23474 #define RCC_MC_AHB6LPENSETR_SDMMC1LPEN            B(16)
23475 #define RCC_MC_AHB6LPENSETR_SDMMC2LPEN            B(17)
23476 #define RCC_MC_AHB6LPENSETR_CRC1LPEN              B(20)
23477 #define RCC_MC_AHB6LPENSETR_USBHLPEN              B(24)
23478 
23479 /*******************  Bit definition for RCC_MC_AHB6LPENCLRR register  ************/
23480 /*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
23481  * peripheral. Writing '0' has no effect, reading will return the effective values of the
23482  * corresponding bits. Writing a '1' sets the corresponding bit to '0' */
23483 #define RCC_MC_AHB6LPENCLRR_MDMALPEN              B(0)
23484 #define RCC_MC_AHB6LPENCLRR_GPULPEN               B(5)
23485 #define RCC_MC_AHB6LPENCLRR_ETHCKLPEN             B(7)
23486 #define RCC_MC_AHB6LPENCLRR_ETHTXLPEN             B(8)
23487 #define RCC_MC_AHB6LPENCLRR_ETHRXLPEN             B(9)
23488 #define RCC_MC_AHB6LPENCLRR_ETHMACLPEN            B(10)
23489 #define RCC_MC_AHB6LPENCLRR_ETHSTPEN              B(11)
23490 #define RCC_MC_AHB6LPENCLRR_FMCLPEN               B(12)
23491 #define RCC_MC_AHB6LPENCLRR_QSPILPEN              B(14)
23492 #define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN            B(16)
23493 #define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN            B(17)
23494 #define RCC_MC_AHB6LPENCLRR_CRC1LPEN              B(20)
23495 #define RCC_MC_AHB6LPENCLRR_USBHLPEN              B(24)
23496 
23497 /*******************  Bit definition for RCC_MP_TZAHB6LPENSETR register  ***********/
23498 /*!<  This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
23499  * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
23500  * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
23501 #define RCC_MP_TZAHB6LPENSETR_MDMALPEN            B(0)
23502 
23503 /*******************  Bit definition for RCC_MP_TZAHB6LPENCLRR register  ************/
23504 /*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
23505  * peripheral. Writing '0' has no effect, reading will return the effective values of the
23506  * corresponding bits. Writing a '1' sets the corresponding bit to '0' */
23507 #define RCC_MC_TZAHB6LPENCLRR_MDMALPEN            B(0)
23508 
23509 /*******************  Bit definition for RCC_MC_AHB2LPENSETR register  ***********/
23510 /*!<  This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
23511  * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
23512  * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
23513 #define RCC_MC_AHB2LPENSETR_DMA1LPEN              B(0)
23514 #define RCC_MC_AHB2LPENSETR_DMA2LPEN              B(1)
23515 #define RCC_MC_AHB2LPENSETR_DMAMUXLPEN            B(2)
23516 #define RCC_MC_AHB2LPENSETR_ADC12LPEN             B(5)
23517 #define RCC_MC_AHB2LPENSETR_USBOLPEN              B(8)
23518 #define RCC_MC_AHB2LPENSETR_SDMMC3LPEN            B(16)
23519 
23520 /*******************  Bit definition for RCC_MC_AHB2LPENCLRR register  ************/
23521 /*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
23522  * peripheral. Writing '0' has no effect, reading will return the effective values of the
23523  * corresponding bits. Writing a '1' sets the corresponding bit to '0' */
23524 #define RCC_MC_AHB2LPENCLRR_DMA1LPEN              B(0)
23525 #define RCC_MC_AHB2LPENCLRR_DMA2LPEN              B(1)
23526 #define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN            B(2)
23527 #define RCC_MC_AHB2LPENCLRR_ADC12LPEN             B(5)
23528 #define RCC_MC_AHB2LPENCLRR_USBOLPEN              B(8)
23529 #define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN            B(16)
23530 
23531 /*******************  Bit definition for RCC_MC_AHB3LPENSETR register  ***********/
23532 /*!<  This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
23533  * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
23534  * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
23535 #define RCC_MC_AHB3LPENSETR_DCMILPEN              B(0)
23536 #define RCC_MC_AHB3LPENSETR_HASH2LPEN             B(5)
23537 #define RCC_MC_AHB3LPENSETR_RNG2LPEN              B(6)
23538 #define RCC_MC_AHB3LPENSETR_CRC2LPEN              B(7)
23539 #define RCC_MC_AHB3LPENSETR_HSEMLPEN              B(11)
23540 #define RCC_MC_AHB3LPENSETR_IPCCLPEN              B(12)
23541 
23542 /*******************  Bit definition for RCC_MC_AHB3LPENCLRR register  ************/
23543 /*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
23544  * peripheral. Writing '0' has no effect, reading will return the effective values of the
23545  * corresponding bits. Writing a '1' sets the corresponding bit to '0' */
23546 #define RCC_MC_AHB3LPENCLRR_DCMILPEN              B(0)
23547 #define RCC_MC_AHB3LPENCLRR_HASH2LPEN             B(5)
23548 #define RCC_MC_AHB3LPENCLRR_RNG2LPEN              B(6)
23549 #define RCC_MC_AHB3LPENCLRR_CRC2LPEN              B(7)
23550 #define RCC_MC_AHB3LPENCLRR_HSEMLPEN              B(11)
23551 #define RCC_MC_AHB3LPENCLRR_IPCCLPEN              B(12)
23552 
23553 /*******************  Bit definition for RCC_MC_AHB4LPENSETR register  ***********/
23554 /*!<  This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
23555  * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
23556  * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
23557 #define RCC_MC_AHB4LPENSETR_GPIOALPEN             B(0)
23558 #define RCC_MC_AHB4LPENSETR_GPIOBLPEN             B(1)
23559 #define RCC_MC_AHB4LPENSETR_GPIOCLPEN             B(2)
23560 #define RCC_MC_AHB4LPENSETR_GPIODLPEN             B(3)
23561 #define RCC_MC_AHB4LPENSETR_GPIOELPEN             B(4)
23562 #define RCC_MC_AHB4LPENSETR_GPIOFLPEN             B(5)
23563 #define RCC_MC_AHB4LPENSETR_GPIOGLPEN             B(6)
23564 #define RCC_MC_AHB4LPENSETR_GPIOHLPEN             B(7)
23565 #define RCC_MC_AHB4LPENSETR_GPIOILPEN             B(8)
23566 #define RCC_MC_AHB4LPENSETR_GPIOJLPEN             B(9)
23567 #define RCC_MC_AHB4LPENSETR_GPIOKLPEN             B(10)
23568 
23569 /*******************  Bit definition for RCC_MC_AHB4LPENCLRR register  ************/
23570 /*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
23571  * peripheral. Writing '0' has no effect, reading will return the effective values of the
23572  * corresponding bits. Writing a '1' sets the corresponding bit to '0' */
23573 #define RCC_MC_AHB4LPENCLRR_GPIOALPEN             B(0)
23574 #define RCC_MC_AHB4LPENCLRR_GPIOBLPEN             B(1)
23575 #define RCC_MC_AHB4LPENCLRR_GPIOCLPEN             B(2)
23576 #define RCC_MC_AHB4LPENCLRR_GPIODLPEN             B(3)
23577 #define RCC_MC_AHB4LPENCLRR_GPIOELPEN             B(4)
23578 #define RCC_MC_AHB4LPENCLRR_GPIOFLPEN             B(5)
23579 #define RCC_MC_AHB4LPENCLRR_GPIOGLPEN             B(6)
23580 #define RCC_MC_AHB4LPENCLRR_GPIOHLPEN             B(7)
23581 #define RCC_MC_AHB4LPENCLRR_GPIOILPEN             B(8)
23582 #define RCC_MC_AHB4LPENCLRR_GPIOJLPEN             B(9)
23583 #define RCC_MC_AHB4LPENCLRR_GPIOKLPEN             B(10)
23584 
23585 /*******************  Bit definition for RCC_MC_AXIMLPENSETR register  ***********/
23586 /*!<  This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
23587  * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
23588  * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
23589 #define RCC_MC_AXIMLPENSETR_SYSRAMLPEN            B(0)
23590 
23591 /*******************  Bit definition for RCC_MC_AXIMLPENCLRR register  ************/
23592 /*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
23593  * peripheral. Writing '0' has no effect, reading will return the effective values of the
23594  * corresponding bits. Writing a '1' sets the corresponding bit to '0' */
23595 #define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN            B(0)
23596 
23597 /*******************  Bit definition for RCC_MC_MLAHBLPENSETR register  ***********/
23598 /*!<  This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
23599  * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
23600  * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
23601 #define RCC_MC_MLAHBLPENSETR_SRAM1LPEN            B(0)
23602 #define RCC_MC_MLAHBLPENSETR_SRAM2LPEN            B(1)
23603 #define RCC_MC_MLAHBLPENSETR_SRAM3LPEN            B(2)
23604 #define RCC_MC_MLAHBLPENSETR_RETRAMLPEN           B(4)
23605 
23606 /*******************  Bit definition for RCC_MC_MLAHBLPENCLRR register  ************/
23607 /*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
23608  * peripheral. Writing '0' has no effect, reading will return the effective values of the
23609  * corresponding bits. Writing a '1' sets the corresponding bit to '0' */
23610 #define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN            B(0)
23611 #define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN            B(1)
23612 #define RCC_MC_MLAHBLPENCLRR_SRAM3LPEN            B(2)
23613 #define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN           B(4)
23614 
23615 
23616 /*******************  Bit definition for RCC_BR_RSTSCLRR register  ************/
23617 /*!< This register is used by the BOOTROM to check the reset source.
23618  * Writing "0" has no effect, reading will return the effective values of the corresponding
23619  * bits. Writing a '1' clears the corresponding bit to '0'
23620  *
23621  * @note In order to identify the reset source, the MPU application must use
23622  *       RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application
23623  *       must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR).
23624  * @note This register except MPUP[1:0]RSTF flags is located into VDD domain,
23625  *       and is reset by por_rst reset.
23626  * @note If TZEN = '1', this register can only be modified in secure mode.
23627  */
23628 #define RCC_BR_RSTSCLRR_PORRSTF_Pos           (0U)
23629 #define RCC_BR_RSTSCLRR_PORRSTF_Msk           (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos)   /*!< 0x00000001 */
23630 #define RCC_BR_RSTSCLRR_PORRSTF               RCC_BR_RSTSCLRR_PORRSTF_Msk             /*POR/PDR reset flag*/
23631 
23632 #define RCC_BR_RSTSCLRR_BORRSTF_Pos           (1U)
23633 #define RCC_BR_RSTSCLRR_BORRSTF_Msk           (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos)   /*!< 0x00000002 */
23634 #define RCC_BR_RSTSCLRR_BORRSTF               RCC_BR_RSTSCLRR_BORRSTF_Msk             /*BOR reset flag*/
23635 
23636 #define RCC_BR_RSTSCLRR_PADRSTF_Pos           (2U)
23637 #define RCC_BR_RSTSCLRR_PADRSTF_Msk           (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos)   /*!< 0x00000004 */
23638 #define RCC_BR_RSTSCLRR_PADRSTF               RCC_BR_RSTSCLRR_PADRSTF_Msk             /*NRST reset flag*/
23639 
23640 #define RCC_BR_RSTSCLRR_HCSSRSTF_Pos          (3U)
23641 #define RCC_BR_RSTSCLRR_HCSSRSTF_Msk          (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos)  /*!< 0x00000008 */
23642 #define RCC_BR_RSTSCLRR_HCSSRSTF              RCC_BR_RSTSCLRR_HCSSRSTF_Msk            /*HSE CSS reset flag*/
23643 
23644 #define RCC_BR_RSTSCLRR_VCORERSTF_Pos         (4U)
23645 #define RCC_BR_RSTSCLRR_VCORERSTF_Msk         (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */
23646 #define RCC_BR_RSTSCLRR_VCORERSTF             RCC_BR_RSTSCLRR_VCORERSTF_Msk           /*VDDCORE reset flag*/
23647 
23648 #define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos         (6U)
23649 #define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk         (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */
23650 #define RCC_BR_RSTSCLRR_MPSYSRSTF             RCC_BR_RSTSCLRR_MPSYSRSTF_Msk           /*MPU System reset flag*/
23651 
23652 #define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos         (7U)
23653 #define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk         (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */
23654 #define RCC_BR_RSTSCLRR_MCSYSRSTF             RCC_BR_RSTSCLRR_MCSYSRSTF_Msk           /*MCU System reset flag*/
23655 
23656 #define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos         (8U)
23657 #define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk         (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */
23658 #define RCC_BR_RSTSCLRR_IWDG1RSTF             RCC_BR_RSTSCLRR_IWDG1RSTF_Msk           /*IWDG1 reset flag*/
23659 
23660 #define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos         (9U)
23661 #define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk         (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */
23662 #define RCC_BR_RSTSCLRR_IWDG2RSTF             RCC_BR_RSTSCLRR_IWDG2RSTF_Msk           /*IWDG2 reset flag*/
23663 
23664 #define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos         (13U)
23665 #define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk         (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */
23666 #define RCC_BR_RSTSCLRR_MPUP0RSTF             RCC_BR_RSTSCLRR_MPUP0RSTF_Msk           /*MPU processor 0 reset flag*/
23667 
23668 #define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos         (14U)
23669 #define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk         (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */
23670 #define RCC_BR_RSTSCLRR_MPUP1RSTF             RCC_BR_RSTSCLRR_MPUP1RSTF_Msk           /*MPU processor 1 reset flag*/
23671 
23672 
23673 /*******************  Bit definition for RCC_MC_RSTSCLRR register  ************/
23674 /*!< This register is used by the MCU to check the reset source.
23675  * Writing "0" has no effect, reading will return the effective values of the corresponding
23676  * bits. Writing a "1" clears the corresponding bit to 0
23677  * @note This register is located into VDD domain, and is reset by rst_por reset.
23678  */
23679 #define RCC_MC_RSTSCLRR_PORRSTF_Pos           (0U)
23680 #define RCC_MC_RSTSCLRR_PORRSTF_Msk           (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos)   /*!< 0x00000001 */
23681 #define RCC_MC_RSTSCLRR_PORRSTF               RCC_MC_RSTSCLRR_PORRSTF_Msk             /*POR/PDR reset flag*/
23682 
23683 #define RCC_MC_RSTSCLRR_BORRSTF_Pos           (1U)
23684 #define RCC_MC_RSTSCLRR_BORRSTF_Msk           (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos)   /*!< 0x00000002 */
23685 #define RCC_MC_RSTSCLRR_BORRSTF               RCC_MC_RSTSCLRR_BORRSTF_Msk             /*BOR reset flag*/
23686 
23687 #define RCC_MC_RSTSCLRR_PADRSTF_Pos           (2U)
23688 #define RCC_MC_RSTSCLRR_PADRSTF_Msk           (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos)   /*!< 0x00000004 */
23689 #define RCC_MC_RSTSCLRR_PADRSTF               RCC_MC_RSTSCLRR_PADRSTF_Msk             /*NRST reset flag*/
23690 
23691 #define RCC_MC_RSTSCLRR_HCSSRSTF_Pos          (3U)
23692 #define RCC_MC_RSTSCLRR_HCSSRSTF_Msk          (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos)  /*!< 0x00000008 */
23693 #define RCC_MC_RSTSCLRR_HCSSRSTF              RCC_MC_RSTSCLRR_HCSSRSTF_Msk            /*HSE CSS reset flag*/
23694 
23695 #define RCC_MC_RSTSCLRR_VCORERSTF_Pos         (4U)
23696 #define RCC_MC_RSTSCLRR_VCORERSTF_Msk         (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */
23697 #define RCC_MC_RSTSCLRR_VCORERSTF             RCC_MC_RSTSCLRR_VCORERSTF_Msk           /*VDDCORE reset flag*/
23698 
23699 #define RCC_MC_RSTSCLRR_MCURSTF_Pos           (5U)
23700 #define RCC_MC_RSTSCLRR_MCURSTF_Msk           (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000080 */
23701 #define RCC_MC_RSTSCLRR_MCURSTF               RCC_MC_RSTSCLRR_MCURSTF_Msk           /*MCU reset flag*/
23702 
23703 #define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos         (6U)
23704 #define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk         (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */
23705 #define RCC_MC_RSTSCLRR_MPSYSRSTF             RCC_MC_RSTSCLRR_MPSYSRSTF_Msk           /*MPU System reset flag*/
23706 
23707 #define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos         (7U)
23708 #define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk         (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */
23709 #define RCC_MC_RSTSCLRR_MCSYSRSTF             RCC_MC_RSTSCLRR_MCSYSRSTF_Msk           /*MCU System reset flag*/
23710 
23711 #define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos         (8U)
23712 #define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk         (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */
23713 #define RCC_MC_RSTSCLRR_IWDG1RSTF             RCC_MC_RSTSCLRR_IWDG1RSTF_Msk           /*IWDG1 reset flag*/
23714 
23715 #define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos         (9U)
23716 #define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk         (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */
23717 #define RCC_MC_RSTSCLRR_IWDG2RSTF             RCC_MC_RSTSCLRR_IWDG2RSTF_Msk           /*IWDG2 reset flag*/
23718 
23719 #define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos         (10U)
23720 #define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk         (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000200 */
23721 #define RCC_MC_RSTSCLRR_WWDG1RSTF             RCC_MC_RSTSCLRR_WWDG1RSTF_Msk           /*WWDG1 reset flag*/
23722 
23723 /*******************  Bit definition for RCC_MP_RSTSCLRR register ************/
23724 /*!< This register is used by the MPU to check the reset source. This register is updated
23725  * by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or
23726  * exit from STANDBY or CSTANDBY.
23727  *
23728  * @note Writing '0' has no effect, reading will return the effective values of
23729  *       the corresponding bits. Writing a '1' clears the corresponding bit to '0'.
23730  * @note The register is located in VDD_CORE.
23731  * @note If TZEN = '1', this register can only be modified in secure mode.
23732  */
23733 #define RCC_MP_RSTSCLRR_PORRSTF_Pos           (0U)
23734 #define RCC_MP_RSTSCLRR_PORRSTF_Msk           (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos)   /*!< 0x00000001 */
23735 #define RCC_MP_RSTSCLRR_PORRSTF               RCC_MP_RSTSCLRR_PORRSTF_Msk             /*POR/PDR reset flag*/
23736 
23737 #define RCC_MP_RSTSCLRR_BORRSTF_Pos           (1U)
23738 #define RCC_MP_RSTSCLRR_BORRSTF_Msk           (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos)   /*!< 0x00000002 */
23739 #define RCC_MP_RSTSCLRR_BORRSTF               RCC_MP_RSTSCLRR_BORRSTF_Msk             /*BOR reset flag*/
23740 
23741 #define RCC_MP_RSTSCLRR_PADRSTF_Pos           (2U)
23742 #define RCC_MP_RSTSCLRR_PADRSTF_Msk           (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos)   /*!< 0x00000004 */
23743 #define RCC_MP_RSTSCLRR_PADRSTF               RCC_MP_RSTSCLRR_PADRSTF_Msk             /*NRST reset flag*/
23744 
23745 #define RCC_MP_RSTSCLRR_HCSSRSTF_Pos          (3U)
23746 #define RCC_MP_RSTSCLRR_HCSSRSTF_Msk          (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos)  /*!< 0x00000008 */
23747 #define RCC_MP_RSTSCLRR_HCSSRSTF              RCC_MP_RSTSCLRR_HCSSRSTF_Msk            /*HSE CSS reset flag*/
23748 
23749 #define RCC_MP_RSTSCLRR_VCORERSTF_Pos         (4U)
23750 #define RCC_MP_RSTSCLRR_VCORERSTF_Msk         (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */
23751 #define RCC_MP_RSTSCLRR_VCORERSTF             RCC_MP_RSTSCLRR_VCORERSTF_Msk           /*VDDCORE reset flag*/
23752 
23753 #define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos         (6U)
23754 #define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk         (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */
23755 #define RCC_MP_RSTSCLRR_MPSYSRSTF             RCC_MP_RSTSCLRR_MPSYSRSTF_Msk           /*MPU System reset flag*/
23756 
23757 #define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos         (7U)
23758 #define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk         (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */
23759 #define RCC_MP_RSTSCLRR_MCSYSRSTF             RCC_MP_RSTSCLRR_MCSYSRSTF_Msk           /*MCU System reset flag*/
23760 
23761 #define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos         (8U)
23762 #define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk         (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */
23763 #define RCC_MP_RSTSCLRR_IWDG1RSTF             RCC_MP_RSTSCLRR_IWDG1RSTF_Msk           /*IWDG1 reset flag*/
23764 
23765 #define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos         (9U)
23766 #define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk         (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */
23767 #define RCC_MP_RSTSCLRR_IWDG2RSTF             RCC_MP_RSTSCLRR_IWDG2RSTF_Msk           /*IWDG2 reset flag*/
23768 
23769 #define RCC_MP_RSTSCLRR_STDBYRSTF_Pos         (11U)
23770 #define RCC_MP_RSTSCLRR_STDBYRSTF_Msk         (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */
23771 #define RCC_MP_RSTSCLRR_STDBYRSTF             RCC_MP_RSTSCLRR_STDBYRSTF_Msk           /*System Standby reset flag*/
23772 
23773 #define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos        (12U)
23774 #define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk        (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */
23775 #define RCC_MP_RSTSCLRR_CSTDBYRSTF            RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk           /*MPU CStandby reset flag*/
23776 
23777 #define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos         (13U)
23778 #define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk         (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */
23779 #define RCC_MP_RSTSCLRR_MPUP0RSTF             RCC_MP_RSTSCLRR_MPUP0RSTF_Msk           /*MPU processor 0 reset flag*/
23780 
23781 #define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos         (14U)
23782 #define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk         (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */
23783 #define RCC_MP_RSTSCLRR_MPUP1RSTF             RCC_MP_RSTSCLRR_MPUP1RSTF_Msk           /*MPU processor 1 reset flag*/
23784 
23785 #define RCC_MP_RSTSCLRR_SPARE_Pos             (15U)
23786 #define RCC_MP_RSTSCLRR_SPARE_Msk             (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos)     /*!< 0x00008000 */
23787 #define RCC_MP_RSTSCLRR_SPARE                 RCC_MP_RSTSCLRR_SPARE_Msk               /*Spare bits*/
23788 
23789 /*******************  Bit definition for RCC_MP_IWDGFZSETR register ************/
23790 /*!< This register is used by the MPU in order to freeze the IWDGs clocks.
23791  * After a system reset or STANDBY reset (nreset), or a CSTANDBY reset (rst_cstby)
23792  * the MPU is allowed to write it once.
23793  * Writing "0" has no effect, reading will return the effective values of the corresponding
23794  * bits. Writing a "1" sets the corresponding bit to 1. If TZEN = 1, this register can only be
23795  * modified in secure mode.
23796  */
23797 #define RCC_MP_IWDGFZSETR_FZ_IWDG1            B(0)
23798 #define RCC_MP_IWDGFZSETR_FZ_IWDG2            B(1)
23799 
23800 
23801 /*******************  Bit definition for RCC_MP_IWDGFZCLRR register ************/
23802 /*!< This register is used by the MPU in order to unfreeze the IWDGs clocks.
23803  * Writing "0" has no effect, reading will return the effective values of the corresponding
23804  * bits. Writing a "1" clears the corresponding bit to 0. If TZEN = 1, this register can only
23805  * be modified in secure mode.
23806  */
23807 #define RCC_MP_IWDGFZCLRR_FZ_IWDG1            B(0)
23808 #define RCC_MP_IWDGFZCLRR_FZ_IWDG2            B(1)
23809 
23810 /*******************  Bit definition for RCC_VERR register ************/
23811 /*!< This register gives the IP version.  */
23812 #define RCC_VERR_MINREV_Pos                   (0U)
23813 #define RCC_VERR_MINREV_Msk                   (0xFU << RCC_VERR_MINREV_Pos)    /*!< 0x0000000F */
23814 #define RCC_VERR_MINREV                       RCC_VERR_MINREV_Msk
23815 #define RCC_VERR_MAJREV_Pos                   (4U)
23816 #define RCC_VERR_MAJREV_Msk                   (0xFU << RCC_VERR_MAJREV_Pos)    /*!< 0x000000F0 */
23817 #define RCC_VERR_MAJREV                       RCC_VERR_MAJREV_Msk
23818 
23819 /*******************  Bit definition for RCC_IDR register ************/
23820 /*!< This register gives the unique identifier of the RCC  */
23821 #define RCC_VERR_ID_Pos                       (0U)
23822 #define RCC_VERR_ID_Msk                       (0xFFFFFFFFU << RCC_VERR_ID_Pos) /*!< 0xFFFFFFFF */
23823 #define RCC_VERR_ID                           RCC_VERR_ID_Msk
23824 
23825 /*******************  Bit definition for RCC_IDR register ************/
23826 /*!< This register gives the decoding space, which is for the RCC of 4 kB */
23827 #define RCC_VERR_SIDR_Pos                     (0U)
23828 #define RCC_VERR_SIDR_Msk                     (0xFFFFFFFFU << RCC_VERR_SIDR_Pos) /*!< 0xFFFFFFFF */
23829 #define RCC_VERR_SIDR                         RCC_VERR_SIDR_Msk
23830 
23831 /******************************************************************************/
23832 /*                                                                            */
23833 /*                                    RNG                                     */
23834 /*                                                                            */
23835 /******************************************************************************/
23836 /********************  Bits definition for RNG_CR register  *******************/
23837 #define RNG_CR_RNGEN_Pos    (2U)
23838 #define RNG_CR_RNGEN_Msk    (0x1U << RNG_CR_RNGEN_Pos)                         /*!< 0x00000004 */
23839 #define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk
23840 #define RNG_CR_IE_Pos       (3U)
23841 #define RNG_CR_IE_Msk       (0x1U << RNG_CR_IE_Pos)                            /*!< 0x00000008 */
23842 #define RNG_CR_IE           RNG_CR_IE_Msk
23843 #define RNG_CR_CED_Pos      (5U)
23844 #define RNG_CR_CED_Msk      (0x1U << RNG_CR_CED_Pos)                           /*!< 0x00000020 */
23845 #define RNG_CR_CED          RNG_CR_CED_Msk
23846 
23847 /********************  Bits definition for RNG_SR register  *******************/
23848 #define RNG_SR_DRDY_Pos     (0U)
23849 #define RNG_SR_DRDY_Msk     (0x1U << RNG_SR_DRDY_Pos)                          /*!< 0x00000001 */
23850 #define RNG_SR_DRDY         RNG_SR_DRDY_Msk
23851 #define RNG_SR_CECS_Pos     (1U)
23852 #define RNG_SR_CECS_Msk     (0x1U << RNG_SR_CECS_Pos)                          /*!< 0x00000002 */
23853 #define RNG_SR_CECS         RNG_SR_CECS_Msk
23854 #define RNG_SR_SECS_Pos     (2U)
23855 #define RNG_SR_SECS_Msk     (0x1U << RNG_SR_SECS_Pos)                          /*!< 0x00000004 */
23856 #define RNG_SR_SECS         RNG_SR_SECS_Msk
23857 #define RNG_SR_CEIS_Pos     (5U)
23858 #define RNG_SR_CEIS_Msk     (0x1U << RNG_SR_CEIS_Pos)                          /*!< 0x00000020 */
23859 #define RNG_SR_CEIS         RNG_SR_CEIS_Msk
23860 #define RNG_SR_SEIS_Pos     (6U)
23861 #define RNG_SR_SEIS_Msk     (0x1U << RNG_SR_SEIS_Pos)                          /*!< 0x00000040 */
23862 #define RNG_SR_SEIS         RNG_SR_SEIS_Msk
23863 
23864 /**********************  Bit definition for RNG_VERR register  *****************/
23865 #define RNG_VERR_MINREV_Pos      (0U)
23866 #define RNG_VERR_MINREV_Msk      (0xFU << RNG_VERR_MINREV_Pos)               /*!< 0x0000000F */
23867 #define RNG_VERR_MINREV          RNG_VERR_MINREV_Msk                         /*!< Minor Revision number */
23868 #define RNG_VERR_MAJREV_Pos      (4U)
23869 #define RNG_VERR_MAJREV_Msk      (0xFU << RNG_VERR_MAJREV_Pos)               /*!< 0x000000F0 */
23870 #define RNG_VERR_MAJREV          RNG_VERR_MAJREV_Msk                         /*!< Major Revision number */
23871 
23872 /**********************  Bit definition for RNG_IPIDR register  ****************/
23873 #define RNG_IPIDR_ID_Pos       (0U)
23874 #define RNG_IPIDR_ID_Msk       (0xFFFFFFFFU << RNG_IPIDR_ID_Pos)         /*!< 0xFFFFFFFF */
23875 #define RNG_IPIDR_ID           RNG_IPIDR_ID_Msk                          /*!< IP Identification */
23876 
23877 /**********************  Bit definition for RNG_SIDR register  *****************/
23878 #define RNG_SIDR_SID_Pos         (0U)
23879 #define RNG_SIDR_SID_Msk         (0xFFFFFFFFU << RNG_SIDR_SID_Pos)           /*!< 0xFFFFFFFF */
23880 #define RNG_SIDR_SID             RNG_SIDR_SID_Msk                            /*!< IP size identification */
23881 
23882 /******************************************************************************/
23883 /*                                                                            */
23884 /*                           Real-Time Clock (RTC)                            */
23885 /*                                                                            */
23886 /******************************************************************************/
23887 /*
23888 * @brief Specific device feature definitions
23889 */
23890 
23891 /********************  Bits definition for RTC_TR register  *******************/
23892 #define RTC_TR_PM_Pos                     (22U)
23893 #define RTC_TR_PM_Msk                     (0x1U << RTC_TR_PM_Pos)              /*!< 0x00400000 */
23894 #define RTC_TR_PM                         RTC_TR_PM_Msk
23895 #define RTC_TR_HT_Pos                     (20U)
23896 #define RTC_TR_HT_Msk                     (0x3U << RTC_TR_HT_Pos)              /*!< 0x00300000 */
23897 #define RTC_TR_HT                         RTC_TR_HT_Msk
23898 #define RTC_TR_HT_0                       (0x1U << RTC_TR_HT_Pos)              /*!< 0x00100000 */
23899 #define RTC_TR_HT_1                       (0x2U << RTC_TR_HT_Pos)              /*!< 0x00200000 */
23900 #define RTC_TR_HU_Pos                     (16U)
23901 #define RTC_TR_HU_Msk                     (0xFU << RTC_TR_HU_Pos)              /*!< 0x000F0000 */
23902 #define RTC_TR_HU                         RTC_TR_HU_Msk
23903 #define RTC_TR_HU_0                       (0x1U << RTC_TR_HU_Pos)              /*!< 0x00010000 */
23904 #define RTC_TR_HU_1                       (0x2U << RTC_TR_HU_Pos)              /*!< 0x00020000 */
23905 #define RTC_TR_HU_2                       (0x4U << RTC_TR_HU_Pos)              /*!< 0x00040000 */
23906 #define RTC_TR_HU_3                       (0x8U << RTC_TR_HU_Pos)              /*!< 0x00080000 */
23907 #define RTC_TR_MNT_Pos                    (12U)
23908 #define RTC_TR_MNT_Msk                    (0x7U << RTC_TR_MNT_Pos)             /*!< 0x00007000 */
23909 #define RTC_TR_MNT                        RTC_TR_MNT_Msk
23910 #define RTC_TR_MNT_0                      (0x1U << RTC_TR_MNT_Pos)             /*!< 0x00001000 */
23911 #define RTC_TR_MNT_1                      (0x2U << RTC_TR_MNT_Pos)             /*!< 0x00002000 */
23912 #define RTC_TR_MNT_2                      (0x4U << RTC_TR_MNT_Pos)             /*!< 0x00004000 */
23913 #define RTC_TR_MNU_Pos                    (8U)
23914 #define RTC_TR_MNU_Msk                    (0xFU << RTC_TR_MNU_Pos)             /*!< 0x00000F00 */
23915 #define RTC_TR_MNU                        RTC_TR_MNU_Msk
23916 #define RTC_TR_MNU_0                      (0x1U << RTC_TR_MNU_Pos)             /*!< 0x00000100 */
23917 #define RTC_TR_MNU_1                      (0x2U << RTC_TR_MNU_Pos)             /*!< 0x00000200 */
23918 #define RTC_TR_MNU_2                      (0x4U << RTC_TR_MNU_Pos)             /*!< 0x00000400 */
23919 #define RTC_TR_MNU_3                      (0x8U << RTC_TR_MNU_Pos)             /*!< 0x00000800 */
23920 #define RTC_TR_ST_Pos                     (4U)
23921 #define RTC_TR_ST_Msk                     (0x7U << RTC_TR_ST_Pos)              /*!< 0x00000070 */
23922 #define RTC_TR_ST                         RTC_TR_ST_Msk
23923 #define RTC_TR_ST_0                       (0x1U << RTC_TR_ST_Pos)              /*!< 0x00000010 */
23924 #define RTC_TR_ST_1                       (0x2U << RTC_TR_ST_Pos)              /*!< 0x00000020 */
23925 #define RTC_TR_ST_2                       (0x4U << RTC_TR_ST_Pos)              /*!< 0x00000040 */
23926 #define RTC_TR_SU_Pos                     (0U)
23927 #define RTC_TR_SU_Msk                     (0xFU << RTC_TR_SU_Pos)              /*!< 0x0000000F */
23928 #define RTC_TR_SU                         RTC_TR_SU_Msk
23929 #define RTC_TR_SU_0                       (0x1U << RTC_TR_SU_Pos)              /*!< 0x00000001 */
23930 #define RTC_TR_SU_1                       (0x2U << RTC_TR_SU_Pos)              /*!< 0x00000002 */
23931 #define RTC_TR_SU_2                       (0x4U << RTC_TR_SU_Pos)              /*!< 0x00000004 */
23932 #define RTC_TR_SU_3                       (0x8U << RTC_TR_SU_Pos)              /*!< 0x00000008 */
23933 
23934 /********************  Bits definition for RTC_DR register  *******************/
23935 #define RTC_DR_YT_Pos                     (20U)
23936 #define RTC_DR_YT_Msk                     (0xFU << RTC_DR_YT_Pos)              /*!< 0x00F00000 */
23937 #define RTC_DR_YT                         RTC_DR_YT_Msk
23938 #define RTC_DR_YT_0                       (0x1U << RTC_DR_YT_Pos)              /*!< 0x00100000 */
23939 #define RTC_DR_YT_1                       (0x2U << RTC_DR_YT_Pos)              /*!< 0x00200000 */
23940 #define RTC_DR_YT_2                       (0x4U << RTC_DR_YT_Pos)              /*!< 0x00400000 */
23941 #define RTC_DR_YT_3                       (0x8U << RTC_DR_YT_Pos)              /*!< 0x00800000 */
23942 #define RTC_DR_YU_Pos                     (16U)
23943 #define RTC_DR_YU_Msk                     (0xFU << RTC_DR_YU_Pos)              /*!< 0x000F0000 */
23944 #define RTC_DR_YU                         RTC_DR_YU_Msk
23945 #define RTC_DR_YU_0                       (0x1U << RTC_DR_YU_Pos)              /*!< 0x00010000 */
23946 #define RTC_DR_YU_1                       (0x2U << RTC_DR_YU_Pos)              /*!< 0x00020000 */
23947 #define RTC_DR_YU_2                       (0x4U << RTC_DR_YU_Pos)              /*!< 0x00040000 */
23948 #define RTC_DR_YU_3                       (0x8U << RTC_DR_YU_Pos)              /*!< 0x00080000 */
23949 #define RTC_DR_WDU_Pos                    (13U)
23950 #define RTC_DR_WDU_Msk                    (0x7U << RTC_DR_WDU_Pos)             /*!< 0x0000E000 */
23951 #define RTC_DR_WDU                        RTC_DR_WDU_Msk
23952 #define RTC_DR_WDU_0                      (0x1U << RTC_DR_WDU_Pos)             /*!< 0x00002000 */
23953 #define RTC_DR_WDU_1                      (0x2U << RTC_DR_WDU_Pos)             /*!< 0x00004000 */
23954 #define RTC_DR_WDU_2                      (0x4U << RTC_DR_WDU_Pos)             /*!< 0x00008000 */
23955 #define RTC_DR_MT_Pos                     (12U)
23956 #define RTC_DR_MT_Msk                     (0x1U << RTC_DR_MT_Pos)              /*!< 0x00001000 */
23957 #define RTC_DR_MT                         RTC_DR_MT_Msk
23958 #define RTC_DR_MU_Pos                     (8U)
23959 #define RTC_DR_MU_Msk                     (0xFU << RTC_DR_MU_Pos)              /*!< 0x00000F00 */
23960 #define RTC_DR_MU                         RTC_DR_MU_Msk
23961 #define RTC_DR_MU_0                       (0x1U << RTC_DR_MU_Pos)              /*!< 0x00000100 */
23962 #define RTC_DR_MU_1                       (0x2U << RTC_DR_MU_Pos)              /*!< 0x00000200 */
23963 #define RTC_DR_MU_2                       (0x4U << RTC_DR_MU_Pos)              /*!< 0x00000400 */
23964 #define RTC_DR_MU_3                       (0x8U << RTC_DR_MU_Pos)              /*!< 0x00000800 */
23965 #define RTC_DR_DT_Pos                     (4U)
23966 #define RTC_DR_DT_Msk                     (0x3U << RTC_DR_DT_Pos)              /*!< 0x00000030 */
23967 #define RTC_DR_DT                         RTC_DR_DT_Msk
23968 #define RTC_DR_DT_0                       (0x1U << RTC_DR_DT_Pos)              /*!< 0x00000010 */
23969 #define RTC_DR_DT_1                       (0x2U << RTC_DR_DT_Pos)              /*!< 0x00000020 */
23970 #define RTC_DR_DU_Pos                     (0U)
23971 #define RTC_DR_DU_Msk                     (0xFU << RTC_DR_DU_Pos)              /*!< 0x0000000F */
23972 #define RTC_DR_DU                         RTC_DR_DU_Msk
23973 #define RTC_DR_DU_0                       (0x1U << RTC_DR_DU_Pos)              /*!< 0x00000001 */
23974 #define RTC_DR_DU_1                       (0x2U << RTC_DR_DU_Pos)              /*!< 0x00000002 */
23975 #define RTC_DR_DU_2                       (0x4U << RTC_DR_DU_Pos)              /*!< 0x00000004 */
23976 #define RTC_DR_DU_3                       (0x8U << RTC_DR_DU_Pos)              /*!< 0x00000008 */
23977 
23978 /********************  Bits definition for RTC_SSR register  ******************/
23979 #define RTC_SSR_SS_Pos                    (0U)
23980 #define RTC_SSR_SS_Msk                    (0xFFFFU << RTC_SSR_SS_Pos)          /*!< 0x0000FFFF */
23981 #define RTC_SSR_SS                        RTC_SSR_SS_Msk
23982 
23983 /****************  Bits definition for RTC_ICSR (RTC_ISR) register *************/
23984 #define RTC_ICSR_RECALPF_Pos         (16U)
23985 #define RTC_ICSR_RECALPF_Msk         (0x1UL << RTC_ICSR_RECALPF_Pos)           /*!< 0x00010000 */
23986 #define RTC_ICSR_RECALPF             RTC_ICSR_RECALPF_Msk
23987 #define RTC_ICSR_INIT_Pos            (7U)
23988 #define RTC_ICSR_INIT_Msk            (0x1UL << RTC_ICSR_INIT_Pos)              /*!< 0x00000080 */
23989 #define RTC_ICSR_INIT                RTC_ICSR_INIT_Msk
23990 #define RTC_ICSR_INITF_Pos           (6U)
23991 #define RTC_ICSR_INITF_Msk           (0x1UL << RTC_ICSR_INITF_Pos)             /*!< 0x00000040 */
23992 #define RTC_ICSR_INITF               RTC_ICSR_INITF_Msk
23993 #define RTC_ICSR_RSF_Pos             (5U)
23994 #define RTC_ICSR_RSF_Msk             (0x1UL << RTC_ICSR_RSF_Pos)               /*!< 0x00000020 */
23995 #define RTC_ICSR_RSF                 RTC_ICSR_RSF_Msk
23996 #define RTC_ICSR_INITS_Pos           (4U)
23997 #define RTC_ICSR_INITS_Msk           (0x1UL << RTC_ICSR_INITS_Pos)             /*!< 0x00000010 */
23998 #define RTC_ICSR_INITS               RTC_ICSR_INITS_Msk
23999 #define RTC_ICSR_SHPF_Pos            (3U)
24000 #define RTC_ICSR_SHPF_Msk            (0x1UL << RTC_ICSR_SHPF_Pos)              /*!< 0x00000008 */
24001 #define RTC_ICSR_SHPF                RTC_ICSR_SHPF_Msk
24002 #define RTC_ICSR_WUTWF_Pos           (2U)
24003 #define RTC_ICSR_WUTWF_Msk           (0x1UL << RTC_ICSR_WUTWF_Pos)             /*!< 0x00000004 */
24004 #define RTC_ICSR_WUTWF               RTC_ICSR_WUTWF_Msk
24005 #define RTC_ICSR_ALRBWF_Pos          (1U)
24006 #define RTC_ICSR_ALRBWF_Msk          (0x1UL << RTC_ICSR_ALRBWF_Pos)            /*!< 0x00000002 */
24007 #define RTC_ICSR_ALRBWF              RTC_ICSR_ALRBWF_Msk
24008 #define RTC_ICSR_ALRAWF_Pos          (0U)
24009 #define RTC_ICSR_ALRAWF_Msk          (0x1UL << RTC_ICSR_ALRAWF_Pos)            /*!< 0x00000001 */
24010 #define RTC_ICSR_ALRAWF              RTC_ICSR_ALRAWF_Msk
24011 
24012 
24013 /********************  Bits definition for RTC_PRER register  *****************/
24014 #define RTC_PRER_PREDIV_A_Pos             (16U)
24015 #define RTC_PRER_PREDIV_A_Msk             (0x7FU << RTC_PRER_PREDIV_A_Pos)     /*!< 0x007F0000 */
24016 #define RTC_PRER_PREDIV_A                 RTC_PRER_PREDIV_A_Msk
24017 #define RTC_PRER_PREDIV_S_Pos             (0U)
24018 #define RTC_PRER_PREDIV_S_Msk             (0x7FFFU << RTC_PRER_PREDIV_S_Pos)   /*!< 0x00007FFF */
24019 #define RTC_PRER_PREDIV_S                 RTC_PRER_PREDIV_S_Msk
24020 
24021 /********************  Bits definition for RTC_WUTR register  *****************/
24022 #define RTC_WUTR_WUT_Pos                  (0U)
24023 #define RTC_WUTR_WUT_Msk                  (0xFFFFU << RTC_WUTR_WUT_Pos)        /*!< 0x0000FFFF */
24024 #define RTC_WUTR_WUT                      RTC_WUTR_WUT_Msk
24025 
24026 /********************  Bits definition for RTC_CR register  *******************/
24027 #define RTC_CR_OUT2EN_Pos                 (31U)
24028 #define RTC_CR_OUT2EN_Msk                 (0x1U << RTC_CR_OUT2EN_Pos)          /*!< 0x80000000 */
24029 #define RTC_CR_OUT2EN                     RTC_CR_OUT2EN_Msk
24030 #define RTC_CR_TAMPALRM_TYPE_Pos          (30U)
24031 #define RTC_CR_TAMPALRM_TYPE_Msk          (0x1U << RTC_CR_TAMPALRM_TYPE_Pos)   /*!< 0x40000000 */
24032 #define RTC_CR_TAMPALRM_TYPE              RTC_CR_TAMPALRM_TYPE_Msk
24033 #define RTC_CR_TAMPALRM_PU_Pos            (29U)
24034 #define RTC_CR_TAMPALRM_PU_Msk            (0x1U << RTC_CR_TAMPALRM_PU_Pos)     /*!< 0x20000000 */
24035 #define RTC_CR_TAMPALRM_PU                RTC_CR_TAMPALRM_PU_Msk
24036 #define RTC_CR_TAMPOE_Pos                 (26U)
24037 #define RTC_CR_TAMPOE_Msk                 (0x1U << RTC_CR_TAMPOE_Pos)          /*!< 0x04000000 */
24038 #define RTC_CR_TAMPOE                     RTC_CR_TAMPOE_Msk
24039 #define RTC_CR_TAMPTS_Pos                 (25U)
24040 #define RTC_CR_TAMPTS_Msk                 (0x1U << RTC_CR_TAMPTS_Pos)          /*!< 0x02000000 */
24041 #define RTC_CR_TAMPTS                     RTC_CR_TAMPTS_Msk
24042 #define RTC_CR_ITSE_Pos                   (24U)
24043 #define RTC_CR_ITSE_Msk                   (0x1U << RTC_CR_ITSE_Pos)            /*!< 0x01000000 */
24044 #define RTC_CR_ITSE                       RTC_CR_ITSE_Msk
24045 #define RTC_CR_COE_Pos                    (23U)
24046 #define RTC_CR_COE_Msk                    (0x1U << RTC_CR_COE_Pos)             /*!< 0x00800000 */
24047 #define RTC_CR_COE                        RTC_CR_COE_Msk
24048 #define RTC_CR_OSEL_Pos                   (21U)
24049 #define RTC_CR_OSEL_Msk                   (0x3U << RTC_CR_OSEL_Pos)            /*!< 0x00600000 */
24050 #define RTC_CR_OSEL                       RTC_CR_OSEL_Msk
24051 #define RTC_CR_OSEL_0                     (0x1U << RTC_CR_OSEL_Pos)            /*!< 0x00200000 */
24052 #define RTC_CR_OSEL_1                     (0x2U << RTC_CR_OSEL_Pos)            /*!< 0x00400000 */
24053 #define RTC_CR_POL_Pos                    (20U)
24054 #define RTC_CR_POL_Msk                    (0x1U << RTC_CR_POL_Pos)             /*!< 0x00100000 */
24055 #define RTC_CR_POL                        RTC_CR_POL_Msk
24056 #define RTC_CR_COSEL_Pos                  (19U)
24057 #define RTC_CR_COSEL_Msk                  (0x1U << RTC_CR_COSEL_Pos)           /*!< 0x00080000 */
24058 #define RTC_CR_COSEL                      RTC_CR_COSEL_Msk
24059 #define RTC_CR_BKP_Pos                    (18U)
24060 #define RTC_CR_BKP_Msk                    (0x1U << RTC_CR_BKP_Pos)             /*!< 0x00040000 */
24061 #define RTC_CR_BKP                        RTC_CR_BKP_Msk
24062 #define RTC_CR_SUB1H_Pos                  (17U)
24063 #define RTC_CR_SUB1H_Msk                  (0x1U << RTC_CR_SUB1H_Pos)           /*!< 0x00020000 */
24064 #define RTC_CR_SUB1H                      RTC_CR_SUB1H_Msk
24065 #define RTC_CR_ADD1H_Pos                  (16U)
24066 #define RTC_CR_ADD1H_Msk                  (0x1U << RTC_CR_ADD1H_Pos)           /*!< 0x00010000 */
24067 #define RTC_CR_ADD1H                      RTC_CR_ADD1H_Msk
24068 #define RTC_CR_TSIE_Pos                   (15U)
24069 #define RTC_CR_TSIE_Msk                   (0x1U << RTC_CR_TSIE_Pos)            /*!< 0x00008000 */
24070 #define RTC_CR_TSIE                       RTC_CR_TSIE_Msk
24071 #define RTC_CR_WUTIE_Pos                  (14U)
24072 #define RTC_CR_WUTIE_Msk                  (0x1U << RTC_CR_WUTIE_Pos)           /*!< 0x00004000 */
24073 #define RTC_CR_WUTIE                      RTC_CR_WUTIE_Msk
24074 #define RTC_CR_ALRBIE_Pos                 (13U)
24075 #define RTC_CR_ALRBIE_Msk                 (0x1U << RTC_CR_ALRBIE_Pos)          /*!< 0x00002000 */
24076 #define RTC_CR_ALRBIE                     RTC_CR_ALRBIE_Msk
24077 #define RTC_CR_ALRAIE_Pos                 (12U)
24078 #define RTC_CR_ALRAIE_Msk                 (0x1U << RTC_CR_ALRAIE_Pos)          /*!< 0x00001000 */
24079 #define RTC_CR_ALRAIE                     RTC_CR_ALRAIE_Msk
24080 #define RTC_CR_TSE_Pos                    (11U)
24081 #define RTC_CR_TSE_Msk                    (0x1U << RTC_CR_TSE_Pos)             /*!< 0x00000800 */
24082 #define RTC_CR_TSE                        RTC_CR_TSE_Msk
24083 #define RTC_CR_WUTE_Pos                   (10U)
24084 #define RTC_CR_WUTE_Msk                   (0x1U << RTC_CR_WUTE_Pos)            /*!< 0x00000400 */
24085 #define RTC_CR_WUTE                       RTC_CR_WUTE_Msk
24086 #define RTC_CR_ALRBE_Pos                  (9U)
24087 #define RTC_CR_ALRBE_Msk                  (0x1U << RTC_CR_ALRBE_Pos)           /*!< 0x00000200 */
24088 #define RTC_CR_ALRBE                      RTC_CR_ALRBE_Msk
24089 #define RTC_CR_ALRAE_Pos                  (8U)
24090 #define RTC_CR_ALRAE_Msk                  (0x1U << RTC_CR_ALRAE_Pos)           /*!< 0x00000100 */
24091 #define RTC_CR_ALRAE                      RTC_CR_ALRAE_Msk
24092 #define RTC_CR_FMT_Pos                    (6U)
24093 #define RTC_CR_FMT_Msk                    (0x1U << RTC_CR_FMT_Pos)             /*!< 0x00000040 */
24094 #define RTC_CR_FMT                        RTC_CR_FMT_Msk
24095 #define RTC_CR_BYPSHAD_Pos                (5U)
24096 #define RTC_CR_BYPSHAD_Msk                (0x1U << RTC_CR_BYPSHAD_Pos)         /*!< 0x00000020 */
24097 #define RTC_CR_BYPSHAD                    RTC_CR_BYPSHAD_Msk
24098 #define RTC_CR_REFCKON_Pos                (4U)
24099 #define RTC_CR_REFCKON_Msk                (0x1U << RTC_CR_REFCKON_Pos)         /*!< 0x00000010 */
24100 #define RTC_CR_REFCKON                    RTC_CR_REFCKON_Msk
24101 #define RTC_CR_TSEDGE_Pos                 (3U)
24102 #define RTC_CR_TSEDGE_Msk                 (0x1U << RTC_CR_TSEDGE_Pos)          /*!< 0x00000008 */
24103 #define RTC_CR_TSEDGE                     RTC_CR_TSEDGE_Msk
24104 #define RTC_CR_WUCKSEL_Pos                (0U)
24105 #define RTC_CR_WUCKSEL_Msk                (0x7U << RTC_CR_WUCKSEL_Pos)         /*!< 0x00000007 */
24106 #define RTC_CR_WUCKSEL                    RTC_CR_WUCKSEL_Msk
24107 #define RTC_CR_WUCKSEL_0                  (0x1U << RTC_CR_WUCKSEL_Pos)         /*!< 0x00000001 */
24108 #define RTC_CR_WUCKSEL_1                  (0x2U << RTC_CR_WUCKSEL_Pos)         /*!< 0x00000002 */
24109 #define RTC_CR_WUCKSEL_2                  (0x4U << RTC_CR_WUCKSEL_Pos)         /*!< 0x00000004 */
24110 
24111 /********************  Bits definition for RTC_SMCR register  *******************/
24112 #define RTC_SMCR_DECPROT_Pos              (15U)
24113 #define RTC_SMCR_DECPROT_Msk              (0x1U << RTC_SMCR_DECPROT_Pos)       /*!< 0x00008000 */
24114 #define RTC_SMCR_DECPROT                  RTC_SMCR_DECPROT_Msk
24115 #define RTC_SMCR_INITDPROT_Pos            (14U)
24116 #define RTC_SMCR_INITDPROT_Msk            (0x1U << RTC_SMCR_INITDPROT_Pos)     /*!< 0x00004000 */
24117 #define RTC_SMCR_INITDPROT                RTC_SMCR_INITDPROT_Msk
24118 #define RTC_SMCR_CALDPROT_Pos             (13U)
24119 #define RTC_SMCR_CALDPROT_Msk             (0x1U << RTC_SMCR_CALDPROT_Pos)      /*!< 0x00002000 */
24120 #define RTC_SMCR_CALDPROT                 RTC_SMCR_CALDPROT_Msk
24121 #define RTC_SMCR_TSDPROT_Pos              (3U)
24122 #define RTC_SMCR_TSDPROT_Msk              (0x1U << RTC_SMCR_TSDPROT_Pos)       /*!< 0x00000008 */
24123 #define RTC_SMCR_TSDPROT                  RTC_SMCR_TSDPROT_Msk
24124 #define RTC_SMCR_WUTDPROT_Pos             (2U)
24125 #define RTC_SMCR_WUTDPROT_Msk             (0x1U << RTC_SMCR_WUTDPROT_Pos)      /*!< 0x00000004 */
24126 #define RTC_SMCR_WUTDPROT                 RTC_SMCR_WUTDPROT_Msk
24127 #define RTC_SMCR_ALRBDPROT_Pos            (1U)
24128 #define RTC_SMCR_ALRBDPROT_Msk            (0x1U << RTC_SMCR_ALRBDPROT_Pos)     /*!< 0x00000002 */
24129 #define RTC_SMCR_ALRBDPROT                RTC_SMCR_ALRBDPROT_Msk
24130 #define RTC_SMCR_ALRADPROT_Pos            (0U)
24131 #define RTC_SMCR_ALRADPROT_Msk            (0x1U << RTC_SMCR_ALRADPROT_Pos)     /*!< 0x00000001 */
24132 #define RTC_SMCR_ALRADPROT                RTC_SMCR_ALRADPROT_Msk
24133 
24134 /********************  Bits definition for RTC_WPR register  ******************/
24135 #define RTC_WPR_KEY_Pos                   (0U)
24136 #define RTC_WPR_KEY_Msk                   (0xFFU << RTC_WPR_KEY_Pos)           /*!< 0x000000FF */
24137 #define RTC_WPR_KEY                       RTC_WPR_KEY_Msk
24138 
24139 /********************  Bits definition for RTC_CALR register  *****************/
24140 #define RTC_CALR_CALP_Pos                 (15U)
24141 #define RTC_CALR_CALP_Msk                 (0x1U << RTC_CALR_CALP_Pos)          /*!< 0x00008000 */
24142 #define RTC_CALR_CALP                     RTC_CALR_CALP_Msk
24143 #define RTC_CALR_CALW8_Pos                (14U)
24144 #define RTC_CALR_CALW8_Msk                (0x1U << RTC_CALR_CALW8_Pos)         /*!< 0x00004000 */
24145 #define RTC_CALR_CALW8                    RTC_CALR_CALW8_Msk
24146 #define RTC_CALR_CALW16_Pos               (13U)
24147 #define RTC_CALR_CALW16_Msk               (0x1U << RTC_CALR_CALW16_Pos)        /*!< 0x00002000 */
24148 #define RTC_CALR_CALW16                   RTC_CALR_CALW16_Msk
24149 #define RTC_CALR_CALM_Pos                 (0U)
24150 #define RTC_CALR_CALM_Msk                 (0x1FFU << RTC_CALR_CALM_Pos)        /*!< 0x000001FF */
24151 #define RTC_CALR_CALM                     RTC_CALR_CALM_Msk
24152 #define RTC_CALR_CALM_0                   (0x001U << RTC_CALR_CALM_Pos)        /*!< 0x00000001 */
24153 #define RTC_CALR_CALM_1                   (0x002U << RTC_CALR_CALM_Pos)        /*!< 0x00000002 */
24154 #define RTC_CALR_CALM_2                   (0x004U << RTC_CALR_CALM_Pos)        /*!< 0x00000004 */
24155 #define RTC_CALR_CALM_3                   (0x008U << RTC_CALR_CALM_Pos)        /*!< 0x00000008 */
24156 #define RTC_CALR_CALM_4                   (0x010U << RTC_CALR_CALM_Pos)        /*!< 0x00000010 */
24157 #define RTC_CALR_CALM_5                   (0x020U << RTC_CALR_CALM_Pos)        /*!< 0x00000020 */
24158 #define RTC_CALR_CALM_6                   (0x040U << RTC_CALR_CALM_Pos)        /*!< 0x00000040 */
24159 #define RTC_CALR_CALM_7                   (0x080U << RTC_CALR_CALM_Pos)        /*!< 0x00000080 */
24160 #define RTC_CALR_CALM_8                   (0x100U << RTC_CALR_CALM_Pos)        /*!< 0x00000100 */
24161 
24162 /********************  Bits definition for RTC_SHIFTR register  ***************/
24163 #define RTC_SHIFTR_SUBFS_Pos              (0U)
24164 #define RTC_SHIFTR_SUBFS_Msk              (0x7FFFU << RTC_SHIFTR_SUBFS_Pos)    /*!< 0x00007FFF */
24165 #define RTC_SHIFTR_SUBFS                  RTC_SHIFTR_SUBFS_Msk
24166 #define RTC_SHIFTR_ADD1S_Pos              (31U)
24167 #define RTC_SHIFTR_ADD1S_Msk              (0x1U << RTC_SHIFTR_ADD1S_Pos)       /*!< 0x80000000 */
24168 #define RTC_SHIFTR_ADD1S                  RTC_SHIFTR_ADD1S_Msk
24169 
24170 /********************  Bits definition for RTC_TSTR register  *****************/
24171 #define RTC_TSTR_PM_Pos                   (22U)
24172 #define RTC_TSTR_PM_Msk                   (0x1U << RTC_TSTR_PM_Pos)            /*!< 0x00400000 */
24173 #define RTC_TSTR_PM                       RTC_TSTR_PM_Msk
24174 #define RTC_TSTR_HT_Pos                   (20U)
24175 #define RTC_TSTR_HT_Msk                   (0x3U << RTC_TSTR_HT_Pos)            /*!< 0x00300000 */
24176 #define RTC_TSTR_HT                       RTC_TSTR_HT_Msk
24177 #define RTC_TSTR_HT_0                     (0x1U << RTC_TSTR_HT_Pos)            /*!< 0x00100000 */
24178 #define RTC_TSTR_HT_1                     (0x2U << RTC_TSTR_HT_Pos)            /*!< 0x00200000 */
24179 #define RTC_TSTR_HU_Pos                   (16U)
24180 #define RTC_TSTR_HU_Msk                   (0xFU << RTC_TSTR_HU_Pos)            /*!< 0x000F0000 */
24181 #define RTC_TSTR_HU                       RTC_TSTR_HU_Msk
24182 #define RTC_TSTR_HU_0                     (0x1U << RTC_TSTR_HU_Pos)            /*!< 0x00010000 */
24183 #define RTC_TSTR_HU_1                     (0x2U << RTC_TSTR_HU_Pos)            /*!< 0x00020000 */
24184 #define RTC_TSTR_HU_2                     (0x4U << RTC_TSTR_HU_Pos)            /*!< 0x00040000 */
24185 #define RTC_TSTR_HU_3                     (0x8U << RTC_TSTR_HU_Pos)            /*!< 0x00080000 */
24186 #define RTC_TSTR_MNT_Pos                  (12U)
24187 #define RTC_TSTR_MNT_Msk                  (0x7U << RTC_TSTR_MNT_Pos)           /*!< 0x00007000 */
24188 #define RTC_TSTR_MNT                      RTC_TSTR_MNT_Msk
24189 #define RTC_TSTR_MNT_0                    (0x1U << RTC_TSTR_MNT_Pos)           /*!< 0x00001000 */
24190 #define RTC_TSTR_MNT_1                    (0x2U << RTC_TSTR_MNT_Pos)           /*!< 0x00002000 */
24191 #define RTC_TSTR_MNT_2                    (0x4U << RTC_TSTR_MNT_Pos)           /*!< 0x00004000 */
24192 #define RTC_TSTR_MNU_Pos                  (8U)
24193 #define RTC_TSTR_MNU_Msk                  (0xFU << RTC_TSTR_MNU_Pos)           /*!< 0x00000F00 */
24194 #define RTC_TSTR_MNU                      RTC_TSTR_MNU_Msk
24195 #define RTC_TSTR_MNU_0                    (0x1U << RTC_TSTR_MNU_Pos)           /*!< 0x00000100 */
24196 #define RTC_TSTR_MNU_1                    (0x2U << RTC_TSTR_MNU_Pos)           /*!< 0x00000200 */
24197 #define RTC_TSTR_MNU_2                    (0x4U << RTC_TSTR_MNU_Pos)           /*!< 0x00000400 */
24198 #define RTC_TSTR_MNU_3                    (0x8U << RTC_TSTR_MNU_Pos)           /*!< 0x00000800 */
24199 #define RTC_TSTR_ST_Pos                   (4U)
24200 #define RTC_TSTR_ST_Msk                   (0x7U << RTC_TSTR_ST_Pos)            /*!< 0x00000070 */
24201 #define RTC_TSTR_ST                       RTC_TSTR_ST_Msk
24202 #define RTC_TSTR_ST_0                     (0x1U << RTC_TSTR_ST_Pos)            /*!< 0x00000010 */
24203 #define RTC_TSTR_ST_1                     (0x2U << RTC_TSTR_ST_Pos)            /*!< 0x00000020 */
24204 #define RTC_TSTR_ST_2                     (0x4U << RTC_TSTR_ST_Pos)            /*!< 0x00000040 */
24205 #define RTC_TSTR_SU_Pos                   (0U)
24206 #define RTC_TSTR_SU_Msk                   (0xFU << RTC_TSTR_SU_Pos)            /*!< 0x0000000F */
24207 #define RTC_TSTR_SU                       RTC_TSTR_SU_Msk
24208 #define RTC_TSTR_SU_0                     (0x1U << RTC_TSTR_SU_Pos)            /*!< 0x00000001 */
24209 #define RTC_TSTR_SU_1                     (0x2U << RTC_TSTR_SU_Pos)            /*!< 0x00000002 */
24210 #define RTC_TSTR_SU_2                     (0x4U << RTC_TSTR_SU_Pos)            /*!< 0x00000004 */
24211 #define RTC_TSTR_SU_3                     (0x8U << RTC_TSTR_SU_Pos)            /*!< 0x00000008 */
24212 
24213 /********************  Bits definition for RTC_TSDR register  *****************/
24214 #define RTC_TSDR_WDU_Pos                  (13U)
24215 #define RTC_TSDR_WDU_Msk                  (0x7U << RTC_TSDR_WDU_Pos)           /*!< 0x0000E000 */
24216 #define RTC_TSDR_WDU                      RTC_TSDR_WDU_Msk
24217 #define RTC_TSDR_WDU_0                    (0x1U << RTC_TSDR_WDU_Pos)           /*!< 0x00002000 */
24218 #define RTC_TSDR_WDU_1                    (0x2U << RTC_TSDR_WDU_Pos)           /*!< 0x00004000 */
24219 #define RTC_TSDR_WDU_2                    (0x4U << RTC_TSDR_WDU_Pos)           /*!< 0x00008000 */
24220 #define RTC_TSDR_MT_Pos                   (12U)
24221 #define RTC_TSDR_MT_Msk                   (0x1U << RTC_TSDR_MT_Pos)            /*!< 0x00001000 */
24222 #define RTC_TSDR_MT                       RTC_TSDR_MT_Msk
24223 #define RTC_TSDR_MU_Pos                   (8U)
24224 #define RTC_TSDR_MU_Msk                   (0xFU << RTC_TSDR_MU_Pos)            /*!< 0x00000F00 */
24225 #define RTC_TSDR_MU                       RTC_TSDR_MU_Msk
24226 #define RTC_TSDR_MU_0                     (0x1U << RTC_TSDR_MU_Pos)            /*!< 0x00000100 */
24227 #define RTC_TSDR_MU_1                     (0x2U << RTC_TSDR_MU_Pos)            /*!< 0x00000200 */
24228 #define RTC_TSDR_MU_2                     (0x4U << RTC_TSDR_MU_Pos)            /*!< 0x00000400 */
24229 #define RTC_TSDR_MU_3                     (0x8U << RTC_TSDR_MU_Pos)            /*!< 0x00000800 */
24230 #define RTC_TSDR_DT_Pos                   (4U)
24231 #define RTC_TSDR_DT_Msk                   (0x3U << RTC_TSDR_DT_Pos)            /*!< 0x00000030 */
24232 #define RTC_TSDR_DT                       RTC_TSDR_DT_Msk
24233 #define RTC_TSDR_DT_0                     (0x1U << RTC_TSDR_DT_Pos)            /*!< 0x00000010 */
24234 #define RTC_TSDR_DT_1                     (0x2U << RTC_TSDR_DT_Pos)            /*!< 0x00000020 */
24235 #define RTC_TSDR_DU_Pos                   (0U)
24236 #define RTC_TSDR_DU_Msk                   (0xFU << RTC_TSDR_DU_Pos)            /*!< 0x0000000F */
24237 #define RTC_TSDR_DU                       RTC_TSDR_DU_Msk
24238 #define RTC_TSDR_DU_0                     (0x1U << RTC_TSDR_DU_Pos)            /*!< 0x00000001 */
24239 #define RTC_TSDR_DU_1                     (0x2U << RTC_TSDR_DU_Pos)            /*!< 0x00000002 */
24240 #define RTC_TSDR_DU_2                     (0x4U << RTC_TSDR_DU_Pos)            /*!< 0x00000004 */
24241 #define RTC_TSDR_DU_3                     (0x8U << RTC_TSDR_DU_Pos)            /*!< 0x00000008 */
24242 
24243 /********************  Bits definition for RTC_TSSSR register  ******************/
24244 #define RTC_TSSSR_SS_Pos                  (0U)
24245 #define RTC_TSSSR_SS_Msk                  (0xFFFFU << RTC_TSSSR_SS_Pos)        /*!< 0x0000FFFF */
24246 #define RTC_TSSSR_SS                      RTC_TSSSR_SS_Msk
24247 
24248 /********************  Bits definition for RTC_ALRMAR register  ***************/
24249 #define RTC_ALRMAR_MSK4_Pos               (31U)
24250 #define RTC_ALRMAR_MSK4_Msk               (0x1U << RTC_ALRMAR_MSK4_Pos)        /*!< 0x80000000 */
24251 #define RTC_ALRMAR_MSK4                   RTC_ALRMAR_MSK4_Msk
24252 #define RTC_ALRMAR_WDSEL_Pos              (30U)
24253 #define RTC_ALRMAR_WDSEL_Msk              (0x1U << RTC_ALRMAR_WDSEL_Pos)       /*!< 0x40000000 */
24254 #define RTC_ALRMAR_WDSEL                  RTC_ALRMAR_WDSEL_Msk
24255 #define RTC_ALRMAR_DT_Pos                 (28U)
24256 #define RTC_ALRMAR_DT_Msk                 (0x3U << RTC_ALRMAR_DT_Pos)          /*!< 0x30000000 */
24257 #define RTC_ALRMAR_DT                     RTC_ALRMAR_DT_Msk
24258 #define RTC_ALRMAR_DT_0                   (0x1U << RTC_ALRMAR_DT_Pos)          /*!< 0x10000000 */
24259 #define RTC_ALRMAR_DT_1                   (0x2U << RTC_ALRMAR_DT_Pos)          /*!< 0x20000000 */
24260 #define RTC_ALRMAR_DU_Pos                 (24U)
24261 #define RTC_ALRMAR_DU_Msk                 (0xFU << RTC_ALRMAR_DU_Pos)          /*!< 0x0F000000 */
24262 #define RTC_ALRMAR_DU                     RTC_ALRMAR_DU_Msk
24263 #define RTC_ALRMAR_DU_0                   (0x1U << RTC_ALRMAR_DU_Pos)          /*!< 0x01000000 */
24264 #define RTC_ALRMAR_DU_1                   (0x2U << RTC_ALRMAR_DU_Pos)          /*!< 0x02000000 */
24265 #define RTC_ALRMAR_DU_2                   (0x4U << RTC_ALRMAR_DU_Pos)          /*!< 0x04000000 */
24266 #define RTC_ALRMAR_DU_3                   (0x8U << RTC_ALRMAR_DU_Pos)          /*!< 0x08000000 */
24267 #define RTC_ALRMAR_MSK3_Pos               (23U)
24268 #define RTC_ALRMAR_MSK3_Msk               (0x1U << RTC_ALRMAR_MSK3_Pos)        /*!< 0x00800000 */
24269 #define RTC_ALRMAR_MSK3                   RTC_ALRMAR_MSK3_Msk
24270 #define RTC_ALRMAR_PM_Pos                 (22U)
24271 #define RTC_ALRMAR_PM_Msk                 (0x1U << RTC_ALRMAR_PM_Pos)          /*!< 0x00400000 */
24272 #define RTC_ALRMAR_PM                     RTC_ALRMAR_PM_Msk
24273 #define RTC_ALRMAR_HT_Pos                 (20U)
24274 #define RTC_ALRMAR_HT_Msk                 (0x3U << RTC_ALRMAR_HT_Pos)          /*!< 0x00300000 */
24275 #define RTC_ALRMAR_HT                     RTC_ALRMAR_HT_Msk
24276 #define RTC_ALRMAR_HT_0                   (0x1U << RTC_ALRMAR_HT_Pos)          /*!< 0x00100000 */
24277 #define RTC_ALRMAR_HT_1                   (0x2U << RTC_ALRMAR_HT_Pos)          /*!< 0x00200000 */
24278 #define RTC_ALRMAR_HU_Pos                 (16U)
24279 #define RTC_ALRMAR_HU_Msk                 (0xFU << RTC_ALRMAR_HU_Pos)          /*!< 0x000F0000 */
24280 #define RTC_ALRMAR_HU                     RTC_ALRMAR_HU_Msk
24281 #define RTC_ALRMAR_HU_0                   (0x1U << RTC_ALRMAR_HU_Pos)          /*!< 0x00010000 */
24282 #define RTC_ALRMAR_HU_1                   (0x2U << RTC_ALRMAR_HU_Pos)          /*!< 0x00020000 */
24283 #define RTC_ALRMAR_HU_2                   (0x4U << RTC_ALRMAR_HU_Pos)          /*!< 0x00040000 */
24284 #define RTC_ALRMAR_HU_3                   (0x8U << RTC_ALRMAR_HU_Pos)          /*!< 0x00080000 */
24285 #define RTC_ALRMAR_MSK2_Pos               (15U)
24286 #define RTC_ALRMAR_MSK2_Msk               (0x1U << RTC_ALRMAR_MSK2_Pos)        /*!< 0x00008000 */
24287 #define RTC_ALRMAR_MSK2                   RTC_ALRMAR_MSK2_Msk
24288 #define RTC_ALRMAR_MNT_Pos                (12U)
24289 #define RTC_ALRMAR_MNT_Msk                (0x7U << RTC_ALRMAR_MNT_Pos)         /*!< 0x00007000 */
24290 #define RTC_ALRMAR_MNT                    RTC_ALRMAR_MNT_Msk
24291 #define RTC_ALRMAR_MNT_0                  (0x1U << RTC_ALRMAR_MNT_Pos)         /*!< 0x00001000 */
24292 #define RTC_ALRMAR_MNT_1                  (0x2U << RTC_ALRMAR_MNT_Pos)         /*!< 0x00002000 */
24293 #define RTC_ALRMAR_MNT_2                  (0x4U << RTC_ALRMAR_MNT_Pos)         /*!< 0x00004000 */
24294 #define RTC_ALRMAR_MNU_Pos                (8U)
24295 #define RTC_ALRMAR_MNU_Msk                (0xFU << RTC_ALRMAR_MNU_Pos)         /*!< 0x00000F00 */
24296 #define RTC_ALRMAR_MNU                    RTC_ALRMAR_MNU_Msk
24297 #define RTC_ALRMAR_MNU_0                  (0x1U << RTC_ALRMAR_MNU_Pos)         /*!< 0x00000100 */
24298 #define RTC_ALRMAR_MNU_1                  (0x2U << RTC_ALRMAR_MNU_Pos)         /*!< 0x00000200 */
24299 #define RTC_ALRMAR_MNU_2                  (0x4U << RTC_ALRMAR_MNU_Pos)         /*!< 0x00000400 */
24300 #define RTC_ALRMAR_MNU_3                  (0x8U << RTC_ALRMAR_MNU_Pos)         /*!< 0x00000800 */
24301 #define RTC_ALRMAR_MSK1_Pos               (7U)
24302 #define RTC_ALRMAR_MSK1_Msk               (0x1U << RTC_ALRMAR_MSK1_Pos)        /*!< 0x00000080 */
24303 #define RTC_ALRMAR_MSK1                   RTC_ALRMAR_MSK1_Msk
24304 #define RTC_ALRMAR_ST_Pos                 (4U)
24305 #define RTC_ALRMAR_ST_Msk                 (0x7U << RTC_ALRMAR_ST_Pos)          /*!< 0x00000070 */
24306 #define RTC_ALRMAR_ST                     RTC_ALRMAR_ST_Msk
24307 #define RTC_ALRMAR_ST_0                   (0x1U << RTC_ALRMAR_ST_Pos)          /*!< 0x00000010 */
24308 #define RTC_ALRMAR_ST_1                   (0x2U << RTC_ALRMAR_ST_Pos)          /*!< 0x00000020 */
24309 #define RTC_ALRMAR_ST_2                   (0x4U << RTC_ALRMAR_ST_Pos)          /*!< 0x00000040 */
24310 #define RTC_ALRMAR_SU_Pos                 (0U)
24311 #define RTC_ALRMAR_SU_Msk                 (0xFU << RTC_ALRMAR_SU_Pos)          /*!< 0x0000000F */
24312 #define RTC_ALRMAR_SU                     RTC_ALRMAR_SU_Msk
24313 #define RTC_ALRMAR_SU_0                   (0x1U << RTC_ALRMAR_SU_Pos)          /*!< 0x00000001 */
24314 #define RTC_ALRMAR_SU_1                   (0x2U << RTC_ALRMAR_SU_Pos)          /*!< 0x00000002 */
24315 #define RTC_ALRMAR_SU_2                   (0x4U << RTC_ALRMAR_SU_Pos)          /*!< 0x00000004 */
24316 #define RTC_ALRMAR_SU_3                   (0x8U << RTC_ALRMAR_SU_Pos)          /*!< 0x00000008 */
24317 
24318 /********************  Bits definition for RTC_ALRMASSR register  *************/
24319 #define RTC_ALRMASSR_MASKSS_Pos           (24U)
24320 #define RTC_ALRMASSR_MASKSS_Msk           (0xFU << RTC_ALRMASSR_MASKSS_Pos)    /*!< 0x0F000000 */
24321 #define RTC_ALRMASSR_MASKSS               RTC_ALRMASSR_MASKSS_Msk
24322 #define RTC_ALRMASSR_MASKSS_0             (0x1U << RTC_ALRMASSR_MASKSS_Pos)    /*!< 0x01000000 */
24323 #define RTC_ALRMASSR_MASKSS_1             (0x2U << RTC_ALRMASSR_MASKSS_Pos)    /*!< 0x02000000 */
24324 #define RTC_ALRMASSR_MASKSS_2             (0x4U << RTC_ALRMASSR_MASKSS_Pos)    /*!< 0x04000000 */
24325 #define RTC_ALRMASSR_MASKSS_3             (0x8U << RTC_ALRMASSR_MASKSS_Pos)    /*!< 0x08000000 */
24326 #define RTC_ALRMASSR_SS_Pos               (0U)
24327 #define RTC_ALRMASSR_SS_Msk               (0x7FFFU << RTC_ALRMASSR_SS_Pos)     /*!< 0x00007FFF */
24328 #define RTC_ALRMASSR_SS                   RTC_ALRMASSR_SS_Msk
24329 
24330 /********************  Bits definition for RTC_ALRMBR register  ***************/
24331 #define RTC_ALRMBR_MSK4_Pos               (31U)
24332 #define RTC_ALRMBR_MSK4_Msk               (0x1U << RTC_ALRMBR_MSK4_Pos)        /*!< 0x80000000 */
24333 #define RTC_ALRMBR_MSK4                   RTC_ALRMBR_MSK4_Msk
24334 #define RTC_ALRMBR_WDSEL_Pos              (30U)
24335 #define RTC_ALRMBR_WDSEL_Msk              (0x1U << RTC_ALRMBR_WDSEL_Pos)       /*!< 0x40000000 */
24336 #define RTC_ALRMBR_WDSEL                  RTC_ALRMBR_WDSEL_Msk
24337 #define RTC_ALRMBR_DT_Pos                 (28U)
24338 #define RTC_ALRMBR_DT_Msk                 (0x3U << RTC_ALRMBR_DT_Pos)          /*!< 0x30000000 */
24339 #define RTC_ALRMBR_DT                     RTC_ALRMBR_DT_Msk
24340 #define RTC_ALRMBR_DT_0                   (0x1U << RTC_ALRMBR_DT_Pos)          /*!< 0x10000000 */
24341 #define RTC_ALRMBR_DT_1                   (0x2U << RTC_ALRMBR_DT_Pos)          /*!< 0x20000000 */
24342 #define RTC_ALRMBR_DU_Pos                 (24U)
24343 #define RTC_ALRMBR_DU_Msk                 (0xFU << RTC_ALRMBR_DU_Pos)          /*!< 0x0F000000 */
24344 #define RTC_ALRMBR_DU                     RTC_ALRMBR_DU_Msk
24345 #define RTC_ALRMBR_DU_0                   (0x1U << RTC_ALRMBR_DU_Pos)          /*!< 0x01000000 */
24346 #define RTC_ALRMBR_DU_1                   (0x2U << RTC_ALRMBR_DU_Pos)          /*!< 0x02000000 */
24347 #define RTC_ALRMBR_DU_2                   (0x4U << RTC_ALRMBR_DU_Pos)          /*!< 0x04000000 */
24348 #define RTC_ALRMBR_DU_3                   (0x8U << RTC_ALRMBR_DU_Pos)          /*!< 0x08000000 */
24349 #define RTC_ALRMBR_MSK3_Pos               (23U)
24350 #define RTC_ALRMBR_MSK3_Msk               (0x1U << RTC_ALRMBR_MSK3_Pos)        /*!< 0x00800000 */
24351 #define RTC_ALRMBR_MSK3                   RTC_ALRMBR_MSK3_Msk
24352 #define RTC_ALRMBR_PM_Pos                 (22U)
24353 #define RTC_ALRMBR_PM_Msk                 (0x1U << RTC_ALRMBR_PM_Pos)          /*!< 0x00400000 */
24354 #define RTC_ALRMBR_PM                     RTC_ALRMBR_PM_Msk
24355 #define RTC_ALRMBR_HT_Pos                 (20U)
24356 #define RTC_ALRMBR_HT_Msk                 (0x3U << RTC_ALRMBR_HT_Pos)          /*!< 0x00300000 */
24357 #define RTC_ALRMBR_HT                     RTC_ALRMBR_HT_Msk
24358 #define RTC_ALRMBR_HT_0                   (0x1U << RTC_ALRMBR_HT_Pos)          /*!< 0x00100000 */
24359 #define RTC_ALRMBR_HT_1                   (0x2U << RTC_ALRMBR_HT_Pos)          /*!< 0x00200000 */
24360 #define RTC_ALRMBR_HU_Pos                 (16U)
24361 #define RTC_ALRMBR_HU_Msk                 (0xFU << RTC_ALRMBR_HU_Pos)          /*!< 0x000F0000 */
24362 #define RTC_ALRMBR_HU                     RTC_ALRMBR_HU_Msk
24363 #define RTC_ALRMBR_HU_0                   (0x1U << RTC_ALRMBR_HU_Pos)          /*!< 0x00010000 */
24364 #define RTC_ALRMBR_HU_1                   (0x2U << RTC_ALRMBR_HU_Pos)          /*!< 0x00020000 */
24365 #define RTC_ALRMBR_HU_2                   (0x4U << RTC_ALRMBR_HU_Pos)          /*!< 0x00040000 */
24366 #define RTC_ALRMBR_HU_3                   (0x8U << RTC_ALRMBR_HU_Pos)          /*!< 0x00080000 */
24367 #define RTC_ALRMBR_MSK2_Pos               (15U)
24368 #define RTC_ALRMBR_MSK2_Msk               (0x1U << RTC_ALRMBR_MSK2_Pos)        /*!< 0x00008000 */
24369 #define RTC_ALRMBR_MSK2                   RTC_ALRMBR_MSK2_Msk
24370 #define RTC_ALRMBR_MNT_Pos                (12U)
24371 #define RTC_ALRMBR_MNT_Msk                (0x7U << RTC_ALRMBR_MNT_Pos)         /*!< 0x00007000 */
24372 #define RTC_ALRMBR_MNT                    RTC_ALRMBR_MNT_Msk
24373 #define RTC_ALRMBR_MNT_0                  (0x1U << RTC_ALRMBR_MNT_Pos)         /*!< 0x00001000 */
24374 #define RTC_ALRMBR_MNT_1                  (0x2U << RTC_ALRMBR_MNT_Pos)         /*!< 0x00002000 */
24375 #define RTC_ALRMBR_MNT_2                  (0x4U << RTC_ALRMBR_MNT_Pos)         /*!< 0x00004000 */
24376 #define RTC_ALRMBR_MNU_Pos                (8U)
24377 #define RTC_ALRMBR_MNU_Msk                (0xFU << RTC_ALRMBR_MNU_Pos)         /*!< 0x00000F00 */
24378 #define RTC_ALRMBR_MNU                    RTC_ALRMBR_MNU_Msk
24379 #define RTC_ALRMBR_MNU_0                  (0x1U << RTC_ALRMBR_MNU_Pos)         /*!< 0x00000100 */
24380 #define RTC_ALRMBR_MNU_1                  (0x2U << RTC_ALRMBR_MNU_Pos)         /*!< 0x00000200 */
24381 #define RTC_ALRMBR_MNU_2                  (0x4U << RTC_ALRMBR_MNU_Pos)         /*!< 0x00000400 */
24382 #define RTC_ALRMBR_MNU_3                  (0x8U << RTC_ALRMBR_MNU_Pos)         /*!< 0x00000800 */
24383 #define RTC_ALRMBR_MSK1_Pos               (7U)
24384 #define RTC_ALRMBR_MSK1_Msk               (0x1U << RTC_ALRMBR_MSK1_Pos)        /*!< 0x00000080 */
24385 #define RTC_ALRMBR_MSK1                   RTC_ALRMBR_MSK1_Msk
24386 #define RTC_ALRMBR_ST_Pos                 (4U)
24387 #define RTC_ALRMBR_ST_Msk                 (0x7U << RTC_ALRMBR_ST_Pos)          /*!< 0x00000070 */
24388 #define RTC_ALRMBR_ST                     RTC_ALRMBR_ST_Msk
24389 #define RTC_ALRMBR_ST_0                   (0x1U << RTC_ALRMBR_ST_Pos)          /*!< 0x00000010 */
24390 #define RTC_ALRMBR_ST_1                   (0x2U << RTC_ALRMBR_ST_Pos)          /*!< 0x00000020 */
24391 #define RTC_ALRMBR_ST_2                   (0x4U << RTC_ALRMBR_ST_Pos)          /*!< 0x00000040 */
24392 #define RTC_ALRMBR_SU_Pos                 (0U)
24393 #define RTC_ALRMBR_SU_Msk                 (0xFU << RTC_ALRMBR_SU_Pos)          /*!< 0x0000000F */
24394 #define RTC_ALRMBR_SU                     RTC_ALRMBR_SU_Msk
24395 #define RTC_ALRMBR_SU_0                   (0x1U << RTC_ALRMBR_SU_Pos)          /*!< 0x00000001 */
24396 #define RTC_ALRMBR_SU_1                   (0x2U << RTC_ALRMBR_SU_Pos)          /*!< 0x00000002 */
24397 #define RTC_ALRMBR_SU_2                   (0x4U << RTC_ALRMBR_SU_Pos)          /*!< 0x00000004 */
24398 #define RTC_ALRMBR_SU_3                   (0x8U << RTC_ALRMBR_SU_Pos)          /*!< 0x00000008 */
24399 
24400 /********************  Bits definition for RTC_ALRMBSSR register  *************/
24401 #define RTC_ALRMBSSR_MASKSS_Pos           (24U)
24402 #define RTC_ALRMBSSR_MASKSS_Msk           (0xFU << RTC_ALRMBSSR_MASKSS_Pos)    /*!< 0x0F000000 */
24403 #define RTC_ALRMBSSR_MASKSS               RTC_ALRMBSSR_MASKSS_Msk
24404 #define RTC_ALRMBSSR_MASKSS_0             (0x1U << RTC_ALRMBSSR_MASKSS_Pos)    /*!< 0x01000000 */
24405 #define RTC_ALRMBSSR_MASKSS_1             (0x2U << RTC_ALRMBSSR_MASKSS_Pos)    /*!< 0x02000000 */
24406 #define RTC_ALRMBSSR_MASKSS_2             (0x4U << RTC_ALRMBSSR_MASKSS_Pos)    /*!< 0x04000000 */
24407 #define RTC_ALRMBSSR_MASKSS_3             (0x8U << RTC_ALRMBSSR_MASKSS_Pos)    /*!< 0x08000000 */
24408 #define RTC_ALRMBSSR_SS_Pos               (0U)
24409 #define RTC_ALRMBSSR_SS_Msk               (0x7FFFU << RTC_ALRMBSSR_SS_Pos)     /*!< 0x00007FFF */
24410 #define RTC_ALRMBSSR_SS                   RTC_ALRMBSSR_SS_Msk
24411 
24412 /********************  Bits definition for RTC_SR register  *************/
24413 #define RTC_SR_ITSF_Pos                   (5U)
24414 #define RTC_SR_ITSF_Msk                   (0x1U << RTC_SR_ITSF_Pos)            /*!< 0x00000020 */
24415 #define RTC_SR_ITSF                       RTC_SR_ITSF_Msk
24416 #define RTC_SR_TSOVF_Pos                  (4U)
24417 #define RTC_SR_TSOVF_Msk                  (0x1U << RTC_SR_TSOVF_Pos)           /*!< 0x00000010 */
24418 #define RTC_SR_TSOVF                      RTC_SR_TSOVF_Msk
24419 #define RTC_SR_TSF_Pos                    (3U)
24420 #define RTC_SR_TSF_Msk                    (0x1U << RTC_SR_TSF_Pos)             /*!< 0x00000008 */
24421 #define RTC_SR_TSF                        RTC_SR_TSF_Msk
24422 #define RTC_SR_WUTF_Pos                   (2U)
24423 #define RTC_SR_WUTF_Msk                   (0x1U << RTC_SR_WUTF_Pos)            /*!< 0x00000004 */
24424 #define RTC_SR_WUTF                       RTC_SR_WUTF_Msk
24425 #define RTC_SR_ALRBF_Pos                  (1U)
24426 #define RTC_SR_ALRBF_Msk                  (0x1U << RTC_SR_ALRBF_Pos)           /*!< 0x00000002 */
24427 #define RTC_SR_ALRBF                      RTC_SR_ALRBF_Msk
24428 #define RTC_SR_ALRAF_Pos                  (0U)
24429 #define RTC_SR_ALRAF_Msk                  (0x1U << RTC_SR_ALRAF_Pos)           /*!< 0x00000001 */
24430 #define RTC_SR_ALRAF                      RTC_SR_ALRAF_Msk
24431 
24432 /********************  Bits definition for RTC_MISR register  *************/
24433 #define RTC_MISR_ITSMF_Pos                (5U)
24434 #define RTC_MISR_ITSMF_Msk                (0x1U << RTC_MISR_ITSMF_Pos)         /*!< 0x00000020 */
24435 #define RTC_MISR_ITSMF                    RTC_MISR_ITSMF_Msk
24436 #define RTC_MISR_TSOVMF_Pos               (4U)
24437 #define RTC_MISR_TSOVMF_Msk               (0x1U << RTC_MISR_TSOVMF_Pos)        /*!< 0x00000010 */
24438 #define RTC_MISR_TSOVMF                   RTC_MISR_TSOVMF_Msk
24439 #define RTC_MISR_TSMF_Pos                 (3U)
24440 #define RTC_MISR_TSMF_Msk                 (0x1U << RTC_MISR_TSMF_Pos)          /*!< 0x00000008 */
24441 #define RTC_MISR_TSMF                     RTC_MISR_TSMF_Msk
24442 #define RTC_MISR_WUTMF_Pos                (2U)
24443 #define RTC_MISR_WUTMF_Msk                (0x1U << RTC_MISR_WUTMF_Pos)         /*!< 0x00000004 */
24444 #define RTC_MISR_WUTMF                    RTC_MISR_WUTMF_Msk
24445 #define RTC_MISR_ALRBMF_Pos               (1U)
24446 #define RTC_MISR_ALRBMF_Msk               (0x1U << RTC_MISR_ALRBMF_Pos)        /*!< 0x00000002 */
24447 #define RTC_MISR_ALRBMF                   RTC_MISR_ALRBMF_Msk
24448 #define RTC_MISR_ALRAMF_Pos               (0U)
24449 #define RTC_MISR_ALRAMF_Msk               (0x1U << RTC_MISR_ALRAMF_Pos)        /*!< 0x00000001 */
24450 #define RTC_MISR_ALRAMF                   RTC_MISR_ALRAMF_Msk
24451 
24452 /********************  Bits definition for RTC_SMISR register  *************/
24453 #define RTC_SMISR_ITSMF_Pos               (5U)
24454 #define RTC_SMISR_ITSMF_Msk               (0x1U << RTC_SMISR_ITSMF_Pos)        /*!< 0x00000020 */
24455 #define RTC_SMISR_ITSMF                   RTC_SMISR_ITSMF_Msk
24456 #define RTC_SMISR_TSOVMF_Pos              (4U)
24457 #define RTC_SMISR_TSOVMF_Msk              (0x1U << RTC_SMISR_TSOVMF_Pos)       /*!< 0x00000010 */
24458 #define RTC_SMISR_TSOVMF                  RTC_SMISR_TSOVMF_Msk
24459 #define RTC_SMISR_TSMF_Pos                (3U)
24460 #define RTC_SMISR_TSMF_Msk                (0x1U << RTC_SMISR_TSMF_Pos)         /*!< 0x00000008 */
24461 #define RTC_SMISR_TSMF                    RTC_SMISR_TSMF_Msk
24462 #define RTC_SMISR_WUTMF_Pos               (2U)
24463 #define RTC_SMISR_WUTMF_Msk               (0x1U << RTC_SMISR_WUTMF_Pos)        /*!< 0x00000004 */
24464 #define RTC_SMISR_WUTMF                   RTC_SMISR_WUTMF_Msk
24465 #define RTC_SMISR_ALRBMF_Pos              (1U)
24466 #define RTC_SMISR_ALRBMF_Msk              (0x1U << RTC_SMISR_ALRBMF_Pos)       /*!< 0x00000002 */
24467 #define RTC_SMISR_ALRBMF                  RTC_SMISR_ALRBMF_Msk
24468 #define RTC_SMISR_ALRAMF_Pos              (0U)
24469 #define RTC_SMISR_ALRAMF_Msk              (0x1U << RTC_SMISR_ALRAMF_Pos)       /*!< 0x00000001 */
24470 #define RTC_SMISR_ALRAMF                  RTC_SMISR_ALRAMF_Msk
24471 
24472 /********************  Bits definition for RTC_SCR register  *************/
24473 #define RTC_SCR_CITSF_Pos                 (5U)
24474 #define RTC_SCR_CITSF_Msk                 (0x1U << RTC_SCR_CITSF_Pos)          /*!< 0x00000020 */
24475 #define RTC_SCR_CITSF                     RTC_SCR_CITSF_Msk
24476 #define RTC_SCR_CTSOVF_Pos                (4U)
24477 #define RTC_SCR_CTSOVF_Msk                (0x1U << RTC_SCR_CTSOVF_Pos)         /*!< 0x00000010 */
24478 #define RTC_SCR_CTSOVF                    RTC_SCR_CTSOVF_Msk
24479 #define RTC_SCR_CTSF_Pos                  (3U)
24480 #define RTC_SCR_CTSF_Msk                  (0x1U << RTC_SCR_CTSF_Pos)           /*!< 0x00000008 */
24481 #define RTC_SCR_CTSF                      RTC_SCR_CTSF_Msk
24482 #define RTC_SCR_CWUTF_Pos                 (2U)
24483 #define RTC_SCR_CWUTF_Msk                 (0x1U << RTC_SCR_CWUTF_Pos)          /*!< 0x00000004 */
24484 #define RTC_SCR_CWUTF                     RTC_SCR_CWUTF_Msk
24485 #define RTC_SCR_CALRBF_Pos                (1U)
24486 #define RTC_SCR_CALRBF_Msk                (0x1U << RTC_SCR_CALRBF_Pos)         /*!< 0x00000002 */
24487 #define RTC_SCR_CALRBF                    RTC_SCR_CALRBF_Msk
24488 #define RTC_SCR_CALRAF_Pos                (0U)
24489 #define RTC_SCR_CALRAF_Msk                (0x1U << RTC_SCR_CALRAF_Pos)         /*!< 0x00000001 */
24490 #define RTC_SCR_CALRAF                    RTC_SCR_CALRAF_Msk
24491 
24492 /********************  Bits definition for RTC_OR register  ****************/
24493 #define RTC_CFGR_LSCOEN_Pos               (1U)
24494 #define RTC_CFGR_LSCOEN_Msk               (0x3U << RTC_CFGR_LSCOEN_Pos)        /*!< 0x00000006 */
24495 #define RTC_CFGR_LSCOEN                   RTC_CFGR_LSCOEN_Msk
24496 #define RTC_CFGR_LSCOEN_0                 (0x1U << RTC_CFGR_LSCOEN_Pos)        /*!< 0x00000002 */
24497 #define RTC_CFGR_LSCOEN_1                 (0x2U << RTC_CFGR_LSCOEN_Pos)        /*!< 0x00000004 */
24498 #define RTC_CFGR_OUT2_RMP_Pos             (0U)
24499 #define RTC_CFGR_OUT2_RMP_Msk             (0x1U << RTC_OR_OUT2_RMP_Pos)        /*!< 0x00000001 */
24500 #define RTC_CFGR_OUT2_RMP                 RTC_OR_OUT2_RMP_Msk
24501 
24502 /********************  Bits definition for RTC_HWCFGR register  *************/
24503 
24504 #define RTC_HWCFGR_TRUST_ZONE_Pos         (24U)
24505 #define RTC_HWCFGR_TRUST_ZONE_Msk         (0xFU << RTC_HWCFGR_TRUST_ZONE_Pos)  /*!< 0x0F000000 */
24506 #define RTC_HWCFGR_TRUST_ZONE             RTC_HWCFGR_TRUST_ZONE_Msk
24507 #define RTC_HWCFGR_TRUST_ZONE_0           (0x1U << RTC_HWCFGR_TRUST_ZONE_Pos)  /*!< 0x01000000 */
24508 #define RTC_HWCFGR_TRUST_ZONE_1           (0x2U << RTC_HWCFGR_TRUST_ZONE_Pos)  /*!< 0x02000000 */
24509 #define RTC_HWCFGR_TRUST_ZONE_2           (0x4U << RTC_HWCFGR_TRUST_ZONE_Pos)  /*!< 0x04000000 */
24510 #define RTC_HWCFGR_TRUST_ZONE_3           (0x8U << RTC_HWCFGR_TRUST_ZONE_Pos)  /*!< 0x08000000 */
24511 
24512 #define RTC_HWCFGR_OPTIONREG_OUT_Pos      (16U)
24513 #define RTC_HWCFGR_OPTIONREG_OUT_Msk      (0xFFU << RTC_HWCFGR_OPTIONREG_OUT_Pos) /*!< 0x00FF0000 */
24514 #define RTC_HWCFGR_OPTIONREG_OUT          RTC_HWCFGR_OPTIONREG_OUT_Msk
24515 #define RTC_HWCFGR_OPTIONREG_OUT_0        (0x01U << RTC_HWCFGR_OPTIONREG_OUT_Pos) /*!< 0x00010000 */
24516 #define RTC_HWCFGR_OPTIONREG_OUT_1        (0x02U << RTC_HWCFGR_OPTIONREG_OUT_Pos) /*!< 0x00020000 */
24517 #define RTC_HWCFGR_OPTIONREG_OUT_2        (0x04U << RTC_HWCFGR_OPTIONREG_OUT_Pos) /*!< 0x00040000 */
24518 #define RTC_HWCFGR_OPTIONREG_OUT_3        (0x08U << RTC_HWCFGR_OPTIONREG_OUT_Pos) /*!< 0x00080000 */
24519 #define RTC_HWCFGR_OPTIONREG_OUT_4        (0x10U << RTC_HWCFGR_OPTIONREG_OUT_Pos) /*!< 0x00100000 */
24520 #define RTC_HWCFGR_OPTIONREG_OUT_5        (0x20U << RTC_HWCFGR_OPTIONREG_OUT_Pos) /*!< 0x00200000 */
24521 #define RTC_HWCFGR_OPTIONREG_OUT_6        (0x40U << RTC_HWCFGR_OPTIONREG_OUT_Pos) /*!< 0x00400000 */
24522 #define RTC_HWCFGR_OPTIONREG_OUT_7        (0x80U << RTC_HWCFGR_OPTIONREG_OUT_Pos) /*!< 0x00800000 */
24523 
24524 #define RTC_HWCFGR_TIMESTAMP_Pos          (12U)
24525 #define RTC_HWCFGR_TIMESTAMP_Msk          (0xFU << RTC_HWCFGR_TIMESTAMP_Pos)   /*!< 0x0000F000 */
24526 #define RTC_HWCFGR_TIMESTAMP              RTC_HWCFGR_TIMESTAMP_Msk
24527 #define RTC_HWCFGR_TIMESTAMP_0            (0x1U << RTC_HWCFGR_TIMESTAMP_Pos)   /*!< 0x00001000 */
24528 #define RTC_HWCFGR_TIMESTAMP_1            (0x2U << RTC_HWCFGR_TIMESTAMP_Pos)   /*!< 0x00002000 */
24529 #define RTC_HWCFGR_TIMESTAMP_2            (0x4U << RTC_HWCFGR_TIMESTAMP_Pos)   /*!< 0x00004000 */
24530 #define RTC_HWCFGR_TIMESTAMP_3            (0x8U << RTC_HWCFGR_TIMESTAMP_Pos)   /*!< 0x00008000 */
24531 
24532 #define RTC_HWCFGR_SMOOTH_CALIB_Pos       (8U)
24533 #define RTC_HWCFGR_SMOOTH_CALIB_Msk       (0xFU << RTC_HWCFGR_SMOOTH_CALIB_Pos) /*!< 0x00000F00 */
24534 #define RTC_HWCFGR_SMOOTH_CALIB           RTC_HWCFGR_SMOOTH_CALIB_Msk
24535 #define RTC_HWCFGR_SMOOTH_CALIB_0         (0x1U << RTC_HWCFGR_SMOOTH_CALIB_Pos) /*!< 0x00000100 */
24536 #define RTC_HWCFGR_SMOOTH_CALIB_1         (0x2U << RTC_HWCFGR_SMOOTH_CALIB_Pos) /*!< 0x00000200 */
24537 #define RTC_HWCFGR_SMOOTH_CALIB_2         (0x4U << RTC_HWCFGR_SMOOTH_CALIB_Pos) /*!< 0x00000400 */
24538 #define RTC_HWCFGR_SMOOTH_CALIB_3         (0x8U << RTC_HWCFGR_SMOOTH_CALIB_Pos) /*!< 0x00000800 */
24539 
24540 #define RTC_HWCFGR_WAKEUP_Pos             (4U)
24541 #define RTC_HWCFGR_WAKEUP_Msk             (0xFU << RTC_HWCFGR_WAKEUP_Pos)      /*!< 0x000000F0 */
24542 #define RTC_HWCFGR_WAKEUP                 RTC_HWCFGR_WAKEUP_Msk
24543 #define RTC_HWCFGR_WAKEUP_0               (0x1U << RTC_HWCFGR_WAKEUP_Pos)      /*!< 0x00000010 */
24544 #define RTC_HWCFGR_WAKEUP_1               (0x2U << RTC_HWCFGR_WAKEUP_Pos)      /*!< 0x00000020 */
24545 #define RTC_HWCFGR_WAKEUP_2               (0x4U << RTC_HWCFGR_WAKEUP_Pos)      /*!< 0x00000040 */
24546 #define RTC_HWCFGR_WAKEUP_3               (0x8U << RTC_HWCFGR_WAKEUP_Pos)      /*!< 0x00000080 */
24547 
24548 #define RTC_HWCFGR_ALARMB_Pos             (0U)
24549 #define RTC_HWCFGR_ALARMB_Msk             (0xFU << RTC_HWCFGR_ALARMB_Pos)      /*!< 0x0000000F */
24550 #define RTC_HWCFGR_ALARMB                 RTC_HWCFGR_ALARMB_Msk
24551 #define RTC_HWCFGR_ALARMB_0               (0x1U << RTC_HWCFGR_ALARMB_Pos)      /*!< 0x00000001 */
24552 #define RTC_HWCFGR_ALARMB_1               (0x2U << RTC_HWCFGR_ALARMB_Pos)      /*!< 0x00000002 */
24553 #define RTC_HWCFGR_ALARMB_2               (0x4U << RTC_HWCFGR_ALARMB_Pos)      /*!< 0x00000004 */
24554 #define RTC_HWCFGR_ALARMB_3               (0x8U << RTC_HWCFGR_ALARMB_Pos)      /*!< 0x00000008 */
24555 
24556 
24557 /********************  Bits definition for RTC_VERR register  ****************/
24558 #define RTC_VERR_MAJREV_Pos               (4U)
24559 #define RTC_VERR_MAJREV_Msk               (0xFU << RTC_VERR_MAJREV_Pos)        /*!< 0x000000F0 */
24560 #define RTC_VERR_MAJREV                   RTC_VERR_MAJREV_Msk
24561 #define RTC_VERR_MAJREV_0                 (0x1U << RTC_VERR_MAJREV_Pos)        /*!< 0x00000010 */
24562 #define RTC_VERR_MAJREV_1                 (0x2U << RTC_VERR_MAJREV_Pos)        /*!< 0x00000020 */
24563 #define RTC_VERR_MAJREV_2                 (0x4U << RTC_VERR_MAJREV_Pos)        /*!< 0x00000040 */
24564 #define RTC_VERR_MAJREV_3                 (0x8U << RTC_VERR_MAJREV_Pos)        /*!< 0x00000080 */
24565 #define RTC_VERR_MINREV_Pos               (0U)
24566 #define RTC_VERR_MINREV_Msk               (0xFU << RTC_VERR_MINREV_Pos)        /*!< 0x0000000F */
24567 #define RTC_VERR_MINREV                   RTC_VERR_MINREV_Msk
24568 #define RTC_VERR_MINREV_0                 (0x1U << RTC_VERR_MINREV_Pos)        /*!< 0x00000001 */
24569 #define RTC_VERR_MINREV_1                 (0x2U << RTC_VERR_MINREV_Pos)        /*!< 0x00000002 */
24570 #define RTC_VERR_MINREV_2                 (0x4U << RTC_VERR_MINREV_Pos)        /*!< 0x00000004 */
24571 #define RTC_VERR_MINREV_3                 (0x8U << RTC_VERR_MINREV_Pos)        /*!< 0x00000008 */
24572 
24573 /********************  Bits definition for RTC_IPIDR register  ****************/
24574 #define RTC_IPIDR_ID_Pos                  (0U)
24575 #define RTC_IPIDR_ID_Msk                  (0xFFFFFFFFU << RTC_IPIDR_ID_Pos)    /*!< 0xFFFFFFFF */
24576 #define RTC_IPIDR_ID                      RTC_IPIDR_ID_Msk
24577 
24578 /********************  Bits definition for RTC_SIDR register  ****************/
24579 #define RTC_SIDR_SID_Pos                  (0U)
24580 #define RTC_SIDR_SID_Msk                  (0xFFFFFFFFU << RTC_SIDR_SID_Pos)    /*!< 0xFFFFFFFF */
24581 #define RTC_SIDR_SID                      RTC_SIDR_SID_Msk
24582 
24583 /******************************************************************************/
24584 /*                                                                            */
24585 /*                           Tamper and Backup registers (TAMP)               */
24586 /*                                                                            */
24587 /******************************************************************************/
24588 
24589 /********************  Bits definition for TAMP_CR1 register  ***************/
24590 #define TAMP_CR1_TAMPE_Pos                  (0U)
24591 #define TAMP_CR1_TAMPE_Msk                  (0x7U << TAMP_CR1_TAMPE_Pos)      /*!< 0x000000FF */
24592 #define TAMP_CR1_TAMPE                      TAMP_CR1_TAMPE_Msk
24593 #define TAMP_CR1_TAMP1E_Pos                 (0U)
24594 #define TAMP_CR1_TAMP1E_Msk                 (0x1U << TAMP_CR1_TAMP1E_Pos)      /*!< 0x00000001 */
24595 #define TAMP_CR1_TAMP1E                     TAMP_CR1_TAMP1E_Msk
24596 #define TAMP_CR1_TAMP2E_Pos                 (1U)
24597 #define TAMP_CR1_TAMP2E_Msk                 (0x1U << TAMP_CR1_TAMP2E_Pos)      /*!< 0x00000002 */
24598 #define TAMP_CR1_TAMP2E                     TAMP_CR1_TAMP2E_Msk
24599 #define TAMP_CR1_TAMP3E_Pos                 (2U)
24600 #define TAMP_CR1_TAMP3E_Msk                 (0x1U << TAMP_CR1_TAMP3E_Pos)      /*!< 0x00000004 */
24601 #define TAMP_CR1_TAMP3E                     TAMP_CR1_TAMP3E_Msk
24602 #define TAMP_CR1_ITAMPE_Pos                 (16U)
24603 #define TAMP_CR1_ITAMPE_Msk                 (0x9FU << TAMP_CR1_ITAMPE_Pos)   /*!< 0xFFFF0000 */
24604 #define TAMP_CR1_ITAMPE                     TAMP_CR1_ITAMPE_Msk
24605 #define TAMP_CR1_ITAMP1E_Pos                (16U)
24606 #define TAMP_CR1_ITAMP1E_Msk                (0x1U << TAMP_CR1_ITAMP1E_Pos)     /*!< 0x00010000 */
24607 #define TAMP_CR1_ITAMP1E                    TAMP_CR1_ITAMP1E_Msk
24608 #define TAMP_CR1_ITAMP2E_Pos                (17U)
24609 #define TAMP_CR1_ITAMP2E_Msk                (0x1U << TAMP_CR1_ITAMP2E_Pos)     /*!< 0x00020000 */
24610 #define TAMP_CR1_ITAMP2E                    TAMP_CR1_ITAMP2E_Msk
24611 #define TAMP_CR1_ITAMP3E_Pos                (18U)
24612 #define TAMP_CR1_ITAMP3E_Msk                (0x1U << TAMP_CR1_ITAMP3E_Pos)     /*!< 0x00040000 */
24613 #define TAMP_CR1_ITAMP3E                    TAMP_CR1_ITAMP3E_Msk
24614 #define TAMP_CR1_ITAMP4E_Pos                (19U)
24615 #define TAMP_CR1_ITAMP4E_Msk                (0x1U << TAMP_CR1_ITAMP4E_Pos)     /*!< 0x00080000 */
24616 #define TAMP_CR1_ITAMP4E                    TAMP_CR1_ITAMP4E_Msk
24617 #define TAMP_CR1_ITAMP5E_Pos                (20U)
24618 #define TAMP_CR1_ITAMP5E_Msk                (0x1U << TAMP_CR1_ITAMP5E_Pos)     /*!< 0x00100000 */
24619 #define TAMP_CR1_ITAMP5E                    TAMP_CR1_ITAMP5E_Msk
24620 #define TAMP_CR1_ITAMP8E_Pos                (23U)
24621 #define TAMP_CR1_ITAMP8E_Msk                (0x1U << TAMP_CR1_ITAMP8E_Pos)     /*!< 0x00800000 */
24622 #define TAMP_CR1_ITAMP8E                    TAMP_CR1_ITAMP8E_Msk
24623 
24624 
24625 /********************  Bits definition for TAMP_CR2 register  ***************/
24626 #define TAMP_CR2_TAMPNOERASE_Pos     (0U)
24627 #define TAMP_CR2_TAMPNOERase_Msk     (0x7U << TAMP_CR2_TAMPNOERASE_Pos)   /*!< 0x000000FF */
24628 #define TAMP_CR2_TAMPNOER            TAMP_CR2_TAMPNOERase_Msk
24629 #define TAMP_CR2_TAMP1NOERASE_Pos    (0U)
24630 #define TAMP_CR2_TAMP1NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos)      /*!< 0x00000001 */
24631 #define TAMP_CR2_TAMP1NOERASE        TAMP_CR2_TAMP1NOERASE_Msk
24632 #define TAMP_CR2_TAMP2NOERASE_Pos    (1U)
24633 #define TAMP_CR2_TAMP2NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos)      /*!< 0x00000002 */
24634 #define TAMP_CR2_TAMP2NOERASE        TAMP_CR2_TAMP2NOERASE_Msk
24635 #define TAMP_CR2_TAMP3NOERASE_Pos    (2U)
24636 #define TAMP_CR2_TAMP3NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos)      /*!< 0x00000004 */
24637 #define TAMP_CR2_TAMP3NOERASE        TAMP_CR2_TAMP3NOERASE_Msk
24638 #define TAMP_CR2_TAMPMSK_Pos         (16U)
24639 #define TAMP_CR2_TAMPMSK_Msk         (0x7U << TAMP_CR2_TAMPMSK_Pos)     /*!< 0x00FF0000 */
24640 #define TAMP_CR2_TAMPMSK             TAMP_CR2_TAMPMSK_Msk
24641 #define TAMP_CR2_TAMP1MSK_Pos        (16U)
24642 #define TAMP_CR2_TAMP1MSK_Msk        (0x1UL << TAMP_CR2_TAMP1MSK_Pos)          /*!< 0x00010000 */
24643 #define TAMP_CR2_TAMP1MSK            TAMP_CR2_TAMP1MSK_Msk
24644 #define TAMP_CR2_TAMP2MSK_Pos        (17U)
24645 #define TAMP_CR2_TAMP2MSK_Msk        (0x1UL << TAMP_CR2_TAMP2MSK_Pos)          /*!< 0x00020000 */
24646 #define TAMP_CR2_TAMP2MSK            TAMP_CR2_TAMP2MSK_Msk
24647 #define TAMP_CR2_TAMP3MSK_Pos        (18U)
24648 #define TAMP_CR2_TAMP3MSK_Msk        (0x1UL << TAMP_CR2_TAMP3MSK_Pos)          /*!< 0x00040000 */
24649 #define TAMP_CR2_TAMP3MSK            TAMP_CR2_TAMP3MSK_Msk
24650 #define TAMP_CR2_TAMPTRG_Pos          (24U)
24651 #define TAMP_CR2_TAMPTRG_Msk          (0xFFU << TAMP_CR2_TAMPTRG_Pos)    /*!< 0xFF000000 */
24652 #define TAMP_CR2_TAMPTRG              TAMP_CR2_TAMPTRG_Msk
24653 #define TAMP_CR2_TAMP1TRG_Pos         (24U)
24654 #define TAMP_CR2_TAMP1TRG_Msk         (0x1U << TAMP_CR2_TAMP1TRG_Pos)    /*!< 0x01000000 */
24655 #define TAMP_CR2_TAMP1TRG             TAMP_CR2_TAMP1TRG_Msk
24656 #define TAMP_CR2_TAMP2TRG_Pos         (25U)
24657 #define TAMP_CR2_TAMP2TRG_Msk         (0x1U << TAMP_CR2_TAMP2TRG_Pos)    /*!< 0x02000000 */
24658 #define TAMP_CR2_TAMP2TRG             TAMP_CR2_TAMP2TRG_Msk
24659 #define TAMP_CR2_TAMP3TRG_Pos         (26U)
24660 #define TAMP_CR2_TAMP3TRG_Msk         (0x1U << TAMP_CR2_TAMP3TRG_Pos)    /*!< 0x04000000 */
24661 #define TAMP_CR2_TAMP3TRG             TAMP_CR2_TAMP3TRG_Msk
24662 
24663 
24664 /********************  Bits definition for TAMP_FLTCR register  ***************/
24665 #define TAMP_FLTCR_TAMPFREQ_Pos             (0U)
24666 #define TAMP_FLTCR_TAMPFREQ_Msk             (0x7U << TAMP_FLTCR_TAMPFREQ_Pos)  /*!< 0x00000007 */
24667 #define TAMP_FLTCR_TAMPFREQ                 TAMP_FLTCR_TAMPFREQ_Msk
24668 #define TAMP_FLTCR_TAMPFREQ_0               (0x1U << TAMP_FLTCR_TAMPFREQ_Pos)  /*!< 0x00000001 */
24669 #define TAMP_FLTCR_TAMPFREQ_1               (0x2U << TAMP_FLTCR_TAMPFREQ_Pos)  /*!< 0x00000002 */
24670 #define TAMP_FLTCR_TAMPFREQ_2               (0x4U << TAMP_FLTCR_TAMPFREQ_Pos)  /*!< 0x00000004 */
24671 #define TAMP_FLTCR_TAMPFLT_Pos              (3U)
24672 #define TAMP_FLTCR_TAMPFLT_Msk              (0x3U << TAMP_FLTCR_TAMPFLT_Pos)   /*!< 0x00000018 */
24673 #define TAMP_FLTCR_TAMPFLT                  TAMP_FLTCR_TAMPFLT_Msk
24674 #define TAMP_FLTCR_TAMPFLT_0                (0x1U << TAMP_FLTCR_TAMPFLT_Pos)   /*!< 0x00000008 */
24675 #define TAMP_FLTCR_TAMPFLT_1                (0x2U << TAMP_FLTCR_TAMPFLT_Pos)   /*!< 0x00000010 */
24676 #define TAMP_FLTCR_TAMPPRCH_Pos             (5U)
24677 #define TAMP_FLTCR_TAMPPRCH_Msk             (0x3U << TAMP_FLTCR_TAMPPRCH_Pos)  /*!< 0x00000060 */
24678 #define TAMP_FLTCR_TAMPPRCH                 TAMP_FLTCR_TAMPPRCH_Msk
24679 #define TAMP_FLTCR_TAMPPRCH_0               (0x1U << TAMP_FLTCR_TAMPPRCH_Pos)  /*!< 0x00000020 */
24680 #define TAMP_FLTCR_TAMPPRCH_1               (0x2U << TAMP_FLTCR_TAMPPRCH_Pos)  /*!< 0x00000040 */
24681 #define TAMP_FLTCR_TAMPPUDIS_Pos            (7U)
24682 #define TAMP_FLTCR_TAMPPUDIS_Msk            (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */
24683 #define TAMP_FLTCR_TAMPPUDIS                TAMP_FLTCR_TAMPPUDIS_Msk
24684 
24685 /********************  Bits definition for TAMP_ATCR1 register  ***************/
24686 #define TAMP_ATCR1_TAMPAM_Pos        (0U)
24687 #define TAMP_ATCR1_TAMPAM_Msk        (0xFFU << TAMP_ATCR1_TAMPAM_Pos)    /*!< 0x000000FF */
24688 #define TAMP_ATCR1_TAMPAM            TAMP_ATCR1_TAMPAM_Msk
24689 #define TAMP_ATCR1_TAMP1AM_Pos       (0U)
24690 #define TAMP_ATCR1_TAMP1AM_Msk       (0x1UL <<TAMP_ATCR1_TAMP1AM_Pos)          /*!< 0x00000001 */
24691 #define TAMP_ATCR1_TAMP1AM           TAMP_ATCR1_TAMP1AM_Msk
24692 #define TAMP_ATCR1_TAMP2AM_Pos       (1U)
24693 #define TAMP_ATCR1_TAMP2AM_Msk       (0x1UL <<TAMP_ATCR1_TAMP2AM_Pos)          /*!< 0x00000002 */
24694 #define TAMP_ATCR1_TAMP2AM           TAMP_ATCR1_TAMP2AM_Msk
24695 #define TAMP_ATCR1_TAMP3AM_Pos       (2U)
24696 #define TAMP_ATCR1_TAMP3AM_Msk       (0x1UL <<TAMP_ATCR1_TAMP3AM_Pos)          /*!< 0x00000004 */
24697 #define TAMP_ATCR1_TAMP3AM           TAMP_ATCR1_TAMP3AM_Msk
24698 #define TAMP_ATCR1_TAMP4AM_Pos       (3U)
24699 #define TAMP_ATCR1_TAMP4AM_Msk       (0x1UL <<TAMP_ATCR1_TAMP4AM_Pos)          /*!< 0x00000008 */
24700 #define TAMP_ATCR1_TAMP4AM           TAMP_ATCR1_TAMP4AM_Msk
24701 #define TAMP_ATCR1_TAMP5AM_Pos       (4U)
24702 #define TAMP_ATCR1_TAMP5AM_Msk       (0x1UL <<TAMP_ATCR1_TAMP5AM_Pos)          /*!< 0x00000010 */
24703 #define TAMP_ATCR1_TAMP5AM           TAMP_ATCR1_TAMP5AM_Msk
24704 #define TAMP_ATCR1_TAMP6AM_Pos       (6U)
24705 #define TAMP_ATCR1_TAMP6AM_Msk       (0x1UL <<TAMP_ATCR1_TAMP6AM_Pos)          /*!< 0x00000020 */
24706 #define TAMP_ATCR1_TAMP6AM           TAMP_ATCR1_TAMP6AM_Msk
24707 #define TAMP_ATCR1_TAMP7AM_Pos       (6U)
24708 #define TAMP_ATCR1_TAMP7AM_Msk       (0x1UL <<TAMP_ATCR1_TAMP7AM_Pos)          /*!< 0x00000040 */
24709 #define TAMP_ATCR1_TAMP7AM           TAMP_ATCR1_TAMP7AM_Msk
24710 #define TAMP_ATCR1_TAMP8AM_Pos       (7U)
24711 #define TAMP_ATCR1_TAMP8AM_Msk       (0x1UL <<TAMP_ATCR1_TAMP8AM_Pos)          /*!< 0x00000080 */
24712 #define TAMP_ATCR1_TAMP8AM           TAMP_ATCR1_TAMP8AM_Msk
24713 #define TAMP_ATCR1_ATOSEL1_Pos       (8U)
24714 #define TAMP_ATCR1_ATOSEL1_Msk       (0x3UL <<TAMP_ATCR1_ATOSEL1_Pos)          /*!< 0x00000300 */
24715 #define TAMP_ATCR1_ATOSEL1            TAMP_ATCR1_ATOSEL1_Msk
24716 #define TAMP_ATCR1_ATOSEL1_0         (0x1UL << TAMP_ATCR1_ATOSEL1_Pos)         /*!< 0x00000100 */
24717 #define TAMP_ATCR1_ATOSEL1_1         (0x2UL << TAMP_ATCR1_ATOSEL1_Pos)         /*!< 0x00000200 */
24718 #define TAMP_ATCR1_ATOSEL2_Pos       (10U)
24719 #define TAMP_ATCR1_ATOSEL2_Msk       (0x3UL <<TAMP_ATCR1_ATOSEL2_Pos)          /*!< 0x00000C00 */
24720 #define TAMP_ATCR1_ATOSEL2            TAMP_ATCR1_ATOSEL2_Msk
24721 #define TAMP_ATCR1_ATOSEL2_0         (0x1UL << TAMP_ATCR1_ATOSEL2_Pos)         /*!< 0x00000400 */
24722 #define TAMP_ATCR1_ATOSEL2_1         (0x2UL << TAMP_ATCR1_ATOSEL2_Pos)         /*!< 0x00000800 */
24723 #define TAMP_ATCR1_ATOSEL3_Pos       (12U)
24724 #define TAMP_ATCR1_ATOSEL3_Msk       (0x3UL <<TAMP_ATCR1_ATOSEL3_Pos)          /*!< 0x00003000 */
24725 #define TAMP_ATCR1_ATOSEL3            TAMP_ATCR1_ATOSEL3_Msk
24726 #define TAMP_ATCR1_ATOSEL3_0         (0x1UL << TAMP_ATCR1_ATOSEL3_Pos)         /*!< 0x00001000 */
24727 #define TAMP_ATCR1_ATOSEL3_1         (0x2UL << TAMP_ATCR1_ATOSEL3_Pos)         /*!< 0x00002000 */
24728 #define TAMP_ATCR1_ATOSEL4_Pos       (14U)
24729 #define TAMP_ATCR1_ATOSEL4_Msk       (0x3UL <<TAMP_ATCR1_ATOSEL4_Pos)          /*!< 0x0000C000 */
24730 #define TAMP_ATCR1_ATOSEL4            TAMP_ATCR1_ATOSEL4_Msk
24731 #define TAMP_ATCR1_ATOSEL4_0         (0x1UL << TAMP_ATCR1_ATOSEL4_Pos)         /*!< 0x00004000 */
24732 #define TAMP_ATCR1_ATOSEL4_1         (0x2UL << TAMP_ATCR1_ATOSEL4_Pos)         /*!< 0x00008000 */
24733 #define TAMP_ATCR1_ATCKSEL_Pos       (16U)
24734 #define TAMP_ATCR1_ATCKSEL_Msk       (0x7UL <<TAMP_ATCR1_ATCKSEL_Pos)          /*!< 0x00070000 */
24735 #define TAMP_ATCR1_ATCKSEL            TAMP_ATCR1_ATCKSEL_Msk
24736 #define TAMP_ATCR1_ATCKSEL_0         (0x1UL << TAMP_ATCR1_ATCKSEL_Pos)         /*!< 0x00010000 */
24737 #define TAMP_ATCR1_ATCKSEL_1         (0x2UL << TAMP_ATCR1_ATCKSEL_Pos)         /*!< 0x00020000 */
24738 #define TAMP_ATCR1_ATCKSEL_2         (0x4UL << TAMP_ATCR1_ATCKSEL_Pos)         /*!< 0x00040000 */
24739 #define TAMP_ATCR1_ATPER_Pos         (24U)
24740 #define TAMP_ATCR1_ATPER_Msk         (0x7UL <<TAMP_ATCR1_ATPER_Pos)            /*!< 0x07000000 */
24741 #define TAMP_ATCR1_ATPER              TAMP_ATCR1_ATPER_Msk
24742 #define TAMP_ATCR1_ATPER_0           (0x1UL << TAMP_ATCR1_ATPER_Pos)           /*!< 0x01000000 */
24743 #define TAMP_ATCR1_ATPER_1           (0x2UL << TAMP_ATCR1_ATPER_Pos)           /*!< 0x02000000 */
24744 #define TAMP_ATCR1_ATPER_2           (0x4UL << TAMP_ATCR1_ATPER_Pos)           /*!< 0x04000000 */
24745 #define TAMP_ATCR1_ATOSHARE_Pos      (30U)
24746 #define TAMP_ATCR1_ATOSHARE_Msk      (0x1UL <<TAMP_ATCR1_ATOSHARE_Pos)         /*!< 0x40000000 */
24747 #define TAMP_ATCR1_ATOSHARE          TAMP_ATCR1_ATOSHARE_Msk
24748 #define TAMP_ATCR1_FLTEN_Pos         (31U)
24749 #define TAMP_ATCR1_FLTEN_Msk         (0x1UL <<TAMP_ATCR1_FLTEN_Pos)            /*!< 0x80000000 */
24750 #define TAMP_ATCR1_FLTEN             TAMP_ATCR1_FLTEN_Msk
24751 
24752 /********************  Bits definition for TAMP_ATSEEDR register  ***************/
24753 #define TAMP_ATSEEDR_SEED_Pos               (0U)
24754 #define TAMP_ATSEEDR_SEED_Msk               (0xFFFFFFFFU << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */
24755 #define TAMP_ATSEEDR_SEED                   TAMP_ATSEEDR_SEED_Msk
24756 
24757 /********************  Bits definition for TAMP_ATOR register  ***************/
24758 #define TAMP_ATOR_PRNG_Pos                  (0U)
24759 #define TAMP_ATOR_PRNG_Msk                  (0xFFU << TAMP_ATOR_PRNG_Pos)      /*!< 0x000000FF */
24760 #define TAMP_ATOR_PRNG                      TAMP_ATOR_PRNG_Msk
24761 #define TAMP_ATOR_PRNG_0                    (0x01U << TAMP_ATOR_PRNG_Pos)      /*!< 0x00000001 */
24762 #define TAMP_ATOR_PRNG_1                    (0x02U << TAMP_ATOR_PRNG_Pos)      /*!< 0x00000002 */
24763 #define TAMP_ATOR_PRNG_2                    (0x04U << TAMP_ATOR_PRNG_Pos)      /*!< 0x00000004 */
24764 #define TAMP_ATOR_PRNG_3                    (0x08U << TAMP_ATOR_PRNG_Pos)      /*!< 0x00000008 */
24765 #define TAMP_ATOR_PRNG_4                    (0x10U << TAMP_ATOR_PRNG_Pos)      /*!< 0x00000010 */
24766 #define TAMP_ATOR_PRNG_5                    (0x20U << TAMP_ATOR_PRNG_Pos)      /*!< 0x00000020 */
24767 #define TAMP_ATOR_PRNG_6                    (0x40U << TAMP_ATOR_PRNG_Pos)      /*!< 0x00000040 */
24768 #define TAMP_ATOR_PRNG_7                    (0x80U << TAMP_ATOR_PRNG_Pos)      /*!< 0x00000080 */
24769 #define TAMP_ATOR_SEEDF_Pos                 (14U)
24770 #define TAMP_ATOR_SEEDF_Msk                 (0x1U << TAMP_ATOR_SEEDF_Pos)      /*!< 0x00004000 */
24771 #define TAMP_ATOR_SEEDF                     TAMP_ATOR_SEEDF_Msk
24772 #define TAMP_ATOR_INITS_Pos                 (15U)
24773 #define TAMP_ATOR_INITS_Msk                 (0x1U << TAMP_ATOR_INITS_Pos)      /*!< 0x00008000 */
24774 #define TAMP_ATOR_INITS                     TAMP_ATOR_INITS_Msk
24775 
24776 /********************  Bits definition for TAMP_SMCR register  ***************/
24777 #define TAMP_SMCR_BKPRWDPROT_Pos            (0U)
24778 #define TAMP_SMCR_BKPRWDPROT_Msk            (0xFFU << TAMP_SMCR_BKPRWDPROT_Pos) /*!< 0x000000FF */
24779 #define TAMP_SMCR_BKPRWDPROT                TAMP_SMCR_BKPRWDPROT_Msk
24780 #define TAMP_SMCR_BKPRWDPROT_0              (0x01U << TAMP_SMCR_BKPRWDPROT_Pos) /*!< 0x00000001 */
24781 #define TAMP_SMCR_BKPRWDPROT_1              (0x02U << TAMP_SMCR_BKPRWDPROT_Pos) /*!< 0x00000002 */
24782 #define TAMP_SMCR_BKPRWDPROT_2              (0x04U << TAMP_SMCR_BKPRWDPROT_Pos) /*!< 0x00000004 */
24783 #define TAMP_SMCR_BKPRWDPROT_3              (0x08U << TAMP_SMCR_BKPRWDPROT_Pos) /*!< 0x00000008 */
24784 #define TAMP_SMCR_BKPRWDPROT_4              (0x10U << TAMP_SMCR_BKPRWDPROT_Pos) /*!< 0x00000010 */
24785 #define TAMP_SMCR_BKPRWDPROT_5              (0x20U << TAMP_SMCR_BKPRWDPROT_Pos) /*!< 0x00000020 */
24786 #define TAMP_SMCR_BKPRWDPROT_6              (0x40U << TAMP_SMCR_BKPRWDPROT_Pos) /*!< 0x00000040 */
24787 #define TAMP_SMCR_BKPRWDPROT_7              (0x80U << TAMP_SMCR_BKPRWDPROT_Pos) /*!< 0x00000080 */
24788 #define TAMP_SMCR_BKPWDPROT_Pos             (16U)
24789 #define TAMP_SMCR_BKPWDPROT_Msk             (0xFFU << TAMP_SMCR_BKPWDPROT_Pos) /*!< 0x00FF0000 */
24790 #define TAMP_SMCR_BKPWDPROT                 TAMP_SMCR_BKPWDPROT_Msk
24791 #define TAMP_SMCR_BKPWDPROT_0               (0x01U << TAMP_SMCR_BKPWDPROT_Pos) /*!< 0x00010000 */
24792 #define TAMP_SMCR_BKPWDPROT_1               (0x02U << TAMP_SMCR_BKPWDPROT_Pos) /*!< 0x00020000 */
24793 #define TAMP_SMCR_BKPWDPROT_2               (0x04U << TAMP_SMCR_BKPWDPROT_Pos) /*!< 0x00040000 */
24794 #define TAMP_SMCR_BKPWDPROT_3               (0x08U << TAMP_SMCR_BKPWDPROT_Pos) /*!< 0x00080000 */
24795 #define TAMP_SMCR_BKPWDPROT_4               (0x10U << TAMP_SMCR_BKPWDPROT_Pos) /*!< 0x00100000 */
24796 #define TAMP_SMCR_BKPWDPROT_5               (0x20U << TAMP_SMCR_BKPWDPROT_Pos) /*!< 0x00200000 */
24797 #define TAMP_SMCR_BKPWDPROT_6               (0x40U << TAMP_SMCR_BKPWDPROT_Pos) /*!< 0x00400000 */
24798 #define TAMP_SMCR_BKPWDPROT_7               (0x80U << TAMP_SMCR_BKPWDPROT_Pos) /*!< 0x00800000 */
24799 #define TAMP_SMCR_TAMPDPROT_Pos             (31U)
24800 #define TAMP_SMCR_TAMPDPROT_Msk             (0x1U << TAMP_SMCR_TAMPDPROT_Pos)  /*!< 0x80000000 */
24801 #define TAMP_SMCR_TAMPDPROT                 TAMP_SMCR_TAMPDPROT_Msk
24802 
24803 /********************  Bits definition for TAMP_IER register  ***************/
24804 #define TAMP_IER_TAMPIE_Pos                 (0U)
24805 #define TAMP_IER_TAMPIE_Msk                 (0x7U << TAMP_IER_TAMPIE_Pos)     /*!< 0x000000FF */
24806 #define TAMP_IER_TAMPIE                     TAMP_IER_TAMPIE_Msk
24807 #define TAMP_IER_TAMP1IE_Pos                (0U)
24808 #define TAMP_IER_TAMP1IE_Msk                (0x1U << TAMP_IER_TAMP1IE_Pos)     /*!< 0x00000001 */
24809 #define TAMP_IER_TAMP1IE                    TAMP_IER_TAMP1IE_Msk
24810 #define TAMP_IER_TAMP2IE_Pos                (1U)
24811 #define TAMP_IER_TAMP2IE_Msk                (0x1U << TAMP_IER_TAMP2IE_Pos)     /*!< 0x00000002 */
24812 #define TAMP_IER_TAMP2IE                    TAMP_IER_TAMP2IE_Msk
24813 #define TAMP_IER_TAMP3IE_Pos                (2U)
24814 #define TAMP_IER_TAMP3IE_Msk                (0x1U << TAMP_IER_TAMP3IE_Pos)     /*!< 0x00000004 */
24815 #define TAMP_IER_TAMP3IE                    TAMP_IER_TAMP3IE_Msk
24816 #define TAMP_IER_ITAMPIE_Pos                (16U)
24817 #define TAMP_IER_ITAMPIE_Msk                (0x9FU << TAMP_IER_ITAMPIE_Pos)  /*!< 0xFFFF0000 */
24818 #define TAMP_IER_ITAMPIE                    TAMP_IER_ITAMPIE_Msk
24819 #define TAMP_IER_ITAMP1IE_Pos               (16U)
24820 #define TAMP_IER_ITAMP1IE_Msk               (0x1U << TAMP_IER_ITAMP1IE_Pos)    /*!< 0x00010000 */
24821 #define TAMP_IER_ITAMP1IE                   TAMP_IER_ITAMP1IE_Msk
24822 #define TAMP_IER_ITAMP2IE_Pos               (17U)
24823 #define TAMP_IER_ITAMP2IE_Msk               (0x1U << TAMP_IER_ITAMP2IE_Pos)    /*!< 0x00020000 */
24824 #define TAMP_IER_ITAMP2IE                   TAMP_IER_ITAMP2IE_Msk
24825 #define TAMP_IER_ITAMP3IE_Pos               (18U)
24826 #define TAMP_IER_ITAMP3IE_Msk               (0x1U << TAMP_IER_ITAMP3IE_Pos)    /*!< 0x00040000 */
24827 #define TAMP_IER_ITAMP3IE                   TAMP_IER_ITAMP3IE_Msk
24828 #define TAMP_IER_ITAMP4IE_Pos               (19U)
24829 #define TAMP_IER_ITAMP4IE_Msk               (0x1U << TAMP_IER_ITAMP4IE_Pos)    /*!< 0x00080000 */
24830 #define TAMP_IER_ITAMP4IE                   TAMP_IER_ITAMP4IE_Msk
24831 #define TAMP_IER_ITAMP5IE_Pos               (20U)
24832 #define TAMP_IER_ITAMP5IE_Msk               (0x1U << TAMP_IER_ITAMP5IE_Pos)    /*!< 0x00100000 */
24833 #define TAMP_IER_ITAMP5IE                   TAMP_IER_ITAMP5IE_Msk
24834 #define TAMP_IER_ITAMP8IE_Pos               (23U)
24835 #define TAMP_IER_ITAMP8IE_Msk               (0x1U << TAMP_IER_ITAMP8IE_Pos)    /*!< 0x00800000 */
24836 #define TAMP_IER_ITAMP8IE                   TAMP_IER_ITAMP8IE_Msk
24837 
24838 
24839 /********************  Bits definition for TAMP_SR register  ***************/
24840 #define TAMP_SR_TAMPF_Pos                   (0U)
24841 #define TAMP_SR_TAMPF_Msk                   (0x7U << TAMP_SR_TAMPF_Pos)       /*!< 0x000000FF */
24842 #define TAMP_SR_TAMPF                       TAMP_SR_TAMPF_Msk
24843 #define TAMP_SR_TAMP1F_Pos                  (0U)
24844 #define TAMP_SR_TAMP1F_Msk                  (0x1U << TAMP_SR_TAMP1F_Pos)       /*!< 0x00000001 */
24845 #define TAMP_SR_TAMP1F                      TAMP_SR_TAMP1F_Msk
24846 #define TAMP_SR_TAMP2F_Pos                  (1U)
24847 #define TAMP_SR_TAMP2F_Msk                  (0x1U << TAMP_SR_TAMP2F_Pos)       /*!< 0x00000002 */
24848 #define TAMP_SR_TAMP2F                      TAMP_SR_TAMP2F_Msk
24849 #define TAMP_SR_TAMP3F_Pos                  (2U)
24850 #define TAMP_SR_TAMP3F_Msk                  (0x1U << TAMP_SR_TAMP3F_Pos)       /*!< 0x00000004 */
24851 #define TAMP_SR_TAMP3F                      TAMP_SR_TAMP3F_Msk
24852 #define TAMP_SR_ITAMPF_Pos                  (16U)
24853 #define TAMP_SR_ITAMPF_Msk                  (0x9FU << TAMP_SR_ITAMPF_Pos)    /*!< 0xFFFF0000 */
24854 #define TAMP_SR_ITAMPF                      TAMP_SR_ITAMPF_Msk
24855 #define TAMP_SR_ITAMP1F_Pos                 (16U)
24856 #define TAMP_SR_ITAMP1F_Msk                 (0x1U << TAMP_SR_ITAMP1F_Pos)      /*!< 0x00010000 */
24857 #define TAMP_SR_ITAMP1F                     TAMP_SR_ITAMP1F_Msk
24858 #define TAMP_SR_ITAMP2F_Pos                 (17U)
24859 #define TAMP_SR_ITAMP2F_Msk                 (0x1U << TAMP_SR_ITAMP2F_Pos)      /*!< 0x00020000 */
24860 #define TAMP_SR_ITAMP2F                     TAMP_SR_ITAMP2F_Msk
24861 #define TAMP_SR_ITAMP3F_Pos                 (18U)
24862 #define TAMP_SR_ITAMP3F_Msk                 (0x1U << TAMP_SR_ITAMP3F_Pos)      /*!< 0x00040000 */
24863 #define TAMP_SR_ITAMP3F                     TAMP_SR_ITAMP3F_Msk
24864 #define TAMP_SR_ITAMP4F_Pos                 (19U)
24865 #define TAMP_SR_ITAMP4F_Msk                 (0x1U << TAMP_SR_ITAMP4F_Pos)      /*!< 0x00080000 */
24866 #define TAMP_SR_ITAMP4F                     TAMP_SR_ITAMP4F_Msk
24867 #define TAMP_SR_ITAMP5F_Pos                 (20U)
24868 #define TAMP_SR_ITAMP5F_Msk                 (0x1U << TAMP_SR_ITAMP5F_Pos)      /*!< 0x00100000 */
24869 #define TAMP_SR_ITAMP5F                     TAMP_SR_ITAMP5F_Msk
24870 #define TAMP_SR_ITAMP8F_Pos                 (23U)
24871 #define TAMP_SR_ITAMP8F_Msk                 (0x1U << TAMP_SR_ITAMP8F_Pos)      /*!< 0x00800000 */
24872 #define TAMP_SR_ITAMP8F                     TAMP_SR_ITAMP8F_Msk
24873 
24874 
24875 /********************  Bits definition for TAMP_MISR register  ***************/
24876 #define TAMP_MISR_TAMPMF_Pos                (0U)
24877 #define TAMP_MISR_TAMPMF_Msk                (0x7U << TAMP_MISR_TAMPMF_Pos)    /*!< 0x000000FF */
24878 #define TAMP_MISR_TAMPMF                    TAMP_MISR_TAMPMF_Msk
24879 #define TAMP_MISR_TAMP1MF_Pos               (0U)
24880 #define TAMP_MISR_TAMP1MF_Msk               (0x1U << TAMP_MISR_TAMP1MF_Pos)    /*!< 0x00000001 */
24881 #define TAMP_MISR_TAMP1MF                   TAMP_MISR_TAMP1MF_Msk
24882 #define TAMP_MISR_TAMP2MF_Pos               (1U)
24883 #define TAMP_MISR_TAMP2MF_Msk               (0x1U << TAMP_MISR_TAMP2MF_Pos)    /*!< 0x00000002 */
24884 #define TAMP_MISR_TAMP2MF                   TAMP_MISR_TAMP2MF_Msk
24885 #define TAMP_MISR_TAMP3MF_Pos               (2U)
24886 #define TAMP_MISR_TAMP3MF_Msk               (0x1U << TAMP_MISR_TAMP3MF_Pos)    /*!< 0x00000004 */
24887 #define TAMP_MISR_TAMP3MF                   TAMP_MISR_TAMP3MF_Msk
24888 #define TAMP_MISR_ITAMPMF_Pos               (16U)
24889 #define TAMP_MISR_ITAMPMF_Msk               (0x9FU << TAMP_MISR_ITAMPMF_Pos) /*!< 0xFFFF0000 */
24890 #define TAMP_MISR_ITAMPMF                   TAMP_MISR_ITAMPMF_Msk
24891 #define TAMP_MISR_ITAMP1MF_Pos              (16U)
24892 #define TAMP_MISR_ITAMP1MF_Msk              (0x1U << TAMP_MISR_ITAMP1MF_Pos)   /*!< 0x00010000 */
24893 #define TAMP_MISR_ITAMP1MF                  TAMP_MISR_ITAMP1MF_Msk
24894 #define TAMP_MISR_ITAMP2MF_Pos              (17U)
24895 #define TAMP_MISR_ITAMP2MF_Msk              (0x1U << TAMP_MISR_ITAMP2MF_Pos)   /*!< 0x00020000 */
24896 #define TAMP_MISR_ITAMP2MF                  TAMP_MISR_ITAMP2MF_Msk
24897 #define TAMP_MISR_ITAMP3MF_Pos              (18U)
24898 #define TAMP_MISR_ITAMP3MF_Msk              (0x1U << TAMP_MISR_ITAMP3MF_Pos)   /*!< 0x00040000 */
24899 #define TAMP_MISR_ITAMP3MF                  TAMP_MISR_ITAMP3MF_Msk
24900 #define TAMP_MISR_ITAMP4MF_Pos              (19U)
24901 #define TAMP_MISR_ITAMP4MF_Msk              (0x1U << TAMP_MISR_ITAMP4MF_Pos)   /*!< 0x00080000 */
24902 #define TAMP_MISR_ITAMP4MF                  TAMP_MISR_ITAMP4MF_Msk
24903 #define TAMP_MISR_ITAMP5MF_Pos              (20U)
24904 #define TAMP_MISR_ITAMP5MF_Msk              (0x1U << TAMP_MISR_ITAMP5MF_Pos)   /*!< 0x00100000 */
24905 #define TAMP_MISR_ITAMP5MF                  TAMP_MISR_ITAMP5MF_Msk
24906 #define TAMP_MISR_ITAMP8MF_Pos              (23U)
24907 #define TAMP_MISR_ITAMP8MF_Msk              (0x1U << TAMP_MISR_ITAMP8MF_Pos)   /*!< 0x00800000 */
24908 #define TAMP_MISR_ITAMP8MF                  TAMP_MISR_ITAMP8MF_Msk
24909 
24910 
24911 /********************  Bits definition for TAMP_SMISR register  ***************/
24912 #define TAMP_SMISR_TAMPMF_Pos               (0U)
24913 #define TAMP_SMISR_TAMPMF_Msk               (0x7U << TAMP_SMISR_TAMPMF_Pos)   /*!< 0x000000FF */
24914 #define TAMP_SMISR_TAMPMF                   TAMP_SMISR_TAMPMF_Msk
24915 #define TAMP_SMISR_TAMP1MF_Pos              (0U)
24916 #define TAMP_SMISR_TAMP1MF_Msk              (0x1U << TAMP_SMISR_TAMP1MF_Pos)   /*!< 0x00000001 */
24917 #define TAMP_SMISR_TAMP1MF                  TAMP_SMISR_TAMP1MF_Msk
24918 #define TAMP_SMISR_TAMP2MF_Pos              (1U)
24919 #define TAMP_SMISR_TAMP2MF_Msk              (0x1U << TAMP_SMISR_TAMP2MF_Pos)   /*!< 0x00000002 */
24920 #define TAMP_SMISR_TAMP2MF                  TAMP_SMISR_TAMP2MF_Msk
24921 #define TAMP_SMISR_TAMP3MF_Pos              (2U)
24922 #define TAMP_SMISR_TAMP3MF_Msk              (0x1U << TAMP_SMISR_TAMP3MF_Pos)   /*!< 0x00000004 */
24923 #define TAMP_SMISR_TAMP3MF                  TAMP_SMISR_TAMP3MF_Msk
24924 #define TAMP_SMISR_ITAMPMF_Pos              (16U)
24925 #define TAMP_SMISR_ITAMPMF_Msk              (0x9FU << TAMP_SMISR_ITAMPMF_Pos) /*!< 0xFFFF0000 */
24926 #define TAMP_SMISR_ITAMPMF                  TAMP_SMISR_ITAMPMF_Msk
24927 #define TAMP_SMISR_ITAMP1MF_Pos             (16U)
24928 #define TAMP_SMISR_ITAMP1MF_Msk             (0x1U << TAMP_SMISR_ITAMP1MF_Pos)  /*!< 0x00010000 */
24929 #define TAMP_SMISR_ITAMP1MF                 TAMP_SMISR_ITAMP1MF_Msk
24930 #define TAMP_SMISR_ITAMP2MF_Pos             (17U)
24931 #define TAMP_SMISR_ITAMP2MF_Msk             (0x1U << TAMP_SMISR_ITAMP2MF_Pos)  /*!< 0x00020000 */
24932 #define TAMP_SMISR_ITAMP2MF                 TAMP_SMISR_ITAMP2MF_Msk
24933 #define TAMP_SMISR_ITAMP3MF_Pos             (18U)
24934 #define TAMP_SMISR_ITAMP3MF_Msk             (0x1U << TAMP_SMISR_ITAMP3MF_Pos)  /*!< 0x00040000 */
24935 #define TAMP_SMISR_ITAMP3MF                 TAMP_SMISR_ITAMP3MF_Msk
24936 #define TAMP_SMISR_ITAMP4MF_Pos             (19U)
24937 #define TAMP_SMISR_ITAMP4MF_Msk             (0x1U << TAMP_SMISR_ITAMP4MF_Pos)  /*!< 0x00080000 */
24938 #define TAMP_SMISR_ITAMP4MF                 TAMP_SMISR_ITAMP4MF_Msk
24939 #define TAMP_SMISR_ITAMP5MF_Pos             (20U)
24940 #define TAMP_SMISR_ITAMP5MF_Msk             (0x1U << TAMP_SMISR_ITAMP5MF_Pos)  /*!< 0x00100000 */
24941 #define TAMP_SMISR_ITAMP5MF                 TAMP_SMISR_ITAMP5MF_Msk
24942 #define TAMP_SMISR_ITAMP8MF_Pos             (23U)
24943 #define TAMP_SMISR_ITAMP8MF_Msk             (0x1U << TAMP_SMISR_ITAMP8MF_Pos)  /*!< 0x00800000 */
24944 #define TAMP_SMISR_ITAMP8MF                 TAMP_SMISR_ITAMP8MF_Msk
24945 
24946 
24947 /********************  Bits definition for TAMP_SCR register  ***************/
24948 #define TAMP_SCR_CTAMPF_Pos                 (0U)
24949 #define TAMP_SCR_CTAMPF_Msk                 (0x7U << TAMP_SCR_CTAMPF_Pos)     /*!< 0x000000FF */
24950 #define TAMP_SCR_CTAMPF                     TAMP_SCR_CTAMPF_Msk
24951 #define TAMP_SCR_CTAMP1F_Pos                (0U)
24952 #define TAMP_SCR_CTAMP1F_Msk                (0x1U << TAMP_SCR_CTAMP1F_Pos)     /*!< 0x00000001 */
24953 #define TAMP_SCR_CTAMP1F                    TAMP_SCR_CTAMP1F_Msk
24954 #define TAMP_SCR_CTAMP2F_Pos                (1U)
24955 #define TAMP_SCR_CTAMP2F_Msk                (0x1U << TAMP_SCR_CTAMP2F_Pos)     /*!< 0x00000002 */
24956 #define TAMP_SCR_CTAMP2F                    TAMP_SCR_CTAMP2F_Msk
24957 #define TAMP_SCR_CTAMP3F_Pos                (2U)
24958 #define TAMP_SCR_CTAMP3F_Msk                (0x1U << TAMP_SCR_CTAMP3F_Pos)     /*!< 0x00000004 */
24959 #define TAMP_SCR_CTAMP3F                    TAMP_SCR_CTAMP3F_Msk
24960 #define TAMP_SCR_CITAMPF_Pos                (16U)
24961 #define TAMP_SCR_CITAMPF_Msk                (0x9FU << TAMP_SCR_CITAMPF_Pos)  /*!< 0xFFFF0000 */
24962 #define TAMP_SCR_CITAMPF                    TAMP_SCR_CITAMPF_Msk
24963 #define TAMP_SCR_CITAMP1F_Pos               (16U)
24964 #define TAMP_SCR_CITAMP1F_Msk               (0x1U << TAMP_SCR_CITAMP1F_Pos)    /*!< 0x00010000 */
24965 #define TAMP_SCR_CITAMP1F                   TAMP_SCR_CITAMP1F_Msk
24966 #define TAMP_SCR_CITAMP2F_Pos               (17U)
24967 #define TAMP_SCR_CITAMP2F_Msk               (0x1U << TAMP_SCR_CITAMP2F_Pos)    /*!< 0x00020000 */
24968 #define TAMP_SCR_CITAMP2F                   TAMP_SCR_CITAMP2F_Msk
24969 #define TAMP_SCR_CITAMP3F_Pos               (18U)
24970 #define TAMP_SCR_CITAMP3F_Msk               (0x1U << TAMP_SCR_CITAMP3F_Pos)    /*!< 0x00040000 */
24971 #define TAMP_SCR_CITAMP3F                   TAMP_SCR_CITAMP3F_Msk
24972 #define TAMP_SCR_CITAMP4F_Pos               (19U)
24973 #define TAMP_SCR_CITAMP4F_Msk               (0x1U << TAMP_SCR_CITAMP4F_Pos)    /*!< 0x00080000 */
24974 #define TAMP_SCR_CITAMP4F                   TAMP_SCR_CITAMP4F_Msk
24975 #define TAMP_SCR_CITAMP5F_Pos               (20U)
24976 #define TAMP_SCR_CITAMP5F_Msk               (0x1U << TAMP_SCR_CITAMP5F_Pos)    /*!< 0x00100000 */
24977 #define TAMP_SCR_CITAMP5F                   TAMP_SCR_CITAMP5F_Msk
24978 #define TAMP_SCR_CITAMP8F_Pos               (23U)
24979 #define TAMP_SCR_CITAMP8F_Msk               (0x1U << TAMP_SCR_CITAMP8F_Pos)    /*!< 0x00800000 */
24980 #define TAMP_SCR_CITAMP8F                   TAMP_SCR_CITAMP8F_Msk
24981 
24982 
24983 /********************  Bits definition for TAMP_OR register (TAMP_CFGR)  ****************/
24984 #define TAMP_CFGR_OUT3_RMP_Pos                (0U)
24985 #define TAMP_CFGR_OUT3_RMP_Msk                (0x1U << TAMP_CFGR_OUT3_RMP_Pos)     /*!< 0x00000001 */
24986 #define TAMP_CFGR_OUT3_RMP                    TAMP_CFGR_OUT3_RMP_Msk
24987 
24988 
24989 /********************  Bits definition for TAMP_COUNTR register  ****************/
24990 #define TAMP_COUNTR_COUNT_Pos               (0U)
24991 #define TAMP_COUNTR_COUNT_Msk               (0xFFFFFFFFU << TAMP_COUNTR_COUNT_Pos) /*!< 0xFFFFFFFF */
24992 #define TAMP_COUNTR_COUNT                   TAMP_COUNTR_COUNT_Msk
24993 
24994 
24995 /********************  Bits definition for TAMP_BKPxR register  ****************/
24996 #define TAMP_BKP0R_Pos                      (0U)
24997 #define TAMP_BKP0R_Msk                      (0xFFFFFFFFU << TAMP_BKP0R_Pos)    /*!< 0xFFFFFFFF */
24998 #define TAMP_BKP0R                          TAMP_BKP0R_Msk
24999 #define TAMP_BKP1R_Pos                      (0U)
25000 #define TAMP_BKP1R_Msk                      (0xFFFFFFFFU << TAMP_BKP1R_Pos)    /*!< 0xFFFFFFFF */
25001 #define TAMP_BKP1R                          TAMP_BKP1R_Msk
25002 #define TAMP_BKP2R_Pos                      (0U)
25003 #define TAMP_BKP2R_Msk                      (0xFFFFFFFFU << TAMP_BKP2R_Pos)    /*!< 0xFFFFFFFF */
25004 #define TAMP_BKP2R                          TAMP_BKP2R_Msk
25005 #define TAMP_BKP3R_Pos                      (0U)
25006 #define TAMP_BKP3R_Msk                      (0xFFFFFFFFU << TAMP_BKP3R_Pos)    /*!< 0xFFFFFFFF */
25007 #define TAMP_BKP3R                          TAMP_BKP3R_Msk
25008 #define TAMP_BKP4R_Pos                      (0U)
25009 #define TAMP_BKP4R_Msk                      (0xFFFFFFFFU << TAMP_BKP4R_Pos)    /*!< 0xFFFFFFFF */
25010 #define TAMP_BKP4R                          TAMP_BKP4R_Msk
25011 #define TAMP_BKP5R_Pos                      (0U)
25012 #define TAMP_BKP5R_Msk                      (0xFFFFFFFFU << TAMP_BKP5R_Pos)    /*!< 0xFFFFFFFF */
25013 #define TAMP_BKP5R                          TAMP_BKP5R_Msk
25014 #define TAMP_BKP6R_Pos                      (0U)
25015 #define TAMP_BKP6R_Msk                      (0xFFFFFFFFU << TAMP_BKP6R_Pos)    /*!< 0xFFFFFFFF */
25016 #define TAMP_BKP6R                          TAMP_BKP6R_Msk
25017 #define TAMP_BKP7R_Pos                      (0U)
25018 #define TAMP_BKP7R_Msk                      (0xFFFFFFFFU << TAMP_BKP7R_Pos)    /*!< 0xFFFFFFFF */
25019 #define TAMP_BKP7R                          TAMP_BKP7R_Msk
25020 #define TAMP_BKP8R_Pos                      (0U)
25021 #define TAMP_BKP8R_Msk                      (0xFFFFFFFFU << TAMP_BKP8R_Pos)    /*!< 0xFFFFFFFF */
25022 #define TAMP_BKP8R                          TAMP_BKP8R_Msk
25023 #define TAMP_BKP9R_Pos                      (0U)
25024 #define TAMP_BKP9R_Msk                      (0xFFFFFFFFU << TAMP_BKP9R_Pos)    /*!< 0xFFFFFFFF */
25025 #define TAMP_BKP9R                          TAMP_BKP9R_Msk
25026 #define TAMP_BKP10R_Pos                     (0U)
25027 #define TAMP_BKP10R_Msk                     (0xFFFFFFFFU << TAMP_BKP10R_Pos)   /*!< 0xFFFFFFFF */
25028 #define TAMP_BKP10R                         TAMP_BKP10R_Msk
25029 #define TAMP_BKP11R_Pos                     (0U)
25030 #define TAMP_BKP11R_Msk                     (0xFFFFFFFFU << TAMP_BKP11R_Pos)   /*!< 0xFFFFFFFF */
25031 #define TAMP_BKP11R                         TAMP_BKP11R_Msk
25032 #define TAMP_BKP12R_Pos                     (0U)
25033 #define TAMP_BKP12R_Msk                     (0xFFFFFFFFU << TAMP_BKP12R_Pos)   /*!< 0xFFFFFFFF */
25034 #define TAMP_BKP12R                         TAMP_BKP12R_Msk
25035 #define TAMP_BKP13R_Pos                     (0U)
25036 #define TAMP_BKP13R_Msk                     (0xFFFFFFFFU << TAMP_BKP13R_Pos)   /*!< 0xFFFFFFFF */
25037 #define TAMP_BKP13R                         TAMP_BKP13R_Msk
25038 #define TAMP_BKP14R_Pos                     (0U)
25039 #define TAMP_BKP14R_Msk                     (0xFFFFFFFFU << TAMP_BKP14R_Pos)   /*!< 0xFFFFFFFF */
25040 #define TAMP_BKP14R                         TAMP_BKP14R_Msk
25041 #define TAMP_BKP15R_Pos                     (0U)
25042 #define TAMP_BKP15R_Msk                     (0xFFFFFFFFU << TAMP_BKP15R_Pos)   /*!< 0xFFFFFFFF */
25043 #define TAMP_BKP15R                         TAMP_BKP15R_Msk
25044 #define TAMP_BKP16R_Pos                     (0U)
25045 #define TAMP_BKP16R_Msk                     (0xFFFFFFFFU << TAMP_BKP16R_Pos)   /*!< 0xFFFFFFFF */
25046 #define TAMP_BKP16R                         TAMP_BKP16R_Msk
25047 #define TAMP_BKP17R_Pos                     (0U)
25048 #define TAMP_BKP17R_Msk                     (0xFFFFFFFFU << TAMP_BKP17R_Pos)   /*!< 0xFFFFFFFF */
25049 #define TAMP_BKP17R                         TAMP_BKP17R_Msk
25050 #define TAMP_BKP18R_Pos                     (0U)
25051 #define TAMP_BKP18R_Msk                     (0xFFFFFFFFU << TAMP_BKP18R_Pos)   /*!< 0xFFFFFFFF */
25052 #define TAMP_BKP18R                         TAMP_BKP18R_Msk
25053 #define TAMP_BKP19R_Pos                     (0U)
25054 #define TAMP_BKP19R_Msk                     (0xFFFFFFFFU << TAMP_BKP19R_Pos)   /*!< 0xFFFFFFFF */
25055 #define TAMP_BKP19R                         TAMP_BKP19R_Msk
25056 #define TAMP_BKP20R_Pos                     (0U)
25057 #define TAMP_BKP20R_Msk                     (0xFFFFFFFFU << TAMP_BKP20R_Pos)   /*!< 0xFFFFFFFF */
25058 #define TAMP_BKP20R                         TAMP_BKP20R_Msk
25059 #define TAMP_BKP21R_Pos                     (0U)
25060 #define TAMP_BKP21R_Msk                     (0xFFFFFFFFU << TAMP_BKP21R_Pos)   /*!< 0xFFFFFFFF */
25061 #define TAMP_BKP21R                         TAMP_BKP21R_Msk
25062 #define TAMP_BKP22R_Pos                     (0U)
25063 #define TAMP_BKP22R_Msk                     (0xFFFFFFFFU << TAMP_BKP22R_Pos)   /*!< 0xFFFFFFFF */
25064 #define TAMP_BKP22R                         TAMP_BKP22R_Msk
25065 #define TAMP_BKP23R_Pos                     (0U)
25066 #define TAMP_BKP23R_Msk                     (0xFFFFFFFFU << TAMP_BKP23R_Pos)   /*!< 0xFFFFFFFF */
25067 #define TAMP_BKP23R                         TAMP_BKP23R_Msk
25068 #define TAMP_BKP24R_Pos                     (0U)
25069 #define TAMP_BKP24R_Msk                     (0xFFFFFFFFU << TAMP_BKP24R_Pos)   /*!< 0xFFFFFFFF */
25070 #define TAMP_BKP24R                         TAMP_BKP24R_Msk
25071 #define TAMP_BKP25R_Pos                     (0U)
25072 #define TAMP_BKP25R_Msk                     (0xFFFFFFFFU << TAMP_BKP25R_Pos)   /*!< 0xFFFFFFFF */
25073 #define TAMP_BKP25R                         TAMP_BKP25R_Msk
25074 #define TAMP_BKP26R_Pos                     (0U)
25075 #define TAMP_BKP26R_Msk                     (0xFFFFFFFFU << TAMP_BKP26R_Pos)   /*!< 0xFFFFFFFF */
25076 #define TAMP_BKP26R                         TAMP_BKP26R_Msk
25077 #define TAMP_BKP27R_Pos                     (0U)
25078 #define TAMP_BKP27R_Msk                     (0xFFFFFFFFU << TAMP_BKP27R_Pos)   /*!< 0xFFFFFFFF */
25079 #define TAMP_BKP27R                         TAMP_BKP27R_Msk
25080 #define TAMP_BKP28R_Pos                     (0U)
25081 #define TAMP_BKP28R_Msk                     (0xFFFFFFFFU << TAMP_BKP28R_Pos)   /*!< 0xFFFFFFFF */
25082 #define TAMP_BKP28R                         TAMP_BKP28R_Msk
25083 #define TAMP_BKP29R_Pos                     (0U)
25084 #define TAMP_BKP29R_Msk                     (0xFFFFFFFFU << TAMP_BKP29R_Pos)   /*!< 0xFFFFFFFF */
25085 #define TAMP_BKP29R                         TAMP_BKP29R_Msk
25086 #define TAMP_BKP30R_Pos                     (0U)
25087 #define TAMP_BKP30R_Msk                     (0xFFFFFFFFU << TAMP_BKP30R_Pos)   /*!< 0xFFFFFFFF */
25088 #define TAMP_BKP30R                         TAMP_BKP30R_Msk
25089 #define TAMP_BKP31R_Pos                     (0U)
25090 #define TAMP_BKP31R_Msk                     (0xFFFFFFFFU << TAMP_BKP31R_Pos)   /*!< 0xFFFFFFFF */
25091 #define TAMP_BKP31R                         TAMP_BKP31R_Msk
25092 
25093 
25094 /********************  Bits definition for TAMP_HWCFGR2 register  *************/
25095 #define TAMP_HWCFGR2_TRUST_ZONE_Pos         (8U)
25096 #define TAMP_HWCFGR2_TRUST_ZONE_Msk         (0xFU << TAMP_HWCFGR2_TRUST_ZONE_Pos) /*!< 0x00000F00 */
25097 #define TAMP_HWCFGR2_TRUST_ZONE             TAMP_HWCFGR2_TRUST_ZONE_Msk
25098 #define TAMP_HWCFGR2_TRUST_ZONE_0           (0x1U << TAMP_HWCFGR2_TRUST_ZONE_Pos) /*!< 0x00000100 */
25099 #define TAMP_HWCFGR2_TRUST_ZONE_1           (0x2U << TAMP_HWCFGR2_TRUST_ZONE_Pos) /*!< 0x00000200 */
25100 #define TAMP_HWCFGR2_TRUST_ZONE_2           (0x4U << TAMP_HWCFGR2_TRUST_ZONE_Pos) /*!< 0x00000400 */
25101 #define TAMP_HWCFGR2_TRUST_ZONE_3           (0x8U << TAMP_HWCFGR2_TRUST_ZONE_Pos) /*!< 0x00000800 */
25102 
25103 #define TAMP_HWCFGR2_OPTIONREG_OUT_Pos      (0U)
25104 #define TAMP_HWCFGR2_OPTIONREG_OUT_Msk      (0xFFU << TAMP_HWCFGR2_OPTIONREG_OUT_Pos) /*!< 0x000000FF */
25105 #define TAMP_HWCFGR2_OPTIONREG_OUT          TAMP_HWCFGR2_OPTIONREG_OUT_Msk
25106 #define TAMP_HWCFGR2_OPTIONREG_OUT_0        (0x01U << TAMP_HWCFGR2_OPTIONREG_OUT_Pos) /*!< 0x00000001 */
25107 #define TAMP_HWCFGR2_OPTIONREG_OUT_1        (0x02U << TAMP_HWCFGR2_OPTIONREG_OUT_Pos) /*!< 0x00000002 */
25108 #define TAMP_HWCFGR2_OPTIONREG_OUT_2        (0x04U << TAMP_HWCFGR2_OPTIONREG_OUT_Pos) /*!< 0x00000004 */
25109 #define TAMP_HWCFGR2_OPTIONREG_OUT_3        (0x08U << TAMP_HWCFGR2_OPTIONREG_OUT_Pos) /*!< 0x00000008 */
25110 #define TAMP_HWCFGR2_OPTIONREG_OUT_4        (0x10U << TAMP_HWCFGR2_OPTIONREG_OUT_Pos) /*!< 0x00000010 */
25111 #define TAMP_HWCFGR2_OPTIONREG_OUT_5        (0x20U << TAMP_HWCFGR2_OPTIONREG_OUT_Pos) /*!< 0x00000020 */
25112 #define TAMP_HWCFGR2_OPTIONREG_OUT_6        (0x40U << TAMP_HWCFGR2_OPTIONREG_OUT_Pos) /*!< 0x00000040 */
25113 #define TAMP_HWCFGR2_OPTIONREG_OUT_7        (0x80U << TAMP_HWCFGR2_OPTIONREG_OUT_Pos) /*!< 0x00000080 */
25114 
25115 /********************  Bits definition for TAMP_HWCFGR1 register  *************/
25116 #define TAMP_HWCFGR1_INT_TAMPER_Pos         (16U)
25117 #define TAMP_HWCFGR1_INT_TAMPER_Msk         (0xFFFFU << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0xFFFF0000 */
25118 #define TAMP_HWCFGR1_INT_TAMPER             TAMP_HWCFGR1_INT_TAMPER_Msk
25119 #define TAMP_HWCFGR1_INT_TAMPER_0           (0x0001U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x00010000 */
25120 #define TAMP_HWCFGR1_INT_TAMPER_1           (0x0002U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x00020000 */
25121 #define TAMP_HWCFGR1_INT_TAMPER_2           (0x0004U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x00040000 */
25122 #define TAMP_HWCFGR1_INT_TAMPER_3           (0x0008U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x00080000 */
25123 #define TAMP_HWCFGR1_INT_TAMPER_4           (0x0010U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x00100000 */
25124 #define TAMP_HWCFGR1_INT_TAMPER_5           (0x0020U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x00200000 */
25125 #define TAMP_HWCFGR1_INT_TAMPER_6           (0x0040U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x00400000 */
25126 #define TAMP_HWCFGR1_INT_TAMPER_7           (0x0080U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x00800000 */
25127 #define TAMP_HWCFGR1_INT_TAMPER_8           (0x0100U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x01000000 */
25128 #define TAMP_HWCFGR1_INT_TAMPER_9           (0x0200U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x02000000 */
25129 #define TAMP_HWCFGR1_INT_TAMPER_10          (0x0400U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x04000000 */
25130 #define TAMP_HWCFGR1_INT_TAMPER_11          (0x0800U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x08000000 */
25131 #define TAMP_HWCFGR1_INT_TAMPER_12          (0x1000U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x10000000 */
25132 #define TAMP_HWCFGR1_INT_TAMPER_13          (0x2000U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x20000000 */
25133 #define TAMP_HWCFGR1_INT_TAMPER_14          (0x4000U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x40000000 */
25134 #define TAMP_HWCFGR1_INT_TAMPER_15          (0x8000U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x80000000 */
25135 
25136 #define TAMP_HWCFGR1_ACTIVE_TAMPER_Pos      (12U)
25137 #define TAMP_HWCFGR1_ACTIVE_TAMPER_Msk      (0xFU << TAMP_HWCFGR1_ACTIVE_TAMPER_Pos) /*!< 0x0000F000 */
25138 #define TAMP_HWCFGR1_ACTIVE_TAMPER          TAMP_HWCFGR1_ACTIVE_TAMPER_Msk
25139 #define TAMP_HWCFGR1_ACTIVE_TAMPER_0        (0x1U << TAMP_HWCFGR1_ACTIVE_TAMPER_Pos) /*!< 0x00001000 */
25140 #define TAMP_HWCFGR1_ACTIVE_TAMPER_1        (0x2U << TAMP_HWCFGR1_ACTIVE_TAMPER_Pos) /*!< 0x00002000 */
25141 #define TAMP_HWCFGR1_ACTIVE_TAMPER_2        (0x4U << TAMP_HWCFGR1_ACTIVE_TAMPER_Pos) /*!< 0x00004000 */
25142 #define TAMP_HWCFGR1_ACTIVE_TAMPER_3        (0x8U << TAMP_HWCFGR1_ACTIVE_TAMPER_Pos) /*!< 0x00008000 */
25143 
25144 #define TAMP_HWCFGR1_TAMPER_Pos             (8U)
25145 #define TAMP_HWCFGR1_TAMPER_Msk             (0xFU << TAMP_HWCFGR1_TAMPER_Pos)  /*!< 0x00000F00 */
25146 #define TAMP_HWCFGR1_TAMPER                 TAMP_HWCFGR1_TAMPER_Msk
25147 #define TAMP_HWCFGR1_TAMPER_0               (0x1U << TAMP_HWCFGR1_TAMPER_Pos)  /*!< 0x00000100 */
25148 #define TAMP_HWCFGR1_TAMPER_1               (0x2U << TAMP_HWCFGR1_TAMPER_Pos)  /*!< 0x00000200 */
25149 #define TAMP_HWCFGR1_TAMPER_2               (0x4U << TAMP_HWCFGR1_TAMPER_Pos)  /*!< 0x00000400 */
25150 #define TAMP_HWCFGR1_TAMPER_3               (0x8U << TAMP_HWCFGR1_TAMPER_Pos)  /*!< 0x00000800 */
25151 
25152 #define TAMP_HWCFGR1_BACKUP_REGS_Pos        (0U)
25153 #define TAMP_HWCFGR1_BACKUP_REGS_Msk        (0xFFU << TAMP_HWCFGR1_BACKUP_REGS_Pos) /*!< 0x000000FF */
25154 #define TAMP_HWCFGR1_BACKUP_REGS            TAMP_HWCFGR1_BACKUP_REGS_Msk
25155 #define TAMP_HWCFGR1_BACKUP_REGS_0          (0x01U << TAMP_HWCFGR1_BACKUP_REGS_Pos) /*!< 0x00000001 */
25156 #define TAMP_HWCFGR1_BACKUP_REGS_1          (0x02U << TAMP_HWCFGR1_BACKUP_REGS_Pos) /*!< 0x00000002 */
25157 #define TAMP_HWCFGR1_BACKUP_REGS_2          (0x04U << TAMP_HWCFGR1_BACKUP_REGS_Pos) /*!< 0x00000004 */
25158 #define TAMP_HWCFGR1_BACKUP_REGS_3          (0x08U << TAMP_HWCFGR1_BACKUP_REGS_Pos) /*!< 0x00000008 */
25159 #define TAMP_HWCFGR1_BACKUP_REGS_4          (0x10U << TAMP_HWCFGR1_BACKUP_REGS_Pos) /*!< 0x00000010 */
25160 #define TAMP_HWCFGR1_BACKUP_REGS_5          (0x20U << TAMP_HWCFGR1_BACKUP_REGS_Pos) /*!< 0x00000020 */
25161 #define TAMP_HWCFGR1_BACKUP_REGS_6          (0x40U << TAMP_HWCFGR1_BACKUP_REGS_Pos) /*!< 0x00000040 */
25162 #define TAMP_HWCFGR1_BACKUP_REGS_7          (0x80U << TAMP_HWCFGR1_BACKUP_REGS_Pos) /*!< 0x00000080 */
25163 
25164 /********************  Bits definition for TAMP_VERR register  ****************/
25165 #define TAMP_VERR_MAJREV_Pos                (4U)
25166 #define TAMP_VERR_MAJREV_Msk                (0xFU << TAMP_VERR_MAJREV_Pos)     /*!< 0x000000F0 */
25167 #define TAMP_VERR_MAJREV                    TAMP_VERR_MAJREV_Msk
25168 #define TAMP_VERR_MAJREV_0                  (0x1U << TAMP_VERR_MAJREV_Pos)     /*!< 0x00000010 */
25169 #define TAMP_VERR_MAJREV_1                  (0x2U << TAMP_VERR_MAJREV_Pos)     /*!< 0x00000020 */
25170 #define TAMP_VERR_MAJREV_2                  (0x4U << TAMP_VERR_MAJREV_Pos)     /*!< 0x00000040 */
25171 #define TAMP_VERR_MAJREV_3                  (0x8U << TAMP_VERR_MAJREV_Pos)     /*!< 0x00000080 */
25172 #define TAMP_VERR_MINREV_Pos                (0U)
25173 #define TAMP_VERR_MINREV_Msk                (0xFU << TAMP_VERR_MINREV_Pos)     /*!< 0x0000000F */
25174 #define TAMP_VERR_MINREV                    TAMP_VERR_MINREV_Msk
25175 #define TAMP_VERR_MINREV_0                  (0x1U << TAMP_VERR_MINREV_Pos)     /*!< 0x00000001 */
25176 #define TAMP_VERR_MINREV_1                  (0x2U << TAMP_VERR_MINREV_Pos)     /*!< 0x00000002 */
25177 #define TAMP_VERR_MINREV_2                  (0x4U << TAMP_VERR_MINREV_Pos)     /*!< 0x00000004 */
25178 #define TAMP_VERR_MINREV_3                  (0x8U << TAMP_VERR_MINREV_Pos)     /*!< 0x00000008 */
25179 
25180 /********************  Bits definition for TAMP_IPIDR register  ****************/
25181 #define TAMP_IPIDR_ID_Pos                   (0U)
25182 #define TAMP_IPIDR_ID_Msk                   (0xFFFFFFFFU << TAMP_IPIDR_ID_Pos) /*!< 0xFFFFFFFF */
25183 #define TAMP_IPIDR_ID                       TAMP_IPIDR_ID_Msk
25184 
25185 /********************  Bits definition for TAMP_SIDR register  ****************/
25186 #define TAMP_SIDR_SID_Pos                   (0U)
25187 #define TAMP_SIDR_SID_Msk                   (0xFFFFFFFFU << TAMP_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
25188 #define TAMP_SIDR_SID                       TAMP_SIDR_SID_Msk
25189 
25190 /******************** Number of backup registers ******************************/
25191 #define TAMP_BKP_NUMBER_Pos                 (5U)
25192 #define TAMP_BKP_NUMBER_Msk                 (0x1U << TAMP_BKP_NUMBER_Pos)      /*!< 0x00000020 */
25193 #define TAMP_BKP_NUMBER                     TAMP_BKP_NUMBER_Msk
25194 
25195 /******************** Number of tamper registers ******************************/
25196 #define TAMP_TAMPER_NUMBER_Pos              (0U)
25197 #define TAMP_TAMPER_NUMBER_Msk              (0x3U << TAMP_TAMPER_NUMBER_Pos)   /*!< 0x00000003 */
25198 #define TAMP_TAMPER_NUMBER                  TAMP_TAMPER_NUMBER_Msk
25199 
25200 /******************************************************************************/
25201 /*                                                                            */
25202 /*                              SPDIF-RX Interface                            */
25203 /*                                                                            */
25204 /******************************************************************************/
25205 /********************  Bit definition for SPDIF_CR register  *******************/
25206 #define SPDIFRX_CR_SPDIFEN_Pos      (0U)
25207 #define SPDIFRX_CR_SPDIFEN_Msk      (0x3U << SPDIFRX_CR_SPDIFEN_Pos)           /*!< 0x00000003 */
25208 #define SPDIFRX_CR_SPDIFEN          SPDIFRX_CR_SPDIFEN_Msk                     /*!<Peripheral Block Enable                      */
25209 #define SPDIFRX_CR_RXDMAEN_Pos      (2U)
25210 #define SPDIFRX_CR_RXDMAEN_Msk      (0x1U << SPDIFRX_CR_RXDMAEN_Pos)           /*!< 0x00000004 */
25211 #define SPDIFRX_CR_RXDMAEN          SPDIFRX_CR_RXDMAEN_Msk                     /*!<Receiver DMA Enable for data flow            */
25212 #define SPDIFRX_CR_RXSTEO_Pos       (3U)
25213 #define SPDIFRX_CR_RXSTEO_Msk       (0x1U << SPDIFRX_CR_RXSTEO_Pos)            /*!< 0x00000008 */
25214 #define SPDIFRX_CR_RXSTEO           SPDIFRX_CR_RXSTEO_Msk                      /*!<Stereo Mode                                  */
25215 #define SPDIFRX_CR_DRFMT_Pos        (4U)
25216 #define SPDIFRX_CR_DRFMT_Msk        (0x3U << SPDIFRX_CR_DRFMT_Pos)             /*!< 0x00000030 */
25217 #define SPDIFRX_CR_DRFMT            SPDIFRX_CR_DRFMT_Msk                       /*!<RX Data format                               */
25218 #define SPDIFRX_CR_PMSK_Pos         (6U)
25219 #define SPDIFRX_CR_PMSK_Msk         (0x1U << SPDIFRX_CR_PMSK_Pos)              /*!< 0x00000040 */
25220 #define SPDIFRX_CR_PMSK             SPDIFRX_CR_PMSK_Msk                        /*!<Mask Parity error bit                        */
25221 #define SPDIFRX_CR_VMSK_Pos         (7U)
25222 #define SPDIFRX_CR_VMSK_Msk         (0x1U << SPDIFRX_CR_VMSK_Pos)              /*!< 0x00000080 */
25223 #define SPDIFRX_CR_VMSK             SPDIFRX_CR_VMSK_Msk                        /*!<Mask of Validity bit                         */
25224 #define SPDIFRX_CR_CUMSK_Pos        (8U)
25225 #define SPDIFRX_CR_CUMSK_Msk        (0x1U << SPDIFRX_CR_CUMSK_Pos)             /*!< 0x00000100 */
25226 #define SPDIFRX_CR_CUMSK            SPDIFRX_CR_CUMSK_Msk                       /*!<Mask of channel status and user bits         */
25227 #define SPDIFRX_CR_PTMSK_Pos        (9U)
25228 #define SPDIFRX_CR_PTMSK_Msk        (0x1U << SPDIFRX_CR_PTMSK_Pos)             /*!< 0x00000200 */
25229 #define SPDIFRX_CR_PTMSK            SPDIFRX_CR_PTMSK_Msk                       /*!<Mask of Preamble Type bits                   */
25230 #define SPDIFRX_CR_CBDMAEN_Pos      (10U)
25231 #define SPDIFRX_CR_CBDMAEN_Msk      (0x1U << SPDIFRX_CR_CBDMAEN_Pos)           /*!< 0x00000400 */
25232 #define SPDIFRX_CR_CBDMAEN          SPDIFRX_CR_CBDMAEN_Msk                     /*!<Control Buffer DMA ENable for control flow   */
25233 #define SPDIFRX_CR_CHSEL_Pos        (11U)
25234 #define SPDIFRX_CR_CHSEL_Msk        (0x1U << SPDIFRX_CR_CHSEL_Pos)             /*!< 0x00000800 */
25235 #define SPDIFRX_CR_CHSEL            SPDIFRX_CR_CHSEL_Msk                       /*!<Channel Selection                            */
25236 #define SPDIFRX_CR_NBTR_Pos         (12U)
25237 #define SPDIFRX_CR_NBTR_Msk         (0x3U << SPDIFRX_CR_NBTR_Pos)              /*!< 0x00003000 */
25238 #define SPDIFRX_CR_NBTR             SPDIFRX_CR_NBTR_Msk                        /*!<Maximum allowed re-tries during synchronization phase */
25239 #define SPDIFRX_CR_WFA_Pos          (14U)
25240 #define SPDIFRX_CR_WFA_Msk          (0x1U << SPDIFRX_CR_WFA_Pos)               /*!< 0x00004000 */
25241 #define SPDIFRX_CR_WFA              SPDIFRX_CR_WFA_Msk                         /*!<Wait For Activity     */
25242 #define SPDIFRX_CR_INSEL_Pos        (16U)
25243 #define SPDIFRX_CR_INSEL_Msk        (0x7U << SPDIFRX_CR_INSEL_Pos)             /*!< 0x00070000 */
25244 #define SPDIFRX_CR_INSEL            SPDIFRX_CR_INSEL_Msk                       /*!<SPDIF input selection */
25245 
25246 /*******************  Bit definition for SPDIFRX_IMR register  *******************/
25247 #define SPDIFRX_IMR_RXNEIE_Pos      (0U)
25248 #define SPDIFRX_IMR_RXNEIE_Msk      (0x1U << SPDIFRX_IMR_RXNEIE_Pos)           /*!< 0x00000001 */
25249 #define SPDIFRX_IMR_RXNEIE          SPDIFRX_IMR_RXNEIE_Msk                     /*!<RXNE interrupt enable                              */
25250 #define SPDIFRX_IMR_CSRNEIE_Pos     (1U)
25251 #define SPDIFRX_IMR_CSRNEIE_Msk     (0x1U << SPDIFRX_IMR_CSRNEIE_Pos)          /*!< 0x00000002 */
25252 #define SPDIFRX_IMR_CSRNEIE         SPDIFRX_IMR_CSRNEIE_Msk                    /*!<Control Buffer Ready Interrupt Enable              */
25253 #define SPDIFRX_IMR_PERRIE_Pos      (2U)
25254 #define SPDIFRX_IMR_PERRIE_Msk      (0x1U << SPDIFRX_IMR_PERRIE_Pos)           /*!< 0x00000004 */
25255 #define SPDIFRX_IMR_PERRIE          SPDIFRX_IMR_PERRIE_Msk                     /*!<Parity error interrupt enable                      */
25256 #define SPDIFRX_IMR_OVRIE_Pos       (3U)
25257 #define SPDIFRX_IMR_OVRIE_Msk       (0x1U << SPDIFRX_IMR_OVRIE_Pos)            /*!< 0x00000008 */
25258 #define SPDIFRX_IMR_OVRIE           SPDIFRX_IMR_OVRIE_Msk                      /*!<Overrun error Interrupt Enable                     */
25259 #define SPDIFRX_IMR_SBLKIE_Pos      (4U)
25260 #define SPDIFRX_IMR_SBLKIE_Msk      (0x1U << SPDIFRX_IMR_SBLKIE_Pos)           /*!< 0x00000010 */
25261 #define SPDIFRX_IMR_SBLKIE          SPDIFRX_IMR_SBLKIE_Msk                     /*!<Synchronization Block Detected Interrupt Enable    */
25262 #define SPDIFRX_IMR_SYNCDIE_Pos     (5U)
25263 #define SPDIFRX_IMR_SYNCDIE_Msk     (0x1U << SPDIFRX_IMR_SYNCDIE_Pos)          /*!< 0x00000020 */
25264 #define SPDIFRX_IMR_SYNCDIE         SPDIFRX_IMR_SYNCDIE_Msk                    /*!<Synchronization Done                               */
25265 #define SPDIFRX_IMR_IFEIE_Pos       (6U)
25266 #define SPDIFRX_IMR_IFEIE_Msk       (0x1U << SPDIFRX_IMR_IFEIE_Pos)            /*!< 0x00000040 */
25267 #define SPDIFRX_IMR_IFEIE           SPDIFRX_IMR_IFEIE_Msk                      /*!<Serial Interface Error Interrupt Enable            */
25268 
25269 /*******************  Bit definition for SPDIFRX_SR register  *******************/
25270 #define SPDIFRX_SR_RXNE_Pos         (0U)
25271 #define SPDIFRX_SR_RXNE_Msk         (0x1U << SPDIFRX_SR_RXNE_Pos)              /*!< 0x00000001 */
25272 #define SPDIFRX_SR_RXNE             SPDIFRX_SR_RXNE_Msk                        /*!<Read data register not empty                          */
25273 #define SPDIFRX_SR_CSRNE_Pos        (1U)
25274 #define SPDIFRX_SR_CSRNE_Msk        (0x1U << SPDIFRX_SR_CSRNE_Pos)             /*!< 0x00000002 */
25275 #define SPDIFRX_SR_CSRNE            SPDIFRX_SR_CSRNE_Msk                       /*!<The Control Buffer register is not empty              */
25276 #define SPDIFRX_SR_PERR_Pos         (2U)
25277 #define SPDIFRX_SR_PERR_Msk         (0x1U << SPDIFRX_SR_PERR_Pos)              /*!< 0x00000004 */
25278 #define SPDIFRX_SR_PERR             SPDIFRX_SR_PERR_Msk                        /*!<Parity error                                          */
25279 #define SPDIFRX_SR_OVR_Pos          (3U)
25280 #define SPDIFRX_SR_OVR_Msk          (0x1U << SPDIFRX_SR_OVR_Pos)               /*!< 0x00000008 */
25281 #define SPDIFRX_SR_OVR              SPDIFRX_SR_OVR_Msk                         /*!<Overrun error                                         */
25282 #define SPDIFRX_SR_SBD_Pos          (4U)
25283 #define SPDIFRX_SR_SBD_Msk          (0x1U << SPDIFRX_SR_SBD_Pos)               /*!< 0x00000010 */
25284 #define SPDIFRX_SR_SBD              SPDIFRX_SR_SBD_Msk                         /*!<Synchronization Block Detected                        */
25285 #define SPDIFRX_SR_SYNCD_Pos        (5U)
25286 #define SPDIFRX_SR_SYNCD_Msk        (0x1U << SPDIFRX_SR_SYNCD_Pos)             /*!< 0x00000020 */
25287 #define SPDIFRX_SR_SYNCD            SPDIFRX_SR_SYNCD_Msk                       /*!<Synchronization Done                                  */
25288 #define SPDIFRX_SR_FERR_Pos         (6U)
25289 #define SPDIFRX_SR_FERR_Msk         (0x1U << SPDIFRX_SR_FERR_Pos)              /*!< 0x00000040 */
25290 #define SPDIFRX_SR_FERR             SPDIFRX_SR_FERR_Msk                        /*!<Framing error                                         */
25291 #define SPDIFRX_SR_SERR_Pos         (7U)
25292 #define SPDIFRX_SR_SERR_Msk         (0x1U << SPDIFRX_SR_SERR_Pos)              /*!< 0x00000080 */
25293 #define SPDIFRX_SR_SERR             SPDIFRX_SR_SERR_Msk                        /*!<Synchronization error                                 */
25294 #define SPDIFRX_SR_TERR_Pos         (8U)
25295 #define SPDIFRX_SR_TERR_Msk         (0x1U << SPDIFRX_SR_TERR_Pos)              /*!< 0x00000100 */
25296 #define SPDIFRX_SR_TERR             SPDIFRX_SR_TERR_Msk                        /*!<Time-out error                                        */
25297 #define SPDIFRX_SR_WIDTH5_Pos       (16U)
25298 #define SPDIFRX_SR_WIDTH5_Msk       (0x7FFFU << SPDIFRX_SR_WIDTH5_Pos)         /*!< 0x7FFF0000 */
25299 #define SPDIFRX_SR_WIDTH5           SPDIFRX_SR_WIDTH5_Msk                      /*!<Duration of 5 symbols counted with spdif_clk          */
25300 
25301 /*******************  Bit definition for SPDIFRX_IFCR register  *******************/
25302 #define SPDIFRX_IFCR_PERRCF_Pos     (2U)
25303 #define SPDIFRX_IFCR_PERRCF_Msk     (0x1U << SPDIFRX_IFCR_PERRCF_Pos)          /*!< 0x00000004 */
25304 #define SPDIFRX_IFCR_PERRCF         SPDIFRX_IFCR_PERRCF_Msk                    /*!<Clears the Parity error flag                         */
25305 #define SPDIFRX_IFCR_OVRCF_Pos      (3U)
25306 #define SPDIFRX_IFCR_OVRCF_Msk      (0x1U << SPDIFRX_IFCR_OVRCF_Pos)           /*!< 0x00000008 */
25307 #define SPDIFRX_IFCR_OVRCF          SPDIFRX_IFCR_OVRCF_Msk                     /*!<Clears the Overrun error flag                        */
25308 #define SPDIFRX_IFCR_SBDCF_Pos      (4U)
25309 #define SPDIFRX_IFCR_SBDCF_Msk      (0x1U << SPDIFRX_IFCR_SBDCF_Pos)           /*!< 0x00000010 */
25310 #define SPDIFRX_IFCR_SBDCF          SPDIFRX_IFCR_SBDCF_Msk                     /*!<Clears the Synchronization Block Detected flag       */
25311 #define SPDIFRX_IFCR_SYNCDCF_Pos    (5U)
25312 #define SPDIFRX_IFCR_SYNCDCF_Msk    (0x1U << SPDIFRX_IFCR_SYNCDCF_Pos)         /*!< 0x00000020 */
25313 #define SPDIFRX_IFCR_SYNCDCF        SPDIFRX_IFCR_SYNCDCF_Msk                   /*!<Clears the Synchronization Done flag                 */
25314 
25315 /*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b00 case) *******************/
25316 #define SPDIFRX_DR0_DR_Pos          (0U)
25317 #define SPDIFRX_DR0_DR_Msk          (0xFFFFFFU << SPDIFRX_DR0_DR_Pos)          /*!< 0x00FFFFFF */
25318 #define SPDIFRX_DR0_DR              SPDIFRX_DR0_DR_Msk                         /*!<Data value            */
25319 #define SPDIFRX_DR0_PE_Pos          (24U)
25320 #define SPDIFRX_DR0_PE_Msk          (0x1U << SPDIFRX_DR0_PE_Pos)               /*!< 0x01000000 */
25321 #define SPDIFRX_DR0_PE              SPDIFRX_DR0_PE_Msk                         /*!<Parity Error bit      */
25322 #define SPDIFRX_DR0_V_Pos           (25U)
25323 #define SPDIFRX_DR0_V_Msk           (0x1U << SPDIFRX_DR0_V_Pos)                /*!< 0x02000000 */
25324 #define SPDIFRX_DR0_V               SPDIFRX_DR0_V_Msk                          /*!<Validity bit          */
25325 #define SPDIFRX_DR0_U_Pos           (26U)
25326 #define SPDIFRX_DR0_U_Msk           (0x1U << SPDIFRX_DR0_U_Pos)                /*!< 0x04000000 */
25327 #define SPDIFRX_DR0_U               SPDIFRX_DR0_U_Msk                          /*!<User bit              */
25328 #define SPDIFRX_DR0_C_Pos           (27U)
25329 #define SPDIFRX_DR0_C_Msk           (0x1U << SPDIFRX_DR0_C_Pos)                /*!< 0x08000000 */
25330 #define SPDIFRX_DR0_C               SPDIFRX_DR0_C_Msk                          /*!<Channel Status bit    */
25331 #define SPDIFRX_DR0_PT_Pos          (28U)
25332 #define SPDIFRX_DR0_PT_Msk          (0x3U << SPDIFRX_DR0_PT_Pos)               /*!< 0x30000000 */
25333 #define SPDIFRX_DR0_PT              SPDIFRX_DR0_PT_Msk                         /*!<Preamble Type         */
25334 
25335 /*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b01 case) *******************/
25336 #define SPDIFRX_DR1_DR_Pos          (8U)
25337 #define SPDIFRX_DR1_DR_Msk          (0xFFFFFFU << SPDIFRX_DR1_DR_Pos)          /*!< 0xFFFFFF00 */
25338 #define SPDIFRX_DR1_DR              SPDIFRX_DR1_DR_Msk                         /*!<Data value            */
25339 #define SPDIFRX_DR1_PT_Pos          (4U)
25340 #define SPDIFRX_DR1_PT_Msk          (0x3U << SPDIFRX_DR1_PT_Pos)               /*!< 0x00000030 */
25341 #define SPDIFRX_DR1_PT              SPDIFRX_DR1_PT_Msk                         /*!<Preamble Type         */
25342 #define SPDIFRX_DR1_C_Pos           (3U)
25343 #define SPDIFRX_DR1_C_Msk           (0x1U << SPDIFRX_DR1_C_Pos)                /*!< 0x00000008 */
25344 #define SPDIFRX_DR1_C               SPDIFRX_DR1_C_Msk                          /*!<Channel Status bit    */
25345 #define SPDIFRX_DR1_U_Pos           (2U)
25346 #define SPDIFRX_DR1_U_Msk           (0x1U << SPDIFRX_DR1_U_Pos)                /*!< 0x00000004 */
25347 #define SPDIFRX_DR1_U               SPDIFRX_DR1_U_Msk                          /*!<User bit              */
25348 #define SPDIFRX_DR1_V_Pos           (1U)
25349 #define SPDIFRX_DR1_V_Msk           (0x1U << SPDIFRX_DR1_V_Pos)                /*!< 0x00000002 */
25350 #define SPDIFRX_DR1_V               SPDIFRX_DR1_V_Msk                          /*!<Validity bit          */
25351 #define SPDIFRX_DR1_PE_Pos          (0U)
25352 #define SPDIFRX_DR1_PE_Msk          (0x1U << SPDIFRX_DR1_PE_Pos)               /*!< 0x00000001 */
25353 #define SPDIFRX_DR1_PE              SPDIFRX_DR1_PE_Msk                         /*!<Parity Error bit      */
25354 
25355 /*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b10 case) *******************/
25356 #define SPDIFRX_DR1_DRNL1_Pos       (16U)
25357 #define SPDIFRX_DR1_DRNL1_Msk       (0xFFFFU << SPDIFRX_DR1_DRNL1_Pos)         /*!< 0xFFFF0000 */
25358 #define SPDIFRX_DR1_DRNL1           SPDIFRX_DR1_DRNL1_Msk                      /*!<Data value Channel B      */
25359 #define SPDIFRX_DR1_DRNL2_Pos       (0U)
25360 #define SPDIFRX_DR1_DRNL2_Msk       (0xFFFFU << SPDIFRX_DR1_DRNL2_Pos)         /*!< 0x0000FFFF */
25361 #define SPDIFRX_DR1_DRNL2           SPDIFRX_DR1_DRNL2_Msk                      /*!<Data value Channel A      */
25362 
25363 /*******************  Bit definition for SPDIFRX_CSR register   *******************/
25364 #define SPDIFRX_CSR_USR_Pos         (0U)
25365 #define SPDIFRX_CSR_USR_Msk         (0xFFFFU << SPDIFRX_CSR_USR_Pos)           /*!< 0x0000FFFF */
25366 #define SPDIFRX_CSR_USR             SPDIFRX_CSR_USR_Msk                        /*!<User data information           */
25367 #define SPDIFRX_CSR_CS_Pos          (16U)
25368 #define SPDIFRX_CSR_CS_Msk          (0xFFU << SPDIFRX_CSR_CS_Pos)              /*!< 0x00FF0000 */
25369 #define SPDIFRX_CSR_CS              SPDIFRX_CSR_CS_Msk                         /*!<Channel A status information    */
25370 #define SPDIFRX_CSR_SOB_Pos         (24U)
25371 #define SPDIFRX_CSR_SOB_Msk         (0x1U << SPDIFRX_CSR_SOB_Pos)              /*!< 0x01000000 */
25372 #define SPDIFRX_CSR_SOB             SPDIFRX_CSR_SOB_Msk                        /*!<Start Of Block                  */
25373 
25374 /*******************  Bit definition for SPDIFRX_DIR register    *******************/
25375 #define SPDIFRX_DIR_THI_Pos         (0U)
25376 #define SPDIFRX_DIR_THI_Msk         (0x1FFFU << SPDIFRX_DIR_THI_Pos)           /*!< 0x00001FFF */
25377 #define SPDIFRX_DIR_THI             SPDIFRX_DIR_THI_Msk                        /*!<Threshold LOW      */
25378 #define SPDIFRX_DIR_TLO_Pos         (16U)
25379 #define SPDIFRX_DIR_TLO_Msk         (0x1FFFU << SPDIFRX_DIR_TLO_Pos)           /*!< 0x1FFF0000 */
25380 #define SPDIFRX_DIR_TLO             SPDIFRX_DIR_TLO_Msk                        /*!<Threshold HIGH     */
25381 
25382 /**********************  Bit definition for SPDIFRX_VERR register  *****************/
25383 #define SPDIFRX_VERR_MINREV_Pos      (0U)
25384 #define SPDIFRX_VERR_MINREV_Msk      (0xFU << SPDIFRX_VERR_MINREV_Pos)               /*!< 0x0000000F */
25385 #define SPDIFRX_VERR_MINREV          SPDIFRX_VERR_MINREV_Msk                         /*!< Minor Revision number */
25386 #define SPDIFRX_VERR_MAJREV_Pos      (4U)
25387 #define SPDIFRX_VERR_MAJREV_Msk      (0xFU << SPDIFRX_VERR_MAJREV_Pos)               /*!< 0x000000F0 */
25388 #define SPDIFRX_VERR_MAJREV          SPDIFRX_VERR_MAJREV_Msk                         /*!< Major Revision number */
25389 
25390 /**********************  Bit definition for SPDIFRX_IPIDR register  ****************/
25391 #define SPDIFRX_IPIDR_IPID_Pos       (0U)
25392 #define SPDIFRX_IPIDR_IPID_Msk       (0xFFFFFFFFU << SPDIFRX_IPIDR_IPID_Pos)         /*!< 0xFFFFFFFF */
25393 #define SPDIFRX_IPIDR_IPID           SPDIFRX_IPIDR_IPID_Msk                          /*!< IP Identification */
25394 
25395 /**********************  Bit definition for SPDIFRX_SIDR register  *****************/
25396 #define SPDIFRX_SIDR_SID_Pos         (0U)
25397 #define SPDIFRX_SIDR_SID_Msk         (0xFFFFFFFFU << SPDIFRX_SIDR_SID_Pos)           /*!< 0xFFFFFFFF */
25398 #define SPDIFRX_SIDR_SID             SPDIFRX_SIDR_SID_Msk                            /*!< IP size identification */
25399 
25400 /******************************************************************************/
25401 /*                                                                            */
25402 /*                          Serial Audio Interface                            */
25403 /*                                                                            */
25404 /******************************************************************************/
25405 /********************  Bit definition for SAI_GCR register  *******************/
25406 #define SAI_GCR_SYNCIN_Pos         (0U)
25407 #define SAI_GCR_SYNCIN_Msk         (0x3UL << SAI_GCR_SYNCIN_Pos)               /*!< 0x00000003 */
25408 #define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
25409 #define SAI_GCR_SYNCIN_0           (0x1U << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000001 */
25410 #define SAI_GCR_SYNCIN_1           (0x2U << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000002 */
25411 
25412 #define SAI_GCR_SYNCOUT_Pos        (4U)
25413 #define SAI_GCR_SYNCOUT_Msk        (0x3UL << SAI_GCR_SYNCOUT_Pos)              /*!< 0x00000030 */
25414 #define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
25415 #define SAI_GCR_SYNCOUT_0          (0x1U << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000010 */
25416 #define SAI_GCR_SYNCOUT_1          (0x2U << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000020 */
25417 
25418 /*******************  Bit definition for SAI_xCR1 register  *******************/
25419 #define SAI_xCR1_MODE_Pos          (0U)
25420 #define SAI_xCR1_MODE_Msk          (0x3UL << SAI_xCR1_MODE_Pos)                /*!< 0x00000003 */
25421 #define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */
25422 #define SAI_xCR1_MODE_0            (0x1U << SAI_xCR1_MODE_Pos)                 /*!< 0x00000001 */
25423 #define SAI_xCR1_MODE_1            (0x2U << SAI_xCR1_MODE_Pos)                 /*!< 0x00000002 */
25424 
25425 #define SAI_xCR1_PRTCFG_Pos        (2U)
25426 #define SAI_xCR1_PRTCFG_Msk        (0x3UL << SAI_xCR1_PRTCFG_Pos)              /*!< 0x0000000C */
25427 #define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
25428 #define SAI_xCR1_PRTCFG_0          (0x1U << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000004 */
25429 #define SAI_xCR1_PRTCFG_1          (0x2U << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000008 */
25430 
25431 #define SAI_xCR1_DS_Pos            (5U)
25432 #define SAI_xCR1_DS_Msk            (0x7UL << SAI_xCR1_DS_Pos)                  /*!< 0x000000E0 */
25433 #define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */
25434 #define SAI_xCR1_DS_0              (0x1U << SAI_xCR1_DS_Pos)                   /*!< 0x00000020 */
25435 #define SAI_xCR1_DS_1              (0x2U << SAI_xCR1_DS_Pos)                   /*!< 0x00000040 */
25436 #define SAI_xCR1_DS_2              (0x4U << SAI_xCR1_DS_Pos)                   /*!< 0x00000080 */
25437 
25438 #define SAI_xCR1_LSBFIRST_Pos      (8U)
25439 #define SAI_xCR1_LSBFIRST_Msk      (0x1UL << SAI_xCR1_LSBFIRST_Pos)            /*!< 0x00000100 */
25440 #define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */
25441 #define SAI_xCR1_CKSTR_Pos         (9U)
25442 #define SAI_xCR1_CKSTR_Msk         (0x1UL << SAI_xCR1_CKSTR_Pos)               /*!< 0x00000200 */
25443 #define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */
25444 
25445 #define SAI_xCR1_SYNCEN_Pos        (10U)
25446 #define SAI_xCR1_SYNCEN_Msk        (0x3UL << SAI_xCR1_SYNCEN_Pos)              /*!< 0x00000C00 */
25447 #define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */
25448 #define SAI_xCR1_SYNCEN_0          (0x1U << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000400 */
25449 #define SAI_xCR1_SYNCEN_1          (0x2U << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000800 */
25450 
25451 #define SAI_xCR1_MONO_Pos          (12U)
25452 #define SAI_xCR1_MONO_Msk          (0x1UL << SAI_xCR1_MONO_Pos)                /*!< 0x00001000 */
25453 #define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */
25454 #define SAI_xCR1_OUTDRIV_Pos       (13U)
25455 #define SAI_xCR1_OUTDRIV_Msk       (0x1UL << SAI_xCR1_OUTDRIV_Pos)             /*!< 0x00002000 */
25456 #define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */
25457 #define SAI_xCR1_SAIEN_Pos         (16U)
25458 #define SAI_xCR1_SAIEN_Msk         (0x1UL << SAI_xCR1_SAIEN_Pos)               /*!< 0x00010000 */
25459 #define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */
25460 #define SAI_xCR1_DMAEN_Pos         (17U)
25461 #define SAI_xCR1_DMAEN_Msk         (0x1UL << SAI_xCR1_DMAEN_Pos)               /*!< 0x00020000 */
25462 #define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */
25463 #define SAI_xCR1_NODIV_Pos         (19U)
25464 #define SAI_xCR1_NODIV_Msk         (0x1UL << SAI_xCR1_NODIV_Pos)               /*!< 0x00080000 */
25465 #define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */
25466 
25467 #define SAI_xCR1_MCKDIV_Pos        (20U)
25468 #define SAI_xCR1_MCKDIV_Msk        (0x3FUL << SAI_xCR1_MCKDIV_Pos)             /*!< 0x03F00000 */
25469 #define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[5:0] (Master ClocK Divider)  */
25470 #define SAI_xCR1_MCKDIV_0          (0x01U << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00100000 */
25471 #define SAI_xCR1_MCKDIV_1          (0x02U << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00200000 */
25472 #define SAI_xCR1_MCKDIV_2          (0x04U << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00400000 */
25473 #define SAI_xCR1_MCKDIV_3          (0x08U << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00800000 */
25474 #define SAI_xCR1_MCKDIV_4          (0x10U << SAI_xCR1_MCKDIV_Pos)              /*!< 0x01000000 */
25475 #define SAI_xCR1_MCKDIV_5          (0x20U << SAI_xCR1_MCKDIV_Pos)              /*!< 0x02000000 */
25476 
25477 #define SAI_xCR1_MCKEN_Pos         (27U)
25478 #define SAI_xCR1_MCKEN_Msk         (0x1UL << SAI_xCR1_MCKEN_Pos)               /*!< 0x08000000 */
25479 #define SAI_xCR1_MCKEN             SAI_xCR1_MCKEN_Msk                          /*!<Master ClocK enable */
25480 
25481 #define SAI_xCR1_OSR_Pos           (26U)
25482 #define SAI_xCR1_OSR_Msk           (0x1UL << SAI_xCR1_OSR_Pos)                 /*!< 0x04000000 */
25483 #define SAI_xCR1_OSR               SAI_xCR1_OSR_Msk                            /*!<OverSampling Ratio for master clock  */
25484 
25485 /* Legacy define */
25486 #define  SAI_xCR1_NOMCK               SAI_xCR1_NODIV
25487 
25488 /*******************  Bit definition for SAI_xCR2 register  *******************/
25489 #define SAI_xCR2_FTH_Pos           (0U)
25490 #define SAI_xCR2_FTH_Msk           (0x7UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000007 */
25491 #define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */
25492 #define SAI_xCR2_FTH_0             (0x1U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000001 */
25493 #define SAI_xCR2_FTH_1             (0x2U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000002 */
25494 #define SAI_xCR2_FTH_2             (0x4U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000004 */
25495 
25496 #define SAI_xCR2_FFLUSH_Pos        (3U)
25497 #define SAI_xCR2_FFLUSH_Msk        (0x1UL << SAI_xCR2_FFLUSH_Pos)              /*!< 0x00000008 */
25498 #define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */
25499 #define SAI_xCR2_TRIS_Pos          (4U)
25500 #define SAI_xCR2_TRIS_Msk          (0x1UL << SAI_xCR2_TRIS_Pos)                /*!< 0x00000010 */
25501 #define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */
25502 #define SAI_xCR2_MUTE_Pos          (5U)
25503 #define SAI_xCR2_MUTE_Msk          (0x1UL << SAI_xCR2_MUTE_Pos)                /*!< 0x00000020 */
25504 #define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */
25505 #define SAI_xCR2_MUTEVAL_Pos       (6U)
25506 #define SAI_xCR2_MUTEVAL_Msk       (0x1UL << SAI_xCR2_MUTEVAL_Pos)             /*!< 0x00000040 */
25507 #define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */
25508 
25509 #define SAI_xCR2_MUTECNT_Pos       (7U)
25510 #define SAI_xCR2_MUTECNT_Msk       (0x3FUL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00001F80 */
25511 #define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */
25512 #define SAI_xCR2_MUTECNT_0         (0x01U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000080 */
25513 #define SAI_xCR2_MUTECNT_1         (0x02U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000100 */
25514 #define SAI_xCR2_MUTECNT_2         (0x04U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000200 */
25515 #define SAI_xCR2_MUTECNT_3         (0x08U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000400 */
25516 #define SAI_xCR2_MUTECNT_4         (0x10U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000800 */
25517 #define SAI_xCR2_MUTECNT_5         (0x20U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001000 */
25518 
25519 #define SAI_xCR2_CPL_Pos           (13U)
25520 #define SAI_xCR2_CPL_Msk           (0x1UL << SAI_xCR2_CPL_Pos)                 /*!< 0x00002000 */
25521 #define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!< Complement Bit             */
25522 
25523 #define SAI_xCR2_COMP_Pos          (14U)
25524 #define SAI_xCR2_COMP_Msk          (0x3UL << SAI_xCR2_COMP_Pos)                /*!< 0x0000C000 */
25525 #define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */
25526 #define SAI_xCR2_COMP_0            (0x1U << SAI_xCR2_COMP_Pos)                 /*!< 0x00004000 */
25527 #define SAI_xCR2_COMP_1            (0x2U << SAI_xCR2_COMP_Pos)                 /*!< 0x00008000 */
25528 
25529 /******************  Bit definition for SAI_xFRCR register  *******************/
25530 #define SAI_xFRCR_FRL_Pos          (0U)
25531 #define SAI_xFRCR_FRL_Msk          (0xFFUL << SAI_xFRCR_FRL_Pos)               /*!< 0x000000FF */
25532 #define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](FRame Length)  */
25533 #define SAI_xFRCR_FRL_0            (0x01U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000001 */
25534 #define SAI_xFRCR_FRL_1            (0x02U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000002 */
25535 #define SAI_xFRCR_FRL_2            (0x04U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000004 */
25536 #define SAI_xFRCR_FRL_3            (0x08U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000008 */
25537 #define SAI_xFRCR_FRL_4            (0x10U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000010 */
25538 #define SAI_xFRCR_FRL_5            (0x20U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000020 */
25539 #define SAI_xFRCR_FRL_6            (0x40U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000040 */
25540 #define SAI_xFRCR_FRL_7            (0x80U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000080 */
25541 
25542 #define SAI_xFRCR_FSALL_Pos        (8U)
25543 #define SAI_xFRCR_FSALL_Msk        (0x7FUL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00007F00 */
25544 #define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FSALL[6:0] (Frame Synchronization Active Level Length)  */
25545 #define SAI_xFRCR_FSALL_0          (0x01U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000100 */
25546 #define SAI_xFRCR_FSALL_1          (0x02U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000200 */
25547 #define SAI_xFRCR_FSALL_2          (0x04U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000400 */
25548 #define SAI_xFRCR_FSALL_3          (0x08U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000800 */
25549 #define SAI_xFRCR_FSALL_4          (0x10U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00001000 */
25550 #define SAI_xFRCR_FSALL_5          (0x20U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00002000 */
25551 #define SAI_xFRCR_FSALL_6          (0x40U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00004000 */
25552 
25553 #define SAI_xFRCR_FSDEF_Pos        (16U)
25554 #define SAI_xFRCR_FSDEF_Msk        (0x1UL << SAI_xFRCR_FSDEF_Pos)              /*!< 0x00010000 */
25555 #define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!<Frame Synchronization Definition  */
25556 #define SAI_xFRCR_FSPOL_Pos        (17U)
25557 #define SAI_xFRCR_FSPOL_Msk        (0x1UL << SAI_xFRCR_FSPOL_Pos)              /*!< 0x00020000 */
25558 #define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */
25559 #define SAI_xFRCR_FSOFF_Pos        (18U)
25560 #define SAI_xFRCR_FSOFF_Msk        (0x1UL << SAI_xFRCR_FSOFF_Pos)              /*!< 0x00040000 */
25561 #define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */
25562 
25563 /* Legacy define */
25564 #define  SAI_xFRCR_FSPO                      SAI_xFRCR_FSPOL
25565 
25566 /******************  Bit definition for SAI_xSLOTR register  *******************/
25567 #define SAI_xSLOTR_FBOFF_Pos       (0U)
25568 #define SAI_xSLOTR_FBOFF_Msk       (0x1FUL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x0000001F */
25569 #define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FBOFF[4:0](First Bit Offset)  */
25570 #define SAI_xSLOTR_FBOFF_0         (0x01U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000001 */
25571 #define SAI_xSLOTR_FBOFF_1         (0x02U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000002 */
25572 #define SAI_xSLOTR_FBOFF_2         (0x04U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000004 */
25573 #define SAI_xSLOTR_FBOFF_3         (0x08U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000008 */
25574 #define SAI_xSLOTR_FBOFF_4         (0x10U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000010 */
25575 
25576 #define SAI_xSLOTR_SLOTSZ_Pos      (6U)
25577 #define SAI_xSLOTR_SLOTSZ_Msk      (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)            /*!< 0x000000C0 */
25578 #define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */
25579 #define SAI_xSLOTR_SLOTSZ_0        (0x1U << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000040 */
25580 #define SAI_xSLOTR_SLOTSZ_1        (0x2U << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000080 */
25581 
25582 #define SAI_xSLOTR_NBSLOT_Pos      (8U)
25583 #define SAI_xSLOTR_NBSLOT_Msk      (0xFUL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000F00 */
25584 #define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
25585 #define SAI_xSLOTR_NBSLOT_0        (0x1U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000100 */
25586 #define SAI_xSLOTR_NBSLOT_1        (0x2U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000200 */
25587 #define SAI_xSLOTR_NBSLOT_2        (0x4U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000400 */
25588 #define SAI_xSLOTR_NBSLOT_3        (0x8U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000800 */
25589 
25590 #define SAI_xSLOTR_SLOTEN_Pos      (16U)
25591 #define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)         /*!< 0xFFFF0000 */
25592 #define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */
25593 
25594 /*******************  Bit definition for SAI_xIMR register  *******************/
25595 #define SAI_xIMR_OVRUDRIE_Pos      (0U)
25596 #define SAI_xIMR_OVRUDRIE_Msk      (0x1UL << SAI_xIMR_OVRUDRIE_Pos)            /*!< 0x00000001 */
25597 #define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */
25598 #define SAI_xIMR_MUTEDETIE_Pos     (1U)
25599 #define SAI_xIMR_MUTEDETIE_Msk     (0x1UL << SAI_xIMR_MUTEDETIE_Pos)           /*!< 0x00000002 */
25600 #define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */
25601 #define SAI_xIMR_WCKCFGIE_Pos      (2U)
25602 #define SAI_xIMR_WCKCFGIE_Msk      (0x1UL << SAI_xIMR_WCKCFGIE_Pos)            /*!< 0x00000004 */
25603 #define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */
25604 #define SAI_xIMR_FREQIE_Pos        (3U)
25605 #define SAI_xIMR_FREQIE_Msk        (0x1UL << SAI_xIMR_FREQIE_Pos)              /*!< 0x00000008 */
25606 #define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */
25607 #define SAI_xIMR_CNRDYIE_Pos       (4U)
25608 #define SAI_xIMR_CNRDYIE_Msk       (0x1UL << SAI_xIMR_CNRDYIE_Pos)             /*!< 0x00000010 */
25609 #define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */
25610 #define SAI_xIMR_AFSDETIE_Pos      (5U)
25611 #define SAI_xIMR_AFSDETIE_Msk      (0x1UL << SAI_xIMR_AFSDETIE_Pos)            /*!< 0x00000020 */
25612 #define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */
25613 #define SAI_xIMR_LFSDETIE_Pos      (6U)
25614 #define SAI_xIMR_LFSDETIE_Msk      (0x1UL << SAI_xIMR_LFSDETIE_Pos)            /*!< 0x00000040 */
25615 #define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */
25616 
25617 /********************  Bit definition for SAI_xSR register  *******************/
25618 #define SAI_xSR_OVRUDR_Pos         (0U)
25619 #define SAI_xSR_OVRUDR_Msk         (0x1UL << SAI_xSR_OVRUDR_Pos)               /*!< 0x00000001 */
25620 #define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */
25621 #define SAI_xSR_MUTEDET_Pos        (1U)
25622 #define SAI_xSR_MUTEDET_Msk        (0x1UL << SAI_xSR_MUTEDET_Pos)              /*!< 0x00000002 */
25623 #define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */
25624 #define SAI_xSR_WCKCFG_Pos         (2U)
25625 #define SAI_xSR_WCKCFG_Msk         (0x1UL << SAI_xSR_WCKCFG_Pos)               /*!< 0x00000004 */
25626 #define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */
25627 #define SAI_xSR_FREQ_Pos           (3U)
25628 #define SAI_xSR_FREQ_Msk           (0x1UL << SAI_xSR_FREQ_Pos)                 /*!< 0x00000008 */
25629 #define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */
25630 #define SAI_xSR_CNRDY_Pos          (4U)
25631 #define SAI_xSR_CNRDY_Msk          (0x1UL << SAI_xSR_CNRDY_Pos)                /*!< 0x00000010 */
25632 #define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */
25633 #define SAI_xSR_AFSDET_Pos         (5U)
25634 #define SAI_xSR_AFSDET_Msk         (0x1UL << SAI_xSR_AFSDET_Pos)               /*!< 0x00000020 */
25635 #define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */
25636 #define SAI_xSR_LFSDET_Pos         (6U)
25637 #define SAI_xSR_LFSDET_Msk         (0x1UL << SAI_xSR_LFSDET_Pos)               /*!< 0x00000040 */
25638 #define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */
25639 
25640 #define SAI_xSR_FLVL_Pos           (16U)
25641 #define SAI_xSR_FLVL_Msk           (0x7UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00070000 */
25642 #define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */
25643 #define SAI_xSR_FLVL_0             (0x1U << SAI_xSR_FLVL_Pos)                  /*!< 0x00010000 */
25644 #define SAI_xSR_FLVL_1             (0x2U << SAI_xSR_FLVL_Pos)                  /*!< 0x00020000 */
25645 #define SAI_xSR_FLVL_2             (0x4U << SAI_xSR_FLVL_Pos)                  /*!< 0x00040000 */
25646 
25647 /******************  Bit definition for SAI_xCLRFR register  ******************/
25648 #define SAI_xCLRFR_COVRUDR_Pos     (0U)
25649 #define SAI_xCLRFR_COVRUDR_Msk     (0x1UL << SAI_xCLRFR_COVRUDR_Pos)           /*!< 0x00000001 */
25650 #define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */
25651 #define SAI_xCLRFR_CMUTEDET_Pos    (1U)
25652 #define SAI_xCLRFR_CMUTEDET_Msk    (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)          /*!< 0x00000002 */
25653 #define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */
25654 #define SAI_xCLRFR_CWCKCFG_Pos     (2U)
25655 #define SAI_xCLRFR_CWCKCFG_Msk     (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)           /*!< 0x00000004 */
25656 #define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */
25657 #define SAI_xCLRFR_CFREQ_Pos       (3U)
25658 #define SAI_xCLRFR_CFREQ_Msk       (0x1UL << SAI_xCLRFR_CFREQ_Pos)             /*!< 0x00000008 */
25659 #define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */
25660 #define SAI_xCLRFR_CCNRDY_Pos      (4U)
25661 #define SAI_xCLRFR_CCNRDY_Msk      (0x1UL << SAI_xCLRFR_CCNRDY_Pos)            /*!< 0x00000010 */
25662 #define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */
25663 #define SAI_xCLRFR_CAFSDET_Pos     (5U)
25664 #define SAI_xCLRFR_CAFSDET_Msk     (0x1UL << SAI_xCLRFR_CAFSDET_Pos)           /*!< 0x00000020 */
25665 #define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */
25666 #define SAI_xCLRFR_CLFSDET_Pos     (6U)
25667 #define SAI_xCLRFR_CLFSDET_Msk     (0x1UL << SAI_xCLRFR_CLFSDET_Pos)           /*!< 0x00000040 */
25668 #define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */
25669 
25670 /******************  Bit definition for SAI_xDR register  *********************/
25671 #define SAI_xDR_DATA_Pos           (0U)
25672 #define SAI_xDR_DATA_Msk           (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)          /*!< 0xFFFFFFFF */
25673 #define SAI_xDR_DATA               SAI_xDR_DATA_Msk
25674 
25675 /*******************  Bit definition for SAI_PDMCR register  ******************/
25676 #define SAI_PDMCR_PDMEN_Pos        (0U)
25677 #define SAI_PDMCR_PDMEN_Msk        (0x1UL << SAI_PDMCR_PDMEN_Pos)              /*!< 0x00000001 */
25678 #define SAI_PDMCR_PDMEN            SAI_PDMCR_PDMEN_Msk                         /*!<PDM Enable                                          */
25679 
25680 #define SAI_PDMCR_MICNBR_Pos       (4U)
25681 #define SAI_PDMCR_MICNBR_Msk       (0x3UL << SAI_PDMCR_MICNBR_Pos)             /*!< 0x00000030 */
25682 #define SAI_PDMCR_MICNBR           SAI_PDMCR_MICNBR_Msk                        /*!<Number of microphones                               */
25683 #define SAI_PDMCR_MICNBR_0         (0x1U << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000010 */
25684 #define SAI_PDMCR_MICNBR_1         (0x2U << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000020 */
25685 
25686 #define SAI_PDMCR_CKEN1_Pos        (8U)
25687 #define SAI_PDMCR_CKEN1_Msk        (0x1UL << SAI_PDMCR_CKEN1_Pos)              /*!< 0x00000100 */
25688 #define SAI_PDMCR_CKEN1            SAI_PDMCR_CKEN1_Msk                         /*!<Clock enable of bitstream clock number 1            */
25689 #define SAI_PDMCR_CKEN2_Pos        (9U)
25690 #define SAI_PDMCR_CKEN2_Msk        (0x1UL << SAI_PDMCR_CKEN2_Pos)              /*!< 0x00000200 */
25691 #define SAI_PDMCR_CKEN2            SAI_PDMCR_CKEN2_Msk                         /*!<Clock enable of bitstream clock number 2            */
25692 #define SAI_PDMCR_CKEN3_Pos        (10U)
25693 #define SAI_PDMCR_CKEN3_Msk        (0x1UL << SAI_PDMCR_CKEN3_Pos)              /*!< 0x00000400 */
25694 #define SAI_PDMCR_CKEN3            SAI_PDMCR_CKEN3_Msk                         /*!<Clock enable of bitstream clock number 3            */
25695 #define SAI_PDMCR_CKEN4_Pos        (11U)
25696 #define SAI_PDMCR_CKEN4_Msk        (0x1UL << SAI_PDMCR_CKEN4_Pos)              /*!< 0x00000800 */
25697 #define SAI_PDMCR_CKEN4            SAI_PDMCR_CKEN4_Msk                         /*!<Clock enable of bitstream clock number 4            */
25698 
25699 /******************  Bit definition for SAI_PDMDLY register  ******************/
25700 #define SAI_PDMDLY_DLYM1L_Pos      (0U)
25701 #define SAI_PDMDLY_DLYM1L_Msk      (0x7UL << SAI_PDMDLY_DLYM1L_Pos)            /*!< 0x00000007 */
25702 #define SAI_PDMDLY_DLYM1L          SAI_PDMDLY_DLYM1L_Msk                       /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */
25703 #define SAI_PDMDLY_DLYM1L_0        (0x1U << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000001 */
25704 #define SAI_PDMDLY_DLYM1L_1        (0x2U << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000002 */
25705 #define SAI_PDMDLY_DLYM1L_2        (0x4U << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000004 */
25706 
25707 #define SAI_PDMDLY_DLYM1R_Pos      (4U)
25708 #define SAI_PDMDLY_DLYM1R_Msk      (0x7UL << SAI_PDMDLY_DLYM1R_Pos)            /*!< 0x00000070 */
25709 #define SAI_PDMDLY_DLYM1R          SAI_PDMDLY_DLYM1R_Msk                       /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */
25710 #define SAI_PDMDLY_DLYM1R_0        (0x1U << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000010 */
25711 #define SAI_PDMDLY_DLYM1R_1        (0x2U << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000020 */
25712 #define SAI_PDMDLY_DLYM1R_2        (0x4U << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000040 */
25713 
25714 #define SAI_PDMDLY_DLYM2L_Pos      (8U)
25715 #define SAI_PDMDLY_DLYM2L_Msk      (0x7UL << SAI_PDMDLY_DLYM2L_Pos)            /*!< 0x00000700 */
25716 #define SAI_PDMDLY_DLYM2L          SAI_PDMDLY_DLYM2L_Msk                       /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */
25717 #define SAI_PDMDLY_DLYM2L_0        (0x1U << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000100 */
25718 #define SAI_PDMDLY_DLYM2L_1        (0x2U << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000200 */
25719 #define SAI_PDMDLY_DLYM2L_2        (0x4U << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000400 */
25720 
25721 #define SAI_PDMDLY_DLYM2R_Pos      (12U)
25722 #define SAI_PDMDLY_DLYM2R_Msk      (0x7UL << SAI_PDMDLY_DLYM2R_Pos)            /*!< 0x00007000 */
25723 #define SAI_PDMDLY_DLYM2R          SAI_PDMDLY_DLYM2R_Msk                       /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2)*/
25724 #define SAI_PDMDLY_DLYM2R_0        (0x1U << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00001000 */
25725 #define SAI_PDMDLY_DLYM2R_1        (0x2U << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00002000 */
25726 #define SAI_PDMDLY_DLYM2R_2        (0x4U << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00004000 */
25727 
25728 #define SAI_PDMDLY_DLYM3L_Pos      (16U)
25729 #define SAI_PDMDLY_DLYM3L_Msk      (0x7UL << SAI_PDMDLY_DLYM3L_Pos)            /*!< 0x00070000 */
25730 #define SAI_PDMDLY_DLYM3L          SAI_PDMDLY_DLYM3L_Msk                       /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3)*/
25731 #define SAI_PDMDLY_DLYM3L_0        (0x1U << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00010000 */
25732 #define SAI_PDMDLY_DLYM3L_1        (0x2U << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00020000 */
25733 #define SAI_PDMDLY_DLYM3L_2        (0x4U << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00040000 */
25734 
25735 #define SAI_PDMDLY_DLYM3R_Pos      (20U)
25736 #define SAI_PDMDLY_DLYM3R_Msk      (0x7UL << SAI_PDMDLY_DLYM3R_Pos)            /*!< 0x00700000 */
25737 #define SAI_PDMDLY_DLYM3R          SAI_PDMDLY_DLYM3R_Msk                       /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3)*/
25738 #define SAI_PDMDLY_DLYM3R_0        (0x1U << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00100000 */
25739 #define SAI_PDMDLY_DLYM3R_1        (0x2U << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00200000 */
25740 #define SAI_PDMDLY_DLYM3R_2        (0x4U << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00400000 */
25741 
25742 #define SAI_PDMDLY_DLYM4L_Pos      (24U)
25743 #define SAI_PDMDLY_DLYM4L_Msk      (0x7UL << SAI_PDMDLY_DLYM4L_Pos)            /*!< 0x07000000 */
25744 #define SAI_PDMDLY_DLYM4L          SAI_PDMDLY_DLYM4L_Msk                       /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4)*/
25745 #define SAI_PDMDLY_DLYM4L_0        (0x1U << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x01000000 */
25746 #define SAI_PDMDLY_DLYM4L_1        (0x2U << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x02000000 */
25747 #define SAI_PDMDLY_DLYM4L_2        (0x4U << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x04000000 */
25748 
25749 #define SAI_PDMDLY_DLYM4R_Pos      (28U)
25750 #define SAI_PDMDLY_DLYM4R_Msk      (0x7UL << SAI_PDMDLY_DLYM4R_Pos)            /*!< 0x70000000 */
25751 #define SAI_PDMDLY_DLYM4R          SAI_PDMDLY_DLYM4R_Msk                       /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4)*/
25752 #define SAI_PDMDLY_DLYM4R_0        (0x1U << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x10000000 */
25753 #define SAI_PDMDLY_DLYM4R_1        (0x2U << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x20000000 */
25754 #define SAI_PDMDLY_DLYM4R_2        (0x4U << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x40000000 */
25755 
25756 /**********************  Bit definition for SAI_HWCFGR register  ***************/
25757 #define SAI_HWCFGR_FIFO_SIZE_Pos      (0U)
25758 #define SAI_HWCFGR_FIFO_SIZE_Msk      (0xFFU << SAI_HWCFGR_FIFO_SIZE_Pos)          /*!< 0x000000FF */
25759 #define SAI_HWCFGR_FIFO_SIZE          SAI_HWCFGR_FIFO_SIZE_Msk                    /*!< FIFO size for SAIA and SAIB */
25760 #define SAI_HWCFGR_SPDIF_PDM_Pos      (8U)
25761 #define SAI_HWCFGR_SPDIF_PDM_Msk      (0xFU << SAI_HWCFGR_SPDIF_PDM_Pos)          /*!< 0x00000F00 */
25762 #define SAI_HWCFGR_SPDIF_PDM          SAI_HWCFGR_SPDIF_PDM_Msk                    /*!< Support of SPDIF-OUT and PDM interfaces */
25763 #define SAI_HWCFGR_OPTION_REGOUT_Pos  (12U)
25764 #define SAI_HWCFGR_OPTION_REGOUT_Msk  (0xFFU << SAI_HWCFGR_OPTION_REGOUT_Pos)     /*!< 0x000FF000 */
25765 #define SAI_HWCFGR_OPTION_REGOUT      SAI_HWCFGR_OPTION_REGOUT_Msk                /*!< Support of SAI_IOR register */
25766 
25767 /**********************  Bit definition for SAI_VERR register  *****************/
25768 #define SAI_VERR_MINREV_Pos      (0U)
25769 #define SAI_VERR_MINREV_Msk      (0xFU << SAI_VERR_MINREV_Pos)               /*!< 0x0000000F */
25770 #define SAI_VERR_MINREV          SAI_VERR_MINREV_Msk                         /*!< Minor Revision number */
25771 #define SAI_VERR_MAJREV_Pos      (4U)
25772 #define SAI_VERR_MAJREV_Msk      (0xFU << SAI_VERR_MAJREV_Pos)               /*!< 0x000000F0 */
25773 #define SAI_VERR_MAJREV          SAI_VERR_MAJREV_Msk                         /*!< Major Revision number */
25774 
25775 /**********************  Bit definition for SAI_IPIDR register  ****************/
25776 #define SAI_IPIDR_IPID_Pos       (0U)
25777 #define SAI_IPIDR_IPID_Msk       (0xFFFFFFFFU << SAI_IPIDR_IPID_Pos)         /*!< 0xFFFFFFFF */
25778 #define SAI_IPIDR_IPID           SAI_IPIDR_IPID_Msk                          /*!< IP Identification */
25779 
25780 /**********************  Bit definition for SAI_SIDR register  *****************/
25781 #define SAI_SIDR_SID_Pos         (0U)
25782 #define SAI_SIDR_SID_Msk         (0xFFFFFFFFU << SAI_SIDR_SID_Pos)           /*!< 0xFFFFFFFF */
25783 #define SAI_SIDR_SID             SAI_SIDR_SID_Msk                            /*!< IP size identification */
25784 
25785 /******************************************************************************/
25786 /*                                                                            */
25787 /*                          LCD Controller (LCD)                              */
25788 /*                                                                            */
25789 /******************************************************************************/
25790 
25791 /*******************  Bit definition for LCD_CR register  *********************/
25792 #define LCD_CR_LCDEN_Pos            (0U)
25793 #define LCD_CR_LCDEN_Msk            (0x1U << LCD_CR_LCDEN_Pos)                 /*!< 0x00000001 */
25794 #define LCD_CR_LCDEN                LCD_CR_LCDEN_Msk                           /*!< LCD Enable Bit */
25795 #define LCD_CR_VSEL_Pos             (1U)
25796 #define LCD_CR_VSEL_Msk             (0x1U << LCD_CR_VSEL_Pos)                  /*!< 0x00000002 */
25797 #define LCD_CR_VSEL                 LCD_CR_VSEL_Msk                            /*!< Voltage source selector Bit */
25798 
25799 #define LCD_CR_DUTY_Pos             (2U)
25800 #define LCD_CR_DUTY_Msk             (0x7U << LCD_CR_DUTY_Pos)                  /*!< 0x0000001C */
25801 #define LCD_CR_DUTY                 LCD_CR_DUTY_Msk                            /*!< DUTY[2:0] bits (Duty selector) */
25802 #define LCD_CR_DUTY_0               (0x1U << LCD_CR_DUTY_Pos)                  /*!< 0x00000004 */
25803 #define LCD_CR_DUTY_1               (0x2U << LCD_CR_DUTY_Pos)                  /*!< 0x00000008 */
25804 #define LCD_CR_DUTY_2               (0x4U << LCD_CR_DUTY_Pos)                  /*!< 0x00000010 */
25805 
25806 #define LCD_CR_BIAS_Pos             (5U)
25807 #define LCD_CR_BIAS_Msk             (0x3U << LCD_CR_BIAS_Pos)                  /*!< 0x00000060 */
25808 #define LCD_CR_BIAS                 LCD_CR_BIAS_Msk                            /*!< BIAS[1:0] bits (Bias selector) */
25809 #define LCD_CR_BIAS_0               (0x1U << LCD_CR_BIAS_Pos)                  /*!< 0x00000020 */
25810 #define LCD_CR_BIAS_1               (0x2U << LCD_CR_BIAS_Pos)                  /*!< 0x00000040 */
25811 
25812 #define LCD_CR_MUX_SEG_Pos          (7U)
25813 #define LCD_CR_MUX_SEG_Msk          (0x1U << LCD_CR_MUX_SEG_Pos)               /*!< 0x00000080 */
25814 #define LCD_CR_MUX_SEG              LCD_CR_MUX_SEG_Msk                         /*!< Mux Segment Enable Bit */
25815 #define LCD_CR_BUFEN_Pos            (8U)
25816 #define LCD_CR_BUFEN_Msk            (0x1U << LCD_CR_BUFEN_Pos)                 /*!< 0x00000100 */
25817 #define LCD_CR_BUFEN                LCD_CR_BUFEN_Msk                           /*!< Voltage output buffer enable */
25818 /*******************  Bit definition for LCD_FCR register  ********************/
25819 #define LCD_FCR_HD_Pos              (0U)
25820 #define LCD_FCR_HD_Msk              (0x1U << LCD_FCR_HD_Pos)                   /*!< 0x00000001 */
25821 #define LCD_FCR_HD                  LCD_FCR_HD_Msk                             /*!< High Drive Enable Bit */
25822 #define LCD_FCR_SOFIE_Pos           (1U)
25823 #define LCD_FCR_SOFIE_Msk           (0x1U << LCD_FCR_SOFIE_Pos)                /*!< 0x00000002 */
25824 #define LCD_FCR_SOFIE               LCD_FCR_SOFIE_Msk                          /*!< Start of Frame Interrupt Enable Bit */
25825 #define LCD_FCR_UDDIE_Pos           (3U)
25826 #define LCD_FCR_UDDIE_Msk           (0x1U << LCD_FCR_UDDIE_Pos)                /*!< 0x00000008 */
25827 #define LCD_FCR_UDDIE               LCD_FCR_UDDIE_Msk                          /*!< Update Display Done Interrupt Enable Bit */
25828 
25829 #define LCD_FCR_PON_Pos             (4U)
25830 #define LCD_FCR_PON_Msk             (0x7U << LCD_FCR_PON_Pos)                  /*!< 0x00000070 */
25831 #define LCD_FCR_PON                 LCD_FCR_PON_Msk                            /*!< PON[2:0] bits (Puls ON Duration) */
25832 #define LCD_FCR_PON_0               (0x1U << LCD_FCR_PON_Pos)                  /*!< 0x00000010 */
25833 #define LCD_FCR_PON_1               (0x2U << LCD_FCR_PON_Pos)                  /*!< 0x00000020 */
25834 #define LCD_FCR_PON_2               (0x4U << LCD_FCR_PON_Pos)                  /*!< 0x00000040 */
25835 
25836 #define LCD_FCR_DEAD_Pos            (7U)
25837 #define LCD_FCR_DEAD_Msk            (0x7U << LCD_FCR_DEAD_Pos)                 /*!< 0x00000380 */
25838 #define LCD_FCR_DEAD                LCD_FCR_DEAD_Msk                           /*!< DEAD[2:0] bits (DEAD Time) */
25839 #define LCD_FCR_DEAD_0              (0x1U << LCD_FCR_DEAD_Pos)                 /*!< 0x00000080 */
25840 #define LCD_FCR_DEAD_1              (0x2U << LCD_FCR_DEAD_Pos)                 /*!< 0x00000100 */
25841 #define LCD_FCR_DEAD_2              (0x4U << LCD_FCR_DEAD_Pos)                 /*!< 0x00000200 */
25842 
25843 #define LCD_FCR_CC_Pos              (10U)
25844 #define LCD_FCR_CC_Msk              (0x7U << LCD_FCR_CC_Pos)                   /*!< 0x00001C00 */
25845 #define LCD_FCR_CC                  LCD_FCR_CC_Msk                             /*!< CC[2:0] bits (Contrast Control) */
25846 #define LCD_FCR_CC_0                (0x1U << LCD_FCR_CC_Pos)                   /*!< 0x00000400 */
25847 #define LCD_FCR_CC_1                (0x2U << LCD_FCR_CC_Pos)                   /*!< 0x00000800 */
25848 #define LCD_FCR_CC_2                (0x4U << LCD_FCR_CC_Pos)                   /*!< 0x00001000 */
25849 
25850 #define LCD_FCR_BLINKF_Pos          (13U)
25851 #define LCD_FCR_BLINKF_Msk          (0x7U << LCD_FCR_BLINKF_Pos)               /*!< 0x0000E000 */
25852 #define LCD_FCR_BLINKF              LCD_FCR_BLINKF_Msk                         /*!< BLINKF[2:0] bits (Blink Frequency) */
25853 #define LCD_FCR_BLINKF_0            (0x1U << LCD_FCR_BLINKF_Pos)               /*!< 0x00002000 */
25854 #define LCD_FCR_BLINKF_1            (0x2U << LCD_FCR_BLINKF_Pos)               /*!< 0x00004000 */
25855 #define LCD_FCR_BLINKF_2            (0x4U << LCD_FCR_BLINKF_Pos)               /*!< 0x00008000 */
25856 
25857 #define LCD_FCR_BLINK_Pos           (16U)
25858 #define LCD_FCR_BLINK_Msk           (0x3U << LCD_FCR_BLINK_Pos)                /*!< 0x00030000 */
25859 #define LCD_FCR_BLINK               LCD_FCR_BLINK_Msk                          /*!< BLINK[1:0] bits (Blink Enable) */
25860 #define LCD_FCR_BLINK_0             (0x1U << LCD_FCR_BLINK_Pos)                /*!< 0x00010000 */
25861 #define LCD_FCR_BLINK_1             (0x2U << LCD_FCR_BLINK_Pos)                /*!< 0x00020000 */
25862 
25863 #define LCD_FCR_DIV_Pos             (18U)
25864 #define LCD_FCR_DIV_Msk             (0xFU << LCD_FCR_DIV_Pos)                  /*!< 0x003C0000 */
25865 #define LCD_FCR_DIV                 LCD_FCR_DIV_Msk                            /*!< DIV[3:0] bits (Divider) */
25866 #define LCD_FCR_PS_Pos              (22U)
25867 #define LCD_FCR_PS_Msk              (0xFU << LCD_FCR_PS_Pos)                   /*!< 0x03C00000 */
25868 #define LCD_FCR_PS                  LCD_FCR_PS_Msk                             /*!< PS[3:0] bits (Prescaler) */
25869 
25870 /*******************  Bit definition for LCD_SR register  *********************/
25871 #define LCD_SR_ENS_Pos              (0U)
25872 #define LCD_SR_ENS_Msk              (0x1U << LCD_SR_ENS_Pos)                   /*!< 0x00000001 */
25873 #define LCD_SR_ENS                  LCD_SR_ENS_Msk                             /*!< LCD Enabled Bit */
25874 #define LCD_SR_SOF_Pos              (1U)
25875 #define LCD_SR_SOF_Msk              (0x1U << LCD_SR_SOF_Pos)                   /*!< 0x00000002 */
25876 #define LCD_SR_SOF                  LCD_SR_SOF_Msk                             /*!< Start Of Frame Flag Bit */
25877 #define LCD_SR_UDR_Pos              (2U)
25878 #define LCD_SR_UDR_Msk              (0x1U << LCD_SR_UDR_Pos)                   /*!< 0x00000004 */
25879 #define LCD_SR_UDR                  LCD_SR_UDR_Msk                             /*!< Update Display Request Bit */
25880 #define LCD_SR_UDD_Pos              (3U)
25881 #define LCD_SR_UDD_Msk              (0x1U << LCD_SR_UDD_Pos)                   /*!< 0x00000008 */
25882 #define LCD_SR_UDD                  LCD_SR_UDD_Msk                             /*!< Update Display Done Flag Bit */
25883 #define LCD_SR_RDY_Pos              (4U)
25884 #define LCD_SR_RDY_Msk              (0x1U << LCD_SR_RDY_Pos)                   /*!< 0x00000010 */
25885 #define LCD_SR_RDY                  LCD_SR_RDY_Msk                             /*!< Ready Flag Bit */
25886 #define LCD_SR_FCRSR_Pos            (5U)
25887 #define LCD_SR_FCRSR_Msk            (0x1U << LCD_SR_FCRSR_Pos)                 /*!< 0x00000020 */
25888 #define LCD_SR_FCRSR                LCD_SR_FCRSR_Msk                           /*!< LCD FCR Register Synchronization Flag Bit */
25889 
25890 /*******************  Bit definition for LCD_CLR register  ********************/
25891 #define LCD_CLR_SOFC_Pos            (1U)
25892 #define LCD_CLR_SOFC_Msk            (0x1U << LCD_CLR_SOFC_Pos)                 /*!< 0x00000002 */
25893 #define LCD_CLR_SOFC                LCD_CLR_SOFC_Msk                           /*!< Start Of Frame Flag Clear Bit */
25894 #define LCD_CLR_UDDC_Pos            (3U)
25895 #define LCD_CLR_UDDC_Msk            (0x1U << LCD_CLR_UDDC_Pos)                 /*!< 0x00000008 */
25896 #define LCD_CLR_UDDC                LCD_CLR_UDDC_Msk                           /*!< Update Display Done Flag Clear Bit */
25897 
25898 /*******************  Bit definition for LCD_RAM register  ********************/
25899 #define LCD_RAM_SEGMENT_DATA_Pos    (0U)
25900 #define LCD_RAM_SEGMENT_DATA_Msk    (0xFFFFFFFFU << LCD_RAM_SEGMENT_DATA_Pos)  /*!< 0xFFFFFFFF */
25901 #define LCD_RAM_SEGMENT_DATA        LCD_RAM_SEGMENT_DATA_Msk                   /*!< Segment Data Bits */
25902 
25903 /******************************************************************************/
25904 /*                                                                            */
25905 /*                           SDMMC Interface                                  */
25906 /*                                                                            */
25907 /******************************************************************************/
25908 /******************  Bit definition for SDMMC_POWER register  ******************/
25909 // #define SDMMC_POWER_PWRCTRL_Pos         (0U)
25910 // #define SDMMC_POWER_PWRCTRL_Msk         (0x3U << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000003 */
25911 // #define SDMMC_POWER_PWRCTRL             SDMMC_POWER_PWRCTRL_Msk                /*!<PWRCTRL[1:0] bits (Power supply control bits) */
25912 // #define SDMMC_POWER_PWRCTRL_0           (0x1U << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000001 */
25913 // #define SDMMC_POWER_PWRCTRL_1           (0x2U << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000002 */
25914 // #define SDMMC_POWER_VSWITCH_Pos         (2U)
25915 // #define SDMMC_POWER_VSWITCH_Msk         (0x1U << SDMMC_POWER_VSWITCH_Pos)      /*!< 0x00000004 */
25916 // #define SDMMC_POWER_VSWITCH             SDMMC_POWER_VSWITCH_Msk                /*!<Voltage switch sequence start */
25917 // #define SDMMC_POWER_VSWITCHEN_Pos       (3U)
25918 // #define SDMMC_POWER_VSWITCHEN_Msk       (0x1U << SDMMC_POWER_VSWITCHEN_Pos)    /*!< 0x00000008 */
25919 // #define SDMMC_POWER_VSWITCHEN           SDMMC_POWER_VSWITCHEN_Msk              /*!<Voltage switch procedure enable */
25920 // #define SDMMC_POWER_DIRPOL_Pos          (4U)
25921 // #define SDMMC_POWER_DIRPOL_Msk          (0x1U << SDMMC_POWER_DIRPOL_Pos)       /*!< 0x00000010 */
25922 // #define SDMMC_POWER_DIRPOL              SDMMC_POWER_DIRPOL_Msk                 /*!<Data and Command direction signals polarity selection */
25923 
25924 // /******************  Bit definition for SDMMC_CLKCR register  ******************/
25925 // #define SDMMC_CLKCR_CLKDIV_Pos          (0U)
25926 // #define SDMMC_CLKCR_CLKDIV_Msk          (0x3FFU << SDMMC_CLKCR_CLKDIV_Pos)     /*!< 0x000003FF */
25927 // #define SDMMC_CLKCR_CLKDIV              SDMMC_CLKCR_CLKDIV_Msk                 /*!<Clock divide factor             */
25928 // #define SDMMC_CLKCR_PWRSAV_Pos          (12U)
25929 // #define SDMMC_CLKCR_PWRSAV_Msk          (0x1U << SDMMC_CLKCR_PWRSAV_Pos)       /*!< 0x00001000 */
25930 // #define SDMMC_CLKCR_PWRSAV              SDMMC_CLKCR_PWRSAV_Msk                 /*!<Power saving configuration bit  */
25931 
25932 // #define SDMMC_CLKCR_WIDBUS_Pos          (14U)
25933 // #define SDMMC_CLKCR_WIDBUS_Msk          (0x3U << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x0000C000 */
25934 // #define SDMMC_CLKCR_WIDBUS              SDMMC_CLKCR_WIDBUS_Msk                 /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
25935 // #define SDMMC_CLKCR_WIDBUS_0            (0x1U << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x00004000 */
25936 // #define SDMMC_CLKCR_WIDBUS_1            (0x2U << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x00008000 */
25937 
25938 // #define SDMMC_CLKCR_NEGEDGE_Pos         (16U)
25939 // #define SDMMC_CLKCR_NEGEDGE_Msk         (0x1U << SDMMC_CLKCR_NEGEDGE_Pos)      /*!< 0x00010000 */
25940 // #define SDMMC_CLKCR_NEGEDGE             SDMMC_CLKCR_NEGEDGE_Msk                /*!<SDMMC_CK dephasing selection bit */
25941 // #define SDMMC_CLKCR_HWFC_EN_Pos         (17U)
25942 // #define SDMMC_CLKCR_HWFC_EN_Msk         (0x1U << SDMMC_CLKCR_HWFC_EN_Pos)      /*!< 0x00020000 */
25943 // #define SDMMC_CLKCR_HWFC_EN             SDMMC_CLKCR_HWFC_EN_Msk                /*!<HW Flow Control enable           */
25944 // #define SDMMC_CLKCR_DDR_Pos             (18U)
25945 // #define SDMMC_CLKCR_DDR_Msk             (0x1U << SDMMC_CLKCR_DDR_Pos)          /*!< 0x00040000 */
25946 // #define SDMMC_CLKCR_DDR                 SDMMC_CLKCR_DDR_Msk                    /*!<Data rate signaling selection    */
25947 // #define SDMMC_CLKCR_BUSSPEED_Pos        (19U)
25948 // #define SDMMC_CLKCR_BUSSPEED_Msk        (0x1U << SDMMC_CLKCR_BUSSPEED_Pos)     /*!< 0x00080000 */
25949 // #define SDMMC_CLKCR_BUSSPEED            SDMMC_CLKCR_BUSSPEED_Msk               /*!<Bus speed mode selection         */
25950 // #define SDMMC_CLKCR_SELCLKRX_Pos        (20U)
25951 // #define SDMMC_CLKCR_SELCLKRX_Msk        (0x3U << SDMMC_CLKCR_SELCLKRX_Pos)     /*!< 0x00300000 */
25952 // #define SDMMC_CLKCR_SELCLKRX            SDMMC_CLKCR_SELCLKRX_Msk               /*!<SELCLKRX[1:0] bits (Receive clock selection) */
25953 // #define SDMMC_CLKCR_SELCLKRX_0          (0x1U << SDMMC_CLKCR_SELCLKRX_Pos)     /*!< 0x00100000 */
25954 // #define SDMMC_CLKCR_SELCLKRX_1          (0x2U << SDMMC_CLKCR_SELCLKRX_Pos)     /*!< 0x00200000 */
25955 
25956 // /*******************  Bit definition for SDMMC_ARG register  *******************/
25957 // #define SDMMC_ARG_CMDARG_Pos            (0U)
25958 // #define SDMMC_ARG_CMDARG_Msk            (0xFFFFFFFFU << SDMMC_ARG_CMDARG_Pos)  /*!< 0xFFFFFFFF */
25959 // #define SDMMC_ARG_CMDARG                SDMMC_ARG_CMDARG_Msk                   /*!<Command argument */
25960 
25961 // /*******************  Bit definition for SDMMC_CMD register  *******************/
25962 // #define SDMMC_CMD_CMDINDEX_Pos          (0U)
25963 // #define SDMMC_CMD_CMDINDEX_Msk          (0x3FU << SDMMC_CMD_CMDINDEX_Pos)      /*!< 0x0000003F */
25964 // #define SDMMC_CMD_CMDINDEX              SDMMC_CMD_CMDINDEX_Msk                 /*!<Command Index                               */
25965 // #define SDMMC_CMD_CMDTRANS_Pos          (6U)
25966 // #define SDMMC_CMD_CMDTRANS_Msk          (0x1U << SDMMC_CMD_CMDTRANS_Pos)       /*!< 0x00000040 */
25967 // #define SDMMC_CMD_CMDTRANS              SDMMC_CMD_CMDTRANS_Msk                 /*!<CPSM Treats command as a Data Transfer      */
25968 // #define SDMMC_CMD_CMDSTOP_Pos           (7U)
25969 // #define SDMMC_CMD_CMDSTOP_Msk           (0x1U << SDMMC_CMD_CMDSTOP_Pos)        /*!< 0x00000080 */
25970 // #define SDMMC_CMD_CMDSTOP               SDMMC_CMD_CMDSTOP_Msk                  /*!<CPSM Treats command as a Stop               */
25971 
25972 // #define SDMMC_CMD_WAITRESP_Pos          (8U)
25973 // #define SDMMC_CMD_WAITRESP_Msk          (0x3U << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x00000300 */
25974 // #define SDMMC_CMD_WAITRESP              SDMMC_CMD_WAITRESP_Msk                 /*!<WAITRESP[1:0] bits (Wait for response bits) */
25975 // #define SDMMC_CMD_WAITRESP_0            (0x1U << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x00000100 */
25976 // #define SDMMC_CMD_WAITRESP_1            (0x2U << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x00000200 */
25977 
25978 // #define SDMMC_CMD_WAITINT_Pos           (10U)
25979 // #define SDMMC_CMD_WAITINT_Msk           (0x1U << SDMMC_CMD_WAITINT_Pos)        /*!< 0x00000400 */
25980 // #define SDMMC_CMD_WAITINT               SDMMC_CMD_WAITINT_Msk                  /*!<CPSM Waits for Interrupt Request                               */
25981 // #define SDMMC_CMD_WAITPEND_Pos          (11U)
25982 // #define SDMMC_CMD_WAITPEND_Msk          (0x1U << SDMMC_CMD_WAITPEND_Pos)       /*!< 0x00000800 */
25983 // #define SDMMC_CMD_WAITPEND              SDMMC_CMD_WAITPEND_Msk                 /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
25984 // #define SDMMC_CMD_CPSMEN_Pos            (12U)
25985 // #define SDMMC_CMD_CPSMEN_Msk            (0x1U << SDMMC_CMD_CPSMEN_Pos)         /*!< 0x00001000 */
25986 // #define SDMMC_CMD_CPSMEN                SDMMC_CMD_CPSMEN_Msk                   /*!<Command path state machine (CPSM) Enable bit                   */
25987 // #define SDMMC_CMD_DTHOLD_Pos            (13U)
25988 // #define SDMMC_CMD_DTHOLD_Msk            (0x1U << SDMMC_CMD_DTHOLD_Pos)         /*!< 0x00002000 */
25989 // #define SDMMC_CMD_DTHOLD                SDMMC_CMD_DTHOLD_Msk                   /*!<Hold new data block transmission and reception in the DPSM     */
25990 // #define SDMMC_CMD_BOOTMODE_Pos          (14U)
25991 // #define SDMMC_CMD_BOOTMODE_Msk          (0x1U << SDMMC_CMD_BOOTMODE_Pos)       /*!< 0x00004000 */
25992 // #define SDMMC_CMD_BOOTMODE              SDMMC_CMD_BOOTMODE_Msk                 /*!<Boot mode                                                      */
25993 // #define SDMMC_CMD_BOOTEN_Pos            (15U)
25994 // #define SDMMC_CMD_BOOTEN_Msk            (0x1U << SDMMC_CMD_BOOTEN_Pos)         /*!< 0x00008000 */
25995 // #define SDMMC_CMD_BOOTEN                SDMMC_CMD_BOOTEN_Msk                   /*!<Enable Boot mode procedure                                     */
25996 // #define SDMMC_CMD_CMDSUSPEND_Pos        (16U)
25997 // #define SDMMC_CMD_CMDSUSPEND_Msk        (0x1U << SDMMC_CMD_CMDSUSPEND_Pos)    /*!< 0x00010000 */
25998 // #define SDMMC_CMD_CMDSUSPEND            SDMMC_CMD_CMDSUSPEND_Msk              /*!<CPSM Treats command as a Suspend or Resume command             */
25999 
26000 // /*****************  Bit definition for SDMMC_RESPCMD register  *****************/
26001 // #define SDMMC_RESPCMD_RESPCMD_Pos       (0U)
26002 // #define SDMMC_RESPCMD_RESPCMD_Msk       (0x3FU << SDMMC_RESPCMD_RESPCMD_Pos)   /*!< 0x0000003F */
26003 // #define SDMMC_RESPCMD_RESPCMD           SDMMC_RESPCMD_RESPCMD_Msk              /*!<Response command index */
26004 
26005 // /******************  Bit definition for SDMMC_RESP0 register  ******************/
26006 // #define SDMMC_RESP0_CARDSTATUS0_Pos     (0U)
26007 // #define SDMMC_RESP0_CARDSTATUS0_Msk     (0xFFFFFFFFU << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
26008 // #define SDMMC_RESP0_CARDSTATUS0         SDMMC_RESP0_CARDSTATUS0_Msk            /*!<Card Status */
26009 
26010 // /******************  Bit definition for SDMMC_RESP1 register  ******************/
26011 // #define SDMMC_RESP1_CARDSTATUS1_Pos     (0U)
26012 // #define SDMMC_RESP1_CARDSTATUS1_Msk     (0xFFFFFFFFU << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
26013 // #define SDMMC_RESP1_CARDSTATUS1         SDMMC_RESP1_CARDSTATUS1_Msk            /*!<Card Status */
26014 
26015 // /******************  Bit definition for SDMMC_RESP2 register  ******************/
26016 // #define SDMMC_RESP2_CARDSTATUS2_Pos     (0U)
26017 // #define SDMMC_RESP2_CARDSTATUS2_Msk     (0xFFFFFFFFU << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
26018 // #define SDMMC_RESP2_CARDSTATUS2         SDMMC_RESP2_CARDSTATUS2_Msk            /*!<Card Status */
26019 
26020 // /******************  Bit definition for SDMMC_RESP3 register  ******************/
26021 // #define SDMMC_RESP3_CARDSTATUS3_Pos     (0U)
26022 // #define SDMMC_RESP3_CARDSTATUS3_Msk     (0xFFFFFFFFU << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
26023 // #define SDMMC_RESP3_CARDSTATUS3         SDMMC_RESP3_CARDSTATUS3_Msk            /*!<Card Status */
26024 
26025 // /******************  Bit definition for SDMMC_RESP4 register  ******************/
26026 // #define SDMMC_RESP4_CARDSTATUS4_Pos     (0U)
26027 // #define SDMMC_RESP4_CARDSTATUS4_Msk     (0xFFFFFFFFU << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
26028 // #define SDMMC_RESP4_CARDSTATUS4         SDMMC_RESP4_CARDSTATUS4_Msk            /*!<Card Status */
26029 
26030 // /******************  Bit definition for SDMMC_DTIMER register  *****************/
26031 // #define SDMMC_DTIMER_DATATIME_Pos       (0U)
26032 // #define SDMMC_DTIMER_DATATIME_Msk       (0xFFFFFFFFU << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
26033 // #define SDMMC_DTIMER_DATATIME           SDMMC_DTIMER_DATATIME_Msk              /*!<Data timeout period. */
26034 
26035 // /******************  Bit definition for SDMMC_DLEN register  *******************/
26036 // #define SDMMC_DLEN_DATALENGTH_Pos       (0U)
26037 // #define SDMMC_DLEN_DATALENGTH_Msk       (0x1FFFFFFU << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
26038 // #define SDMMC_DLEN_DATALENGTH           SDMMC_DLEN_DATALENGTH_Msk              /*!<Data length value    */
26039 
26040 // /******************  Bit definition for SDMMC_DCTRL register  ******************/
26041 // #define SDMMC_DCTRL_DTEN_Pos            (0U)
26042 // #define SDMMC_DCTRL_DTEN_Msk            (0x1U << SDMMC_DCTRL_DTEN_Pos)         /*!< 0x00000001 */
26043 // #define SDMMC_DCTRL_DTEN                SDMMC_DCTRL_DTEN_Msk                   /*!<Data transfer enabled bit                */
26044 // #define SDMMC_DCTRL_DTDIR_Pos           (1U)
26045 // #define SDMMC_DCTRL_DTDIR_Msk           (0x1U << SDMMC_DCTRL_DTDIR_Pos)        /*!< 0x00000002 */
26046 // #define SDMMC_DCTRL_DTDIR               SDMMC_DCTRL_DTDIR_Msk                  /*!<Data transfer direction selection        */
26047 // #define SDMMC_DCTRL_DTMODE_Pos          (2U)
26048 // #define SDMMC_DCTRL_DTMODE_Msk          (0x3U << SDMMC_DCTRL_DTMODE_Pos)       /*!< 0x0000000C */
26049 // #define SDMMC_DCTRL_DTMODE              SDMMC_DCTRL_DTMODE_Msk                 /*!<DTMODE[1:0] Data transfer mode selection */
26050 // #define SDMMC_DCTRL_DTMODE_0            (0x1U << SDMMC_DCTRL_DTMODE_Pos)       /*!< 0x0004 */
26051 // #define SDMMC_DCTRL_DTMODE_1            (0x2U << SDMMC_DCTRL_DTMODE_Pos)       /*!< 0x0008 */
26052 
26053 // #define SDMMC_DCTRL_DBLOCKSIZE_Pos      (4U)
26054 // #define SDMMC_DCTRL_DBLOCKSIZE_Msk      (0xFU << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x000000F0 */
26055 // #define SDMMC_DCTRL_DBLOCKSIZE          SDMMC_DCTRL_DBLOCKSIZE_Msk             /*!<DBLOCKSIZE[3:0] bits (Data block size) */
26056 // #define SDMMC_DCTRL_DBLOCKSIZE_0        (0x1U << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x0010 */
26057 // #define SDMMC_DCTRL_DBLOCKSIZE_1        (0x2U << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x0020 */
26058 // #define SDMMC_DCTRL_DBLOCKSIZE_2        (0x4U << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x0040 */
26059 // #define SDMMC_DCTRL_DBLOCKSIZE_3        (0x8U << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x0080 */
26060 
26061 // #define SDMMC_DCTRL_RWSTART_Pos         (8U)
26062 // #define SDMMC_DCTRL_RWSTART_Msk         (0x1U << SDMMC_DCTRL_RWSTART_Pos)      /*!< 0x00000100 */
26063 // #define SDMMC_DCTRL_RWSTART             SDMMC_DCTRL_RWSTART_Msk                /*!<Read wait start                                 */
26064 // #define SDMMC_DCTRL_RWSTOP_Pos          (9U)
26065 // #define SDMMC_DCTRL_RWSTOP_Msk          (0x1U << SDMMC_DCTRL_RWSTOP_Pos)       /*!< 0x00000200 */
26066 // #define SDMMC_DCTRL_RWSTOP              SDMMC_DCTRL_RWSTOP_Msk                 /*!<Read wait stop                                  */
26067 // #define SDMMC_DCTRL_RWMOD_Pos           (10U)
26068 // #define SDMMC_DCTRL_RWMOD_Msk           (0x1U << SDMMC_DCTRL_RWMOD_Pos)        /*!< 0x00000400 */
26069 // #define SDMMC_DCTRL_RWMOD               SDMMC_DCTRL_RWMOD_Msk                  /*!<Read wait mode                                  */
26070 // #define SDMMC_DCTRL_SDIOEN_Pos          (11U)
26071 // #define SDMMC_DCTRL_SDIOEN_Msk          (0x1U << SDMMC_DCTRL_SDIOEN_Pos)       /*!< 0x00000800 */
26072 // #define SDMMC_DCTRL_SDIOEN              SDMMC_DCTRL_SDIOEN_Msk                 /*!<SD I/O enable functions                         */
26073 // #define SDMMC_DCTRL_BOOTACKEN_Pos       (12U)
26074 // #define SDMMC_DCTRL_BOOTACKEN_Msk       (0x1U << SDMMC_DCTRL_BOOTACKEN_Pos)    /*!< 0x00001000 */
26075 // #define SDMMC_DCTRL_BOOTACKEN           SDMMC_DCTRL_BOOTACKEN_Msk              /*!<Enable the reception of the Boot Acknowledgment */
26076 // #define SDMMC_DCTRL_FIFORST_Pos         (13U)
26077 // #define SDMMC_DCTRL_FIFORST_Msk         (0x1U << SDMMC_DCTRL_FIFORST_Pos)      /*!< 0x00002000 */
26078 // #define SDMMC_DCTRL_FIFORST             SDMMC_DCTRL_FIFORST_Msk                /*!<FIFO reset                                      */
26079 
26080 // /******************  Bit definition for SDMMC_DCOUNT register  *****************/
26081 // #define SDMMC_DCOUNT_DATACOUNT_Pos      (0U)
26082 // #define SDMMC_DCOUNT_DATACOUNT_Msk      (0x1FFFFFFU << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
26083 // #define SDMMC_DCOUNT_DATACOUNT          SDMMC_DCOUNT_DATACOUNT_Msk             /*!<Data count value */
26084 
26085 // /******************  Bit definition for SDMMC_STA register  ********************/
26086 // #define SDMMC_STA_CCRCFAIL_Pos          (0U)
26087 // #define SDMMC_STA_CCRCFAIL_Msk          (0x1U << SDMMC_STA_CCRCFAIL_Pos)       /*!< 0x00000001 */
26088 // #define SDMMC_STA_CCRCFAIL              SDMMC_STA_CCRCFAIL_Msk                 /*!<Command response received (CRC check failed)  */
26089 // #define SDMMC_STA_DCRCFAIL_Pos          (1U)
26090 // #define SDMMC_STA_DCRCFAIL_Msk          (0x1U << SDMMC_STA_DCRCFAIL_Pos)       /*!< 0x00000002 */
26091 // #define SDMMC_STA_DCRCFAIL              SDMMC_STA_DCRCFAIL_Msk                 /*!<Data block sent/received (CRC check failed)   */
26092 // #define SDMMC_STA_CTIMEOUT_Pos          (2U)
26093 // #define SDMMC_STA_CTIMEOUT_Msk          (0x1U << SDMMC_STA_CTIMEOUT_Pos)       /*!< 0x00000004 */
26094 // #define SDMMC_STA_CTIMEOUT              SDMMC_STA_CTIMEOUT_Msk                 /*!<Command response timeout                      */
26095 // #define SDMMC_STA_DTIMEOUT_Pos          (3U)
26096 // #define SDMMC_STA_DTIMEOUT_Msk          (0x1U << SDMMC_STA_DTIMEOUT_Pos)       /*!< 0x00000008 */
26097 // #define SDMMC_STA_DTIMEOUT              SDMMC_STA_DTIMEOUT_Msk                 /*!<Data timeout                                  */
26098 // #define SDMMC_STA_TXUNDERR_Pos          (4U)
26099 // #define SDMMC_STA_TXUNDERR_Msk          (0x1U << SDMMC_STA_TXUNDERR_Pos)       /*!< 0x00000010 */
26100 // #define SDMMC_STA_TXUNDERR              SDMMC_STA_TXUNDERR_Msk                 /*!<Transmit FIFO underrun error                  */
26101 // #define SDMMC_STA_RXOVERR_Pos           (5U)
26102 // #define SDMMC_STA_RXOVERR_Msk           (0x1U << SDMMC_STA_RXOVERR_Pos)        /*!< 0x00000020 */
26103 // #define SDMMC_STA_RXOVERR               SDMMC_STA_RXOVERR_Msk                  /*!<Received FIFO overrun error                   */
26104 // #define SDMMC_STA_CMDREND_Pos           (6U)
26105 // #define SDMMC_STA_CMDREND_Msk           (0x1U << SDMMC_STA_CMDREND_Pos)        /*!< 0x00000040 */
26106 // #define SDMMC_STA_CMDREND               SDMMC_STA_CMDREND_Msk                  /*!<Command response received (CRC check passed)  */
26107 // #define SDMMC_STA_CMDSENT_Pos           (7U)
26108 // #define SDMMC_STA_CMDSENT_Msk           (0x1U << SDMMC_STA_CMDSENT_Pos)        /*!< 0x00000080 */
26109 // #define SDMMC_STA_CMDSENT               SDMMC_STA_CMDSENT_Msk                  /*!<Command sent (no response required)           */
26110 // #define SDMMC_STA_DATAEND_Pos           (8U)
26111 // #define SDMMC_STA_DATAEND_Msk           (0x1U << SDMMC_STA_DATAEND_Pos)        /*!< 0x00000100 */
26112 // #define SDMMC_STA_DATAEND               SDMMC_STA_DATAEND_Msk                  /*!<Data end (data counter, SDIDCOUNT, is zero)   */
26113 // #define SDMMC_STA_DHOLD_Pos             (9U)
26114 // #define SDMMC_STA_DHOLD_Msk             (0x1U << SDMMC_STA_DHOLD_Pos)          /*!< 0x00000200 */
26115 // #define SDMMC_STA_DHOLD                 SDMMC_STA_DHOLD_Msk                    /*!<Data transfer Hold                                                      */
26116 // #define SDMMC_STA_DBCKEND_Pos           (10U)
26117 // #define SDMMC_STA_DBCKEND_Msk           (0x1U << SDMMC_STA_DBCKEND_Pos)        /*!< 0x00000400 */
26118 // #define SDMMC_STA_DBCKEND               SDMMC_STA_DBCKEND_Msk                  /*!<Data block sent/received (CRC check passed)   */
26119 // #define SDMMC_STA_DABORT_Pos            (11U)
26120 // #define SDMMC_STA_DABORT_Msk            (0x1U << SDMMC_STA_DABORT_Pos)         /*!< 0x00000800 */
26121 // #define SDMMC_STA_DABORT                SDMMC_STA_DABORT_Msk                   /*!<Data transfer aborted by CMD12                                          */
26122 // #define SDMMC_STA_CPSMACT_Pos           (12U)
26123 // #define SDMMC_STA_CPSMACT_Msk           (0x1U << SDMMC_STA_CPSMACT_Pos)        /*!< 0x00001000 */
26124 // #define SDMMC_STA_CPSMACT               SDMMC_STA_CPSMACT_Msk                  /*!<Data path state machine active                                          */
26125 // #define SDMMC_STA_DPSMACT_Pos           (13U)
26126 // #define SDMMC_STA_DPSMACT_Msk           (0x1U << SDMMC_STA_DPSMACT_Pos)        /*!< 0x00002000 */
26127 // #define SDMMC_STA_DPSMACT               SDMMC_STA_DPSMACT_Msk                  /*!<Command path state machine active                                       */
26128 // #define SDMMC_STA_TXFIFOHE_Pos          (14U)
26129 // #define SDMMC_STA_TXFIFOHE_Msk          (0x1U << SDMMC_STA_TXFIFOHE_Pos)       /*!< 0x00004000 */
26130 // #define SDMMC_STA_TXFIFOHE              SDMMC_STA_TXFIFOHE_Msk                 /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
26131 // #define SDMMC_STA_RXFIFOHF_Pos          (15U)
26132 // #define SDMMC_STA_RXFIFOHF_Msk          (0x1U << SDMMC_STA_RXFIFOHF_Pos)       /*!< 0x00008000 */
26133 // #define SDMMC_STA_RXFIFOHF              SDMMC_STA_RXFIFOHF_Msk                 /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
26134 // #define SDMMC_STA_TXFIFOF_Pos           (16U)
26135 // #define SDMMC_STA_TXFIFOF_Msk           (0x1U << SDMMC_STA_TXFIFOF_Pos)        /*!< 0x00010000 */
26136 // #define SDMMC_STA_TXFIFOF               SDMMC_STA_TXFIFOF_Msk                  /*!<Transmit FIFO full                            */
26137 // #define SDMMC_STA_RXFIFOF_Pos           (17U)
26138 // #define SDMMC_STA_RXFIFOF_Msk           (0x1U << SDMMC_STA_RXFIFOF_Pos)        /*!< 0x00020000 */
26139 // #define SDMMC_STA_RXFIFOF               SDMMC_STA_RXFIFOF_Msk                  /*!<Receive FIFO full                             */
26140 // #define SDMMC_STA_TXFIFOE_Pos           (18U)
26141 // #define SDMMC_STA_TXFIFOE_Msk           (0x1U << SDMMC_STA_TXFIFOE_Pos)        /*!< 0x00040000 */
26142 // #define SDMMC_STA_TXFIFOE               SDMMC_STA_TXFIFOE_Msk                  /*!<Transmit FIFO empty                           */
26143 // #define SDMMC_STA_RXFIFOE_Pos           (19U)
26144 // #define SDMMC_STA_RXFIFOE_Msk           (0x1U << SDMMC_STA_RXFIFOE_Pos)        /*!< 0x00080000 */
26145 // #define SDMMC_STA_RXFIFOE               SDMMC_STA_RXFIFOE_Msk                  /*!<Receive FIFO empty                            */
26146 // #define SDMMC_STA_BUSYD0_Pos            (20U)
26147 // #define SDMMC_STA_BUSYD0_Msk            (0x1U << SDMMC_STA_BUSYD0_Pos)         /*!< 0x00100000 */
26148 // #define SDMMC_STA_BUSYD0                SDMMC_STA_BUSYD0_Msk                   /*!<Inverted value of SDMMC_D0 line (Busy)                                  */
26149 // #define SDMMC_STA_BUSYD0END_Pos         (21U)
26150 // #define SDMMC_STA_BUSYD0END_Msk         (0x1U << SDMMC_STA_BUSYD0END_Pos)      /*!< 0x00200000 */
26151 // #define SDMMC_STA_BUSYD0END             SDMMC_STA_BUSYD0END_Msk                /*!<End of SDMMC_D0 Busy following a CMD response detected                  */
26152 // #define SDMMC_STA_SDIOIT_Pos            (22U)
26153 // #define SDMMC_STA_SDIOIT_Msk            (0x1U << SDMMC_STA_SDIOIT_Pos)        /*!< 0x00400000 */
26154 // #define SDMMC_STA_SDIOIT                SDMMC_STA_SDIOIT_Msk                  /*!<SDIO interrupt received                                                 */
26155 // #define SDMMC_STA_ACKFAIL_Pos           (23U)
26156 // #define SDMMC_STA_ACKFAIL_Msk           (0x1U << SDMMC_STA_ACKFAIL_Pos)        /*!< 0x00800000 */
26157 // #define SDMMC_STA_ACKFAIL               SDMMC_STA_ACKFAIL_Msk                  /*!<Boot Acknowledgment received (BootAck check fail)                       */
26158 // #define SDMMC_STA_ACKTIMEOUT_Pos        (24U)
26159 // #define SDMMC_STA_ACKTIMEOUT_Msk        (0x1U << SDMMC_STA_ACKTIMEOUT_Pos)     /*!< 0x01000000 */
26160 // #define SDMMC_STA_ACKTIMEOUT            SDMMC_STA_ACKTIMEOUT_Msk               /*!<Boot Acknowledgment timeout                                             */
26161 // #define SDMMC_STA_VSWEND_Pos            (25U)
26162 // #define SDMMC_STA_VSWEND_Msk            (0x1U << SDMMC_STA_VSWEND_Pos)         /*!< 0x02000000 */
26163 // #define SDMMC_STA_VSWEND                SDMMC_STA_VSWEND_Msk                   /*!<Voltage switch critical timing section completion                       */
26164 // #define SDMMC_STA_CKSTOP_Pos            (26U)
26165 // #define SDMMC_STA_CKSTOP_Msk            (0x1U << SDMMC_STA_CKSTOP_Pos)         /*!< 0x04000000 */
26166 // #define SDMMC_STA_CKSTOP                SDMMC_STA_CKSTOP_Msk                   /*!<SDMMC_CK stopped in Voltage switch procedure                            */
26167 // #define SDMMC_STA_IDMATE_Pos            (27U)
26168 // #define SDMMC_STA_IDMATE_Msk            (0x1U << SDMMC_STA_IDMATE_Pos)         /*!< 0x08000000 */
26169 // #define SDMMC_STA_IDMATE                SDMMC_STA_IDMATE_Msk                   /*!<IDMA transfer error                                                     */
26170 // #define SDMMC_STA_IDMABTC_Pos           (28U)
26171 // #define SDMMC_STA_IDMABTC_Msk           (0x1U << SDMMC_STA_IDMABTC_Pos)        /*!< 0x10000000 */
26172 // #define SDMMC_STA_IDMABTC               SDMMC_STA_IDMABTC_Msk                  /*!<IDMA buffer transfer complete                                           */
26173 
26174 // /*******************  Bit definition for SDMMC_ICR register  *******************/
26175 // #define SDMMC_ICR_CCRCFAILC_Pos         (0U)
26176 // #define SDMMC_ICR_CCRCFAILC_Msk         (0x1U << SDMMC_ICR_CCRCFAILC_Pos)      /*!< 0x00000001 */
26177 // #define SDMMC_ICR_CCRCFAILC             SDMMC_ICR_CCRCFAILC_Msk                /*!<CCRCFAIL flag clear bit */
26178 // #define SDMMC_ICR_DCRCFAILC_Pos         (1U)
26179 // #define SDMMC_ICR_DCRCFAILC_Msk         (0x1U << SDMMC_ICR_DCRCFAILC_Pos)      /*!< 0x00000002 */
26180 // #define SDMMC_ICR_DCRCFAILC             SDMMC_ICR_DCRCFAILC_Msk                /*!<DCRCFAIL flag clear bit */
26181 // #define SDMMC_ICR_CTIMEOUTC_Pos         (2U)
26182 // #define SDMMC_ICR_CTIMEOUTC_Msk         (0x1U << SDMMC_ICR_CTIMEOUTC_Pos)      /*!< 0x00000004 */
26183 // #define SDMMC_ICR_CTIMEOUTC             SDMMC_ICR_CTIMEOUTC_Msk                /*!<CTIMEOUT flag clear bit */
26184 // #define SDMMC_ICR_DTIMEOUTC_Pos         (3U)
26185 // #define SDMMC_ICR_DTIMEOUTC_Msk         (0x1U << SDMMC_ICR_DTIMEOUTC_Pos)      /*!< 0x00000008 */
26186 // #define SDMMC_ICR_DTIMEOUTC             SDMMC_ICR_DTIMEOUTC_Msk                /*!<DTIMEOUT flag clear bit */
26187 // #define SDMMC_ICR_TXUNDERRC_Pos         (4U)
26188 // #define SDMMC_ICR_TXUNDERRC_Msk         (0x1U << SDMMC_ICR_TXUNDERRC_Pos)      /*!< 0x00000010 */
26189 // #define SDMMC_ICR_TXUNDERRC             SDMMC_ICR_TXUNDERRC_Msk                /*!<TXUNDERR flag clear bit */
26190 // #define SDMMC_ICR_RXOVERRC_Pos          (5U)
26191 // #define SDMMC_ICR_RXOVERRC_Msk          (0x1U << SDMMC_ICR_RXOVERRC_Pos)       /*!< 0x00000020 */
26192 // #define SDMMC_ICR_RXOVERRC              SDMMC_ICR_RXOVERRC_Msk                 /*!<RXOVERR flag clear bit  */
26193 // #define SDMMC_ICR_CMDRENDC_Pos          (6U)
26194 // #define SDMMC_ICR_CMDRENDC_Msk          (0x1U << SDMMC_ICR_CMDRENDC_Pos)       /*!< 0x00000040 */
26195 // #define SDMMC_ICR_CMDRENDC              SDMMC_ICR_CMDRENDC_Msk                 /*!<CMDREND flag clear bit  */
26196 // #define SDMMC_ICR_CMDSENTC_Pos          (7U)
26197 // #define SDMMC_ICR_CMDSENTC_Msk          (0x1U << SDMMC_ICR_CMDSENTC_Pos)       /*!< 0x00000080 */
26198 // #define SDMMC_ICR_CMDSENTC              SDMMC_ICR_CMDSENTC_Msk                 /*!<CMDSENT flag clear bit  */
26199 // #define SDMMC_ICR_DATAENDC_Pos          (8U)
26200 // #define SDMMC_ICR_DATAENDC_Msk          (0x1U << SDMMC_ICR_DATAENDC_Pos)       /*!< 0x00000100 */
26201 // #define SDMMC_ICR_DATAENDC              SDMMC_ICR_DATAENDC_Msk                 /*!<DATAEND flag clear bit  */
26202 // #define SDMMC_ICR_DHOLDC_Pos            (9U)
26203 // #define SDMMC_ICR_DHOLDC_Msk            (0x1U << SDMMC_ICR_DHOLDC_Pos)         /*!< 0x00000200 */
26204 // #define SDMMC_ICR_DHOLDC                SDMMC_ICR_DHOLDC_Msk                   /*!<DHOLD flag clear bit       */
26205 // #define SDMMC_ICR_DBCKENDC_Pos          (10U)
26206 // #define SDMMC_ICR_DBCKENDC_Msk          (0x1U << SDMMC_ICR_DBCKENDC_Pos)       /*!< 0x00000400 */
26207 // #define SDMMC_ICR_DBCKENDC              SDMMC_ICR_DBCKENDC_Msk                 /*!<DBCKEND flag clear bit  */
26208 // #define SDMMC_ICR_DABORTC_Pos           (11U)
26209 // #define SDMMC_ICR_DABORTC_Msk           (0x1U << SDMMC_ICR_DABORTC_Pos)        /*!< 0x00000800 */
26210 // #define SDMMC_ICR_DABORTC               SDMMC_ICR_DABORTC_Msk                  /*!<DABORTC flag clear bit     */
26211 // #define SDMMC_ICR_BUSYD0ENDC_Pos        (21U)
26212 // #define SDMMC_ICR_BUSYD0ENDC_Msk        (0x1U << SDMMC_ICR_BUSYD0ENDC_Pos)     /*!< 0x00200000 */
26213 // #define SDMMC_ICR_BUSYD0ENDC            SDMMC_ICR_BUSYD0ENDC_Msk               /*!<BUSYD0ENDC flag clear bit  */
26214 // #define SDMMC_ICR_SDIOITC_Pos           (22U)
26215 // #define SDMMC_ICR_SDIOITC_Msk           (0x1U << SDMMC_ICR_SDIOITC_Pos)       /*!< 0x00400000 */
26216 // #define SDMMC_ICR_SDIOITC               SDMMC_ICR_SDIOITC_Msk                 /*!<SDIOIT flag clear bit      */
26217 // #define SDMMC_ICR_ACKFAILC_Pos          (23U)
26218 // #define SDMMC_ICR_ACKFAILC_Msk          (0x1U << SDMMC_ICR_ACKFAILC_Pos)       /*!< 0x00800000 */
26219 // #define SDMMC_ICR_ACKFAILC              SDMMC_ICR_ACKFAILC_Msk                 /*!<ACKFAILC flag clear bit    */
26220 // #define SDMMC_ICR_ACKTIMEOUTC_Pos       (24U)
26221 // #define SDMMC_ICR_ACKTIMEOUTC_Msk       (0x1U << SDMMC_ICR_ACKTIMEOUTC_Pos)    /*!< 0x01000000 */
26222 // #define SDMMC_ICR_ACKTIMEOUTC           SDMMC_ICR_ACKTIMEOUTC_Msk              /*!<ACKTIMEOUTC flag clear bit */
26223 // #define SDMMC_ICR_VSWENDC_Pos           (25U)
26224 // #define SDMMC_ICR_VSWENDC_Msk           (0x1U << SDMMC_ICR_VSWENDC_Pos)        /*!< 0x02000000 */
26225 // #define SDMMC_ICR_VSWENDC               SDMMC_ICR_VSWENDC_Msk                  /*!<VSWENDC flag clear bit     */
26226 // #define SDMMC_ICR_CKSTOPC_Pos           (26U)
26227 // #define SDMMC_ICR_CKSTOPC_Msk           (0x1U << SDMMC_ICR_CKSTOPC_Pos)        /*!< 0x04000000 */
26228 // #define SDMMC_ICR_CKSTOPC               SDMMC_ICR_CKSTOPC_Msk                  /*!<CKSTOPC flag clear bit     */
26229 // #define SDMMC_ICR_IDMATEC_Pos           (27U)
26230 // #define SDMMC_ICR_IDMATEC_Msk           (0x1U << SDMMC_ICR_IDMATEC_Pos)        /*!< 0x08000000 */
26231 // #define SDMMC_ICR_IDMATEC               SDMMC_ICR_IDMATEC_Msk                  /*!<IDMATEC flag clear bit     */
26232 // #define SDMMC_ICR_IDMABTCC_Pos          (28U)
26233 // #define SDMMC_ICR_IDMABTCC_Msk          (0x1U << SDMMC_ICR_IDMABTCC_Pos)       /*!< 0x10000000 */
26234 // #define SDMMC_ICR_IDMABTCC              SDMMC_ICR_IDMABTCC_Msk                 /*!<IDMABTCC flag clear bit    */
26235 
26236 // /******************  Bit definition for SDMMC_MASK register  *******************/
26237 // #define SDMMC_MASK_CCRCFAILIE_Pos       (0U)
26238 // #define SDMMC_MASK_CCRCFAILIE_Msk       (0x1U << SDMMC_MASK_CCRCFAILIE_Pos)    /*!< 0x00000001 */
26239 // #define SDMMC_MASK_CCRCFAILIE           SDMMC_MASK_CCRCFAILIE_Msk              /*!<Command CRC Fail Interrupt Enable          */
26240 // #define SDMMC_MASK_DCRCFAILIE_Pos       (1U)
26241 // #define SDMMC_MASK_DCRCFAILIE_Msk       (0x1U << SDMMC_MASK_DCRCFAILIE_Pos)    /*!< 0x00000002 */
26242 // #define SDMMC_MASK_DCRCFAILIE           SDMMC_MASK_DCRCFAILIE_Msk              /*!<Data CRC Fail Interrupt Enable             */
26243 // #define SDMMC_MASK_CTIMEOUTIE_Pos       (2U)
26244 // #define SDMMC_MASK_CTIMEOUTIE_Msk       (0x1U << SDMMC_MASK_CTIMEOUTIE_Pos)    /*!< 0x00000004 */
26245 // #define SDMMC_MASK_CTIMEOUTIE           SDMMC_MASK_CTIMEOUTIE_Msk              /*!<Command TimeOut Interrupt Enable           */
26246 // #define SDMMC_MASK_DTIMEOUTIE_Pos       (3U)
26247 // #define SDMMC_MASK_DTIMEOUTIE_Msk       (0x1U << SDMMC_MASK_DTIMEOUTIE_Pos)    /*!< 0x00000008 */
26248 // #define SDMMC_MASK_DTIMEOUTIE           SDMMC_MASK_DTIMEOUTIE_Msk              /*!<Data TimeOut Interrupt Enable              */
26249 // #define SDMMC_MASK_TXUNDERRIE_Pos       (4U)
26250 // #define SDMMC_MASK_TXUNDERRIE_Msk       (0x1U << SDMMC_MASK_TXUNDERRIE_Pos)    /*!< 0x00000010 */
26251 // #define SDMMC_MASK_TXUNDERRIE           SDMMC_MASK_TXUNDERRIE_Msk              /*!<Tx FIFO UnderRun Error Interrupt Enable    */
26252 // #define SDMMC_MASK_RXOVERRIE_Pos        (5U)
26253 // #define SDMMC_MASK_RXOVERRIE_Msk        (0x1U << SDMMC_MASK_RXOVERRIE_Pos)     /*!< 0x00000020 */
26254 // #define SDMMC_MASK_RXOVERRIE            SDMMC_MASK_RXOVERRIE_Msk               /*!<Rx FIFO OverRun Error Interrupt Enable     */
26255 // #define SDMMC_MASK_CMDRENDIE_Pos        (6U)
26256 // #define SDMMC_MASK_CMDRENDIE_Msk        (0x1U << SDMMC_MASK_CMDRENDIE_Pos)     /*!< 0x00000040 */
26257 // #define SDMMC_MASK_CMDRENDIE            SDMMC_MASK_CMDRENDIE_Msk               /*!<Command Response Received Interrupt Enable */
26258 // #define SDMMC_MASK_CMDSENTIE_Pos        (7U)
26259 // #define SDMMC_MASK_CMDSENTIE_Msk        (0x1U << SDMMC_MASK_CMDSENTIE_Pos)     /*!< 0x00000080 */
26260 // #define SDMMC_MASK_CMDSENTIE            SDMMC_MASK_CMDSENTIE_Msk               /*!<Command Sent Interrupt Enable              */
26261 // #define SDMMC_MASK_DATAENDIE_Pos        (8U)
26262 // #define SDMMC_MASK_DATAENDIE_Msk        (0x1U << SDMMC_MASK_DATAENDIE_Pos)     /*!< 0x00000100 */
26263 // #define SDMMC_MASK_DATAENDIE            SDMMC_MASK_DATAENDIE_Msk               /*!<Data End Interrupt Enable                  */
26264 // #define SDMMC_MASK_DHOLDIE_Pos          (9U)
26265 // #define SDMMC_MASK_DHOLDIE_Msk          (0x1U << SDMMC_MASK_DHOLDIE_Pos)       /*!< 0x00000200 */
26266 // #define SDMMC_MASK_DHOLDIE              SDMMC_MASK_DHOLDIE_Msk                 /*!<Data Hold Interrupt Enable                 */
26267 // #define SDMMC_MASK_DBCKENDIE_Pos        (10U)
26268 // #define SDMMC_MASK_DBCKENDIE_Msk        (0x1U << SDMMC_MASK_DBCKENDIE_Pos)     /*!< 0x00000400 */
26269 // #define SDMMC_MASK_DBCKENDIE            SDMMC_MASK_DBCKENDIE_Msk               /*!<Data Block End Interrupt Enable            */
26270 // #define SDMMC_MASK_DABORTIE_Pos         (11U)
26271 // #define SDMMC_MASK_DABORTIE_Msk         (0x1U << SDMMC_MASK_DABORTIE_Pos)      /*!< 0x00000800 */
26272 // #define SDMMC_MASK_DABORTIE             SDMMC_MASK_DABORTIE_Msk                /*!<Data transfer aborted interrupt enable     */
26273 
26274 // #define SDMMC_MASK_TXFIFOHEIE_Pos       (14U)
26275 // #define SDMMC_MASK_TXFIFOHEIE_Msk       (0x1U << SDMMC_MASK_TXFIFOHEIE_Pos)    /*!< 0x00004000 */
26276 // #define SDMMC_MASK_TXFIFOHEIE           SDMMC_MASK_TXFIFOHEIE_Msk              /*!<Tx FIFO Half Empty interrupt Enable        */
26277 // #define SDMMC_MASK_RXFIFOHFIE_Pos       (15U)
26278 // #define SDMMC_MASK_RXFIFOHFIE_Msk       (0x1U << SDMMC_MASK_RXFIFOHFIE_Pos)    /*!< 0x00008000 */
26279 // #define SDMMC_MASK_RXFIFOHFIE           SDMMC_MASK_RXFIFOHFIE_Msk              /*!<Rx FIFO Half Full interrupt Enable         */
26280 
26281 // #define SDMMC_MASK_RXFIFOFIE_Pos        (17U)
26282 // #define SDMMC_MASK_RXFIFOFIE_Msk        (0x1U << SDMMC_MASK_RXFIFOFIE_Pos)     /*!< 0x00020000 */
26283 // #define SDMMC_MASK_RXFIFOFIE            SDMMC_MASK_RXFIFOFIE_Msk               /*!<Rx FIFO Full interrupt Enable              */
26284 // #define SDMMC_MASK_TXFIFOEIE_Pos        (18U)
26285 // #define SDMMC_MASK_TXFIFOEIE_Msk        (0x1U << SDMMC_MASK_TXFIFOEIE_Pos)     /*!< 0x00040000 */
26286 // #define SDMMC_MASK_TXFIFOEIE            SDMMC_MASK_TXFIFOEIE_Msk               /*!<Tx FIFO Empty interrupt Enable             */
26287 
26288 // #define SDMMC_MASK_BUSYD0ENDIE_Pos      (21U)
26289 // #define SDMMC_MASK_BUSYD0ENDIE_Msk      (0x1U << SDMMC_MASK_BUSYD0ENDIE_Pos)   /*!< 0x00200000 */
26290 // #define SDMMC_MASK_BUSYD0ENDIE          SDMMC_MASK_BUSYD0ENDIE_Msk             /*!<BUSYD0ENDIE interrupt Enable */
26291 // #define SDMMC_MASK_SDIOITIE_Pos         (22U)
26292 // #define SDMMC_MASK_SDIOITIE_Msk         (0x1U << SDMMC_MASK_SDIOITIE_Pos)     /*!< 0x00400000 */
26293 // #define SDMMC_MASK_SDIOITIE             SDMMC_MASK_SDIOITIE_Msk               /*!<SDMMC Mode Interrupt Received interrupt Enable */
26294 // #define SDMMC_MASK_ACKFAILIE_Pos        (23U)
26295 // #define SDMMC_MASK_ACKFAILIE_Msk        (0x1U << SDMMC_MASK_ACKFAILIE_Pos)     /*!< 0x00800000 */
26296 // #define SDMMC_MASK_ACKFAILIE            SDMMC_MASK_ACKFAILIE_Msk               /*!<Acknowledgment Fail Interrupt Enable */
26297 // #define SDMMC_MASK_ACKTIMEOUTIE_Pos     (24U)
26298 // #define SDMMC_MASK_ACKTIMEOUTIE_Msk     (0x1U << SDMMC_MASK_ACKTIMEOUTIE_Pos)  /*!< 0x01000000 */
26299 // #define SDMMC_MASK_ACKTIMEOUTIE         SDMMC_MASK_ACKTIMEOUTIE_Msk            /*!<Acknowledgment timeout Interrupt Enable */
26300 // #define SDMMC_MASK_VSWENDIE_Pos         (25U)
26301 // #define SDMMC_MASK_VSWENDIE_Msk         (0x1U << SDMMC_MASK_VSWENDIE_Pos)      /*!< 0x02000000 */
26302 // #define SDMMC_MASK_VSWENDIE             SDMMC_MASK_VSWENDIE_Msk                /*!<Voltage switch critical timing section completion Interrupt Enable */
26303 // #define SDMMC_MASK_CKSTOPIE_Pos         (26U)
26304 // #define SDMMC_MASK_CKSTOPIE_Msk         (0x1U << SDMMC_MASK_CKSTOPIE_Pos)      /*!< 0x04000000 */
26305 // #define SDMMC_MASK_CKSTOPIE             SDMMC_MASK_CKSTOPIE_Msk                /*!<Voltage Switch clock stopped Interrupt Enable */
26306 // #define SDMMC_MASK_IDMABTCIE_Pos        (28U)
26307 // #define SDMMC_MASK_IDMABTCIE_Msk        (0x1U << SDMMC_MASK_IDMABTCIE_Pos)     /*!< 0x10000000 */
26308 // #define SDMMC_MASK_IDMABTCIE            SDMMC_MASK_IDMABTCIE_Msk               /*!<IDMA buffer transfer complete Interrupt Enable */
26309 
26310 // /*****************  Bit definition for SDMMC_FIFOCNT register  *****************/
26311 // #define SDMMC_FIFOCNT_FIFOCOUNT_Pos     (0U)
26312 // #define SDMMC_FIFOCNT_FIFOCOUNT_Msk     (0xFFFFFFU << SDMMC_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
26313 // #define SDMMC_FIFOCNT_FIFOCOUNT         SDMMC_FIFOCNT_FIFOCOUNT_Msk            /*!<Remaining number of words to be written to or read from the FIFO */
26314 
26315 // /******************  Bit definition for SDMMC_FIFO register  *******************/
26316 // #define SDMMC_FIFO_FIFODATA_Pos         (0U)
26317 // #define SDMMC_FIFO_FIFODATA_Msk         (0xFFFFFFFFU << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
26318 // #define SDMMC_FIFO_FIFODATA             SDMMC_FIFO_FIFODATA_Msk                /*!<Receive and transmit FIFO data */
26319 
26320 // /******************  Bit definition for SDMMC_IDMACTRL register ****************/
26321 // #define SDMMC_IDMA_IDMAEN_Pos           (0U)
26322 // #define SDMMC_IDMA_IDMAEN_Msk           (0x1U << SDMMC_IDMA_IDMAEN_Pos)        /*!< 0x00000001 */
26323 // #define SDMMC_IDMA_IDMAEN               SDMMC_IDMA_IDMAEN_Msk                  /*!< Enable the internal DMA of the SDMMC peripheral */
26324 // #define SDMMC_IDMA_IDMABMODE_Pos        (1U)
26325 // #define SDMMC_IDMA_IDMABMODE_Msk        (0x1U << SDMMC_IDMA_IDMABMODE_Pos)     /*!< 0x00000002 */
26326 // #define SDMMC_IDMA_IDMABMODE            SDMMC_IDMA_IDMABMODE_Msk               /*!< Enable double buffer mode for IDMA */
26327 // #define SDMMC_IDMA_IDMABACT_Pos         (2U)
26328 // #define SDMMC_IDMA_IDMABACT_Msk         (0x1U << SDMMC_IDMA_IDMABACT_Pos)      /*!< 0x00000004 */
26329 // #define SDMMC_IDMA_IDMABACT             SDMMC_IDMA_IDMABACT_Msk                /*!< Uses buffer 1 when double buffer mode is selected */
26330 
26331 // /**********************  Bit definition for SDMMC_VERR register  *****************/
26332 // #define SDMMC_VERR_MINREV_Pos      (0U)
26333 // #define SDMMC_VERR_MINREV_Msk      (0xFU << SDMMC_VERR_MINREV_Pos)               /*!< 0x0000000F */
26334 // #define SDMMC_VERR_MINREV          SDMMC_VERR_MINREV_Msk                         /*!< Minor Revision number */
26335 // #define SDMMC_VERR_MAJREV_Pos      (4U)
26336 // #define SDMMC_VERR_MAJREV_Msk      (0xFU << SDMMC_VERR_MAJREV_Pos)               /*!< 0x000000F0 */
26337 // #define SDMMC_VERR_MAJREV          SDMMC_VERR_MAJREV_Msk                         /*!< Major Revision number */
26338 
26339 // /**********************  Bit definition for SDMMC_IPIDR register  ****************/
26340 // #define SDMMC_IPIDR_IPID_Pos       (0U)
26341 // #define SDMMC_IPIDR_IPID_Msk       (0xFFFFFFFFU << SDMMC_IPIDR_IPID_Pos)         /*!< 0xFFFFFFFF */
26342 // #define SDMMC_IPIDR_IPID           SDMMC_IPIDR_IPID_Msk                          /*!< IP Identification */
26343 
26344 // /**********************  Bit definition for SDMMC_SIDR register  *****************/
26345 // #define SDMMC_SIDR_SID_Pos         (0U)
26346 // #define SDMMC_SIDR_SID_Msk         (0xFFFFFFFFU << SDMMC_SIDR_SID_Pos)           /*!< 0xFFFFFFFF */
26347 // #define SDMMC_SIDR_SID             SDMMC_SIDR_SID_Msk                            /*!< IP size identification */
26348 
26349 /******************************************************************************/
26350 /*                                                                            */
26351 /*                        Delay Block Interface (DLYB)                        */
26352 /*                                                                            */
26353 /******************************************************************************/
26354 /*******************  Bit definition for DLYB_CR register  ********************/
26355 #define DLYB_CR_DEN_Pos         (0U)
26356 #define DLYB_CR_DEN_Msk         (0x1U << DLYB_CR_DEN_Pos)                      /*!< 0x00000001 */
26357 #define DLYB_CR_DEN             DLYB_CR_DEN_Msk                                /*!<Delay Block enable */
26358 #define DLYB_CR_SEN_Pos         (1U)
26359 #define DLYB_CR_SEN_Msk         (0x1U << DLYB_CR_SEN_Pos)                      /*!< 0x00000002 */
26360 #define DLYB_CR_SEN             DLYB_CR_SEN_Msk                                /*!<Sampler length enable */
26361 
26362 
26363 /*******************  Bit definition for DLYB_CFGR register  ********************/
26364 #define DLYB_CFGR_SEL_Pos       (0U)
26365 #define DLYB_CFGR_SEL_Msk       (0xFU << DLYB_CFGR_SEL_Pos)                    /*!< 0x0000000F */
26366 #define DLYB_CFGR_SEL           DLYB_CFGR_SEL_Msk                              /*!<Select the phase for the Output clock[3:0] */
26367 #define DLYB_CFGR_SEL_0         (0x1U << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000001 */
26368 #define DLYB_CFGR_SEL_1         (0x2U << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000002 */
26369 #define DLYB_CFGR_SEL_2         (0x3U << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000003 */
26370 #define DLYB_CFGR_SEL_3         (0x8U << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000008 */
26371 
26372 #define DLYB_CFGR_UNIT_Pos      (8U)
26373 #define DLYB_CFGR_UNIT_Msk      (0x7FU << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00007F00 */
26374 #define DLYB_CFGR_UNIT          DLYB_CFGR_UNIT_Msk                             /*!<Delay Defines the delay of a Unit delay cell[6:0] */
26375 #define DLYB_CFGR_UNIT_0        (0x01U << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000100 */
26376 #define DLYB_CFGR_UNIT_1        (0x02U << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000200 */
26377 #define DLYB_CFGR_UNIT_2        (0x04U << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000400 */
26378 #define DLYB_CFGR_UNIT_3        (0x08U << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000800 */
26379 #define DLYB_CFGR_UNIT_4        (0x10U << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00001000 */
26380 #define DLYB_CFGR_UNIT_5        (0x20U << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00002000 */
26381 #define DLYB_CFGR_UNIT_6        (0x40U << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00004000 */
26382 
26383 #define DLYB_CFGR_LNG_Pos       (16U)
26384 #define DLYB_CFGR_LNG_Msk       (0xFFFU << DLYB_CFGR_LNG_Pos)                  /*!< 0x0FFF0000 */
26385 #define DLYB_CFGR_LNG           DLYB_CFGR_LNG_Msk                              /*!<Delay line length value[11:0] */
26386 #define DLYB_CFGR_LNG_0         (0x001U << DLYB_CFGR_LNG_Pos)                  /*!< 0x00010000 */
26387 #define DLYB_CFGR_LNG_1         (0x002U << DLYB_CFGR_LNG_Pos)                  /*!< 0x00020000 */
26388 #define DLYB_CFGR_LNG_2         (0x004U << DLYB_CFGR_LNG_Pos)                  /*!< 0x00040000 */
26389 #define DLYB_CFGR_LNG_3         (0x008U << DLYB_CFGR_LNG_Pos)                  /*!< 0x00080000 */
26390 #define DLYB_CFGR_LNG_4         (0x010U << DLYB_CFGR_LNG_Pos)                  /*!< 0x00100000 */
26391 #define DLYB_CFGR_LNG_5         (0x020U << DLYB_CFGR_LNG_Pos)                  /*!< 0x00200000 */
26392 #define DLYB_CFGR_LNG_6         (0x040U << DLYB_CFGR_LNG_Pos)                  /*!< 0x00400000 */
26393 #define DLYB_CFGR_LNG_7         (0x080U << DLYB_CFGR_LNG_Pos)                  /*!< 0x00800000 */
26394 #define DLYB_CFGR_LNG_8         (0x100U << DLYB_CFGR_LNG_Pos)                  /*!< 0x01000000 */
26395 #define DLYB_CFGR_LNG_9         (0x200U << DLYB_CFGR_LNG_Pos)                  /*!< 0x02000000 */
26396 #define DLYB_CFGR_LNG_10        (0x400U << DLYB_CFGR_LNG_Pos)                  /*!< 0x04000000 */
26397 #define DLYB_CFGR_LNG_11        (0x800U << DLYB_CFGR_LNG_Pos)                  /*!< 0x08000000 */
26398 
26399 #define DLYB_CFGR_LNGF_Pos      (31U)
26400 #define DLYB_CFGR_LNGF_Msk      (0x1U << DLYB_CFGR_LNGF_Pos)                   /*!< 0x80000000 */
26401 #define DLYB_CFGR_LNGF          DLYB_CFGR_LNGF_Msk                             /*!<Length valid flag */
26402 
26403 /**********************  Bit definition for DLYB_VERR register  *****************/
26404 #define DLYB_VERR_MINREV_Pos      (0U)
26405 #define DLYB_VERR_MINREV_Msk      (0xFU << DLYB_VERR_MINREV_Pos)               /*!< 0x0000000F */
26406 #define DLYB_VERR_MINREV          DLYB_VERR_MINREV_Msk                         /*!< Minor Revision number */
26407 #define DLYB_VERR_MAJREV_Pos      (4U)
26408 #define DLYB_VERR_MAJREV_Msk      (0xFU << DLYB_VERR_MAJREV_Pos)               /*!< 0x000000F0 */
26409 #define DLYB_VERR_MAJREV          DLYB_VERR_MAJREV_Msk                         /*!< Major Revision number */
26410 
26411 /**********************  Bit definition for DLYB_IPIDR register  ****************/
26412 #define DLYB_IPIDR_IPID_Pos       (0U)
26413 #define DLYB_IPIDR_IPID_Msk       (0xFFFFFFFFU << DLYB_IPIDR_IPID_Pos)         /*!< 0xFFFFFFFF */
26414 #define DLYB_IPIDR_IPID           DLYB_IPIDR_IPID_Msk                          /*!< IP Identification */
26415 
26416 /**********************  Bit definition for DLYB_SIDR register  *****************/
26417 #define DLYB_SIDR_SID_Pos         (0U)
26418 #define DLYB_SIDR_SID_Msk         (0xFFFFFFFFU << DLYB_SIDR_SID_Pos)           /*!< 0xFFFFFFFF */
26419 #define DLYB_SIDR_SID             DLYB_SIDR_SID_Msk                            /*!< IP size identification */
26420 
26421 /******************************************************************************/
26422 /*                                                                            */
26423 /*                        Serial Peripheral Interface (SPI)                   */
26424 /*                                                                            */
26425 /******************************************************************************/
26426 /*******************  Bit definition for SPI_CR1 register  ********************/
26427 #define SPI_CR1_SPE_Pos             (0U)
26428 #define SPI_CR1_SPE_Msk             (0x1U << SPI_CR1_SPE_Pos)                  /*!< 0x00000001 */
26429 #define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<Serial Peripheral Enable                       */
26430 #define SPI_CR1_MASRX_Pos           (8U)
26431 #define SPI_CR1_MASRX_Msk           (0x1U << SPI_CR1_MASRX_Pos)                /*!< 0x00000100 */
26432 #define SPI_CR1_MASRX               SPI_CR1_MASRX_Msk                          /*!<Master automatic SUSP in Receive mode          */
26433 #define SPI_CR1_CSTART_Pos          (9U)
26434 #define SPI_CR1_CSTART_Msk          (0x1U << SPI_CR1_CSTART_Pos)               /*!< 0x00000200 */
26435 #define SPI_CR1_CSTART              SPI_CR1_CSTART_Msk                         /*!<Master transfer start                          */
26436 #define SPI_CR1_CSUSP_Pos           (10U)
26437 #define SPI_CR1_CSUSP_Msk           (0x1U << SPI_CR1_CSUSP_Pos)                /*!< 0x00000400 */
26438 #define SPI_CR1_CSUSP               SPI_CR1_CSUSP_Msk                          /*!<Master SUSPend request                         */
26439 #define SPI_CR1_HDDIR_Pos           (11U)
26440 #define SPI_CR1_HDDIR_Msk           (0x1U << SPI_CR1_HDDIR_Pos)                /*!< 0x00000800 */
26441 #define SPI_CR1_HDDIR               SPI_CR1_HDDIR_Msk                          /*!<Rx/Tx direction at Half-duplex mode            */
26442 #define SPI_CR1_SSI_Pos             (12U)
26443 #define SPI_CR1_SSI_Msk             (0x1U << SPI_CR1_SSI_Pos)                  /*!< 0x00001000 */
26444 #define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal SS signal input level                 */
26445 #define SPI_CR1_CRC33_17_Pos        (13U)
26446 #define SPI_CR1_CRC33_17_Msk        (0x1U << SPI_CR1_CRC33_17_Pos)             /*!< 0x00002000 */
26447 #define SPI_CR1_CRC33_17            SPI_CR1_CRC33_17_Msk                       /*!<32-bit CRC polynomial configuration            */
26448 #define SPI_CR1_RCRCINI_Pos         (14U)
26449 #define SPI_CR1_RCRCINI_Msk         (0x1U << SPI_CR1_RCRCINI_Pos)              /*!< 0x00004000 */
26450 #define SPI_CR1_RCRCINI             SPI_CR1_RCRCINI_Msk                        /*!<CRC calculation initialization pattern control for receiver    */
26451 #define SPI_CR1_TCRCINI_Pos         (15U)
26452 #define SPI_CR1_TCRCINI_Msk         (0x1U << SPI_CR1_TCRCINI_Pos)              /*!< 0x00008000 */
26453 #define SPI_CR1_TCRCINI             SPI_CR1_TCRCINI_Msk                        /*!<CRC calculation initialization pattern control for transmitter */
26454 #define SPI_CR1_IOLOCK_Pos          (16U)
26455 #define SPI_CR1_IOLOCK_Msk          (0x1U << SPI_CR1_IOLOCK_Pos)               /*!< 0x00010000 */
26456 #define SPI_CR1_IOLOCK              SPI_CR1_IOLOCK_Msk                         /*!<Locking the AF configuration of associated IOs */
26457 
26458 /*******************  Bit definition for SPI_CR2 register  ********************/
26459 #define SPI_CR2_TSER_Pos            (16U)
26460 #define SPI_CR2_TSER_Msk            (0xFFFFU << SPI_CR2_TSER_Pos)              /*!< 0xFFFF0000 */
26461 #define SPI_CR2_TSER                SPI_CR2_TSER_Msk                           /*!<Number of data transfer extension                */
26462 #define SPI_CR2_TSIZE_Pos           (0U)
26463 #define SPI_CR2_TSIZE_Msk           (0xFFFFU << SPI_CR2_TSIZE_Pos)             /*!< 0x0000FFFF */
26464 #define SPI_CR2_TSIZE               SPI_CR2_TSIZE_Msk                          /*!<Number of data at current transfer               */
26465 
26466 /*******************  Bit definition for SPI_CFG1 register  ********************/
26467 #define SPI_CFG1_DSIZE_Pos          (0U)
26468 #define SPI_CFG1_DSIZE_Msk          (0x1FU << SPI_CFG1_DSIZE_Pos)              /*!< 0x0000001F */
26469 #define SPI_CFG1_DSIZE              SPI_CFG1_DSIZE_Msk                         /*!<DSIZE [4:0]: Number of bits in at single SPI data frame */
26470 #define SPI_CFG1_DSIZE_0            (0x01U << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000001 */
26471 #define SPI_CFG1_DSIZE_1            (0x02U << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000002 */
26472 #define SPI_CFG1_DSIZE_2            (0x04U << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000004 */
26473 #define SPI_CFG1_DSIZE_3            (0x08U << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000008 */
26474 #define SPI_CFG1_DSIZE_4            (0x10U << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000010 */
26475 
26476 #define SPI_CFG1_FTHLV_Pos          (5U)
26477 #define SPI_CFG1_FTHLV_Msk          (0xFU << SPI_CFG1_FTHLV_Pos)               /*!< 0x000001E0 */
26478 #define SPI_CFG1_FTHLV              SPI_CFG1_FTHLV_Msk                         /*!<FTHVL [3:0]: FIFO threshold level*/
26479 #define SPI_CFG1_FTHLV_0            (0x1U << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000020 */
26480 #define SPI_CFG1_FTHLV_1            (0x2U << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000040 */
26481 #define SPI_CFG1_FTHLV_2            (0x4U << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000080 */
26482 #define SPI_CFG1_FTHLV_3            (0x8U << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000100 */
26483 
26484 #define SPI_CFG1_UDRCFG_Pos         (9U)
26485 #define SPI_CFG1_UDRCFG_Msk         (0x3U << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000600 */
26486 #define SPI_CFG1_UDRCFG             SPI_CFG1_UDRCFG_Msk                        /*!<UDRCFG [1:0]: Behavior of slave transmitter at underrun condition*/
26487 #define SPI_CFG1_UDRCFG_0           (0x1U << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000200 */
26488 #define SPI_CFG1_UDRCFG_1           (0x2U << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000400 */
26489 
26490 
26491 #define SPI_CFG1_UDRDET_Pos         (11U)
26492 #define SPI_CFG1_UDRDET_Msk         (0x3U << SPI_CFG1_UDRDET_Pos)              /*!< 0x00001800 */
26493 #define SPI_CFG1_UDRDET             SPI_CFG1_UDRDET_Msk                        /*!<UDRDET [1:0]: Detection of underrun condition at slave transmitter*/
26494 #define SPI_CFG1_UDRDET_0           (0x1U << SPI_CFG1_UDRDET_Pos)              /*!< 0x00000800 */
26495 #define SPI_CFG1_UDRDET_1           (0x2U << SPI_CFG1_UDRDET_Pos)              /*!< 0x00001000 */
26496 
26497 #define SPI_CFG1_RXDMAEN_Pos        (14U)
26498 #define SPI_CFG1_RXDMAEN_Msk        (0x1U << SPI_CFG1_RXDMAEN_Pos)             /*!< 0x00004000 */
26499 #define SPI_CFG1_RXDMAEN            SPI_CFG1_RXDMAEN_Msk                       /*!<Rx DMA stream enable                */
26500 #define SPI_CFG1_TXDMAEN_Pos        (15U)
26501 #define SPI_CFG1_TXDMAEN_Msk        (0x1U << SPI_CFG1_TXDMAEN_Pos)             /*!< 0x00008000 */
26502 #define SPI_CFG1_TXDMAEN            SPI_CFG1_TXDMAEN_Msk                       /*!<Tx DMA stream enable                */
26503 
26504 #define SPI_CFG1_CRCSIZE_Pos        (16U)
26505 #define SPI_CFG1_CRCSIZE_Msk        (0x1FU << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x001F0000 */
26506 #define SPI_CFG1_CRCSIZE            SPI_CFG1_CRCSIZE_Msk                       /*!<CRCSIZE [4:0]: Length of CRC frame*/
26507 #define SPI_CFG1_CRCSIZE_0          (0x01U << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00010000 */
26508 #define SPI_CFG1_CRCSIZE_1          (0x02U << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00020000 */
26509 #define SPI_CFG1_CRCSIZE_2          (0x04U << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00040000 */
26510 #define SPI_CFG1_CRCSIZE_3          (0x08U << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00080000 */
26511 #define SPI_CFG1_CRCSIZE_4          (0x10U << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00100000 */
26512 
26513 #define SPI_CFG1_CRCEN_Pos          (22U)
26514 #define SPI_CFG1_CRCEN_Msk          (0x1U << SPI_CFG1_CRCEN_Pos)               /*!< 0x00400000 */
26515 #define SPI_CFG1_CRCEN              SPI_CFG1_CRCEN_Msk                         /*!<Hardware CRC computation enable */
26516 
26517 #define SPI_CFG1_MBR_Pos            (28U)
26518 #define SPI_CFG1_MBR_Msk            (0x7U << SPI_CFG1_MBR_Pos)                 /*!< 0x70000000 */
26519 #define SPI_CFG1_MBR                SPI_CFG1_MBR_Msk                           /*!<Master baud rate                */
26520 #define SPI_CFG1_MBR_0              (0x1U << SPI_CFG1_MBR_Pos)                 /*!< 0x10000000 */
26521 #define SPI_CFG1_MBR_1              (0x2U << SPI_CFG1_MBR_Pos)                 /*!< 0x20000000 */
26522 #define SPI_CFG1_MBR_2              (0x4U << SPI_CFG1_MBR_Pos)                 /*!< 0x40000000 */
26523 
26524 /*******************  Bit definition for SPI_CFG2 register  ********************/
26525 #define SPI_CFG2_MSSI_Pos           (0U)
26526 #define SPI_CFG2_MSSI_Msk           (0xFU << SPI_CFG2_MSSI_Pos)                /*!< 0x0000000F */
26527 #define SPI_CFG2_MSSI               SPI_CFG2_MSSI_Msk                          /*!<Master SS Idleness */
26528 #define SPI_CFG2_MSSI_0             (0x1U << SPI_CFG2_MSSI_Pos)                /*!< 0x00000001 */
26529 #define SPI_CFG2_MSSI_1             (0x2U << SPI_CFG2_MSSI_Pos)                /*!< 0x00000002 */
26530 #define SPI_CFG2_MSSI_2             (0x4U << SPI_CFG2_MSSI_Pos)                /*!< 0x00000004 */
26531 #define SPI_CFG2_MSSI_3             (0x8U << SPI_CFG2_MSSI_Pos)                /*!< 0x00000008 */
26532 
26533 #define SPI_CFG2_MIDI_Pos           (4U)
26534 #define SPI_CFG2_MIDI_Msk           (0xFU << SPI_CFG2_MIDI_Pos)                /*!< 0x000000F0 */
26535 #define SPI_CFG2_MIDI               SPI_CFG2_MIDI_Msk                          /*!<Master Inter-Data Idleness */
26536 #define SPI_CFG2_MIDI_0             (0x1U << SPI_CFG2_MIDI_Pos)                /*!< 0x00000010 */
26537 #define SPI_CFG2_MIDI_1             (0x2U << SPI_CFG2_MIDI_Pos)                /*!< 0x00000020 */
26538 #define SPI_CFG2_MIDI_2             (0x4U << SPI_CFG2_MIDI_Pos)                /*!< 0x00000040 */
26539 #define SPI_CFG2_MIDI_3             (0x8U << SPI_CFG2_MIDI_Pos)                /*!< 0x00000080 */
26540 
26541 #define SPI_CFG2_IOSWP_Pos          (15U)
26542 #define SPI_CFG2_IOSWP_Msk          (0x1U << SPI_CFG2_IOSWP_Pos)               /*!< 0x00008000 */
26543 #define SPI_CFG2_IOSWP              SPI_CFG2_IOSWP_Msk                         /*!<Swap functionality of MISO and MOSI pins */
26544 
26545 #define SPI_CFG2_COMM_Pos           (17U)
26546 #define SPI_CFG2_COMM_Msk           (0x3U << SPI_CFG2_COMM_Pos)                /*!< 0x00060000 */
26547 #define SPI_CFG2_COMM               SPI_CFG2_COMM_Msk                          /*!<COMM [1:0]: SPI Communication Mode*/
26548 #define SPI_CFG2_COMM_0             (0x1U << SPI_CFG2_COMM_Pos)                /*!< 0x00020000 */
26549 #define SPI_CFG2_COMM_1             (0x2U << SPI_CFG2_COMM_Pos)                /*!< 0x00040000 */
26550 
26551 #define SPI_CFG2_SP_Pos             (19U)
26552 #define SPI_CFG2_SP_Msk             (0x7U << SPI_CFG2_SP_Pos)                  /*!< 0x00380000 */
26553 #define SPI_CFG2_SP                 SPI_CFG2_SP_Msk                            /*!<SP[2:0]: Serial Protocol */
26554 #define SPI_CFG2_SP_0               (0x1U << SPI_CFG2_SP_Pos)                  /*!< 0x00080000 */
26555 #define SPI_CFG2_SP_1               (0x2U << SPI_CFG2_SP_Pos)                  /*!< 0x00100000 */
26556 #define SPI_CFG2_SP_2               (0x4U << SPI_CFG2_SP_Pos)                  /*!< 0x00200000 */
26557 
26558 #define SPI_CFG2_MASTER_Pos         (22U)
26559 #define SPI_CFG2_MASTER_Msk         (0x1U << SPI_CFG2_MASTER_Pos)              /*!< 0x00400000 */
26560 #define SPI_CFG2_MASTER             SPI_CFG2_MASTER_Msk                        /*!<SPI Master           */
26561 #define SPI_CFG2_LSBFRST_Pos        (23U)
26562 #define SPI_CFG2_LSBFRST_Msk        (0x1U << SPI_CFG2_LSBFRST_Pos)             /*!< 0x00800000 */
26563 #define SPI_CFG2_LSBFRST            SPI_CFG2_LSBFRST_Msk                       /*!<Data frame format               */
26564 #define SPI_CFG2_CPHA_Pos           (24U)
26565 #define SPI_CFG2_CPHA_Msk           (0x1U << SPI_CFG2_CPHA_Pos)                /*!< 0x01000000 */
26566 #define SPI_CFG2_CPHA               SPI_CFG2_CPHA_Msk                          /*!<Clock Phase      */
26567 #define SPI_CFG2_CPOL_Pos           (25U)
26568 #define SPI_CFG2_CPOL_Msk           (0x1U << SPI_CFG2_CPOL_Pos)                /*!< 0x02000000 */
26569 #define SPI_CFG2_CPOL               SPI_CFG2_CPOL_Msk                          /*!<Clock Polarity   */
26570 #define SPI_CFG2_SSM_Pos            (26U)
26571 #define SPI_CFG2_SSM_Msk            (0x1U << SPI_CFG2_SSM_Pos)                 /*!< 0x04000000 */
26572 #define SPI_CFG2_SSM                SPI_CFG2_SSM_Msk                           /*!<Software slave management */
26573 
26574 #define SPI_CFG2_SSIOP_Pos          (28U)
26575 #define SPI_CFG2_SSIOP_Msk          (0x1U << SPI_CFG2_SSIOP_Pos)               /*!< 0x10000000 */
26576 #define SPI_CFG2_SSIOP              SPI_CFG2_SSIOP_Msk                         /*!<SS input/output polarity */
26577 #define SPI_CFG2_SSOE_Pos           (29U)
26578 #define SPI_CFG2_SSOE_Msk           (0x1U << SPI_CFG2_SSOE_Pos)                /*!< 0x20000000 */
26579 #define SPI_CFG2_SSOE               SPI_CFG2_SSOE_Msk                          /*!<SS output enable */
26580 #define SPI_CFG2_SSOM_Pos           (30U)
26581 #define SPI_CFG2_SSOM_Msk           (0x1U << SPI_CFG2_SSOM_Pos)                /*!< 0x40000000 */
26582 #define SPI_CFG2_SSOM               SPI_CFG2_SSOM_Msk                          /*!<SS output management in master mode */
26583 
26584 #define SPI_CFG2_AFCNTR_Pos         (31U)
26585 #define SPI_CFG2_AFCNTR_Msk         (0x1U << SPI_CFG2_AFCNTR_Pos)              /*!< 0x80000000 */
26586 #define SPI_CFG2_AFCNTR             SPI_CFG2_AFCNTR_Msk                        /*!<Alternate function GPIOs control */
26587 
26588 /*******************  Bit definition for SPI_IER register  ********************/
26589 #define SPI_IER_RXPIE_Pos           (0U)
26590 #define SPI_IER_RXPIE_Msk           (0x1U << SPI_IER_RXPIE_Pos)                /*!< 0x00000001 */
26591 #define SPI_IER_RXPIE               SPI_IER_RXPIE_Msk                          /*!<RXP Interrupt Enable						*/
26592 #define SPI_IER_TXPIE_Pos           (1U)
26593 #define SPI_IER_TXPIE_Msk           (0x1U << SPI_IER_TXPIE_Pos)                /*!< 0x00000002 */
26594 #define SPI_IER_TXPIE               SPI_IER_TXPIE_Msk                          /*!<TXP interrupt enable						*/
26595 #define SPI_IER_DXPIE_Pos           (2U)
26596 #define SPI_IER_DXPIE_Msk           (0x1U << SPI_IER_DXPIE_Pos)                /*!< 0x00000004 */
26597 #define SPI_IER_DXPIE               SPI_IER_DXPIE_Msk                          /*!<DXP interrupt enable 						*/
26598 #define SPI_IER_EOTIE_Pos           (3U)
26599 #define SPI_IER_EOTIE_Msk           (0x1U << SPI_IER_EOTIE_Pos)                /*!< 0x00000008 */
26600 #define SPI_IER_EOTIE               SPI_IER_EOTIE_Msk                          /*!<EOT/SUSP/TXC interrupt enable 	*/
26601 #define SPI_IER_TXTFIE_Pos          (4U)
26602 #define SPI_IER_TXTFIE_Msk          (0x1U << SPI_IER_TXTFIE_Pos)               /*!< 0x00000010 */
26603 #define SPI_IER_TXTFIE              SPI_IER_TXTFIE_Msk                         /*!<TXTF interrupt enable 					*/
26604 #define SPI_IER_UDRIE_Pos           (5U)
26605 #define SPI_IER_UDRIE_Msk           (0x1U << SPI_IER_UDRIE_Pos)                /*!< 0x00000020 */
26606 #define SPI_IER_UDRIE               SPI_IER_UDRIE_Msk                          /*!<UDR interrupt enable 						*/
26607 #define SPI_IER_OVRIE_Pos           (6U)
26608 #define SPI_IER_OVRIE_Msk           (0x1U << SPI_IER_OVRIE_Pos)                /*!< 0x00000040 */
26609 #define SPI_IER_OVRIE               SPI_IER_OVRIE_Msk                          /*!<OVR interrupt enable 						*/
26610 #define SPI_IER_CRCEIE_Pos           (7U)
26611 #define SPI_IER_CRCEIE_Msk           (0x1U << SPI_IER_CRCEIE_Pos)                /*!< 0x00000080 */
26612 #define SPI_IER_CRCEIE               SPI_IER_CRCEIE_Msk                          /*!<CRC interrupt enable 						*/
26613 #define SPI_IER_TIFREIE_Pos         (8U)
26614 #define SPI_IER_TIFREIE_Msk         (0x1U << SPI_IER_TIFREIE_Pos)              /*!< 0x00000100 */
26615 #define SPI_IER_TIFREIE             SPI_IER_TIFREIE_Msk                        /*!<TI Frame Error interrupt enable */
26616 #define SPI_IER_MODFIE_Pos          (9U)
26617 #define SPI_IER_MODFIE_Msk          (0x1U << SPI_IER_MODFIE_Pos)               /*!< 0x00000200 */
26618 #define SPI_IER_MODFIE              SPI_IER_MODFIE_Msk                         /*!<MODF interrupt enable 					*/
26619 #define SPI_IER_TSERFIE_Pos          (10U)
26620 #define SPI_IER_TSERFIE_Msk          (0x1U << SPI_IER_TSERFIE_Pos)               /*!< 0x00000400 */
26621 #define SPI_IER_TSERFIE              SPI_IER_TSERFIE_Msk                         /*!<TSERF interrupt enable 				*/
26622 
26623 /*******************  Bit definition for SPI_SR register  ********************/
26624 #define SPI_SR_RXP_Pos              (0U)
26625 #define SPI_SR_RXP_Msk              (0x1U << SPI_SR_RXP_Pos)                   /*!< 0x00000001 */
26626 #define SPI_SR_RXP                  SPI_SR_RXP_Msk                             /*!<Rx-Packet available            */
26627 #define SPI_SR_TXP_Pos              (1U)
26628 #define SPI_SR_TXP_Msk              (0x1U << SPI_SR_TXP_Pos)                   /*!< 0x00000002 */
26629 #define SPI_SR_TXP                  SPI_SR_TXP_Msk                             /*!<Tx-Packet space available      */
26630 #define SPI_SR_DXP_Pos              (2U)
26631 #define SPI_SR_DXP_Msk              (0x1U << SPI_SR_DXP_Pos)                   /*!< 0x00000004 */
26632 #define SPI_SR_DXP                  SPI_SR_DXP_Msk                             /*!<Duplex Packet available         */
26633 #define SPI_SR_EOT_Pos              (3U)
26634 #define SPI_SR_EOT_Msk              (0x1U << SPI_SR_EOT_Pos)                   /*!< 0x00000008 */
26635 #define SPI_SR_EOT                  SPI_SR_EOT_Msk                             /*!<Duplex Packet available         */
26636 #define SPI_SR_TXTF_Pos             (4U)
26637 #define SPI_SR_TXTF_Msk             (0x1U << SPI_SR_TXTF_Pos)                  /*!< 0x00000010 */
26638 #define SPI_SR_TXTF                 SPI_SR_TXTF_Msk                            /*!<Transmission Transfer Filled    */
26639 #define SPI_SR_UDR_Pos              (5U)
26640 #define SPI_SR_UDR_Msk              (0x1U << SPI_SR_UDR_Pos)                   /*!< 0x00000020 */
26641 #define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!<UDR at Slave transmission       */
26642 #define SPI_SR_OVR_Pos              (6U)
26643 #define SPI_SR_OVR_Msk              (0x1U << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */
26644 #define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!<Rx-Packet available            */
26645 #define SPI_SR_CRCE_Pos             (7U)
26646 #define SPI_SR_CRCE_Msk             (0x1U << SPI_SR_CRCE_Pos)                  /*!< 0x00000080 */
26647 #define SPI_SR_CRCE                 SPI_SR_CRCE_Msk                            /*!<CRC Error Detected              */
26648 #define SPI_SR_TIFRE_Pos            (8U)
26649 #define SPI_SR_TIFRE_Msk            (0x1U << SPI_SR_TIFRE_Pos)                 /*!< 0x00000100 */
26650 #define SPI_SR_TIFRE                SPI_SR_TIFRE_Msk                           /*!<TI frame format error Detected  */
26651 #define SPI_SR_MODF_Pos             (9U)
26652 #define SPI_SR_MODF_Msk             (0x1U << SPI_SR_MODF_Pos)                  /*!< 0x00000200 */
26653 #define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!<Mode Fault Detected             */
26654 #define SPI_SR_TSERF_Pos            (10U)
26655 #define SPI_SR_TSERF_Msk            (0x1U << SPI_SR_TSERF_Pos)                 /*!< 0x00000400 */
26656 #define SPI_SR_TSERF                SPI_SR_TSERF_Msk                           /*!<Additional number of SPI data to be transacted was reload */
26657 #define SPI_SR_SUSP_Pos             (11U)
26658 #define SPI_SR_SUSP_Msk             (0x1U << SPI_SR_SUSP_Pos)                  /*!< 0x00000800 */
26659 #define SPI_SR_SUSP                 SPI_SR_SUSP_Msk                            /*!<SUSP is set by hardware  */
26660 #define SPI_SR_TXC_Pos              (12U)
26661 #define SPI_SR_TXC_Msk              (0x1U << SPI_SR_TXC_Pos)                   /*!< 0x00001000 */
26662 #define SPI_SR_TXC                  SPI_SR_TXC_Msk                             /*!<TxFIFO transmission complete */
26663 #define SPI_SR_RXPLVL_Pos           (13U)
26664 #define SPI_SR_RXPLVL_Msk           (0x3U << SPI_SR_RXPLVL_Pos)                /*!< 0x00006000 */
26665 #define SPI_SR_RXPLVL               SPI_SR_RXPLVL_Msk                          /*!<RxFIFO Packing Level                             */
26666 #define SPI_SR_RXPLVL_0             (0x1U << SPI_SR_RXPLVL_Pos)                /*!< 0x00002000 */
26667 #define SPI_SR_RXPLVL_1             (0x2U << SPI_SR_RXPLVL_Pos)                /*!< 0x00004000 */
26668 #define SPI_SR_RXWNE_Pos            (15U)
26669 #define SPI_SR_RXWNE_Msk            (0x1U << SPI_SR_RXWNE_Pos)                 /*!< 0x00008000 */
26670 #define SPI_SR_RXWNE                SPI_SR_RXWNE_Msk                           /*!<Rx FIFO Word Not Empty                           */
26671 #define SPI_SR_CTSIZE_Pos           (16U)
26672 #define SPI_SR_CTSIZE_Msk           (0xFFFFU << SPI_SR_CTSIZE_Pos)             /*!< 0xFFFF0000 */
26673 #define SPI_SR_CTSIZE               SPI_SR_CTSIZE_Msk                          /*!<Number of data frames remaining in TSIZE         */
26674 
26675 /*******************  Bit definition for SPI_IFCR register  ********************/
26676 #define SPI_IFCR_EOTC_Pos           (3U)
26677 #define SPI_IFCR_EOTC_Msk           (0x1U << SPI_IFCR_EOTC_Pos)                /*!< 0x00000008 */
26678 #define SPI_IFCR_EOTC               SPI_IFCR_EOTC_Msk                          /*!<End Of Transfer flag clear              */
26679 #define SPI_IFCR_TXTFC_Pos          (4U)
26680 #define SPI_IFCR_TXTFC_Msk          (0x1U << SPI_IFCR_TXTFC_Pos)               /*!< 0x00000010 */
26681 #define SPI_IFCR_TXTFC              SPI_IFCR_TXTFC_Msk                         /*!<Transmission Transfer Filled flag clear */
26682 #define SPI_IFCR_UDRC_Pos           (5U)
26683 #define SPI_IFCR_UDRC_Msk           (0x1U << SPI_IFCR_UDRC_Pos)                /*!< 0x00000020 */
26684 #define SPI_IFCR_UDRC               SPI_IFCR_UDRC_Msk                          /*!<Underrun flag clear                     */
26685 #define SPI_IFCR_OVRC_Pos           (6U)
26686 #define SPI_IFCR_OVRC_Msk           (0x1U << SPI_IFCR_OVRC_Pos)                /*!< 0x00000040 */
26687 #define SPI_IFCR_OVRC               SPI_IFCR_OVRC_Msk                          /*!<Overrun flag clear                      */
26688 #define SPI_IFCR_CRCEC_Pos          (7U)
26689 #define SPI_IFCR_CRCEC_Msk          (0x1U << SPI_IFCR_CRCEC_Pos)               /*!< 0x00000080 */
26690 #define SPI_IFCR_CRCEC              SPI_IFCR_CRCEC_Msk                         /*!<CRC Error flag clear                    */
26691 #define SPI_IFCR_TIFREC_Pos         (8U)
26692 #define SPI_IFCR_TIFREC_Msk         (0x1U << SPI_IFCR_TIFREC_Pos)              /*!< 0x00000100 */
26693 #define SPI_IFCR_TIFREC             SPI_IFCR_TIFREC_Msk                        /*!<TI frame format error flag clear        */
26694 #define SPI_IFCR_MODFC_Pos          (9U)
26695 #define SPI_IFCR_MODFC_Msk          (0x1U << SPI_IFCR_MODFC_Pos)               /*!< 0x00000200 */
26696 #define SPI_IFCR_MODFC              SPI_IFCR_MODFC_Msk                         /*!<Mode Fault flag clear                   */
26697 #define SPI_IFCR_TSERFC_Pos         (10U)
26698 #define SPI_IFCR_TSERFC_Msk         (0x1U << SPI_IFCR_TSERFC_Pos)              /*!< 0x00000400 */
26699 #define SPI_IFCR_TSERFC             SPI_IFCR_TSERFC_Msk                        /*!<TSERFC flag clear                       */
26700 #define SPI_IFCR_SUSPC_Pos          (11U)
26701 #define SPI_IFCR_SUSPC_Msk          (0x1U << SPI_IFCR_SUSPC_Pos)               /*!< 0x00000800 */
26702 #define SPI_IFCR_SUSPC              SPI_IFCR_SUSPC_Msk                         /*!<SUSPend flag clear                      */
26703 
26704 /*******************  Bit definition for SPI_TXDR register  ********************/
26705 #define SPI_TXDR_TXDR_Pos           (0U)
26706 #define SPI_TXDR_TXDR_Msk           (0xFFFFFFFFU << SPI_TXDR_TXDR_Pos)         /*!< 0xFFFFFFFF */
26707 #define SPI_TXDR_TXDR               SPI_TXDR_TXDR_Msk                          /* Transmit Data Register */
26708 
26709 /*******************  Bit definition for SPI_RXDR register  ********************/
26710 #define SPI_RXDR_RXDR_Pos           (0U)
26711 #define SPI_RXDR_RXDR_Msk           (0xFFFFFFFFU << SPI_RXDR_RXDR_Pos)         /*!< 0xFFFFFFFF */
26712 #define SPI_RXDR_RXDR               SPI_RXDR_RXDR_Msk                          /* Receive Data Register  */
26713 
26714 /*******************  Bit definition for SPI_CRCPOLY register  ********************/
26715 #define SPI_CRCPOLY_CRCPOLY_Pos     (0U)
26716 #define SPI_CRCPOLY_CRCPOLY_Msk     (0xFFFFFFFFU << SPI_CRCPOLY_CRCPOLY_Pos)   /*!< 0xFFFFFFFF */
26717 #define SPI_CRCPOLY_CRCPOLY         SPI_CRCPOLY_CRCPOLY_Msk                    /* CRC Polynomial register  */
26718 
26719 /*******************  Bit definition for SPI_TXCRC register  ********************/
26720 #define SPI_TXCRC_TXCRC_Pos         (0U)
26721 #define SPI_TXCRC_TXCRC_Msk         (0xFFFFFFFFU << SPI_TXCRC_TXCRC_Pos)       /*!< 0xFFFFFFFF */
26722 #define SPI_TXCRC_TXCRC             SPI_TXCRC_TXCRC_Msk                        /* CRCRegister for transmitter */
26723 
26724 /*******************  Bit definition for SPI_RXCRC register  ********************/
26725 #define SPI_RXCRC_RXCRC_Pos         (0U)
26726 #define SPI_RXCRC_RXCRC_Msk         (0xFFFFFFFFU << SPI_RXCRC_RXCRC_Pos)       /*!< 0xFFFFFFFF */
26727 #define SPI_RXCRC_RXCRC             SPI_RXCRC_RXCRC_Msk                        /* CRCRegister for receiver */
26728 
26729 /*******************  Bit definition for SPI_UDRDR register  ********************/
26730 #define SPI_UDRDR_UDRDR_Pos         (0U)
26731 #define SPI_UDRDR_UDRDR_Msk         (0xFFFFFFFFU << SPI_UDRDR_UDRDR_Pos)       /*!< 0xFFFFFFFF */
26732 #define SPI_UDRDR_UDRDR             SPI_UDRDR_UDRDR_Msk                        /* Data at slave underrun condition */
26733 
26734 /******************  Bit definition for SPI_I2SCFGR register  *****************/
26735 #define SPI_I2SCFGR_I2SMOD_Pos      (0U)
26736 #define SPI_I2SCFGR_I2SMOD_Msk      (0x1U << SPI_I2SCFGR_I2SMOD_Pos)           /*!< 0x00000001 */
26737 #define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
26738 #define SPI_I2SCFGR_I2SCFG_Pos      (1U)
26739 #define SPI_I2SCFGR_I2SCFG_Msk      (0x7U << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x0000000E */
26740 #define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFGR[1:0] bits (I2S configuration mode) */
26741 #define SPI_I2SCFGR_I2SCFG_0        (0x1U << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000002 */
26742 #define SPI_I2SCFGR_I2SCFG_1        (0x2U << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000004 */
26743 #define SPI_I2SCFGR_I2SCFG_2        (0x4U << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000008 */
26744 #define SPI_I2SCFGR_I2SSTD_Pos      (4U)
26745 #define SPI_I2SCFGR_I2SSTD_Msk      (0x3U << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000030 */
26746 #define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] I2S standard selection                */
26747 #define SPI_I2SCFGR_I2SSTD_0        (0x1U << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */
26748 #define SPI_I2SCFGR_I2SSTD_1        (0x2U << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */
26749 #define SPI_I2SCFGR_PCMSYNC_Pos     (7U)
26750 #define SPI_I2SCFGR_PCMSYNC_Msk     (0x1U << SPI_I2SCFGR_PCMSYNC_Pos)          /*!< 0x00000080 */
26751 #define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                         */
26752 #define SPI_I2SCFGR_DATLEN_Pos      (8U)
26753 #define SPI_I2SCFGR_DATLEN_Msk      (0x3U << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000300 */
26754 #define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] Data length to be transferred         */
26755 #define SPI_I2SCFGR_DATLEN_0        (0x1U << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000100 */
26756 #define SPI_I2SCFGR_DATLEN_1        (0x2U << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000200 */
26757 #define SPI_I2SCFGR_CHLEN_Pos       (10U)
26758 #define SPI_I2SCFGR_CHLEN_Msk       (0x1U << SPI_I2SCFGR_CHLEN_Pos)            /*!< 0x00000400 */
26759 #define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
26760 #define SPI_I2SCFGR_CKPOL_Pos       (11U)
26761 #define SPI_I2SCFGR_CKPOL_Msk       (0x1U << SPI_I2SCFGR_CKPOL_Pos)            /*!< 0x00000800 */
26762 #define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<Steady state clock polarity                       */
26763 #define SPI_I2SCFGR_FIXCH_Pos       (12U)
26764 #define SPI_I2SCFGR_FIXCH_Msk       (0x1U << SPI_I2SCFGR_FIXCH_Pos)            /*!< 0x00001000 */
26765 #define SPI_I2SCFGR_FIXCH           SPI_I2SCFGR_FIXCH_Msk                      /*!<Fixed channel length in SLAVE                     */
26766 #define SPI_I2SCFGR_WSINV_Pos       (13U)
26767 #define SPI_I2SCFGR_WSINV_Msk       (0x1U << SPI_I2SCFGR_WSINV_Pos)            /*!< 0x00002000 */
26768 #define SPI_I2SCFGR_WSINV           SPI_I2SCFGR_WSINV_Msk                      /*!<Word select inversion                             */
26769 #define SPI_I2SCFGR_DATFMT_Pos      (14U)
26770 #define SPI_I2SCFGR_DATFMT_Msk      (0x1U << SPI_I2SCFGR_DATFMT_Pos)           /*!< 0x00003000 */
26771 #define SPI_I2SCFGR_DATFMT          SPI_I2SCFGR_DATFMT_Msk                     /*!<Data format                                       */
26772 #define SPI_I2SCFGR_I2SDIV_Pos      (16U)
26773 #define SPI_I2SCFGR_I2SDIV_Msk      (0xFFU << SPI_I2SCFGR_I2SDIV_Pos)          /*!< 0x00FF0000 */
26774 #define SPI_I2SCFGR_I2SDIV          SPI_I2SCFGR_I2SDIV_Msk                     /*!<I2S Linear prescaler */
26775 #define SPI_I2SCFGR_ODD_Pos         (24U)
26776 #define SPI_I2SCFGR_ODD_Msk         (0x1U << SPI_I2SCFGR_ODD_Pos)              /*!< 0x01000000 */
26777 #define SPI_I2SCFGR_ODD             SPI_I2SCFGR_ODD_Msk                        /*!<Odd factor for the prescaler */
26778 #define SPI_I2SCFGR_MCKOE_Pos       (25U)
26779 #define SPI_I2SCFGR_MCKOE_Msk       (0x1U << SPI_I2SCFGR_MCKOE_Pos)            /*!< 0x02000000 */
26780 #define SPI_I2SCFGR_MCKOE           SPI_I2SCFGR_MCKOE_Msk                      /*!<Master Clock Output Enable */
26781 
26782 /**********************  Bit definition for SPI_HWCFGR register  ***************/
26783 #define SPI_HWCFGR_TXFCFG_Pos    (0U)
26784 #define SPI_HWCFGR_TXFCFG_Msk    (0xFU << SPI_HWCFGR_TXFCFG_Pos)               /*!< 0x0000000F */
26785 #define SPI_HWCFGR_TXFCFG        SPI_HWCFGR_TXFCFG_Msk                         /*!< TxFIFO size */
26786 #define SPI_HWCFGR_RXFCFG_Pos    (4U)
26787 #define SPI_HWCFGR_RXFCFG_Msk    (0xFU << SPI_HWCFGR_RXFCFG_Pos)               /*!< 0x0000000F */
26788 #define SPI_HWCFGR_RXFCFG        SPI_HWCFGR_RXFCFG_Msk                         /*!< RxFIFO size */
26789 #define SPI_HWCFGR_CRCCFG_Pos    (8U)
26790 #define SPI_HWCFGR_CRCCFG_Msk    (0xFU << SPI_HWCFGR_CRCCFG_Pos)               /*!< 0x0000000F */
26791 #define SPI_HWCFGR_CRCCFG        SPI_HWCFGR_CRCCFG_Msk                         /*!< CRC configuration for SPI */
26792 #define SPI_HWCFGR_I2SCFG_Pos    (12U)
26793 #define SPI_HWCFGR_I2SCFG_Msk    (0xFU << SPI_HWCFGR_I2SCFG_Pos)               /*!< 0x0000000F */
26794 #define SPI_HWCFGR_I2SCFG        SPI_HWCFGR_I2SCFG_Msk                         /*!< I2S configuration */
26795 #define SPI_HWCFGR_DSCFG_Pos     (16U)
26796 #define SPI_HWCFGR_DSCFG_Msk     (0xFU << SPI_HWCFGR_DSCFG_Pos)                /*!< 0x0000000F */
26797 #define SPI_HWCFGR_DSCFG         SPI_HWCFGR_DSCFG_Msk                          /*!< SPI data size configuration */
26798 
26799 /**********************  Bit definition for SPI_VERR register  *****************/
26800 #define SPI_VERR_MINREV_Pos      (0U)
26801 #define SPI_VERR_MINREV_Msk      (0xFU << SPI_VERR_MINREV_Pos)               /*!< 0x0000000F */
26802 #define SPI_VERR_MINREV          SPI_VERR_MINREV_Msk                         /*!< Minor Revision number */
26803 #define SPI_VERR_MAJREV_Pos      (4U)
26804 #define SPI_VERR_MAJREV_Msk      (0xFU << SPI_VERR_MAJREV_Pos)               /*!< 0x000000F0 */
26805 #define SPI_VERR_MAJREV          SPI_VERR_MAJREV_Msk                         /*!< Major Revision number */
26806 
26807 /**********************  Bit definition for SPI_IPIDR register  ****************/
26808 #define SPI_IPIDR_IPID_Pos       (0U)
26809 #define SPI_IPIDR_IPID_Msk       (0xFFFFFFFFU << SPI_IPIDR_IPID_Pos)         /*!< 0xFFFFFFFF */
26810 #define SPI_IPIDR_IPID           SPI_IPIDR_IPID_Msk                          /*!< IP Identification */
26811 
26812 /**********************  Bit definition for SPI_SIDR register  *****************/
26813 #define SPI_SIDR_SID_Pos         (0U)
26814 #define SPI_SIDR_SID_Msk         (0xFFFFFFFFU << SPI_SIDR_SID_Pos)           /*!< 0xFFFFFFFF */
26815 #define SPI_SIDR_SID             SPI_SIDR_SID_Msk                            /*!< IP size identification */
26816 
26817 /******************************************************************************/
26818 /*                                                                            */
26819 /*                                    QUADSPI                                 */
26820 /*                                                                            */
26821 /******************************************************************************/
26822 /*****************  Bit definition for QUADSPI_CR register  *******************/
26823 #define QUADSPI_CR_EN_Pos                (0U)
26824 #define QUADSPI_CR_EN_Msk                (0x1U << QUADSPI_CR_EN_Pos)           /*!< 0x00000001 */
26825 #define QUADSPI_CR_EN                    QUADSPI_CR_EN_Msk                     /*!< Enable */
26826 #define QUADSPI_CR_ABORT_Pos             (1U)
26827 #define QUADSPI_CR_ABORT_Msk             (0x1U << QUADSPI_CR_ABORT_Pos)        /*!< 0x00000002 */
26828 #define QUADSPI_CR_ABORT                 QUADSPI_CR_ABORT_Msk                  /*!< Abort request */
26829 #define QUADSPI_CR_DMAEN_Pos             (2U)
26830 #define QUADSPI_CR_DMAEN_Msk             (0x1U << QUADSPI_CR_DMAEN_Pos)        /*!< 0x00000004 */
26831 #define QUADSPI_CR_DMAEN                 QUADSPI_CR_DMAEN_Msk                  /*!< DMA Enable */
26832 #define QUADSPI_CR_TCEN_Pos              (3U)
26833 #define QUADSPI_CR_TCEN_Msk              (0x1U << QUADSPI_CR_TCEN_Pos)         /*!< 0x00000008 */
26834 #define QUADSPI_CR_TCEN                  QUADSPI_CR_TCEN_Msk                   /*!< Timeout Counter Enable */
26835 #define QUADSPI_CR_SSHIFT_Pos            (4U)
26836 #define QUADSPI_CR_SSHIFT_Msk            (0x1U << QUADSPI_CR_SSHIFT_Pos)       /*!< 0x00000010 */
26837 #define QUADSPI_CR_SSHIFT                QUADSPI_CR_SSHIFT_Msk                 /*!< SSHIFT Sample Shift */
26838 #define QUADSPI_CR_DFM_Pos               (6U)
26839 #define QUADSPI_CR_DFM_Msk               (0x1U << QUADSPI_CR_DFM_Pos)          /*!< 0x00000040 */
26840 #define QUADSPI_CR_DFM                   QUADSPI_CR_DFM_Msk                    /*!< Dual Flash Mode */
26841 #define QUADSPI_CR_FSEL_Pos              (7U)
26842 #define QUADSPI_CR_FSEL_Msk              (0x1U << QUADSPI_CR_FSEL_Pos)         /*!< 0x00000080 */
26843 #define QUADSPI_CR_FSEL                  QUADSPI_CR_FSEL_Msk                   /*!< Flash Select */
26844 #define QUADSPI_CR_FTHRES_Pos            (8U)
26845 #define QUADSPI_CR_FTHRES_Msk            (0xFU << QUADSPI_CR_FTHRES_Pos)       /*!< 0x00000F00 */
26846 #define QUADSPI_CR_FTHRES                QUADSPI_CR_FTHRES_Msk                 /*!< FTHRES[3:0] FIFO Level */
26847 #define QUADSPI_CR_FTHRES_0              (0x1U << QUADSPI_CR_FTHRES_Pos)       /*!< 0x00000100 */
26848 #define QUADSPI_CR_FTHRES_1              (0x2U << QUADSPI_CR_FTHRES_Pos)       /*!< 0x00000200 */
26849 #define QUADSPI_CR_FTHRES_2              (0x4U << QUADSPI_CR_FTHRES_Pos)       /*!< 0x00000400 */
26850 #define QUADSPI_CR_FTHRES_3              (0x8U << QUADSPI_CR_FTHRES_Pos)       /*!< 0x00000800 */
26851 #define QUADSPI_CR_TEIE_Pos              (16U)
26852 #define QUADSPI_CR_TEIE_Msk              (0x1U << QUADSPI_CR_TEIE_Pos)         /*!< 0x00010000 */
26853 #define QUADSPI_CR_TEIE                  QUADSPI_CR_TEIE_Msk                   /*!< Transfer Error Interrupt Enable */
26854 #define QUADSPI_CR_TCIE_Pos              (17U)
26855 #define QUADSPI_CR_TCIE_Msk              (0x1U << QUADSPI_CR_TCIE_Pos)         /*!< 0x00020000 */
26856 #define QUADSPI_CR_TCIE                  QUADSPI_CR_TCIE_Msk                   /*!< Transfer Complete Interrupt Enable */
26857 #define QUADSPI_CR_FTIE_Pos              (18U)
26858 #define QUADSPI_CR_FTIE_Msk              (0x1U << QUADSPI_CR_FTIE_Pos)         /*!< 0x00040000 */
26859 #define QUADSPI_CR_FTIE                  QUADSPI_CR_FTIE_Msk                   /*!< FIFO Threshold Interrupt Enable */
26860 #define QUADSPI_CR_SMIE_Pos              (19U)
26861 #define QUADSPI_CR_SMIE_Msk              (0x1U << QUADSPI_CR_SMIE_Pos)         /*!< 0x00080000 */
26862 #define QUADSPI_CR_SMIE                  QUADSPI_CR_SMIE_Msk                   /*!< Status Match Interrupt Enable */
26863 #define QUADSPI_CR_TOIE_Pos              (20U)
26864 #define QUADSPI_CR_TOIE_Msk              (0x1U << QUADSPI_CR_TOIE_Pos)         /*!< 0x00100000 */
26865 #define QUADSPI_CR_TOIE                  QUADSPI_CR_TOIE_Msk                   /*!< TimeOut Interrupt Enable */
26866 #define QUADSPI_CR_APMS_Pos              (22U)
26867 #define QUADSPI_CR_APMS_Msk              (0x1U << QUADSPI_CR_APMS_Pos)         /*!< 0x00400000 */
26868 #define QUADSPI_CR_APMS                  QUADSPI_CR_APMS_Msk                   /*!< Bit 1 */
26869 #define QUADSPI_CR_PMM_Pos               (23U)
26870 #define QUADSPI_CR_PMM_Msk               (0x1U << QUADSPI_CR_PMM_Pos)          /*!< 0x00800000 */
26871 #define QUADSPI_CR_PMM                   QUADSPI_CR_PMM_Msk                    /*!< Polling Match Mode */
26872 #define QUADSPI_CR_PRESCALER_Pos         (24U)
26873 #define QUADSPI_CR_PRESCALER_Msk         (0xFFU << QUADSPI_CR_PRESCALER_Pos)   /*!< 0xFF000000 */
26874 #define QUADSPI_CR_PRESCALER             QUADSPI_CR_PRESCALER_Msk              /*!< PRESCALER[7:0] Clock prescaler */
26875 #define QUADSPI_CR_PRESCALER_0           (0x01U << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x01000000 */
26876 #define QUADSPI_CR_PRESCALER_1           (0x02U << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x02000000 */
26877 #define QUADSPI_CR_PRESCALER_2           (0x04U << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x04000000 */
26878 #define QUADSPI_CR_PRESCALER_3           (0x08U << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x08000000 */
26879 #define QUADSPI_CR_PRESCALER_4           (0x10U << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x10000000 */
26880 #define QUADSPI_CR_PRESCALER_5           (0x20U << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x20000000 */
26881 #define QUADSPI_CR_PRESCALER_6           (0x40U << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x40000000 */
26882 #define QUADSPI_CR_PRESCALER_7           (0x80U << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x80000000 */
26883 
26884 /*****************  Bit definition for QUADSPI_DCR register  ******************/
26885 #define QUADSPI_DCR_CKMODE_Pos           (0U)
26886 #define QUADSPI_DCR_CKMODE_Msk           (0x1U << QUADSPI_DCR_CKMODE_Pos)      /*!< 0x00000001 */
26887 #define QUADSPI_DCR_CKMODE               QUADSPI_DCR_CKMODE_Msk                /*!< Mode 0 / Mode 3 */
26888 #define QUADSPI_DCR_CSHT_Pos             (8U)
26889 #define QUADSPI_DCR_CSHT_Msk             (0x7U << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000700 */
26890 #define QUADSPI_DCR_CSHT                 QUADSPI_DCR_CSHT_Msk                  /*!< CSHT[2:0]: ChipSelect High Time */
26891 #define QUADSPI_DCR_CSHT_0               (0x1U << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000100 */
26892 #define QUADSPI_DCR_CSHT_1               (0x2U << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000200 */
26893 #define QUADSPI_DCR_CSHT_2               (0x4U << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000400 */
26894 #define QUADSPI_DCR_FSIZE_Pos            (16U)
26895 #define QUADSPI_DCR_FSIZE_Msk            (0x1FU << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x001F0000 */
26896 #define QUADSPI_DCR_FSIZE                QUADSPI_DCR_FSIZE_Msk                 /*!< FSIZE[4:0]: Flash Size */
26897 #define QUADSPI_DCR_FSIZE_0              (0x01U << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00010000 */
26898 #define QUADSPI_DCR_FSIZE_1              (0x02U << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00020000 */
26899 #define QUADSPI_DCR_FSIZE_2              (0x04U << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00040000 */
26900 #define QUADSPI_DCR_FSIZE_3              (0x08U << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00080000 */
26901 #define QUADSPI_DCR_FSIZE_4              (0x10U << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00100000 */
26902 
26903 /******************  Bit definition for QUADSPI_SR register  *******************/
26904 #define QUADSPI_SR_TEF_Pos               (0U)
26905 #define QUADSPI_SR_TEF_Msk               (0x1U << QUADSPI_SR_TEF_Pos)          /*!< 0x00000001 */
26906 #define QUADSPI_SR_TEF                   QUADSPI_SR_TEF_Msk                    /*!< Transfer Error Flag */
26907 #define QUADSPI_SR_TCF_Pos               (1U)
26908 #define QUADSPI_SR_TCF_Msk               (0x1U << QUADSPI_SR_TCF_Pos)          /*!< 0x00000002 */
26909 #define QUADSPI_SR_TCF                   QUADSPI_SR_TCF_Msk                    /*!< Transfer Complete Flag */
26910 #define QUADSPI_SR_FTF_Pos               (2U)
26911 #define QUADSPI_SR_FTF_Msk               (0x1U << QUADSPI_SR_FTF_Pos)          /*!< 0x00000004 */
26912 #define QUADSPI_SR_FTF                   QUADSPI_SR_FTF_Msk                    /*!< FIFO Threshlod Flag */
26913 #define QUADSPI_SR_SMF_Pos               (3U)
26914 #define QUADSPI_SR_SMF_Msk               (0x1U << QUADSPI_SR_SMF_Pos)          /*!< 0x00000008 */
26915 #define QUADSPI_SR_SMF                   QUADSPI_SR_SMF_Msk                    /*!< Status Match Flag */
26916 #define QUADSPI_SR_TOF_Pos               (4U)
26917 #define QUADSPI_SR_TOF_Msk               (0x1U << QUADSPI_SR_TOF_Pos)          /*!< 0x00000010 */
26918 #define QUADSPI_SR_TOF                   QUADSPI_SR_TOF_Msk                    /*!< Timeout Flag */
26919 #define QUADSPI_SR_BUSY_Pos              (5U)
26920 #define QUADSPI_SR_BUSY_Msk              (0x1U << QUADSPI_SR_BUSY_Pos)         /*!< 0x00000020 */
26921 #define QUADSPI_SR_BUSY                  QUADSPI_SR_BUSY_Msk                   /*!< Busy */
26922 #define QUADSPI_SR_FLEVEL_Pos            (8U)
26923 #define QUADSPI_SR_FLEVEL_Msk            (0x1FU << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00001F00 */
26924 #define QUADSPI_SR_FLEVEL                QUADSPI_SR_FLEVEL_Msk                 /*!< FIFO Threshlod Flag */
26925 #define QUADSPI_SR_FLEVEL_0              (0x01U << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000100 */
26926 #define QUADSPI_SR_FLEVEL_1              (0x02U << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000200 */
26927 #define QUADSPI_SR_FLEVEL_2              (0x04U << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000400 */
26928 #define QUADSPI_SR_FLEVEL_3              (0x08U << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000800 */
26929 #define QUADSPI_SR_FLEVEL_4              (0x10U << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00001000 */
26930 
26931 /******************  Bit definition for QUADSPI_FCR register  ******************/
26932 #define QUADSPI_FCR_CTEF_Pos             (0U)
26933 #define QUADSPI_FCR_CTEF_Msk             (0x1U << QUADSPI_FCR_CTEF_Pos)        /*!< 0x00000001 */
26934 #define QUADSPI_FCR_CTEF                 QUADSPI_FCR_CTEF_Msk                  /*!< Clear Transfer Error Flag */
26935 #define QUADSPI_FCR_CTCF_Pos             (1U)
26936 #define QUADSPI_FCR_CTCF_Msk             (0x1U << QUADSPI_FCR_CTCF_Pos)        /*!< 0x00000002 */
26937 #define QUADSPI_FCR_CTCF                 QUADSPI_FCR_CTCF_Msk                  /*!< Clear Transfer Complete Flag */
26938 #define QUADSPI_FCR_CSMF_Pos             (3U)
26939 #define QUADSPI_FCR_CSMF_Msk             (0x1U << QUADSPI_FCR_CSMF_Pos)        /*!< 0x00000008 */
26940 #define QUADSPI_FCR_CSMF                 QUADSPI_FCR_CSMF_Msk                  /*!< Clear Status Match Flag */
26941 #define QUADSPI_FCR_CTOF_Pos             (4U)
26942 #define QUADSPI_FCR_CTOF_Msk             (0x1U << QUADSPI_FCR_CTOF_Pos)        /*!< 0x00000010 */
26943 #define QUADSPI_FCR_CTOF                 QUADSPI_FCR_CTOF_Msk                  /*!< Clear Timeout Flag */
26944 
26945 /******************  Bit definition for QUADSPI_DLR register  ******************/
26946 #define QUADSPI_DLR_DL_Pos               (0U)
26947 #define QUADSPI_DLR_DL_Msk               (0xFFFFFFFFU << QUADSPI_DLR_DL_Pos)   /*!< 0xFFFFFFFF */
26948 #define QUADSPI_DLR_DL                   QUADSPI_DLR_DL_Msk                    /*!< DL[31:0]: Data Length */
26949 
26950 /******************  Bit definition for QUADSPI_CCR register  ******************/
26951 #define QUADSPI_CCR_INSTRUCTION_Pos      (0U)
26952 #define QUADSPI_CCR_INSTRUCTION_Msk      (0xFFU << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
26953 #define QUADSPI_CCR_INSTRUCTION          QUADSPI_CCR_INSTRUCTION_Msk           /*!< INSTRUCTION[7:0]: Instruction */
26954 #define QUADSPI_CCR_INSTRUCTION_0        (0x01U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */
26955 #define QUADSPI_CCR_INSTRUCTION_1        (0x02U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */
26956 #define QUADSPI_CCR_INSTRUCTION_2        (0x04U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */
26957 #define QUADSPI_CCR_INSTRUCTION_3        (0x08U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */
26958 #define QUADSPI_CCR_INSTRUCTION_4        (0x10U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */
26959 #define QUADSPI_CCR_INSTRUCTION_5        (0x20U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */
26960 #define QUADSPI_CCR_INSTRUCTION_6        (0x40U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */
26961 #define QUADSPI_CCR_INSTRUCTION_7        (0x80U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */
26962 #define QUADSPI_CCR_IMODE_Pos            (8U)
26963 #define QUADSPI_CCR_IMODE_Msk            (0x3U << QUADSPI_CCR_IMODE_Pos)       /*!< 0x00000300 */
26964 #define QUADSPI_CCR_IMODE                QUADSPI_CCR_IMODE_Msk                 /*!< IMODE[1:0]: Instruction Mode */
26965 #define QUADSPI_CCR_IMODE_0              (0x1U << QUADSPI_CCR_IMODE_Pos)       /*!< 0x00000100 */
26966 #define QUADSPI_CCR_IMODE_1              (0x2U << QUADSPI_CCR_IMODE_Pos)       /*!< 0x00000200 */
26967 #define QUADSPI_CCR_ADMODE_Pos           (10U)
26968 #define QUADSPI_CCR_ADMODE_Msk           (0x3U << QUADSPI_CCR_ADMODE_Pos)      /*!< 0x00000C00 */
26969 #define QUADSPI_CCR_ADMODE               QUADSPI_CCR_ADMODE_Msk                /*!< ADMODE[1:0]: Address Mode */
26970 #define QUADSPI_CCR_ADMODE_0             (0x1U << QUADSPI_CCR_ADMODE_Pos)      /*!< 0x00000400 */
26971 #define QUADSPI_CCR_ADMODE_1             (0x2U << QUADSPI_CCR_ADMODE_Pos)      /*!< 0x00000800 */
26972 #define QUADSPI_CCR_ADSIZE_Pos           (12U)
26973 #define QUADSPI_CCR_ADSIZE_Msk           (0x3U << QUADSPI_CCR_ADSIZE_Pos)      /*!< 0x00003000 */
26974 #define QUADSPI_CCR_ADSIZE               QUADSPI_CCR_ADSIZE_Msk                /*!< ADSIZE[1:0]: Address Size */
26975 #define QUADSPI_CCR_ADSIZE_0             (0x1U << QUADSPI_CCR_ADSIZE_Pos)      /*!< 0x00001000 */
26976 #define QUADSPI_CCR_ADSIZE_1             (0x2U << QUADSPI_CCR_ADSIZE_Pos)      /*!< 0x00002000 */
26977 #define QUADSPI_CCR_ABMODE_Pos           (14U)
26978 #define QUADSPI_CCR_ABMODE_Msk           (0x3U << QUADSPI_CCR_ABMODE_Pos)      /*!< 0x0000C000 */
26979 #define QUADSPI_CCR_ABMODE               QUADSPI_CCR_ABMODE_Msk                /*!< ABMODE[1:0]: Alternate Bytes Mode */
26980 #define QUADSPI_CCR_ABMODE_0             (0x1U << QUADSPI_CCR_ABMODE_Pos)      /*!< 0x00004000 */
26981 #define QUADSPI_CCR_ABMODE_1             (0x2U << QUADSPI_CCR_ABMODE_Pos)      /*!< 0x00008000 */
26982 #define QUADSPI_CCR_ABSIZE_Pos           (16U)
26983 #define QUADSPI_CCR_ABSIZE_Msk           (0x3U << QUADSPI_CCR_ABSIZE_Pos)      /*!< 0x00030000 */
26984 #define QUADSPI_CCR_ABSIZE               QUADSPI_CCR_ABSIZE_Msk                /*!< ABSIZE[1:0]: Instruction Mode */
26985 #define QUADSPI_CCR_ABSIZE_0             (0x1U << QUADSPI_CCR_ABSIZE_Pos)      /*!< 0x00010000 */
26986 #define QUADSPI_CCR_ABSIZE_1             (0x2U << QUADSPI_CCR_ABSIZE_Pos)      /*!< 0x00020000 */
26987 #define QUADSPI_CCR_DCYC_Pos             (18U)
26988 #define QUADSPI_CCR_DCYC_Msk             (0x1FU << QUADSPI_CCR_DCYC_Pos)       /*!< 0x007C0000 */
26989 #define QUADSPI_CCR_DCYC                 QUADSPI_CCR_DCYC_Msk                  /*!< DCYC[4:0]: Dummy Cycles */
26990 #define QUADSPI_CCR_DCYC_0               (0x01U << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00040000 */
26991 #define QUADSPI_CCR_DCYC_1               (0x02U << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00080000 */
26992 #define QUADSPI_CCR_DCYC_2               (0x04U << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00100000 */
26993 #define QUADSPI_CCR_DCYC_3               (0x08U << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00200000 */
26994 #define QUADSPI_CCR_DCYC_4               (0x10U << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00400000 */
26995 #define QUADSPI_CCR_DMODE_Pos            (24U)
26996 #define QUADSPI_CCR_DMODE_Msk            (0x3U << QUADSPI_CCR_DMODE_Pos)       /*!< 0x03000000 */
26997 #define QUADSPI_CCR_DMODE                QUADSPI_CCR_DMODE_Msk                 /*!< DMODE[1:0]: Data Mode */
26998 #define QUADSPI_CCR_DMODE_0              (0x1U << QUADSPI_CCR_DMODE_Pos)       /*!< 0x01000000 */
26999 #define QUADSPI_CCR_DMODE_1              (0x2U << QUADSPI_CCR_DMODE_Pos)       /*!< 0x02000000 */
27000 #define QUADSPI_CCR_FMODE_Pos            (26U)
27001 #define QUADSPI_CCR_FMODE_Msk            (0x3U << QUADSPI_CCR_FMODE_Pos)       /*!< 0x0C000000 */
27002 #define QUADSPI_CCR_FMODE                QUADSPI_CCR_FMODE_Msk                 /*!< FMODE[1:0]: Functional Mode */
27003 #define QUADSPI_CCR_FMODE_0              (0x1U << QUADSPI_CCR_FMODE_Pos)       /*!< 0x04000000 */
27004 #define QUADSPI_CCR_FMODE_1              (0x2U << QUADSPI_CCR_FMODE_Pos)       /*!< 0x08000000 */
27005 #define QUADSPI_CCR_SIOO_Pos             (28U)
27006 #define QUADSPI_CCR_SIOO_Msk             (0x1U << QUADSPI_CCR_SIOO_Pos)        /*!< 0x10000000 */
27007 #define QUADSPI_CCR_SIOO                 QUADSPI_CCR_SIOO_Msk                  /*!< SIOO: Send Instruction Only Once Mode */
27008 #define QUADSPI_CCR_DHHC_Pos             (30U)
27009 #define QUADSPI_CCR_DHHC_Msk             (0x1U << QUADSPI_CCR_DHHC_Pos)        /*!< 0x40000000 */
27010 #define QUADSPI_CCR_DHHC                 QUADSPI_CCR_DHHC_Msk                  /*!< DHHC: DDR hold half cycle */
27011 #define QUADSPI_CCR_DDRM_Pos             (31U)
27012 #define QUADSPI_CCR_DDRM_Msk             (0x1U << QUADSPI_CCR_DDRM_Pos)        /*!< 0x80000000 */
27013 #define QUADSPI_CCR_DDRM                 QUADSPI_CCR_DDRM_Msk                  /*!< DDRM: Double Data Rate Mode */
27014 
27015 /******************  Bit definition for QUADSPI_AR register  *******************/
27016 #define QUADSPI_AR_ADDRESS_Pos           (0U)
27017 #define QUADSPI_AR_ADDRESS_Msk           (0xFFFFFFFFU << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
27018 #define QUADSPI_AR_ADDRESS               QUADSPI_AR_ADDRESS_Msk                /*!< ADDRESS[31:0]: Address */
27019 
27020 /******************  Bit definition for QUADSPI_ABR register  ******************/
27021 #define QUADSPI_ABR_ALTERNATE_Pos        (0U)
27022 #define QUADSPI_ABR_ALTERNATE_Msk        (0xFFFFFFFFU << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
27023 #define QUADSPI_ABR_ALTERNATE            QUADSPI_ABR_ALTERNATE_Msk             /*!< ALTERNATE[31:0]: Alternate Bytes */
27024 
27025 /******************  Bit definition for QUADSPI_DR register  *******************/
27026 #define QUADSPI_DR_DATA_Pos              (0U)
27027 #define QUADSPI_DR_DATA_Msk              (0xFFFFFFFFU << QUADSPI_DR_DATA_Pos)  /*!< 0xFFFFFFFF */
27028 #define QUADSPI_DR_DATA                  QUADSPI_DR_DATA_Msk                   /*!< DATA[31:0]: Data */
27029 
27030 /******************  Bit definition for QUADSPI_PSMKR register  ****************/
27031 #define QUADSPI_PSMKR_MASK_Pos           (0U)
27032 #define QUADSPI_PSMKR_MASK_Msk           (0xFFFFFFFFU << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
27033 #define QUADSPI_PSMKR_MASK               QUADSPI_PSMKR_MASK_Msk                /*!< MASK[31:0]: Status Mask */
27034 
27035 /******************  Bit definition for QUADSPI_PSMAR register  ****************/
27036 #define QUADSPI_PSMAR_MATCH_Pos          (0U)
27037 #define QUADSPI_PSMAR_MATCH_Msk          (0xFFFFFFFFU << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
27038 #define QUADSPI_PSMAR_MATCH              QUADSPI_PSMAR_MATCH_Msk               /*!< MATCH[31:0]: Status Match */
27039 
27040 /******************  Bit definition for QUADSPI_PIR register  *****************/
27041 #define QUADSPI_PIR_INTERVAL_Pos         (0U)
27042 #define QUADSPI_PIR_INTERVAL_Msk         (0xFFFFU << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
27043 #define QUADSPI_PIR_INTERVAL             QUADSPI_PIR_INTERVAL_Msk              /*!< INTERVAL[15:0]: Polling Interval */
27044 
27045 /******************  Bit definition for QUADSPI_LPTR register  *****************/
27046 #define QUADSPI_LPTR_TIMEOUT_Pos         (0U)
27047 #define QUADSPI_LPTR_TIMEOUT_Msk         (0xFFFFU << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
27048 #define QUADSPI_LPTR_TIMEOUT             QUADSPI_LPTR_TIMEOUT_Msk              /*!< TIMEOUT[15:0]: Timeout period */
27049 
27050 /**********************  Bit definition for QUADSPI_HWCFGR register  ***************/
27051 #define QUADSPI_HWCFGR_FIFOSIZE_Pos   (0U)
27052 #define QUADSPI_HWCFGR_FIFOSIZE_Msk   (0xFU << QUADSPI_HWCFGR_FIFOSIZE_Pos)           /*!< 0x0000000F */
27053 #define QUADSPI_HWCFGR_FIFOSIZE        QUADSPI_HWCFGR_FIFOSIZE_Msk                     /*!< size of FIFO in words */
27054 #define QUADSPI_HWCFGR_IDLENGTH_Pos   (4U)
27055 #define QUADSPI_HWCFGR_IDLENGTH_Msk   (0xFU << QUADSPI_HWCFGR_IDLENGTH_Pos)           /*!< 0x0000000F */
27056 #define QUADSPI_HWCFGR_IDLENGTH        QUADSPI_HWCFGR_IDLENGTH_Msk                     /*!< size in bit of the FIFO pointer */
27057 #define QUADSPI_HWCFGR_PRESCVAL_Pos    (8U)
27058 #define QUADSPI_HWCFGR_PRESCVAL_Msk   (0xFU << QUADSPI_HWCFGR_PRESCVAL_Pos)           /*!< 0x0000000F */
27059 #define QUADSPI_HWCFGR_PRESCVAL        QUADSPI_HWCFGR_PRESCVAL_Msk                     /*!< reset value of the prescaler */
27060 #define QUADSPI_HWCFGR_IDLENGTH_Pos   (4U)
27061 #define QUADSPI_HWCFGR_IDLENGTH_Msk   (0xFU << QUADSPI_HWCFGR_IDLENGTH_Pos)           /*!< 0x0000000F */
27062 #define QUADSPI_HWCFGR_IDLENGTH        QUADSPI_HWCFGR_IDLENGTH_Msk                     /*!< length of the AXI IDs. */
27063 
27064 /**********************  Bit definition for QUADSPI_VERR register  *****************/
27065 #define QUADSPI_VERR_MINREV_Pos      (0U)
27066 #define QUADSPI_VERR_MINREV_Msk      (0xFU << QUADSPI_VERR_MINREV_Pos)               /*!< 0x0000000F */
27067 #define QUADSPI_VERR_MINREV          QUADSPI_VERR_MINREV_Msk                         /*!< Minor Revision number */
27068 #define QUADSPI_VERR_MAJREV_Pos      (4U)
27069 #define QUADSPI_VERR_MAJREV_Msk      (0xFU << QUADSPI_VERR_MAJREV_Pos)               /*!< 0x000000F0 */
27070 #define QUADSPI_VERR_MAJREV          QUADSPI_VERR_MAJREV_Msk                         /*!< Major Revision number */
27071 
27072 /**********************  Bit definition for QUADSPI_IPIDR register  ****************/
27073 #define QUADSPI_IPIDR_ID_Pos       (0U)
27074 #define QUADSPI_IPIDR_ID_Msk       (0xFFFFFFFFU << QUADSPI_IPIDR_ID_Pos)         /*!< 0xFFFFFFFF */
27075 #define QUADSPI_IPIDR_ID           QUADSPI_IPIDR_ID_Msk                          /*!< IP Identification */
27076 
27077 /**********************  Bit definition for QUADSPI_SIDR register  *****************/
27078 #define QUADSPI_SIDR_SID_Pos         (0U)
27079 #define QUADSPI_SIDR_SID_Msk         (0xFFFFFFFFU << QUADSPI_SIDR_SID_Pos)           /*!< 0xFFFFFFFF */
27080 #define QUADSPI_SIDR_SID             QUADSPI_SIDR_SID_Msk                            /*!< IP size identification */
27081 
27082 /******************************************************************************/
27083 /*                                                                            */
27084 /*                                 SYSCFG                                     */
27085 /*                                                                            */
27086 /******************************************************************************/
27087 /******************  Bit definition for SYSCFG_BOOTR register  *****************/
27088 #define SYSCFG_BOOTR_BOOT0_Pos               (0U)
27089 #define SYSCFG_BOOTR_BOOT0_Msk               (0x1U << SYSCFG_BOOTR_BOOT0_Pos)  /*!< 0x00000001 */
27090 #define SYSCFG_BOOTR_BOOT0                   SYSCFG_BOOTR_BOOT0_Msk            /*!< BOOT0 pin value */
27091 #define SYSCFG_BOOTR_BOOT1_Pos               (1U)
27092 #define SYSCFG_BOOTR_BOOT1_Msk               (0x1U << SYSCFG_BOOTR_BOOT1_Pos)  /*!< 0x00000002 */
27093 #define SYSCFG_BOOTR_BOOT1                   SYSCFG_BOOTR_BOOT1_Msk            /*!< BOOT1 pin value */
27094 #define SYSCFG_BOOTR_BOOT2_Pos               (2U)
27095 #define SYSCFG_BOOTR_BOOT2_Msk               (0x1U << SYSCFG_BOOTR_BOOT2_Pos)  /*!< 0x00000004 */
27096 #define SYSCFG_BOOTR_BOOT2                   SYSCFG_BOOTR_BOOT2_Msk            /*!< BOOT2 pin value */
27097 #define SYSCFG_BOOTR_BOOT0_PD_Pos            (4U)
27098 #define SYSCFG_BOOTR_BOOT0_PD_Msk            (0x1U << SYSCFG_BOOTR_BOOT0_PD_Pos) /*!< 0x00000010 */
27099 #define SYSCFG_BOOTR_BOOT0_PD                SYSCFG_BOOTR_BOOT0_PD_Msk         /*!< BOOT0 pin pull-down disable */
27100 #define SYSCFG_BOOTR_BOOT1_PD_Pos            (5U)
27101 #define SYSCFG_BOOTR_BOOT1_PD_Msk            (0x1U << SYSCFG_BOOTR_BOOT1_PD_Pos) /*!< 0x00000020 */
27102 #define SYSCFG_BOOTR_BOOT1_PD                SYSCFG_BOOTR_BOOT1_PD_Msk         /*!< BOOT1 pin pull-down disable */
27103 #define SYSCFG_BOOTR_BOOT2_PD_Pos            (6U)
27104 #define SYSCFG_BOOTR_BOOT2_PD_Msk            (0x1U << SYSCFG_BOOTR_BOOT2_PD_Pos) /*!< 0x00000040 */
27105 #define SYSCFG_BOOTR_BOOT2_PD                SYSCFG_BOOTR_BOOT2_PD_Msk         /*!< BOOT2 pin pull-down disable */
27106 
27107 
27108 /******************  Bit definition for SYSCFG_PMCSETR register  ******************/
27109 #define SYSCFG_PMCSETR_I2C1_FMP_Pos     (0U)
27110 #define SYSCFG_PMCSETR_I2C1_FMP_Msk     (0x1U << SYSCFG_PMCSETR_I2C1_FMP_Pos)        /*!< 0x00000001 */
27111 #define SYSCFG_PMCSETR_I2C1_FMP         SYSCFG_PMCSETR_I2C1_FMP_Msk                  /*!< I2C1 Fast mode plus */
27112 #define SYSCFG_PMCSETR_I2C2_FMP_Pos     (1U)
27113 #define SYSCFG_PMCSETR_I2C2_FMP_Msk     (0x1U << SYSCFG_PMCSETR_I2C2_FMP_Pos)        /*!< 0x00000002 */
27114 #define SYSCFG_PMCSETR_I2C2_FMP         SYSCFG_PMCSETR_I2C2_FMP_Msk                  /*!< I2C2 Fast mode plus */
27115 #define SYSCFG_PMCSETR_I2C3_FMP_Pos     (2U)
27116 #define SYSCFG_PMCSETR_I2C3_FMP_Msk     (0x1U << SYSCFG_PMCSETR_I2C3_FMP_Pos)        /*!< 0x00000004 */
27117 #define SYSCFG_PMCSETR_I2C3_FMP         SYSCFG_PMCSETR_I2C3_FMP_Msk                  /*!< I2C3 Fast mode plus */
27118 #define SYSCFG_PMCSETR_I2C4_FMP_Pos     (3U)
27119 #define SYSCFG_PMCSETR_I2C4_FMP_Msk     (0x1U << SYSCFG_PMCSETR_I2C4_FMP_Pos)        /*!< 0x00000008 */
27120 #define SYSCFG_PMCSETR_I2C4_FMP         SYSCFG_PMCSETR_I2C4_FMP_Msk                  /*!< I2C4 Fast mode plus */
27121 #define SYSCFG_PMCSETR_I2C5_FMP_Pos     (4U)
27122 #define SYSCFG_PMCSETR_I2C5_FMP_Msk     (0x1U << SYSCFG_PMCSETR_I2C5_FMP_Pos)        /*!< 0x00000010 */
27123 #define SYSCFG_PMCSETR_I2C5_FMP         SYSCFG_PMCSETR_I2C5_FMP_Msk                  /*!< I2C5 Fast mode plus */
27124 #define SYSCFG_PMCSETR_I2C6_FMP_Pos     (5U)
27125 #define SYSCFG_PMCSETR_I2C6_FMP_Msk     (0x1U << SYSCFG_PMCSETR_I2C6_FMP_Pos)        /*!< 0x00000020 */
27126 #define SYSCFG_PMCSETR_I2C6_FMP         SYSCFG_PMCSETR_I2C6_FMP_Msk                  /*!< I2C6 Fast mode plus */
27127 
27128 #define SYSCFG_PMCSETR_EN_BOOSTER_Pos     (8U)
27129 #define SYSCFG_PMCSETR_EN_BOOSTER_Msk     (0x1U << SYSCFG_PMCSETR_EN_BOOSTER_Pos)         /*!< 0x00000100 */
27130 #define SYSCFG_PMCSETR_EN_BOOSTER          SYSCFG_PMCSETR_EN_BOOSTER_Msk                   /*!< I/O analog switch voltage booster enable */
27131 
27132 #define SYSCFG_PMCSETR_ANASWVDD_Pos     (9U)
27133 #define SYSCFG_PMCSETR_ANASWVDD_Msk     (0x1U << SYSCFG_PMCSETR_ANASWVDD_Pos)         /*!< 0x00000200 */
27134 #define SYSCFG_PMCSETR_ANASWVDD         SYSCFG_PMCSETR_ANASWVDD_Msk                   /*!< GPIO analog switches control voltage selection */
27135 
27136 #define SYSCFG_PMCSETR_ETH_CLK_SEL_Pos         (16U)
27137 #define SYSCFG_PMCSETR_ETH_CLK_SEL_Msk         (0x1U << SYSCFG_PMCSETR_ETH_CLK_SEL_Pos)           /*!< 0x00010000 */
27138 #define SYSCFG_PMCSETR_ETH_CLK_SEL             SYSCFG_PMCSETR_ETH_CLK_SEL_Msk                     /*!< Internal clock ETH_CLK1 from RCC is used regardless AFMux */
27139 #define SYSCFG_PMCSETR_ETH_REF_CLK_SEL_Pos     (17U)
27140 #define SYSCFG_PMCSETR_ETH_REF_CLK_SEL_Msk     (0x1U << SYSCFG_PMCSETR_ETH_REF_CLK_SEL_Pos)       /*!< 0x00020000 */
27141 #define SYSCFG_PMCSETR_ETH_REF_CLK_SEL         SYSCFG_PMCSETR_ETH_REF_CLK_SEL_Msk                 /*!< Ethernet 50MHz RMII clock selection */
27142 #define SYSCFG_PMCSETR_ETH_SELMII_Pos          (20U)
27143 #define SYSCFG_PMCSETR_ETH_SELMII_Msk          (0x1U << SYSCFG_PMCSETR_ETH_SELMII_Pos)            /*!< 0x00100000 */
27144 #define SYSCFG_PMCSETR_ETH_SELMII_SEL          SYSCFG_PMCSETR_ETH_SELMII_Msk                      /*!< controls MII or GMII when ETH_SEL[2:0] = 0b000 */
27145 #define SYSCFG_PMCSETR_ETH_SEL_Pos             (21U)
27146 #define SYSCFG_PMCSETR_ETH_SEL_Msk             (0x7U << SYSCFG_PMCSETR_ETH_SEL_Pos)               /*!< 0x00E00000 */
27147 #define SYSCFG_PMCSETR_ETH_SEL                 SYSCFG_PMCSETR_ETH_SEL_Msk                         /*!< Ethernet PHY Interface Selection */
27148 #define SYSCFG_PMCSETR_ETH_SEL_0               (0x1U << SYSCFG_PMCSETR_ETH_SEL_Pos)               /*!< 0x00200000 */
27149 #define SYSCFG_PMCSETR_ETH_SEL_1               (0x2U << SYSCFG_PMCSETR_ETH_SEL_Pos)               /*!< 0x00400000 */
27150 #define SYSCFG_PMCSETR_ETH_SEL_2               (0x4U << SYSCFG_PMCSETR_ETH_SEL_Pos)               /*!< 0x00800000 */
27151 #define SYSCFG_PMCSETR_ETH_SEL_CONF_Pos        (20U)
27152 #define SYSCFG_PMCSETR_ETH_SEL_CONF_Msk        (0xFU << SYSCFG_PMCSETR_ETH_SEL_CONF_Pos)         /*!< 0x00F00000 */
27153 #define SYSCFG_PMCSETR_ETH_SEL_CONF            SYSCFG_PMCSETR_ETH_SEL_CONF_Msk                    /*!< Ethernet PHY Interface Configuration */
27154 
27155 #define SYSCFG_PMCSETR_ANA0_SEL_Pos            (24U)
27156 #define SYSCFG_PMCSETR_ANA0_SEL_Msk            (0x1U << SYSCFG_PMCSETR_ANA0_SEL_Pos)              /*!< 0x01000000 */
27157 #define SYSCFG_PMCSETR_ANA0_SEL_SEL             SYSCFG_PMCSETR_ANA0_SEL_Msk                       /*!< controls analog connection between ANA0 and PA0 pin */
27158 #define SYSCFG_PMCSETR_ANA1_SEL_Pos            (25U)
27159 #define SYSCFG_PMCSETR_ANA1_SEL_Msk            (0x1U << SYSCFG_PMCSETR_ANA1_SEL_Pos)              /*!< 0x02000000 */
27160 #define SYSCFG_PMCSETR_ANA1_SEL_SEL            SYSCFG_PMCSETR_ANA1_SEL_Msk                       /*!< controls analog connection between ANA1 and PA1 pin */
27161 
27162 /******************  Bit definition for SYSCFG_PMCCLRR register  ******************/
27163 #define SYSCFG_PMCCLRR_I2C1_FMP_Pos     (0U)
27164 #define SYSCFG_PMCCLRR_I2C1_FMP_Msk     (0x1U << SYSCFG_PMCCLRR_I2C1_FMP_Pos)        /*!< 0x00000001 */
27165 #define SYSCFG_PMCCLRR_I2C1_FMP         SYSCFG_PMCCLRR_I2C1_FMP_Msk                  /*!< I2C1 Fast mode plus */
27166 #define SYSCFG_PMCCLRR_I2C2_FMP_Pos     (1U)
27167 #define SYSCFG_PMCCLRR_I2C2_FMP_Msk     (0x1U << SYSCFG_PMCCLRR_I2C2_FMP_Pos)        /*!< 0x00000002 */
27168 #define SYSCFG_PMCCLRR_I2C2_FMP         SYSCFG_PMCCLRR_I2C2_FMP_Msk                  /*!< I2C2 Fast mode plus */
27169 #define SYSCFG_PMCCLRR_I2C3_FMP_Pos     (2U)
27170 #define SYSCFG_PMCCLRR_I2C3_FMP_Msk     (0x1U << SYSCFG_PMCCLRR_I2C3_FMP_Pos)        /*!< 0x00000004 */
27171 #define SYSCFG_PMCCLRR_I2C3_FMP         SYSCFG_PMCCLRR_I2C3_FMP_Msk                  /*!< I2C3 Fast mode plus */
27172 #define SYSCFG_PMCCLRR_I2C4_FMP_Pos     (3U)
27173 #define SYSCFG_PMCCLRR_I2C4_FMP_Msk     (0x1U << SYSCFG_PMCCLRR_I2C4_FMP_Pos)        /*!< 0x00000008 */
27174 #define SYSCFG_PMCCLRR_I2C4_FMP         SYSCFG_PMCCLRR_I2C4_FMP_Msk                  /*!< I2C4 Fast mode plus */
27175 #define SYSCFG_PMCCLRR_I2C5_FMP_Pos     (4U)
27176 #define SYSCFG_PMCCLRR_I2C5_FMP_Msk     (0x1U << SYSCFG_PMCCLRR_I2C5_FMP_Pos)        /*!< 0x00000010 */
27177 #define SYSCFG_PMCCLRR_I2C5_FMP         SYSCFG_PMCCLRR_I2C5_FMP_Msk                  /*!< I2C5 Fast mode plus */
27178 #define SYSCFG_PMCCLRR_I2C6_FMP_Pos     (5U)
27179 #define SYSCFG_PMCCLRR_I2C6_FMP_Msk     (0x1U << SYSCFG_PMCCLRR_I2C6_FMP_Pos)        /*!< 0x00000020 */
27180 #define SYSCFG_PMCCLRR_I2C6_FMP         SYSCFG_PMCCLRR_I2C6_FMP_Msk                  /*!< I2C6 Fast mode plus */
27181 
27182 #define SYSCFG_PMCCLRR_EN_BOOSTER_Pos     (8U)
27183 #define SYSCFG_PMCCLRR_EN_BOOSTER_Msk     (0x1U << SYSCFG_PMCCLRR_EN_BOOSTER_Pos)         /*!< 0x00000100 */
27184 #define SYSCFG_PMCCLRR_EN_BOOSTER          SYSCFG_PMCCLRR_EN_BOOSTER_Msk                   /*!< I/O analog switch voltage booster enable */
27185 
27186 #define SYSCFG_PMCCLRR_ANASWVDD_Pos     (9U)
27187 #define SYSCFG_PMCCLRR_ANASWVDD_Msk     (0x1U << SYSCFG_PMCCLRR_ANASWVDD_Pos)         /*!< 0x00000200 */
27188 #define SYSCFG_PMCCLRR_ANASWVDD         SYSCFG_PMCCLRR_ANASWVDD_Msk                   /*!< GPIO analog switches control voltage selection */
27189 
27190 #define SYSCFG_PMCCLRR_ETH_CLK_SEL_Pos         (16U)
27191 #define SYSCFG_PMCCLRR_ETH_CLK_SEL_Msk         (0x1U << SYSCFG_PMCCLRR_ETH_CLK_SEL_Pos)           /*!< 0x00010000 */
27192 #define SYSCFG_PMCCLRR_ETH_CLK_SEL             SYSCFG_PMCCLRR_ETH_CLK_SEL_Msk                     /*!< Internal clock ETH_CLK1 from RCC is used regardless AFMux */
27193 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos     (17U)
27194 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Msk     (0x1U << SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos)       /*!< 0x00020000 */
27195 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL         SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Msk                 /*!< Ethernet 50MHz RMII clock selection */
27196 #define SYSCFG_PMCCLRR_ETH_SELMII_Pos          (20U)
27197 #define SYSCFG_PMCCLRR_ETH_SELMII_Msk          (0x1U << SYSCFG_PMCCLRR_ETH_SELMII_Pos)            /*!< 0x00100000 */
27198 #define SYSCFG_PMCCLRR_ETH_SELMII_SEL          SYSCFG_PMCCLRR_ETH_SELMII_Msk                      /*!< controls MII or GMII when ETH_SEL[2:0] = 0b000 */
27199 #define SYSCFG_PMCCLRR_ETH_SEL_Pos             (21U)
27200 #define SYSCFG_PMCCLRR_ETH_SEL_Msk             (0x7U << SYSCFG_PMCCLRR_ETH_SEL_Pos)               /*!< 0x00E00000 */
27201 #define SYSCFG_PMCCLRR_ETH_SEL                 SYSCFG_PMCCLRR_ETH_SEL_Msk                         /*!< Ethernet PHY Interface Selection */
27202 #define SYSCFG_PMCCLRR_ETH_SEL_0               (0x1U << SYSCFG_PMCCLRR_ETH_SEL_Pos)               /*!< 0x00200000 */
27203 #define SYSCFG_PMCCLRR_ETH_SEL_1               (0x2U << SYSCFG_PMCCLRR_ETH_SEL_Pos)               /*!< 0x00400000 */
27204 #define SYSCFG_PMCCLRR_ETH_SEL_2               (0x4U << SYSCFG_PMCCLRR_ETH_SEL_Pos)               /*!< 0x00800000 */
27205 #define SYSCFG_PMCCLRR_ETH_SEL_CONF_Pos        (20U)
27206 #define SYSCFG_PMCCLRR_ETH_SEL_CONF_Msk        (0xFU << SYSCFG_PMCCLRR_ETH_SEL_CONF_Pos)          /*!< 0x00F00000 */
27207 #define SYSCFG_PMCCLRR_ETH_SEL_CONF            SYSCFG_PMCCLRR_ETH_SEL_CONF_Msk                   /*!< Ethernet PHY Interface Configuration */
27208 
27209 #define SYSCFG_PMCCLRR_ANA0_SEL_Pos            (24U)
27210 #define SYSCFG_PMCCLRR_ANA0_SEL_Msk            (0x1U << SYSCFG_PMCCLRR_ANA0_SEL_Pos)              /*!< 0x01000000 */
27211 #define SYSCFG_PMCCLRR_ANA0_SEL_SEL             SYSCFG_PMCCLRR_ANA0_SEL_Msk                       /*!< controls analog connection between ANA0 and PA0 pin */
27212 #define SYSCFG_PMCCLRR_ANA1_SEL_Pos            (25U)
27213 #define SYSCFG_PMCCLRR_ANA1_SEL_Msk            (0x1U << SYSCFG_PMCCLRR_ANA1_SEL_Pos)              /*!< 0x02000000 */
27214 #define SYSCFG_PMCCLRR_ANA1_SEL_SEL            SYSCFG_PMCCLRR_ANA1_SEL_Msk                       /*!< controls analog connection between ANA1 and PA1 pin */
27215 
27216 /******************  Bit definition for SYSCFG_IOCTRLSETR register  *****************/
27217 #define SYSCFG_IOCTRLSETR_HSLVEN_TRACE_Pos      (0U)
27218 #define SYSCFG_IOCTRLSETR_HSLVEN_TRACE_Msk      (0x1U << SYSCFG_IOCTRLSETR_HSLVEN_TRACE_Pos) /*!< 0x00000001 */
27219 #define SYSCFG_IOCTRLSETR_HSLVEN_TRACE          SYSCFG_IOCTRLSETR_HSLVEN_TRACE_Msk   /*!< High Speed Low Voltage Pad mode Enable */
27220 #define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI_Pos    (1U)
27221 #define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI_Msk    (0x1U << SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI_Pos) /*!< 0x00000002 */
27222 #define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI        SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI_Msk /*!< High Speed Low Voltage Pad mode Enable */
27223 #define SYSCFG_IOCTRLSETR_HSLVEN_ETH_Pos        (2U)
27224 #define SYSCFG_IOCTRLSETR_HSLVEN_ETH_Msk        (0x1U << SYSCFG_IOCTRLSETR_HSLVEN_ETH_Pos) /*!< 0x00000004 */
27225 #define SYSCFG_IOCTRLSETR_HSLVEN_ETH            SYSCFG_IOCTRLSETR_HSLVEN_ETH_Msk     /*!< High Speed Low Voltage Pad mode Enable */
27226 #define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC_Pos      (3U)
27227 #define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC_Msk      (0x1U << SYSCFG_IOCTRLSETR_HSLVEN_SDMMC_Pos) /*!< 0x00000008 */
27228 #define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC          SYSCFG_IOCTRLSETR_HSLVEN_SDMMC_Msk   /*!< High Speed Low Voltage Pad mode Enable */
27229 #define SYSCFG_IOCTRLSETR_HSLVEN_SPI_Pos        (4U)
27230 #define SYSCFG_IOCTRLSETR_HSLVEN_SPI_Msk        (0x1U << SYSCFG_IOCTRLSETR_HSLVEN_SPI_Pos) /*!< 0x00000010 */
27231 #define SYSCFG_IOCTRLSETR_HSLVEN_SPI            SYSCFG_IOCTRLSETR_HSLVEN_SPI_Msk     /*!< High Speed Low Voltage Pad mode Enable */
27232 
27233 /******************  Bit definition for SYSCFG_IOCTRLCLRR register  *****************/
27234 #define SYSCFG_IOCTRLCLRR_HSLVEN_TRACE_Pos      (0U)
27235 #define SYSCFG_IOCTRLCLRR_HSLVEN_TRACE_Msk      (0x1U << SYSCFG_IOCTRLCLRR_HSLVEN_TRACE_Pos) /*!< 0x00000001 */
27236 #define SYSCFG_IOCTRLCLRR_HSLVEN_TRACE          SYSCFG_IOCTRLCLRR_HSLVEN_TRACE_Msk   /*!< High Speed Low Voltage Pad mode Enable */
27237 #define SYSCFG_IOCTRLCLRR_HSLVEN_QUADSPI_Pos    (1U)
27238 #define SYSCFG_IOCTRLCLRR_HSLVEN_QUADSPI_Msk    (0x1U << SYSCFG_IOCTRLCLRR_HSLVEN_QUADSPI_Pos) /*!< 0x00000002 */
27239 #define SYSCFG_IOCTRLCLRR_HSLVEN_QUADSPI        SYSCFG_IOCTRLCLRR_HSLVEN_QUADSPI_Msk /*!< High Speed Low Voltage Pad mode Enable */
27240 #define SYSCFG_IOCTRLCLRR_HSLVEN_ETH_Pos        (2U)
27241 #define SYSCFG_IOCTRLCLRR_HSLVEN_ETH_Msk        (0x1U << SYSCFG_IOCTRLCLRR_HSLVEN_ETH_Pos) /*!< 0x00000004 */
27242 #define SYSCFG_IOCTRLCLRR_HSLVEN_ETH            SYSCFG_IOCTRLCLRR_HSLVEN_ETH_Msk     /*!< High Speed Low Voltage Pad mode Enable */
27243 #define SYSCFG_IOCTRLCLRR_HSLVEN_SDMMC_Pos      (3U)
27244 #define SYSCFG_IOCTRLCLRR_HSLVEN_SDMMC_Msk      (0x1U << SYSCFG_IOCTRLCLRR_HSLVEN_SDMMC_Pos) /*!< 0x00000008 */
27245 #define SYSCFG_IOCTRLCLRR_HSLVEN_SDMMC          SYSCFG_IOCTRLCLRR_HSLVEN_SDMMC_Msk   /*!< High Speed Low Voltage Pad mode Enable */
27246 #define SYSCFG_IOCTRLCLRR_HSLVEN_SPI_Pos        (4U)
27247 #define SYSCFG_IOCTRLCLRR_HSLVEN_SPI_Msk        (0x1U << SYSCFG_IOCTRLCLRR_HSLVEN_SPI_Pos) /*!< 0x00000010 */
27248 #define SYSCFG_IOCTRLCLRR_HSLVEN_SPI            SYSCFG_IOCTRLCLRR_HSLVEN_SPI_Msk     /*!< High Speed Low Voltage Pad mode Enable */
27249 
27250 /******************  Bit definition for SYSCFG_ICNR register  ********************/
27251 #define SYSCFG_ICNR_AXI_M0_Pos               (0U)
27252 #define SYSCFG_ICNR_AXI_M0_Msk               (0x1U << SYSCFG_ICNR_AXI_M0_Pos)  /*!< 0x00000001 */
27253 #define SYSCFG_ICNR_AXI_M0                   SYSCFG_ICNR_AXI_M0_Msk            /*!< controls which slave port is used by the master to access the DDR */
27254 #define SYSCFG_ICNR_AXI_M1_Pos               (1U)
27255 #define SYSCFG_ICNR_AXI_M1_Msk               (0x1U << SYSCFG_ICNR_AXI_M1_Pos)  /*!< 0x00000002 */
27256 #define SYSCFG_ICNR_AXI_M1                   SYSCFG_ICNR_AXI_M1_Msk            /*!< controls which slave port is used by the master to access the DDR */
27257 #define SYSCFG_ICNR_AXI_M2_Pos               (2U)
27258 #define SYSCFG_ICNR_AXI_M2_Msk               (0x1U << SYSCFG_ICNR_AXI_M2_Pos)  /*!< 0x00000004 */
27259 #define SYSCFG_ICNR_AXI_M2                   SYSCFG_ICNR_AXI_M2_Msk            /*!< controls which slave port is used by the master to access the DDR */
27260 #define SYSCFG_ICNR_AXI_M3_Pos               (3U)
27261 #define SYSCFG_ICNR_AXI_M3_Msk               (0x1U << SYSCFG_ICNR_AXI_M3_Pos)  /*!< 0x00000008 */
27262 #define SYSCFG_ICNR_AXI_M3                   SYSCFG_ICNR_AXI_M3_Msk            /*!< controls which slave port is used by the master to access the DDR */
27263 #define SYSCFG_ICNR_AXI_M5_Pos               (5U)
27264 #define SYSCFG_ICNR_AXI_M5_Msk               (0x1U << SYSCFG_ICNR_AXI_M5_Pos)  /*!< 0x00000020 */
27265 #define SYSCFG_ICNR_AXI_M5                   SYSCFG_ICNR_AXI_M5_Msk            /*!< controls which slave port is used by the master to access the DDR */
27266 #define SYSCFG_ICNR_AXI_M6_Pos               (6U)
27267 #define SYSCFG_ICNR_AXI_M6_Msk               (0x1U << SYSCFG_ICNR_AXI_M6_Pos)  /*!< 0x00000040 */
27268 #define SYSCFG_ICNR_AXI_M6                   SYSCFG_ICNR_AXI_M6_Msk            /*!< controls which slave port is used by the master to access the DDR */
27269 #define SYSCFG_ICNR_AXI_M7_Pos               (7U)
27270 #define SYSCFG_ICNR_AXI_M7_Msk               (0x1U << SYSCFG_ICNR_AXI_M7_Pos)  /*!< 0x00000080 */
27271 #define SYSCFG_ICNR_AXI_M7                   SYSCFG_ICNR_AXI_M7_Msk            /*!< controls which slave port is used by the master to access the DDR */
27272 #define SYSCFG_ICNR_AXI_M8_Pos               (8U)
27273 #define SYSCFG_ICNR_AXI_M8_Msk               (0x1U << SYSCFG_ICNR_AXI_M8_Pos)  /*!< 0x00000100 */
27274 #define SYSCFG_ICNR_AXI_M8                   SYSCFG_ICNR_AXI_M8_Msk            /*!< controls which slave port is used by the master to access the DDR */
27275 #define SYSCFG_ICNR_AXI_M9_Pos               (9U)
27276 #define SYSCFG_ICNR_AXI_M9_Msk               (0x1U << SYSCFG_ICNR_AXI_M9_Pos)  /*!< 0x00000200 */
27277 #define SYSCFG_ICNR_AXI_M9                   SYSCFG_ICNR_AXI_M9_Msk            /*!< controls which slave port is used by the master to access the DDR */
27278 #define SYSCFG_ICNR_AXI_M10_Pos              (10U)
27279 #define SYSCFG_ICNR_AXI_M10_Msk              (0x1U << SYSCFG_ICNR_AXI_M10_Pos) /*!< 0x00000400 */
27280 #define SYSCFG_ICNR_AXI_M10                  SYSCFG_ICNR_AXI_M10_Msk           /*!< controls which slave port is used by the master to access the DDR */
27281 
27282 /******************  Bit definition for SYSCFG_CMPCR register   ********************/
27283 #define SYSCFG_CMPCR_SW_CTRL_Pos             (1U)
27284 #define SYSCFG_CMPCR_SW_CTRL_Msk             (0x1U << SYSCFG_CMPCR_SW_CTRL_Pos) /*!< 0x00000002 */
27285 #define SYSCFG_CMPCR_SW_CTRL                 SYSCFG_CMPCR_SW_CTRL_Msk          /*!< Compensation Software Control */
27286 #define SYSCFG_CMPCR_READY_Pos               (8U)
27287 #define SYSCFG_CMPCR_READY_Msk               (0x1U << SYSCFG_CMPCR_READY_Pos)  /*!< 0x00000100 */
27288 #define SYSCFG_CMPCR_READY                   SYSCFG_CMPCR_READY_Msk            /*!< Compensation cell ready flag */
27289 #define SYSCFG_CMPCR_RANSRC_Pos              (16U)
27290 #define SYSCFG_CMPCR_RANSRC_Msk              (0xFU << SYSCFG_CMPCR_RANSRC_Pos) /*!< 0x000F0000 */
27291 #define SYSCFG_CMPCR_RANSRC                  SYSCFG_CMPCR_RANSRC_Msk           /*!< NMOS I/O Compensation value sent to IOs when SW_CTRL = 1 */
27292 #define SYSCFG_CMPCR_RANSRC_0                (0x1U << SYSCFG_CMPCR_RANSRC_Pos) /*!< 0x00010000 */
27293 #define SYSCFG_CMPCR_RANSRC_1                (0x2U << SYSCFG_CMPCR_RANSRC_Pos) /*!< 0x00020000 */
27294 #define SYSCFG_CMPCR_RANSRC_2                (0x4U << SYSCFG_CMPCR_RANSRC_Pos) /*!< 0x00040000 */
27295 #define SYSCFG_CMPCR_RANSRC_3                (0x8U << SYSCFG_CMPCR_RANSRC_Pos) /*!< 0x00080000 */
27296 #define SYSCFG_CMPCR_RAPSRC_Pos              (20U)
27297 #define SYSCFG_CMPCR_RAPSRC_Msk              (0xFU << SYSCFG_CMPCR_RAPSRC_Pos) /*!< 0x00F00000 */
27298 #define SYSCFG_CMPCR_RAPSRC                  SYSCFG_CMPCR_RAPSRC_Msk           /*!< PMOS I/O Compensation value sent to IOs when SW_CTRL = 1 */
27299 #define SYSCFG_CMPCR_RAPSRC_0                (0x1U << SYSCFG_CMPCR_RAPSRC_Pos) /*!< 0x00100000 */
27300 #define SYSCFG_CMPCR_RAPSRC_1                (0x2U << SYSCFG_CMPCR_RAPSRC_Pos) /*!< 0x00200000 */
27301 #define SYSCFG_CMPCR_RAPSRC_2                (0x4U << SYSCFG_CMPCR_RAPSRC_Pos) /*!< 0x00400000 */
27302 #define SYSCFG_CMPCR_RAPSRC_3                (0x8U << SYSCFG_CMPCR_RAPSRC_Pos) /*!< 0x00800000 */
27303 #define SYSCFG_CMPCR_ANSRC_Pos               (24U)
27304 #define SYSCFG_CMPCR_ANSRC_Msk               (0xFU << SYSCFG_CMPCR_ANSRC_Pos)  /*!< 0x0F000000 */
27305 #define SYSCFG_CMPCR_ANSRC                   SYSCFG_CMPCR_ANSRC_Msk            /*!< NMOS I/O Compensation value provided by compensation cell */
27306 #define SYSCFG_CMPCR_ANSRC_0                 (0x1U << SYSCFG_CMPCR_ANSRC_Pos)  /*!< 0x01000000 */
27307 #define SYSCFG_CMPCR_ANSRC_1                 (0x2U << SYSCFG_CMPCR_ANSRC_Pos)  /*!< 0x02000000 */
27308 #define SYSCFG_CMPCR_ANSRC_2                 (0x4U << SYSCFG_CMPCR_ANSRC_Pos)  /*!< 0x04000000 */
27309 #define SYSCFG_CMPCR_ANSRC_3                 (0x8U << SYSCFG_CMPCR_ANSRC_Pos)  /*!< 0x08000000 */
27310 #define SYSCFG_CMPCR_APSRC_Pos               (28U)
27311 #define SYSCFG_CMPCR_APSRC_Msk               (0xFU << SYSCFG_CMPCR_APSRC_Pos)  /*!< 0xF0000000 */
27312 #define SYSCFG_CMPCR_APSRC                   SYSCFG_CMPCR_APSRC_Msk            /*!< PMOS I/O Compensation value provided by compensation cell */
27313 #define SYSCFG_CMPCR_APSRC_0                 (0x1U << SYSCFG_CMPCR_APSRC_Pos)  /*!< 0x10000000 */
27314 #define SYSCFG_CMPCR_APSRC_1                 (0x2U << SYSCFG_CMPCR_APSRC_Pos)  /*!< 0x20000000 */
27315 #define SYSCFG_CMPCR_APSRC_2                 (0x4U << SYSCFG_CMPCR_APSRC_Pos)  /*!< 0x40000000 */
27316 #define SYSCFG_CMPCR_APSRC_3                 (0x8U << SYSCFG_CMPCR_APSRC_Pos)  /*!< 0x80000000 */
27317 
27318 /******************  Bit definition for SYSCFG_CMPENSETR register   ********************/
27319 #define SYSCFG_CMPENSETR_MPU_EN_Pos              (0U)
27320 #define SYSCFG_CMPENSETR_MPU_EN_Msk              (0x1U << SYSCFG_CMPENSETR_MPU_EN_Pos) /*!< 0x00000001 */
27321 #define SYSCFG_CMPENSETR_MPU_EN                  SYSCFG_CMPENSETR_MPU_EN_Msk           /*!< Compensation cell enable */
27322 #define SYSCFG_CMPENSETR_MCU_EN_Pos              (1U)
27323 #define SYSCFG_CMPENSETR_MCU_EN_Msk              (0x1U << SYSCFG_CMPENSETR_MCU_EN_Pos) /*!< 0x00000001 */
27324 #define SYSCFG_CMPENSETR_MCU_EN                  SYSCFG_CMPENSETR_MCU_EN_Msk           /*!< Compensation cell enable */
27325 
27326 
27327 /******************  Bit definition for SYSCFG_CMPENCLRR register   ********************/
27328 #define SYSCFG_CMPENCLRR_MPU_EN_Pos              (0U)
27329 #define SYSCFG_CMPENCLRR_MPU_EN_Msk              (0x1U << SYSCFG_CMPENCLRR_MPU_EN_Pos)  /*!< 0x00000001 */
27330 #define SYSCFG_CMPENCLRR_MPU_EN                  SYSCFG_CMPENCLRR_MPU_EN_Msk            /*!< Compensation cell disable */
27331 #define SYSCFG_CMPENCLRR_MCU_EN_Pos              (0U)
27332 #define SYSCFG_CMPENCLRR_MCU_EN_Msk              (0x1U << SYSCFG_CMPENCLRR_MCU_EN_Pos)  /*!< 0x00000001 */
27333 #define SYSCFG_CMPENCLRR_MCU_EN                  SYSCFG_CMPENCLRR_MCU_EN_Msk            /*!< Compensation cell disable */
27334 
27335 /******************  Bit definition for SYSCFG_CBR register  ******************/
27336 #define SYSCFG_CBR_CLL_Pos           (0U)
27337 #define SYSCFG_CBR_CLL_Msk           (0x1U << SYSCFG_CBR_CLL_Pos)              /*!< 0x00000001 */
27338 #define SYSCFG_CBR_CLL               SYSCFG_CBR_CLL_Msk                        /*!< Cortex-M4 LOCKUP (Hardfault) output enable bit */
27339 #define SYSCFG_CBR_PVDL_Pos          (2U)
27340 #define SYSCFG_CBR_PVDL_Msk          (0x1U << SYSCFG_CBR_PVDL_Pos)             /*!< 0x00000004 */
27341 #define SYSCFG_CBR_PVDL              SYSCFG_CBR_PVDL_Msk                       /*!< PVD lock enable bit */
27342 
27343 /**********************  Bit definition for SYSCFG_VERR register  *****************/
27344 #define SYSCFG_VERR_MINREV_Pos      (0U)
27345 #define SYSCFG_VERR_MINREV_Msk      (0xFU << SYSCFG_VERR_MINREV_Pos)               /*!< 0x0000000F */
27346 #define SYSCFG_VERR_MINREV          SYSCFG_VERR_MINREV_Msk                         /*!< Minor Revision number */
27347 #define SYSCFG_VERR_MAJREV_Pos      (4U)
27348 #define SYSCFG_VERR_MAJREV_Msk      (0xFU << SYSCFG_VERR_MAJREV_Pos)               /*!< 0x000000F0 */
27349 #define SYSCFG_VERR_MAJREV          SYSCFG_VERR_MAJREV_Msk                         /*!< Major Revision number */
27350 
27351 /**********************  Bit definition for SYSCFG_IPIDR register  ****************/
27352 #define SYSCFG_IPIDR_IPID_Pos       (0U)
27353 #define SYSCFG_IPIDR_IPID_Msk       (0xFFFFFFFFU << SYSCFG_IPIDR_IPID_Pos)         /*!< 0xFFFFFFFF */
27354 #define SYSCFG_IPIDR_IPID           SYSCFG_IPIDR_IPID_Msk                          /*!< IP Identification */
27355 
27356 /**********************  Bit definition for SYSCFG_SIDR register  *****************/
27357 #define SYSCFG_SIDR_SID_Pos         (0U)
27358 #define SYSCFG_SIDR_SID_Msk         (0xFFFFFFFFU << SYSCFG_SIDR_SID_Pos)           /*!< 0xFFFFFFFF */
27359 #define SYSCFG_SIDR_SID             SYSCFG_SIDR_SID_Msk                            /*!< IP size identification */
27360 
27361 /******************************************************************************/
27362 /*                                                                            */
27363 /*                         Temperature Sensor (DTS)                           */
27364 /*                                                                            */
27365 /******************************************************************************/
27366 
27367 /******************  Bit definition for DTS_CFGR1 register  ******************/
27368 #define DTS_CFGR1_TS1_EN_Pos               (0U)
27369 #define DTS_CFGR1_TS1_EN_Msk               (0x1U << DTS_CFGR1_TS1_EN_Pos) /*!< 0x00000001 */
27370 #define DTS_CFGR1_TS1_EN                   DTS_CFGR1_TS1_EN_Msk        /*!< DTS1 Enable */
27371 #define DTS_CFGR1_TS1_START_Pos            (4U)
27372 #define DTS_CFGR1_TS1_START_Msk            (0x1U << DTS_CFGR1_TS1_START_Pos) /*!< 0x00000010 */
27373 #define DTS_CFGR1_TS1_START                DTS_CFGR1_TS1_START_Msk     /*!< Proceed to a frequency measurement on DTS1 */
27374 #define DTS_CFGR1_TS1_INTRIG_SEL_Pos       (8U)
27375 #define DTS_CFGR1_TS1_INTRIG_SEL_Msk       (0xFU << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000F00 */
27376 #define DTS_CFGR1_TS1_INTRIG_SEL           DTS_CFGR1_TS1_INTRIG_SEL_Msk /*!< Input triggers selection bits [3:0] for DTS1 */
27377 #define DTS_CFGR1_TS1_INTRIG_SEL_0         (0x1U << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000100 */
27378 #define DTS_CFGR1_TS1_INTRIG_SEL_1         (0x2U << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000200 */
27379 #define DTS_CFGR1_TS1_INTRIG_SEL_2         (0x4U << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000400 */
27380 #define DTS_CFGR1_TS1_INTRIG_SEL_3         (0x8U << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000800 */
27381 #define DTS_CFGR1_TS1_SMP_TIME_Pos         (16U)
27382 #define DTS_CFGR1_TS1_SMP_TIME_Msk         (0xFU << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x000F0000 */
27383 #define DTS_CFGR1_TS1_SMP_TIME             DTS_CFGR1_TS1_SMP_TIME_Msk  /*!< Sample time [3:0] for DTS1 */
27384 #define DTS_CFGR1_TS1_SMP_TIME_0           (0x1U << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00010000 */
27385 #define DTS_CFGR1_TS1_SMP_TIME_1           (0x2U << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00020000 */
27386 #define DTS_CFGR1_TS1_SMP_TIME_2           (0x4U << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00040000 */
27387 #define DTS_CFGR1_TS1_SMP_TIME_3           (0x8U << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00080000 */
27388 #define DTS_CFGR1_REFCLK_SEL_Pos           (20U)
27389 #define DTS_CFGR1_REFCLK_SEL_Msk           (0x1U << DTS_CFGR1_REFCLK_SEL_Pos) /*!< 0x00100000 */
27390 #define DTS_CFGR1_REFCLK_SEL               DTS_CFGR1_REFCLK_SEL_Msk    /*!< Reference Clock Selection */
27391 #define DTS_CFGR1_Q_MEAS_OPT_Pos           (21U)
27392 #define DTS_CFGR1_Q_MEAS_OPT_Msk           (0x1U << DTS_CFGR1_Q_MEAS_OPT_Pos) /*!< 0x00200000 */
27393 #define DTS_CFGR1_Q_MEAS_OPT               DTS_CFGR1_Q_MEAS_OPT_Msk    /*!< Quick measure option bit  */
27394 #define DTS_CFGR1_HSREF_CLK_DIV_Pos        (24U)
27395 #define DTS_CFGR1_HSREF_CLK_DIV_Msk        (0x7FU << DTS_CFGR1_HSREF_CLK_DIV_Pos) /*!< 0x7F000000 */
27396 #define DTS_CFGR1_HSREF_CLK_DIV            DTS_CFGR1_HSREF_CLK_DIV_Msk /*!< High Speed Clock Divider Ratio [6:0]*/
27397 
27398 /******************  Bit definition for DTS_T0VALR1 register  ******************/
27399 #define DTS_T0VALR1_TS1_FMT0_Pos           (0U)
27400 #define DTS_T0VALR1_TS1_FMT0_Msk           (0xFFFFU << DTS_T0VALR1_TS1_FMT0_Pos) /*!< 0x0000FFFF */
27401 #define DTS_T0VALR1_TS1_FMT0               DTS_T0VALR1_TS1_FMT0_Msk    /*!< Engineering value of the measured frequency at T0 for DTS1 */
27402 #define DTS_T0VALR1_TS1_T0_Pos             (16U)
27403 #define DTS_T0VALR1_TS1_T0_Msk             (0x3U << DTS_T0VALR1_TS1_T0_Pos) /*!< 0x00030000 */
27404 #define DTS_T0VALR1_TS1_T0                 DTS_T0VALR1_TS1_T0_Msk      /*!< Engineering value of the DTSerature T0 for DTS1 */
27405 
27406 /******************  Bit definition for DTS_RAMPVALR register  ******************/
27407 #define DTS_RAMPVALR_TS1_RAMP_COEFF_Pos    (0U)
27408 #define DTS_RAMPVALR_TS1_RAMP_COEFF_Msk    (0xFFFFU << DTS_RAMPVALR_TS1_RAMP_COEFF_Pos) /*!< 0x0000FFFF */
27409 #define DTS_RAMPVALR_TS1_RAMP_COEFF        DTS_RAMPVALR_TS1_RAMP_COEFF_Msk /*!< Engineering value of the ramp coefficient for DTS1 */
27410 
27411 /******************  Bit definition for DTS_ITR1 register      ******************/
27412 #define DTS_ITR1_TS1_LITTHD_Pos            (0U)
27413 #define DTS_ITR1_TS1_LITTHD_Msk            (0xFFFFU << DTS_ITR1_TS1_LITTHD_Pos) /*!< 0x0000FFFF */
27414 #define DTS_ITR1_TS1_LITTHD                DTS_ITR1_TS1_LITTHD_Msk     /*!< Low interrupt threshold[15:0] for DTS1 */
27415 #define DTS_ITR1_TS1_HITTHD_Pos            (16U)
27416 #define DTS_ITR1_TS1_HITTHD_Msk            (0xFFFFU << DTS_ITR1_TS1_HITTHD_Pos) /*!< 0xFFFF0000 */
27417 #define DTS_ITR1_TS1_HITTHD                DTS_ITR1_TS1_HITTHD_Msk     /*!< High interrupt threshold[15:0] for DTS1 */
27418 
27419 /******************  Bit definition for DTS_DR register        ******************/
27420 #define DTS_DR_TS1_MFREQ_Pos               (0U)
27421 #define DTS_DR_TS1_MFREQ_Msk               (0xFFFFU << DTS_DR_TS1_MFREQ_Pos) /*!< 0x0000FFFF */
27422 #define DTS_DR_TS1_MFREQ                   DTS_DR_TS1_MFREQ_Msk        /*!< Measured Frequency[15:0] for DTS1 */
27423 
27424 /******************  Bit definition for DTS_SR register        ******************/
27425 #define DTS_SR_TS1_ITEF_Pos                (0U)
27426 #define DTS_SR_TS1_ITEF_Msk                (0x1U << DTS_SR_TS1_ITEF_Pos) /*!< 0x00000001 */
27427 #define DTS_SR_TS1_ITEF                    DTS_SR_TS1_ITEF_Msk         /*!< Interrupt flag for end of measure for DTS1 */
27428 #define DTS_SR_TS1_ITLF_Pos                (1U)
27429 #define DTS_SR_TS1_ITLF_Msk                (0x1U << DTS_SR_TS1_ITLF_Pos) /*!< 0x00000002 */
27430 #define DTS_SR_TS1_ITLF                    DTS_SR_TS1_ITLF_Msk         /*!< Interrupt flag for low threshold for DTS1  */
27431 #define DTS_SR_TS1_ITHF_Pos                (2U)
27432 #define DTS_SR_TS1_ITHF_Msk                (0x1U << DTS_SR_TS1_ITHF_Pos) /*!< 0x00000004 */
27433 #define DTS_SR_TS1_ITHF                    DTS_SR_TS1_ITHF_Msk         /*!< Interrupt flag for high threshold for DTS1 */
27434 #define DTS_SR_TS1_AITEF_Pos               (4U)
27435 #define DTS_SR_TS1_AITEF_Msk               (0x1U << DTS_SR_TS1_AITEF_Pos) /*!< 0x00000010 */
27436 #define DTS_SR_TS1_AITEF                   DTS_SR_TS1_AITEF_Msk        /*!< Asynchronous interrupt flag for end of measure for DTS1 */
27437 #define DTS_SR_TS1_AITLF_Pos               (5U)
27438 #define DTS_SR_TS1_AITLF_Msk               (0x1U << DTS_SR_TS1_AITLF_Pos) /*!< 0x00000020 */
27439 #define DTS_SR_TS1_AITLF                   DTS_SR_TS1_AITLF_Msk        /*!< Asynchronous interrupt flag for low threshold for DTS1  */
27440 #define DTS_SR_TS1_AITHF_Pos               (6U)
27441 #define DTS_SR_TS1_AITHF_Msk               (0x1U << DTS_SR_TS1_AITHF_Pos) /*!< 0x00000040 */
27442 #define DTS_SR_TS1_AITHF                   DTS_SR_TS1_AITHF_Msk        /*!< Asynchronous interrupt flag for high threshold for DTS1 */
27443 #define DTS_SR_TS1_RDY_Pos                 (15U)
27444 #define DTS_SR_TS1_RDY_Msk                 (0x1U << DTS_SR_TS1_RDY_Pos) /*!< 0x00008000 */
27445 #define DTS_SR_TS1_RDY                     DTS_SR_TS1_RDY_Msk          /*!< DTS1 ready flag */
27446 
27447 /******************  Bit definition for DTS_ITENR register      ******************/
27448 #define DTS_ITENR_TS1_ITEEN_Pos            (0U)
27449 #define DTS_ITENR_TS1_ITEEN_Msk            (0x1U << DTS_ITENR_TS1_ITEEN_Pos) /*!< 0x00000001 */
27450 #define DTS_ITENR_TS1_ITEEN                DTS_ITENR_TS1_ITEEN_Msk     /*!< Enable interrupt flag for end of measure for DTS1 */
27451 #define DTS_ITENR_TS1_ITLEN_Pos            (1U)
27452 #define DTS_ITENR_TS1_ITLEN_Msk            (0x1U << DTS_ITENR_TS1_ITLEN_Pos) /*!< 0x00000002 */
27453 #define DTS_ITENR_TS1_ITLEN                DTS_ITENR_TS1_ITLEN_Msk     /*!< Enable interrupt flag for low threshold for DTS1  */
27454 #define DTS_ITENR_TS1_ITHEN_Pos            (2U)
27455 #define DTS_ITENR_TS1_ITHEN_Msk            (0x1U << DTS_ITENR_TS1_ITHEN_Pos) /*!< 0x00000004 */
27456 #define DTS_ITENR_TS1_ITHEN                DTS_ITENR_TS1_ITHEN_Msk     /*!< Enable interrupt flag for high threshold for DTS1 */
27457 #define DTS_ITENR_TS1_AITEEN_Pos           (4U)
27458 #define DTS_ITENR_TS1_AITEEN_Msk           (0x1U << DTS_ITENR_TS1_AITEEN_Pos) /*!< 0x00000010 */
27459 #define DTS_ITENR_TS1_AITEEN               DTS_ITENR_TS1_AITEEN_Msk    /*!< Enable asynchronous interrupt flag for end of measure for DTS1 */
27460 #define DTS_ITENR_TS1_AITLEN_Pos           (5U)
27461 #define DTS_ITENR_TS1_AITLEN_Msk           (0x1U << DTS_ITENR_TS1_AITLEN_Pos) /*!< 0x00000020 */
27462 #define DTS_ITENR_TS1_AITLEN               DTS_ITENR_TS1_AITLEN_Msk    /*!< Enable Asynchronous interrupt flag for low threshold for DTS1  */
27463 #define DTS_ITENR_TS1_AITHEN_Pos           (6U)
27464 #define DTS_ITENR_TS1_AITHEN_Msk           (0x1U << DTS_ITENR_TS1_AITHEN_Pos) /*!< 0x00000040 */
27465 #define DTS_ITENR_TS1_AITHEN               DTS_ITENR_TS1_AITHEN_Msk    /*!< Enable asynchronous interrupt flag for high threshold for DTS1 */
27466 
27467 /******************  Bit definition for DTS_ICIFR register      ******************/
27468 #define DTS_ICIFR_TS1_CITEF_Pos            (0U)
27469 #define DTS_ICIFR_TS1_CITEF_Msk            (0x1U << DTS_ICIFR_TS1_CITEF_Pos) /*!< 0x00000001 */
27470 #define DTS_ICIFR_TS1_CITEF                DTS_ICIFR_TS1_CITEF_Msk     /*!< Clear the IT flag for End Of Measure for DTS1 */
27471 #define DTS_ICIFR_TS1_CITLF_Pos            (1U)
27472 #define DTS_ICIFR_TS1_CITLF_Msk            (0x1U << DTS_ICIFR_TS1_CITLF_Pos) /*!< 0x00000002 */
27473 #define DTS_ICIFR_TS1_CITLF                DTS_ICIFR_TS1_CITLF_Msk     /*!< Clear the IT flag for low threshold for DTS1  */
27474 #define DTS_ICIFR_TS1_CITHF_Pos            (2U)
27475 #define DTS_ICIFR_TS1_CITHF_Msk            (0x1U << DTS_ICIFR_TS1_CITHF_Pos) /*!< 0x00000004 */
27476 #define DTS_ICIFR_TS1_CITHF                DTS_ICIFR_TS1_CITHF_Msk     /*!< Clear the IT flag for high threshold on DTS1  */
27477 #define DTS_ICIFR_TS1_CAITEF_Pos           (4U)
27478 #define DTS_ICIFR_TS1_CAITEF_Msk           (0x1U << DTS_ICIFR_TS1_CAITEF_Pos) /*!< 0x00000010 */
27479 #define DTS_ICIFR_TS1_CAITEF               DTS_ICIFR_TS1_CAITEF_Msk    /*!< Clear the asynchronous IT flag for End Of Measure for DTS1 */
27480 #define DTS_ICIFR_TS1_CAITLF_Pos           (5U)
27481 #define DTS_ICIFR_TS1_CAITLF_Msk           (0x1U << DTS_ICIFR_TS1_CAITLF_Pos) /*!< 0x00000020 */
27482 #define DTS_ICIFR_TS1_CAITLF               DTS_ICIFR_TS1_CAITLF_Msk    /*!< Clear the asynchronous IT flag for low threshold for DTS1  */
27483 #define DTS_ICIFR_TS1_CAITHF_Pos           (6U)
27484 #define DTS_ICIFR_TS1_CAITHF_Msk           (0x1U << DTS_ICIFR_TS1_CAITHF_Pos) /*!< 0x00000040 */
27485 #define DTS_ICIFR_TS1_CAITHF               DTS_ICIFR_TS1_CAITHF_Msk    /*!< Clear the asynchronous IT flag for high threshold on DTS1  */
27486 
27487 
27488 /******************************************************************************/
27489 /*                                                                            */
27490 /*                                    TIM                                     */
27491 /*                                                                            */
27492 /******************************************************************************/
27493 /*******************  Bit definition for TIM_CR1 register  ********************/
27494 #define TIM_CR1_CEN               ((uint16_t)0x0001)                           /*!<Counter enable */
27495 #define TIM_CR1_UDIS              ((uint16_t)0x0002)                           /*!<Update disable */
27496 #define TIM_CR1_URS               ((uint16_t)0x0004)                           /*!<Update request source */
27497 #define TIM_CR1_OPM               ((uint16_t)0x0008)                           /*!<One pulse mode */
27498 #define TIM_CR1_DIR               ((uint16_t)0x0010)                           /*!<Direction */
27499 
27500 #define TIM_CR1_CMS               ((uint16_t)0x0060)                           /*!<CMS[1:0] bits (Center-aligned mode selection) */
27501 #define TIM_CR1_CMS_0             ((uint16_t)0x0020)                           /*!<Bit 0 */
27502 #define TIM_CR1_CMS_1             ((uint16_t)0x0040)                           /*!<Bit 1 */
27503 
27504 #define TIM_CR1_ARPE              ((uint16_t)0x0080)                           /*!<Auto-reload preload enable */
27505 
27506 #define TIM_CR1_CKD               ((uint16_t)0x0300)                           /*!<CKD[1:0] bits (clock division) */
27507 #define TIM_CR1_CKD_0             ((uint16_t)0x0100)                           /*!<Bit 0 */
27508 #define TIM_CR1_CKD_1             ((uint16_t)0x0200)                           /*!<Bit 1 */
27509 
27510 #define TIM_CR1_UIFREMAP          ((uint16_t)0x0800)                           /*!<Update interrupt flag remap */
27511 
27512 /*******************  Bit definition for TIM_CR2 register  ********************/
27513 #define TIM_CR2_CCPC_Pos          (0U)
27514 #define TIM_CR2_CCPC_Msk          (0x1U << TIM_CR2_CCPC_Pos)                   /*!< 0x00000001 */
27515 #define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */
27516 #define TIM_CR2_CCUS_Pos          (2U)
27517 #define TIM_CR2_CCUS_Msk          (0x1U << TIM_CR2_CCUS_Pos)                   /*!< 0x00000004 */
27518 #define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
27519 #define TIM_CR2_CCDS_Pos          (3U)
27520 #define TIM_CR2_CCDS_Msk          (0x1U << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
27521 #define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
27522 
27523 #define TIM_CR2_MMS_Pos           (4U)
27524 #define TIM_CR2_MMS_Msk           (0x7U << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
27525 #define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
27526 #define TIM_CR2_MMS_0             (0x1U << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */
27527 #define TIM_CR2_MMS_1             (0x2U << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */
27528 #define TIM_CR2_MMS_2             (0x4U << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */
27529 
27530 #define TIM_CR2_TI1S_Pos          (7U)
27531 #define TIM_CR2_TI1S_Msk          (0x1U << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
27532 #define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
27533 #define TIM_CR2_OIS1_Pos          (8U)
27534 #define TIM_CR2_OIS1_Msk          (0x1U << TIM_CR2_OIS1_Pos)                   /*!< 0x00000100 */
27535 #define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */
27536 #define TIM_CR2_OIS1N_Pos         (9U)
27537 #define TIM_CR2_OIS1N_Msk         (0x1U << TIM_CR2_OIS1N_Pos)                  /*!< 0x00000200 */
27538 #define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
27539 #define TIM_CR2_OIS2_Pos          (10U)
27540 #define TIM_CR2_OIS2_Msk          (0x1U << TIM_CR2_OIS2_Pos)                   /*!< 0x00000400 */
27541 #define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */
27542 #define TIM_CR2_OIS2N_Pos         (11U)
27543 #define TIM_CR2_OIS2N_Msk         (0x1U << TIM_CR2_OIS2N_Pos)                  /*!< 0x00000800 */
27544 #define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
27545 #define TIM_CR2_OIS3_Pos          (12U)
27546 #define TIM_CR2_OIS3_Msk          (0x1U << TIM_CR2_OIS3_Pos)                   /*!< 0x00001000 */
27547 #define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */
27548 #define TIM_CR2_OIS3N_Pos         (13U)
27549 #define TIM_CR2_OIS3N_Msk         (0x1U << TIM_CR2_OIS3N_Pos)                  /*!< 0x00002000 */
27550 #define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
27551 #define TIM_CR2_OIS4_Pos          (14U)
27552 #define TIM_CR2_OIS4_Msk          (0x1U << TIM_CR2_OIS4_Pos)                   /*!< 0x00004000 */
27553 #define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */
27554 #define TIM_CR2_OIS5_Pos          (16U)
27555 #define TIM_CR2_OIS5_Msk          (0x1U << TIM_CR2_OIS5_Pos)                   /*!< 0x00010000 */
27556 #define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */
27557 #define TIM_CR2_OIS6_Pos          (18U)
27558 #define TIM_CR2_OIS6_Msk          (0x1U << TIM_CR2_OIS6_Pos)                   /*!< 0x00040000 */
27559 #define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */
27560 
27561 #define TIM_CR2_MMS2_Pos          (20U)
27562 #define TIM_CR2_MMS2_Msk          (0xFU << TIM_CR2_MMS2_Pos)                   /*!< 0x00F00000 */
27563 #define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */
27564 #define TIM_CR2_MMS2_0            (0x1U << TIM_CR2_MMS2_Pos)                   /*!< 0x00100000 */
27565 #define TIM_CR2_MMS2_1            (0x2U << TIM_CR2_MMS2_Pos)                   /*!< 0x00200000 */
27566 #define TIM_CR2_MMS2_2            (0x4U << TIM_CR2_MMS2_Pos)                   /*!< 0x00400000 */
27567 #define TIM_CR2_MMS2_3            (0x8U << TIM_CR2_MMS2_Pos)                   /*!< 0x00800000 */
27568 
27569 /*******************  Bit definition for TIM_SMCR register  *******************/
27570 #define TIM_SMCR_SMS_Pos          (0U)
27571 #define TIM_SMCR_SMS_Msk          (0x10007U << TIM_SMCR_SMS_Pos)               /*!< 0x00010007 */
27572 #define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
27573 #define TIM_SMCR_SMS_0            (0x00001U << TIM_SMCR_SMS_Pos)               /*!< 0x00000001 */
27574 #define TIM_SMCR_SMS_1            (0x00002U << TIM_SMCR_SMS_Pos)               /*!< 0x00000002 */
27575 #define TIM_SMCR_SMS_2            (0x00004U << TIM_SMCR_SMS_Pos)               /*!< 0x00000004 */
27576 #define TIM_SMCR_SMS_3            (0x10000U << TIM_SMCR_SMS_Pos)               /*!< 0x00010000 */
27577 
27578 #define TIM_SMCR_TS_Pos           (4U)
27579 #define TIM_SMCR_TS_Msk           (0x30007U << TIM_SMCR_TS_Pos)                /*!< 0x00300070 */
27580 #define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[4:0] bits (Trigger selection) */
27581 #define TIM_SMCR_TS_0             (0x00001U << TIM_SMCR_TS_Pos)                /*!< 0x00000010 */
27582 #define TIM_SMCR_TS_1             (0x00002U << TIM_SMCR_TS_Pos)                /*!< 0x00000020 */
27583 #define TIM_SMCR_TS_2             (0x00004U << TIM_SMCR_TS_Pos)                /*!< 0x00000040 */
27584 #define TIM_SMCR_TS_3             (0x10000U << TIM_SMCR_TS_Pos)                /*!< 0x00100000 */
27585 #define TIM_SMCR_TS_4             (0x20000U << TIM_SMCR_TS_Pos)                /*!< 0x00200000 */
27586 
27587 #define TIM_SMCR_MSM_Pos          (7U)
27588 #define TIM_SMCR_MSM_Msk          (0x1U << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
27589 #define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
27590 
27591 #define TIM_SMCR_ETF_Pos          (8U)
27592 #define TIM_SMCR_ETF_Msk          (0xFU << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
27593 #define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
27594 #define TIM_SMCR_ETF_0            (0x1U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */
27595 #define TIM_SMCR_ETF_1            (0x2U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */
27596 #define TIM_SMCR_ETF_2            (0x4U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */
27597 #define TIM_SMCR_ETF_3            (0x8U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */
27598 
27599 #define TIM_SMCR_ETPS_Pos         (12U)
27600 #define TIM_SMCR_ETPS_Msk         (0x3U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
27601 #define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
27602 #define TIM_SMCR_ETPS_0           (0x1U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */
27603 #define TIM_SMCR_ETPS_1           (0x2U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */
27604 
27605 #define TIM_SMCR_ECE_Pos          (14U)
27606 #define TIM_SMCR_ECE_Msk          (0x1U << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
27607 #define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
27608 #define TIM_SMCR_ETP_Pos          (15U)
27609 #define TIM_SMCR_ETP_Msk          (0x1U << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
27610 #define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
27611 
27612 /*******************  Bit definition for TIM_DIER register  *******************/
27613 #define TIM_DIER_UIE              ((uint16_t)0x0001)                           /*!<Update interrupt enable */
27614 #define TIM_DIER_CC1IE            ((uint16_t)0x0002)                           /*!<Capture/Compare 1 interrupt enable */
27615 #define TIM_DIER_CC2IE            ((uint16_t)0x0004)                           /*!<Capture/Compare 2 interrupt enable */
27616 #define TIM_DIER_CC3IE            ((uint16_t)0x0008)                           /*!<Capture/Compare 3 interrupt enable */
27617 #define TIM_DIER_CC4IE            ((uint16_t)0x0010)                           /*!<Capture/Compare 4 interrupt enable */
27618 #define TIM_DIER_COMIE            ((uint16_t)0x0020)                           /*!<COM interrupt enable */
27619 #define TIM_DIER_TIE              ((uint16_t)0x0040)                           /*!<Trigger interrupt enable */
27620 #define TIM_DIER_BIE              ((uint16_t)0x0080)                           /*!<Break interrupt enable */
27621 #define TIM_DIER_UDE              ((uint16_t)0x0100)                           /*!<Update DMA request enable */
27622 #define TIM_DIER_CC1DE            ((uint16_t)0x0200)                           /*!<Capture/Compare 1 DMA request enable */
27623 #define TIM_DIER_CC2DE            ((uint16_t)0x0400)                           /*!<Capture/Compare 2 DMA request enable */
27624 #define TIM_DIER_CC3DE            ((uint16_t)0x0800)                           /*!<Capture/Compare 3 DMA request enable */
27625 #define TIM_DIER_CC4DE            ((uint16_t)0x1000)                           /*!<Capture/Compare 4 DMA request enable */
27626 #define TIM_DIER_COMDE            ((uint16_t)0x2000)                           /*!<COM DMA request enable */
27627 #define TIM_DIER_TDE              ((uint16_t)0x4000)                           /*!<Trigger DMA request enable */
27628 
27629 /********************  Bit definition for TIM_SR register  ********************/
27630 #define TIM_SR_UIF_Pos            (0U)
27631 #define TIM_SR_UIF_Msk            (0x1U << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
27632 #define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
27633 #define TIM_SR_CC1IF_Pos          (1U)
27634 #define TIM_SR_CC1IF_Msk          (0x1U << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
27635 #define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
27636 #define TIM_SR_CC2IF_Pos          (2U)
27637 #define TIM_SR_CC2IF_Msk          (0x1U << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
27638 #define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
27639 #define TIM_SR_CC3IF_Pos          (3U)
27640 #define TIM_SR_CC3IF_Msk          (0x1U << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
27641 #define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
27642 #define TIM_SR_CC4IF_Pos          (4U)
27643 #define TIM_SR_CC4IF_Msk          (0x1U << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
27644 #define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
27645 #define TIM_SR_COMIF_Pos          (5U)
27646 #define TIM_SR_COMIF_Msk          (0x1U << TIM_SR_COMIF_Pos)                   /*!< 0x00000020 */
27647 #define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */
27648 #define TIM_SR_TIF_Pos            (6U)
27649 #define TIM_SR_TIF_Msk            (0x1U << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
27650 #define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
27651 #define TIM_SR_BIF_Pos            (7U)
27652 #define TIM_SR_BIF_Msk            (0x1U << TIM_SR_BIF_Pos)                     /*!< 0x00000080 */
27653 #define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */
27654 #define TIM_SR_B2IF_Pos           (8U)
27655 #define TIM_SR_B2IF_Msk           (0x1U << TIM_SR_B2IF_Pos)                    /*!< 0x00000100 */
27656 #define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break2 interrupt Flag */
27657 #define TIM_SR_CC1OF_Pos          (9U)
27658 #define TIM_SR_CC1OF_Msk          (0x1U << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
27659 #define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
27660 #define TIM_SR_CC2OF_Pos          (10U)
27661 #define TIM_SR_CC2OF_Msk          (0x1U << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
27662 #define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
27663 #define TIM_SR_CC3OF_Pos          (11U)
27664 #define TIM_SR_CC3OF_Msk          (0x1U << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
27665 #define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
27666 #define TIM_SR_CC4OF_Pos          (12U)
27667 #define TIM_SR_CC4OF_Msk          (0x1U << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
27668 #define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
27669 #define TIM_SR_CC5IF_Pos          (16U)
27670 #define TIM_SR_CC5IF_Msk          (0x1U << TIM_SR_CC5IF_Pos)                   /*!< 0x00010000 */
27671 #define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */
27672 #define TIM_SR_CC6IF_Pos          (17U)
27673 #define TIM_SR_CC6IF_Msk          (0x1U << TIM_SR_CC6IF_Pos)                   /*!< 0x00020000 */
27674 #define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */
27675 #define TIM_SR_SBIF_Pos           (13U)
27676 #define TIM_SR_SBIF_Msk           (0x1U << TIM_SR_SBIF_Pos)                    /*!< 0x00002000 */
27677 #define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!< System Break Flag */
27678 
27679 /*******************  Bit definition for TIM_EGR register  ********************/
27680 #define TIM_EGR_UG                ((uint16_t)0x0001)                           /*!<Update Generation */
27681 #define TIM_EGR_CC1G              ((uint16_t)0x0002)                           /*!<Capture/Compare 1 Generation */
27682 #define TIM_EGR_CC2G              ((uint16_t)0x0004)                           /*!<Capture/Compare 2 Generation */
27683 #define TIM_EGR_CC3G              ((uint16_t)0x0008)                           /*!<Capture/Compare 3 Generation */
27684 #define TIM_EGR_CC4G              ((uint16_t)0x0010)                           /*!<Capture/Compare 4 Generation */
27685 #define TIM_EGR_COMG              ((uint16_t)0x0020)                           /*!<Capture/Compare Control Update Generation */
27686 #define TIM_EGR_TG                ((uint16_t)0x0040)                           /*!<Trigger Generation */
27687 #define TIM_EGR_BG                ((uint16_t)0x0080)                           /*!<Break Generation */
27688 #define TIM_EGR_B2G               ((uint16_t)0x0100)                           /*!<Break Generation */
27689 
27690 
27691 /******************  Bit definition for TIM_CCMR1 register  *******************/
27692 #define TIM_CCMR1_CC1S_Pos        (0U)
27693 #define TIM_CCMR1_CC1S_Msk        (0x3U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
27694 #define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
27695 #define TIM_CCMR1_CC1S_0          (0x1U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
27696 #define TIM_CCMR1_CC1S_1          (0x2U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
27697 
27698 #define TIM_CCMR1_OC1FE_Pos       (2U)
27699 #define TIM_CCMR1_OC1FE_Msk       (0x1U << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
27700 #define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
27701 #define TIM_CCMR1_OC1PE_Pos       (3U)
27702 #define TIM_CCMR1_OC1PE_Msk       (0x1U << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
27703 #define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
27704 
27705 #define TIM_CCMR1_OC1M_Pos        (4U)
27706 #define TIM_CCMR1_OC1M_Msk        (0x1007U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010070 */
27707 #define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
27708 #define TIM_CCMR1_OC1M_0          (0x0001U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000010 */
27709 #define TIM_CCMR1_OC1M_1          (0x0002U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000020 */
27710 #define TIM_CCMR1_OC1M_2          (0x0004U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000040 */
27711 #define TIM_CCMR1_OC1M_3          (0x1000U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010000 */
27712 
27713 #define TIM_CCMR1_OC1CE_Pos       (7U)
27714 #define TIM_CCMR1_OC1CE_Msk       (0x1U << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
27715 #define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */
27716 
27717 #define TIM_CCMR1_CC2S_Pos        (8U)
27718 #define TIM_CCMR1_CC2S_Msk        (0x3U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
27719 #define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
27720 #define TIM_CCMR1_CC2S_0          (0x1U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
27721 #define TIM_CCMR1_CC2S_1          (0x2U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
27722 
27723 #define TIM_CCMR1_OC2FE_Pos       (10U)
27724 #define TIM_CCMR1_OC2FE_Msk       (0x1U << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
27725 #define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
27726 #define TIM_CCMR1_OC2PE_Pos       (11U)
27727 #define TIM_CCMR1_OC2PE_Msk       (0x1U << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
27728 #define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
27729 
27730 #define TIM_CCMR1_OC2M_Pos        (12U)
27731 #define TIM_CCMR1_OC2M_Msk        (0x1007U << TIM_CCMR1_OC2M_Pos)              /*!< 0x01007000 */
27732 #define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
27733 #define TIM_CCMR1_OC2M_0          (0x0001U << TIM_CCMR1_OC2M_Pos)              /*!< 0x00001000 */
27734 #define TIM_CCMR1_OC2M_1          (0x0002U << TIM_CCMR1_OC2M_Pos)              /*!< 0x00002000 */
27735 #define TIM_CCMR1_OC2M_2          (0x0004U << TIM_CCMR1_OC2M_Pos)              /*!< 0x00004000 */
27736 #define TIM_CCMR1_OC2M_3          (0x1000U << TIM_CCMR1_OC2M_Pos)              /*!< 0x01000000 */
27737 
27738 #define TIM_CCMR1_OC2CE_Pos       (15U)
27739 #define TIM_CCMR1_OC2CE_Msk       (0x1U << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
27740 #define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
27741 
27742 /*----------------------------------------------------------------------------*/
27743 
27744 #define TIM_CCMR1_IC1PSC_Pos      (2U)
27745 #define TIM_CCMR1_IC1PSC_Msk      (0x3U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
27746 #define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
27747 #define TIM_CCMR1_IC1PSC_0        (0x1U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */
27748 #define TIM_CCMR1_IC1PSC_1        (0x2U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */
27749 
27750 #define TIM_CCMR1_IC1F_Pos        (4U)
27751 #define TIM_CCMR1_IC1F_Msk        (0xFU << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
27752 #define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
27753 #define TIM_CCMR1_IC1F_0          (0x1U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */
27754 #define TIM_CCMR1_IC1F_1          (0x2U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */
27755 #define TIM_CCMR1_IC1F_2          (0x4U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */
27756 #define TIM_CCMR1_IC1F_3          (0x8U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */
27757 
27758 #define TIM_CCMR1_IC2PSC_Pos      (10U)
27759 #define TIM_CCMR1_IC2PSC_Msk      (0x3U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
27760 #define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
27761 #define TIM_CCMR1_IC2PSC_0        (0x1U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */
27762 #define TIM_CCMR1_IC2PSC_1        (0x2U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */
27763 
27764 #define TIM_CCMR1_IC2F_Pos        (12U)
27765 #define TIM_CCMR1_IC2F_Msk        (0xFU << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
27766 #define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
27767 #define TIM_CCMR1_IC2F_0          (0x1U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */
27768 #define TIM_CCMR1_IC2F_1          (0x2U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */
27769 #define TIM_CCMR1_IC2F_2          (0x4U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */
27770 #define TIM_CCMR1_IC2F_3          (0x8U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */
27771 
27772 /******************  Bit definition for TIM_CCMR2 register  *******************/
27773 #define TIM_CCMR2_CC3S_Pos        (0U)
27774 #define TIM_CCMR2_CC3S_Msk        (0x3U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
27775 #define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
27776 #define TIM_CCMR2_CC3S_0          (0x1U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
27777 #define TIM_CCMR2_CC3S_1          (0x2U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
27778 
27779 #define TIM_CCMR2_OC3FE_Pos       (2U)
27780 #define TIM_CCMR2_OC3FE_Msk       (0x1U << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
27781 #define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
27782 #define TIM_CCMR2_OC3PE_Pos       (3U)
27783 #define TIM_CCMR2_OC3PE_Msk       (0x1U << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
27784 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
27785 
27786 #define TIM_CCMR2_OC3M_Pos        (4U)
27787 #define TIM_CCMR2_OC3M_Msk        (0x1007U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010070 */
27788 #define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
27789 #define TIM_CCMR2_OC3M_0          (0x0001U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00000010 */
27790 #define TIM_CCMR2_OC3M_1          (0x0002U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00000020 */
27791 #define TIM_CCMR2_OC3M_2          (0x0004U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00000040 */
27792 #define TIM_CCMR2_OC3M_3          (0x1000U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010000 */
27793 
27794 #define TIM_CCMR2_OC3CE_Pos       (7U)
27795 #define TIM_CCMR2_OC3CE_Msk       (0x1U << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
27796 #define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
27797 
27798 #define TIM_CCMR2_CC4S_Pos        (8U)
27799 #define TIM_CCMR2_CC4S_Msk        (0x3U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
27800 #define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
27801 #define TIM_CCMR2_CC4S_0          (0x1U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
27802 #define TIM_CCMR2_CC4S_1          (0x2U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
27803 
27804 #define TIM_CCMR2_OC4FE_Pos       (10U)
27805 #define TIM_CCMR2_OC4FE_Msk       (0x1U << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
27806 #define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
27807 #define TIM_CCMR2_OC4PE_Pos       (11U)
27808 #define TIM_CCMR2_OC4PE_Msk       (0x1U << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
27809 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
27810 
27811 #define TIM_CCMR2_OC4M_Pos        (12U)
27812 #define TIM_CCMR2_OC4M_Msk        (0x1007U << TIM_CCMR2_OC4M_Pos)              /*!< 0x01007000 */
27813 #define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
27814 #define TIM_CCMR2_OC4M_0          (0x0001U << TIM_CCMR2_OC4M_Pos)              /*!< 0x00001000 */
27815 #define TIM_CCMR2_OC4M_1          (0x0002U << TIM_CCMR2_OC4M_Pos)              /*!< 0x00002000 */
27816 #define TIM_CCMR2_OC4M_2          (0x0004U << TIM_CCMR2_OC4M_Pos)              /*!< 0x00004000 */
27817 #define TIM_CCMR2_OC4M_3          (0x1000U << TIM_CCMR2_OC4M_Pos)              /*!< 0x01000000 */
27818 
27819 #define TIM_CCMR2_OC4CE_Pos       (15U)
27820 #define TIM_CCMR2_OC4CE_Msk       (0x1U << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
27821 #define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
27822 
27823 /*----------------------------------------------------------------------------*/
27824 
27825 #define TIM_CCMR2_IC3PSC          ((uint16_t)0x0000000C)                       /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
27826 #define TIM_CCMR2_IC3PSC_0        ((uint16_t)0x00000004)                       /*!<Bit 0 */
27827 #define TIM_CCMR2_IC3PSC_1        ((uint16_t)0x00000008)                       /*!<Bit 1 */
27828 
27829 #define TIM_CCMR2_IC3F            ((uint16_t)0x000000F0)                       /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
27830 #define TIM_CCMR2_IC3F_0          ((uint16_t)0x00000010)                       /*!<Bit 0 */
27831 #define TIM_CCMR2_IC3F_1          ((uint16_t)0x00000020)                       /*!<Bit 1 */
27832 #define TIM_CCMR2_IC3F_2          ((uint16_t)0x00000040)                       /*!<Bit 2 */
27833 #define TIM_CCMR2_IC3F_3          ((uint16_t)0x00000080)                       /*!<Bit 3 */
27834 
27835 #define TIM_CCMR2_IC4PSC          ((uint16_t)0x00000C00)                       /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
27836 #define TIM_CCMR2_IC4PSC_0        ((uint16_t)0x00000400)                       /*!<Bit 0 */
27837 #define TIM_CCMR2_IC4PSC_1        ((uint16_t)0x00000800)                       /*!<Bit 1 */
27838 
27839 #define TIM_CCMR2_IC4F            ((uint16_t)0x0000F000)                       /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
27840 #define TIM_CCMR2_IC4F_0          ((uint16_t)0x00001000)                       /*!<Bit 0 */
27841 #define TIM_CCMR2_IC4F_1          ((uint16_t)0x00002000)                       /*!<Bit 1 */
27842 #define TIM_CCMR2_IC4F_2          ((uint16_t)0x00004000)                       /*!<Bit 2 */
27843 #define TIM_CCMR2_IC4F_3          ((uint16_t)0x00008000)                       /*!<Bit 3 */
27844 
27845 /*******************  Bit definition for TIM_CCER register  *******************/
27846 #define TIM_CCER_CC1E_Pos         (0U)
27847 #define TIM_CCER_CC1E_Msk         (0x1U << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
27848 #define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
27849 #define TIM_CCER_CC1P_Pos         (1U)
27850 #define TIM_CCER_CC1P_Msk         (0x1U << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
27851 #define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
27852 #define TIM_CCER_CC1NE_Pos        (2U)
27853 #define TIM_CCER_CC1NE_Msk        (0x1U << TIM_CCER_CC1NE_Pos)                 /*!< 0x00000004 */
27854 #define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */
27855 #define TIM_CCER_CC1NP_Pos        (3U)
27856 #define TIM_CCER_CC1NP_Msk        (0x1U << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
27857 #define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
27858 #define TIM_CCER_CC2E_Pos         (4U)
27859 #define TIM_CCER_CC2E_Msk         (0x1U << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
27860 #define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
27861 #define TIM_CCER_CC2P_Pos         (5U)
27862 #define TIM_CCER_CC2P_Msk         (0x1U << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
27863 #define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
27864 #define TIM_CCER_CC2NE_Pos        (6U)
27865 #define TIM_CCER_CC2NE_Msk        (0x1U << TIM_CCER_CC2NE_Pos)                 /*!< 0x00000040 */
27866 #define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */
27867 #define TIM_CCER_CC2NP_Pos        (7U)
27868 #define TIM_CCER_CC2NP_Msk        (0x1U << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
27869 #define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
27870 #define TIM_CCER_CC3E_Pos         (8U)
27871 #define TIM_CCER_CC3E_Msk         (0x1U << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
27872 #define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
27873 #define TIM_CCER_CC3P_Pos         (9U)
27874 #define TIM_CCER_CC3P_Msk         (0x1U << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
27875 #define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
27876 #define TIM_CCER_CC3NE_Pos        (10U)
27877 #define TIM_CCER_CC3NE_Msk        (0x1U << TIM_CCER_CC3NE_Pos)                 /*!< 0x00000400 */
27878 #define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */
27879 #define TIM_CCER_CC3NP_Pos        (11U)
27880 #define TIM_CCER_CC3NP_Msk        (0x1U << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
27881 #define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
27882 #define TIM_CCER_CC4E_Pos         (12U)
27883 #define TIM_CCER_CC4E_Msk         (0x1U << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
27884 #define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
27885 #define TIM_CCER_CC4P_Pos         (13U)
27886 #define TIM_CCER_CC4P_Msk         (0x1U << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
27887 #define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
27888 #define TIM_CCER_CC4NP_Pos        (15U)
27889 #define TIM_CCER_CC4NP_Msk        (0x1U << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
27890 #define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
27891 #define TIM_CCER_CC5E_Pos         (16U)
27892 #define TIM_CCER_CC5E_Msk         (0x1U << TIM_CCER_CC5E_Pos)                  /*!< 0x00010000 */
27893 #define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */
27894 #define TIM_CCER_CC5P_Pos         (17U)
27895 #define TIM_CCER_CC5P_Msk         (0x1U << TIM_CCER_CC5P_Pos)                  /*!< 0x00020000 */
27896 #define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */
27897 #define TIM_CCER_CC6E_Pos         (20U)
27898 #define TIM_CCER_CC6E_Msk         (0x1U << TIM_CCER_CC6E_Pos)                  /*!< 0x00100000 */
27899 #define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */
27900 #define TIM_CCER_CC6P_Pos         (21U)
27901 #define TIM_CCER_CC6P_Msk         (0x1U << TIM_CCER_CC6P_Pos)                  /*!< 0x00200000 */
27902 #define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */
27903 /*******************  Bit definition for TIM_CNT register  ********************/
27904 #define TIM_CNT_CNT_Pos           (0U)
27905 #define TIM_CNT_CNT_Msk           (0xFFFFFFFFU << TIM_CNT_CNT_Pos)             /*!< 0xFFFFFFFF */
27906 #define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
27907 #define TIM_CNT_UIFCPY_Pos        (31U)
27908 #define TIM_CNT_UIFCPY_Msk        (0x1U << TIM_CNT_UIFCPY_Pos)                 /*!< 0x80000000 */
27909 #define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy */
27910 /*******************  Bit definition for TIM_PSC register  ********************/
27911 #define TIM_PSC_PSC               ((uint16_t)0xFFFF)                           /*!<Prescaler Value */
27912 
27913 /*******************  Bit definition for TIM_ARR register  ********************/
27914 #define TIM_ARR_ARR_Pos           (0U)
27915 #define TIM_ARR_ARR_Msk           (0xFFFFFFFFU << TIM_ARR_ARR_Pos)             /*!< 0xFFFFFFFF */
27916 #define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
27917 
27918 /*******************  Bit definition for TIM_RCR register  ********************/
27919 #define TIM_RCR_REP               ((uint8_t)0xFF)                              /*!<Repetition Counter Value */
27920 
27921 /*******************  Bit definition for TIM_CCR1 register  *******************/
27922 #define TIM_CCR1_CCR1             ((uint16_t)0xFFFF)                           /*!<Capture/Compare 1 Value */
27923 
27924 /*******************  Bit definition for TIM_CCR2 register  *******************/
27925 #define TIM_CCR2_CCR2             ((uint16_t)0xFFFF)                           /*!<Capture/Compare 2 Value */
27926 
27927 /*******************  Bit definition for TIM_CCR3 register  *******************/
27928 #define TIM_CCR3_CCR3             ((uint16_t)0xFFFF)                           /*!<Capture/Compare 3 Value */
27929 
27930 /*******************  Bit definition for TIM_CCR4 register  *******************/
27931 #define TIM_CCR4_CCR4             ((uint16_t)0xFFFF)                           /*!<Capture/Compare 4 Value */
27932 
27933 /*******************  Bit definition for TIM_CCR5 register  *******************/
27934 #define TIM_CCR5_CCR5_Pos         (0U)
27935 #define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFU << TIM_CCR5_CCR5_Pos)           /*!< 0xFFFFFFFF */
27936 #define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */
27937 #define TIM_CCR5_GC5C1_Pos        (29U)
27938 #define TIM_CCR5_GC5C1_Msk        (0x1U << TIM_CCR5_GC5C1_Pos)                 /*!< 0x20000000 */
27939 #define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */
27940 #define TIM_CCR5_GC5C2_Pos        (30U)
27941 #define TIM_CCR5_GC5C2_Msk        (0x1U << TIM_CCR5_GC5C2_Pos)                 /*!< 0x40000000 */
27942 #define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */
27943 #define TIM_CCR5_GC5C3_Pos        (31U)
27944 #define TIM_CCR5_GC5C3_Msk        (0x1U << TIM_CCR5_GC5C3_Pos)                 /*!< 0x80000000 */
27945 #define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */
27946 
27947 /*******************  Bit definition for TIM_CCR6 register  *******************/
27948 #define TIM_CCR6_CCR6             ((uint16_t)0xFFFF)                           /*!<Capture/Compare 6 Value */
27949 
27950 /*******************  Bit definition for TIM_BDTR register  *******************/
27951 #define TIM_BDTR_DTG_Pos          (0U)
27952 #define TIM_BDTR_DTG_Msk          (0xFFU << TIM_BDTR_DTG_Pos)                  /*!< 0x000000FF */
27953 #define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
27954 #define TIM_BDTR_DTG_0            (0x01U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000001 */
27955 #define TIM_BDTR_DTG_1            (0x02U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000002 */
27956 #define TIM_BDTR_DTG_2            (0x04U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000004 */
27957 #define TIM_BDTR_DTG_3            (0x08U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000008 */
27958 #define TIM_BDTR_DTG_4            (0x10U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000010 */
27959 #define TIM_BDTR_DTG_5            (0x20U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000020 */
27960 #define TIM_BDTR_DTG_6            (0x40U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000040 */
27961 #define TIM_BDTR_DTG_7            (0x80U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000080 */
27962 
27963 #define TIM_BDTR_LOCK_Pos         (8U)
27964 #define TIM_BDTR_LOCK_Msk         (0x3U << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000300 */
27965 #define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
27966 #define TIM_BDTR_LOCK_0           (0x1U << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000100 */
27967 #define TIM_BDTR_LOCK_1           (0x2U << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000200 */
27968 
27969 #define TIM_BDTR_OSSI_Pos         (10U)
27970 #define TIM_BDTR_OSSI_Msk         (0x1U << TIM_BDTR_OSSI_Pos)                  /*!< 0x00000400 */
27971 #define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
27972 #define TIM_BDTR_OSSR_Pos         (11U)
27973 #define TIM_BDTR_OSSR_Msk         (0x1U << TIM_BDTR_OSSR_Pos)                  /*!< 0x00000800 */
27974 #define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
27975 #define TIM_BDTR_BKE_Pos          (12U)
27976 #define TIM_BDTR_BKE_Msk          (0x1U << TIM_BDTR_BKE_Pos)                   /*!< 0x00001000 */
27977 #define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break1 */
27978 #define TIM_BDTR_BKP_Pos          (13U)
27979 #define TIM_BDTR_BKP_Msk          (0x1U << TIM_BDTR_BKP_Pos)                   /*!< 0x00002000 */
27980 #define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break1 */
27981 #define TIM_BDTR_AOE_Pos          (14U)
27982 #define TIM_BDTR_AOE_Msk          (0x1U << TIM_BDTR_AOE_Pos)                   /*!< 0x00004000 */
27983 #define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
27984 #define TIM_BDTR_MOE_Pos          (15U)
27985 #define TIM_BDTR_MOE_Msk          (0x1U << TIM_BDTR_MOE_Pos)                   /*!< 0x00008000 */
27986 #define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
27987 
27988 #define TIM_BDTR_BKF_Pos          (16U)
27989 #define TIM_BDTR_BKF_Msk          (0xFU << TIM_BDTR_BKF_Pos)                   /*!< 0x000F0000 */
27990 #define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break1 */
27991 #define TIM_BDTR_BK2F_Pos         (20U)
27992 #define TIM_BDTR_BK2F_Msk         (0xFU << TIM_BDTR_BK2F_Pos)                  /*!< 0x00F00000 */
27993 #define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break2 */
27994 
27995 #define TIM_BDTR_BK2E_Pos         (24U)
27996 #define TIM_BDTR_BK2E_Msk         (0x1U << TIM_BDTR_BK2E_Pos)                  /*!< 0x01000000 */
27997 #define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break2 */
27998 #define TIM_BDTR_BK2P_Pos         (25U)
27999 #define TIM_BDTR_BK2P_Msk         (0x1U << TIM_BDTR_BK2P_Pos)                  /*!< 0x02000000 */
28000 #define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break2 */
28001 
28002 #define TIM_BDTR_BKDSRM_Pos       (26U)
28003 #define TIM_BDTR_BKDSRM_Msk       (0x1U << TIM_BDTR_BKDSRM_Pos)                /*!< 0x04000000 */
28004 #define TIM_BDTR_BKDSRM           TIM_BDTR_BKDSRM_Msk                          /*!<Break Disarmed for Break1 */
28005 #define TIM_BDTR_BK2DSRM_Pos      (27U)
28006 #define TIM_BDTR_BK2DSRM_Msk      (0x1U << TIM_BDTR_BK2DSRM_Pos)               /*!< 0x08000000 */
28007 #define TIM_BDTR_BK2DSRM          TIM_BDTR_BK2DSRM_Msk                         /*!<Break Disarmed for Break2 */
28008 
28009 #define TIM_BDTR_BKBID_Pos        (28U)
28010 #define TIM_BDTR_BKBID_Msk        (0x1U << TIM_BDTR_BKBID_Pos)                 /*!< 0x10000000 */
28011 #define TIM_BDTR_BKBID            TIM_BDTR_BKBID_Msk                           /*!<Break Bidirectionnal for Break1 */
28012 #define TIM_BDTR_BK2BID_Pos       (29U)
28013 #define TIM_BDTR_BK2BID_Msk       (0x1U << TIM_BDTR_BK2BID_Pos)                /*!< 0x20000000 */
28014 #define TIM_BDTR_BK2BID           TIM_BDTR_BK2BID_Msk                          /*!<Break Bidirectionnal for Break2 */
28015 
28016 /*******************  Bit definition for TIM_DCR register  ********************/
28017 #define TIM_DCR_DBA               ((uint16_t)0x001F)                           /*!<DBA[4:0] bits (DMA Base Address) */
28018 #define TIM_DCR_DBA_0             ((uint16_t)0x0001)                           /*!<Bit 0 */
28019 #define TIM_DCR_DBA_1             ((uint16_t)0x0002)                           /*!<Bit 1 */
28020 #define TIM_DCR_DBA_2             ((uint16_t)0x0004)                           /*!<Bit 2 */
28021 #define TIM_DCR_DBA_3             ((uint16_t)0x0008)                           /*!<Bit 3 */
28022 #define TIM_DCR_DBA_4             ((uint16_t)0x0010)                           /*!<Bit 4 */
28023 
28024 #define TIM_DCR_DBL               ((uint16_t)0x1F00)                           /*!<DBL[4:0] bits (DMA Burst Length) */
28025 #define TIM_DCR_DBL_0             ((uint16_t)0x0100)                           /*!<Bit 0 */
28026 #define TIM_DCR_DBL_1             ((uint16_t)0x0200)                           /*!<Bit 1 */
28027 #define TIM_DCR_DBL_2             ((uint16_t)0x0400)                           /*!<Bit 2 */
28028 #define TIM_DCR_DBL_3             ((uint16_t)0x0800)                           /*!<Bit 3 */
28029 #define TIM_DCR_DBL_4             ((uint16_t)0x1000)                           /*!<Bit 4 */
28030 
28031 /*******************  Bit definition for TIM_DMAR register  *******************/
28032 #define TIM_DMAR_DMAB             ((uint16_t)0xFFFF)                           /*!<DMA register for burst accesses */
28033 
28034 /*******************  Bit definition for TIM16_OR register  *********************/
28035 #define TIM16_OR_TI1_RMP            ((uint16_t)0x00C0)                         /*!<TI1_RMP[1:0] bits (TIM16 Input 1 remap) */
28036 #define TIM16_OR_TI1_RMP_0          ((uint16_t)0x0040)                         /*!<Bit 0 */
28037 #define TIM16_OR_TI1_RMP_1          ((uint16_t)0x0080)                         /*!<Bit 1 */
28038 
28039 /*******************  Bit definition for TIM1_OR register  *********************/
28040 #define TIM1_OR_ETR_RMP            ((uint16_t)0x000F)                          /*!<ETR_RMP[3:0] bits (TIM1 ETR remap) */
28041 #define TIM1_OR_ETR_RMP_0          ((uint16_t)0x0001)                          /*!<Bit 0 */
28042 #define TIM1_OR_ETR_RMP_1          ((uint16_t)0x0002)                          /*!<Bit 1 */
28043 #define TIM1_OR_ETR_RMP_2          ((uint16_t)0x0004)                          /*!<Bit 2 */
28044 #define TIM1_OR_ETR_RMP_3          ((uint16_t)0x0008)                          /*!<Bit 3 */
28045 
28046 /*******************  Bit definition for TIM8_OR register  *********************/
28047 #define TIM8_OR_ETR_RMP            ((uint16_t)0x000F)                          /*!<ETR_RMP[3:0] bits (TIM8 ETR remap) */
28048 #define TIM8_OR_ETR_RMP_0          ((uint16_t)0x0001)                          /*!<Bit 0 */
28049 #define TIM8_OR_ETR_RMP_1          ((uint16_t)0x0002)                          /*!<Bit 1 */
28050 #define TIM8_OR_ETR_RMP_2          ((uint16_t)0x0004)                          /*!<Bit 2 */
28051 #define TIM8_OR_ETR_RMP_3          ((uint16_t)0x0008)                          /*!<Bit 3 */
28052 
28053 /******************  Bit definition for TIM_CCMR3 register  *******************/
28054 #define TIM_CCMR3_OC5FE_Pos       (2U)
28055 #define TIM_CCMR3_OC5FE_Msk       (0x1U << TIM_CCMR3_OC5FE_Pos)                /*!< 0x00000004 */
28056 #define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */
28057 #define TIM_CCMR3_OC5PE_Pos       (3U)
28058 #define TIM_CCMR3_OC5PE_Msk       (0x1U << TIM_CCMR3_OC5PE_Pos)                /*!< 0x00000008 */
28059 #define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
28060 
28061 #define TIM_CCMR3_OC5M_Pos        (4U)
28062 #define TIM_CCMR3_OC5M_Msk        (0x1007U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010070 */
28063 #define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
28064 #define TIM_CCMR3_OC5M_0          (0x0001U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000010 */
28065 #define TIM_CCMR3_OC5M_1          (0x0002U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000020 */
28066 #define TIM_CCMR3_OC5M_2          (0x0004U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000040 */
28067 #define TIM_CCMR3_OC5M_3          (0x1000U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010000 */
28068 
28069 #define TIM_CCMR3_OC5CE_Pos       (7U)
28070 #define TIM_CCMR3_OC5CE_Msk       (0x1U << TIM_CCMR3_OC5CE_Pos)                /*!< 0x00000080 */
28071 #define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */
28072 
28073 #define TIM_CCMR3_OC6FE_Pos       (10U)
28074 #define TIM_CCMR3_OC6FE_Msk       (0x1U << TIM_CCMR3_OC6FE_Pos)                /*!< 0x00000400 */
28075 #define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 4 Fast enable */
28076 #define TIM_CCMR3_OC6PE_Pos       (11U)
28077 #define TIM_CCMR3_OC6PE_Msk       (0x1U << TIM_CCMR3_OC6PE_Pos)                /*!< 0x00000800 */
28078 #define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 4 Preload enable */
28079 
28080 #define TIM_CCMR3_OC6M_Pos        (12U)
28081 #define TIM_CCMR3_OC6M_Msk        (0x1007U << TIM_CCMR3_OC6M_Pos)              /*!< 0x01007000 */
28082 #define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
28083 #define TIM_CCMR3_OC6M_0          (0x0001U << TIM_CCMR3_OC6M_Pos)              /*!< 0x00001000 */
28084 #define TIM_CCMR3_OC6M_1          (0x0002U << TIM_CCMR3_OC6M_Pos)              /*!< 0x00002000 */
28085 #define TIM_CCMR3_OC6M_2          (0x0004U << TIM_CCMR3_OC6M_Pos)              /*!< 0x00004000 */
28086 #define TIM_CCMR3_OC6M_3          (0x1000U << TIM_CCMR3_OC6M_Pos)              /*!< 0x01000000 */
28087 
28088 #define TIM_CCMR3_OC6CE_Pos       (15U)
28089 #define TIM_CCMR3_OC6CE_Msk       (0x1U << TIM_CCMR3_OC6CE_Pos)                /*!< 0x00008000 */
28090 #define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 4 Clear Enable */
28091 /*******************  Bit definition for TIM1_AF1 register  *********************/
28092 #define TIM1_AF1_BKINE_Pos         (0U)
28093 #define TIM1_AF1_BKINE_Msk         (0x1U << TIM1_AF1_BKINE_Pos)                /*!< 0x00000001 */
28094 #define TIM1_AF1_BKINE             TIM1_AF1_BKINE_Msk                          /*!<BKINE Break input enable bit */
28095 #define TIM1_AF1_BKDF1BK0E_Pos      (8U)
28096 #define TIM1_AF1_BKDF1BK0E_Msk      (0x1U << TIM1_AF1_BKDF1BK0E_Pos)             /*!< 0x00000100 */
28097 #define TIM1_AF1_BKDF1BK0E          TIM1_AF1_BKDF1BK0E_Msk                       /*!<BKDF1BK0E Break input DFSDM Break 0 */
28098 #define TIM1_AF1_BKINP_Pos         (9U)
28099 #define TIM1_AF1_BKINP_Msk         (0x1U << TIM1_AF1_BKINP_Pos)                /*!< 0x00000200 */
28100 #define TIM1_AF1_BKINP             TIM1_AF1_BKINP_Msk                          /*!<BRKINP Break input polarity */
28101 
28102 #define TIM1_AF1_ETRSEL_Pos       (14U)
28103 #define TIM1_AF1_ETRSEL_Msk       (0xFU << TIM1_AF1_ETRSEL_Pos)              /*!< 0x0003C000 */
28104 #define TIM1_AF1_ETRSEL           TIM1_AF1_ETRSEL_Msk                        /*!<ETRSEL[3:0] bits (TIM1 ETR SEL) */
28105 #define TIM1_AF1_ETRSEL_0         (0x1U << TIM1_AF1_ETRSEL_Pos)              /*!< 0x00004000 */
28106 #define TIM1_AF1_ETRSEL_1         (0x2U << TIM1_AF1_ETRSEL_Pos)              /*!< 0x00008000 */
28107 #define TIM1_AF1_ETRSEL_2         (0x4U << TIM1_AF1_ETRSEL_Pos)              /*!< 0x00010000 */
28108 #define TIM1_AF1_ETRSEL_3         (0x8U << TIM1_AF1_ETRSEL_Pos)              /*!< 0x00020000 */
28109 
28110 /*******************  Bit definition for TIM1_AF2 register  *********************/
28111 #define TIM1_AF2_BK2INE_Pos        (0U)
28112 #define TIM1_AF2_BK2INE_Msk        (0x1U << TIM1_AF2_BK2INE_Pos)               /*!< 0x00000001 */
28113 #define TIM1_AF2_BK2INE            TIM1_AF2_BK2INE_Msk                         /*!<BK2INE Break input 2 enable bit */
28114 #define TIM1_AF2_BK2DF1BK1E_Pos     (8U)
28115 #define TIM1_AF2_BK2DF1BK1E_Msk     (0x1U << TIM1_AF2_BK2DF1BK1E_Pos)            /*!< 0x00000100 */
28116 #define TIM1_AF2_BK2DF1BK1E         TIM1_AF2_BK2DF1BK1E_Msk                      /*!<BK2DF1BK1E Break input2 DFSDM Break 1 */
28117 #define TIM1_AF2_BK2INP_Pos        (9U)
28118 #define TIM1_AF2_BK2INP_Msk        (0x1U << TIM1_AF2_BK2INP_Pos)               /*!< 0x00000200 */
28119 #define TIM1_AF2_BK2INP            TIM1_AF2_BK2INP_Msk                         /*!<BRKINP Break2 input polarity */
28120 
28121 /*******************  Bit definition for TIM1_TISEL register  *********************/
28122 #define TIM1_TISEL_TI1SEL_Pos      (0U)
28123 #define TIM1_TISEL_TI1SEL_Msk      (0xFU << TIM1_TISEL_TI1SEL_Pos)             /*!< 0x0000000F */
28124 #define TIM1_TISEL_TI1SEL          TIM1_TISEL_TI1SEL_Msk                       /*!<TI1SEL[3:0] bits (TIM1 TI1 SEL)*/
28125 #define TIM1_TISEL_TI1SEL_0        (0x1U << TIM1_TISEL_TI1SEL_Pos)             /*!< 0x00000001 */
28126 #define TIM1_TISEL_TI1SEL_1        (0x2U << TIM1_TISEL_TI1SEL_Pos)             /*!< 0x00000002 */
28127 #define TIM1_TISEL_TI1SEL_2        (0x4U << TIM1_TISEL_TI1SEL_Pos)             /*!< 0x00000004 */
28128 #define TIM1_TISEL_TI1SEL_3        (0x8U << TIM1_TISEL_TI1SEL_Pos)             /*!< 0x00000008 */
28129 
28130 #define TIM1_TISEL_TI2SEL_Pos      (8U)
28131 #define TIM1_TISEL_TI2SEL_Msk      (0xFU << TIM1_TISEL_TI2SEL_Pos)             /*!< 0x00000F00 */
28132 #define TIM1_TISEL_TI2SEL          TIM1_TISEL_TI2SEL_Msk                       /*!<TI2SEL[3:0] bits (TIM1 TI2 SEL)*/
28133 #define TIM1_TISEL_TI2SEL_0        (0x1U << TIM1_TISEL_TI2SEL_Pos)             /*!< 0x00000100 */
28134 #define TIM1_TISEL_TI2SEL_1        (0x2U << TIM1_TISEL_TI2SEL_Pos)             /*!< 0x00000200 */
28135 #define TIM1_TISEL_TI2SEL_2        (0x4U << TIM1_TISEL_TI2SEL_Pos)             /*!< 0x00000400 */
28136 #define TIM1_TISEL_TI2SEL_3        (0x8U << TIM1_TISEL_TI2SEL_Pos)             /*!< 0x00000800 */
28137 
28138 #define TIM1_TISEL_TI3SEL_Pos      (16U)
28139 #define TIM1_TISEL_TI3SEL_Msk      (0xFU << TIM1_TISEL_TI3SEL_Pos)             /*!< 0x000F0000 */
28140 #define TIM1_TISEL_TI3SEL          TIM1_TISEL_TI3SEL_Msk                       /*!<TI3SEL[3:0] bits (TIM1 TI3 SEL)*/
28141 #define TIM1_TISEL_TI3SEL_0        (0x1U << TIM1_TISEL_TI3SEL_Pos)             /*!< 0x00010000 */
28142 #define TIM1_TISEL_TI3SEL_1        (0x2U << TIM1_TISEL_TI3SEL_Pos)             /*!< 0x00020000 */
28143 #define TIM1_TISEL_TI3SEL_2        (0x4U << TIM1_TISEL_TI3SEL_Pos)             /*!< 0x00040000 */
28144 #define TIM1_TISEL_TI3SEL_3        (0x8U << TIM1_TISEL_TI3SEL_Pos)             /*!< 0x00080000 */
28145 
28146 #define TIM1_TISEL_TI4SEL_Pos      (24U)
28147 #define TIM1_TISEL_TI4SEL_Msk      (0xFU << TIM1_TISEL_TI4SEL_Pos)             /*!< 0x0F000000 */
28148 #define TIM1_TISEL_TI4SEL          TIM1_TISEL_TI4SEL_Msk                       /*!<TI4SEL[3:0] bits (TIM1 TI4 SEL)*/
28149 #define TIM1_TISEL_TI4SEL_0        (0x1U << TIM1_TISEL_TI4SEL_Pos)             /*!< 0x01000000 */
28150 #define TIM1_TISEL_TI4SEL_1        (0x2U << TIM1_TISEL_TI4SEL_Pos)             /*!< 0x02000000 */
28151 #define TIM1_TISEL_TI4SEL_2        (0x4U << TIM1_TISEL_TI4SEL_Pos)             /*!< 0x04000000 */
28152 #define TIM1_TISEL_TI4SEL_3        (0x8U << TIM1_TISEL_TI4SEL_Pos)             /*!< 0x08000000 */
28153 
28154 /*******************  Bit definition for TIM8_AF1 register  *********************/
28155 #define TIM8_AF1_BKINE_Pos         (0U)
28156 #define TIM8_AF1_BKINE_Msk         (0x1U << TIM8_AF1_BKINE_Pos)                /*!< 0x00000001 */
28157 #define TIM8_AF1_BKINE             TIM8_AF1_BKINE_Msk                          /*!<BKINE Break input enable bit */
28158 #define TIM8_AF1_BKDFBK2E_Pos      (8U)
28159 #define TIM8_AF1_BKDFBK2E_Msk      (0x1U << TIM8_AF1_BKDFBK2E_Pos)             /*!< 0x00000100 */
28160 #define TIM8_AF1_BKDFBK2E          TIM8_AF1_BKDFBK2E_Msk                       /*!<BKDFBK2E Break input DFSDM Break 2 */
28161 #define TIM8_AF1_BKINP_Pos         (9U)
28162 #define TIM8_AF1_BKINP_Msk         (0x1U << TIM8_AF1_BKINP_Pos)                /*!< 0x00000200 */
28163 #define TIM8_AF1_BKINP             TIM8_AF1_BKINP_Msk                          /*!<BRKINP Break input polarity */
28164 
28165 #define TIM8_AF1_ETRSEL_Pos       (14U)
28166 #define TIM8_AF1_ETRSEL_Msk       (0xFU << TIM8_AF1_ETRSEL_Pos)              /*!< 0x0003C000 */
28167 #define TIM8_AF1_ETRSEL           TIM8_AF1_ETRSEL_Msk                        /*!<ETRSEL[3:0] bits (TIM8 ETR SEL) */
28168 #define TIM8_AF1_ETRSEL_0         (0x1U << TIM8_AF1_ETRSEL_Pos)              /*!< 0x00004000 */
28169 #define TIM8_AF1_ETRSEL_1         (0x2U << TIM8_AF1_ETRSEL_Pos)              /*!< 0x00008000 */
28170 #define TIM8_AF1_ETRSEL_2         (0x4U << TIM8_AF1_ETRSEL_Pos)              /*!< 0x00010000 */
28171 #define TIM8_AF1_ETRSEL_3         (0x8U << TIM8_AF1_ETRSEL_Pos)              /*!< 0x00020000 */
28172 /*******************  Bit definition for TIM8_AF2 register  *********************/
28173 #define TIM8_AF2_BK2INE_Pos        (0U)
28174 #define TIM8_AF2_BK2INE_Msk        (0x1U << TIM8_AF2_BK2INE_Pos)               /*!< 0x00000001 */
28175 #define TIM8_AF2_BK2INE            TIM8_AF2_BK2INE_Msk                         /*!<BK2INE Break input 2 enable bit */
28176 #define TIM8_AF2_BK2DFBK3E_Pos     (8U)
28177 #define TIM8_AF2_BK2DFBK3E_Msk     (0x1U << TIM8_AF2_BK2DFBK3E_Pos)            /*!< 0x00000100 */
28178 #define TIM8_AF2_BK2DFBK3E         TIM8_AF2_BK2DFBK3E_Msk                      /*!<BK2DFBK1E Break input2 DFSDM Break 3 */
28179 #define TIM8_AF2_BK2INP_Pos        (9U)
28180 #define TIM8_AF2_BK2INP_Msk        (0x1U << TIM8_AF2_BK2INP_Pos)               /*!< 0x00000200 */
28181 #define TIM8_AF2_BK2INP            TIM8_AF2_BK2INP_Msk                         /*!<BRKINP Break2 input polarity */
28182 
28183 /*******************  Bit definition for TIM8_TISEL register  *********************/
28184 #define TIM8_TISEL_TI1SEL_Pos      (0U)
28185 #define TIM8_TISEL_TI1SEL_Msk      (0xFU << TIM8_TISEL_TI1SEL_Pos)             /*!< 0x0000000F */
28186 #define TIM8_TISEL_TI1SEL          TIM8_TISEL_TI1SEL_Msk                       /*!<TI1SEL[3:0] bits (TIM8 TI1 SEL)*/
28187 #define TIM8_TISEL_TI1SEL_0        (0x1U << TIM8_TISEL_TI1SEL_Pos)             /*!< 0x00000001 */
28188 #define TIM8_TISEL_TI1SEL_1        (0x2U << TIM8_TISEL_TI1SEL_Pos)             /*!< 0x00000002 */
28189 #define TIM8_TISEL_TI1SEL_2        (0x4U << TIM8_TISEL_TI1SEL_Pos)             /*!< 0x00000004 */
28190 #define TIM8_TISEL_TI1SEL_3        (0x8U << TIM8_TISEL_TI1SEL_Pos)             /*!< 0x00000008 */
28191 
28192 #define TIM8_TISEL_TI2SEL_Pos      (8U)
28193 #define TIM8_TISEL_TI2SEL_Msk      (0xFU << TIM8_TISEL_TI2SEL_Pos)             /*!< 0x00000F00 */
28194 #define TIM8_TISEL_TI2SEL          TIM8_TISEL_TI2SEL_Msk                       /*!<TI2SEL[3:0] bits (TIM8 TI2 SEL)*/
28195 #define TIM8_TISEL_TI2SEL_0        (0x1U << TIM8_TISEL_TI2SEL_Pos)             /*!< 0x00000100 */
28196 #define TIM8_TISEL_TI2SEL_1        (0x2U << TIM8_TISEL_TI2SEL_Pos)             /*!< 0x00000200 */
28197 #define TIM8_TISEL_TI2SEL_2        (0x4U << TIM8_TISEL_TI2SEL_Pos)             /*!< 0x00000400 */
28198 #define TIM8_TISEL_TI2SEL_3        (0x8U << TIM8_TISEL_TI2SEL_Pos)             /*!< 0x00000800 */
28199 
28200 #define TIM8_TISEL_TI3SEL_Pos      (16U)
28201 #define TIM8_TISEL_TI3SEL_Msk      (0xFU << TIM8_TISEL_TI3SEL_Pos)             /*!< 0x000F0000 */
28202 #define TIM8_TISEL_TI3SEL          TIM8_TISEL_TI3SEL_Msk                       /*!<TI3SEL[3:0] bits (TIM8 TI3 SEL)*/
28203 #define TIM8_TISEL_TI3SEL_0        (0x1U << TIM8_TISEL_TI3SEL_Pos)             /*!< 0x00010000 */
28204 #define TIM8_TISEL_TI3SEL_1        (0x2U << TIM8_TISEL_TI3SEL_Pos)             /*!< 0x00020000 */
28205 #define TIM8_TISEL_TI3SEL_2        (0x4U << TIM8_TISEL_TI3SEL_Pos)             /*!< 0x00040000 */
28206 #define TIM8_TISEL_TI3SEL_3        (0x8U << TIM8_TISEL_TI3SEL_Pos)             /*!< 0x00080000 */
28207 
28208 #define TIM8_TISEL_TI4SEL_Pos      (24U)
28209 #define TIM8_TISEL_TI4SEL_Msk      (0xFU << TIM8_TISEL_TI4SEL_Pos)             /*!< 0x0F000000 */
28210 #define TIM8_TISEL_TI4SEL          TIM8_TISEL_TI4SEL_Msk                       /*!<TI4SEL[3:0] bits (TIM8 TI4 SEL)*/
28211 #define TIM8_TISEL_TI4SEL_0        (0x1U << TIM8_TISEL_TI4SEL_Pos)             /*!< 0x01000000 */
28212 #define TIM8_TISEL_TI4SEL_1        (0x2U << TIM8_TISEL_TI4SEL_Pos)             /*!< 0x02000000 */
28213 #define TIM8_TISEL_TI4SEL_2        (0x4U << TIM8_TISEL_TI4SEL_Pos)             /*!< 0x04000000 */
28214 #define TIM8_TISEL_TI4SEL_3        (0x8U << TIM8_TISEL_TI4SEL_Pos)             /*!< 0x08000000 */
28215 
28216 /*******************  Bit definition for TIM2_AF1 register  *********************/
28217 #define TIM2_AF1_ETRSEL_Pos       (14U)
28218 #define TIM2_AF1_ETRSEL_Msk       (0xFU << TIM2_AF1_ETRSEL_Pos)              /*!< 0x0003C000 */
28219 #define TIM2_AF1_ETRSEL           TIM2_AF1_ETRSEL_Msk                        /*!<ETRSEL[3:0] bits (TIM2 ETR SEL) */
28220 #define TIM2_AF1_ETRSEL_0         (0x1U << TIM2_AF1_ETRSEL_Pos)              /*!< 0x00004000 */
28221 #define TIM2_AF1_ETRSEL_1         (0x2U << TIM2_AF1_ETRSEL_Pos)              /*!< 0x00008000 */
28222 #define TIM2_AF1_ETRSEL_2         (0x4U << TIM2_AF1_ETRSEL_Pos)              /*!< 0x00010000 */
28223 #define TIM2_AF1_ETRSEL_3         (0x8U << TIM2_AF1_ETRSEL_Pos)              /*!< 0x00020000 */
28224 
28225 /*******************  Bit definition for TIM2_TISEL register  *********************/
28226 #define TIM2_TISEL_TI1SEL_Pos      (0U)
28227 #define TIM2_TISEL_TI1SEL_Msk      (0xFU << TIM2_TISEL_TI1SEL_Pos)             /*!< 0x0000000F */
28228 #define TIM2_TISEL_TI1SEL          TIM2_TISEL_TI1SEL_Msk                       /*!<TI1SEL[3:0] bits (TIM1 TI1 SEL)*/
28229 #define TIM2_TISEL_TI1SEL_0        (0x1U << TIM2_TISEL_TI1SEL_Pos)             /*!< 0x00000001 */
28230 #define TIM2_TISEL_TI1SEL_1        (0x2U << TIM2_TISEL_TI1SEL_Pos)             /*!< 0x00000002 */
28231 #define TIM2_TISEL_TI1SEL_2        (0x4U << TIM2_TISEL_TI1SEL_Pos)             /*!< 0x00000004 */
28232 #define TIM2_TISEL_TI1SEL_3        (0x8U << TIM2_TISEL_TI1SEL_Pos)             /*!< 0x00000008 */
28233 
28234 #define TIM2_TISEL_TI2SEL_Pos      (8U)
28235 #define TIM2_TISEL_TI2SEL_Msk      (0xFU << TIM2_TISEL_TI2SEL_Pos)             /*!< 0x00000F00 */
28236 #define TIM2_TISEL_TI2SEL          TIM2_TISEL_TI2SEL_Msk                       /*!<TI2SEL[3:0] bits (TIM2 TI2 SEL)*/
28237 #define TIM2_TISEL_TI2SEL_0        (0x1U << TIM2_TISEL_TI2SEL_Pos)             /*!< 0x00000100 */
28238 #define TIM2_TISEL_TI2SEL_1        (0x2U << TIM2_TISEL_TI2SEL_Pos)             /*!< 0x00000200 */
28239 #define TIM2_TISEL_TI2SEL_2        (0x4U << TIM2_TISEL_TI2SEL_Pos)             /*!< 0x00000400 */
28240 #define TIM2_TISEL_TI2SEL_3        (0x8U << TIM2_TISEL_TI2SEL_Pos)             /*!< 0x00000800 */
28241 
28242 #define TIM2_TISEL_TI3SEL_Pos      (16U)
28243 #define TIM2_TISEL_TI3SEL_Msk      (0xFU << TIM2_TISEL_TI3SEL_Pos)             /*!< 0x000F0000 */
28244 #define TIM2_TISEL_TI3SEL          TIM2_TISEL_TI3SEL_Msk                       /*!<TI3SEL[3:0] bits (TIM2 TI3 SEL)*/
28245 #define TIM2_TISEL_TI3SEL_0        (0x1U << TIM2_TISEL_TI3SEL_Pos)             /*!< 0x00010000 */
28246 #define TIM2_TISEL_TI3SEL_1        (0x2U << TIM2_TISEL_TI3SEL_Pos)             /*!< 0x00020000 */
28247 #define TIM2_TISEL_TI3SEL_2        (0x4U << TIM2_TISEL_TI3SEL_Pos)             /*!< 0x00040000 */
28248 #define TIM2_TISEL_TI3SEL_3        (0x8U << TIM2_TISEL_TI3SEL_Pos)             /*!< 0x00080000 */
28249 
28250 #define TIM2_TISEL_TI4SEL_Pos      (24U)
28251 #define TIM2_TISEL_TI4SEL_Msk      (0xFU << TIM2_TISEL_TI4SEL_Pos)             /*!< 0x0F000000 */
28252 #define TIM2_TISEL_TI4SEL          TIM2_TISEL_TI4SEL_Msk                       /*!<TI4SEL[3:0] bits (TIM2 TI4 SEL)*/
28253 #define TIM2_TISEL_TI4SEL_0        (0x1U << TIM2_TISEL_TI4SEL_Pos)             /*!< 0x01000000 */
28254 #define TIM2_TISEL_TI4SEL_1        (0x2U << TIM2_TISEL_TI4SEL_Pos)             /*!< 0x02000000 */
28255 #define TIM2_TISEL_TI4SEL_2        (0x4U << TIM2_TISEL_TI4SEL_Pos)             /*!< 0x04000000 */
28256 #define TIM2_TISEL_TI4SEL_3        (0x8U << TIM2_TISEL_TI4SEL_Pos)             /*!< 0x08000000 */
28257 
28258 /*******************  Bit definition for TIM3_AF1 register  *********************/
28259 #define TIM3_AF1_ETRSEL_Pos       (14U)
28260 #define TIM3_AF1_ETRSEL_Msk       (0xFU << TIM3_AF1_ETRSEL_Pos)              /*!< 0x0003C000 */
28261 #define TIM3_AF1_ETRSEL           TIM3_AF1_ETRSEL_Msk                        /*!<ETRSEL[3:0] bits (TIM3 ETR SEL) */
28262 #define TIM3_AF1_ETRSEL_0         (0x1U << TIM3_AF1_ETRSEL_Pos)              /*!< 0x00004000 */
28263 #define TIM3_AF1_ETRSEL_1         (0x2U << TIM3_AF1_ETRSEL_Pos)              /*!< 0x00008000 */
28264 #define TIM3_AF1_ETRSEL_2         (0x4U << TIM3_AF1_ETRSEL_Pos)              /*!< 0x00010000 */
28265 #define TIM3_AF1_ETRSEL_3         (0x8U << TIM3_AF1_ETRSEL_Pos)              /*!< 0x00020000 */
28266 
28267 /*******************  Bit definition for TIM3_TISEL register  *********************/
28268 #define TIM3_TISEL_TI1SEL_Pos      (0U)
28269 #define TIM3_TISEL_TI1SEL_Msk      (0xFU << TIM3_TISEL_TI1SEL_Pos)             /*!< 0x0000000F */
28270 #define TIM3_TISEL_TI1SEL          TIM3_TISEL_TI1SEL_Msk                       /*!<TI1SEL[3:0] bits (TIM3 TI1 SEL)*/
28271 #define TIM3_TISEL_TI1SEL_0        (0x1U << TIM3_TISEL_TI1SEL_Pos)             /*!< 0x00000001 */
28272 #define TIM3_TISEL_TI1SEL_1        (0x2U << TIM3_TISEL_TI1SEL_Pos)             /*!< 0x00000002 */
28273 #define TIM3_TISEL_TI1SEL_2        (0x4U << TIM3_TISEL_TI1SEL_Pos)             /*!< 0x00000004 */
28274 #define TIM3_TISEL_TI1SEL_3        (0x8U << TIM3_TISEL_TI1SEL_Pos)             /*!< 0x00000008 */
28275 
28276 #define TIM3_TISEL_TI2SEL_Pos      (8U)
28277 #define TIM3_TISEL_TI2SEL_Msk      (0xFU << TIM3_TISEL_TI2SEL_Pos)             /*!< 0x00000F00 */
28278 #define TIM3_TISEL_TI2SEL          TIM3_TISEL_TI2SEL_Msk                       /*!<TI2SEL[3:0] bits (TIM3 TI2 SEL)*/
28279 #define TIM3_TISEL_TI2SEL_0        (0x1U << TIM3_TISEL_TI2SEL_Pos)             /*!< 0x00000100 */
28280 #define TIM3_TISEL_TI2SEL_1        (0x2U << TIM3_TISEL_TI2SEL_Pos)             /*!< 0x00000200 */
28281 #define TIM3_TISEL_TI2SEL_2        (0x4U << TIM3_TISEL_TI2SEL_Pos)             /*!< 0x00000400 */
28282 #define TIM3_TISEL_TI2SEL_3        (0x8U << TIM3_TISEL_TI2SEL_Pos)             /*!< 0x00000800 */
28283 
28284 #define TIM3_TISEL_TI3SEL_Pos      (16U)
28285 #define TIM3_TISEL_TI3SEL_Msk      (0xFU << TIM3_TISEL_TI3SEL_Pos)             /*!< 0x000F0000 */
28286 #define TIM3_TISEL_TI3SEL          TIM3_TISEL_TI3SEL_Msk                       /*!<TI3SEL[3:0] bits (TIM3 TI3 SEL)*/
28287 #define TIM3_TISEL_TI3SEL_0        (0x1U << TIM3_TISEL_TI3SEL_Pos)             /*!< 0x00010000 */
28288 #define TIM3_TISEL_TI3SEL_1        (0x2U << TIM3_TISEL_TI3SEL_Pos)             /*!< 0x00020000 */
28289 #define TIM3_TISEL_TI3SEL_2        (0x4U << TIM3_TISEL_TI3SEL_Pos)             /*!< 0x00040000 */
28290 #define TIM3_TISEL_TI3SEL_3        (0x8U << TIM3_TISEL_TI3SEL_Pos)             /*!< 0x00080000 */
28291 
28292 #define TIM3_TISEL_TI4SEL_Pos      (24U)
28293 #define TIM3_TISEL_TI4SEL_Msk      (0xFU << TIM3_TISEL_TI4SEL_Pos)             /*!< 0x0F000000 */
28294 #define TIM3_TISEL_TI4SEL          TIM3_TISEL_TI4SEL_Msk                       /*!<TI4SEL[3:0] bits (TIM3 TI4 SEL)*/
28295 #define TIM3_TISEL_TI4SEL_0        (0x1U << TIM3_TISEL_TI4SEL_Pos)             /*!< 0x01000000 */
28296 #define TIM3_TISEL_TI4SEL_1        (0x2U << TIM3_TISEL_TI4SEL_Pos)             /*!< 0x02000000 */
28297 #define TIM3_TISEL_TI4SEL_2        (0x4U << TIM3_TISEL_TI4SEL_Pos)             /*!< 0x04000000 */
28298 #define TIM3_TISEL_TI4SEL_3        (0x8U << TIM3_TISEL_TI4SEL_Pos)             /*!< 0x08000000 */
28299 
28300 /*******************  Bit definition for TIM4_AF1 register  *********************/
28301 #define TIM4_AF1_ETRSEL_Pos       (14U)
28302 #define TIM4_AF1_ETRSEL_Msk       (0xFU << TIM4_AF1_ETRSEL_Pos)              /*!< 0x0003C000 */
28303 #define TIM4_AF1_ETRSEL           TIM4_AF1_ETRSEL_Msk                        /*!<ETRSEL[3:0] bits (TIM4 ETR SEL) */
28304 #define TIM4_AF1_ETRSEL_0         (0x1U << TIM4_AF1_ETRSEL_Pos)              /*!< 0x00004000 */
28305 #define TIM4_AF1_ETRSEL_1         (0x2U << TIM4_AF1_ETRSEL_Pos)              /*!< 0x00008000 */
28306 #define TIM4_AF1_ETRSEL_2         (0x4U << TIM4_AF1_ETRSEL_Pos)              /*!< 0x00010000 */
28307 #define TIM4_AF1_ETRSEL_3         (0x8U << TIM4_AF1_ETRSEL_Pos)              /*!< 0x00020000 */
28308 
28309 /*******************  Bit definition for TIM4_TISEL register  *********************/
28310 #define TIM4_TISEL_TI1SEL_Pos      (0U)
28311 #define TIM4_TISEL_TI1SEL_Msk      (0xFU << TIM4_TISEL_TI1SEL_Pos)             /*!< 0x0000000F */
28312 #define TIM4_TISEL_TI1SEL          TIM4_TISEL_TI1SEL_Msk                       /*!<TI1SEL[3:0] bits (TIM4 TI1 SEL)*/
28313 #define TIM4_TISEL_TI1SEL_0        (0x1U << TIM4_TISEL_TI1SEL_Pos)             /*!< 0x00000001 */
28314 #define TIM4_TISEL_TI1SEL_1        (0x2U << TIM4_TISEL_TI1SEL_Pos)             /*!< 0x00000002 */
28315 #define TIM4_TISEL_TI1SEL_2        (0x4U << TIM4_TISEL_TI1SEL_Pos)             /*!< 0x00000004 */
28316 #define TIM4_TISEL_TI1SEL_3        (0x8U << TIM4_TISEL_TI1SEL_Pos)             /*!< 0x00000008 */
28317 
28318 #define TIM4_TISEL_TI2SEL_Pos      (8U)
28319 #define TIM4_TISEL_TI2SEL_Msk      (0xFU << TIM4_TISEL_TI2SEL_Pos)             /*!< 0x00000F00 */
28320 #define TIM4_TISEL_TI2SEL          TIM4_TISEL_TI2SEL_Msk                       /*!<TI2SEL[3:0] bits (TIM4 TI2 SEL)*/
28321 #define TIM4_TISEL_TI2SEL_0        (0x1U << TIM4_TISEL_TI2SEL_Pos)             /*!< 0x00000100 */
28322 #define TIM4_TISEL_TI2SEL_1        (0x2U << TIM4_TISEL_TI2SEL_Pos)             /*!< 0x00000200 */
28323 #define TIM4_TISEL_TI2SEL_2        (0x4U << TIM4_TISEL_TI2SEL_Pos)             /*!< 0x00000400 */
28324 #define TIM4_TISEL_TI2SEL_3        (0x8U << TIM4_TISEL_TI2SEL_Pos)             /*!< 0x00000800 */
28325 
28326 #define TIM4_TISEL_TI3SEL_Pos      (16U)
28327 #define TIM4_TISEL_TI3SEL_Msk      (0xFU << TIM4_TISEL_TI3SEL_Pos)             /*!< 0x000F0000 */
28328 #define TIM4_TISEL_TI3SEL          TIM4_TISEL_TI3SEL_Msk                       /*!<TI3SEL[3:0] bits (TIM4 TI3 SEL)*/
28329 #define TIM4_TISEL_TI3SEL_0        (0x1U << TIM4_TISEL_TI3SEL_Pos)             /*!< 0x00010000 */
28330 #define TIM4_TISEL_TI3SEL_1        (0x2U << TIM4_TISEL_TI3SEL_Pos)             /*!< 0x00020000 */
28331 #define TIM4_TISEL_TI3SEL_2        (0x4U << TIM4_TISEL_TI3SEL_Pos)             /*!< 0x00040000 */
28332 #define TIM4_TISEL_TI3SEL_3        (0x8U << TIM4_TISEL_TI3SEL_Pos)             /*!< 0x00080000 */
28333 
28334 #define TIM4_TISEL_TI4SEL_Pos      (24U)
28335 #define TIM4_TISEL_TI4SEL_Msk      (0xFU << TIM4_TISEL_TI4SEL_Pos)             /*!< 0x0F000000 */
28336 #define TIM4_TISEL_TI4SEL          TIM4_TISEL_TI4SEL_Msk                       /*!<TI4SEL[3:0] bits (TIM4 TI4 SEL)*/
28337 #define TIM4_TISEL_TI4SEL_0        (0x1U << TIM4_TISEL_TI4SEL_Pos)             /*!< 0x01000000 */
28338 #define TIM4_TISEL_TI4SEL_1        (0x2U << TIM4_TISEL_TI4SEL_Pos)             /*!< 0x02000000 */
28339 #define TIM4_TISEL_TI4SEL_2        (0x4U << TIM4_TISEL_TI4SEL_Pos)             /*!< 0x04000000 */
28340 #define TIM4_TISEL_TI4SEL_3        (0x8U << TIM4_TISEL_TI4SEL_Pos)             /*!< 0x08000000 */
28341 
28342 /*******************  Bit definition for TIM5_AF1 register  *********************/
28343 #define TIM5_AF1_ETRSEL_Pos       (14U)
28344 #define TIM5_AF1_ETRSEL_Msk       (0xFU << TIM5_AF1_ETRSEL_Pos)              /*!< 0x0003C000 */
28345 #define TIM5_AF1_ETRSEL           TIM5_AF1_ETRSEL_Msk                        /*!<ETRSEL[3:0] bits (TIM5 ETR SEL) */
28346 #define TIM5_AF1_ETRSEL_0         (0x1U << TIM5_AF1_ETRSEL_Pos)              /*!< 0x00004000 */
28347 #define TIM5_AF1_ETRSEL_1         (0x2U << TIM5_AF1_ETRSEL_Pos)              /*!< 0x00008000 */
28348 #define TIM5_AF1_ETRSEL_2         (0x4U << TIM5_AF1_ETRSEL_Pos)              /*!< 0x00010000 */
28349 #define TIM5_AF1_ETRSEL_3         (0x8U << TIM5_AF1_ETRSEL_Pos)              /*!< 0x00020000 */
28350 
28351 /*******************  Bit definition for TIM5_TISEL register  *********************/
28352 #define TIM5_TISEL_TI1SEL_Pos      (0U)
28353 #define TIM5_TISEL_TI1SEL_Msk      (0xFU << TIM5_TISEL_TI1SEL_Pos)             /*!< 0x0000000F */
28354 #define TIM5_TISEL_TI1SEL          TIM5_TISEL_TI1SEL_Msk                       /*!<TI1SEL[3:0] bits (TIM3 TI1 SEL)*/
28355 #define TIM5_TISEL_TI1SEL_0        (0x1U << TIM5_TISEL_TI1SEL_Pos)             /*!< 0x00000001 */
28356 #define TIM5_TISEL_TI1SEL_1        (0x2U << TIM5_TISEL_TI1SEL_Pos)             /*!< 0x00000002 */
28357 #define TIM5_TISEL_TI1SEL_2        (0x4U << TIM5_TISEL_TI1SEL_Pos)             /*!< 0x00000004 */
28358 #define TIM5_TISEL_TI1SEL_3        (0x8U << TIM5_TISEL_TI1SEL_Pos)             /*!< 0x00000008 */
28359 
28360 #define TIM5_TISEL_TI2SEL_Pos      (8U)
28361 #define TIM5_TISEL_TI2SEL_Msk      (0xFU << TIM5_TISEL_TI2SEL_Pos)             /*!< 0x00000F00 */
28362 #define TIM5_TISEL_TI2SEL          TIM5_TISEL_TI2SEL_Msk                       /*!<TI2SEL[3:0] bits (TIM3 TI2 SEL)*/
28363 #define TIM5_TISEL_TI2SEL_0        (0x1U << TIM5_TISEL_TI2SEL_Pos)             /*!< 0x00000100 */
28364 #define TIM5_TISEL_TI2SEL_1        (0x2U << TIM5_TISEL_TI2SEL_Pos)             /*!< 0x00000200 */
28365 #define TIM5_TISEL_TI2SEL_2        (0x4U << TIM5_TISEL_TI2SEL_Pos)             /*!< 0x00000400 */
28366 #define TIM5_TISEL_TI2SEL_3        (0x8U << TIM5_TISEL_TI2SEL_Pos)             /*!< 0x00000800 */
28367 
28368 #define TIM5_TISEL_TI3SEL_Pos      (16U)
28369 #define TIM5_TISEL_TI3SEL_Msk      (0xFU << TIM5_TISEL_TI3SEL_Pos)             /*!< 0x000F0000 */
28370 #define TIM5_TISEL_TI3SEL          TIM5_TISEL_TI3SEL_Msk                       /*!<TI3SEL[3:0] bits (TIM3 TI3 SEL)*/
28371 #define TIM5_TISEL_TI3SEL_0        (0x1U << TIM5_TISEL_TI3SEL_Pos)             /*!< 0x00010000 */
28372 #define TIM5_TISEL_TI3SEL_1        (0x2U << TIM5_TISEL_TI3SEL_Pos)             /*!< 0x00020000 */
28373 #define TIM5_TISEL_TI3SEL_2        (0x4U << TIM5_TISEL_TI3SEL_Pos)             /*!< 0x00040000 */
28374 #define TIM5_TISEL_TI3SEL_3        (0x8U << TIM5_TISEL_TI3SEL_Pos)             /*!< 0x00080000 */
28375 
28376 #define TIM5_TISEL_TI4SEL_Pos      (24U)
28377 #define TIM5_TISEL_TI4SEL_Msk      (0xFU << TIM5_TISEL_TI4SEL_Pos)             /*!< 0x0F000000 */
28378 #define TIM5_TISEL_TI4SEL          TIM5_TISEL_TI4SEL_Msk                       /*!<TI4SEL[3:0] bits (TIM3 TI4 SEL)*/
28379 #define TIM5_TISEL_TI4SEL_0        (0x1U << TIM5_TISEL_TI4SEL_Pos)             /*!< 0x01000000 */
28380 #define TIM5_TISEL_TI4SEL_1        (0x2U << TIM5_TISEL_TI4SEL_Pos)             /*!< 0x02000000 */
28381 #define TIM5_TISEL_TI4SEL_2        (0x4U << TIM5_TISEL_TI4SEL_Pos)             /*!< 0x04000000 */
28382 #define TIM5_TISEL_TI4SEL_3        (0x8U << TIM5_TISEL_TI4SEL_Pos)             /*!< 0x08000000 */
28383 
28384 /*******************  Bit definition for TIM15_AF1 register  *********************/
28385 #define TIM15_AF1_BKINE_Pos         (0U)
28386 #define TIM15_AF1_BKINE_Msk         (0x1U << TIM15_AF1_BKINE_Pos)              /*!< 0x00000001 */
28387 #define TIM15_AF1_BKINE             TIM15_AF1_BKINE_Msk                        /*!<BKINE Break input enable bit */
28388 #define TIM15_AF1_BKCMP1E_Pos       (1U)
28389 #define TIM15_AF1_BKCMP1E_Msk       (0x1U << TIM15_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */
28390 #define TIM15_AF1_BKCMP1E           TIM15_AF1_BKCMP1E_Msk                      /*!<BKCMP1E Break Compare1 Enable bit */
28391 #define TIM15_AF1_BKCMP2E_Pos       (2U)
28392 #define TIM15_AF1_BKCMP2E_Msk       (0x1U << TIM15_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */
28393 #define TIM15_AF1_BKCMP2E           TIM15_AF1_BKCMP2E_Msk                      /*!<BKCMP1E Break Compare2 Enable bit  */
28394 #define TIM15_AF1_BKDF1BK2E_Pos     (8U)
28395 #define TIM15_AF1_BKDF1BK2E_Msk     (0x1U << TIM15_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */
28396 #define TIM15_AF1_BKDF1BK2E         TIM15_AF1_BKDF1BK2E_Msk                    /*!<BRK dfsdm1_break[0] enable */
28397 #define TIM15_AF1_BKINP_Pos         (9U)
28398 #define TIM15_AF1_BKINP_Msk         (0x1U << TIM15_AF1_BKINP_Pos)              /*!< 0x00000200 */
28399 #define TIM15_AF1_BKINP             TIM15_AF1_BKINP_Msk                        /*!<BRKINP Break input polarity */
28400 #define TIM15_AF1_BKCMP1P_Pos       (10U)
28401 #define TIM15_AF1_BKCMP1P_Msk       (0x1U << TIM15_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */
28402 #define TIM15_AF1_BKCMP1P           TIM15_AF1_BKCMP1P_Msk                      /*!<BKCMP1P Break COMP1 input polarity */
28403 #define TIM15_AF1_BKCMP2P_Pos       (11U)
28404 #define TIM15_AF1_BKCMP2P_Msk       (0x1U << TIM15_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */
28405 #define TIM15_AF1_BKCMP2P           TIM15_AF1_BKCMP2P_Msk                      /*!<BKCMP2P Break COMP2 input polarity */
28406 
28407 /*******************  Bit definition for TIM15_TISEL register  *********************/
28408 #define TIM15_TISEL_TI1SEL_Pos      (0U)
28409 #define TIM15_TISEL_TI1SEL_Msk      (0xFU << TIM15_TISEL_TI1SEL_Pos)           /*!< 0x0000000F */
28410 #define TIM15_TISEL_TI1SEL          TIM15_TISEL_TI1SEL_Msk                     /*!<TI1SEL[3:0] bits (TIM15 TI1 SEL)*/
28411 #define TIM15_TISEL_TI1SEL_0        (0x1U << TIM15_TISEL_TI1SEL_Pos)           /*!< 0x00000001 */
28412 #define TIM15_TISEL_TI1SEL_1        (0x2U << TIM15_TISEL_TI1SEL_Pos)           /*!< 0x00000002 */
28413 #define TIM15_TISEL_TI1SEL_2        (0x4U << TIM15_TISEL_TI1SEL_Pos)           /*!< 0x00000004 */
28414 #define TIM15_TISEL_TI1SEL_3        (0x8U << TIM15_TISEL_TI1SEL_Pos)           /*!< 0x00000008 */
28415 
28416 #define TIM15_TISEL_TI2SEL_Pos      (8U)
28417 #define TIM15_TISEL_TI2SEL_Msk      (0xFU << TIM15_TISEL_TI2SEL_Pos)           /*!< 0x00000F00 */
28418 #define TIM15_TISEL_TI2SEL          TIM15_TISEL_TI2SEL_Msk                     /*!<TI2SEL[3:0] bits (TIM15 TI2 SEL)*/
28419 #define TIM15_TISEL_TI2SEL_0        (0x1U << TIM15_TISEL_TI2SEL_Pos)           /*!< 0x00000100 */
28420 #define TIM15_TISEL_TI2SEL_1        (0x2U << TIM15_TISEL_TI2SEL_Pos)           /*!< 0x00000200 */
28421 #define TIM15_TISEL_TI2SEL_2        (0x4U << TIM15_TISEL_TI2SEL_Pos)           /*!< 0x00000400 */
28422 #define TIM15_TISEL_TI2SEL_3        (0x8U << TIM15_TISEL_TI2SEL_Pos)           /*!< 0x00000800 */
28423 
28424 /*******************  Bit definition for TIM12_TISEL register  *********************/
28425 #define TIM12_TISEL_TI1SEL_Pos      (0U)
28426 #define TIM12_TISEL_TI1SEL_Msk      (0xFU << TIM12_TISEL_TI1SEL_Pos)           /*!< 0x0000000F */
28427 #define TIM12_TISEL_TI1SEL          TIM12_TISEL_TI1SEL_Msk                     /*!<TI1SEL[3:0] bits (TIM12 TI1 SEL)*/
28428 #define TIM12_TISEL_TI1SEL_0        (0x1U << TIM12_TISEL_TI1SEL_Pos)           /*!< 0x00000001 */
28429 #define TIM12_TISEL_TI1SEL_1        (0x2U << TIM12_TISEL_TI1SEL_Pos)           /*!< 0x00000002 */
28430 #define TIM12_TISEL_TI1SEL_2        (0x4U << TIM12_TISEL_TI1SEL_Pos)           /*!< 0x00000004 */
28431 #define TIM12_TISEL_TI1SEL_3        (0x8U << TIM12_TISEL_TI1SEL_Pos)           /*!< 0x00000008 */
28432 
28433 #define TIM12_TISEL_TI2SEL_Pos      (8U)
28434 #define TIM12_TISEL_TI2SEL_Msk      (0xFU << TIM12_TISEL_TI2SEL_Pos)           /*!< 0x00000F00 */
28435 #define TIM12_TISEL_TI2SEL          TIM12_TISEL_TI2SEL_Msk                     /*!<TI2SEL[3:0] bits (TIM15 TI2 SEL)*/
28436 #define TIM12_TISEL_TI2SEL_0        (0x1U << TIM12_TISEL_TI2SEL_Pos)           /*!< 0x00000100 */
28437 #define TIM12_TISEL_TI2SEL_1        (0x2U << TIM12_TISEL_TI2SEL_Pos)           /*!< 0x00000200 */
28438 #define TIM12_TISEL_TI2SEL_2        (0x4U << TIM12_TISEL_TI2SEL_Pos)           /*!< 0x00000400 */
28439 #define TIM12_TISEL_TI2SEL_3        (0x8U << TIM12_TISEL_TI2SEL_Pos)           /*!< 0x00000800 */
28440 
28441 /*******************  Bit definition for TIM16_ register  *********************/
28442 #define TIM16_AF1_BKINE_Pos         (0U)
28443 #define TIM16_AF1_BKINE_Msk         (0x1U << TIM16_AF1_BKINE_Pos)              /*!< 0x00000001 */
28444 #define TIM16_AF1_BKINE             TIM16_AF1_BKINE_Msk                        /*!<BKINE Break input enable bit */
28445 #define TIM16_AF1_BKDF1BK2E_Pos     (8U)
28446 #define TIM16_AF1_BKDF1BK2E_Msk     (0x1U << TIM16_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */
28447 #define TIM16_AF1_BKDF1BK2E         TIM16_AF1_BKDF1BK2E_Msk                    /*!<BRK dfsdm1_break[1] enable */
28448 #define TIM16_AF1_BKINP_Pos         (9U)
28449 #define TIM16_AF1_BKINP_Msk         (0x1U << TIM16_AF1_BKINP_Pos)              /*!< 0x00000200 */
28450 #define TIM16_AF1_BKINP             TIM16_AF1_BKINP_Msk                        /*!<BRKINP Break input polarity */
28451 
28452 /*******************  Bit definition for TIM16_TISEL register  *********************/
28453 #define TIM16_TISEL_TI1SEL_Pos      (0U)
28454 #define TIM16_TISEL_TI1SEL_Msk      (0xFU << TIM16_TISEL_TI1SEL_Pos)           /*!< 0x0000000F */
28455 #define TIM16_TISEL_TI1SEL          TIM16_TISEL_TI1SEL_Msk                     /*!<TI1SEL[3:0] bits (TIM16 TI1 SEL) */
28456 #define TIM16_TISEL_TI1SEL_0        (0x1U << TIM16_TISEL_TI1SEL_Pos)           /*!< 0x00000001 */
28457 #define TIM16_TISEL_TI1SEL_1        (0x2U << TIM16_TISEL_TI1SEL_Pos)           /*!< 0x00000002 */
28458 #define TIM16_TISEL_TI1SEL_2        (0x4U << TIM16_TISEL_TI1SEL_Pos)           /*!< 0x00000004 */
28459 #define TIM16_TISEL_TI1SEL_3        (0x8U << TIM16_TISEL_TI1SEL_Pos)           /*!< 0x00000008 */
28460 
28461 /*******************  Bit definition for TIM17_AF1 register  *********************/
28462 #define TIM17_AF1_BKINE_Pos         (0U)
28463 #define TIM17_AF1_BKINE_Msk         (0x1U << TIM17_AF1_BKINE_Pos)              /*!< 0x00000001 */
28464 #define TIM17_AF1_BKINE             TIM17_AF1_BKINE_Msk                        /*!<BKINE Break input enable bit */
28465 #define TIM17_AF1_BKDF1BK2E_Pos     (8U)
28466 #define TIM17_AF1_BKDF1BK2E_Msk     (0x1U << TIM17_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */
28467 #define TIM17_AF1_BKDF1BK2E         TIM17_AF1_BKDF1BK2E_Msk                    /*!<BRK dfsdm1_break[2] enable */
28468 #define TIM17_AF1_BKINP_Pos         (9U)
28469 #define TIM17_AF1_BKINP_Msk         (0x1U << TIM17_AF1_BKINP_Pos)              /*!< 0x00000200 */
28470 #define TIM17_AF1_BKINP             TIM17_AF1_BKINP_Msk                        /*!<BRKINP Break input polarity */
28471 
28472 
28473 /*******************  Bit definition for TIM17_TISEL register  *********************/
28474 #define TIM17_TISEL_TI1SEL_Pos      (0U)
28475 #define TIM17_TISEL_TI1SEL_Msk      (0xFU << TIM17_TISEL_TI1SEL_Pos)           /*!< 0x0000000F */
28476 #define TIM17_TISEL_TI1SEL          TIM17_TISEL_TI1SEL_Msk                     /*!<TI1SEL[3:0] bits (TIM17 TI1 SEL) */
28477 #define TIM17_TISEL_TI1SEL_0        (0x1U << TIM17_TISEL_TI1SEL_Pos)           /*!< 0x00000001 */
28478 #define TIM17_TISEL_TI1SEL_1        (0x2U << TIM17_TISEL_TI1SEL_Pos)           /*!< 0x00000002 */
28479 #define TIM17_TISEL_TI1SEL_2        (0x4U << TIM17_TISEL_TI1SEL_Pos)           /*!< 0x00000004 */
28480 #define TIM17_TISEL_TI1SEL_3        (0x8U << TIM17_TISEL_TI1SEL_Pos)           /*!< 0x00000008 */
28481 
28482 /*******************  Bit definition for TIM_TISEL register  *********************/
28483 #define TIM_TISEL_TI1SEL_Pos      (0U)
28484 #define TIM_TISEL_TI1SEL_Msk      (0xFUL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x0000000F */
28485 #define TIM_TISEL_TI1SEL          TIM_TISEL_TI1SEL_Msk                         /*!<TI1SEL[3:0] bits (TIM1 TI1 SEL)*/
28486 #define TIM_TISEL_TI1SEL_0        (0x1UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000001 */
28487 #define TIM_TISEL_TI1SEL_1        (0x2UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000002 */
28488 #define TIM_TISEL_TI1SEL_2        (0x4UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000004 */
28489 #define TIM_TISEL_TI1SEL_3        (0x8UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000008 */
28490 
28491 #define TIM_TISEL_TI2SEL_Pos      (8U)
28492 #define TIM_TISEL_TI2SEL_Msk      (0xFUL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000F00 */
28493 #define TIM_TISEL_TI2SEL          TIM_TISEL_TI2SEL_Msk                         /*!<TI2SEL[3:0] bits (TIM1 TI2 SEL)*/
28494 #define TIM_TISEL_TI2SEL_0        (0x1UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000100 */
28495 #define TIM_TISEL_TI2SEL_1        (0x2UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000200 */
28496 #define TIM_TISEL_TI2SEL_2        (0x4UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000400 */
28497 #define TIM_TISEL_TI2SEL_3        (0x8UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000800 */
28498 
28499 #define TIM_TISEL_TI3SEL_Pos      (16U)
28500 #define TIM_TISEL_TI3SEL_Msk      (0xFUL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x000F0000 */
28501 #define TIM_TISEL_TI3SEL          TIM_TISEL_TI3SEL_Msk                         /*!<TI3SEL[3:0] bits (TIM1 TI3 SEL)*/
28502 #define TIM_TISEL_TI3SEL_0        (0x1UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00010000 */
28503 #define TIM_TISEL_TI3SEL_1        (0x2UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00020000 */
28504 #define TIM_TISEL_TI3SEL_2        (0x4UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00040000 */
28505 #define TIM_TISEL_TI3SEL_3        (0x8UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00080000 */
28506 
28507 #define TIM_TISEL_TI4SEL_Pos      (24U)
28508 #define TIM_TISEL_TI4SEL_Msk      (0xFUL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x0F000000 */
28509 #define TIM_TISEL_TI4SEL          TIM_TISEL_TI4SEL_Msk                         /*!<TI4SEL[3:0] bits (TIM1 TI4 SEL)*/
28510 #define TIM_TISEL_TI4SEL_0        (0x1UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x01000000 */
28511 #define TIM_TISEL_TI4SEL_1        (0x2UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x02000000 */
28512 #define TIM_TISEL_TI4SEL_2        (0x4UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x04000000 */
28513 #define TIM_TISEL_TI4SEL_3        (0x8UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x08000000 */
28514 
28515 /******************************************************************************/
28516 /*                                                                            */
28517 /*                         Low Power Timer (LPTTIM)                           */
28518 /*                                                                            */
28519 /******************************************************************************/
28520 /******************  Bit definition for LPTIM_ISR register  *******************/
28521 #define LPTIM_ISR_CMPM_Pos          (0U)
28522 #define LPTIM_ISR_CMPM_Msk          (0x1U << LPTIM_ISR_CMPM_Pos)               /*!< 0x00000001 */
28523 #define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
28524 #define LPTIM_ISR_ARRM_Pos          (1U)
28525 #define LPTIM_ISR_ARRM_Msk          (0x1U << LPTIM_ISR_ARRM_Pos)               /*!< 0x00000002 */
28526 #define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
28527 #define LPTIM_ISR_EXTTRIG_Pos       (2U)
28528 #define LPTIM_ISR_EXTTRIG_Msk       (0x1U << LPTIM_ISR_EXTTRIG_Pos)            /*!< 0x00000004 */
28529 #define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
28530 #define LPTIM_ISR_CMPOK_Pos         (3U)
28531 #define LPTIM_ISR_CMPOK_Msk         (0x1U << LPTIM_ISR_CMPOK_Pos)              /*!< 0x00000008 */
28532 #define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
28533 #define LPTIM_ISR_ARROK_Pos         (4U)
28534 #define LPTIM_ISR_ARROK_Msk         (0x1U << LPTIM_ISR_ARROK_Pos)              /*!< 0x00000010 */
28535 #define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
28536 #define LPTIM_ISR_UP_Pos            (5U)
28537 #define LPTIM_ISR_UP_Msk            (0x1U << LPTIM_ISR_UP_Pos)                 /*!< 0x00000020 */
28538 #define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
28539 #define LPTIM_ISR_DOWN_Pos          (6U)
28540 #define LPTIM_ISR_DOWN_Msk          (0x1U << LPTIM_ISR_DOWN_Pos)               /*!< 0x00000040 */
28541 #define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
28542 
28543 /******************  Bit definition for LPTIM_ICR register  *******************/
28544 #define LPTIM_ICR_CMPMCF_Pos        (0U)
28545 #define LPTIM_ICR_CMPMCF_Msk        (0x1U << LPTIM_ICR_CMPMCF_Pos)             /*!< 0x00000001 */
28546 #define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
28547 #define LPTIM_ICR_ARRMCF_Pos        (1U)
28548 #define LPTIM_ICR_ARRMCF_Msk        (0x1U << LPTIM_ICR_ARRMCF_Pos)             /*!< 0x00000002 */
28549 #define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
28550 #define LPTIM_ICR_EXTTRIGCF_Pos     (2U)
28551 #define LPTIM_ICR_EXTTRIGCF_Msk     (0x1U << LPTIM_ICR_EXTTRIGCF_Pos)          /*!< 0x00000004 */
28552 #define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
28553 #define LPTIM_ICR_CMPOKCF_Pos       (3U)
28554 #define LPTIM_ICR_CMPOKCF_Msk       (0x1U << LPTIM_ICR_CMPOKCF_Pos)            /*!< 0x00000008 */
28555 #define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
28556 #define LPTIM_ICR_ARROKCF_Pos       (4U)
28557 #define LPTIM_ICR_ARROKCF_Msk       (0x1U << LPTIM_ICR_ARROKCF_Pos)            /*!< 0x00000010 */
28558 #define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
28559 #define LPTIM_ICR_UPCF_Pos          (5U)
28560 #define LPTIM_ICR_UPCF_Msk          (0x1U << LPTIM_ICR_UPCF_Pos)               /*!< 0x00000020 */
28561 #define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
28562 #define LPTIM_ICR_DOWNCF_Pos        (6U)
28563 #define LPTIM_ICR_DOWNCF_Msk        (0x1U << LPTIM_ICR_DOWNCF_Pos)             /*!< 0x00000040 */
28564 #define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
28565 
28566 /******************  Bit definition for LPTIM_IER register ********************/
28567 #define LPTIM_IER_CMPMIE_Pos        (0U)
28568 #define LPTIM_IER_CMPMIE_Msk        (0x1U << LPTIM_IER_CMPMIE_Pos)             /*!< 0x00000001 */
28569 #define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
28570 #define LPTIM_IER_ARRMIE_Pos        (1U)
28571 #define LPTIM_IER_ARRMIE_Msk        (0x1U << LPTIM_IER_ARRMIE_Pos)             /*!< 0x00000002 */
28572 #define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
28573 #define LPTIM_IER_EXTTRIGIE_Pos     (2U)
28574 #define LPTIM_IER_EXTTRIGIE_Msk     (0x1U << LPTIM_IER_EXTTRIGIE_Pos)          /*!< 0x00000004 */
28575 #define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
28576 #define LPTIM_IER_CMPOKIE_Pos       (3U)
28577 #define LPTIM_IER_CMPOKIE_Msk       (0x1U << LPTIM_IER_CMPOKIE_Pos)            /*!< 0x00000008 */
28578 #define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
28579 #define LPTIM_IER_ARROKIE_Pos       (4U)
28580 #define LPTIM_IER_ARROKIE_Msk       (0x1U << LPTIM_IER_ARROKIE_Pos)            /*!< 0x00000010 */
28581 #define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
28582 #define LPTIM_IER_UPIE_Pos          (5U)
28583 #define LPTIM_IER_UPIE_Msk          (0x1U << LPTIM_IER_UPIE_Pos)               /*!< 0x00000020 */
28584 #define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
28585 #define LPTIM_IER_DOWNIE_Pos        (6U)
28586 #define LPTIM_IER_DOWNIE_Msk        (0x1U << LPTIM_IER_DOWNIE_Pos)             /*!< 0x00000040 */
28587 #define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
28588 
28589 /******************  Bit definition for LPTIM_CFGR register *******************/
28590 #define LPTIM_CFGR_CKSEL_Pos        (0U)
28591 #define LPTIM_CFGR_CKSEL_Msk        (0x1U << LPTIM_CFGR_CKSEL_Pos)             /*!< 0x00000001 */
28592 #define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
28593 
28594 #define LPTIM_CFGR_CKPOL_Pos        (1U)
28595 #define LPTIM_CFGR_CKPOL_Msk        (0x3U << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000006 */
28596 #define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
28597 #define LPTIM_CFGR_CKPOL_0          (0x1U << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */
28598 #define LPTIM_CFGR_CKPOL_1          (0x2U << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */
28599 
28600 #define LPTIM_CFGR_CKFLT_Pos        (3U)
28601 #define LPTIM_CFGR_CKFLT_Msk        (0x3U << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000018 */
28602 #define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
28603 #define LPTIM_CFGR_CKFLT_0          (0x1U << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */
28604 #define LPTIM_CFGR_CKFLT_1          (0x2U << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */
28605 
28606 #define LPTIM_CFGR_TRGFLT_Pos       (6U)
28607 #define LPTIM_CFGR_TRGFLT_Msk       (0x3U << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x000000C0 */
28608 #define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
28609 #define LPTIM_CFGR_TRGFLT_0         (0x1U << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */
28610 #define LPTIM_CFGR_TRGFLT_1         (0x2U << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */
28611 
28612 #define LPTIM_CFGR_PRESC_Pos        (9U)
28613 #define LPTIM_CFGR_PRESC_Msk        (0x7U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000E00 */
28614 #define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
28615 #define LPTIM_CFGR_PRESC_0          (0x1U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */
28616 #define LPTIM_CFGR_PRESC_1          (0x2U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */
28617 #define LPTIM_CFGR_PRESC_2          (0x4U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */
28618 
28619 #define LPTIM_CFGR_TRIGSEL_Pos      (13U)
28620 #define LPTIM_CFGR_TRIGSEL_Msk      (0x7U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x0000E000 */
28621 #define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
28622 #define LPTIM_CFGR_TRIGSEL_0        (0x1U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */
28623 #define LPTIM_CFGR_TRIGSEL_1        (0x2U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */
28624 #define LPTIM_CFGR_TRIGSEL_2        (0x4U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */
28625 
28626 #define LPTIM_CFGR_TRIGEN_Pos       (17U)
28627 #define LPTIM_CFGR_TRIGEN_Msk       (0x3U << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00060000 */
28628 #define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
28629 #define LPTIM_CFGR_TRIGEN_0         (0x1U << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */
28630 #define LPTIM_CFGR_TRIGEN_1         (0x2U << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */
28631 
28632 #define LPTIM_CFGR_TIMOUT_Pos       (19U)
28633 #define LPTIM_CFGR_TIMOUT_Msk       (0x1U << LPTIM_CFGR_TIMOUT_Pos)            /*!< 0x00080000 */
28634 #define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
28635 #define LPTIM_CFGR_WAVE_Pos         (20U)
28636 #define LPTIM_CFGR_WAVE_Msk         (0x1U << LPTIM_CFGR_WAVE_Pos)              /*!< 0x00100000 */
28637 #define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
28638 #define LPTIM_CFGR_WAVPOL_Pos       (21U)
28639 #define LPTIM_CFGR_WAVPOL_Msk       (0x1U << LPTIM_CFGR_WAVPOL_Pos)            /*!< 0x00200000 */
28640 #define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
28641 #define LPTIM_CFGR_PRELOAD_Pos      (22U)
28642 #define LPTIM_CFGR_PRELOAD_Msk      (0x1U << LPTIM_CFGR_PRELOAD_Pos)           /*!< 0x00400000 */
28643 #define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
28644 #define LPTIM_CFGR_COUNTMODE_Pos    (23U)
28645 #define LPTIM_CFGR_COUNTMODE_Msk    (0x1U << LPTIM_CFGR_COUNTMODE_Pos)         /*!< 0x00800000 */
28646 #define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
28647 #define LPTIM_CFGR_ENC_Pos          (24U)
28648 #define LPTIM_CFGR_ENC_Msk          (0x1U << LPTIM_CFGR_ENC_Pos)               /*!< 0x01000000 */
28649 #define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
28650 
28651 /******************  Bit definition for LPTIM_CR register  ********************/
28652 #define LPTIM_CR_ENABLE_Pos         (0U)
28653 #define LPTIM_CR_ENABLE_Msk         (0x1U << LPTIM_CR_ENABLE_Pos)              /*!< 0x00000001 */
28654 #define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
28655 #define LPTIM_CR_SNGSTRT_Pos        (1U)
28656 #define LPTIM_CR_SNGSTRT_Msk        (0x1U << LPTIM_CR_SNGSTRT_Pos)             /*!< 0x00000002 */
28657 #define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
28658 #define LPTIM_CR_CNTSTRT_Pos        (2U)
28659 #define LPTIM_CR_CNTSTRT_Msk        (0x1U << LPTIM_CR_CNTSTRT_Pos)             /*!< 0x00000004 */
28660 #define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
28661 #define LPTIM_CR_COUNTRST_Pos       (3U)
28662 #define LPTIM_CR_COUNTRST_Msk       (0x1U << LPTIM_CR_COUNTRST_Pos)            /*!< 0x00000008 */
28663 #define LPTIM_CR_COUNTRST           LPTIM_CR_COUNTRST_Msk                      /*!< Timer Counter reset in synchronous mode*/
28664 #define LPTIM_CR_RSTARE_Pos         (4U)
28665 #define LPTIM_CR_RSTARE_Msk         (0x1U << LPTIM_CR_RSTARE_Pos)              /*!< 0x00000010 */
28666 #define LPTIM_CR_RSTARE             LPTIM_CR_RSTARE_Msk                        /*!< Timer Counter reset after read enable (asynchronously)*/
28667 
28668 
28669 /******************  Bit definition for LPTIM_CMP register  *******************/
28670 #define LPTIM_CMP_CMP_Pos           (0U)
28671 #define LPTIM_CMP_CMP_Msk           (0xFFFFU << LPTIM_CMP_CMP_Pos)             /*!< 0x0000FFFF */
28672 #define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
28673 
28674 /******************  Bit definition for LPTIM_ARR register  *******************/
28675 #define LPTIM_ARR_ARR_Pos           (0U)
28676 #define LPTIM_ARR_ARR_Msk           (0xFFFFU << LPTIM_ARR_ARR_Pos)             /*!< 0x0000FFFF */
28677 #define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
28678 
28679 /******************  Bit definition for LPTIM_CNT register  *******************/
28680 #define LPTIM_CNT_CNT_Pos           (0U)
28681 #define LPTIM_CNT_CNT_Msk           (0xFFFFU << LPTIM_CNT_CNT_Pos)             /*!< 0x0000FFFF */
28682 #define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
28683 
28684 /******************  Bit definition for LPTIM_CFGR2 register  *******************/
28685 #define LPTIM_CFGR2_IN1SEL_Pos      (0U)
28686 #define LPTIM_CFGR2_IN1SEL_Msk      (0xFUL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x0000000F */
28687 #define LPTIM_CFGR2_IN1SEL          LPTIM_CFGR2_IN1SEL_Msk                     /*!< CFGR2[3:0] bits (INPUT1 selection) */
28688 #define LPTIM_CFGR2_IN1SEL_0_Pos    (LPTIM_CFGR2_IN1SEL_Pos)
28689 #define LPTIM_CFGR2_IN1SEL_0_Msk    (0x1U << LPTIM_CFGR2_IN1SEL_0_Pos)         /*!< 0x00000001 */
28690 #define LPTIM_CFGR2_IN1SEL_0        LPTIM_CFGR2_IN1SEL_0_Msk                   /*!< Bit 0 */
28691 #define LPTIM_CFGR2_IN1SEL_1_Pos    (1U)
28692 #define LPTIM_CFGR2_IN1SEL_1_Msk    (0x1U << LPTIM_CFGR2_IN1SEL_1_Pos)         /*!< 0x00000002 */
28693 #define LPTIM_CFGR2_IN1SEL_1        LPTIM_CFGR2_IN1SEL_1_Msk                   /*!< Bit 1 */
28694 #define LPTIM_CFGR2_IN1SEL_2_Pos    (2U)
28695 #define LPTIM_CFGR2_IN1SEL_2_Msk    (0x1U << LPTIM_CFGR2_IN1SEL_2_Pos)         /*!< 0x00000004 */
28696 #define LPTIM_CFGR2_IN1SEL_2        LPTIM_CFGR2_IN1SEL_2_Msk                   /*!< Bit 2 */
28697 #define LPTIM_CFGR2_IN1SEL_3_Pos    (3U)
28698 #define LPTIM_CFGR2_IN1SEL_3_Msk    (0x1U << LPTIM_CFGR2_IN1SEL_3_Pos)         /*!< 0x00000008 */
28699 #define LPTIM_CFGR2_IN1SEL_3        LPTIM_CFGR2_IN1SEL_3_Msk                   /*!< Bit 3 */
28700 
28701 #define LPTIM_CFGR2_IN2SEL_Pos      (4U)
28702 #define LPTIM_CFGR2_IN2SEL_Msk      (0xFUL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x000000F0 */
28703 #define LPTIM_CFGR2_IN2SEL          LPTIM_CFGR2_IN2SEL_Msk                     /*!< CFGR2[7:4] bits (INPUT2 selection) */
28704 #define LPTIM_CFGR2_IN2SEL_0_Pos    (LPTIM_CFGR2_IN2SEL_Pos)
28705 #define LPTIM_CFGR2_IN2SEL_0_Msk    (0x1U << LPTIM_CFGR2_IN2SEL_0_Pos)         /*!< 0x00000010 */
28706 #define LPTIM_CFGR2_IN2SEL_0        LPTIM_CFGR2_IN2SEL_0_Msk                   /*!< Bit 4 */
28707 #define LPTIM_CFGR2_IN2SEL_1_Pos    (5U)
28708 #define LPTIM_CFGR2_IN2SEL_1_Msk    (0x1U << LPTIM_CFGR2_IN2SEL_1_Pos)         /*!< 0x00000020 */
28709 #define LPTIM_CFGR2_IN2SEL_1        LPTIM_CFGR2_IN2SEL_1_Msk                   /*!< Bit 5 */
28710 #define LPTIM_CFGR2_IN2SEL_2_Pos    (6U)
28711 #define LPTIM_CFGR2_IN2SEL_2_Msk    (0x1U << LPTIM_CFGR2_IN2SEL_2_Pos)         /*!< 0x00000040 */
28712 #define LPTIM_CFGR2_IN2SEL_2        LPTIM_CFGR2_IN2SEL_2_Msk                   /*!< Bit 6 */
28713 #define LPTIM_CFGR2_IN2SEL_3_Pos    (7U)
28714 #define LPTIM_CFGR2_IN2SEL_3_Msk    (0x1U << LPTIM_CFGR2_IN2SEL_3_Pos)         /*!< 0x00000080 */
28715 #define LPTIM_CFGR2_IN2SEL_3        LPTIM_CFGR2_IN2SEL_3_Msk                   /*!< Bit 7 */
28716 
28717 /**********************  Bit definition for LPTIM_HWCFGR register  ***************/
28718 #define LPTIM_HWCFGR_CFG1_Pos  (0U)
28719 #define LPTIM_HWCFGR_CFG1_Msk  (0xFFU << LPTIM_HWCFGR_CFG1_Pos)          /*!< 0x000000FF */
28720 #define LPTIM_HWCFGR_CFG1      LPTIM_HWCFGR_CFG1_Msk                     /*!< HW CFG1 */
28721 #define LPTIM_HWCFGR_CFG2_Pos  (8U)
28722 #define LPTIM_HWCFGR_CFG2_Msk  (0xFFU << LPTIM_HWCFGR_CFG2_Pos)          /*!< 0x0000FF00 */
28723 #define LPTIM_HWCFGR_CFG2      LPTIM_HWCFGR_CFG2_Msk                     /*!< HW CFG2 */
28724 #define LPTIM_HWCFGR_CFG3_Pos  (16U)
28725 #define LPTIM_HWCFGR_CFG3_Msk  (0xFU << LPTIM_HWCFGR_CFG3_Pos)           /*!< 0x000F0000 */
28726 #define LPTIM_HWCFGR_CFG3      LPTIM_HWCFGR_CFG3_Msk                     /*!< HW CFG3 */
28727 #define LPTIM_HWCFGR_CFG4_Pos  (24U)
28728 #define LPTIM_HWCFGR_CFG4_Msk  (0xFFU << LPTIM_HWCFGR_CFG4_Pos)          /*!< 0xFF000000 */
28729 #define LPTIM_HWCFGR_CFG4      LPTIM_HWCFGR_CFG4_Msk                     /*!< HW CFG4 */
28730 
28731 /**********************  Bit definition for LPTIM_VERR register  *****************/
28732 #define LPTIM_VERR_MINREV_Pos      (0U)
28733 #define LPTIM_VERR_MINREV_Msk      (0xFU << LPTIM_VERR_MINREV_Pos)               /*!< 0x0000000F */
28734 #define LPTIM_VERR_MINREV          LPTIM_VERR_MINREV_Msk                         /*!< Minor Revision number */
28735 #define LPTIM_VERR_MAJREV_Pos      (4U)
28736 #define LPTIM_VERR_MAJREV_Msk      (0xFU << LPTIM_VERR_MAJREV_Pos)               /*!< 0x000000F0 */
28737 #define LPTIM_VERR_MAJREV          LPTIM_VERR_MAJREV_Msk                         /*!< Major Revision number */
28738 
28739 /**********************  Bit definition for LPTIM_PIDR register  ****************/
28740 #define LPTIM_PIDR_IPID_Pos       (0U)
28741 #define LPTIM_PIDR_IPID_Msk       (0xFFFFFFFFU << LPTIM_PIDR_IPID_Pos)         /*!< 0xFFFFFFFF */
28742 #define LPTIM_PIDR_IPID           LPTIM_PIDR_IPID_Msk                          /*!< IP Identification */
28743 
28744 /**********************  Bit definition for LPTIM_SIDR register  *****************/
28745 #define LPTIM_SIDR_SID_Pos         (0U)
28746 #define LPTIM_SIDR_SID_Msk         (0xFFFFFFFFU << LPTIM_SIDR_SID_Pos)           /*!< 0xFFFFFFFF */
28747 #define LPTIM_SIDR_SID             LPTIM_SIDR_SID_Msk                            /*!< IP size identification */
28748 
28749 /******************************************************************************/
28750 /*                                                                            */
28751 /*                      Analog Comparators (COMP)                             */
28752 /*                                                                            */
28753 /******************************************************************************/
28754 
28755 /*******************  Bit definition for COMP_SR register  ********************/
28756 #define COMP_SR_C1VAL_Pos            (0U)
28757 #define COMP_SR_C1VAL_Msk            (0x1U << COMP_SR_C1VAL_Pos)               /*!< 0x00000001 */
28758 #define COMP_SR_C1VAL                COMP_SR_C1VAL_Msk
28759 #define COMP_SR_C2VAL_Pos            (1U)
28760 #define COMP_SR_C2VAL_Msk            (0x1U << COMP_SR_C2VAL_Pos)               /*!< 0x00000002 */
28761 #define COMP_SR_C2VAL                COMP_SR_C2VAL_Msk
28762 #define COMP_SR_C1IF_Pos             (16U)
28763 #define COMP_SR_C1IF_Msk             (0x1U << COMP_SR_C1IF_Pos)                /*!< 0x00010000 */
28764 #define COMP_SR_C1IF                 COMP_SR_C1IF_Msk
28765 #define COMP_SR_C2IF_Pos             (17U)
28766 #define COMP_SR_C2IF_Msk             (0x1U << COMP_SR_C2IF_Pos)                /*!< 0x00020000 */
28767 #define COMP_SR_C2IF                 COMP_SR_C2IF_Msk
28768 /*******************  Bit definition for COMP_ICFR register  ********************/
28769 #define COMP_ICFR_C1IF_Pos           (16U)
28770 #define COMP_ICFR_C1IF_Msk           (0x1U << COMP_ICFR_C1IF_Pos)              /*!< 0x00010000 */
28771 #define COMP_ICFR_C1IF               COMP_ICFR_C1IF_Msk
28772 #define COMP_ICFR_C2IF_Pos           (17U)
28773 #define COMP_ICFR_C2IF_Msk           (0x1U << COMP_ICFR_C2IF_Pos)              /*!< 0x00020000 */
28774 #define COMP_ICFR_C2IF               COMP_ICFR_C2IF_Msk
28775 /*******************  Bit definition for COMP_OR register  ********************/
28776 #define COMP_OR_AFOPA6_Pos           (0U)
28777 #define COMP_OR_AFOPA6_Msk           (0x1U << COMP_OR_AFOPA6_Pos)              /*!< 0x00000001 */
28778 #define COMP_OR_AFOPA6               COMP_OR_AFOPA6_Msk
28779 #define COMP_OR_AFOPA8_Pos           (1U)
28780 #define COMP_OR_AFOPA8_Msk           (0x1U << COMP_OR_AFOPA8_Pos)              /*!< 0x00000002 */
28781 #define COMP_OR_AFOPA8               COMP_OR_AFOPA8_Msk
28782 #define COMP_OR_AFOPB12_Pos          (2U)
28783 #define COMP_OR_AFOPB12_Msk          (0x1U << COMP_OR_AFOPB12_Pos)             /*!< 0x00000004 */
28784 #define COMP_OR_AFOPB12              COMP_OR_AFOPB12_Msk
28785 #define COMP_OR_AFOPE6_Pos           (3U)
28786 #define COMP_OR_AFOPE6_Msk           (0x1U << COMP_OR_AFOPE6_Pos)              /*!< 0x00000008 */
28787 #define COMP_OR_AFOPE6               COMP_OR_AFOPE6_Msk
28788 #define COMP_OR_AFOPE15_Pos          (4U)
28789 #define COMP_OR_AFOPE15_Msk          (0x1U << COMP_OR_AFOPE15_Pos)             /*!< 0x00000010 */
28790 #define COMP_OR_AFOPE15              COMP_OR_AFOPE15_Msk
28791 #define COMP_OR_AFOPG2_Pos           (5U)
28792 #define COMP_OR_AFOPG2_Msk           (0x1U << COMP_OR_AFOPG2_Pos)              /*!< 0x00000020 */
28793 #define COMP_OR_AFOPG2               COMP_OR_AFOPG2_Msk
28794 #define COMP_OR_AFOPG3_Pos           (6U)
28795 #define COMP_OR_AFOPG3_Msk           (0x1U << COMP_OR_AFOPG3_Pos)              /*!< 0x00000040 */
28796 #define COMP_OR_AFOPG3               COMP_OR_AFOPG3_Msk
28797 #define COMP_OR_AFOPG4_Pos           (7U)
28798 #define COMP_OR_AFOPG4_Msk           (0x1U << COMP_OR_AFOPG4_Pos)              /*!< 0x00000080 */
28799 #define COMP_OR_AFOPG4               COMP_OR_AFOPG4_Msk
28800 #define COMP_OR_AFOPI1_Pos           (8U)
28801 #define COMP_OR_AFOPI1_Msk           (0x1U << COMP_OR_AFOPI1_Pos)              /*!< 0x00000100 */
28802 #define COMP_OR_AFOPI1               COMP_OR_AFOPI1_Msk
28803 #define COMP_OR_AFOPI4_Pos           (9U)
28804 #define COMP_OR_AFOPI4_Msk           (0x1U << COMP_OR_AFOPI4_Pos)              /*!< 0x00000200 */
28805 #define COMP_OR_AFOPI4               COMP_OR_AFOPI4_Msk
28806 #define COMP_OR_AFOPK2_Pos           (10U)
28807 #define COMP_OR_AFOPK2_Msk           (0x1U << COMP_OR_AFOPK2_Pos)              /*!< 0x00000400 */
28808 #define COMP_OR_AFOPK2               COMP_OR_AFOPK2_Msk
28809 
28810 /*!< ******************  Bit definition for COMP_CFGRx register  ********************/
28811 #define COMP_CFGRx_EN_Pos            (0U)
28812 #define COMP_CFGRx_EN_Msk            (0x1U << COMP_CFGRx_EN_Pos)               /*!< 0x00000001 */
28813 #define COMP_CFGRx_EN                COMP_CFGRx_EN_Msk                         /*!< COMPx enable bit                     */
28814 #define COMP_CFGRx_BRGEN_Pos         (1U)
28815 #define COMP_CFGRx_BRGEN_Msk         (0x1U << COMP_CFGRx_BRGEN_Pos)            /*!< 0x00000002 */
28816 #define COMP_CFGRx_BRGEN             COMP_CFGRx_BRGEN_Msk                      /*!< COMPx Scaler bridge enable           */
28817 #define COMP_CFGRx_SCALEN_Pos        (2U)
28818 #define COMP_CFGRx_SCALEN_Msk        (0x1U << COMP_CFGRx_SCALEN_Pos)           /*!< 0x00000004 */
28819 #define COMP_CFGRx_SCALEN            COMP_CFGRx_SCALEN_Msk                     /*!< COMPx Voltage scaler enable bit      */
28820 #define COMP_CFGRx_POLARITY_Pos      (3U)
28821 #define COMP_CFGRx_POLARITY_Msk      (0x1U << COMP_CFGRx_POLARITY_Pos)         /*!< 0x00000008 */
28822 #define COMP_CFGRx_POLARITY          COMP_CFGRx_POLARITY_Msk                   /*!< COMPx  polarity selection bit        */
28823 #define COMP_CFGRx_WINMODE_Pos       (4U)
28824 #define COMP_CFGRx_WINMODE_Msk       (0x1U << COMP_CFGRx_WINMODE_Pos)          /*!< 0x00000010 */
28825 #define COMP_CFGRx_WINMODE           COMP_CFGRx_WINMODE_Msk                    /*!< COMPx Windows mode selection bit     */
28826 #define COMP_CFGRx_ITEN_Pos          (6U)
28827 #define COMP_CFGRx_ITEN_Msk          (0x1U << COMP_CFGRx_ITEN_Pos)             /*!< 0x00000040 */
28828 #define COMP_CFGRx_ITEN              COMP_CFGRx_ITEN_Msk                       /*!< COMPx  interrupt enable              */
28829 #define COMP_CFGRx_HYST_Pos          (8U)
28830 #define COMP_CFGRx_HYST_Msk          (0x3U << COMP_CFGRx_HYST_Pos)             /*!< 0x00000300 */
28831 #define COMP_CFGRx_HYST              COMP_CFGRx_HYST_Msk                       /*!< COMPx  hysteresis selection bits     */
28832 #define COMP_CFGRx_HYST_0            (0x1U << COMP_CFGRx_HYST_Pos)             /*!< 0x00000100 */
28833 #define COMP_CFGRx_HYST_1            (0x2U << COMP_CFGRx_HYST_Pos)             /*!< 0x00000200 */
28834 #define COMP_CFGRx_PWRMODE_Pos       (12U)
28835 #define COMP_CFGRx_PWRMODE_Msk       (0x3U << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00003000 */
28836 #define COMP_CFGRx_PWRMODE           COMP_CFGRx_PWRMODE_Msk                    /*!< COMPx Power Mode of the comparator   */
28837 #define COMP_CFGRx_PWRMODE_0         (0x1U << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00001000 */
28838 #define COMP_CFGRx_PWRMODE_1         (0x2U << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00002000 */
28839 #define COMP_CFGRx_INMSEL_Pos        (16U)
28840 #define COMP_CFGRx_INMSEL_Msk        (0x7U << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00070000 */
28841 #define COMP_CFGRx_INMSEL            COMP_CFGRx_INMSEL_Msk                     /*!< COMPx  input minus selection bit  */
28842 #define COMP_CFGRx_INMSEL_0          (0x1U << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00010000 */
28843 #define COMP_CFGRx_INMSEL_1          (0x2U << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00020000 */
28844 #define COMP_CFGRx_INMSEL_2          (0x4U << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00040000 */
28845 #define COMP_CFGRx_INPSEL_Pos        (20U)
28846 #define COMP_CFGRx_INPSEL_Msk        (0x1U << COMP_CFGRx_INPSEL_Pos)           /*!< 0x00100000 */
28847 #define COMP_CFGRx_INPSEL            COMP_CFGRx_INPSEL_Msk                     /*!< COMPx  input plus selection bit       */
28848 #define COMP_CFGRx_BLANKING_Pos      (24U)
28849 #define COMP_CFGRx_BLANKING_Msk      (0xFU << COMP_CFGRx_BLANKING_Pos)         /*!< 0x0F000000 */
28850 #define COMP_CFGRx_BLANKING          COMP_CFGRx_BLANKING_Msk                   /*!< COMPx  blanking source selection bits */
28851 #define COMP_CFGRx_BLANKING_0        (0x1U << COMP_CFGRx_BLANKING_Pos)         /*!< 0x01000000 */
28852 #define COMP_CFGRx_BLANKING_1        (0x2U << COMP_CFGRx_BLANKING_Pos)         /*!< 0x02000000 */
28853 #define COMP_CFGRx_BLANKING_2        (0x4U << COMP_CFGRx_BLANKING_Pos)         /*!< 0x04000000 */
28854 #define COMP_CFGRx_LOCK_Pos          (31U)
28855 #define COMP_CFGRx_LOCK_Msk          (0x1U << COMP_CFGRx_LOCK_Pos)             /*!< 0x80000000 */
28856 #define COMP_CFGRx_LOCK              COMP_CFGRx_LOCK_Msk                       /*!< COMPx Lock Bit                        */
28857 
28858 
28859 /******************************************************************************/
28860 /*                                                                            */
28861 /*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
28862 /*                                                                            */
28863 /******************************************************************************/
28864 /******************  Bit definition for USART_CR1 register  *******************/
28865 #define USART_CR1_UE_Pos             (0U)
28866 #define USART_CR1_UE_Msk             (0x1U << USART_CR1_UE_Pos)                /*!< 0x00000001 */
28867 #define USART_CR1_UE                 USART_CR1_UE_Msk                          /*!< USART Enable */
28868 #define USART_CR1_UESM_Pos           (1U)
28869 #define USART_CR1_UESM_Msk           (0x1U << USART_CR1_UESM_Pos)              /*!< 0x00000002 */
28870 #define USART_CR1_UESM               USART_CR1_UESM_Msk                        /*!< USART Enable in STOP Mode */
28871 #define USART_CR1_RE_Pos             (2U)
28872 #define USART_CR1_RE_Msk             (0x1U << USART_CR1_RE_Pos)                /*!< 0x00000004 */
28873 #define USART_CR1_RE                 USART_CR1_RE_Msk                          /*!< Receiver Enable */
28874 #define USART_CR1_TE_Pos             (3U)
28875 #define USART_CR1_TE_Msk             (0x1U << USART_CR1_TE_Pos)                /*!< 0x00000008 */
28876 #define USART_CR1_TE                 USART_CR1_TE_Msk                          /*!< Transmitter Enable */
28877 #define USART_CR1_IDLEIE_Pos         (4U)
28878 #define USART_CR1_IDLEIE_Msk         (0x1U << USART_CR1_IDLEIE_Pos)            /*!< 0x00000010 */
28879 #define USART_CR1_IDLEIE             USART_CR1_IDLEIE_Msk                      /*!< IDLE Interrupt Enable */
28880 #define USART_CR1_RXNEIE_Pos         (5U)
28881 #define USART_CR1_RXNEIE_Msk         (0x1U << USART_CR1_RXNEIE_Pos)            /*!< 0x00000020 */
28882 #define USART_CR1_RXNEIE             USART_CR1_RXNEIE_Msk                      /*!< RXNE Interrupt Enable */
28883 #define USART_CR1_RXNEIE_RXFNEIE_Pos USART_CR1_RXNEIE_Pos
28884 #define USART_CR1_RXNEIE_RXFNEIE_Msk USART_CR1_RXNEIE_Msk                      /*!< 0x00000020 */
28885 #define USART_CR1_RXNEIE_RXFNEIE     USART_CR1_RXNEIE_Msk                      /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
28886 #define USART_CR1_TCIE_Pos           (6U)
28887 #define USART_CR1_TCIE_Msk           (0x1U << USART_CR1_TCIE_Pos)              /*!< 0x00000040 */
28888 #define USART_CR1_TCIE               USART_CR1_TCIE_Msk                        /*!< Transmission Complete Interrupt Enable */
28889 #define USART_CR1_TXEIE_Pos          (7U)
28890 #define USART_CR1_TXEIE_Msk          (0x1U << USART_CR1_TXEIE_Pos)             /*!< 0x00000080 */
28891 #define USART_CR1_TXEIE              USART_CR1_TXEIE_Msk                       /*!< TXE Interrupt Enable */
28892 #define USART_CR1_TXEIE_TXFNFIE_Pos  USART_CR1_TXEIE_Pos
28893 #define USART_CR1_TXEIE_TXFNFIE_Msk  USART_CR1_TXEIE_Msk                       /*!< 0x00000080 */
28894 #define USART_CR1_TXEIE_TXFNFIE      USART_CR1_TXEIE_Msk                       /*!< TXE and TX FIFO Not Full Interrupt Enable */
28895 #define USART_CR1_PEIE_Pos           (8U)
28896 #define USART_CR1_PEIE_Msk           (0x1U << USART_CR1_PEIE_Pos)              /*!< 0x00000100 */
28897 #define USART_CR1_PEIE               USART_CR1_PEIE_Msk                        /*!< PE Interrupt Enable */
28898 #define USART_CR1_PS_Pos             (9U)
28899 #define USART_CR1_PS_Msk             (0x1U << USART_CR1_PS_Pos)                /*!< 0x00000200 */
28900 #define USART_CR1_PS                 USART_CR1_PS_Msk                          /*!< Parity Selection */
28901 #define USART_CR1_PCE_Pos            (10U)
28902 #define USART_CR1_PCE_Msk            (0x1U << USART_CR1_PCE_Pos)               /*!< 0x00000400 */
28903 #define USART_CR1_PCE                USART_CR1_PCE_Msk                         /*!< Parity Control Enable */
28904 #define USART_CR1_WAKE_Pos           (11U)
28905 #define USART_CR1_WAKE_Msk           (0x1U << USART_CR1_WAKE_Pos)              /*!< 0x00000800 */
28906 #define USART_CR1_WAKE               USART_CR1_WAKE_Msk                        /*!< Receiver Wakeup method */
28907 #define USART_CR1_M_Pos              (12U)
28908 #define USART_CR1_M_Msk              (0x10001U << USART_CR1_M_Pos)             /*!< 0x10001000 */
28909 #define USART_CR1_M                  USART_CR1_M_Msk                           /*!< Word length */
28910 #define USART_CR1_M0_Pos             (12U)
28911 #define USART_CR1_M0_Msk             (0x1U << USART_CR1_M0_Pos)                /*!< 0x00001000 */
28912 #define USART_CR1_M0                 USART_CR1_M0_Msk                          /*!< Word length - Bit 0 */
28913 #define USART_CR1_MME_Pos            (13U)
28914 #define USART_CR1_MME_Msk            (0x1U << USART_CR1_MME_Pos)               /*!< 0x00002000 */
28915 #define USART_CR1_MME                USART_CR1_MME_Msk                         /*!< Mute Mode Enable */
28916 #define USART_CR1_CMIE_Pos           (14U)
28917 #define USART_CR1_CMIE_Msk           (0x1U << USART_CR1_CMIE_Pos)              /*!< 0x00004000 */
28918 #define USART_CR1_CMIE               USART_CR1_CMIE_Msk                        /*!< Character match interrupt enable */
28919 #define USART_CR1_OVER8_Pos          (15U)
28920 #define USART_CR1_OVER8_Msk          (0x1U << USART_CR1_OVER8_Pos)             /*!< 0x00008000 */
28921 #define USART_CR1_OVER8              USART_CR1_OVER8_Msk                       /*!< Oversampling by 8-bit or 16-bit mode */
28922 #define USART_CR1_DEDT_Pos           (16U)
28923 #define USART_CR1_DEDT_Msk           (0x1FU << USART_CR1_DEDT_Pos)             /*!< 0x001F0000 */
28924 #define USART_CR1_DEDT               USART_CR1_DEDT_Msk                        /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
28925 #define USART_CR1_DEDT_0             (0x01U << USART_CR1_DEDT_Pos)             /*!< 0x00010000 */
28926 #define USART_CR1_DEDT_1             (0x02U << USART_CR1_DEDT_Pos)             /*!< 0x00020000 */
28927 #define USART_CR1_DEDT_2             (0x04U << USART_CR1_DEDT_Pos)             /*!< 0x00040000 */
28928 #define USART_CR1_DEDT_3             (0x08U << USART_CR1_DEDT_Pos)             /*!< 0x00080000 */
28929 #define USART_CR1_DEDT_4             (0x10U << USART_CR1_DEDT_Pos)             /*!< 0x00100000 */
28930 #define USART_CR1_DEAT_Pos           (21U)
28931 #define USART_CR1_DEAT_Msk           (0x1FU << USART_CR1_DEAT_Pos)             /*!< 0x03E00000 */
28932 #define USART_CR1_DEAT               USART_CR1_DEAT_Msk                        /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
28933 #define USART_CR1_DEAT_0             (0x01U << USART_CR1_DEAT_Pos)             /*!< 0x00200000 */
28934 #define USART_CR1_DEAT_1             (0x02U << USART_CR1_DEAT_Pos)             /*!< 0x00400000 */
28935 #define USART_CR1_DEAT_2             (0x04U << USART_CR1_DEAT_Pos)             /*!< 0x00800000 */
28936 #define USART_CR1_DEAT_3             (0x08U << USART_CR1_DEAT_Pos)             /*!< 0x01000000 */
28937 #define USART_CR1_DEAT_4             (0x10U << USART_CR1_DEAT_Pos)             /*!< 0x02000000 */
28938 #define USART_CR1_RTOIE_Pos          (26U)
28939 #define USART_CR1_RTOIE_Msk          (0x1U << USART_CR1_RTOIE_Pos)             /*!< 0x04000000 */
28940 #define USART_CR1_RTOIE              USART_CR1_RTOIE_Msk                       /*!< Receive Time Out interrupt enable */
28941 #define USART_CR1_EOBIE_Pos          (27U)
28942 #define USART_CR1_EOBIE_Msk          (0x1U << USART_CR1_EOBIE_Pos)             /*!< 0x08000000 */
28943 #define USART_CR1_EOBIE              USART_CR1_EOBIE_Msk                       /*!< End of Block interrupt enable */
28944 #define USART_CR1_M1_Pos             (28U)
28945 #define USART_CR1_M1_Msk             (0x1U << USART_CR1_M1_Pos)                /*!< 0x10000000 */
28946 #define USART_CR1_M1                 USART_CR1_M1_Msk                          /*!< Word length - Bit 1 */
28947 #define USART_CR1_FIFOEN_Pos         (29U)
28948 #define USART_CR1_FIFOEN_Msk         (0x1U << USART_CR1_FIFOEN_Pos)            /*!< 0x20000000 */
28949 #define USART_CR1_FIFOEN             USART_CR1_FIFOEN_Msk                      /*!< FIFO mode enable */
28950 #define USART_CR1_TXFEIE_Pos         (30U)
28951 #define USART_CR1_TXFEIE_Msk         (0x1U << USART_CR1_TXFEIE_Pos)            /*!< 0x40000000 */
28952 #define USART_CR1_TXFEIE             USART_CR1_TXFEIE_Msk                      /*!< TXFIFO empty interrupt enable */
28953 #define USART_CR1_RXFFIE_Pos         (31U)
28954 #define USART_CR1_RXFFIE_Msk         (0x1U << USART_CR1_RXFFIE_Pos)            /*!< 0x80000000 */
28955 #define USART_CR1_RXFFIE             USART_CR1_RXFFIE_Msk                      /*!< RXFIFO Full interrupt enable */
28956 
28957 /******************  Bit definition for USART_CR2 register  *******************/
28958 #define USART_CR2_SLVEN_Pos          (0U)
28959 #define USART_CR2_SLVEN_Msk          (0x1U << USART_CR2_SLVEN_Pos)             /*!< 0x00000001 */
28960 #define USART_CR2_SLVEN              USART_CR2_SLVEN_Msk                       /*!< Synchronous Slave mode enable */
28961 #define USART_CR2_DIS_NSS_Pos        (3U)
28962 #define USART_CR2_DIS_NSS_Msk        (0x1U << USART_CR2_DIS_NSS_Pos)           /*!< 0x00000008 */
28963 #define USART_CR2_DIS_NSS            USART_CR2_DIS_NSS_Msk                     /*!< Slave Select (NSS) pin management */
28964 #define USART_CR2_ADDM7_Pos          (4U)
28965 #define USART_CR2_ADDM7_Msk          (0x1U << USART_CR2_ADDM7_Pos)             /*!< 0x00000010 */
28966 #define USART_CR2_ADDM7              USART_CR2_ADDM7_Msk                       /*!< 7-bit or 4-bit Address Detection */
28967 #define USART_CR2_LBDL_Pos           (5U)
28968 #define USART_CR2_LBDL_Msk           (0x1U << USART_CR2_LBDL_Pos)              /*!< 0x00000020 */
28969 #define USART_CR2_LBDL               USART_CR2_LBDL_Msk                        /*!< LIN Break Detection Length */
28970 #define USART_CR2_LBDIE_Pos          (6U)
28971 #define USART_CR2_LBDIE_Msk          (0x1U << USART_CR2_LBDIE_Pos)             /*!< 0x00000040 */
28972 #define USART_CR2_LBDIE              USART_CR2_LBDIE_Msk                       /*!< LIN Break Detection Interrupt Enable */
28973 #define USART_CR2_LBCL_Pos           (8U)
28974 #define USART_CR2_LBCL_Msk           (0x1U << USART_CR2_LBCL_Pos)              /*!< 0x00000100 */
28975 #define USART_CR2_LBCL               USART_CR2_LBCL_Msk                        /*!< Last Bit Clock pulse */
28976 #define USART_CR2_CPHA_Pos           (9U)
28977 #define USART_CR2_CPHA_Msk           (0x1U << USART_CR2_CPHA_Pos)              /*!< 0x00000200 */
28978 #define USART_CR2_CPHA               USART_CR2_CPHA_Msk                        /*!< Clock Phase */
28979 #define USART_CR2_CPOL_Pos           (10U)
28980 #define USART_CR2_CPOL_Msk           (0x1U << USART_CR2_CPOL_Pos)              /*!< 0x00000400 */
28981 #define USART_CR2_CPOL               USART_CR2_CPOL_Msk                        /*!< Clock Polarity */
28982 #define USART_CR2_CLKEN_Pos          (11U)
28983 #define USART_CR2_CLKEN_Msk          (0x1U << USART_CR2_CLKEN_Pos)             /*!< 0x00000800 */
28984 #define USART_CR2_CLKEN              USART_CR2_CLKEN_Msk                       /*!< Clock Enable */
28985 #define USART_CR2_STOP_Pos           (12U)
28986 #define USART_CR2_STOP_Msk           (0x3U << USART_CR2_STOP_Pos)              /*!< 0x00003000 */
28987 #define USART_CR2_STOP               USART_CR2_STOP_Msk                        /*!< STOP[1:0] bits (STOP bits) */
28988 #define USART_CR2_STOP_0             (0x1U << USART_CR2_STOP_Pos)              /*!< 0x00001000 */
28989 #define USART_CR2_STOP_1             (0x2U << USART_CR2_STOP_Pos)              /*!< 0x00002000 */
28990 #define USART_CR2_LINEN_Pos          (14U)
28991 #define USART_CR2_LINEN_Msk          (0x1U << USART_CR2_LINEN_Pos)             /*!< 0x00004000 */
28992 #define USART_CR2_LINEN              USART_CR2_LINEN_Msk                       /*!< LIN mode enable */
28993 #define USART_CR2_SWAP_Pos           (15U)
28994 #define USART_CR2_SWAP_Msk           (0x1U << USART_CR2_SWAP_Pos)              /*!< 0x00008000 */
28995 #define USART_CR2_SWAP               USART_CR2_SWAP_Msk                        /*!< SWAP TX/RX pins */
28996 #define USART_CR2_RXINV_Pos          (16U)
28997 #define USART_CR2_RXINV_Msk          (0x1U << USART_CR2_RXINV_Pos)             /*!< 0x00010000 */
28998 #define USART_CR2_RXINV              USART_CR2_RXINV_Msk                       /*!< RX pin active level inversion */
28999 #define USART_CR2_TXINV_Pos          (17U)
29000 #define USART_CR2_TXINV_Msk          (0x1U << USART_CR2_TXINV_Pos)             /*!< 0x00020000 */
29001 #define USART_CR2_TXINV              USART_CR2_TXINV_Msk                       /*!< TX pin active level inversion */
29002 #define USART_CR2_DATAINV_Pos        (18U)
29003 #define USART_CR2_DATAINV_Msk        (0x1U << USART_CR2_DATAINV_Pos)           /*!< 0x00040000 */
29004 #define USART_CR2_DATAINV            USART_CR2_DATAINV_Msk                     /*!< Binary data inversion */
29005 #define USART_CR2_MSBFIRST_Pos       (19U)
29006 #define USART_CR2_MSBFIRST_Msk       (0x1U << USART_CR2_MSBFIRST_Pos)          /*!< 0x00080000 */
29007 #define USART_CR2_MSBFIRST           USART_CR2_MSBFIRST_Msk                    /*!< Most Significant Bit First */
29008 #define USART_CR2_ABREN_Pos          (20U)
29009 #define USART_CR2_ABREN_Msk          (0x1U << USART_CR2_ABREN_Pos)             /*!< 0x00100000 */
29010 #define USART_CR2_ABREN              USART_CR2_ABREN_Msk                       /*!< Auto Baud-Rate Enable*/
29011 #define USART_CR2_ABRMODE_Pos        (21U)
29012 #define USART_CR2_ABRMODE_Msk        (0x3U << USART_CR2_ABRMODE_Pos)           /*!< 0x00600000 */
29013 #define USART_CR2_ABRMODE            USART_CR2_ABRMODE_Msk                     /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
29014 #define USART_CR2_ABRMODE_0          (0x1U << USART_CR2_ABRMODE_Pos)           /*!< 0x00200000 */
29015 #define USART_CR2_ABRMODE_1          (0x2U << USART_CR2_ABRMODE_Pos)           /*!< 0x00400000 */
29016 #define USART_CR2_RTOEN_Pos          (23U)
29017 #define USART_CR2_RTOEN_Msk          (0x1U << USART_CR2_RTOEN_Pos)             /*!< 0x00800000 */
29018 #define USART_CR2_RTOEN              USART_CR2_RTOEN_Msk                       /*!< Receiver Time-Out enable */
29019 #define USART_CR2_ADD_Pos            (24U)
29020 #define USART_CR2_ADD_Msk            (0xFFU << USART_CR2_ADD_Pos)              /*!< 0xFF000000 */
29021 #define USART_CR2_ADD                USART_CR2_ADD_Msk                         /*!< Address of the USART node */
29022 
29023 /******************  Bit definition for USART_CR3 register  *******************/
29024 #define USART_CR3_EIE_Pos            (0U)
29025 #define USART_CR3_EIE_Msk            (0x1U << USART_CR3_EIE_Pos)               /*!< 0x00000001 */
29026 #define USART_CR3_EIE                USART_CR3_EIE_Msk                         /*!< Error Interrupt Enable */
29027 #define USART_CR3_IREN_Pos           (1U)
29028 #define USART_CR3_IREN_Msk           (0x1U << USART_CR3_IREN_Pos)              /*!< 0x00000002 */
29029 #define USART_CR3_IREN               USART_CR3_IREN_Msk                        /*!< IrDA mode Enable */
29030 #define USART_CR3_IRLP_Pos           (2U)
29031 #define USART_CR3_IRLP_Msk           (0x1U << USART_CR3_IRLP_Pos)              /*!< 0x00000004 */
29032 #define USART_CR3_IRLP               USART_CR3_IRLP_Msk                        /*!< IrDA Low-Power */
29033 #define USART_CR3_HDSEL_Pos          (3U)
29034 #define USART_CR3_HDSEL_Msk          (0x1U << USART_CR3_HDSEL_Pos)             /*!< 0x00000008 */
29035 #define USART_CR3_HDSEL              USART_CR3_HDSEL_Msk                       /*!< Half-Duplex Selection */
29036 #define USART_CR3_NACK_Pos           (4U)
29037 #define USART_CR3_NACK_Msk           (0x1U << USART_CR3_NACK_Pos)              /*!< 0x00000010 */
29038 #define USART_CR3_NACK               USART_CR3_NACK_Msk                        /*!< SmartCard NACK enable */
29039 #define USART_CR3_SCEN_Pos           (5U)
29040 #define USART_CR3_SCEN_Msk           (0x1U << USART_CR3_SCEN_Pos)              /*!< 0x00000020 */
29041 #define USART_CR3_SCEN               USART_CR3_SCEN_Msk                        /*!< SmartCard mode enable */
29042 #define USART_CR3_DMAR_Pos           (6U)
29043 #define USART_CR3_DMAR_Msk           (0x1U << USART_CR3_DMAR_Pos)              /*!< 0x00000040 */
29044 #define USART_CR3_DMAR               USART_CR3_DMAR_Msk                        /*!< DMA Enable Receiver */
29045 #define USART_CR3_DMAT_Pos           (7U)
29046 #define USART_CR3_DMAT_Msk           (0x1U << USART_CR3_DMAT_Pos)              /*!< 0x00000080 */
29047 #define USART_CR3_DMAT               USART_CR3_DMAT_Msk                        /*!< DMA Enable Transmitter */
29048 #define USART_CR3_RTSE_Pos           (8U)
29049 #define USART_CR3_RTSE_Msk           (0x1U << USART_CR3_RTSE_Pos)              /*!< 0x00000100 */
29050 #define USART_CR3_RTSE               USART_CR3_RTSE_Msk                        /*!< RTS Enable */
29051 #define USART_CR3_CTSE_Pos           (9U)
29052 #define USART_CR3_CTSE_Msk           (0x1U << USART_CR3_CTSE_Pos)              /*!< 0x00000200 */
29053 #define USART_CR3_CTSE               USART_CR3_CTSE_Msk                        /*!< CTS Enable */
29054 #define USART_CR3_CTSIE_Pos          (10U)
29055 #define USART_CR3_CTSIE_Msk          (0x1U << USART_CR3_CTSIE_Pos)             /*!< 0x00000400 */
29056 #define USART_CR3_CTSIE              USART_CR3_CTSIE_Msk                       /*!< CTS Interrupt Enable */
29057 #define USART_CR3_ONEBIT_Pos         (11U)
29058 #define USART_CR3_ONEBIT_Msk         (0x1U << USART_CR3_ONEBIT_Pos)            /*!< 0x00000800 */
29059 #define USART_CR3_ONEBIT             USART_CR3_ONEBIT_Msk                      /*!< One sample bit method enable */
29060 #define USART_CR3_OVRDIS_Pos         (12U)
29061 #define USART_CR3_OVRDIS_Msk         (0x1U << USART_CR3_OVRDIS_Pos)            /*!< 0x00001000 */
29062 #define USART_CR3_OVRDIS             USART_CR3_OVRDIS_Msk                      /*!< Overrun Disable */
29063 #define USART_CR3_DDRE_Pos           (13U)
29064 #define USART_CR3_DDRE_Msk           (0x1U << USART_CR3_DDRE_Pos)              /*!< 0x00002000 */
29065 #define USART_CR3_DDRE               USART_CR3_DDRE_Msk                        /*!< DMA Disable on Reception Error */
29066 #define USART_CR3_DEM_Pos            (14U)
29067 #define USART_CR3_DEM_Msk            (0x1U << USART_CR3_DEM_Pos)               /*!< 0x00004000 */
29068 #define USART_CR3_DEM                USART_CR3_DEM_Msk                         /*!< Driver Enable Mode */
29069 #define USART_CR3_DEP_Pos            (15U)
29070 #define USART_CR3_DEP_Msk            (0x1U << USART_CR3_DEP_Pos)               /*!< 0x00008000 */
29071 #define USART_CR3_DEP                USART_CR3_DEP_Msk                         /*!< Driver Enable Polarity Selection */
29072 #define USART_CR3_SCARCNT_Pos        (17U)
29073 #define USART_CR3_SCARCNT_Msk        (0x7U << USART_CR3_SCARCNT_Pos)           /*!< 0x000E0000 */
29074 #define USART_CR3_SCARCNT            USART_CR3_SCARCNT_Msk                     /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
29075 #define USART_CR3_SCARCNT_0          (0x1U << USART_CR3_SCARCNT_Pos)           /*!< 0x00020000 */
29076 #define USART_CR3_SCARCNT_1          (0x2U << USART_CR3_SCARCNT_Pos)           /*!< 0x00040000 */
29077 #define USART_CR3_SCARCNT_2          (0x4U << USART_CR3_SCARCNT_Pos)           /*!< 0x00080000 */
29078 #define USART_CR3_WUS_Pos            (20U)
29079 #define USART_CR3_WUS_Msk            (0x3U << USART_CR3_WUS_Pos)               /*!< 0x00300000 */
29080 #define USART_CR3_WUS                USART_CR3_WUS_Msk                         /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
29081 #define USART_CR3_WUS_0              (0x1U << USART_CR3_WUS_Pos)               /*!< 0x00100000 */
29082 #define USART_CR3_WUS_1              (0x2U << USART_CR3_WUS_Pos)               /*!< 0x00200000 */
29083 #define USART_CR3_WUFIE_Pos          (22U)
29084 #define USART_CR3_WUFIE_Msk          (0x1U << USART_CR3_WUFIE_Pos)             /*!< 0x00400000 */
29085 #define USART_CR3_WUFIE              USART_CR3_WUFIE_Msk                       /*!< Wake Up Interrupt Enable */
29086 #define USART_CR3_TXFTIE_Pos         (23U)
29087 #define USART_CR3_TXFTIE_Msk         (0x1U << USART_CR3_TXFTIE_Pos)            /*!< 0x00800000 */
29088 #define USART_CR3_TXFTIE             USART_CR3_TXFTIE_Msk                      /*!< TXFIFO threshold interrupt enable */
29089 #define USART_CR3_TCBGTIE_Pos        (24U)
29090 #define USART_CR3_TCBGTIE_Msk        (0x1U << USART_CR3_TCBGTIE_Pos)           /*!< 0x01000000 */
29091 #define USART_CR3_TCBGTIE            USART_CR3_TCBGTIE_Msk                     /*!< Transmission Complete Before Guard Time Interrupt Enable */
29092 #define USART_CR3_RXFTCFG_Pos        (25U)
29093 #define USART_CR3_RXFTCFG_Msk        (0x7U << USART_CR3_RXFTCFG_Pos)           /*!< 0x0E000000 */
29094 #define USART_CR3_RXFTCFG            USART_CR3_RXFTCFG_Msk                     /*!< RXFIFO FIFO threshold configuration */
29095 #define USART_CR3_RXFTCFG_0          (0x1U << USART_CR3_RXFTCFG_Pos)           /*!< 0x02000000 */
29096 #define USART_CR3_RXFTCFG_1          (0x2U << USART_CR3_RXFTCFG_Pos)           /*!< 0x04000000 */
29097 #define USART_CR3_RXFTCFG_2          (0x4U << USART_CR3_RXFTCFG_Pos)           /*!< 0x08000000 */
29098 #define USART_CR3_RXFTIE_Pos         (28U)
29099 #define USART_CR3_RXFTIE_Msk         (0x1U << USART_CR3_RXFTIE_Pos)            /*!< 0x10000000 */
29100 #define USART_CR3_RXFTIE             USART_CR3_RXFTIE_Msk                      /*!< RXFIFO threshold interrupt enable */
29101 #define USART_CR3_TXFTCFG_Pos        (29U)
29102 #define USART_CR3_TXFTCFG_Msk        (0x7U << USART_CR3_TXFTCFG_Pos)           /*!< 0xE0000000 */
29103 #define USART_CR3_TXFTCFG            USART_CR3_TXFTCFG_Msk                     /*!< TXFIFO threshold configuration */
29104 #define USART_CR3_TXFTCFG_0          (0x1U << USART_CR3_TXFTCFG_Pos)           /*!< 0x20000000 */
29105 #define USART_CR3_TXFTCFG_1          (0x2U << USART_CR3_TXFTCFG_Pos)           /*!< 0x40000000 */
29106 #define USART_CR3_TXFTCFG_2          (0x4U << USART_CR3_TXFTCFG_Pos)           /*!< 0x80000000 */
29107 
29108 /******************  Bit definition for USART_BRR register  *******************/
29109 #define USART_BRR_LPUART_Pos         (0U)
29110 #define USART_BRR_LPUART_Msk         (0xFFFFFU << USART_BRR_LPUART_Pos)        /*!< 0x000FFFFF */
29111 #define USART_BRR_LPUART             USART_BRR_LPUART_Msk                      /*!< LPUART Baud rate register [19:0] */
29112 #define USART_BRR_BRR_Pos            (0U)
29113 #define USART_BRR_BRR_Msk            (0xFFFFU << USART_BRR_BRR_Pos)            /*!< 0x0000FFFF */
29114 #define USART_BRR_BRR                USART_BRR_BRR_Msk                         /*!< USART Baud rate register [15:0] */
29115 
29116 /******************  Bit definition for USART_GTPR register  ******************/
29117 #define USART_GTPR_PSC_Pos           (0U)
29118 #define USART_GTPR_PSC_Msk           (0xFFU << USART_GTPR_PSC_Pos)             /*!< 0x000000FF */
29119 #define USART_GTPR_PSC               USART_GTPR_PSC_Msk                        /*!< PSC[7:0] bits (Prescaler value) */
29120 #define USART_GTPR_GT_Pos            (8U)
29121 #define USART_GTPR_GT_Msk            (0xFFU << USART_GTPR_GT_Pos)              /*!< 0x0000FF00 */
29122 #define USART_GTPR_GT                USART_GTPR_GT_Msk                         /*!< GT[7:0] bits (Guard time value) */
29123 
29124 /*******************  Bit definition for USART_RTOR register  *****************/
29125 #define USART_RTOR_RTO_Pos           (0U)
29126 #define USART_RTOR_RTO_Msk           (0xFFFFFFU << USART_RTOR_RTO_Pos)         /*!< 0x00FFFFFF */
29127 #define USART_RTOR_RTO               USART_RTOR_RTO_Msk                        /*!< Receiver Time Out Value */
29128 #define USART_RTOR_BLEN_Pos          (24U)
29129 #define USART_RTOR_BLEN_Msk          (0xFFU << USART_RTOR_BLEN_Pos)            /*!< 0xFF000000 */
29130 #define USART_RTOR_BLEN              USART_RTOR_BLEN_Msk                       /*!< Block Length */
29131 
29132 /*******************  Bit definition for USART_RQR register  ******************/
29133 #define USART_RQR_ABRRQ_Pos          (0U)
29134 #define USART_RQR_ABRRQ_Msk          (0x1U << USART_RQR_ABRRQ_Pos)             /*!< 0x00000001 */
29135 #define USART_RQR_ABRRQ              USART_RQR_ABRRQ_Msk                       /*!< Auto-Baud Rate Request */
29136 #define USART_RQR_SBKRQ_Pos          (1U)
29137 #define USART_RQR_SBKRQ_Msk          (0x1U << USART_RQR_SBKRQ_Pos)             /*!< 0x00000002 */
29138 #define USART_RQR_SBKRQ              USART_RQR_SBKRQ_Msk                       /*!< Send Break Request */
29139 #define USART_RQR_MMRQ_Pos           (2U)
29140 #define USART_RQR_MMRQ_Msk           (0x1U << USART_RQR_MMRQ_Pos)              /*!< 0x00000004 */
29141 #define USART_RQR_MMRQ               USART_RQR_MMRQ_Msk                        /*!< Mute Mode Request */
29142 #define USART_RQR_RXFRQ_Pos          (3U)
29143 #define USART_RQR_RXFRQ_Msk          (0x1U << USART_RQR_RXFRQ_Pos)             /*!< 0x00000008 */
29144 #define USART_RQR_RXFRQ              USART_RQR_RXFRQ_Msk                       /*!< Receive Data flush Request */
29145 #define USART_RQR_TXFRQ_Pos          (4U)
29146 #define USART_RQR_TXFRQ_Msk          (0x1U << USART_RQR_TXFRQ_Pos)             /*!< 0x00000010 */
29147 #define USART_RQR_TXFRQ              USART_RQR_TXFRQ_Msk                       /*!< Transmit data flush Request */
29148 
29149 /*******************  Bit definition for USART_ISR register  ******************/
29150 #define USART_ISR_PE_Pos             (0U)
29151 #define USART_ISR_PE_Msk             (0x1U << USART_ISR_PE_Pos)                /*!< 0x00000001 */
29152 #define USART_ISR_PE                 USART_ISR_PE_Msk                          /*!< Parity Error */
29153 #define USART_ISR_FE_Pos             (1U)
29154 #define USART_ISR_FE_Msk             (0x1U << USART_ISR_FE_Pos)                /*!< 0x00000002 */
29155 #define USART_ISR_FE                 USART_ISR_FE_Msk                          /*!< Framing Error */
29156 #define USART_ISR_NE_Pos             (2U)
29157 #define USART_ISR_NE_Msk             (0x1U << USART_ISR_NE_Pos)                /*!< 0x00000004 */
29158 #define USART_ISR_NE                 USART_ISR_NE_Msk                          /*!< Noise detected Flag */
29159 #define USART_ISR_ORE_Pos            (3U)
29160 #define USART_ISR_ORE_Msk            (0x1U << USART_ISR_ORE_Pos)               /*!< 0x00000008 */
29161 #define USART_ISR_ORE                USART_ISR_ORE_Msk                         /*!< OverRun Error */
29162 #define USART_ISR_IDLE_Pos           (4U)
29163 #define USART_ISR_IDLE_Msk           (0x1U << USART_ISR_IDLE_Pos)              /*!< 0x00000010 */
29164 #define USART_ISR_IDLE               USART_ISR_IDLE_Msk                        /*!< IDLE line detected */
29165 #define USART_ISR_RXNE_Pos           (5U)
29166 #define USART_ISR_RXNE_Msk           (0x1U << USART_ISR_RXNE_Pos)              /*!< 0x00000020 */
29167 #define USART_ISR_RXNE               USART_ISR_RXNE_Msk                        /*!< Read Data Register Not Empty */
29168 #define USART_ISR_RXNE_RXFNE_Pos     USART_ISR_RXNE_Pos
29169 #define USART_ISR_RXNE_RXFNE_Msk     USART_ISR_RXNE_Msk                        /*!< 0x00000020 */
29170 #define USART_ISR_RXNE_RXFNE         USART_ISR_RXNE_Msk                        /*!< Read Data Register or RX FIFO Not Empty */
29171 #define USART_ISR_TC_Pos             (6U)
29172 #define USART_ISR_TC_Msk             (0x1U << USART_ISR_TC_Pos)                /*!< 0x00000040 */
29173 #define USART_ISR_TC                 USART_ISR_TC_Msk                          /*!< Transmission Complete */
29174 #define USART_ISR_TXE_Pos            (7U)
29175 #define USART_ISR_TXE_Msk            (0x1U << USART_ISR_TXE_Pos)               /*!< 0x00000080 */
29176 #define USART_ISR_TXE                USART_ISR_TXE_Msk                         /*!< Transmit Data Register Empty */
29177 #define USART_ISR_TXE_TXFNF_Pos      USART_ISR_TXE_Pos
29178 #define USART_ISR_TXE_TXFNF_Msk      USART_ISR_TXE_Msk                       /*!< 0x00000080 */
29179 #define USART_ISR_TXE_TXFNF          USART_ISR_TXE_Msk                       /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
29180 #define USART_ISR_LBDF_Pos           (8U)
29181 #define USART_ISR_LBDF_Msk           (0x1U << USART_ISR_LBDF_Pos)              /*!< 0x00000100 */
29182 #define USART_ISR_LBDF               USART_ISR_LBDF_Msk                        /*!< LIN Break Detection Flag */
29183 #define USART_ISR_CTSIF_Pos          (9U)
29184 #define USART_ISR_CTSIF_Msk          (0x1U << USART_ISR_CTSIF_Pos)             /*!< 0x00000200 */
29185 #define USART_ISR_CTSIF              USART_ISR_CTSIF_Msk                       /*!< CTS interrupt flag */
29186 #define USART_ISR_CTS_Pos            (10U)
29187 #define USART_ISR_CTS_Msk            (0x1U << USART_ISR_CTS_Pos)               /*!< 0x00000400 */
29188 #define USART_ISR_CTS                USART_ISR_CTS_Msk                         /*!< CTS flag */
29189 #define USART_ISR_RTOF_Pos           (11U)
29190 #define USART_ISR_RTOF_Msk           (0x1U << USART_ISR_RTOF_Pos)              /*!< 0x00000800 */
29191 #define USART_ISR_RTOF               USART_ISR_RTOF_Msk                        /*!< Receiver Time Out */
29192 #define USART_ISR_EOBF_Pos           (12U)
29193 #define USART_ISR_EOBF_Msk           (0x1U << USART_ISR_EOBF_Pos)              /*!< 0x00001000 */
29194 #define USART_ISR_EOBF               USART_ISR_EOBF_Msk                        /*!< End Of Block Flag */
29195 #define USART_ISR_UDR_Pos            (13U)
29196 #define USART_ISR_UDR_Msk            (0x1U << USART_ISR_UDR_Pos)               /*!< 0x00002000 */
29197 #define USART_ISR_UDR                USART_ISR_UDR_Msk                         /*!< SPI slave underrun error flag */
29198 #define USART_ISR_ABRE_Pos           (14U)
29199 #define USART_ISR_ABRE_Msk           (0x1U << USART_ISR_ABRE_Pos)              /*!< 0x00004000 */
29200 #define USART_ISR_ABRE               USART_ISR_ABRE_Msk                        /*!< Auto-Baud Rate Error */
29201 #define USART_ISR_ABRF_Pos           (15U)
29202 #define USART_ISR_ABRF_Msk           (0x1U << USART_ISR_ABRF_Pos)              /*!< 0x00008000 */
29203 #define USART_ISR_ABRF               USART_ISR_ABRF_Msk                        /*!< Auto-Baud Rate Flag */
29204 #define USART_ISR_BUSY_Pos           (16U)
29205 #define USART_ISR_BUSY_Msk           (0x1U << USART_ISR_BUSY_Pos)              /*!< 0x00010000 */
29206 #define USART_ISR_BUSY               USART_ISR_BUSY_Msk                        /*!< Busy Flag */
29207 #define USART_ISR_CMF_Pos            (17U)
29208 #define USART_ISR_CMF_Msk            (0x1U << USART_ISR_CMF_Pos)               /*!< 0x00020000 */
29209 #define USART_ISR_CMF                USART_ISR_CMF_Msk                         /*!< Character Match Flag */
29210 #define USART_ISR_SBKF_Pos           (18U)
29211 #define USART_ISR_SBKF_Msk           (0x1U << USART_ISR_SBKF_Pos)              /*!< 0x00040000 */
29212 #define USART_ISR_SBKF               USART_ISR_SBKF_Msk                        /*!< Send Break Flag */
29213 #define USART_ISR_RWU_Pos            (19U)
29214 #define USART_ISR_RWU_Msk            (0x1U << USART_ISR_RWU_Pos)               /*!< 0x00080000 */
29215 #define USART_ISR_RWU                USART_ISR_RWU_Msk                         /*!< Receive Wake Up from mute mode Flag */
29216 #define USART_ISR_WUF_Pos            (20U)
29217 #define USART_ISR_WUF_Msk            (0x1U << USART_ISR_WUF_Pos)               /*!< 0x00100000 */
29218 #define USART_ISR_WUF                USART_ISR_WUF_Msk                         /*!< Wake Up from stop mode Flag */
29219 #define USART_ISR_TEACK_Pos          (21U)
29220 #define USART_ISR_TEACK_Msk          (0x1U << USART_ISR_TEACK_Pos)             /*!< 0x00200000 */
29221 #define USART_ISR_TEACK              USART_ISR_TEACK_Msk                       /*!< Transmit Enable Acknowledge Flag */
29222 #define USART_ISR_REACK_Pos          (22U)
29223 #define USART_ISR_REACK_Msk          (0x1U << USART_ISR_REACK_Pos)             /*!< 0x00400000 */
29224 #define USART_ISR_REACK              USART_ISR_REACK_Msk                       /*!< Receive Enable Acknowledge Flag */
29225 #define USART_ISR_TXFE_Pos           (23U)
29226 #define USART_ISR_TXFE_Msk           (0x1U << USART_ISR_TXFE_Pos)              /*!< 0x00800000 */
29227 #define USART_ISR_TXFE               USART_ISR_TXFE_Msk                        /*!< TXFIFO Empty */
29228 #define USART_ISR_RXFF_Pos           (24U)
29229 #define USART_ISR_RXFF_Msk           (0x1U << USART_ISR_RXFF_Pos)              /*!< 0x01000000 */
29230 #define USART_ISR_RXFF               USART_ISR_RXFF_Msk                        /*!< RXFIFO Full */
29231 #define USART_ISR_TCBGT_Pos          (25U)
29232 #define USART_ISR_TCBGT_Msk          (0x1U << USART_ISR_TCBGT_Pos)             /*!< 0x02000000 */
29233 #define USART_ISR_TCBGT              USART_ISR_TCBGT_Msk                       /*!< Transmission Complete Before Guard Time completion */
29234 #define USART_ISR_RXFT_Pos           (26U)
29235 #define USART_ISR_RXFT_Msk           (0x1U << USART_ISR_RXFT_Pos)              /*!< 0x04000000 */
29236 #define USART_ISR_RXFT               USART_ISR_RXFT_Msk                        /*!< RXFIFO threshold flag */
29237 #define USART_ISR_TXFT_Pos           (27U)
29238 #define USART_ISR_TXFT_Msk           (0x1U << USART_ISR_TXFT_Pos)              /*!< 0x08000000 */
29239 #define USART_ISR_TXFT               USART_ISR_TXFT_Msk                        /*!< TXFIFO threshold flag */
29240 
29241 /*******************  Bit definition for USART_ICR register  ******************/
29242 #define USART_ICR_PECF_Pos           (0U)
29243 #define USART_ICR_PECF_Msk           (0x1U << USART_ICR_PECF_Pos)              /*!< 0x00000001 */
29244 #define USART_ICR_PECF               USART_ICR_PECF_Msk                        /*!< Parity Error Clear Flag */
29245 #define USART_ICR_FECF_Pos           (1U)
29246 #define USART_ICR_FECF_Msk           (0x1U << USART_ICR_FECF_Pos)              /*!< 0x00000002 */
29247 #define USART_ICR_FECF               USART_ICR_FECF_Msk                        /*!< Framing Error Clear Flag */
29248 #define USART_ICR_NECF_Pos           (2U)
29249 #define USART_ICR_NECF_Msk           (0x1U << USART_ICR_NECF_Pos)              /*!< 0x00000004 */
29250 #define USART_ICR_NECF               USART_ICR_NECF_Msk                        /*!< Noise detected Clear Flag */
29251 #define USART_ICR_ORECF_Pos          (3U)
29252 #define USART_ICR_ORECF_Msk          (0x1U << USART_ICR_ORECF_Pos)             /*!< 0x00000008 */
29253 #define USART_ICR_ORECF              USART_ICR_ORECF_Msk                       /*!< OverRun Error Clear Flag */
29254 #define USART_ICR_IDLECF_Pos         (4U)
29255 #define USART_ICR_IDLECF_Msk         (0x1U << USART_ICR_IDLECF_Pos)            /*!< 0x00000010 */
29256 #define USART_ICR_IDLECF             USART_ICR_IDLECF_Msk                      /*!< IDLE line detected Clear Flag */
29257 #define USART_ICR_TXFECF_Pos         (5U)
29258 #define USART_ICR_TXFECF_Msk         (0x1U << USART_ICR_TXFECF_Pos)            /*!< 0x00000020 */
29259 #define USART_ICR_TXFECF             USART_ICR_TXFECF_Msk                      /*!< TXFIFO empty Clear flag */
29260 #define USART_ICR_TCCF_Pos           (6U)
29261 #define USART_ICR_TCCF_Msk           (0x1U << USART_ICR_TCCF_Pos)              /*!< 0x00000040 */
29262 #define USART_ICR_TCCF               USART_ICR_TCCF_Msk                        /*!< Transmission Complete Clear Flag */
29263 #define USART_ICR_TCBGTCF_Pos        (7U)
29264 #define USART_ICR_TCBGTCF_Msk        (0x1U << USART_ICR_TCBGTCF_Pos)           /*!< 0x00000080 */
29265 #define USART_ICR_TCBGTCF            USART_ICR_TCBGTCF_Msk                     /*!< Transmission Complete Before Guard Time Clear Flag */
29266 #define USART_ICR_LBDCF_Pos          (8U)
29267 #define USART_ICR_LBDCF_Msk          (0x1U << USART_ICR_LBDCF_Pos)             /*!< 0x00000100 */
29268 #define USART_ICR_LBDCF              USART_ICR_LBDCF_Msk                       /*!< LIN Break Detection Clear Flag */
29269 #define USART_ICR_CTSCF_Pos          (9U)
29270 #define USART_ICR_CTSCF_Msk          (0x1U << USART_ICR_CTSCF_Pos)             /*!< 0x00000200 */
29271 #define USART_ICR_CTSCF              USART_ICR_CTSCF_Msk                       /*!< CTS Interrupt Clear Flag */
29272 #define USART_ICR_RTOCF_Pos          (11U)
29273 #define USART_ICR_RTOCF_Msk          (0x1U << USART_ICR_RTOCF_Pos)             /*!< 0x00000800 */
29274 #define USART_ICR_RTOCF              USART_ICR_RTOCF_Msk                       /*!< Receiver Time Out Clear Flag */
29275 #define USART_ICR_EOBCF_Pos          (12U)
29276 #define USART_ICR_EOBCF_Msk          (0x1U << USART_ICR_EOBCF_Pos)             /*!< 0x00001000 */
29277 #define USART_ICR_EOBCF              USART_ICR_EOBCF_Msk                       /*!< End Of Block Clear Flag */
29278 #define USART_ICR_UDRCF_Pos          (13U)
29279 #define USART_ICR_UDRCF_Msk          (0x1U << USART_ICR_UDRCF_Pos)             /*!< 0x00002000 */
29280 #define USART_ICR_UDRCF              USART_ICR_UDRCF_Msk                       /*!< SPI Slave Underrun Clear Flag */
29281 #define USART_ICR_CMCF_Pos           (17U)
29282 #define USART_ICR_CMCF_Msk           (0x1U << USART_ICR_CMCF_Pos)              /*!< 0x00020000 */
29283 #define USART_ICR_CMCF               USART_ICR_CMCF_Msk                        /*!< Character Match Clear Flag */
29284 #define USART_ICR_WUCF_Pos           (20U)
29285 #define USART_ICR_WUCF_Msk           (0x1U << USART_ICR_WUCF_Pos)              /*!< 0x00100000 */
29286 #define USART_ICR_WUCF               USART_ICR_WUCF_Msk                        /*!< Wake Up from stop mode Clear Flag */
29287 
29288 /*******************  Bit definition for USART_RDR register  ******************/
29289 #define USART_RDR_RDR_Pos            (0U)
29290 #define USART_RDR_RDR_Msk            (0x1FF << USART_RDR_RDR_Pos)              /*!< 0x000001FF */
29291 #define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
29292 
29293 /*******************  Bit definition for USART_TDR register  ******************/
29294 #define USART_TDR_TDR_Pos            (0U)
29295 #define USART_TDR_TDR_Msk            (0x1FF << USART_TDR_TDR_Pos)              /*!< 0x000001FF */
29296 #define USART_TDR_TDR                USART_TDR_TDR_Msk                         /*!< TDR[8:0] bits (Transmit Data value) */
29297 
29298 /*******************  Bit definition for USART_PRESC register  ****************/
29299 #define USART_PRESC_PRESCALER_Pos    (0U)
29300 #define USART_PRESC_PRESCALER_Msk    (0xFU << USART_PRESC_PRESCALER_Pos)       /*!< 0x0000000F */
29301 #define USART_PRESC_PRESCALER        USART_PRESC_PRESCALER_Msk                 /*!< PRESCALER[3:0] bits (Clock prescaler) */
29302 #define USART_PRESC_PRESCALER_0      (0x1U << USART_PRESC_PRESCALER_Pos)       /*!< 0x00000001 */
29303 #define USART_PRESC_PRESCALER_1      (0x2U << USART_PRESC_PRESCALER_Pos)       /*!< 0x00000002 */
29304 #define USART_PRESC_PRESCALER_2      (0x4U << USART_PRESC_PRESCALER_Pos)       /*!< 0x00000004 */
29305 #define USART_PRESC_PRESCALER_3      (0x8U << USART_PRESC_PRESCALER_Pos)       /*!< 0x00000008 */
29306 
29307 /**********************  Bit definition for USART_HWCFGR2 register  ***************/
29308 #define USART_HWCFGR2_CFG1_Pos  (0U)
29309 #define USART_HWCFGR2_CFG1_Msk  (0xFU << USART_HWCFGR2_CFG1_Pos)          /*!< 0x0000000F */
29310 #define USART_HWCFGR2_CFG1      USART_HWCFGR2_CFG1_Msk                    /*!< HW CFG1 */
29311 #define USART_HWCFGR2_CFG2_Pos  (4U)
29312 #define USART_HWCFGR2_CFG2_Msk  (0xFU << USART_HWCFGR2_CFG2_Pos)          /*!< 0x000000F0 */
29313 #define USART_HWCFGR2_CFG2      USART_HWCFGR2_CFG2_Msk                    /*!< HW CFG2 */
29314 
29315 /**********************  Bit definition for USART_HWCFGR1 register  ***************/
29316 #define USART_HWCFGR1_CFG1_Pos  (0U)
29317 #define USART_HWCFGR1_CFG1_Msk  (0xFU << USART_HWCFGR1_CFG1_Pos)          /*!< 0x0000000F */
29318 #define USART_HWCFGR1_CFG1      USART_HWCFGR1_CFG1_Msk                    /*!< HW CFG1 */
29319 #define USART_HWCFGR1_CFG2_Pos  (4U)
29320 #define USART_HWCFGR1_CFG2_Msk  (0xFU << USART_HWCFGR1_CFG2_Pos)          /*!< 0x000000F0 */
29321 #define USART_HWCFGR1_CFG2      USART_HWCFGR1_CFG2_Msk                    /*!< HW CFG2 */
29322 #define USART_HWCFGR1_CFG3_Pos  (8U)
29323 #define USART_HWCFGR1_CFG3_Msk  (0xFU << USART_HWCFGR1_CFG3_Pos)          /*!< 0x00000F00 */
29324 #define USART_HWCFGR1_CFG3      USART_HWCFGR1_CFG3_Msk                    /*!< HW CFG3 */
29325 #define USART_HWCFGR1_CFG4_Pos  (12U)
29326 #define USART_HWCFGR1_CFG4_Msk  (0xFU << USART_HWCFGR1_CFG4_Pos)          /*!< 0x0000F000 */
29327 #define USART_HWCFGR1_CFG4      USART_HWCFGR1_CFG4_Msk                    /*!< HW CFG4 */
29328 #define USART_HWCFGR1_CFG5_Pos  (16U)
29329 #define USART_HWCFGR1_CFG5_Msk  (0xFU << USART_HWCFGR1_CFG5_Pos)          /*!< 0x000F0000 */
29330 #define USART_HWCFGR1_CFG5      USART_HWCFGR1_CFG5_Msk                    /*!< HW CFG5 */
29331 #define USART_HWCFGR1_CFG6_Pos  (20U)
29332 #define USART_HWCFGR1_CFG6_Msk  (0xFU << USART_HWCFGR1_CFG6_Pos)          /*!< 0x00F00000 */
29333 #define USART_HWCFGR1_CFG6      USART_HWCFGR1_CFG6_Msk                    /*!< HW CFG6 */
29334 #define USART_HWCFGR1_CFG7_Pos  (24U)
29335 #define USART_HWCFGR1_CFG7_Msk  (0xFU << USART_HWCFGR1_CFG7_Pos)          /*!< 0x0F000000 */
29336 #define USART_HWCFGR1_CFG7      USART_HWCFGR1_CFG7_Msk                    /*!< HW CFG7 */
29337 #define USART_HWCFGR1_CFG8_Pos  (28U)
29338 #define USART_HWCFGR1_CFG8_Msk  (0xFU << USART_HWCFGR1_CFG8_Pos)          /*!< 0xF0000000 */
29339 #define USART_HWCFGR1_CFG8      USART_HWCFGR1_CFG8_Msk                    /*!< HW CFG8 */
29340 
29341 /**********************  Bit definition for USART_VERR register  *****************/
29342 #define USART_VERR_MINREV_Pos      (0U)
29343 #define USART_VERR_MINREV_Msk      (0xFU << USART_VERR_MINREV_Pos)               /*!< 0x0000000F */
29344 #define USART_VERR_MINREV          USART_VERR_MINREV_Msk                         /*!< Minor Revision number */
29345 #define USART_VERR_MAJREV_Pos      (4U)
29346 #define USART_VERR_MAJREV_Msk      (0xFU << USART_VERR_MAJREV_Pos)               /*!< 0x000000F0 */
29347 #define USART_VERR_MAJREV          USART_VERR_MAJREV_Msk                         /*!< Major Revision number */
29348 
29349 /**********************  Bit definition for USART_IPIDR register  ****************/
29350 #define USART_IPIDR_IPID_Pos       (0U)
29351 #define USART_IPIDR_IPID_Msk       (0xFFFFFFFFU << USART_IPIDR_IPID_Pos)         /*!< 0xFFFFFFFF */
29352 #define USART_IPIDR_IPID           USART_IPIDR_IPID_Msk                          /*!< IP Identification */
29353 
29354 /**********************  Bit definition for USART_SIDR register  *****************/
29355 #define USART_SIDR_SID_Pos         (0U)
29356 #define USART_SIDR_SID_Msk         (0xFFFFFFFFU << USART_SIDR_SID_Pos)           /*!< 0xFFFFFFFF */
29357 #define USART_SIDR_SID             USART_SIDR_SID_Msk                            /*!< IP size identification */
29358 
29359 /******************************************************************************/
29360 /*                                                                            */
29361 /*           Single Wire Protocol Master Interface (SWPMI)                    */
29362 /*                                                                            */
29363 /******************************************************************************/
29364 
29365 /*******************  Bit definition for SWPMI_CR register   ********************/
29366 #define SWPMI_CR_RXDMA           ((uint16_t)0x0001)                            /*!<Reception DMA enable                                 */
29367 #define SWPMI_CR_TXDMA           ((uint16_t)0x0002)                            /*!<Transmission DMA enable                              */
29368 #define SWPMI_CR_RXMODE          ((uint16_t)0x0004)                            /*!<Reception buffering mode                             */
29369 #define SWPMI_CR_TXMODE          ((uint16_t)0x0008)                            /*!<Transmission buffering mode                          */
29370 #define SWPMI_CR_LPBK            ((uint16_t)0x0010)                            /*!<Loopback mode enable                                 */
29371 #define SWPMI_CR_SWPACT          ((uint16_t)0x0020)                            /*!<Single wire protocol master interface activate       */
29372 #define SWPMI_CR_DEACT           ((uint16_t)0x0400)                            /*!<Single wire protocol master interface deactivate     */
29373 #define SWPMI_CR_SWPEN           ((uint16_t)0x0800)                            /*!<Single wire protocol master transceiver enable       */
29374 
29375 /*******************  Bit definition for SWPMI_BRR register  ********************/
29376 #define SWPMI_BRR_BR             ((uint16_t)0x003F)                            /*!<BR[5:0] bits (Bitrate prescaler) */
29377 
29378 /*******************  Bit definition for SWPMI_ISR register  ********************/
29379 #define SWPMI_ISR_RXBFF          ((uint16_t)0x0001)                            /*!<Receive buffer full flag        */
29380 #define SWPMI_ISR_TXBEF          ((uint16_t)0x0002)                            /*!<Transmit buffer empty flag      */
29381 #define SWPMI_ISR_RXBERF         ((uint16_t)0x0004)                            /*!<Receive CRC error flag          */
29382 #define SWPMI_ISR_RXOVRF         ((uint16_t)0x0008)                            /*!<Receive overrun error flag      */
29383 #define SWPMI_ISR_TXUNRF         ((uint16_t)0x0010)                            /*!<Transmit underrun error flag    */
29384 #define SWPMI_ISR_RXNE           ((uint16_t)0x0020)                            /*!<Receive data register not empty */
29385 #define SWPMI_ISR_TXE            ((uint16_t)0x0040)                            /*!<Transmit data register empty    */
29386 #define SWPMI_ISR_TCF            ((uint16_t)0x0080)                            /*!<Transfer complete flag          */
29387 #define SWPMI_ISR_SRF            ((uint16_t)0x0100)                            /*!<Slave resume flag               */
29388 #define SWPMI_ISR_SUSP           ((uint16_t)0x0200)                            /*!<SUSPEND flag                    */
29389 #define SWPMI_ISR_DEACTF         ((uint16_t)0x0400)                            /*!<DEACTIVATED flag                */
29390 #define SWPMI_ISR_RDYF           ((uint16_t)0x0800)                            /*!<Transceiver ready flag          */
29391 
29392 /*******************  Bit definition for SWPMI_ICR register  ********************/
29393 #define SWPMI_ICR_CRXBFF         ((uint16_t)0x0001)                            /*!<Clear receive buffer full flag       */
29394 #define SWPMI_ICR_CTXBEF         ((uint16_t)0x0002)                            /*!<Clear transmit buffer empty flag     */
29395 #define SWPMI_ICR_CRXBERF        ((uint16_t)0x0004)                            /*!<Clear receive CRC error flag         */
29396 #define SWPMI_ICR_CRXOVRF        ((uint16_t)0x0008)                            /*!<Clear receive overrun error flag     */
29397 #define SWPMI_ICR_CTXUNRF        ((uint16_t)0x0010)                            /*!<Clear transmit underrun error flag   */
29398 #define SWPMI_ICR_CTCF           ((uint16_t)0x0080)                            /*!<Clear transfer complete flag         */
29399 #define SWPMI_ICR_CSRF           ((uint16_t)0x0100)                            /*!<Clear slave resume flag              */
29400 #define SWPMI_ICR_CRDYF          ((uint16_t)0x0800)                            /*!<Clear transceiver ready flag         */
29401 
29402 /*******************  Bit definition for SWPMI_IER register  ********************/
29403 #define SWPMI_IER_RXBFIE         ((uint16_t)0x0001)                            /*!<Receive buffer full interrupt enable        */
29404 #define SWPMI_IER_TXBEIE         ((uint16_t)0x0002)                            /*!<Transmit buffer empty interrupt enable      */
29405 #define SWPMI_IER_RXBERIE        ((uint16_t)0x0004)                            /*!<Receive CRC error interrupt enable          */
29406 #define SWPMI_IER_RXOVRIE        ((uint16_t)0x0008)                            /*!<Receive overrun error interrupt enable      */
29407 #define SWPMI_IER_TXUNRIE        ((uint16_t)0x0010)                            /*!<Transmit underrun error interrupt enable    */
29408 #define SWPMI_IER_RIE            ((uint16_t)0x0020)                            /*!<Receive interrupt enable                    */
29409 #define SWPMI_IER_TIE            ((uint16_t)0x0040)                            /*!<Transmit interrupt enable                   */
29410 #define SWPMI_IER_TCIE           ((uint16_t)0x0080)                            /*!<Transmit complete interrupt enable          */
29411 #define SWPMI_IER_SRIE           ((uint16_t)0x0100)                            /*!<Slave resume interrupt enable               */
29412 #define SWPMI_IER_RDYIE          ((uint16_t)0x0800)                            /*!<Transceiver ready interrupt enable          */
29413 
29414 /*******************  Bit definition for SWPMI_RFL register  ********************/
29415 #define SWPMI_RFL_RFL            ((uint16_t)0x001F)                            /*!<RFL[4:0] bits (Receive Frame length) */
29416 #define SWPMI_RFL_RFL_0_1        ((uint16_t)0x0003)                            /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
29417 
29418 /*******************  Bit definition for SWPMI_TDR register  ********************/
29419 #define SWPMI_TDR_TD_Pos         (0U)
29420 #define SWPMI_TDR_TD_Msk         (0xFFFFFFFFU << SWPMI_TDR_TD_Pos)             /*!< 0xFFFFFFFF */
29421 #define SWPMI_TDR_TD             SWPMI_TDR_TD_Msk                              /*!<Transmit Data Register         */
29422 
29423 /*******************  Bit definition for SWPMI_RDR register  ********************/
29424 #define SWPMI_RDR_RD_Pos         (0U)
29425 #define SWPMI_RDR_RD_Msk         (0xFFFFFFFFU << SWPMI_RDR_RD_Pos)             /*!< 0xFFFFFFFF */
29426 #define SWPMI_RDR_RD             SWPMI_RDR_RD_Msk                              /*!<Recive Data Register           */
29427 
29428 
29429 /*******************  Bit definition for SWPMI_OR register  ********************/
29430 #define SWPMI_OR_TBYP            ((uint16_t)0x0001)                            /*!<SWP Transceiver Bypass */
29431 #define SWPMI_OR_CLASS           ((uint16_t)0x0002)                            /*!<SWP CLASS selection */
29432 
29433 /******************************************************************************/
29434 /*                                                                            */
29435 /*                            Window WATCHDOG                                 */
29436 /*                                                                            */
29437 /******************************************************************************/
29438 /*******************  Bit definition for WWDG_CR register  ********************/
29439 #define WWDG_CR_T_Pos           (0U)
29440 #define WWDG_CR_T_Msk           (0x7FU << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
29441 #define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
29442 #define WWDG_CR_T_0             (0x01U << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
29443 #define WWDG_CR_T_1             (0x02U << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
29444 #define WWDG_CR_T_2             (0x04U << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
29445 #define WWDG_CR_T_3             (0x08U << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
29446 #define WWDG_CR_T_4             (0x10U << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
29447 #define WWDG_CR_T_5             (0x20U << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
29448 #define WWDG_CR_T_6             (0x40U << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
29449 
29450 #define WWDG_CR_WDGA_Pos        (7U)
29451 #define WWDG_CR_WDGA_Msk        (0x1U << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
29452 #define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
29453 
29454 /*******************  Bit definition for WWDG_CFR register  *******************/
29455 #define WWDG_CFR_W_Pos          (0U)
29456 #define WWDG_CFR_W_Msk          (0x7FU << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
29457 #define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */
29458 #define WWDG_CFR_W_0            (0x01U << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
29459 #define WWDG_CFR_W_1            (0x02U << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
29460 #define WWDG_CFR_W_2            (0x04U << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
29461 #define WWDG_CFR_W_3            (0x08U << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
29462 #define WWDG_CFR_W_4            (0x10U << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
29463 #define WWDG_CFR_W_5            (0x20U << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
29464 #define WWDG_CFR_W_6            (0x40U << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
29465 
29466 #define WWDG_CFR_WDGTB_Pos      (11U)
29467 #define WWDG_CFR_WDGTB_Msk      (0x7U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00003800 */
29468 #define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[2:0] bits (Timer Base) */
29469 #define WWDG_CFR_WDGTB_0        (0x1U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000800 */
29470 #define WWDG_CFR_WDGTB_1        (0x2U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00001000 */
29471 #define WWDG_CFR_WDGTB_2        (0x4U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00002000 */
29472 
29473 #define WWDG_CFR_EWI_Pos        (9U)
29474 #define WWDG_CFR_EWI_Msk        (0x1U << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
29475 #define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
29476 
29477 /*******************  Bit definition for WWDG_SR register  ********************/
29478 #define WWDG_SR_EWIF_Pos        (0U)
29479 #define WWDG_SR_EWIF_Msk        (0x1U << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
29480 #define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
29481 
29482 /*******************  Bit definition for WWDG_HWCFGR register  ***************/
29483 #define WWDG_HWCFGR_PREDIV_Pos  (0U)
29484 #define WWDG_HWCFGR_PREDIV_Msk  (0xFFFFU << WWDG_HWCFGR_PREDIV_Pos)            /*!< 0x0000FFFF */
29485 #define WWDG_HWCFGR_PREDIV      WWDG_HWCFGR_PREDIV_Msk                         /*!< Watchdog clock prescaler */
29486 
29487 /*******************  Bit definition for WWDG_VERR register  *****************/
29488 #define WWDG_VERR_MINREV_Pos      (0U)
29489 #define WWDG_VERR_MINREV_Msk      (0xFU << WWDG_VERR_MINREV_Pos)               /*!< 0x0000000F */
29490 #define WWDG_VERR_MINREV          WWDG_VERR_MINREV_Msk                         /*!< Minor Revision number */
29491 #define WWDG_VERR_MAJREV_Pos      (4U)
29492 #define WWDG_VERR_MAJREV_Msk      (0xFU << WWDG_VERR_MAJREV_Pos)               /*!< 0x000000F0 */
29493 #define WWDG_VERR_MAJREV          WWDG_VERR_MAJREV_Msk                         /*!< Major Revision number */
29494 
29495 /*******************  Bit definition for WWDG_IPIDR register  ****************/
29496 #define WWDG_IPIDR_ID_Pos       (0U)
29497 #define WWDG_IPIDR_ID_Msk       (0xFFFFFFFFU << WWDG_IPIDR_ID_Pos)             /*!< 0xFFFFFFFF */
29498 #define WWDG_IPIDR_ID           WWDG_IPIDR_ID_Msk                              /*!< IP Identification */
29499 
29500 /**********************  Bit definition for WWDG_SIDR register  *****************/
29501 #define WWDG_SIDR_SID_Pos         (0U)
29502 #define WWDG_SIDR_SID_Msk         (0xFFFFFFFFU << WWDG_SIDR_SID_Pos)           /*!< 0xFFFFFFFF */
29503 #define WWDG_SIDR_SID             WWDG_SIDR_SID_Msk                            /*!< IP size identification */
29504 
29505 /******************************************************************************/
29506 /*                                                                            */
29507 /*                                MDIOS                                        */
29508 /*                                                                            */
29509 /******************************************************************************/
29510 /********************  Bit definition for MDIOS_CR register  *******************/
29511 #define MDIOS_CR_EN_Pos                (0U)
29512 #define MDIOS_CR_EN_Msk                (0x1U << MDIOS_CR_EN_Pos)               /*!< 0x00000001 */
29513 #define MDIOS_CR_EN                    MDIOS_CR_EN_Msk                         /*!<  MDIOS slave peripheral enable */
29514 #define MDIOS_CR_WRIE_Pos              (1U)
29515 #define MDIOS_CR_WRIE_Msk              (0x1U << MDIOS_CR_WRIE_Pos)             /*!< 0x00000002 */
29516 #define MDIOS_CR_WRIE                  MDIOS_CR_WRIE_Msk                       /*!<  MDIOS slave register write interrupt enable. */
29517 #define MDIOS_CR_RDIE_Pos              (2U)
29518 #define MDIOS_CR_RDIE_Msk              (0x1U << MDIOS_CR_RDIE_Pos)             /*!< 0x00000004 */
29519 #define MDIOS_CR_RDIE                  MDIOS_CR_RDIE_Msk                       /*!<  MDIOS slave register read interrupt enable. */
29520 #define MDIOS_CR_EIE_Pos               (3U)
29521 #define MDIOS_CR_EIE_Msk               (0x1U << MDIOS_CR_EIE_Pos)              /*!< 0x00000008 */
29522 #define MDIOS_CR_EIE                   MDIOS_CR_EIE_Msk                        /*!<  MDIOS slave register error interrupt enable. */
29523 #define MDIOS_CR_DPC_Pos               (7U)
29524 #define MDIOS_CR_DPC_Msk               (0x1U << MDIOS_CR_DPC_Pos)              /*!< 0x00000080 */
29525 #define MDIOS_CR_DPC                   MDIOS_CR_DPC_Msk                        /*!<  MDIOS slave disable preamble check. */
29526 #define MDIOS_CR_PORT_ADDRESS_Pos      (8U)
29527 #define MDIOS_CR_PORT_ADDRESS_Msk      (0x1FU << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00001F00 */
29528 #define MDIOS_CR_PORT_ADDRESS          MDIOS_CR_PORT_ADDRESS_Msk               /*!<  MDIOS slave port address mask. */
29529 #define MDIOS_CR_PORT_ADDRESS_0        (0x01U << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000100 */
29530 #define MDIOS_CR_PORT_ADDRESS_1        (0x02U << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000200 */
29531 #define MDIOS_CR_PORT_ADDRESS_2        (0x04U << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000400 */
29532 #define MDIOS_CR_PORT_ADDRESS_3        (0x08U << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000800 */
29533 #define MDIOS_CR_PORT_ADDRESS_4        (0x10U << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00001000 */
29534 
29535 /********************  Bit definition for MDIOS_SR register  *******************/
29536 #define MDIOS_SR_PERF_Pos              (0U)
29537 #define MDIOS_SR_PERF_Msk              (0x1U << MDIOS_SR_PERF_Pos)             /*!< 0x00000001 */
29538 #define MDIOS_SR_PERF                  MDIOS_SR_PERF_Msk                       /*!<  MDIOS slave turnaround error flag*/
29539 #define MDIOS_SR_SERF_Pos              (1U)
29540 #define MDIOS_SR_SERF_Msk              (0x1U << MDIOS_SR_SERF_Pos)             /*!< 0x00000002 */
29541 #define MDIOS_SR_SERF                  MDIOS_SR_SERF_Msk                       /*!<  MDIOS slave start error flag */
29542 #define MDIOS_SR_TERF_Pos              (2U)
29543 #define MDIOS_SR_TERF_Msk              (0x1U << MDIOS_SR_TERF_Pos)             /*!< 0x00000004 */
29544 #define MDIOS_SR_TERF                  MDIOS_SR_TERF_Msk                       /*!<  MDIOS slave preamble error flag */
29545 
29546 /********************  Bit definition for MDIOS_CLRFR register  *******************/
29547 #define MDIOS_SR_CPERF_Pos             (0U)
29548 #define MDIOS_SR_CPERF_Msk             (0x1U << MDIOS_SR_CPERF_Pos)            /*!< 0x00000001 */
29549 #define MDIOS_SR_CPERF                 MDIOS_SR_CPERF_Msk                      /*!<  MDIOS slave Clear the turnaround error flag */
29550 #define MDIOS_SR_CSERF_Pos             (1U)
29551 #define MDIOS_SR_CSERF_Msk             (0x1U << MDIOS_SR_CSERF_Pos)            /*!< 0x00000002 */
29552 #define MDIOS_SR_CSERF                 MDIOS_SR_CSERF_Msk                      /*!<  MDIOS slave Clear the start error flag */
29553 #define MDIOS_SR_CTERF_Pos             (2U)
29554 #define MDIOS_SR_CTERF_Msk             (0x1U << MDIOS_SR_CTERF_Pos)            /*!< 0x00000004 */
29555 #define MDIOS_SR_CTERF                 MDIOS_SR_CTERF_Msk                      /*!<  MDIOS slave Clear the preamble error flag */
29556 
29557 /**********************  Bit definition for MDIOS_HWCFGR register  ***************/
29558 #define MDIOS_HWCFGR_NBREG_Pos  (0U)
29559 #define MDIOS_HWCFGR_NBREG_Msk  (0xFFU << MDIOS_HWCFGR_NBREG_Pos)                /*!< 0x000000FF */
29560 #define MDIOS_HWCFGR_NBREG      MDIOS_HWCFGR_NBREG_Msk                           /*!< IP configuration number of registers */
29561 
29562 /**********************  Bit definition for MDIOS_VERR register  *****************/
29563 #define MDIOS_VERR_MINREV_Pos      (0U)
29564 #define MDIOS_VERR_MINREV_Msk      (0xFU << MDIOS_VERR_MINREV_Pos)               /*!< 0x0000000F */
29565 #define MDIOS_VERR_MINREV          MDIOS_VERR_MINREV_Msk                         /*!< Minor Revision number */
29566 #define MDIOS_VERR_MAJREV_Pos      (4U)
29567 #define MDIOS_VERR_MAJREV_Msk      (0xFU << MDIOS_VERR_MAJREV_Pos)               /*!< 0x000000F0 */
29568 #define MDIOS_VERR_MAJREV          MDIOS_VERR_MAJREV_Msk                         /*!< Major Revision number */
29569 
29570 /**********************  Bit definition for MDIOS_IPIDR register  ****************/
29571 #define MDIOS_IPIDR_IPID_Pos       (0U)
29572 #define MDIOS_IPIDR_IPID_Msk       (0xFFFFFFFFU << MDIOS_IPIDR_IPID_Pos)         /*!< 0xFFFFFFFF */
29573 #define MDIOS_IPIDR_IPID           MDIOS_IPIDR_IPID_Msk                          /*!< IP Identification */
29574 
29575 /**********************  Bit definition for MDIOS_SIDR register  *****************/
29576 #define MDIOS_SIDR_SID_Pos         (0U)
29577 #define MDIOS_SIDR_SID_Msk         (0xFFFFFFFFU << MDIOS_SIDR_SID_Pos)           /*!< 0xFFFFFFFF */
29578 #define MDIOS_SIDR_SID             MDIOS_SIDR_SID_Msk                            /*!< IP size identification */
29579 
29580 /******************************************************************************/
29581 /*                                                                            */
29582 /*                                       USB_OTG                              */
29583 /*                                                                            */
29584 /******************************************************************************/
29585 /********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/
29586 #define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)
29587 #define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
29588 #define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */
29589 #define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)
29590 #define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
29591 #define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */
29592 #define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)
29593 #define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1U << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
29594 #define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */
29595 #define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)
29596 #define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1U << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
29597 #define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
29598 #define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)
29599 #define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1U << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
29600 #define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */
29601 #define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)
29602 #define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1U << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
29603 #define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */
29604 #define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)
29605 #define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1U << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
29606 #define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */
29607 #define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)
29608 #define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
29609 #define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */
29610 #define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)
29611 #define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
29612 #define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */
29613 #define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)
29614 #define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
29615 #define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */
29616 #define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)
29617 #define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
29618 #define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */
29619 #define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)
29620 #define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
29621 #define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */
29622 #define USB_OTG_GOTGCTL_EHEN_Pos                 (12U)
29623 #define USB_OTG_GOTGCTL_EHEN_Msk                 (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
29624 #define USB_OTG_GOTGCTL_EHEN                     USB_OTG_GOTGCTL_EHEN_Msk      /*!< Embedded host enable */
29625 #define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)
29626 #define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
29627 #define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */
29628 #define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)
29629 #define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
29630 #define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */
29631 #define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)
29632 #define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
29633 #define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */
29634 #define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)
29635 #define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
29636 #define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!< B-session valid */
29637 #define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)
29638 #define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
29639 #define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */
29640 
29641 /********************  Bit definition forUSB_OTG_HCFG register  ********************/
29642 
29643 #define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)
29644 #define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
29645 #define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */
29646 #define USB_OTG_HCFG_FSLSPCS_0                   (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
29647 #define USB_OTG_HCFG_FSLSPCS_1                   (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
29648 #define USB_OTG_HCFG_FSLSS_Pos                   (2U)
29649 #define USB_OTG_HCFG_FSLSS_Msk                   (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
29650 #define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */
29651 
29652 /********************  Bit definition forUSB_OTG_DCFG register  ********************/
29653 
29654 #define USB_OTG_DCFG_DSPD_Pos                    (0U)
29655 #define USB_OTG_DCFG_DSPD_Msk                    (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
29656 #define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */
29657 #define USB_OTG_DCFG_DSPD_0                      (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
29658 #define USB_OTG_DCFG_DSPD_1                      (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
29659 #define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)
29660 #define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
29661 #define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */
29662 
29663 #define USB_OTG_DCFG_DAD_Pos                     (4U)
29664 #define USB_OTG_DCFG_DAD_Msk                     (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
29665 #define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */
29666 #define USB_OTG_DCFG_DAD_0                       (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
29667 #define USB_OTG_DCFG_DAD_1                       (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
29668 #define USB_OTG_DCFG_DAD_2                       (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
29669 #define USB_OTG_DCFG_DAD_3                       (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
29670 #define USB_OTG_DCFG_DAD_4                       (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
29671 #define USB_OTG_DCFG_DAD_5                       (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
29672 #define USB_OTG_DCFG_DAD_6                       (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
29673 
29674 #define USB_OTG_DCFG_PFIVL_Pos                   (11U)
29675 #define USB_OTG_DCFG_PFIVL_Msk                   (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
29676 #define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */
29677 #define USB_OTG_DCFG_PFIVL_0                     (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
29678 #define USB_OTG_DCFG_PFIVL_1                     (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
29679 
29680 #define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)
29681 #define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
29682 #define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */
29683 #define USB_OTG_DCFG_PERSCHIVL_0                 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
29684 #define USB_OTG_DCFG_PERSCHIVL_1                 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
29685 
29686 /********************  Bit definition forUSB_OTG_PCGCR register  ********************/
29687 #define USB_OTG_PCGCR_STPPCLK_Pos                (0U)
29688 #define USB_OTG_PCGCR_STPPCLK_Msk                (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
29689 #define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */
29690 #define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)
29691 #define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
29692 #define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */
29693 #define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)
29694 #define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
29695 #define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */
29696 
29697 /********************  Bit definition forUSB_OTG_GOTGINT register  ********************/
29698 #define USB_OTG_GOTGINT_SEDET_Pos                (2U)
29699 #define USB_OTG_GOTGINT_SEDET_Msk                (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
29700 #define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */
29701 #define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)
29702 #define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
29703 #define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */
29704 #define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)
29705 #define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
29706 #define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */
29707 #define USB_OTG_GOTGINT_HNGDET_Pos               (17U)
29708 #define USB_OTG_GOTGINT_HNGDET_Msk               (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
29709 #define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */
29710 #define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)
29711 #define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
29712 #define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */
29713 #define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)
29714 #define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
29715 #define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */
29716 
29717 /********************  Bit definition forUSB_OTG_DCTL register  ********************/
29718 #define USB_OTG_DCTL_RWUSIG_Pos                  (0U)
29719 #define USB_OTG_DCTL_RWUSIG_Msk                  (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
29720 #define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */
29721 #define USB_OTG_DCTL_SDIS_Pos                    (1U)
29722 #define USB_OTG_DCTL_SDIS_Msk                    (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
29723 #define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */
29724 #define USB_OTG_DCTL_GINSTS_Pos                  (2U)
29725 #define USB_OTG_DCTL_GINSTS_Msk                  (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
29726 #define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */
29727 #define USB_OTG_DCTL_GONSTS_Pos                  (3U)
29728 #define USB_OTG_DCTL_GONSTS_Msk                  (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
29729 #define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */
29730 
29731 #define USB_OTG_DCTL_TCTL_Pos                    (4U)
29732 #define USB_OTG_DCTL_TCTL_Msk                    (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
29733 #define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */
29734 #define USB_OTG_DCTL_TCTL_0                      (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
29735 #define USB_OTG_DCTL_TCTL_1                      (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
29736 #define USB_OTG_DCTL_TCTL_2                      (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
29737 #define USB_OTG_DCTL_SGINAK_Pos                  (7U)
29738 #define USB_OTG_DCTL_SGINAK_Msk                  (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
29739 #define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */
29740 #define USB_OTG_DCTL_CGINAK_Pos                  (8U)
29741 #define USB_OTG_DCTL_CGINAK_Msk                  (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
29742 #define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */
29743 #define USB_OTG_DCTL_SGONAK_Pos                  (9U)
29744 #define USB_OTG_DCTL_SGONAK_Msk                  (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
29745 #define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */
29746 #define USB_OTG_DCTL_CGONAK_Pos                  (10U)
29747 #define USB_OTG_DCTL_CGONAK_Msk                  (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
29748 #define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */
29749 #define USB_OTG_DCTL_POPRGDNE_Pos                (11U)
29750 #define USB_OTG_DCTL_POPRGDNE_Msk                (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
29751 #define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
29752 
29753 /********************  Bit definition forUSB_OTG_HFIR register  ********************/
29754 #define USB_OTG_HFIR_FRIVL_Pos                   (0U)
29755 #define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
29756 #define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */
29757 
29758 /********************  Bit definition forUSB_OTG_HFNUM register  ********************/
29759 #define USB_OTG_HFNUM_FRNUM_Pos                  (0U)
29760 #define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
29761 #define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */
29762 #define USB_OTG_HFNUM_FTREM_Pos                  (16U)
29763 #define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
29764 #define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */
29765 
29766 /********************  Bit definition forUSB_OTG_DSTS register  ********************/
29767 #define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)
29768 #define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
29769 #define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */
29770 
29771 #define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)
29772 #define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
29773 #define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */
29774 #define USB_OTG_DSTS_ENUMSPD_0                   (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
29775 #define USB_OTG_DSTS_ENUMSPD_1                   (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
29776 #define USB_OTG_DSTS_EERR_Pos                    (3U)
29777 #define USB_OTG_DSTS_EERR_Msk                    (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
29778 #define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */
29779 #define USB_OTG_DSTS_FNSOF_Pos                   (8U)
29780 #define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
29781 #define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */
29782 
29783 /********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/
29784 #define USB_OTG_GAHBCFG_GINT_Pos                 (0U)
29785 #define USB_OTG_GAHBCFG_GINT_Msk                 (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
29786 #define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */
29787 
29788 #define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)
29789 #define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
29790 #define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */
29791 #define USB_OTG_GAHBCFG_HBSTLEN_0                (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000002 */
29792 #define USB_OTG_GAHBCFG_HBSTLEN_1                (0x2U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000004 */
29793 #define USB_OTG_GAHBCFG_HBSTLEN_2                (0x4U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000008 */
29794 #define USB_OTG_GAHBCFG_HBSTLEN_3                (0x8U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000010 */
29795 #define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)
29796 #define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
29797 #define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */
29798 #define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)
29799 #define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
29800 #define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */
29801 #define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)
29802 #define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
29803 #define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */
29804 
29805 /********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/
29806 
29807 #define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)
29808 #define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
29809 #define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */
29810 #define USB_OTG_GUSBCFG_TOCAL_0                  (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
29811 #define USB_OTG_GUSBCFG_TOCAL_1                  (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
29812 #define USB_OTG_GUSBCFG_TOCAL_2                  (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
29813 #define USB_OTG_GUSBCFG_PHYIF_Pos                (3U)
29814 #define USB_OTG_GUSBCFG_PHYIF_Msk                (0x1U << USB_OTG_GUSBCFG_PHYIF_Pos) /*!< 0x00000008 */
29815 #define USB_OTG_GUSBCFG_PHYIF                    USB_OTG_GUSBCFG_PHYIF_Msk     /*!< PHY Interface (PHYIf) */
29816 #define USB_OTG_GUSBCFG_ULPI_UTMI_SEL_Pos        (4U)
29817 #define USB_OTG_GUSBCFG_ULPI_UTMI_SEL_Msk        (0x1U << USB_OTG_GUSBCFG_ULPI_UTMI_SEL_Pos) /*!< 0x00000010 */
29818 #define USB_OTG_GUSBCFG_ULPI_UTMI_SEL            USB_OTG_GUSBCFG_ULPI_UTMI_SEL_Msk /*!< ULPI or UTMI+ Select (ULPI_UTMI_Sel) */
29819 #define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)
29820 #define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
29821 #define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
29822 #define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)
29823 #define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
29824 #define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */
29825 #define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)
29826 #define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
29827 #define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */
29828 
29829 #define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)
29830 #define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
29831 #define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */
29832 #define USB_OTG_GUSBCFG_TRDT_0                   (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
29833 #define USB_OTG_GUSBCFG_TRDT_1                   (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
29834 #define USB_OTG_GUSBCFG_TRDT_2                   (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
29835 #define USB_OTG_GUSBCFG_TRDT_3                   (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
29836 #define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)
29837 #define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
29838 #define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */
29839 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)
29840 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
29841 #define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */
29842 #define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)
29843 #define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
29844 #define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */
29845 #define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)
29846 #define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
29847 #define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */
29848 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)
29849 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
29850 #define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */
29851 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)
29852 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
29853 #define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */
29854 #define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)
29855 #define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
29856 #define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */
29857 #define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)
29858 #define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
29859 #define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */
29860 #define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)
29861 #define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
29862 #define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */
29863 #define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)
29864 #define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
29865 #define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */
29866 #define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)
29867 #define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
29868 #define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */
29869 #define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)
29870 #define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
29871 #define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */
29872 #define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)
29873 #define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
29874 #define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */
29875 
29876 /********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
29877 #define USB_OTG_GRSTCTL_CSRST_Pos                (0U)
29878 #define USB_OTG_GRSTCTL_CSRST_Msk                (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
29879 #define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */
29880 #define USB_OTG_GRSTCTL_HSRST_Pos                (1U)
29881 #define USB_OTG_GRSTCTL_HSRST_Msk                (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
29882 #define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */
29883 #define USB_OTG_GRSTCTL_FCRST_Pos                (2U)
29884 #define USB_OTG_GRSTCTL_FCRST_Msk                (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
29885 #define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */
29886 #define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)
29887 #define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
29888 #define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */
29889 #define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)
29890 #define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
29891 #define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */
29892 
29893 #define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)
29894 #define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
29895 #define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */
29896 #define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
29897 #define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
29898 #define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
29899 #define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
29900 #define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
29901 #define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)
29902 #define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
29903 #define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */
29904 #define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)
29905 #define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
29906 #define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */
29907 
29908 /********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/
29909 #define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)
29910 #define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
29911 #define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */
29912 #define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)
29913 #define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
29914 #define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */
29915 #define USB_OTG_DIEPMSK_TOM_Pos                  (3U)
29916 #define USB_OTG_DIEPMSK_TOM_Msk                  (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
29917 #define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */
29918 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)
29919 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
29920 #define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
29921 #define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)
29922 #define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
29923 #define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */
29924 #define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)
29925 #define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
29926 #define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */
29927 #define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)
29928 #define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
29929 #define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */
29930 #define USB_OTG_DIEPMSK_BIM_Pos                  (9U)
29931 #define USB_OTG_DIEPMSK_BIM_Msk                  (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
29932 #define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */
29933 
29934 /********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/
29935 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)
29936 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
29937 #define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */
29938 
29939 #define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)
29940 #define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
29941 #define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */
29942 #define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
29943 #define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
29944 #define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
29945 #define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
29946 #define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
29947 #define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
29948 #define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
29949 #define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
29950 
29951 #define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)
29952 #define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
29953 #define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */
29954 #define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
29955 #define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
29956 #define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
29957 #define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
29958 #define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
29959 #define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
29960 #define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
29961 #define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
29962 
29963 /********************  Bit definition forUSB_OTG_HAINT register  ********************/
29964 #define USB_OTG_HAINT_HAINT_Pos                  (0U)
29965 #define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
29966 #define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */
29967 
29968 /********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/
29969 #define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)
29970 #define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
29971 #define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */
29972 #define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)
29973 #define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
29974 #define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */
29975 #define USB_OTG_DOEPMSK_STUPM_Pos                (3U)
29976 #define USB_OTG_DOEPMSK_STUPM_Msk                (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
29977 #define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */
29978 #define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)
29979 #define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
29980 #define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */
29981 #define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)
29982 #define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
29983 #define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */
29984 #define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)
29985 #define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
29986 #define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */
29987 #define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)
29988 #define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
29989 #define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */
29990 
29991 /********************  Bit definition forUSB_OTG_GINTSTS register  ********************/
29992 #define USB_OTG_GINTSTS_CMOD_Pos                 (0U)
29993 #define USB_OTG_GINTSTS_CMOD_Msk                 (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
29994 #define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */
29995 #define USB_OTG_GINTSTS_MMIS_Pos                 (1U)
29996 #define USB_OTG_GINTSTS_MMIS_Msk                 (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
29997 #define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */
29998 #define USB_OTG_GINTSTS_OTGINT_Pos               (2U)
29999 #define USB_OTG_GINTSTS_OTGINT_Msk               (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
30000 #define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */
30001 #define USB_OTG_GINTSTS_SOF_Pos                  (3U)
30002 #define USB_OTG_GINTSTS_SOF_Msk                  (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
30003 #define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */
30004 #define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)
30005 #define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
30006 #define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */
30007 #define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)
30008 #define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
30009 #define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */
30010 #define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)
30011 #define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
30012 #define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */
30013 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)
30014 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
30015 #define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */
30016 #define USB_OTG_GINTSTS_ESUSP_Pos                (10U)
30017 #define USB_OTG_GINTSTS_ESUSP_Msk                (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
30018 #define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */
30019 #define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)
30020 #define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
30021 #define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */
30022 #define USB_OTG_GINTSTS_USBRST_Pos               (12U)
30023 #define USB_OTG_GINTSTS_USBRST_Msk               (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
30024 #define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */
30025 #define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)
30026 #define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
30027 #define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */
30028 #define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)
30029 #define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
30030 #define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */
30031 #define USB_OTG_GINTSTS_EOPF_Pos                 (15U)
30032 #define USB_OTG_GINTSTS_EOPF_Msk                 (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
30033 #define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */
30034 #define USB_OTG_GINTSTS_IEPINT_Pos               (18U)
30035 #define USB_OTG_GINTSTS_IEPINT_Msk               (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
30036 #define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */
30037 #define USB_OTG_GINTSTS_OEPINT_Pos               (19U)
30038 #define USB_OTG_GINTSTS_OEPINT_Msk               (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
30039 #define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */
30040 #define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)
30041 #define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
30042 #define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */
30043 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)
30044 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
30045 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */
30046 #define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)
30047 #define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
30048 #define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */
30049 #define USB_OTG_GINTSTS_RSTDET_Pos               (23U)
30050 #define USB_OTG_GINTSTS_RSTDET_Msk               (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
30051 #define USB_OTG_GINTSTS_RSTDET                   USB_OTG_GINTSTS_RSTDET_Msk    /*!< Reset detected interrupt                       */
30052 #define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)
30053 #define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
30054 #define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */
30055 #define USB_OTG_GINTSTS_HCINT_Pos                (25U)
30056 #define USB_OTG_GINTSTS_HCINT_Msk                (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
30057 #define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */
30058 #define USB_OTG_GINTSTS_PTXFE_Pos                (26U)
30059 #define USB_OTG_GINTSTS_PTXFE_Msk                (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
30060 #define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */
30061 #define USB_OTG_GINTSTS_LPMINT_Pos               (27U)
30062 #define USB_OTG_GINTSTS_LPMINT_Msk               (0x1U << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
30063 #define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt                                  */
30064 #define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)
30065 #define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
30066 #define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */
30067 #define USB_OTG_GINTSTS_DISCINT_Pos              (29U)
30068 #define USB_OTG_GINTSTS_DISCINT_Msk              (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
30069 #define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */
30070 #define USB_OTG_GINTSTS_SRQINT_Pos               (30U)
30071 #define USB_OTG_GINTSTS_SRQINT_Msk               (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
30072 #define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */
30073 #define USB_OTG_GINTSTS_WKUINT_Pos               (31U)
30074 #define USB_OTG_GINTSTS_WKUINT_Msk               (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
30075 #define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */
30076 
30077 /********************  Bit definition forUSB_OTG_GINTMSK register  ********************/
30078 #define USB_OTG_GINTMSK_MMISM_Pos                (1U)
30079 #define USB_OTG_GINTMSK_MMISM_Msk                (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
30080 #define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */
30081 #define USB_OTG_GINTMSK_OTGINT_Pos               (2U)
30082 #define USB_OTG_GINTMSK_OTGINT_Msk               (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
30083 #define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */
30084 #define USB_OTG_GINTMSK_SOFM_Pos                 (3U)
30085 #define USB_OTG_GINTMSK_SOFM_Msk                 (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
30086 #define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */
30087 #define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)
30088 #define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
30089 #define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */
30090 #define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)
30091 #define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
30092 #define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */
30093 #define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)
30094 #define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
30095 #define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */
30096 #define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)
30097 #define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
30098 #define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */
30099 #define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)
30100 #define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
30101 #define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */
30102 #define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)
30103 #define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
30104 #define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */
30105 #define USB_OTG_GINTMSK_USBRST_Pos               (12U)
30106 #define USB_OTG_GINTMSK_USBRST_Msk               (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
30107 #define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */
30108 #define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)
30109 #define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
30110 #define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */
30111 #define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)
30112 #define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
30113 #define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */
30114 #define USB_OTG_GINTMSK_EOPFM_Pos                (15U)
30115 #define USB_OTG_GINTMSK_EOPFM_Msk                (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
30116 #define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */
30117 #define USB_OTG_GINTMSK_EPMISM_Pos               (17U)
30118 #define USB_OTG_GINTMSK_EPMISM_Msk               (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
30119 #define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */
30120 #define USB_OTG_GINTMSK_IEPINT_Pos               (18U)
30121 #define USB_OTG_GINTMSK_IEPINT_Msk               (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
30122 #define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */
30123 #define USB_OTG_GINTMSK_OEPINT_Pos               (19U)
30124 #define USB_OTG_GINTMSK_OEPINT_Msk               (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
30125 #define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */
30126 #define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)
30127 #define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
30128 #define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */
30129 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)
30130 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
30131 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */
30132 #define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)
30133 #define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
30134 #define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */
30135 #define USB_OTG_GINTMSK_RSTDEM_Pos               (23U)
30136 #define USB_OTG_GINTMSK_RSTDEM_Msk               (0x1U << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */
30137 #define USB_OTG_GINTMSK_RSTDEM                   USB_OTG_GINTMSK_RSTDEM_Msk    /*!< Reset detected interrupt mask                      */
30138 #define USB_OTG_GINTMSK_PRTIM_Pos                (24U)
30139 #define USB_OTG_GINTMSK_PRTIM_Msk                (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
30140 #define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */
30141 #define USB_OTG_GINTMSK_HCIM_Pos                 (25U)
30142 #define USB_OTG_GINTMSK_HCIM_Msk                 (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
30143 #define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */
30144 #define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)
30145 #define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
30146 #define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */
30147 #define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)
30148 #define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1U << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
30149 #define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask                                  */
30150 #define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)
30151 #define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
30152 #define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */
30153 #define USB_OTG_GINTMSK_DISCINT_Pos              (29U)
30154 #define USB_OTG_GINTMSK_DISCINT_Msk              (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
30155 #define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */
30156 #define USB_OTG_GINTMSK_SRQIM_Pos                (30U)
30157 #define USB_OTG_GINTMSK_SRQIM_Msk                (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
30158 #define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */
30159 #define USB_OTG_GINTMSK_WUIM_Pos                 (31U)
30160 #define USB_OTG_GINTMSK_WUIM_Msk                 (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
30161 #define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */
30162 
30163 /********************  Bit definition forUSB_OTG_DAINT register  ********************/
30164 #define USB_OTG_DAINT_IEPINT_Pos                 (0U)
30165 #define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
30166 #define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */
30167 #define USB_OTG_DAINT_OEPINT_Pos                 (16U)
30168 #define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
30169 #define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */
30170 
30171 /********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/
30172 #define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)
30173 #define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
30174 #define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */
30175 
30176 /********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
30177 #define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)
30178 #define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
30179 #define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */
30180 #define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)
30181 #define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
30182 #define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */
30183 #define USB_OTG_GRXSTSP_DPID_Pos                 (15U)
30184 #define USB_OTG_GRXSTSP_DPID_Msk                 (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
30185 #define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */
30186 #define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)
30187 #define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
30188 #define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */
30189 
30190 /********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/
30191 #define USB_OTG_DAINTMSK_IEPM_Pos                (0U)
30192 #define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
30193 #define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */
30194 #define USB_OTG_DAINTMSK_OEPM_Pos                (16U)
30195 #define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
30196 #define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */
30197 
30198 /********************  Bit definition for OTG register  ********************/
30199 
30200 #define USB_OTG_CHNUM_Pos                        (0U)
30201 #define USB_OTG_CHNUM_Msk                        (0xFU << USB_OTG_CHNUM_Pos)   /*!< 0x0000000F */
30202 #define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */
30203 #define USB_OTG_CHNUM_0                          (0x1U << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */
30204 #define USB_OTG_CHNUM_1                          (0x2U << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */
30205 #define USB_OTG_CHNUM_2                          (0x4U << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */
30206 #define USB_OTG_CHNUM_3                          (0x8U << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */
30207 #define USB_OTG_BCNT_Pos                         (4U)
30208 #define USB_OTG_BCNT_Msk                         (0x7FFU << USB_OTG_BCNT_Pos)  /*!< 0x00007FF0 */
30209 #define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */
30210 
30211 #define USB_OTG_DPID_Pos                         (15U)
30212 #define USB_OTG_DPID_Msk                         (0x3U << USB_OTG_DPID_Pos)    /*!< 0x00018000 */
30213 #define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */
30214 #define USB_OTG_DPID_0                           (0x1U << USB_OTG_DPID_Pos)    /*!< 0x00008000 */
30215 #define USB_OTG_DPID_1                           (0x2U << USB_OTG_DPID_Pos)    /*!< 0x00010000 */
30216 
30217 #define USB_OTG_PKTSTS_Pos                       (17U)
30218 #define USB_OTG_PKTSTS_Msk                       (0xFU << USB_OTG_PKTSTS_Pos)  /*!< 0x001E0000 */
30219 #define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */
30220 #define USB_OTG_PKTSTS_0                         (0x1U << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */
30221 #define USB_OTG_PKTSTS_1                         (0x2U << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */
30222 #define USB_OTG_PKTSTS_2                         (0x4U << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */
30223 #define USB_OTG_PKTSTS_3                         (0x8U << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */
30224 
30225 #define USB_OTG_EPNUM_Pos                        (0U)
30226 #define USB_OTG_EPNUM_Msk                        (0xFU << USB_OTG_EPNUM_Pos)   /*!< 0x0000000F */
30227 #define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */
30228 #define USB_OTG_EPNUM_0                          (0x1U << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */
30229 #define USB_OTG_EPNUM_1                          (0x2U << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */
30230 #define USB_OTG_EPNUM_2                          (0x4U << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */
30231 #define USB_OTG_EPNUM_3                          (0x8U << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */
30232 
30233 #define USB_OTG_FRMNUM_Pos                       (21U)
30234 #define USB_OTG_FRMNUM_Msk                       (0xFU << USB_OTG_FRMNUM_Pos)  /*!< 0x01E00000 */
30235 #define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */
30236 #define USB_OTG_FRMNUM_0                         (0x1U << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */
30237 #define USB_OTG_FRMNUM_1                         (0x2U << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */
30238 #define USB_OTG_FRMNUM_2                         (0x4U << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */
30239 #define USB_OTG_FRMNUM_3                         (0x8U << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */
30240 
30241 /********************  Bit definition for OTG register  ********************/
30242 
30243 #define USB_OTG_CHNUM_Pos                        (0U)
30244 #define USB_OTG_CHNUM_Msk                        (0xFU << USB_OTG_CHNUM_Pos)   /*!< 0x0000000F */
30245 #define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */
30246 #define USB_OTG_CHNUM_0                          (0x1U << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */
30247 #define USB_OTG_CHNUM_1                          (0x2U << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */
30248 #define USB_OTG_CHNUM_2                          (0x4U << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */
30249 #define USB_OTG_CHNUM_3                          (0x8U << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */
30250 #define USB_OTG_BCNT_Pos                         (4U)
30251 #define USB_OTG_BCNT_Msk                         (0x7FFU << USB_OTG_BCNT_Pos)  /*!< 0x00007FF0 */
30252 #define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */
30253 
30254 #define USB_OTG_DPID_Pos                         (15U)
30255 #define USB_OTG_DPID_Msk                         (0x3U << USB_OTG_DPID_Pos)    /*!< 0x00018000 */
30256 #define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */
30257 #define USB_OTG_DPID_0                           (0x1U << USB_OTG_DPID_Pos)    /*!< 0x00008000 */
30258 #define USB_OTG_DPID_1                           (0x2U << USB_OTG_DPID_Pos)    /*!< 0x00010000 */
30259 
30260 #define USB_OTG_PKTSTS_Pos                       (17U)
30261 #define USB_OTG_PKTSTS_Msk                       (0xFU << USB_OTG_PKTSTS_Pos)  /*!< 0x001E0000 */
30262 #define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */
30263 #define USB_OTG_PKTSTS_0                         (0x1U << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */
30264 #define USB_OTG_PKTSTS_1                         (0x2U << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */
30265 #define USB_OTG_PKTSTS_2                         (0x4U << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */
30266 #define USB_OTG_PKTSTS_3                         (0x8U << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */
30267 
30268 #define USB_OTG_EPNUM_Pos                        (0U)
30269 #define USB_OTG_EPNUM_Msk                        (0xFU << USB_OTG_EPNUM_Pos)   /*!< 0x0000000F */
30270 #define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */
30271 #define USB_OTG_EPNUM_0                          (0x1U << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */
30272 #define USB_OTG_EPNUM_1                          (0x2U << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */
30273 #define USB_OTG_EPNUM_2                          (0x4U << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */
30274 #define USB_OTG_EPNUM_3                          (0x8U << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */
30275 
30276 #define USB_OTG_FRMNUM_Pos                       (21U)
30277 #define USB_OTG_FRMNUM_Msk                       (0xFU << USB_OTG_FRMNUM_Pos)  /*!< 0x01E00000 */
30278 #define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */
30279 #define USB_OTG_FRMNUM_0                         (0x1U << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */
30280 #define USB_OTG_FRMNUM_1                         (0x2U << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */
30281 #define USB_OTG_FRMNUM_2                         (0x4U << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */
30282 #define USB_OTG_FRMNUM_3                         (0x8U << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */
30283 
30284 /********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/
30285 #define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)
30286 #define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
30287 #define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */
30288 
30289 /********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/
30290 #define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)
30291 #define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
30292 #define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */
30293 
30294 /********************  Bit definition for OTG register  ********************/
30295 #define USB_OTG_NPTXFSA_Pos                      (0U)
30296 #define USB_OTG_NPTXFSA_Msk                      (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
30297 #define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */
30298 #define USB_OTG_NPTXFD_Pos                       (16U)
30299 #define USB_OTG_NPTXFD_Msk                       (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
30300 #define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */
30301 #define USB_OTG_TX0FSA_Pos                       (0U)
30302 #define USB_OTG_TX0FSA_Msk                       (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
30303 #define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */
30304 #define USB_OTG_TX0FD_Pos                        (16U)
30305 #define USB_OTG_TX0FD_Msk                        (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
30306 #define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */
30307 
30308 /********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/
30309 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)
30310 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
30311 #define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
30312 
30313 /********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/
30314 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)
30315 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
30316 #define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
30317 
30318 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)
30319 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
30320 #define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
30321 #define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
30322 #define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
30323 #define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
30324 #define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
30325 #define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
30326 #define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
30327 #define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
30328 #define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
30329 
30330 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)
30331 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
30332 #define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
30333 #define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
30334 #define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
30335 #define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
30336 #define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
30337 #define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
30338 #define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
30339 #define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
30340 
30341 /********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/
30342 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)
30343 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
30344 #define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
30345 #define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)
30346 #define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
30347 #define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */
30348 
30349 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)
30350 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
30351 #define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */
30352 #define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
30353 #define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
30354 #define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
30355 #define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
30356 #define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
30357 #define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
30358 #define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
30359 #define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
30360 #define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
30361 #define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)
30362 #define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
30363 #define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */
30364 
30365 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)
30366 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
30367 #define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */
30368 #define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
30369 #define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
30370 #define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
30371 #define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
30372 #define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
30373 #define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
30374 #define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
30375 #define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
30376 #define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
30377 #define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)
30378 #define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
30379 #define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */
30380 
30381 /********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/
30382 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)
30383 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
30384 #define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
30385 
30386 /********************  Bit definition forUSB_OTG_DEACHINT register  ********************/
30387 #define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)
30388 #define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
30389 #define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */
30390 #define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)
30391 #define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
30392 #define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */
30393 
30394 /********************  Bit definition forUSB_OTG_GCCFG register  ********************/
30395 #define USB_OTG_GCCFG_DCDET_Pos                  (0U)
30396 #define USB_OTG_GCCFG_DCDET_Msk                  (0x1U << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */
30397 #define USB_OTG_GCCFG_DCDET                      USB_OTG_GCCFG_DCDET_Msk       /*!< Data contact detection (DCD) status */
30398 #define USB_OTG_GCCFG_PDET_Pos                   (1U)
30399 #define USB_OTG_GCCFG_PDET_Msk                   (0x1U << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */
30400 #define USB_OTG_GCCFG_PDET                       USB_OTG_GCCFG_PDET_Msk        /*!< Primary detection (PD) status */
30401 #define USB_OTG_GCCFG_SDET_Pos                   (2U)
30402 #define USB_OTG_GCCFG_SDET_Msk                   (0x1U << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */
30403 #define USB_OTG_GCCFG_SDET                       USB_OTG_GCCFG_SDET_Msk        /*!< Secondary detection (SD) status */
30404 #define USB_OTG_GCCFG_PS2DET_Pos                 (3U)
30405 #define USB_OTG_GCCFG_PS2DET_Msk                 (0x1U << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */
30406 #define USB_OTG_GCCFG_PS2DET                     USB_OTG_GCCFG_PS2DET_Msk      /*!< DM pull-up detection status */
30407 #define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)
30408 #define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
30409 #define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */
30410 #define USB_OTG_GCCFG_BCDEN_Pos                  (17U)
30411 #define USB_OTG_GCCFG_BCDEN_Msk                  (0x1U << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */
30412 #define USB_OTG_GCCFG_BCDEN                      USB_OTG_GCCFG_BCDEN_Msk       /*!< Battery charging detector (BCD) enable */
30413 #define USB_OTG_GCCFG_DCDEN_Pos                  (18U)
30414 #define USB_OTG_GCCFG_DCDEN_Msk                  (0x1U << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */
30415 #define USB_OTG_GCCFG_DCDEN                      USB_OTG_GCCFG_DCDEN_Msk       /*!< Data contact detection (DCD) mode enable*/
30416 #define USB_OTG_GCCFG_PDEN_Pos                   (19U)
30417 #define USB_OTG_GCCFG_PDEN_Msk                   (0x1U << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */
30418 #define USB_OTG_GCCFG_PDEN                       USB_OTG_GCCFG_PDEN_Msk        /*!< Primary detection (PD) mode enable*/
30419 #define USB_OTG_GCCFG_SDEN_Pos                   (20U)
30420 #define USB_OTG_GCCFG_SDEN_Msk                   (0x1U << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */
30421 #define USB_OTG_GCCFG_SDEN                       USB_OTG_GCCFG_SDEN_Msk        /*!< Secondary detection (SD) mode enable */
30422 #define USB_OTG_GCCFG_VBDEN_Pos                  (21U)
30423 #define USB_OTG_GCCFG_VBDEN_Msk                  (0x1U << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
30424 #define USB_OTG_GCCFG_VBDEN                      USB_OTG_GCCFG_VBDEN_Msk       /*!< Secondary detection (SD) mode enable */
30425 #define USB_OTG_GCCFG_OTGIDEN_Pos                (22U)
30426 #define USB_OTG_GCCFG_OTGIDEN_Msk                (0x1U << USB_OTG_GCCFG_OTGIDEN_Pos) /*!< 0x00400000 */
30427 #define USB_OTG_GCCFG_OTGIDEN                    USB_OTG_GCCFG_OTGIDEN_Msk     /*!< OTG Id enable */
30428 #define USB_OTG_GCCFG_PHYHSEN_Pos                (23U)
30429 #define USB_OTG_GCCFG_PHYHSEN_Msk                (0x1U << USB_OTG_GCCFG_PHYHSEN_Pos) /*!< 0x00800000 */
30430 #define USB_OTG_GCCFG_PHYHSEN                    USB_OTG_GCCFG_PHYHSEN_Msk     /*!< HS PHY enable */
30431 
30432 /********************  Bit definition forUSB_OTG_GPWRDN) register  ********************/
30433 #define USB_OTG_GPWRDN_ADPMEN_Pos                (0U)
30434 #define USB_OTG_GPWRDN_ADPMEN_Msk                (0x1U << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */
30435 #define USB_OTG_GPWRDN_ADPMEN                    USB_OTG_GPWRDN_ADPMEN_Msk     /*!< ADP module enable */
30436 #define USB_OTG_GPWRDN_ADPIF_Pos                 (23U)
30437 #define USB_OTG_GPWRDN_ADPIF_Msk                 (0x1U << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */
30438 #define USB_OTG_GPWRDN_ADPIF                     USB_OTG_GPWRDN_ADPIF_Msk      /*!< ADP Interrupt flag */
30439 
30440 /********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/
30441 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)
30442 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
30443 #define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */
30444 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)
30445 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
30446 #define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
30447 
30448 /********************  Bit definition forUSB_OTG_CID register  ********************/
30449 #define USB_OTG_CID_PRODUCT_ID_Pos               (0U)
30450 #define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
30451 #define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */
30452 
30453 /********************  Bit definition for USB_OTG_GLPMCFG register  ********************/
30454 #define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)
30455 #define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
30456 #define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /*!< LPM support enable                                     */
30457 #define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)
30458 #define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
30459 #define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /*!< LPM Token acknowledge enable                           */
30460 #define USB_OTG_GLPMCFG_BESL_Pos                 (2U)
30461 #define USB_OTG_GLPMCFG_BESL_Msk                 (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
30462 #define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /*!< BESL value received with last ACKed LPM Token          */
30463 #define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)
30464 #define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
30465 #define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /*!< bRemoteWake value received with last ACKed LPM Token   */
30466 #define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)
30467 #define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
30468 #define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /*!< L1 shallow sleep enable                                */
30469 #define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)
30470 #define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
30471 #define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /*!< BESL threshold                                         */
30472 #define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)
30473 #define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
30474 #define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /*!< L1 deep sleep enable                                   */
30475 #define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)
30476 #define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
30477 #define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /*!< LPM response                                           */
30478 #define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)
30479 #define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
30480 #define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /*!< Port sleep status                                      */
30481 #define USB_OTG_GLPMCFG_L1RSMOK_Pos              (16U)
30482 #define USB_OTG_GLPMCFG_L1RSMOK_Msk              (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
30483 #define USB_OTG_GLPMCFG_L1RSMOK                  USB_OTG_GLPMCFG_L1RSMOK_Msk   /*!< Sleep State Resume OK                                  */
30484 #define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)
30485 #define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
30486 #define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /*!< LPM Channel Index                                      */
30487 #define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)
30488 #define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
30489 #define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /*!< LPM retry count                                        */
30490 #define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)
30491 #define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
30492 #define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /*!< Send LPM transaction                                   */
30493 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)
30494 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
30495 #define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status                                 */
30496 #define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)
30497 #define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
30498 #define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /*!< Enable best effort service latency                     */
30499 
30500 /********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/
30501 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)
30502 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
30503 #define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */
30504 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)
30505 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
30506 #define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */
30507 #define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)
30508 #define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
30509 #define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */
30510 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)
30511 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
30512 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
30513 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)
30514 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
30515 #define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */
30516 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)
30517 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
30518 #define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */
30519 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)
30520 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
30521 #define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
30522 #define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)
30523 #define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
30524 #define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */
30525 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)
30526 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
30527 #define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
30528 
30529 /********************  Bit definition forUSB_OTG_HPRT register  ********************/
30530 #define USB_OTG_HPRT_PCSTS_Pos                   (0U)
30531 #define USB_OTG_HPRT_PCSTS_Msk                   (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
30532 #define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */
30533 #define USB_OTG_HPRT_PCDET_Pos                   (1U)
30534 #define USB_OTG_HPRT_PCDET_Msk                   (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
30535 #define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */
30536 #define USB_OTG_HPRT_PENA_Pos                    (2U)
30537 #define USB_OTG_HPRT_PENA_Msk                    (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
30538 #define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */
30539 #define USB_OTG_HPRT_PENCHNG_Pos                 (3U)
30540 #define USB_OTG_HPRT_PENCHNG_Msk                 (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
30541 #define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */
30542 #define USB_OTG_HPRT_POCA_Pos                    (4U)
30543 #define USB_OTG_HPRT_POCA_Msk                    (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
30544 #define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */
30545 #define USB_OTG_HPRT_POCCHNG_Pos                 (5U)
30546 #define USB_OTG_HPRT_POCCHNG_Msk                 (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
30547 #define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */
30548 #define USB_OTG_HPRT_PRES_Pos                    (6U)
30549 #define USB_OTG_HPRT_PRES_Msk                    (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
30550 #define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume   */
30551 #define USB_OTG_HPRT_PSUSP_Pos                   (7U)
30552 #define USB_OTG_HPRT_PSUSP_Msk                   (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
30553 #define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend  */
30554 #define USB_OTG_HPRT_PRST_Pos                    (8U)
30555 #define USB_OTG_HPRT_PRST_Msk                    (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
30556 #define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset    */
30557 
30558 #define USB_OTG_HPRT_PLSTS_Pos                   (10U)
30559 #define USB_OTG_HPRT_PLSTS_Msk                   (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
30560 #define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status */
30561 #define USB_OTG_HPRT_PLSTS_0                     (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
30562 #define USB_OTG_HPRT_PLSTS_1                     (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
30563 #define USB_OTG_HPRT_PPWR_Pos                    (12U)
30564 #define USB_OTG_HPRT_PPWR_Msk                    (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
30565 #define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power */
30566 
30567 #define USB_OTG_HPRT_PTCTL_Pos                   (13U)
30568 #define USB_OTG_HPRT_PTCTL_Msk                   (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
30569 #define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control */
30570 #define USB_OTG_HPRT_PTCTL_0                     (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
30571 #define USB_OTG_HPRT_PTCTL_1                     (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
30572 #define USB_OTG_HPRT_PTCTL_2                     (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
30573 #define USB_OTG_HPRT_PTCTL_3                     (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
30574 
30575 #define USB_OTG_HPRT_PSPD_Pos                    (17U)
30576 #define USB_OTG_HPRT_PSPD_Msk                    (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
30577 #define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed */
30578 #define USB_OTG_HPRT_PSPD_0                      (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
30579 #define USB_OTG_HPRT_PSPD_1                      (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
30580 
30581 /********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/
30582 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)
30583 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
30584 #define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
30585 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)
30586 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
30587 #define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
30588 #define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)
30589 #define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
30590 #define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask */
30591 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)
30592 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
30593 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
30594 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)
30595 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
30596 #define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
30597 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)
30598 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
30599 #define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
30600 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)
30601 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
30602 #define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
30603 #define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)
30604 #define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
30605 #define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */
30606 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)
30607 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
30608 #define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
30609 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)
30610 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
30611 #define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
30612 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)
30613 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
30614 #define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
30615 
30616 /********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/
30617 #define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)
30618 #define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
30619 #define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address */
30620 #define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)
30621 #define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
30622 #define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth */
30623 
30624 /********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/
30625 #define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)
30626 #define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
30627 #define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size */
30628 #define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)
30629 #define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
30630 #define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint */
30631 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)
30632 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
30633 #define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
30634 #define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)
30635 #define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
30636 #define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status */
30637 
30638 #define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)
30639 #define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
30640 #define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type */
30641 #define USB_OTG_DIEPCTL_EPTYP_0                  (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
30642 #define USB_OTG_DIEPCTL_EPTYP_1                  (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
30643 #define USB_OTG_DIEPCTL_STALL_Pos                (21U)
30644 #define USB_OTG_DIEPCTL_STALL_Msk                (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
30645 #define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake */
30646 
30647 #define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)
30648 #define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
30649 #define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number */
30650 #define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
30651 #define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
30652 #define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
30653 #define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
30654 #define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)
30655 #define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
30656 #define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK */
30657 #define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)
30658 #define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
30659 #define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */
30660 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)
30661 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
30662 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
30663 #define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)
30664 #define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
30665 #define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame */
30666 #define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)
30667 #define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
30668 #define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable */
30669 #define USB_OTG_DIEPCTL_EPENA_Pos                (31U)
30670 #define USB_OTG_DIEPCTL_EPENA_Msk                (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
30671 #define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable */
30672 
30673 /********************  Bit definition forUSB_OTG_HCCHAR register  ********************/
30674 #define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)
30675 #define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
30676 #define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */
30677 
30678 #define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)
30679 #define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
30680 #define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */
30681 #define USB_OTG_HCCHAR_EPNUM_0                   (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
30682 #define USB_OTG_HCCHAR_EPNUM_1                   (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
30683 #define USB_OTG_HCCHAR_EPNUM_2                   (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
30684 #define USB_OTG_HCCHAR_EPNUM_3                   (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
30685 #define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)
30686 #define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
30687 #define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */
30688 #define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)
30689 #define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
30690 #define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */
30691 
30692 #define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)
30693 #define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
30694 #define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */
30695 #define USB_OTG_HCCHAR_EPTYP_0                   (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
30696 #define USB_OTG_HCCHAR_EPTYP_1                   (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
30697 
30698 #define USB_OTG_HCCHAR_MC_Pos                    (20U)
30699 #define USB_OTG_HCCHAR_MC_Msk                    (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
30700 #define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */
30701 #define USB_OTG_HCCHAR_MC_0                      (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
30702 #define USB_OTG_HCCHAR_MC_1                      (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
30703 
30704 #define USB_OTG_HCCHAR_DAD_Pos                   (22U)
30705 #define USB_OTG_HCCHAR_DAD_Msk                   (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
30706 #define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */
30707 #define USB_OTG_HCCHAR_DAD_0                     (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
30708 #define USB_OTG_HCCHAR_DAD_1                     (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
30709 #define USB_OTG_HCCHAR_DAD_2                     (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
30710 #define USB_OTG_HCCHAR_DAD_3                     (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
30711 #define USB_OTG_HCCHAR_DAD_4                     (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
30712 #define USB_OTG_HCCHAR_DAD_5                     (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
30713 #define USB_OTG_HCCHAR_DAD_6                     (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
30714 #define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)
30715 #define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
30716 #define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */
30717 #define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)
30718 #define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
30719 #define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */
30720 #define USB_OTG_HCCHAR_CHENA_Pos                 (31U)
30721 #define USB_OTG_HCCHAR_CHENA_Msk                 (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
30722 #define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */
30723 
30724 /********************  Bit definition forUSB_OTG_HCSPLT register  ********************/
30725 
30726 #define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)
30727 #define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
30728 #define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */
30729 #define USB_OTG_HCSPLT_PRTADDR_0                 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
30730 #define USB_OTG_HCSPLT_PRTADDR_1                 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
30731 #define USB_OTG_HCSPLT_PRTADDR_2                 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
30732 #define USB_OTG_HCSPLT_PRTADDR_3                 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
30733 #define USB_OTG_HCSPLT_PRTADDR_4                 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
30734 #define USB_OTG_HCSPLT_PRTADDR_5                 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
30735 #define USB_OTG_HCSPLT_PRTADDR_6                 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
30736 
30737 #define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)
30738 #define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
30739 #define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */
30740 #define USB_OTG_HCSPLT_HUBADDR_0                 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
30741 #define USB_OTG_HCSPLT_HUBADDR_1                 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
30742 #define USB_OTG_HCSPLT_HUBADDR_2                 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
30743 #define USB_OTG_HCSPLT_HUBADDR_3                 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
30744 #define USB_OTG_HCSPLT_HUBADDR_4                 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
30745 #define USB_OTG_HCSPLT_HUBADDR_5                 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
30746 #define USB_OTG_HCSPLT_HUBADDR_6                 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
30747 
30748 #define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)
30749 #define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
30750 #define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */
30751 #define USB_OTG_HCSPLT_XACTPOS_0                 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
30752 #define USB_OTG_HCSPLT_XACTPOS_1                 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
30753 #define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)
30754 #define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
30755 #define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */
30756 #define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)
30757 #define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
30758 #define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */
30759 
30760 /********************  Bit definition forUSB_OTG_HCINT register  ********************/
30761 #define USB_OTG_HCINT_XFRC_Pos                   (0U)
30762 #define USB_OTG_HCINT_XFRC_Msk                   (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
30763 #define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */
30764 #define USB_OTG_HCINT_CHH_Pos                    (1U)
30765 #define USB_OTG_HCINT_CHH_Msk                    (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
30766 #define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */
30767 #define USB_OTG_HCINT_AHBERR_Pos                 (2U)
30768 #define USB_OTG_HCINT_AHBERR_Msk                 (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
30769 #define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */
30770 #define USB_OTG_HCINT_STALL_Pos                  (3U)
30771 #define USB_OTG_HCINT_STALL_Msk                  (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
30772 #define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */
30773 #define USB_OTG_HCINT_NAK_Pos                    (4U)
30774 #define USB_OTG_HCINT_NAK_Msk                    (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
30775 #define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */
30776 #define USB_OTG_HCINT_ACK_Pos                    (5U)
30777 #define USB_OTG_HCINT_ACK_Msk                    (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
30778 #define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */
30779 #define USB_OTG_HCINT_NYET_Pos                   (6U)
30780 #define USB_OTG_HCINT_NYET_Msk                   (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
30781 #define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */
30782 #define USB_OTG_HCINT_TXERR_Pos                  (7U)
30783 #define USB_OTG_HCINT_TXERR_Msk                  (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
30784 #define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */
30785 #define USB_OTG_HCINT_BBERR_Pos                  (8U)
30786 #define USB_OTG_HCINT_BBERR_Msk                  (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
30787 #define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */
30788 #define USB_OTG_HCINT_FRMOR_Pos                  (9U)
30789 #define USB_OTG_HCINT_FRMOR_Msk                  (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
30790 #define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */
30791 #define USB_OTG_HCINT_DTERR_Pos                  (10U)
30792 #define USB_OTG_HCINT_DTERR_Msk                  (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
30793 #define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */
30794 
30795 /********************  Bit definition forUSB_OTG_DIEPINT register  ********************/
30796 #define USB_OTG_DIEPINT_XFRC_Pos                 (0U)
30797 #define USB_OTG_DIEPINT_XFRC_Msk                 (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
30798 #define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
30799 #define USB_OTG_DIEPINT_EPDISD_Pos               (1U)
30800 #define USB_OTG_DIEPINT_EPDISD_Msk               (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
30801 #define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
30802 #define USB_OTG_DIEPINT_TOC_Pos                  (3U)
30803 #define USB_OTG_DIEPINT_TOC_Msk                  (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
30804 #define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */
30805 #define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)
30806 #define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
30807 #define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */
30808 #define USB_OTG_DIEPINT_INEPNE_Pos               (6U)
30809 #define USB_OTG_DIEPINT_INEPNE_Msk               (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
30810 #define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */
30811 #define USB_OTG_DIEPINT_TXFE_Pos                 (7U)
30812 #define USB_OTG_DIEPINT_TXFE_Msk                 (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
30813 #define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */
30814 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)
30815 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
30816 #define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
30817 #define USB_OTG_DIEPINT_BNA_Pos                  (9U)
30818 #define USB_OTG_DIEPINT_BNA_Msk                  (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
30819 #define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */
30820 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)
30821 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
30822 #define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
30823 #define USB_OTG_DIEPINT_BERR_Pos                 (12U)
30824 #define USB_OTG_DIEPINT_BERR_Msk                 (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
30825 #define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */
30826 #define USB_OTG_DIEPINT_NAK_Pos                  (13U)
30827 #define USB_OTG_DIEPINT_NAK_Msk                  (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
30828 #define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */
30829 
30830 /********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/
30831 #define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)
30832 #define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
30833 #define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */
30834 #define USB_OTG_HCINTMSK_CHHM_Pos                (1U)
30835 #define USB_OTG_HCINTMSK_CHHM_Msk                (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
30836 #define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */
30837 #define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)
30838 #define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
30839 #define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */
30840 #define USB_OTG_HCINTMSK_STALLM_Pos              (3U)
30841 #define USB_OTG_HCINTMSK_STALLM_Msk              (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
30842 #define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */
30843 #define USB_OTG_HCINTMSK_NAKM_Pos                (4U)
30844 #define USB_OTG_HCINTMSK_NAKM_Msk                (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
30845 #define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */
30846 #define USB_OTG_HCINTMSK_ACKM_Pos                (5U)
30847 #define USB_OTG_HCINTMSK_ACKM_Msk                (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
30848 #define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */
30849 #define USB_OTG_HCINTMSK_NYET_Pos                (6U)
30850 #define USB_OTG_HCINTMSK_NYET_Msk                (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
30851 #define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */
30852 #define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)
30853 #define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
30854 #define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */
30855 #define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)
30856 #define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
30857 #define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */
30858 #define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)
30859 #define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
30860 #define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */
30861 #define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)
30862 #define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
30863 #define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */
30864 
30865 /********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
30866 
30867 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)
30868 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
30869 #define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
30870 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)
30871 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
30872 #define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */
30873 #define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)
30874 #define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
30875 #define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */
30876 /********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/
30877 #define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)
30878 #define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
30879 #define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */
30880 #define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)
30881 #define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
30882 #define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */
30883 #define USB_OTG_HCTSIZ_DOPING_Pos                (31U)
30884 #define USB_OTG_HCTSIZ_DOPING_Msk                (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
30885 #define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */
30886 #define USB_OTG_HCTSIZ_DPID_Pos                  (29U)
30887 #define USB_OTG_HCTSIZ_DPID_Msk                  (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
30888 #define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */
30889 #define USB_OTG_HCTSIZ_DPID_0                    (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
30890 #define USB_OTG_HCTSIZ_DPID_1                    (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
30891 
30892 /********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/
30893 #define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)
30894 #define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
30895 #define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */
30896 
30897 /********************  Bit definition forUSB_OTG_HCDMA register  ********************/
30898 #define USB_OTG_HCDMA_DMAADDR_Pos                (0U)
30899 #define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
30900 #define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */
30901 
30902 /********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/
30903 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)
30904 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
30905 #define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
30906 
30907 /********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/
30908 #define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)
30909 #define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
30910 #define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */
30911 #define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)
30912 #define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
30913 #define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */
30914 
30915 /********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/
30916 
30917 #define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)
30918 #define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
30919 #define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */
30920 #define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)
30921 #define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
30922 #define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */
30923 #define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)
30924 #define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
30925 #define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */
30926 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)
30927 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
30928 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
30929 #define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)
30930 #define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
30931 #define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */
30932 #define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)
30933 #define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
30934 #define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */
30935 #define USB_OTG_DOEPCTL_EPTYP_0                  (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
30936 #define USB_OTG_DOEPCTL_EPTYP_1                  (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
30937 #define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)
30938 #define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
30939 #define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */
30940 #define USB_OTG_DOEPCTL_STALL_Pos                (21U)
30941 #define USB_OTG_DOEPCTL_STALL_Msk                (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
30942 #define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */
30943 #define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)
30944 #define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
30945 #define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */
30946 #define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)
30947 #define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
30948 #define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */
30949 #define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)
30950 #define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
30951 #define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */
30952 #define USB_OTG_DOEPCTL_EPENA_Pos                (31U)
30953 #define USB_OTG_DOEPCTL_EPENA_Msk                (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
30954 #define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */
30955 
30956 /********************  Bit definition forUSB_OTG_DOEPINT register  ********************/
30957 #define USB_OTG_DOEPINT_XFRC_Pos                 (0U)
30958 #define USB_OTG_DOEPINT_XFRC_Msk                 (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
30959 #define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
30960 #define USB_OTG_DOEPINT_EPDISD_Pos               (1U)
30961 #define USB_OTG_DOEPINT_EPDISD_Msk               (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
30962 #define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
30963 #define USB_OTG_DOEPINT_STUP_Pos                 (3U)
30964 #define USB_OTG_DOEPINT_STUP_Msk                 (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
30965 #define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */
30966 #define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)
30967 #define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
30968 #define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */
30969 #define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)
30970 #define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
30971 #define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */
30972 #define USB_OTG_DOEPINT_NYET_Pos                 (14U)
30973 #define USB_OTG_DOEPINT_NYET_Msk                 (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
30974 #define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */
30975 
30976 /********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/
30977 
30978 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)
30979 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
30980 #define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
30981 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)
30982 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
30983 #define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */
30984 
30985 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)
30986 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
30987 #define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */
30988 #define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
30989 #define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
30990 
30991 /********************  Bit definition for PCGCCTL register  ********************/
30992 #define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)
30993 #define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
30994 #define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */
30995 #define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)
30996 #define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
30997 #define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */
30998 #define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)
30999 #define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
31000 #define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */
31001 
31002 /**
31003   * @}
31004   */
31005 
31006 /**
31007   * @}
31008   */
31009 
31010 /** @addtogroup Exported_macros
31011   * @{
31012   */
31013 
31014 /******************************* ADC Instances ********************************/
31015 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
31016                                        ((INSTANCE) == ADC2))
31017 
31018 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
31019 
31020 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)
31021 
31022 /******************************** DTS Instances ******************************/
31023 #define IS_DTS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DTS1)
31024 
31025 
31026 /******************************* CRC Instances ********************************/
31027 #define IS_CRC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CRC1) || \
31028                                        ((INSTANCE) == CRC2))
31029 
31030 
31031 /******************************* DAC Instances ********************************/
31032 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
31033 
31034 /******************************* DCMI Instances *******************************/
31035 #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
31036 
31037 /****************************** DFSDM Instances *******************************/
31038 #define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
31039                                          ((INSTANCE) == DFSDM1_Filter1) || \
31040                                          ((INSTANCE) == DFSDM1_Filter2) || \
31041                                          ((INSTANCE) == DFSDM1_Filter3) || \
31042                                          ((INSTANCE) == DFSDM1_Filter4) || \
31043                                          ((INSTANCE) == DFSDM1_Filter5))
31044 
31045 #define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
31046                                                  ((INSTANCE) == DFSDM1_Channel1) || \
31047                                                  ((INSTANCE) == DFSDM1_Channel2) || \
31048                                                  ((INSTANCE) == DFSDM1_Channel3) || \
31049                                                  ((INSTANCE) == DFSDM1_Channel4) || \
31050                                                  ((INSTANCE) == DFSDM1_Channel5) || \
31051                                                  ((INSTANCE) == DFSDM1_Channel6) || \
31052                                                  ((INSTANCE) == DFSDM1_Channel7))
31053 
31054 /******************************** DMA Instances *******************************/
31055 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
31056                                              ((INSTANCE) == DMA1_Stream1) || \
31057                                              ((INSTANCE) == DMA1_Stream2) || \
31058                                              ((INSTANCE) == DMA1_Stream3) || \
31059                                              ((INSTANCE) == DMA1_Stream4) || \
31060                                              ((INSTANCE) == DMA1_Stream5) || \
31061                                              ((INSTANCE) == DMA1_Stream6) || \
31062                                              ((INSTANCE) == DMA1_Stream7) || \
31063                                              ((INSTANCE) == DMA2_Stream0) || \
31064                                              ((INSTANCE) == DMA2_Stream1) || \
31065                                              ((INSTANCE) == DMA2_Stream2) || \
31066                                              ((INSTANCE) == DMA2_Stream3) || \
31067                                              ((INSTANCE) == DMA2_Stream4) || \
31068                                              ((INSTANCE) == DMA2_Stream5) || \
31069                                              ((INSTANCE) == DMA2_Stream6) || \
31070                                              ((INSTANCE) == DMA2_Stream7))
31071 
31072 /******************************** DMA Request Generator Instances **************/
31073 #define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \
31074                                                    ((INSTANCE) == DMAMUX1_RequestGenerator1) || \
31075                                                    ((INSTANCE) == DMAMUX1_RequestGenerator2) || \
31076                                                    ((INSTANCE) == DMAMUX1_RequestGenerator3))
31077 
31078 /******************************** MDMA Request Generator Instances **************/
31079 #define IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDMA_Channel0) || \
31080                                                ((INSTANCE) == MDMA_Channel1) || \
31081                                                ((INSTANCE) == MDMA_Channel2) || \
31082                                                ((INSTANCE) == MDMA_Channel3) || \
31083                                                ((INSTANCE) == MDMA_Channel4) || \
31084                                                ((INSTANCE) == MDMA_Channel5) || \
31085                                                ((INSTANCE) == MDMA_Channel6) || \
31086                                                ((INSTANCE) == MDMA_Channel7) || \
31087                                                ((INSTANCE) == MDMA_Channel8) || \
31088                                                ((INSTANCE) == MDMA_Channel9)  || \
31089                                                ((INSTANCE) == MDMA_Channel10) || \
31090                                                ((INSTANCE) == MDMA_Channel11) || \
31091                                                ((INSTANCE) == MDMA_Channel12) || \
31092                                                ((INSTANCE) == MDMA_Channel13) || \
31093                                                ((INSTANCE) == MDMA_Channel14) || \
31094                                                ((INSTANCE) == MDMA_Channel15) || \
31095                                                ((INSTANCE) == MDMA_Channel16))
31096 /******************************* QUADSPI Instances *******************************/
31097 #define IS_QSPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == QUADSPI)
31098 
31099 /******************************* FDCAN Instances ******************************/
31100 #define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1) || \
31101                                              ((INSTANCE) == FDCAN2))
31102 
31103 #define IS_FDCAN_TT_INSTANCE(INSTANCE) ((INSTANCE) == FDCAN1)
31104 
31105 /******************************* GPIO Instances *******************************/
31106 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
31107                                         ((INSTANCE) == GPIOB) || \
31108                                         ((INSTANCE) == GPIOC) || \
31109                                         ((INSTANCE) == GPIOD) || \
31110                                         ((INSTANCE) == GPIOE) || \
31111                                         ((INSTANCE) == GPIOF) || \
31112                                         ((INSTANCE) == GPIOG) || \
31113                                         ((INSTANCE) == GPIOH) || \
31114                                         ((INSTANCE) == GPIOI) || \
31115                                         ((INSTANCE) == GPIOJ) || \
31116                                         ((INSTANCE) == GPIOK) || \
31117                                         ((INSTANCE) == GPIOZ))
31118 
31119 /**************************** GPIO Lock Instances *****************************/
31120 /* On L4, all GPIO Bank support the Lock mechanism */
31121 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
31122 
31123 /******************************** HSEM Instances *******************************/
31124 #define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)
31125 /********************  Bit definition for HSEM_CR register  *****************/
31126 #define HSEM_CPU1_COREID    (0x00000001U) /* Semaphore Core CA7 ID */
31127 #define HSEM_CPU2_COREID    (0x00000002U) /* Semaphore Core CM4 ID */
31128 #define HSEM_CR_COREID_CURRENT   (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
31129 
31130 #define HSEM_SEMID_MIN     (0U)       /* HSEM ID Min*/
31131 #define HSEM_SEMID_MAX     (31U)      /* HSEM ID Max */
31132 
31133 #define HSEM_PROCESSID_MIN (0U)       /* HSEM Process ID Min */
31134 #define HSEM_PROCESSID_MAX (255U)     /* HSEM Process ID Max */
31135 
31136 #define HSEM_CLEAR_KEY_MIN (0U)       /* HSEM clear Key Min value */
31137 #define HSEM_CLEAR_KEY_MAX (0xFFFFU)  /* HSEM clear Key Max value */
31138 
31139 /******************************** I2C Instances *******************************/
31140 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
31141                                        ((INSTANCE) == I2C2) || \
31142                                        ((INSTANCE) == I2C3) || \
31143                                        ((INSTANCE) == I2C4) || \
31144                                        ((INSTANCE) == I2C5) || \
31145                                        ((INSTANCE) == I2C6) )
31146 /************** I2C Instances : wakeup capability from stop modes *************/
31147 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
31148 
31149 /****************************** SMBUS Instances *******************************/
31150 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
31151                                          ((INSTANCE) == I2C2) || \
31152                                          ((INSTANCE) == I2C3) || \
31153                                          ((INSTANCE) == I2C4) || \
31154                                          ((INSTANCE) == I2C5) || \
31155                                          ((INSTANCE) == I2C6) )
31156 
31157 /******************************* IPCC Instances ********************************/
31158 #define IS_IPCC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IPCC)
31159 
31160 /******************************** I2S Instances *******************************/
31161 #define IS_I2S_ALL_INSTANCE(INSTANCE)   (((INSTANCE) == SPI1) || \
31162                                          ((INSTANCE) == SPI2) || \
31163                                          ((INSTANCE) == SPI3))
31164 
31165 /****************************** LTDC Instances ********************************/
31166 #define IS_LTDC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == LTDC)
31167 
31168 /******************************* RNG Instances ********************************/
31169 #define IS_RNG_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == RNG1) || \
31170                                         ((INSTANCE) == RNG2))
31171 
31172 /******************************* HASH Instances ********************************/
31173 #define IS_HASH_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HASH1) || \
31174                                        ((INSTANCE) == HASH2))
31175 
31176 /******************************* HASH Instances ********************************/
31177 #define IS_HASH_DIGEST_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HASH1_DIGEST) || \
31178                                        ((INSTANCE) == HASH2_DIGEST))
31179 
31180 /****************************** RTC Instances *********************************/
31181 #define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
31182 
31183 /******************************** SDMMC Instances *****************************/
31184 #define IS_SDMMC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SDMMC1) || \
31185                                          ((INSTANCE) == SDMMC2) || \
31186                                          ((INSTANCE) == SDMMC3))
31187 
31188 /******************************** SMBUS Instances *****************************/
31189 #define IS_SMBUS_INSTANCE(INSTANCE)  ((INSTANCE) == I2C1)
31190 
31191 /******************************** SPI Instances *******************************/
31192 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
31193                                        ((INSTANCE) == SPI2) || \
31194                                        ((INSTANCE) == SPI3) || \
31195                                        ((INSTANCE) == SPI4) || \
31196                                        ((INSTANCE) == SPI5) || \
31197                                        ((INSTANCE) == SPI6))
31198 
31199 #define IS_SPI_HIGHEND_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
31200                                            ((INSTANCE) == SPI2) || \
31201                                            ((INSTANCE) == SPI3))
31202 
31203 /****************** LPTIM Instances : All supported instances *****************/
31204 #define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \
31205                                          ((INSTANCE) == LPTIM2) || \
31206                                          ((INSTANCE) == LPTIM3) ||\
31207                                          ((INSTANCE) == LPTIM4) ||\
31208                                          ((INSTANCE) == LPTIM5))
31209 
31210 /****************** LPTIM Instances : supporting encoder interface **************/
31211 #define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \
31212                                                            ((INSTANCE) == LPTIM2))
31213 
31214 /****************** TIM Instances : All supported instances *******************/
31215 #define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \
31216                                          ((INSTANCE) == TIM2)   || \
31217                                          ((INSTANCE) == TIM3)   || \
31218                                          ((INSTANCE) == TIM4)   || \
31219                                          ((INSTANCE) == TIM5)   || \
31220                                          ((INSTANCE) == TIM6)   || \
31221                                          ((INSTANCE) == TIM7)   || \
31222                                          ((INSTANCE) == TIM8)   || \
31223                                          ((INSTANCE) == TIM12)  || \
31224                                          ((INSTANCE) == TIM13)  || \
31225                                          ((INSTANCE) == TIM14)  || \
31226                                          ((INSTANCE) == TIM15)  || \
31227                                          ((INSTANCE) == TIM16)  || \
31228                                          ((INSTANCE) == TIM17))
31229 /************* TIM Instances : at least 1 capture/compare channel *************/
31230 #define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
31231                                          ((INSTANCE) == TIM2)   || \
31232                                          ((INSTANCE) == TIM3)   || \
31233                                          ((INSTANCE) == TIM4)   || \
31234                                          ((INSTANCE) == TIM5)   || \
31235                                          ((INSTANCE) == TIM8)   || \
31236                                          ((INSTANCE) == TIM12)  || \
31237                                          ((INSTANCE) == TIM13)  || \
31238                                          ((INSTANCE) == TIM14)  || \
31239                                          ((INSTANCE) == TIM15)  || \
31240                                          ((INSTANCE) == TIM16)  || \
31241                                          ((INSTANCE) == TIM17))
31242 /************ TIM Instances : at least 2 capture/compare channels *************/
31243 #define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
31244                                          ((INSTANCE) == TIM2)   || \
31245                                          ((INSTANCE) == TIM3)   || \
31246                                          ((INSTANCE) == TIM4)   || \
31247                                          ((INSTANCE) == TIM5)   || \
31248                                          ((INSTANCE) == TIM8)   || \
31249                                          ((INSTANCE) == TIM12)   || \
31250                                          ((INSTANCE) == TIM15))
31251 /************ TIM Instances : at least 3 capture/compare channels *************/
31252 #define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
31253                                          ((INSTANCE) == TIM2)   || \
31254                                          ((INSTANCE) == TIM3)   || \
31255                                          ((INSTANCE) == TIM4)   || \
31256                                          ((INSTANCE) == TIM5)   || \
31257                                          ((INSTANCE) == TIM8))
31258 
31259 /************ TIM Instances : at least 4 capture/compare channels *************/
31260 #define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
31261                                          ((INSTANCE) == TIM2)   || \
31262                                          ((INSTANCE) == TIM3)   || \
31263                                          ((INSTANCE) == TIM4)   || \
31264                                          ((INSTANCE) == TIM5)   || \
31265                                          ((INSTANCE) == TIM8))
31266 /************ TIM Instances : at least 5 capture/compare channels *************/
31267 #define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
31268                                          ((INSTANCE) == TIM8))
31269 /************ TIM Instances : at least 6 capture/compare channels *************/
31270 #define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
31271                                          ((INSTANCE) == TIM8))
31272 
31273 /******************** TIM Instances : Advanced-control timers *****************/
31274 
31275 /******************* TIM Instances : Timer input XOR function *****************/
31276 #define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
31277                                          ((INSTANCE) == TIM2)   || \
31278                                          ((INSTANCE) == TIM3)   || \
31279                                          ((INSTANCE) == TIM4)   || \
31280                                          ((INSTANCE) == TIM5)   || \
31281                                          ((INSTANCE) == TIM8))
31282 /****************** TIM Instances : DMA requests generation (UDE) *************/
31283 #define IS_TIM_DMA_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \
31284                                            ((INSTANCE) == TIM2)   || \
31285                                            ((INSTANCE) == TIM3)   || \
31286                                            ((INSTANCE) == TIM4)   || \
31287                                            ((INSTANCE) == TIM5)   || \
31288                                            ((INSTANCE) == TIM6)   || \
31289                                            ((INSTANCE) == TIM7)   || \
31290                                            ((INSTANCE) == TIM8)   || \
31291                                            ((INSTANCE) == TIM15)  || \
31292                                            ((INSTANCE) == TIM16)  || \
31293                                            ((INSTANCE) == TIM17))
31294 
31295 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
31296 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
31297                                             ((INSTANCE) == TIM2)   || \
31298                                             ((INSTANCE) == TIM3)   || \
31299                                             ((INSTANCE) == TIM4)   || \
31300                                             ((INSTANCE) == TIM5)   || \
31301                                             ((INSTANCE) == TIM8)   || \
31302                                             ((INSTANCE) == TIM15)  || \
31303                                             ((INSTANCE) == TIM16)  || \
31304                                             ((INSTANCE) == TIM17))
31305 
31306 /************ TIM Instances : DMA requests generation (COMDE) *****************/
31307 #define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \
31308                                             ((INSTANCE) == TIM2)   || \
31309                                             ((INSTANCE) == TIM3)   || \
31310                                             ((INSTANCE) == TIM4)   || \
31311                                             ((INSTANCE) == TIM5)   || \
31312                                             ((INSTANCE) == TIM8)   || \
31313                                             ((INSTANCE) == TIM15))
31314 
31315 /******************** TIM Instances : DMA burst feature ***********************/
31316 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
31317                                             ((INSTANCE) == TIM2)   || \
31318                                             ((INSTANCE) == TIM3)   || \
31319                                             ((INSTANCE) == TIM4)   || \
31320                                             ((INSTANCE) == TIM5)   || \
31321                                             ((INSTANCE) == TIM8))
31322 
31323 /***************** TIM Instances : external trigger reamp input availabe *******/
31324 #define IS_TIM_ETR_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \
31325                                            ((INSTANCE) == TIM2)   || \
31326                                            ((INSTANCE) == TIM3)   || \
31327                                            ((INSTANCE) == TIM4)   || \
31328                                            ((INSTANCE) == TIM5)   || \
31329                                            ((INSTANCE) == TIM8))
31330 
31331 /***************** TIM Instances : external trigger reamp input availabe *******/
31332 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \
31333                                               ((INSTANCE) == TIM2)   || \
31334                                               ((INSTANCE) == TIM3)   || \
31335                                               ((INSTANCE) == TIM5)   || \
31336                                               ((INSTANCE) == TIM8))
31337 
31338 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
31339 #define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
31340                                             ((INSTANCE) == TIM2)   || \
31341                                             ((INSTANCE) == TIM3)   || \
31342                                             ((INSTANCE) == TIM4)   || \
31343                                             ((INSTANCE) == TIM5)   || \
31344                                             ((INSTANCE) == TIM6)   || \
31345                                             ((INSTANCE) == TIM7)   || \
31346                                             ((INSTANCE) == TIM8)   || \
31347                                             ((INSTANCE) == TIM12)  || \
31348                                             ((INSTANCE) == TIM15))
31349 
31350 /****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/
31351 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \
31352                                             ((INSTANCE) == TIM2)   || \
31353                                             ((INSTANCE) == TIM3)   || \
31354                                             ((INSTANCE) == TIM4)   || \
31355                                             ((INSTANCE) == TIM5)   || \
31356                                             ((INSTANCE) == TIM8)   || \
31357                                             ((INSTANCE) == TIM12)  || \
31358                                             ((INSTANCE) == TIM15))
31359 
31360 /****************** TIM Instances : remapping capability **********************/
31361 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \
31362                                           ((INSTANCE) == TIM2)  || \
31363                                           ((INSTANCE) == TIM3)  || \
31364                                           ((INSTANCE) == TIM5)  || \
31365                                           ((INSTANCE) == TIM8))
31366 
31367 /****************** TIM Instances : supporting synchronization ****************/
31368 #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)  IS_TIM_MASTER_INSTANCE(INSTANCE)
31369 
31370 /****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
31371 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
31372                                            ((INSTANCE) == TIM8))
31373 
31374 /****** TIM Instances : TISEL available (TIMx_TISEL available )*********/
31375 #define IS_TIM_TISEL_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)   || \
31376                                           ((INSTANCE) == TIM2)   || \
31377                                           ((INSTANCE) == TIM3)   || \
31378                                           ((INSTANCE) == TIM4)   || \
31379                                           ((INSTANCE) == TIM5)   || \
31380                                           ((INSTANCE) == TIM8)   || \
31381                                           ((INSTANCE) == TIM15)  || \
31382                                           ((INSTANCE) == TIM16)  || \
31383                                           ((INSTANCE) == TIM17))
31384 
31385 /****************** TIM Instances : supporting commutation event *************/
31386 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)    || \
31387                                                      ((INSTANCE) == TIM8)    || \
31388                                                      ((INSTANCE) == TIM15)   || \
31389                                                      ((INSTANCE) == TIM16)   || \
31390                                                      ((INSTANCE) == TIM17))
31391 
31392 
31393 /****** TIM Instances : TIM_CCR5_GC5C available (TIMx_CCR5.GC5C available )*********/
31394 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
31395                                                        ((INSTANCE) == TIM8))
31396 /******************* TIM Instances : output(s) available **********************/
31397 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
31398     ((((INSTANCE) == TIM1) &&                  \
31399      (((CHANNEL) == TIM_CHANNEL_1) ||          \
31400       ((CHANNEL) == TIM_CHANNEL_2) ||          \
31401       ((CHANNEL) == TIM_CHANNEL_3) ||          \
31402       ((CHANNEL) == TIM_CHANNEL_4)))           \
31403      ||                                        \
31404      (((INSTANCE) == TIM2) &&                  \
31405      (((CHANNEL) == TIM_CHANNEL_1) ||          \
31406       ((CHANNEL) == TIM_CHANNEL_2) ||          \
31407       ((CHANNEL) == TIM_CHANNEL_3) ||          \
31408       ((CHANNEL) == TIM_CHANNEL_4)))           \
31409   ||                                           \
31410       (((INSTANCE) == TIM3) &&                 \
31411       (((CHANNEL) == TIM_CHANNEL_1)||          \
31412       ((CHANNEL) == TIM_CHANNEL_2) ||          \
31413       ((CHANNEL) == TIM_CHANNEL_3) ||          \
31414       ((CHANNEL) == TIM_CHANNEL_4)))           \
31415   ||                                           \
31416       (((INSTANCE) == TIM4) &&                 \
31417       (((CHANNEL) == TIM_CHANNEL_1) ||         \
31418       ((CHANNEL) == TIM_CHANNEL_2) ||          \
31419       ((CHANNEL) == TIM_CHANNEL_3) ||          \
31420       ((CHANNEL) == TIM_CHANNEL_4)))           \
31421   ||                                           \
31422       (((INSTANCE) == TIM5) &&                 \
31423       (((CHANNEL) == TIM_CHANNEL_1) ||         \
31424       ((CHANNEL) == TIM_CHANNEL_2) ||          \
31425       ((CHANNEL) == TIM_CHANNEL_3) ||          \
31426       ((CHANNEL) == TIM_CHANNEL_4)))           \
31427   ||                                           \
31428       (((INSTANCE) == TIM8) &&                 \
31429       (((CHANNEL) == TIM_CHANNEL_1) ||         \
31430       ((CHANNEL) == TIM_CHANNEL_2) ||          \
31431       ((CHANNEL) == TIM_CHANNEL_3) ||          \
31432       ((CHANNEL) == TIM_CHANNEL_4)))           \
31433   ||                                           \
31434       (((INSTANCE) == TIM12) &&                \
31435       (((CHANNEL) == TIM_CHANNEL_1)))          \
31436   ||                                           \
31437      (((INSTANCE) == TIM13) &&                 \
31438      (((CHANNEL) == TIM_CHANNEL_1)))           \
31439   ||                                           \
31440      (((INSTANCE) == TIM14) &&                 \
31441      (((CHANNEL) == TIM_CHANNEL_1)))           \
31442   ||                                           \
31443      (((INSTANCE) == TIM15) &&                 \
31444      (((CHANNEL) == TIM_CHANNEL_1) ||          \
31445      ((CHANNEL) == TIM_CHANNEL_2)))            \
31446   ||                                           \
31447      (((INSTANCE) == TIM16) &&                 \
31448      (((CHANNEL) == TIM_CHANNEL_1)))           \
31449   ||                                           \
31450      (((INSTANCE) == TIM17) &&                 \
31451      (((CHANNEL) == TIM_CHANNEL_1))))
31452 
31453 /****************** TIM Instances : supporting the break function *************/
31454 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
31455       (((INSTANCE) == TIM1)    || \
31456       ((INSTANCE) == TIM8)     || \
31457        ((INSTANCE) == TIM15)   || \
31458        ((INSTANCE) == TIM16)   || \
31459        ((INSTANCE) == TIM17))
31460 
31461 /************** TIM Instances : supporting Break source selection *************/
31462 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
31463                                                ((INSTANCE) == TIM8)   || \
31464                                                ((INSTANCE) == TIM15)  || \
31465                                                ((INSTANCE) == TIM16)  || \
31466                                                ((INSTANCE) == TIM17))
31467 
31468 /****************** TIM Instances : supporting complementary output(s) ********/
31469 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
31470    ((((INSTANCE) == TIM1) &&                    \
31471      (((CHANNEL) == TIM_CHANNEL_1) ||           \
31472       ((CHANNEL) == TIM_CHANNEL_2) ||           \
31473       ((CHANNEL) == TIM_CHANNEL_3)))            \
31474  ||                                             \
31475       (((INSTANCE) == TIM8) &&                  \
31476       (((CHANNEL) == TIM_CHANNEL_1) ||          \
31477       ((CHANNEL) == TIM_CHANNEL_2) ||           \
31478       ((CHANNEL) == TIM_CHANNEL_3)))            \
31479     ||                                          \
31480     (((INSTANCE) == TIM15) &&                   \
31481       ((CHANNEL) == TIM_CHANNEL_1))             \
31482     ||                                          \
31483     (((INSTANCE) == TIM16) &&                   \
31484      ((CHANNEL) == TIM_CHANNEL_1))              \
31485     ||                                          \
31486     (((INSTANCE) == TIM17) &&                   \
31487      ((CHANNEL) == TIM_CHANNEL_1)))
31488 
31489 /****************** TIM Instances : supporting counting mode selection ********/
31490 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
31491   (((INSTANCE) == TIM1)    || \
31492    ((INSTANCE) == TIM2)    || \
31493    ((INSTANCE) == TIM3)    || \
31494    ((INSTANCE) == TIM4)    || \
31495    ((INSTANCE) == TIM5)    || \
31496    ((INSTANCE) == TIM8))
31497 
31498 /****************** TIM Instances : supporting repetition counter *************/
31499 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
31500   (((INSTANCE) == TIM1)    || \
31501    ((INSTANCE) == TIM8)    || \
31502    ((INSTANCE) == TIM15)   || \
31503    ((INSTANCE) == TIM16)   || \
31504    ((INSTANCE) == TIM17))
31505 
31506 /****************** TIM Instances : supporting clock division *****************/
31507 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
31508   (((INSTANCE) == TIM1)    || \
31509    ((INSTANCE) == TIM2)    || \
31510    ((INSTANCE) == TIM3)    || \
31511    ((INSTANCE) == TIM4)    || \
31512    ((INSTANCE) == TIM5)    || \
31513    ((INSTANCE) == TIM8)    || \
31514    ((INSTANCE) == TIM15)   || \
31515    ((INSTANCE) == TIM16)   || \
31516    ((INSTANCE) == TIM17))
31517 /****************** TIM Instances : supporting external clock mode 1 for ETRF input */
31518 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
31519   (((INSTANCE) == TIM1)    || \
31520    ((INSTANCE) == TIM2)    || \
31521    ((INSTANCE) == TIM3)    || \
31522    ((INSTANCE) == TIM4)    || \
31523    ((INSTANCE) == TIM5)    || \
31524    ((INSTANCE) == TIM8))
31525 
31526 /****************** TIM Instances : supporting external clock mode 2 **********/
31527 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
31528  (((INSTANCE) == TIM1)     || \
31529    ((INSTANCE) == TIM2)    || \
31530    ((INSTANCE) == TIM3)    || \
31531    ((INSTANCE) == TIM4)    || \
31532    ((INSTANCE) == TIM5)    || \
31533    ((INSTANCE) == TIM8))
31534 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
31535 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
31536   (((INSTANCE) == TIM1)    || \
31537    ((INSTANCE) == TIM2)    || \
31538    ((INSTANCE) == TIM3)    || \
31539    ((INSTANCE) == TIM4)    || \
31540    ((INSTANCE) == TIM5)    || \
31541    ((INSTANCE) == TIM8)    || \
31542    ((INSTANCE) == TIM15))
31543 
31544 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
31545 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
31546   (((INSTANCE) == TIM1)    || \
31547    ((INSTANCE) == TIM2)    || \
31548    ((INSTANCE) == TIM3)    || \
31549    ((INSTANCE) == TIM4)    || \
31550    ((INSTANCE) == TIM5)    || \
31551    ((INSTANCE) == TIM8)    || \
31552    ((INSTANCE) == TIM15))
31553 
31554 /****************** TIM Instances : supporting OCxREF clear *******************/
31555 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
31556   (((INSTANCE) == TIM1)    || \
31557    ((INSTANCE) == TIM2)    || \
31558    ((INSTANCE) == TIM3))
31559 /****************** TIM Instances : TIM_32B_COUNTER ***************************/
31560 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
31561   (((INSTANCE) == TIM2)    || \
31562    ((INSTANCE) == TIM5))
31563 
31564 /****************** TIM Instances : TIM_BKIN2 ***************************/
31565 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
31566   (((INSTANCE) == TIM1)    || \
31567    ((INSTANCE) == TIM8))
31568 
31569 /************ TIM Instances : Advanced timers  ********************************/
31570 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
31571                                             ((INSTANCE) == TIM8))
31572 
31573 /****************** TIM Instances : supporting encoder interface **************/
31574 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
31575                                                       ((INSTANCE) == TIM2)      || \
31576                                                       ((INSTANCE) == TIM3)      || \
31577                                                       ((INSTANCE) == TIM4)      || \
31578                                                       ((INSTANCE) == TIM5)      || \
31579                                                       ((INSTANCE) == TIM8))
31580 
31581 /****************** TIM Instances : supporting Hall sensor interface **********/
31582 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1)  || \
31583                                                              ((__INSTANCE__) == TIM2)  || \
31584                                                              ((__INSTANCE__) == TIM3)  || \
31585                                                              ((__INSTANCE__) == TIM4)  || \
31586                                                              ((__INSTANCE__) == TIM5)  || \
31587                                                              ((__INSTANCE__) == TIM8))
31588 
31589 /******************** USART Instances : Synchronous mode **********************/
31590 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
31591                                      ((INSTANCE) == USART2) || \
31592                                      ((INSTANCE) == USART3) || \
31593                                      ((INSTANCE) == USART6))
31594 
31595 /******************** USART Instances : SPI slave mode ************************/
31596 #define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
31597                                               ((INSTANCE) == USART2) || \
31598                                               ((INSTANCE) == USART3) || \
31599                                               ((INSTANCE) == USART6))
31600 
31601 /******************** UART Instances : Asynchronous mode **********************/
31602 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
31603                                     ((INSTANCE) == USART2) || \
31604                                     ((INSTANCE) == USART3) || \
31605                                     ((INSTANCE) == UART4)  || \
31606                                     ((INSTANCE) == UART5)  || \
31607                                     ((INSTANCE) == USART6) || \
31608                                     ((INSTANCE) == UART7)  || \
31609                                     ((INSTANCE) == UART8))
31610 
31611 /******************** UART Instances : FIFO mode.******************************/
31612 #define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
31613                                          ((INSTANCE) == USART2) || \
31614                                          ((INSTANCE) == USART3) || \
31615                                          ((INSTANCE) == UART4)  || \
31616                                          ((INSTANCE) == UART5)  || \
31617                                          ((INSTANCE) == USART6) || \
31618                                          ((INSTANCE) == UART7)  || \
31619                                          ((INSTANCE) == UART8))
31620 
31621 /****************** UART Instances : Auto Baud Rate detection *****************/
31622 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
31623                                                             ((INSTANCE) == USART2) || \
31624                                                             ((INSTANCE) == USART3) || \
31625                                                             ((INSTANCE) == UART4)  || \
31626                                                             ((INSTANCE) == UART5)  || \
31627                                                             ((INSTANCE) == USART6) || \
31628                                                             ((INSTANCE) == UART7)  || \
31629                                                             ((INSTANCE) == UART8))
31630 
31631 /*********************** UART Instances : Driver Enable ***********************/
31632 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
31633                                                   ((INSTANCE) == USART2) || \
31634                                                   ((INSTANCE) == USART3) || \
31635                                                   ((INSTANCE) == UART4)  || \
31636                                                   ((INSTANCE) == UART5)  || \
31637                                                   ((INSTANCE) == USART6) || \
31638                                                   ((INSTANCE) == UART7)  || \
31639                                                   ((INSTANCE) == UART8))
31640 
31641 /********************* UART Instances : Half-Duplex mode **********************/
31642 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
31643                                                ((INSTANCE) == USART2) || \
31644                                                ((INSTANCE) == USART3) || \
31645                                                ((INSTANCE) == UART4)  || \
31646                                                ((INSTANCE) == UART5)  || \
31647                                                ((INSTANCE) == USART6) || \
31648                                                ((INSTANCE) == UART7)  || \
31649                                                ((INSTANCE) == UART8))
31650 
31651 /******************* UART Instances : Hardware Flow control *******************/
31652 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
31653                                            ((INSTANCE) == USART2) || \
31654                                            ((INSTANCE) == USART3) || \
31655                                            ((INSTANCE) == UART4)  || \
31656                                            ((INSTANCE) == UART5)  || \
31657                                            ((INSTANCE) == USART6) || \
31658                                            ((INSTANCE) == UART7)  || \
31659                                            ((INSTANCE) == UART8))
31660 
31661 /************************* UART Instances : LIN mode **************************/
31662 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
31663                                         ((INSTANCE) == USART2) || \
31664                                         ((INSTANCE) == USART3) || \
31665                                         ((INSTANCE) == UART4)  || \
31666                                         ((INSTANCE) == UART5)  || \
31667                                         ((INSTANCE) == USART6) || \
31668                                         ((INSTANCE) == UART7)  || \
31669                                         ((INSTANCE) == UART8))
31670 
31671 /****************** UART Instances : Wake-up from Stop mode *******************/
31672 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
31673                                                     ((INSTANCE) == USART2) || \
31674                                                     ((INSTANCE) == USART3) || \
31675                                                     ((INSTANCE) == UART4)  || \
31676                                                     ((INSTANCE) == UART5)  || \
31677                                                     ((INSTANCE) == USART6) || \
31678                                                    ((INSTANCE) == UART7)  || \
31679                                                     ((INSTANCE) == UART8))
31680 
31681 /************************* UART Instances : IRDA mode *************************/
31682 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
31683                                     ((INSTANCE) == USART2) || \
31684                                     ((INSTANCE) == USART3) || \
31685                                     ((INSTANCE) == UART4)  || \
31686                                     ((INSTANCE) == UART5)  || \
31687                                     ((INSTANCE) == USART6) || \
31688                                     ((INSTANCE) == UART7)  || \
31689                                     ((INSTANCE) == UART8))
31690 
31691 
31692 /********************* USART Instances : Smard card mode **********************/
31693 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
31694                                          ((INSTANCE) == USART2) || \
31695                                          ((INSTANCE) == USART3) || \
31696                                          ((INSTANCE) == USART6))
31697 
31698 
31699 /****************************** IWDG Instances ********************************/
31700 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == IWDG1) || ((INSTANCE) == IWDG2))
31701 
31702 /****************************** USB Instances ********************************/
31703 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
31704 
31705 /****************************** WWDG Instances ********************************/
31706 
31707 #define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG1)
31708 
31709 /****************************** MDIOS Instances ********************************/
31710 #define IS_MDIOS_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == MDIOS)
31711 
31712 /****************************** CEC Instances *********************************/
31713 #define IS_CEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CEC)
31714 
31715 /****************************** SAI Instances ********************************/
31716 #define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
31717                     ((INSTANCE) == SAI1_Block_B) || \
31718                      ((INSTANCE) == SAI2_Block_A) || \
31719                      ((INSTANCE) == SAI2_Block_B) || \
31720                      ((INSTANCE) == SAI3_Block_A) || \
31721                      ((INSTANCE) == SAI3_Block_B) || \
31722                      ((INSTANCE) == SAI4_Block_A) || \
31723                      ((INSTANCE) == SAI4_Block_B))
31724 
31725 /****************************** SPDIFRX Instances ********************************/
31726 #define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)
31727 
31728 /******************************* BSEC VERSION ********************************/
31729 #define BSEC_VERSION(INSTANCE) ((INSTANCE)->VER)
31730 
31731 /******************************* TZPC VERSION ********************************/
31732 #define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER)
31733 
31734 /******************************* FMC VERSION ********************************/
31735 #define FMC_VERSION(INSTANCE) ((INSTANCE)->VERR)
31736 
31737 /******************************* SYSCFG VERSION ********************************/
31738 #define SYSCFG_VERSION(INSTANCE) ((INSTANCE)->VERR)
31739 
31740 /******************************* ETHERNET VERSION ********************************/
31741 #define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR)
31742 
31743 
31744 /******************************* SYSCFG VERSION ********************************/
31745 #define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR)
31746 
31747 /******************************* PWR VERSION ********************************/
31748 #define PWR_VERSION(INSTANCE) ((INSTANCE)->VER)
31749 
31750 /******************************* RCC VERSION ********************************/
31751 #define RCC_VERSION(INSTANCE) ((INSTANCE)->VERR)
31752 
31753 /******************************* HDP VERSION ********************************/
31754 #define HDP_VERSION(INSTANCE) ((INSTANCE)->VERR)
31755 
31756 /******************************* IPCC VERSION ********************************/
31757 #define IPCC_VERSION(INSTANCE) ((INSTANCE)->VER)
31758 
31759 /******************************* HSEM VERSION ********************************/
31760 #define HSEM_VERSION(INSTANCE) ((INSTANCE)->VERR)
31761 
31762 /******************************* GPIO VERSION ********************************/
31763 #define GPIO_VERSION(INSTANCE) ((INSTANCE)->VERR)
31764 
31765 /******************************* DMA VERSION ********************************/
31766 #define DMA_VERSION(INSTANCE) ((INSTANCE)->VERR)
31767 
31768 /******************************* DMAMUX VERSION ********************************/
31769 #define DMAMUX_VERSION(INSTANCE) ((INSTANCE)->VERR)
31770 
31771 /******************************* MDMA VERSION ********************************/
31772 #define MDMA_VERSION(INSTANCE) ((INSTANCE)->VERR)
31773 
31774 /******************************* TAMP VERSION ********************************/
31775 #define TAMP_VERSION(INSTANCE) ((INSTANCE)->VERR)
31776 
31777 /******************************* RTC VERSION ********************************/
31778 #define RTC_VERSION(INSTANCE) ((INSTANCE)->VERR)
31779 
31780 /******************************* SDMMC VERSION ********************************/
31781 #define SDMMC_VERSION(INSTANCE) ((INSTANCE)->VERR)
31782 
31783 /******************************* QUADSPI VERSION ********************************/
31784 #define QUADSPI_VERSION(INSTANCE) ((INSTANCE)->VERR)
31785 
31786 /******************************* CRC VERSION ********************************/
31787 #define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR)
31788 
31789 /******************************* RNG VERSION ********************************/
31790 #define RNG_VERSION(INSTANCE) ((INSTANCE)->VER)
31791 
31792 /******************************* HASH VERSION ********************************/
31793 #define HASH_VERSION(INSTANCE) ((INSTANCE)->VER)
31794 
31795 
31796 /******************************* DCMI VERSION ********************************/
31797 #define DCMI_VERSION(INSTANCE) ((INSTANCE)->VERR)
31798 
31799 /******************************* CEC VERSION ********************************/
31800 #define CEC_VERSION(INSTANCE) ((INSTANCE)->VERR)
31801 
31802 /******************************* LPTIM VERSION ********************************/
31803 #define LPTIM_VERSION(INSTANCE) ((INSTANCE)->VERR)
31804 
31805 /******************************* TIM VERSION ********************************/
31806 #define TIM_VERSION(INSTANCE) ((INSTANCE)->VERR)
31807 
31808 /******************************* IWDG VERSION ********************************/
31809 #define IWDG_VERSION(INSTANCE) ((INSTANCE)->VERR)
31810 
31811 /******************************* WWDG VERSION ********************************/
31812 #define WWDG_VERSION(INSTANCE) ((INSTANCE)->VERR)
31813 
31814 /******************************* DFSDM VERSION ********************************/
31815 #define DFSDM_VERSION(INSTANCE) ((INSTANCE)->VERR)
31816 
31817 /******************************* SAI VERSION ********************************/
31818 #define SAI_VERSION(INSTANCE) ((INSTANCE)->VERR)
31819 
31820 /******************************* MDIOS VERSION ********************************/
31821 #define MDIOS_VERSION(INSTANCE) ((INSTANCE)->VERR)
31822 
31823 /******************************* I2C VERSION ********************************/
31824 #define I2C_VERSION(INSTANCE) ((INSTANCE)->VERR)
31825 
31826 /******************************* USART VERSION ********************************/
31827 #define USART_VERSION(INSTANCE) ((INSTANCE)->VERR)
31828 
31829 /******************************* SPDIFRX VERSION ********************************/
31830 #define SPDIFRX_VERSION(INSTANCE) ((INSTANCE)->VERR)
31831 
31832 /******************************* SPI VERSION ********************************/
31833 #define SPI_VERSION(INSTANCE) ((INSTANCE)->VERR)
31834 
31835 /******************************* ADC VERSION ********************************/
31836 #define ADC_VERSION(INSTANCE) ((INSTANCE)->VERR)
31837 
31838 /******************************* DLYB VERSION ********************************/
31839 #define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR)
31840 
31841 /******************************* DAC VERSION ********************************/
31842 #define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER)
31843 
31844 /******************************* DSI VERSION ********************************/
31845 #define DSI_VERSION(INSTANCE) ((INSTANCE)->VERR)
31846 
31847 /******************************* USBPHYC VERSION ********************************/
31848 #define USBPHYC_VERSION(INSTANCE) ((INSTANCE)->VERR)
31849 
31850 /******************************* DEVICE VERSION ********************************/
31851 #define DEVICE_REVISION() (((DBGMCU->IDCODE) & (DBGMCU_IDCODE_REV_ID_Msk)) >> DBGMCU_IDCODE_REV_ID_Pos)
31852 #define IS_DEVICE_REV_B() (DEVICE_REVISION() == 0x2000)
31853 
31854 /******************************* DEVICE ID  ************************************/
31855 #define DEVICE_ID() ((DBGMCU->IDCODE) & (DBGMCU_IDCODE_DEV_ID_Msk))
31856 
31857 /**
31858   * @brief  Check whether platform is engineering boot mode
31859   * @param  None
31860   * @retval TRUE or FALSE
31861   */
31862 #define IS_ENGINEERING_BOOT_MODE()   (((SYSCFG->BOOTR) & (SYSCFG_BOOTR_BOOT2|SYSCFG_BOOTR_BOOT1|SYSCFG_BOOTR_BOOT0)) == (SYSCFG_BOOTR_BOOT2))
31863 
31864 
31865  /**
31866   * @}
31867   */
31868 
31869 /**
31870   * @}
31871   */
31872 
31873 #ifdef __cplusplus
31874 }
31875 #endif /* __cplusplus */
31876 
31877 #endif /* __STM32MP157Axx_CA7_H */
31878 
31879 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
31880