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Searched defs:VALUE (Results 1 – 25 of 33) sorted by relevance

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/device/soc/st/stm32f407zg/uniproton/board/common/STM32F4xx_StdPeriph_Driver/inc/
Dstm32f4xx_rcc.h92 #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63) argument
93 #define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) argument
94 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) ==… argument
95 #define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15)) argument
97 #define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) argument
98 #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) argument
99 #define IS_RCC_PLLI2SM_VALUE(VALUE) ((VALUE) <= 63) argument
101 #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) argument
102 #define IS_RCC_PLLSAIN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) argument
103 #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) argument
[all …]
Dstm32f4xx_wwdg.h67 #define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F) argument
Dstm32f4xx_rtc.h357 #define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF) argument
430 #define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20) argument
482 #define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF) argument
Dstm32f4xx_dac.h150 #define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \ argument
Dstm32f4xx_sai.h463 #define IS_SAI_BLOCK_MUTE_VALUE(VALUE) (((VALUE) == SAI_ZeroValue) || \ argument
/device/soc/hisilicon/common/platform/wifi/hi3881v100/adapter/
Dhdf_wlan_sdio_adapt.c56 #define REG_WRITE(ADDR, VALUE) \ argument
68 #define REG_SET_BITS(ADDR, VALUE) … argument
80 #define REG_WRITE(ADDR, VALUE) \ argument
87 #define REG_SET_BITS(ADDR, VALUE) … argument
/device/soc/hpmicro/sdk/hpm_sdk/soc/ip/
Dhpm_gpio_regs.h14 __R uint32_t VALUE; /* 0x0: GPIO input value */ member
18 __RW uint32_t VALUE; /* 0x100: GPIO output value */ member
24 __RW uint32_t VALUE; /* 0x200: GPIO direction value */ member
30 __W uint32_t VALUE; /* 0x300: GPIO interrupt flag value */ member
34 __RW uint32_t VALUE; /* 0x400: GPIO interrupt enable value */ member
40 __RW uint32_t VALUE; /* 0x500: GPIO interrupt polarity value */ member
46 __RW uint32_t VALUE; /* 0x600: GPIO interrupt type value */ member
52 __RW uint32_t VALUE; /* 0x700: GPIO interrupt asynchronous value */ member
58 __RW uint32_t VALUE; /* 0x800: GPIO dual edge interrupt enable value */ member
/device/soc/st/common/platform/stm32mp1xx_hal/STM32MP1xx_HAL_Driver/Inc/
Dstm32mp1xx_hal_dfsdm_ex.h69 #define IS_DFSDM_CHANNEL_SKIPPING_VALUE(VALUE) ((VALUE) < 64U) argument
Dstm32mp1xx_hal_rcc.h498 #define IS_RCC_RTC_HSEDIV(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 64)) argument
798 #define IS_RCC_PLLM1_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 64)) argument
800 #define IS_RCC_PLLN1_INT_VALUE(VALUE) ((25 <= (VALUE)) && ((VALUE) <= 100)) argument
801 #define IS_RCC_PLLN1_FRAC_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 512)) argument
802 #define IS_RCC_PLLP1_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128)) argument
803 #define IS_RCC_PLLQ1_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128)) argument
804 #define IS_RCC_PLLR1_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128)) argument
812 #define IS_RCC_PLLM2_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 64)) argument
814 #define IS_RCC_PLLN2_INT_VALUE(VALUE) ((25 <= (VALUE)) && ((VALUE) <= 100)) argument
815 #define IS_RCC_PLLN2_FRAC_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 512)) argument
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Dstm32mp1xx_hal_sai_ex.h86 #define IS_SAI_PDM_MIC_DELAY(VALUE) ((VALUE) <= 7U) argument
Dstm32mp1xx_hal_dfsdm.h740 #define IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 838860… argument
741 #define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1FU) argument
742 #define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFFU) argument
775 #define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 838860… argument
776 #define IS_DFSDM_BREAK_SIGNALS(VALUE) ((VALUE) <= 0xFU) argument
Dstm32mp1xx_hal_dac_ex.h130 #define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \ argument
Dstm32mp1xx_hal_sai.h851 #define IS_SAI_BLOCK_MCK_OVERSAMPLING(VALUE) (((VALUE) == SAI_MCK_OVERSAMPLING_DISABLE) || \ argument
854 #define IS_SAI_PDM_MIC_PAIRS_NUMBER(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 4U)) argument
895 #define IS_SAI_BLOCK_MCK_OUTPUT(VALUE) (((VALUE) == SAI_MCK_OUTPUT_ENABLE) || \ argument
906 #define IS_SAI_BLOCK_MUTE_VALUE(VALUE) (((VALUE) == SAI_ZERO_VALUE) || \ argument
/device/soc/st/stm32f4xx/sdk/Drivers/STM32F4xx_HAL_Driver/Inc/
Dstm32f4xx_hal_flash_ex.h813 #define IS_FLASH_TYPEERASE(VALUE)(((VALUE) == FLASH_TYPEERASE_SECTORS) || \ argument
821 #define IS_WRPSTATE(VALUE)(((VALUE) == OB_WRPSTATE_DISABLE) || \ argument
824 #define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP|OPTIONBYTE_RDP|OPTIONBYTE_USER|OPTIONBYTE_… argument
844 #define IS_PCROPSTATE(VALUE)(((VALUE) == OB_PCROP_STATE_DISABLE) || \ argument
852 #define IS_OBEX(VALUE)(((VALUE) == OPTIONBYTE_PCROP) || \ argument
860 #define IS_OBEX(VALUE)(((VALUE) == OPTIONBYTE_PCROP)) argument
Dstm32f4xx_hal_dfsdm.h978 #define IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 838860… argument
979 #define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1FU) argument
980 #define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFFU) argument
1022 #define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 838860… argument
1023 #define IS_DFSDM_BREAK_SIGNALS(VALUE) ((VALUE) <= 0x0FU) argument
Dstm32f4xx_hal_rcc_ex.h6854 #define IS_RCC_PLLN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U)) argument
6855 #define IS_RCC_PLLI2SN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U)) argument
6889 #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) argument
6893 #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U)) argument
6895 #define IS_RCC_PLLSAIN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U)) argument
6897 #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U)) argument
6899 #define IS_RCC_PLLSAIR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) argument
6901 #define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U)) argument
6903 #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U)) argument
6905 #define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\ argument
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Dstm32f4xx_hal_rcc.h1412 #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63U) argument
1414 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE)… argument
1416 #define IS_RCC_PLLQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U)) argument
1438 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU) argument
Dstm32f4xx_hal_flash.h393 #define IS_FLASH_TYPEPROGRAM(VALUE)(((VALUE) == FLASH_TYPEPROGRAM_BYTE) || \ argument
Dstm32f4xx_hal_rtc_ex.h975 #define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20U) argument
983 #define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FFU) argument
/device/soc/hisilicon/hi3861v100/sdk_liteos/third_party/lwip_sack/include/lwip/
Dlwipopts_dev.h29 #define VALUE(x) VALUE_TO_STRING(x) macro
/device/soc/hpmicro/sdk/hpm_sdk/soc/HPM6280/
Dhpm_sysctl_regs.h16 __RW uint32_t VALUE; /* 0x800: Group setting */ member
23 __RW uint32_t VALUE; /* 0x840: Group setting */ member
30 __RW uint32_t VALUE; /* 0x900: Affiliate of Group */ member
36 __RW uint32_t VALUE; /* 0x920: Retention Contol */ member
/device/qemu/arm_mps2_an386/liteos_m/board/driver/net/
Dlan9118_eth_drv.c70 #define SET_BIT_FIELD(WORD, BIT_MASK, BIT_OFFSET, VALUE) \ argument
77 #define CLR_BIT_FIELD(WORD, BIT_MASK, BIT_OFFSET, VALUE) \ argument
/device/soc/hpmicro/sdk/hpm_sdk/soc/HPM6750/
Dhpm_sysctl_regs.h16 __RW uint32_t VALUE; /* 0x800: Goup setting */ member
23 __RW uint32_t VALUE; /* 0x840: Goup setting */ member
30 __RW uint32_t VALUE; /* 0x900: Affiliate of Group */ member
36 __RW uint32_t VALUE; /* 0x920: Retention Contol */ member
/device/soc/hpmicro/sdk/hpm_sdk/soc/HPM6360/
Dhpm_sysctl_regs.h16 __RW uint32_t VALUE; /* 0x800: Group setting */ member
23 __RW uint32_t VALUE; /* 0x900: Affiliate of Group */ member
30 __RW uint32_t VALUE; /* 0x920: Retention Contol */ member
/device/soc/hpmicro/sdk/hpm_sdk/soc/HPM5361/
Dhpm_sysctl_regs.h16 __RW uint32_t VALUE; /* 0x800: Group setting */ member
23 __RW uint32_t VALUE; /* 0x900: Affiliate of Group */ member
30 __RW uint32_t VALUE; /* 0x920: Retention Contol */ member

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