1 // Copyright (C) 2022 Beken Corporation 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #pragma once 16 17 #ifdef __cplusplus 18 extern "C" { 19 #endif 20 21 22 typedef volatile struct { 23 /* REG_0x00 */ 24 union { 25 struct { 26 uint32_t rgb_int_en: 2; /**<bit[0-1] rgb display interrupt enable */ 27 uint32_t i8080_int_en: 2; /**< i8080 display interrupt enable */ 28 uint32_t rgb_sof: 1; /**< */ 29 uint32_t rgb_eof: 1; /**< */ 30 uint32_t i8080_sof: 1; /**< 8080 display output start of frame */ 31 uint32_t i8080_eof: 1; /**< 8080 display output end of frame */ 32 uint32_t wr_thrd: 10; /**rgb fifo wr thrd */ 33 uint32_t rd_thrd: 10; /**< rgb fifo rd thrd */ 34 uint32_t disconti_mode: 1; /**< open in 20mhz, defult 1 */ 35 uint32_t reserved: 3; 36 }; 37 uint32_t v; 38 } display_int; 39 40 /* REG_0x01 */ 41 union { 42 struct { 43 uint32_t x_pixel: 11; /**< bit[0:10] */ 44 uint32_t dclk_rev: 1; 45 uint32_t y_pixel: 11; /**< bit[12:22] */ 46 uint32_t str_fifo_clr: 1; /**< bit[23] */ 47 uint32_t rgb_disp_on : 1; /**< bit[24] rgb modle enable */ 48 uint32_t rgb_on: 1; /**< bit[25] */ 49 uint32_t lcd_display_on: 1; /**< bit[26] Rgb output signal. */ 50 uint32_t rgb_clk_div: 5; /**< bit[31:27] rgb_clk_div + 1 */ 51 }; 52 uint32_t v; 53 } status; 54 55 /* REG_0x02 */ 56 union { 57 struct { 58 uint32_t rgb_dat: 16;/**< bit[0:15] */ 59 uint32_t reserved: 16; 60 }; 61 uint32_t v; 62 } rgb_fifo; 63 64 /* REG_0x03 */ 65 union { 66 struct { 67 uint32_t hsync_back_porch: 8; /**< bit[0:7] */ 68 uint32_t hsync_front_porch: 7; 69 uint32_t vsync_back_porch: 5; 70 uint32_t vsync_front_porch: 7; 71 uint32_t reserved: 1; 72 uint32_t yuv_sel: 3; 73 }; 74 uint32_t v; 75 } hsync_vsync; 76 77 /* REG_0x04 */ 78 union { 79 struct { 80 uint32_t i8080_disp_en: 1; /**< bit[0] */ 81 uint32_t i8080_dat_on: 1; /**< bit[1] */ 82 uint32_t i8080_fifo_mode: 1; /**< bit[2] 0:when i8080_disp_en=0, invalid write fifo, 1:valid whenever time*/ 83 uint32_t i8080_fifo_clr: 1; /**< bit[3] */ 84 uint32_t i8080_cmdfifo_clr: 1; /**< bit[4] */ 85 uint32_t reset_sleep_in: 1; /**< bit[5] */ 86 uint32_t no_use1: 2; /**< bit[6:7] */ 87 uint32_t tik_cnt: 2; /**<bit[8:9]0：8clk；1：6clk；2：4clk；3：2clk */ 88 uint32_t no_use2: 2; 89 uint32_t i8080_1ms_count: 9; /**< bit[12:20] */ 90 uint32_t reservsed: 11; 91 }; 92 uint32_t v; 93 } i8080_config; 94 95 /* REG_0x05 */ 96 union { 97 struct { 98 uint32_t i8080_cmd_fifo: 16; /**< bit[15: 0] i8080 command fifo */ 99 uint32_t reserved: 16; 100 }; 101 uint32_t v; 102 } i8080_cmd_fifo; 103 104 /* REG_0x06 */ 105 union { 106 struct { 107 uint32_t i8080_dat_fifo: 16; /**bit[15: 0] */ 108 uint32_t reserved: 16; /**< i8080 data fifo */ 109 }; 110 uint32_t v; 111 } i8080_dat_fifo; 112 113 /* REG_0x07 */ 114 union { 115 struct { 116 uint32_t dat_wr_thrd: 8; /**< bit[0:7 i8080 rgb fifo wr thrd */ 117 uint32_t cmd_wr_thrd: 8; /**< i8080 cmd fifo wr thrd */ 118 uint32_t dat_rd_thrd: 8; /**<i8080 dat fifo rd thrd */ 119 uint32_t cmd_rd_thrd: 8; /**< i8080 cmd fifo rd thrd */ 120 }; 121 uint32_t v; 122 } i8080thrd; 123 } lcd_disp_hw_t; 124 125 126 #ifdef __cplusplus 127 } 128 #endif 129 130