1 // SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
2 /*
3 *
4 * (C) COPYRIGHT 2014-2021 ARM Limited. All rights reserved.
5 *
6 * This program is free software and is provided to you under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation, and any use by you of this program is subject to the terms
9 * of such GNU license.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, you can access it online at
18 * http://www.gnu.org/licenses/gpl-2.0.html.
19 *
20 */
21
22 /*
23 * Base kernel property query backend APIs
24 */
25
26 #include <mali_kbase.h>
27 #include <device/mali_kbase_device.h>
28 #include <backend/gpu/mali_kbase_pm_internal.h>
29 #include <backend/gpu/mali_kbase_cache_policy_backend.h>
30 #include <mali_kbase_hwaccess_gpuprops.h>
31
kbase_backend_gpuprops_get(struct kbase_device * kbdev,struct kbase_gpuprops_regdump * regdump)32 int kbase_backend_gpuprops_get(struct kbase_device *kbdev,
33 struct kbase_gpuprops_regdump *regdump)
34 {
35 int i;
36 struct kbase_gpuprops_regdump registers;
37
38 /* Fill regdump with the content of the relevant registers */
39 registers.gpu_id = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_ID));
40
41 registers.l2_features = kbase_reg_read(kbdev,
42 GPU_CONTROL_REG(L2_FEATURES));
43 registers.core_features = 0;
44 #if !MALI_USE_CSF
45 /* TGOx */
46 registers.core_features = kbase_reg_read(kbdev,
47 GPU_CONTROL_REG(CORE_FEATURES));
48 #else /* !MALI_USE_CSF */
49 if (!(((registers.gpu_id & GPU_ID2_PRODUCT_MODEL) ==
50 GPU_ID2_PRODUCT_TDUX) ||
51 ((registers.gpu_id & GPU_ID2_PRODUCT_MODEL) ==
52 GPU_ID2_PRODUCT_TODX)))
53 registers.core_features =
54 kbase_reg_read(kbdev, GPU_CONTROL_REG(CORE_FEATURES));
55 #endif /* MALI_USE_CSF */
56 registers.tiler_features = kbase_reg_read(kbdev,
57 GPU_CONTROL_REG(TILER_FEATURES));
58 registers.mem_features = kbase_reg_read(kbdev,
59 GPU_CONTROL_REG(MEM_FEATURES));
60 registers.mmu_features = kbase_reg_read(kbdev,
61 GPU_CONTROL_REG(MMU_FEATURES));
62 registers.as_present = kbase_reg_read(kbdev,
63 GPU_CONTROL_REG(AS_PRESENT));
64 #if !MALI_USE_CSF
65 registers.js_present = kbase_reg_read(kbdev,
66 GPU_CONTROL_REG(JS_PRESENT));
67 #else /* !MALI_USE_CSF */
68 registers.js_present = 0;
69 #endif /* !MALI_USE_CSF */
70
71 for (i = 0; i < GPU_MAX_JOB_SLOTS; i++)
72 #if !MALI_USE_CSF
73 registers.js_features[i] = kbase_reg_read(kbdev,
74 GPU_CONTROL_REG(JS_FEATURES_REG(i)));
75 #else /* !MALI_USE_CSF */
76 registers.js_features[i] = 0;
77 #endif /* !MALI_USE_CSF */
78
79 for (i = 0; i < BASE_GPU_NUM_TEXTURE_FEATURES_REGISTERS; i++)
80 registers.texture_features[i] = kbase_reg_read(kbdev,
81 GPU_CONTROL_REG(TEXTURE_FEATURES_REG(i)));
82
83 registers.thread_max_threads = kbase_reg_read(kbdev,
84 GPU_CONTROL_REG(THREAD_MAX_THREADS));
85 registers.thread_max_workgroup_size = kbase_reg_read(kbdev,
86 GPU_CONTROL_REG(THREAD_MAX_WORKGROUP_SIZE));
87 registers.thread_max_barrier_size = kbase_reg_read(kbdev,
88 GPU_CONTROL_REG(THREAD_MAX_BARRIER_SIZE));
89 registers.thread_features = kbase_reg_read(kbdev,
90 GPU_CONTROL_REG(THREAD_FEATURES));
91 registers.thread_tls_alloc = kbase_reg_read(kbdev,
92 GPU_CONTROL_REG(THREAD_TLS_ALLOC));
93
94 registers.shader_present_lo = kbase_reg_read(kbdev,
95 GPU_CONTROL_REG(SHADER_PRESENT_LO));
96 registers.shader_present_hi = kbase_reg_read(kbdev,
97 GPU_CONTROL_REG(SHADER_PRESENT_HI));
98
99 registers.tiler_present_lo = kbase_reg_read(kbdev,
100 GPU_CONTROL_REG(TILER_PRESENT_LO));
101 registers.tiler_present_hi = kbase_reg_read(kbdev,
102 GPU_CONTROL_REG(TILER_PRESENT_HI));
103
104 registers.l2_present_lo = kbase_reg_read(kbdev,
105 GPU_CONTROL_REG(L2_PRESENT_LO));
106 registers.l2_present_hi = kbase_reg_read(kbdev,
107 GPU_CONTROL_REG(L2_PRESENT_HI));
108
109 registers.stack_present_lo = kbase_reg_read(kbdev,
110 GPU_CONTROL_REG(STACK_PRESENT_LO));
111 registers.stack_present_hi = kbase_reg_read(kbdev,
112 GPU_CONTROL_REG(STACK_PRESENT_HI));
113
114 if (registers.gpu_id >= GPU_ID2_PRODUCT_MAKE(11, 8, 5, 2)) {
115 registers.gpu_features_lo = kbase_reg_read(kbdev,
116 GPU_CONTROL_REG(GPU_FEATURES_LO));
117 registers.gpu_features_hi = kbase_reg_read(kbdev,
118 GPU_CONTROL_REG(GPU_FEATURES_HI));
119 } else {
120 registers.gpu_features_lo = 0;
121 registers.gpu_features_hi = 0;
122 }
123
124 if (!kbase_is_gpu_removed(kbdev)) {
125 *regdump = registers;
126 return 0;
127 } else
128 return -EIO;
129 }
130
kbase_backend_gpuprops_get_curr_config(struct kbase_device * kbdev,struct kbase_current_config_regdump * curr_config_regdump)131 int kbase_backend_gpuprops_get_curr_config(struct kbase_device *kbdev,
132 struct kbase_current_config_regdump *curr_config_regdump)
133 {
134 if (WARN_ON(!kbdev) || WARN_ON(!curr_config_regdump))
135 return -EINVAL;
136
137 curr_config_regdump->mem_features = kbase_reg_read(kbdev,
138 GPU_CONTROL_REG(MEM_FEATURES));
139
140 curr_config_regdump->shader_present_lo = kbase_reg_read(kbdev,
141 GPU_CONTROL_REG(SHADER_PRESENT_LO));
142 curr_config_regdump->shader_present_hi = kbase_reg_read(kbdev,
143 GPU_CONTROL_REG(SHADER_PRESENT_HI));
144
145 curr_config_regdump->l2_present_lo = kbase_reg_read(kbdev,
146 GPU_CONTROL_REG(L2_PRESENT_LO));
147 curr_config_regdump->l2_present_hi = kbase_reg_read(kbdev,
148 GPU_CONTROL_REG(L2_PRESENT_HI));
149
150 if (kbase_is_gpu_removed(kbdev))
151 return -EIO;
152
153 return 0;
154
155 }
156
kbase_backend_gpuprops_get_features(struct kbase_device * kbdev,struct kbase_gpuprops_regdump * regdump)157 int kbase_backend_gpuprops_get_features(struct kbase_device *kbdev,
158 struct kbase_gpuprops_regdump *regdump)
159 {
160 u32 coherency_features;
161 int error = 0;
162
163 /* Ensure we can access the GPU registers */
164 kbase_pm_register_access_enable(kbdev);
165
166 coherency_features = kbase_cache_get_coherency_features(kbdev);
167
168 if (kbase_is_gpu_removed(kbdev))
169 error = -EIO;
170
171 regdump->coherency_features = coherency_features;
172
173 kbase_pm_register_access_disable(kbdev);
174
175 return error;
176 }
177
kbase_backend_gpuprops_get_l2_features(struct kbase_device * kbdev,struct kbase_gpuprops_regdump * regdump)178 int kbase_backend_gpuprops_get_l2_features(struct kbase_device *kbdev,
179 struct kbase_gpuprops_regdump *regdump)
180 {
181 if (kbase_hw_has_feature(kbdev, BASE_HW_FEATURE_L2_CONFIG)) {
182 u32 l2_features = kbase_reg_read(kbdev,
183 GPU_CONTROL_REG(L2_FEATURES));
184 u32 l2_config =
185 kbase_reg_read(kbdev, GPU_CONTROL_REG(L2_CONFIG));
186 u32 asn_hash[ASN_HASH_COUNT] = {
187 0,
188 };
189 int i;
190
191 if (kbase_hw_has_feature(kbdev, BASE_HW_FEATURE_ASN_HASH)) {
192 for (i = 0; i < ASN_HASH_COUNT; i++)
193 asn_hash[i] = kbase_reg_read(
194 kbdev, GPU_CONTROL_REG(ASN_HASH(i)));
195 }
196
197 if (kbase_is_gpu_removed(kbdev))
198 return -EIO;
199
200 regdump->l2_features = l2_features;
201 regdump->l2_config = l2_config;
202 for (i = 0; i < ASN_HASH_COUNT; i++)
203 regdump->l2_asn_hash[i] = asn_hash[i];
204 }
205
206 return 0;
207 }
208