1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_efuse.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of eFuse LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_EFUSE EFUSE
47 * @brief eFuse LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_LL_EFUSE_H__
53 #define __GR55xx_LL_EFUSE_H__
54
55 /* Includes ------------------------------------------------------------------*/
56 #include "gr55xx.h"
57
58 #ifdef __cplusplus
59 extern "C" {
60 #endif
61
62 #if defined (EFUSE)
63
64 /**
65 * @defgroup EFUSE_LL_MACRO Defines
66 * @{
67 */
68
69 /* Exported constants --------------------------------------------------------*/
70 /** @defgroup EFUSE_LL_Exported_Constants EFUSE Exported Constants
71 * @{
72 */
73
74 /** @defgroup EFUSE_LL_EC_OPERATION EFUSE Operation Defines
75 * @brief Operation defines which can be used with LL_EFUSE_WriteReg function
76 * @{
77 */
78 #define LL_EFUSE_WRITE_KEYRAM EFUSE_OPER_WRITE_KEYRAM /**< Read fwkay and rootkey from eFuse,
79 and write to keyram */
80 #define LL_EFUSE_READ_TRIM EFUSE_OPER_READ_TRIM /**< Read analog trim from eFuse */
81 #define LL_EFUSE_CRC_CHECK EFUSE_OPER_CRC_CHECK /**< Read the special eFuse addr,
82 and calculate CRC value */
83 #define LL_EFUSE_INIT_CHECK EFUSE_OPER_INIT_CHECK /**< Read the whole eFuse value,
84 and check this value with 0 */
85 #define LL_EFUSE_TEST_READ EFUSE_OPER_RD_TEST_MODE /**< Read eFuse test mode from eFuse */
86 /** @} */
87
88 /** @defgroup EFUSE_LL_EC_GET_FLAG Get Flags Defines
89 * @brief Flags defines which can be used with LL_EFUSE_ReadReg function
90 * @{
91 */
92 #define LL_EFUSE_WRITE_KEYRAM_BUSY EFUSE_STATUS_WRITE_KEYRAM_BUSY /**< Write keyram operation is in processing */
93 #define LL_EFUSE_READ_TRIM_DONE EFUSE_STATUS_READ_TRIM_DONE /**< Read trim from eFuse has done */
94 #define LL_EFUSE_CRC_CHECK_DONE EFUSE_STATUS_CRC_CHECK_DONE /**< eFuse CRC check done */
95 #define LL_EFUSE_CRC_CHECK_SUCCESS EFUSE_STATUS_TRIM_CRC_SUCCESS /**< CRC check success */
96 #define LL_EFUSE_INIT_CHECK_DONE EFUSE_STATUS_INIT_DONE /**< eFuse initial value check done */
97 #define LL_EFUSE_INIT_CHECK_SUCCESS EFUSE_STATUS_INIT_SUCCESS /**< eFuse initial value check success */
98 #define LL_EFUSE_WRITE_DONE EFUSE_STATUS_WRITE_DONE /**< eFuse one word write done */
99 #define LL_EFUSE_TEST_DONE EFUSE_STATUS_TEST_MODE_DONE /**< Read from eFuse has done in test mode */
100 /** @} */
101
102 /** @defgroup EFUSE_LL_EC_GET_CTL_FLAG Get Power Controller Flags Defines
103 * @brief Flags defines which can be used with LL_EFUSE_ReadReg function
104 * @{
105 */
106 #define LL_EFUSE_PWR_CTL_EN_DONE MCU_SUB_EFUSE_PWR_CTL0_EN_DONE /**< eFuse power enable done */
107 #define LL_EFUSE_PWR_CTL_DIS_DONE MCU_SUB_EFUSE_PWR_CTL0_DIS_DONE /**< eFuse power disable done */
108 /** @} */
109
110 /** @} */
111
112 /* Exported macro ------------------------------------------------------------*/
113 /** @defgroup EFUSE_LL_Exported_Macros EFUSE Exported Macros
114 * @{
115 */
116
117 /** @defgroup EFUSE_LL_EM_WRITE_READ Common Write and read registers Macros
118 * @{
119 */
120
121 /**
122 * @brief Write a value in eFuse register
123 * @param __instance__ eFuse instance
124 * @param __REG__ Register to be written
125 * @param __VALUE__ Value to be written in the register
126 * @retval None
127 */
128 #define LL_EFUSE_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
129
130 /**
131 * @brief Read a value in eFuse register
132 * @param __instance__ eFuse instance
133 * @param __REG__ Register to be read
134 * @retval Register value
135 */
136 #define LL_EFUSE_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
137
138 /** @} */
139
140 /** @} */
141
142 /** @} */
143
144 /* Exported functions --------------------------------------------------------*/
145 /** @defgroup EFUSE_LL_DRIVER_FUNCTIONS Functions
146 * @{
147 */
148
149 /** @defgroup EFUSE_LL_EF_Configuration Configuration functions
150 * @{
151 */
152
153 /**
154 * @brief Set eFuse program time
155 *
156 * Register|BitsName
157 * --------|--------
158 * TPGM | TIME
159 *
160 * @param EFUSEx eFuse instance
161 * @param time This parameter can be one of the following values: 0 ~ 0xFFF
162 * @retval None
163 */
ll_efuse_set_tpro(efuse_regs_t * EFUSEx,uint32_t time)164 __STATIC_INLINE void ll_efuse_set_tpro(efuse_regs_t *EFUSEx, uint32_t time)
165 {
166 MODIFY_REG(EFUSEx->TPGM, EFUSE_TPGM_TIME, time << EFUSE_TPGM_TIME_Pos);
167 }
168
169 /**
170 * @brief Get eFuse program time
171 *
172 * Register|BitsName
173 * --------|--------
174 * TPGM | TIME
175 *
176 * @param EFUSEx eFuse instance
177 * @retval Returned value can be one of the following values: 0 ~ 0xFFF
178 */
ll_efuse_get_tpro(efuse_regs_t * EFUSEx)179 __STATIC_INLINE uint32_t ll_efuse_get_tpro(efuse_regs_t *EFUSEx)
180 {
181 return (uint32_t)(READ_BITS(EFUSEx->TPGM, EFUSE_TPGM_TIME) >> EFUSE_TPGM_TIME_Pos);
182 }
183
184 /**
185 * @brief Enable read address through APB bus be a main address or backup address
186 *
187 * Register|BitsName
188 * --------|--------
189 * TPGM | MAIN_OR_BACKUP
190 *
191 * @param EFUSEx eFuse instance
192 * @retval None
193 */
ll_efuse_enable_main_backup(efuse_regs_t * EFUSEx)194 __STATIC_INLINE void ll_efuse_enable_main_backup(efuse_regs_t *EFUSEx)
195 {
196 SET_BITS(EFUSEx->TPGM, EFUSE_TPGM_MAIN_OR_BACKUP);
197 }
198
199 /**
200 * @brief Disable read address through APB bus be a main address or backup address
201 *
202 * Register|BitsName
203 * --------|--------
204 * TPGM | MAIN_OR_BACKUP
205 *
206 * @param EFUSEx eFuse instance
207 * @retval None
208 */
ll_efuse_disable_main_backup(efuse_regs_t * EFUSEx)209 __STATIC_INLINE void ll_efuse_disable_main_backup(efuse_regs_t *EFUSEx)
210 {
211 CLEAR_BITS(EFUSEx->TPGM, EFUSE_TPGM_MAIN_OR_BACKUP);
212 }
213
214 /**
215 * @brief Check if read address through APB bus be a main address or backup address is enabled
216 *
217 * Register|BitsName
218 * --------|--------
219 * TPGM | MAIN_OR_BACKUP
220 *
221 * @param EFUSEx eFuse instance
222 * @retval State of bit (1 or 0).
223 */
ll_efuse_is_enabled_main_backup(efuse_regs_t * EFUSEx)224 __STATIC_INLINE uint32_t ll_efuse_is_enabled_main_backup(efuse_regs_t *EFUSEx)
225 {
226 return (READ_BITS(EFUSEx->TPGM, EFUSE_TPGM_MAIN_OR_BACKUP) == (EFUSE_TPGM_MAIN_OR_BACKUP));
227 }
228
229 /**
230 * @brief Set CRC check length
231 *
232 * Register|BitsName
233 * --------|--------
234 * TPGM | CRC_CHECK_LEN
235 *
236 * @param EFUSEx eFuse instance
237 * @param length This parameter can be one of the following values: 1 ~ 60
238 * @retval None
239 */
ll_efuse_set_crc_check_len(efuse_regs_t * EFUSEx,uint32_t length)240 __STATIC_INLINE void ll_efuse_set_crc_check_len(efuse_regs_t *EFUSEx, uint32_t length)
241 {
242 MODIFY_REG(EFUSEx->TPGM, EFUSE_TPGM_CRC_CHECK_LEN, length << EFUSE_TPGM_CRC_CHECK_LEN_Pos);
243 }
244
245 /**
246 * @brief Get CRC check length
247 *
248 * Register|BitsName
249 * --------|--------
250 * TPGM | CRC_CHECK_LEN
251 *
252 * @param EFUSEx eFuse instance
253 * @retval Returned value can be one of the following values: 1 ~ 60
254 */
ll_efuse_get_crc_check_len(efuse_regs_t * EFUSEx)255 __STATIC_INLINE uint32_t ll_efuse_get_crc_check_len(efuse_regs_t *EFUSEx)
256 {
257 return (uint32_t)(READ_BITS(EFUSEx->TPGM, EFUSE_TPGM_CRC_CHECK_LEN) >> EFUSE_TPGM_CRC_CHECK_LEN_Pos);
258 }
259
260 /**
261 * @brief Set the interval number of clk cycles between two bit fuse
262 *
263 * Register|BitsName
264 * --------|--------
265 * TPGM | WRITE_INTERVAL
266 *
267 * @param EFUSEx eFuse instance
268 * @param interval This parameter can be one of the following values: 0 ~ 0xFF
269 * @retval None
270 */
ll_efuse_set_interval(efuse_regs_t * EFUSEx,uint32_t interval)271 __STATIC_INLINE void ll_efuse_set_interval(efuse_regs_t *EFUSEx, uint32_t interval)
272 {
273 MODIFY_REG(EFUSEx->TPGM, EFUSE_TPGM_WRITE_INTERVAL, interval << EFUSE_TPGM_WRITE_INTERVAL_Pos);
274 }
275
276 /**
277 * @brief Get the interval number of clk cycles between two bit fuse
278 *
279 * Register|BitsName
280 * --------|--------
281 * TPGM | WRITE_INTERVAL
282 *
283 * @param EFUSEx eFuse instance
284 * @retval Returned value can be one of the following values: 0 ~ 0xFF
285 */
ll_efuse_get_interval(efuse_regs_t * EFUSEx)286 __STATIC_INLINE uint32_t ll_efuse_get_interval(efuse_regs_t *EFUSEx)
287 {
288 return (uint32_t)(READ_BITS(EFUSEx->TPGM, EFUSE_TPGM_WRITE_INTERVAL) >> EFUSE_TPGM_WRITE_INTERVAL_Pos);
289 }
290
291 /**
292 * @brief Enable eFuse PGENB sigal
293 *
294 * Register|BitsName
295 * --------|--------
296 * PGENB | PGENB_SIG
297 *
298 * @param EFUSEx eFuse instance
299 * @retval None
300 */
ll_efuse_enable_pgenb(efuse_regs_t * EFUSEx)301 __STATIC_INLINE void ll_efuse_enable_pgenb(efuse_regs_t *EFUSEx)
302 {
303 SET_BITS(EFUSEx->PGENB, EFUSE_PGENB_SIG);
304 }
305
306 /**
307 * @brief Disable eFuse PGENB sigal
308 *
309 * Register|BitsName
310 * --------|--------
311 * PGENB | PGENB_SIG
312 *
313 * @param EFUSEx eFuse instance
314 * @retval None
315 */
ll_efuse_disable_pgenb(efuse_regs_t * EFUSEx)316 __STATIC_INLINE void ll_efuse_disable_pgenb(efuse_regs_t *EFUSEx)
317 {
318 CLEAR_BITS(EFUSEx->PGENB, EFUSE_PGENB_SIG);
319 }
320
321 /**
322 * @brief Check if eFuse PGENB sigal is enabled
323 *
324 * Register|BitsName
325 * --------|--------
326 * PGENB | PGENB_SIG
327 *
328 * @param EFUSEx eFuse instance
329 * @retval State of bit (1 or 0).
330 */
ll_efuse_is_enabled_pgenb(efuse_regs_t * EFUSEx)331 __STATIC_INLINE uint32_t ll_efuse_is_enabled_pgenb(efuse_regs_t *EFUSEx)
332 {
333 return (READ_BITS(EFUSEx->PGENB, EFUSE_PGENB_SIG) == (EFUSE_PGENB_SIG));
334 }
335
336 /**
337 * @brief Get test mode
338 * @note This bit should be read only.
339 *
340 * Register|BitsName
341 * --------|--------
342 * TEST_MODE | TEST_MODE
343 *
344 * @param EFUSEx eFuse instance
345 * @retval Returned value can be one of the following values: 0xFFFF
346 */
ll_efuse_get_test_mode(efuse_regs_t * EFUSEx)347 __STATIC_INLINE uint32_t ll_efuse_get_test_mode(efuse_regs_t *EFUSEx)
348 {
349 return (uint32_t)(READ_BITS(EFUSEx->TEST_MODE, EFUSE_TEST_MODE));
350 }
351
352 /**
353 * @brief Set eFuse operation mode
354 *
355 * Register|BitsName
356 * --------|--------
357 * OPERATION | WRITE_KEYRAM
358 * OPERATION | INIT_CHECK
359 * OPERATION | CRC_CHECK
360 * OPERATION | READ_TRIM
361 * OPERATION | RD_TEST_MODE
362 *
363 * @param EFUSEx eFuse instance
364 * @param mode This parameter can be one of the following values:
365 * @arg @ref LL_EFUSE_WRITE_KEYRAM
366 * @arg @ref LL_EFUSE_READ_TRIM
367 * @arg @ref LL_EFUSE_CRC_CHECK
368 * @arg @ref LL_EFUSE_INIT_CHECK
369 * @arg @ref LL_EFUSE_TEST_READ
370 * @retval None
371 */
ll_efuse_set_operation(efuse_regs_t * EFUSEx,uint32_t mode)372 __STATIC_INLINE void ll_efuse_set_operation(efuse_regs_t *EFUSEx, uint32_t mode)
373 {
374 WRITE_REG(EFUSEx->OPERATION, mode);
375 }
376
377 /**
378 * @brief Check active flag
379 *
380 * Register|BitsName
381 * --------|--------
382 * STAT | WRITE_KEYRAM_BUSY
383 * STAT | READ_TRIM_DONE
384 * STAT | TRIM_CRC_SUCCESS
385 * STAT | INIT_DONE
386 * STAT | INIT_SUCCESS
387 * STAT | CRC_CHECK_DONE
388 * STAT | WRITE_DONE
389 * STAT | TEST_MODE_DONE
390 *
391 * @param EFUSEx eFuse instance
392 * @param flag This parameter can be one of the following values:
393 * @arg @ref LL_EFUSE_WRITE_KEYRAM_BUSY
394 * @arg @ref LL_EFUSE_READ_TRIM_DONE
395 * @arg @ref LL_EFUSE_CRC_CHECK_DONE
396 * @arg @ref LL_EFUSE_CRC_CHECK_SUCCESS
397 * @arg @ref LL_EFUSE_INIT_CHECK_DONE
398 * @arg @ref LL_EFUSE_INIT_CHECK_SUCCESS
399 * @arg @ref LL_EFUSE_WRITE_DONE
400 * @arg @ref LL_EFUSE_TEST_DONE
401 * @retval State of bit (1 or 0).
402 */
ll_efuse_is_active_flag(efuse_regs_t * EFUSEx,uint32_t flag)403 __STATIC_INLINE uint32_t ll_efuse_is_active_flag(efuse_regs_t *EFUSEx, uint32_t flag)
404 {
405 return (READ_BITS(EFUSEx->STAT, flag) == (flag));
406 }
407
408 /**
409 * @brief Set key mask
410 *
411 * Register|BitsName
412 * --------|--------
413 * KEY_MASK | KEY_MASK
414 *
415 * @param EFUSEx eFuse instance
416 * @param mask Key mask
417 * @retval None
418 */
ll_efuse_set_key_mask(efuse_regs_t * EFUSEx,uint32_t mask)419 __STATIC_INLINE void ll_efuse_set_key_mask(efuse_regs_t *EFUSEx, uint32_t mask)
420 {
421 WRITE_REG(EFUSEx->KEY_MASK, mask);
422 }
423
424 /**
425 * @brief Get key mask
426 *
427 * Register|BitsName
428 * --------|--------
429 * KEY_MASK | KEY_MASK
430 *
431 * @param EFUSEx eFuse instance
432 * @retval None
433 */
ll_efuse_get_key_mask(efuse_regs_t * EFUSEx)434 __STATIC_INLINE uint32_t ll_efuse_get_key_mask(efuse_regs_t *EFUSEx)
435 {
436 return (uint32_t)(READ_REG(EFUSEx->KEY_MASK));
437 }
438
439 /**
440 * @brief Set CRC check start address
441 * @note The address must be a main info address.
442 *
443 * Register|BitsName
444 * --------|--------
445 * CRC_ADDR | START_CHECK_ADDR
446 *
447 * @param EFUSEx eFuse instance
448 * @param address This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
449 * @retval None
450 */
ll_efuse_set_crc_check_addr(efuse_regs_t * EFUSEx,uint32_t address)451 __STATIC_INLINE void ll_efuse_set_crc_check_addr(efuse_regs_t *EFUSEx, uint32_t address)
452 {
453 WRITE_REG(EFUSEx->CRC_ADDR, address);
454 }
455
456 /**
457 * @brief Get CRC check start address
458 *
459 * Register|BitsName
460 * --------|--------
461 * CRC_ADDR | START_CHECK_ADDR
462 *
463 * @param EFUSEx eFuse instance
464 * @retval Returned value can be one of the following values: 0 ~ 0xFFFFFFFF
465 */
ll_efuse_get_crc_check_addr(efuse_regs_t * EFUSEx)466 __STATIC_INLINE uint32_t ll_efuse_get_crc_check_addr(efuse_regs_t *EFUSEx)
467 {
468 return (uint32_t)(READ_REG(EFUSEx->CRC_ADDR));
469 }
470
471 /**
472 * @brief Get CRC check results
473 *
474 * Register|BitsName
475 * --------|--------
476 * CRC_OUTPUT | OUTPUT_VALUE
477 *
478 * @param EFUSEx eFuse instance
479 * @retval Returned value can be one of the following values: 0 ~ 0xFFFFFFFF
480 */
ll_efuse_get_crc_check_result(efuse_regs_t * EFUSEx)481 __STATIC_INLINE uint32_t ll_efuse_get_crc_check_result(efuse_regs_t *EFUSEx)
482 {
483 return (uint32_t)(READ_REG(EFUSEx->CRC_OUTPUT));
484 }
485
486 /**
487 * @brief Set read trim start address
488 * @note The address must be a main info address.
489 *
490 * Register|BitsName
491 * --------|--------
492 * TRIM_ADDR | START_ADDR
493 *
494 * @param EFUSEx eFuse instance
495 * @param address This parameter can be one of the following values: 0 ~ 0xFFFFFFFF
496 * @retval None
497 */
ll_efuse_set_trim_addr(efuse_regs_t * EFUSEx,uint32_t address)498 __STATIC_INLINE void ll_efuse_set_trim_addr(efuse_regs_t *EFUSEx, uint32_t address)
499 {
500 WRITE_REG(EFUSEx->TRIM_ADDR, address);
501 }
502
503 /**
504 * @brief Get read trim start address
505 *
506 * Register|BitsName
507 * --------|--------
508 * TRIM_ADDR | START_ADDR
509 *
510 * @param EFUSEx eFuse instance
511 * @retval Returned value can be one of the following values: 0 ~ 0xFFFFFFFF
512 */
ll_efuse_get_trim_addr(efuse_regs_t * EFUSEx)513 __STATIC_INLINE uint32_t ll_efuse_get_trim_addr(efuse_regs_t *EFUSEx)
514 {
515 return (uint32_t)(READ_REG(EFUSEx->TRIM_ADDR));
516 }
517
518 /**
519 * @brief Set read trim length
520 *
521 * Register|BitsName
522 * --------|--------
523 * TRIM_LEN | LENGTH
524 *
525 * @param EFUSEx eFuse instance
526 * @param length This parameter can be one of the following values: 1 ~ 14
527 * @retval None
528 */
ll_efuse_set_trim_length(efuse_regs_t * EFUSEx,uint32_t length)529 __STATIC_INLINE void ll_efuse_set_trim_length(efuse_regs_t *EFUSEx, uint32_t length)
530 {
531 WRITE_REG(EFUSEx->TRIM_LEN, length & EFUSE_TRIM_LENGTH);
532 }
533
534 /**
535 * @brief Get read trim length
536 *
537 * Register|BitsName
538 * --------|--------
539 * TRIM_LEN | LENGTH
540 *
541 * @param EFUSEx eFuse instance
542 * @retval Returned value can be one of the following values: 1 ~ 14
543 */
ll_efuse_get_trim_length(efuse_regs_t * EFUSEx)544 __STATIC_INLINE uint32_t ll_efuse_get_trim_length(efuse_regs_t *EFUSEx)
545 {
546 return (uint32_t)(READ_REG(EFUSEx->TRIM_LEN) & EFUSE_TRIM_LENGTH);
547 }
548
549 /**
550 * @brief Get trim value
551 *
552 * Register|BitsName
553 * --------|--------
554 * TRIM[n] | TRIM
555 *
556 * @param EFUSEx eFuse instance
557 * @param indx index of trim value registers: 0 ~ 13
558 * @retval Returned value can be one of the following values: 0 ~ 0xFFFFFFFF
559 */
ll_efuse_get_trim_value(efuse_regs_t * EFUSEx,uint32_t indx)560 __STATIC_INLINE uint32_t ll_efuse_get_trim_value(efuse_regs_t *EFUSEx, uint32_t indx)
561 {
562 return (uint32_t)(READ_REG(EFUSEx->TRIM[indx]));
563 }
564
565 /**
566 * @brief eFuse v1.1 power on.
567 *
568 * Register|BitsName
569 * --------|--------
570 * TPGM | CRC_CHECK_LEN
571 *
572 * @retval None
573 */
ll_efuse_enable_power(efuse_regs_t * EFUSEx)574 __STATIC_INLINE void ll_efuse_enable_power(efuse_regs_t *EFUSEx)
575 {
576 SET_BITS(AON->RF_REG_2, AON_RF_REG_2_EFUSE_VDD_EN);
577 }
578
579 /**
580 * @brief eFuse v1.1 power off.
581 *
582 * Register|BitsName
583 * --------|--------
584 * TPGM | CRC_CHECK_LEN
585 *
586 * @retval None
587 */
ll_efuse_disable_power(efuse_regs_t * EFUSEx)588 __STATIC_INLINE void ll_efuse_disable_power(efuse_regs_t *EFUSEx)
589 {
590 CLEAR_BITS(AON->RF_REG_2, AON_RF_REG_2_EFUSE_VDD_EN);
591 }
592
593 /**
594 * @brief Set Efulse power controller timing pararmeter.
595 *
596 * Register |BitsName
597 * ----------|--------
598 * PWR_DELTA| PWR_DELTA_0
599 * PWR_DELTA| PWR_DELTA_1
600 * PWR_DELTA| PWR_DELTA_2
601 *
602 * @retval None
603 */
ll_efuse_set_controller_power_timing(efuse_regs_t * EFUSEx,uint16_t vddq_0,uint16_t vddq_1,uint16_t vddq_2)604 __STATIC_INLINE void ll_efuse_set_controller_power_timing(efuse_regs_t *EFUSEx, uint16_t vddq_0,
605 uint16_t vddq_1, uint16_t vddq_2)
606 {
607 WRITE_REG(MCU_SUB->EFUSE_PWR_DELTA[0], vddq_0 + (vddq_1 << ITEM_16));
608 WRITE_REG(MCU_SUB->EFUSE_PWR_DELTA[1], vddq_2);
609 }
610
611 /**
612 * @brief Power sequencer begin.
613 *
614 * Register |BitsName
615 * -----------|--------
616 * PWR_CTRL0 | CTRL_ENABLE
617 * PWR_CTRL0 | SEQR_BEGIN
618 *
619 * @retval None
620 */
ll_efuse_enable_controller_power_begin(efuse_regs_t * EFUSEx)621 __STATIC_INLINE void ll_efuse_enable_controller_power_begin(efuse_regs_t *EFUSEx)
622 {
623 WRITE_REG(MCU_SUB->EFUSE_PWR_CTRL[0], MCU_SUB_EFUSE_PWR_CTL0_BGN | MCU_SUB_EFUSE_PWR_CTL0_EN);
624 }
625
626 /**
627 * @brief Power sequencer begin.
628 *
629 * Register |BitsName
630 * -----------|--------
631 * PWR_CTRL0 | CTRL_ENABLE
632 * PWR_CTRL0 | SEQR_STOP
633 *
634 * @retval None
635 */
ll_efuse_enable_controller_power_stop(efuse_regs_t * EFUSEx)636 __STATIC_INLINE void ll_efuse_enable_controller_power_stop(efuse_regs_t *EFUSEx)
637 {
638 WRITE_REG(MCU_SUB->EFUSE_PWR_CTRL[0], MCU_SUB_EFUSE_PWR_CTL0_STP | MCU_SUB_EFUSE_PWR_CTL0_EN);
639 }
640
641 /**
642 * @brief Power sequencer begin.
643 *
644 * Register |BitsName
645 * --------- -|--------
646 * PWR_CTRL0 | CTRL_ENABLE
647 * PWR_CTRL0 | SEQR_BEGIN
648 * PWR_CTRL0 | SEQR_STOP
649 *
650 * @retval None
651 */
ll_efuse_disable_controller_power(efuse_regs_t * EFUSEx)652 __STATIC_INLINE void ll_efuse_disable_controller_power(efuse_regs_t *EFUSEx)
653 {
654 WRITE_REG(MCU_SUB->EFUSE_PWR_CTRL[0], 0);
655 }
656
657 /**
658 * @brief Check power controller active flag
659 *
660 * Register|BitsName
661 * --------|--------
662 * PWR_CTRL1 | EN_DONE
663 * PWR_CTRL1 | DIS_DONE
664 *
665 * @param EFUSEx eFuse instance
666 * @param flag This parameter can be one of the following values:
667 * @arg @ref LL_EFUSE_PWR_CTL_EN_DONE
668 * @arg @ref LL_EFUSE_PWR_CTL_DIS_DONE
669 * @retval State of bit (1 or 0).
670 */
ll_efuse_is_controller_power_flag(efuse_regs_t * EFUSEx,uint32_t flag)671 __STATIC_INLINE uint32_t ll_efuse_is_controller_power_flag(efuse_regs_t *EFUSEx, uint32_t flag)
672 {
673 return (READ_BITS(MCU_SUB->EFUSE_PWR_CTRL[1], flag) == (flag));
674 }
675
676 /** @} */
677
678 /** @} */
679
680 #endif /* EFUSE */
681
682 #ifdef __cplusplus
683 }
684 #endif
685
686 #endif /* __GR55xx_LL_EFUSE_H__ */
687
688 /** @} */
689
690 /** @} */
691
692 /** @} */
693