1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_pwr.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of PWR LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_PWR PWR
47 * @brief PWR LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef GR55xx_LL_PWR_H
53 #define GR55xx_LL_PWR_H
54
55 /* Includes ------------------------------------------------------------------*/
56 #include "gr55xx.h"
57
58 #ifdef __cplusplus
59 extern "C" {
60 #endif
61
62 #if defined(AON)
63
64 /**
65 * @defgroup PWR_LL_MACRO Defines
66 * @{
67 */
68
69 /* Private types -------------------------------------------------------------*/
70 /* Private variables ---------------------------------------------------------*/
71 /* Private constants ---------------------------------------------------------*/
72 /** @defgroup PWR_LL_Private_Constants PWR Private Constants
73 * @{
74 */
75
76 /** @defgroup PWR_LL_PC_EXT_WAKEUP_CTL_LSB External Wakeup Control Low Significant Bit Defines
77 * @{
78 */
79 #define LL_PWR_EXTWKUP_TYPE_LSB (0x01U << AON_EXT_WKUP_CTL_TYPE_Pos) /**< External wakeup level type */
80 #define LL_PWR_EXTWKUP_INVERT_LSB (0x01U << AON_EXT_WKUP_CTL_INVERT_Pos) /**< External wakeup level invert */
81 #define LL_PWR_EXTWKUP_SRC_EN_LSB (0x01U << AON_EXT_WKUP_CTL_SRC_EN_Pos) /**< External wakeup source enable */
82 /** @} */
83
84 /** @} */
85
86 /* Private macros ------------------------------------------------------------*/
87 /** @defgroup PWR_LL_Private_Macro PWR Private Macros
88 * @{
89 */
90
91 /** @defgroup PWR_LL_PM_EXT_WAKEUP_CTL_LSB External Wakeup Control Low Significant Bit Defines
92 * @{
93 */
94
95 /**
96 * @brief PWR_LL_PM_GET_MEM_PWR_MSK PWR Get Memory Power Value Mask
97 */
98 #define LL_PWR_GET_MEM_PWR_MASK(POWER) (((POWER) == LL_PWR_MEM_POWER_OFF) ? 0x0U : \
99 (((POWER) == LL_PWR_MEM_POWER_FULL) ? 0xAAAAAAAAU : 0xFFFFFFFFU))
100
101 /** @} */
102
103 /** @} */
104
105 /* Exported types ------------------------------------------------------------*/
106 /* Exported constants --------------------------------------------------------*/
107 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
108 * @{
109 */
110
111 /** @defgroup PWR_LL_EC_WAKEUP_COND Wakeup Condition
112 * @{
113 */
114 #define LL_PWR_WKUP_COND_EXT AON_PWR_REG01_WAKE_UP_SEL_EXTWKUP /**< External wakeup: AON_GPIO */
115 #define LL_PWR_WKUP_COND_TIMER AON_PWR_REG01_WAKE_UP_SEL_TIMER /**< AON Timer wakeup */
116 #define LL_PWR_WKUP_COND_BLE AON_PWR_REG01_WAKE_UP_SEL_BLE /**< BLE wakeup */
117 #define LL_PWR_WKUP_COND_CALENDAR AON_PWR_REG01_WAKE_UP_SEL_CALENDAR /**< Calendar wakeup */
118 #define LL_PWR_WKUP_COND_BOD_FEDGE AON_PWR_REG01_WAKE_UP_SEL_PMU_BOD_FEDGE /**< PMU Bod falling edge wakeup */
119 #define LL_PWR_WKUP_COND_MSIO_COMP AON_PWR_REG01_WAKE_UP_SEL_MSIO_COMP /**< Msio comparator wakeup */
120 #define LL_PWR_WKUP_COND_ALL AON_PWR_REG01_WAKE_UP_SEL /**< All wakeup sources mask */
121 /** @} */
122
123
124 /** @defgroup PWR_LL_EC_WAKEUP_EVT Wakeup Event
125 * @note Only available on GR5515_C and later version
126 * @{
127 */
128 #define LL_PWR_WKUP_EVENT_BLE AON_SLP_EVENT_SMCOSCEN /**< BLE Timer wakeup event */
129 #define LL_PWR_WKUP_EVENT_TIMER AON_SLP_EVENT_TIMER /**< AON Timer wakeup event */
130 #define LL_PWR_WKUP_EVENT_EXT AON_SLP_EVENT_EXTWKUP /**< External wakeup event: AON_GPIO */
131 #define LL_PWR_WKUP_EVENT_BOD_FEDGE AON_SLP_EVENT_PMU_BOD_FEDGE /**< PMU Bod wakeup event */
132 #define LL_PWR_WKUP_EVENT_MSIO_COMP AON_SLP_EVENT_PMU_MSIO_COMP /**< Msio comparator wakeup event */
133 #define LL_PWR_WKUP_EVENT_WDT AON_SLP_EVENT_WDT_REBOOT /**< AON WDT wakeup event */
134 #define LL_PWR_WKUP_EVENT_CALENDAR AON_SLP_EVENT_CALENDAR_TIMER_ALARM /**< Calendar wakeup event */
135 #define LL_PWR_WKUP_EVENT_ALL (AON_SLP_EVENT_SMCOSCEN | \
136 AON_SLP_EVENT_TIMER | \
137 AON_SLP_EVENT_EXTWKUP | \
138 AON_SLP_EVENT_PMU_BOD_FEDGE | \
139 AON_SLP_EVENT_PMU_MSIO_COMP | \
140 AON_SLP_EVENT_WDT_REBOOT | \
141 AON_SLP_EVENT_CALENDAR_TIMER_ALARM) /**< All event mask */
142 /** @} */
143
144 /** @defgroup PWR_LL_EC_EXTWAKEUP_PIN External Wakeup Pins
145 * @{
146 */
147 #define LL_PWR_EXTWKUP_PIN0 (0x00000001U) /**< WKUP pin 0 : AON_GPIO_PIN0 */
148 #define LL_PWR_EXTWKUP_PIN1 (0x00000002U) /**< WKUP pin 1 : AON_GPIO_PIN1 */
149 #define LL_PWR_EXTWKUP_PIN2 (0x00000004U) /**< WKUP pin 2 : AON_GPIO_PIN2 */
150 #define LL_PWR_EXTWKUP_PIN3 (0x00000008U) /**< WKUP pin 3 : AON_GPIO_PIN3 */
151 #define LL_PWR_EXTWKUP_PIN4 (0x00000010U) /**< WKUP pin 4 : AON_GPIO_PIN4 */
152 #define LL_PWR_EXTWKUP_PIN5 (0x00000020U) /**< WKUP pin 5 : AON_GPIO_PIN5 */
153 #define LL_PWR_EXTWKUP_PIN6 (0x00000040U) /**< WKUP pin 6 : AON_GPIO_PIN6 */
154 #define LL_PWR_EXTWKUP_PIN7 (0x00000080U) /**< WKUP pin 7 : AON_GPIO_PIN7 */
155 #define LL_PWR_EXTWKUP_PIN_ALL (0x000000FFU) /**< WKUP pin all : AON_GPIO_PIN0 ~ AON_GPIO_PIN7 */
156 /** @} */
157
158 /** @defgroup PWR_LL_EC_EXTWAKEUP_TYPE External Wakeup Type
159 * @{
160 */
161 #define LL_PWR_EXTWKUP_TYPE_LOW (LL_PWR_EXTWKUP_INVERT_LSB | LL_PWR_EXTWKUP_TYPE_LSB | \
162 LL_PWR_EXTWKUP_SRC_EN_LSB) /**< Low level wakeup */
163 #define LL_PWR_EXTWKUP_TYPE_HIGH (LL_PWR_EXTWKUP_TYPE_LSB | \
164 LL_PWR_EXTWKUP_SRC_EN_LSB) /**< High level wakeup */
165 #define LL_PWR_EXTWKUP_TYPE_RISING (0x00000000U) /**< Rising edge wakeup */
166 #define LL_PWR_EXTWKUP_TYPE_FALLING (LL_PWR_EXTWKUP_INVERT_LSB | \
167 LL_PWR_EXTWKUP_SRC_EN_LSB) /**< Falling edge wakeup */
168 /** @} */
169
170 /** @defgroup PWR_LL_EC_PSC_CMD Power State Control Commands
171 * @{
172 */
173 #define LL_PWR_CMD_LOOPBACK AON_PSC_CMD_OPC_OPCODE_LOOPBACK /**< Reserved command 0 */
174 #define LL_PWR_CMD_EF_DIR_ON AON_PSC_CMD_OPC_OPCODE_EF_DIR_ON /**< Reserved command 1 */
175 #define LL_PWR_CMD_32_TIMER_LD AON_PSC_CMD_OPC_OPCODE_32_TIMER_LD /**< Load sleep timer command */
176 #define LL_PWR_CMD_DEEP_SLEEP AON_PSC_CMD_OPC_OPCODE_DEEP_SLEEP /**< Enter Deep Sleep
177 Mode command */
178 #define LL_PWR_CMD_EF_DIR_OFF AON_PSC_CMD_OPC_OPCODE_EF_DIR_OFF /**< Reserved command 2 */
179 #define LL_PWR_CMD_EXT_CLK AON_PSC_CMD_OPC_OPCODE_EXT_CLK /**< Select external clock
180 (xo_32KHz) command */
181 #define LL_PWR_CMD_RNG_CLK AON_PSC_CMD_OPC_OPCODE_RNG_CLK /**< Select RING OSC clock
182 command */
183 #define LL_PWR_CMD_RTC_CLK AON_PSC_CMD_OPC_OPCODE_RTC_CLK /**< Select RTC clock command */
184 #define LL_PWR_CMD_RNG2_CLK AON_PSC_CMD_OPC_OPCODE_RNG2_CLK /**< Select RING OSC clock
185 command */
186 #define LL_PWR_CMD_LD_MEM_SLP_CFG AON_PSC_CMD_OPC_OPCODE_LD_MEM_SLP_CFG /**< Load memory sleep settings
187 command */
188 #define LL_PWR_CMD_LD_MEM_WKUP_CFG AON_PSC_CMD_OPC_OPCODE_LD_MEM_WKUP_CFG /**< Load memory wakeup settings
189 command */
190 #define LL_PWR_CMD_DPAD_LE_HI AON_PSC_CMD_OPC_OPCODE_DPAD_LE_HI /**< Force dpad_le high */
191 #define LL_PWR_CMD_DPAD_LE_LO AON_PSC_CMD_OPC_OPCODE_DPAD_LE_LO /**< Force dpad_le low */
192 #define LL_PWR_CMD_SLP_TIMER_MODE_NORMAL AON_PSC_CMD_OPC_OPCODE_SLP_TIMER_MODE_0 /**< Enable sleep timer
193 mode 0 command */
194 #define LL_PWR_CMD_SLP_TIMER_MODE_SINGLE AON_PSC_CMD_OPC_OPCODE_SLP_TIMER_MODE_1 /**< Enable sleep timer
195 mode 1 command */
196 #define LL_PWR_CMD_SLP_TIMER_MODE_RELOAD AON_PSC_CMD_OPC_OPCODE_SLP_TIMER_MODE_2 /**< Enable sleep timer
197 mode 2 command */
198 #define LL_PWR_CMD_SLP_TIMER_MODE_DISABLE AON_PSC_CMD_OPC_OPCODE_SLP_TIMER_MODE_3 /**< Enable sleep timer
199 mode 3 command */
200 /** @} */
201
202
203 /** @} */
204
205 /** @defgroup PWR_LL_EC_DPAD_VALUE Dpad LE State
206 * @{
207 */
208 #define LL_PWR_DPAD_LE_OFF (0x00000000U) /**< Dpad LE LOW */
209 #define LL_PWR_DPAD_LE_ON (0x00000001U) /**< Dpad LE High */
210 /** @} */
211
212 /** @defgroup PWR_LL_EC_TIMER_READ_SEL Timer Read Select
213 * @note Only available on GR5515_C and later version
214 * @{
215 */
216 #define LL_PWR_TIMER_READ_SEL_CAL_TIMER AON_PAD_CTL1_TIMER_READ_SEL_CAL_TIMER /**< Calendar timer */
217 #define LL_PWR_TIMER_READ_SEL_AON_WDT AON_PAD_CTL1_TIMER_READ_SEL_AON_WDT /**< AON watchdog timer */
218 #define LL_PWR_TIMER_READ_SEL_SLP_TIMER AON_PAD_CTL1_TIMER_READ_SEL_SLP_TIMER /**< Sleep timer */
219 #define LL_PWR_TIMER_READ_SEL_CAL_ALARM AON_PAD_CTL1_TIMER_READ_SEL_CAL_ALARM /**< Calendar alarm */
220 /** @} */
221
222 /** @} */
223
224
225 /* Exported macro ------------------------------------------------------------*/
226 /** @defgroup PWR_LL_DRIVER_FUNCTIONS Functions
227 * @{
228 */
229
230 /** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
231 * @{
232 */
233
234 /**
235 * @brief Write a value in PWR register
236 * @param __REG__ Register to be written
237 * @param __VALUE__ Value to be written in the register
238 * @retval None
239 */
240 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(AON->__REG__, (__VALUE__))
241
242 /**
243 * @brief Read a value in PWR register
244 * @param __REG__ Register to be read
245 * @retval Register value
246 */
247 #define LL_PWR_ReadReg(__REG__) READ_REG(AON->__REG__)
248 /** @} */
249
250 /* Exported functions --------------------------------------------------------*/
251 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
252 * @{
253 */
254
255 /** @defgroup PWR_LL_EF_Low_Power_Mode_Configuration Low power mode configuration
256 * @{
257 */
258
259 /**
260 * @brief Set the DeepSleep WakeUp Condition
261 *
262 * Register|BitsName
263 * --------|--------
264 * EXT_WKUP_CTL | WAKE_UP_SEL
265 *
266 * @param condition This parameter can be one of the following values:
267 * @arg @ref LL_PWR_WKUP_COND_EXT
268 * @arg @ref LL_PWR_WKUP_COND_TIMER
269 * @arg @ref LL_PWR_WKUP_COND_BLE
270 * @arg @ref LL_PWR_WKUP_COND_CALENDAR
271 * @arg @ref LL_PWR_WKUP_COND_BOD_FEDGE
272 * @arg @ref LL_PWR_WKUP_COND_MSIO_COMP
273 * @arg @ref LL_PWR_WKUP_COND_ALL
274 * @retval None
275 */
ll_pwr_set_wakeup_condition(uint32_t condition)276 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_wakeup_condition(uint32_t condition)
277 {
278 MODIFY_REG(AON->PWR_RET01, AON_PWR_REG01_WAKE_UP_SEL, condition);
279 }
280
281 /**
282 * @brief Get the Selected DeepSleep WakeUp Condition
283 *
284 * Register|BitsName
285 * --------|--------
286 * EXT_WKUP_CTL | WAKE_UP_SEL
287 *
288 * @retval Returned value can be one of the following values:
289 * @arg @ref LL_PWR_WKUP_COND_EXT
290 * @arg @ref LL_PWR_WKUP_COND_TIMER
291 * @arg @ref LL_PWR_WKUP_COND_BLE
292 * @arg @ref LL_PWR_WKUP_COND_CALENDAR
293 * @arg @ref LL_PWR_WKUP_COND_BOD_FEDGE
294 * @arg @ref LL_PWR_WKUP_COND_MSIO_COMP
295 * @arg @ref LL_PWR_WKUP_COND_ALL
296 */
ll_pwr_get_wakeup_condition(void)297 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_wakeup_condition(void)
298 {
299 return ((uint32_t)READ_BITS(AON->PWR_RET01, AON_PWR_REG01_WAKE_UP_SEL));
300 }
301
302 /**
303 * @brief Get the Event that triggered the DeepSleep WakeUp.
304 * @note Only available on GR5515_C and later version
305 *
306 * Register|BitsName
307 * --------|--------
308 * SLP_EVENT | SMCOSCEN_EVENT
309 * SLP_EVENT | TIMER_EVENT
310 * SLP_EVENT | EXT_WKUP_EVENT
311 * SLP_EVENT | WATCHDOG_EVENT
312 *
313 * @retval Returned value can be combination of the following values:
314 * @arg @ref LL_PWR_WKUP_EVENT_BLE
315 * @arg @ref LL_PWR_WKUP_EVENT_TIMER
316 * @arg @ref LL_PWR_WKUP_EVENT_EXT
317 * @arg @ref LL_PWR_WKUP_EVENT_BOD_FEDGE
318 * @arg @ref LL_PWR_WKUP_EVENT_MSIO_COMP
319 * @arg @ref LL_PWR_WKUP_EVENT_WDT
320 * @arg @ref LL_PWR_WKUP_EVENT_CALENDAR
321 */
ll_pwr_get_wakeup_event(void)322 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_wakeup_event(void)
323 {
324 return ((uint32_t)READ_BITS(AON->SLP_EVENT, LL_PWR_WKUP_EVENT_ALL));
325 }
326
327 /**
328 * @brief Enable the External WakeUp PINx functionality
329 *
330 * Register|BitsName
331 * --------|--------
332 * EXT_WKUP_CTL | MASK
333 *
334 * @param wakeup_pin This parameter can be a combination of the following values:
335 * @arg @ref LL_PWR_EXTWKUP_PIN0
336 * @arg @ref LL_PWR_EXTWKUP_PIN1
337 * @arg @ref LL_PWR_EXTWKUP_PIN2
338 * @arg @ref LL_PWR_EXTWKUP_PIN3
339 * @arg @ref LL_PWR_EXTWKUP_PIN4
340 * @arg @ref LL_PWR_EXTWKUP_PIN5
341 * @arg @ref LL_PWR_EXTWKUP_PIN_ALL
342 * @retval None
343 */
ll_pwr_enable_ext_wakeup_pin(uint32_t wakeup_pin)344 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_ext_wakeup_pin(uint32_t wakeup_pin)
345 {
346 GLOBAL_EXCEPTION_DISABLE();
347 SET_BITS(AON->EXT_WKUP_CTL, wakeup_pin);
348 GLOBAL_EXCEPTION_ENABLE();
349 }
350
351 /**
352 * @brief Disable the External WakeUp PINx functionality
353 *
354 * Register|BitsName
355 * --------|--------
356 * EXT_WKUP_CTL | MASK
357 *
358 * @param wakeup_pin This parameter can be a combination of the following values:
359 * @arg @ref LL_PWR_EXTWKUP_PIN0
360 * @arg @ref LL_PWR_EXTWKUP_PIN1
361 * @arg @ref LL_PWR_EXTWKUP_PIN2
362 * @arg @ref LL_PWR_EXTWKUP_PIN3
363 * @arg @ref LL_PWR_EXTWKUP_PIN4
364 * @arg @ref LL_PWR_EXTWKUP_PIN5
365 * @arg @ref LL_PWR_EXTWKUP_PIN_ALL
366 * @retval None
367 */
ll_pwr_disable_ext_wakeup_pin(uint32_t wakeup_pin)368 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_ext_wakeup_pin(uint32_t wakeup_pin)
369 {
370 GLOBAL_EXCEPTION_DISABLE();
371 CLEAR_BITS(AON->EXT_WKUP_CTL, wakeup_pin);
372 GLOBAL_EXCEPTION_ENABLE();
373 }
374
375 /**
376 * @brief Check if the External WakeUp PINx functionality is enabled
377 *
378 * Register|BitsName
379 * --------|--------
380 * EXT_WKUP_CTL | MASK
381 *
382 * @param wakeup_pin This parameter can be a combination of the following values:
383 * @arg @ref LL_PWR_EXTWKUP_PIN0
384 * @arg @ref LL_PWR_EXTWKUP_PIN1
385 * @arg @ref LL_PWR_EXTWKUP_PIN2
386 * @arg @ref LL_PWR_EXTWKUP_PIN3
387 * @arg @ref LL_PWR_EXTWKUP_PIN4
388 * @arg @ref LL_PWR_EXTWKUP_PIN5
389 * @arg @ref LL_PWR_EXTWKUP_PIN_ALL
390 * @retval State of bit (1 or 0).
391 */
ll_pwr_is_enabled_ext_wakeup_pin(uint32_t wakeup_pin)392 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_ext_wakeup_pin(uint32_t wakeup_pin)
393 {
394 return (READ_BITS(AON->EXT_WKUP_CTL, wakeup_pin) == wakeup_pin);
395 }
396
397 /**
398 * @brief Set the WakeUp Type of External WakeUp PINx.
399 *
400 * Register|BitsName
401 * --------|--------
402 * EXT_WKUP_CTL | INVERT
403 * EXT_WKUP_CTL | TYPE
404 *
405 * @param wakeup_pin This parameter can be a combination of the following values:
406 * @arg @ref LL_PWR_EXTWKUP_PIN0
407 * @arg @ref LL_PWR_EXTWKUP_PIN1
408 * @arg @ref LL_PWR_EXTWKUP_PIN2
409 * @arg @ref LL_PWR_EXTWKUP_PIN3
410 * @arg @ref LL_PWR_EXTWKUP_PIN4
411 * @arg @ref LL_PWR_EXTWKUP_PIN5
412 * @arg @ref LL_PWR_EXTWKUP_PIN_ALL
413 * @param wakeup_type This parameter can be one of the following values:
414 * @arg @ref LL_PWR_EXTWKUP_TYPE_LOW
415 * @arg @ref LL_PWR_EXTWKUP_TYPE_HIGH
416 * @arg @ref LL_PWR_EXTWKUP_TYPE_RISING
417 * @arg @ref LL_PWR_EXTWKUP_TYPE_FALLING
418 * @retval None
419 */
ll_pwr_set_ext_wakeup_type(uint32_t wakeup_pin,uint32_t wakeup_type)420 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_ext_wakeup_type(uint32_t wakeup_pin, uint32_t wakeup_type)
421 {
422 uint32_t invert = ((wakeup_type & LL_PWR_EXTWKUP_INVERT_LSB) == LL_PWR_EXTWKUP_INVERT_LSB) ? \
423 (wakeup_pin << AON_EXT_WKUP_CTL_INVERT_Pos) : 0;
424 uint32_t type = ((wakeup_type & LL_PWR_EXTWKUP_TYPE_LSB) == LL_PWR_EXTWKUP_TYPE_LSB) ? \
425 (wakeup_pin << AON_EXT_WKUP_CTL_TYPE_Pos) : 0;
426 GLOBAL_EXCEPTION_DISABLE();
427 MODIFY_REG(AON->EXT_WKUP_CTL,
428 (wakeup_pin << AON_EXT_WKUP_CTL_INVERT_Pos) | (wakeup_pin << AON_EXT_WKUP_CTL_TYPE_Pos),
429 invert | type);
430 GLOBAL_EXCEPTION_ENABLE();
431 }
432
433 /**
434 * @brief Get the WakeUp Type of External WakeUp PINx.
435 * @note Warning: only one pin can be passed as parameter.
436 *
437 * Register|BitsName
438 * --------|--------
439 * EXT_WKUP_CTL | INVERT
440 * EXT_WKUP_CTL | TYPE
441 *
442 * @param wakeup_pin This parameter can be one of the following values:
443 * @arg @ref LL_PWR_EXTWKUP_PIN0
444 * @arg @ref LL_PWR_EXTWKUP_PIN1
445 * @arg @ref LL_PWR_EXTWKUP_PIN2
446 * @arg @ref LL_PWR_EXTWKUP_PIN3
447 * @arg @ref LL_PWR_EXTWKUP_PIN4
448 * @arg @ref LL_PWR_EXTWKUP_PIN5
449 * @arg @ref LL_PWR_EXTWKUP_PIN_ALL
450 * @retval Returned value can be one of the following values:
451 * @arg @ref LL_PWR_EXTWKUP_TYPE_LOW
452 * @arg @ref LL_PWR_EXTWKUP_TYPE_HIGH
453 * @arg @ref LL_PWR_EXTWKUP_TYPE_RISING
454 * @arg @ref LL_PWR_EXTWKUP_TYPE_FALLING
455 */
ll_pwr_get_ext_wakeup_type(uint32_t wakeup_pin)456 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_ext_wakeup_type(uint32_t wakeup_pin)
457 {
458 return ((uint32_t)(READ_BITS(AON->EXT_WKUP_CTL, AON_EXT_WKUP_CTL_INVERT | AON_EXT_WKUP_CTL_TYPE) >> \
459 POSITION_VAL(wakeup_pin)));
460 }
461
462 /**
463 * @brief Set the 32 bits AON Sleep Timer Value to WakeUp the MCU from DeepSleep Mode.
464 * @note After the value was set, use @arg @ref LL_PWR_CMD_32_TIMER_LD command to
465 * load the configuration into Power State Controller.
466 *
467 * Register|BitsName
468 * --------|--------
469 * TIMER_VALUE | PWR_CTL_TIMER_32B
470 *
471 * @param value 32 bits count value loaded into the t32bit_timer
472 * @retval None
473 */
ll_pwr_set_sleep_timer_value(uint32_t value)474 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_sleep_timer_value(uint32_t value)
475 {
476 WRITE_REG(AON->TIMER_VALUE, value);
477 }
478
479 /**
480 * @brief Get the 32 bit AON Sleep Timer Value to WakeUp the MCU from DeepSleep Mode.
481 *
482 * Register|BitsName
483 * --------|--------
484 * TIMER_VALUE | PWR_CTL_TIMER_32B
485 *
486 * @retval 32 bit AON Timer Count Value
487 */
ll_pwr_get_sleep_timer_value(void)488 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_sleep_timer_value(void)
489 {
490 return READ_REG(AON->TIMER_VALUE);
491 }
492
493 /**
494 * @brief Enable the SMC WakeUp Request.
495 * @note Once this is set up, MCU will wake up SMC, and this bit need to be cleared by MCU.
496 *
497 * Register|BitsName
498 * --------|--------
499 * PWR_RET01 | SMC_WAKEUP_REQ
500 *
501 * @retval None
502 */
ll_pwr_enable_smc_wakeup_req(void)503 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_smc_wakeup_req(void)
504 {
505 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_SMC_WAKEUP_REQ);
506 }
507
508 /**
509 * @brief Disable the SMC WakeUp Request.
510 * @note This function is used to clear SMC WakeUp Request.
511 *
512 * Register|BitsName
513 * --------|--------
514 * PWR_RET01 | SMC_WAKEUP_REQ
515 *
516 * @retval None
517 */
ll_pwr_disable_smc_wakeup_req(void)518 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_smc_wakeup_req(void)
519 {
520 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_SMC_WAKEUP_REQ);
521 }
522
523 /**
524 * @brief Check if the SMC WakeUp Request was enabled or disabled.
525 *
526 * Register|BitsName
527 * --------|--------
528 * PWR_RET01 | SMC_WAKEUP_REQ
529 *
530 * @retval State of bit (1 or 0).
531 */
ll_pwr_is_enabled_smc_wakeup_req(void)532 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_smc_wakeup_req(void)
533 {
534 return (READ_BITS(AON->PWR_RET01, AON_PWR_REG01_SMC_WAKEUP_REQ) == AON_PWR_REG01_SMC_WAKEUP_REQ);
535 }
536
537 /**
538 * @brief Set the DPAD LE value during sleep and after wake up.
539 *
540 * Register|BitsName
541 * --------|--------
542 * MEM_N_SLP_CTL | DPAD_LE_SLP_VAL
543 * MEM_N_SLP_CTL | DPAD_LE_WKUP_VAL
544 *
545 * @param sleep This parameter can be one of the following values:
546 * @arg @ref LL_PWR_DPAD_LE_OFF
547 * @arg @ref LL_PWR_DPAD_LE_ON
548 * @param wakeup This parameter can be one of the following values:
549 * @arg @ref LL_PWR_DPAD_LE_OFF
550 * @arg @ref LL_PWR_DPAD_LE_ON
551 * @retval None
552 */
ll_pwr_set_dpad_le_value(uint32_t sleep,uint32_t wakeup)553 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_dpad_le_value(uint32_t sleep, uint32_t wakeup)
554 {
555 MODIFY_REG(AON->MEM_N_SLP_CTL, AON_MEM_CTL_DPAD_LE_SLP_VAL, (sleep << AON_MEM_CTL_DPAD_LE_SLP_VAL_Pos));
556 MODIFY_REG(AON->MEM_N_SLP_CTL, AON_MEM_CTL_DPAD_LE_WKUP_VAL, (wakeup << AON_MEM_CTL_DPAD_LE_WKUP_VAL_Pos));
557 }
558
559 /**
560 * @brief Request to excute the Power State Controller Command.
561 * @note The PSC command can only be excuted when Power State Controller is not in busy state.
562 * Use @ref ll_pwr_is_active_flag_psc_cmd_busy() to check the busy status, and make sure
563 * the last command has been finished.
564 *
565 * Register|BitsName
566 * --------|--------
567 * PSC_CMD_OPC | OPCODE
568 * PSC_CMD | MCU_PWR_REQ
569 *
570 * @param command This parameter can be one of the following values:
571 * @arg @ref LL_PWR_CMD_LOOPBACK
572 * @arg @ref LL_PWR_CMD_EF_DIR_ON
573 * @arg @ref LL_PWR_CMD_32_TIMER_LD
574 * @arg @ref LL_PWR_CMD_DEEP_SLEEP
575 * @arg @ref LL_PWR_CMD_EF_DIR_OFF
576 * @arg @ref LL_PWR_CMD_EXT_CLK
577 * @arg @ref LL_PWR_CMD_RNG_CLK
578 * @arg @ref LL_PWR_CMD_RTC_CLK
579 * @arg @ref LL_PWR_CMD_LD_MEM_SLP_CFG
580 * @arg @ref LL_PWR_CMD_LD_MEM_WKUP_CFG
581 * @arg @ref LL_PWR_CMD_DPAD_LE_HI (*)
582 * @arg @ref LL_PWR_CMD_DPAD_LE_LO (*)
583 * @arg @ref LL_PWR_CMD_SLP_TIMER_MODE_NORMAL (*)
584 * @arg @ref LL_PWR_CMD_SLP_TIMER_MODE_SINGLE (*)
585 * @arg @ref LL_PWR_CMD_SLP_TIMER_MODE_RELOAD (*)
586 * @arg @ref LL_PWR_CMD_SLP_TIMER_MODE_DISABLE (*)
587 *
588 * (*) Not available in A0 and B0
589 *
590 * @retval None
591 */
ll_pwr_req_excute_psc_command(uint32_t command)592 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_req_excute_psc_command(uint32_t command)
593 {
594 WRITE_REG(AON->PSC_CMD_OPC, (uint8_t)command);
595 SET_BITS(AON->PSC_CMD, AON_PSC_CMD_MCU_PWR_REQ);
596 }
597
598 /** @} */
599
600 /** @addtogroup PWR_LL_EF_Communication_Configuration BLE Communication timer and core configuration function
601 * @{
602 */
603
604 /**
605 * @brief Enable the Communication Timer Reset.
606 * @note Comm timer can be reset when all ble connection were disconnected and
607 * MCU was ready to enter into deepsleep mode.
608 *
609 * Register|BitsName
610 * --------|--------
611 * PWR_RET01 | COMM_TIMER_RST_N
612 *
613 * @retval None
614 */
ll_pwr_enable_comm_timer_reset(void)615 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_timer_reset(void)
616 {
617 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_COMM_TIMER_RST_N);
618 }
619
620 /**
621 * @brief Disable the Communication Timer Reset, and set Communication Timer to running state.
622 * @note After powered up, Comm Timer need to enter into running mode.
623 *
624 * Register|BitsName
625 * --------|--------
626 * PWR_RET01 | COMM_TIMER_RST_N
627 *
628 * @retval None
629 */
ll_pwr_disable_comm_timer_reset(void)630 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_timer_reset(void)
631 {
632 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_COMM_TIMER_RST_N);
633 }
634
635 /**
636 * @brief Check if the Communication Timer Reset was enabled or disabled.
637 *
638 * Register|BitsName
639 * --------|--------
640 * PWR_RET01 | COMM_TIMER_RST_N
641 *
642 * @retval State of bit (1 or 0).
643 */
ll_pwr_is_enabled_comm_timer_reset(void)644 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_timer_reset(void)
645 {
646 return ((uint32_t)(READ_BITS(AON->PWR_RET01, AON_PWR_REG01_COMM_TIMER_RST_N) == 0x0U));
647 }
648
649 /**
650 * @brief Enable the Communication Core Reset.
651 * @note Comm Core can be reset when all ble connection were disconnected and
652 * MCU was ready to enter into deepsleep mode, and When COMM_CORE_RST_N
653 * is 0, the ble is held in reset.
654 *
655 * Register|BitsName
656 * --------|--------
657 * PWR_RET01 | COMM_CORE_RST_N
658 *
659 * @retval None
660 */
ll_pwr_enable_comm_core_reset(void)661 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_core_reset(void)
662 {
663 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_COMM_CORE_RST_N);
664 }
665
666 /**
667 * @brief Disable the Communication Core Reset, and set Communication Core to running state.
668 * @note After powered up, Comm Core need to enter into running mode.
669 *
670 * Register|BitsName
671 * --------|--------
672 * PWR_RET01 | COMM_CORE_RST_N
673 *
674 * @retval None
675 */
ll_pwr_disable_comm_core_reset(void)676 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_core_reset(void)
677 {
678 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_COMM_CORE_RST_N);
679 }
680
681 /**
682 * @brief Check if the Communication Core Reset was enabled or disabled.
683 *
684 * Register|BitsName
685 * --------|--------
686 * PWR_RET01 | COMM_CORE_RST_N
687 *
688 * @retval State of bit (1 or 0).
689 */
ll_pwr_is_enabled_comm_core_reset(void)690 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_reset(void)
691 {
692 return ((uint32_t)(READ_BITS(AON->PWR_RET01, AON_PWR_REG01_COMM_CORE_RST_N) == 0x0U));
693 }
694
695 /**
696 * @brief Enable the Communication Timer Power, the Communication Timer will be Powered Up.
697 *
698 * Register|BitsName
699 * --------|--------
700 * CALENDAR_TIMER_CTL | ISO_EN_PD_COMM_TIMER
701 * CALENDAR_TIMER_CTL | PWR_EN_PD_COMM_TIMER
702 *
703 * @retval None
704 */
ll_pwr_enable_comm_timer_power(void)705 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_timer_power(void)
706 {
707 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_ISO_EN_PD_COMM_TIMER);
708 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_TIMER);
709 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_ISO_EN_PD_COMM_TIMER);
710 }
711
712 /**
713 * @brief Disable the Communication Timer Power, the Communication Timer will be Powered Down.
714 *
715 * Register|BitsName
716 * --------|--------
717 * CALENDAR_TIMER_CTL | ISO_EN_PD_COMM_TIMER
718 * CALENDAR_TIMER_CTL | PWR_EN_PD_COMM_TIMER
719 *
720 * @retval None
721 */
ll_pwr_disable_comm_timer_power(void)722 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_timer_power(void)
723 {
724 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_TIMER);
725 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_ISO_EN_PD_COMM_TIMER);
726 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_TIMER);
727 }
728
729 /**
730 * @brief Check if the Communication Timer Power was enabled or disabled.
731 *
732 * Register|BitsName
733 * --------|--------
734 * CALENDAR_TIMER_CTL | ISO_EN_PD_COMM_TIMER
735 * CALENDAR_TIMER_CTL | PWR_EN_PD_COMM_TIMER
736 *
737 * @retval State of bit (1 or 0).
738 */
ll_pwr_is_enabled_comm_timer_power(void)739 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_timer_power(void)
740 {
741 return ((uint32_t)(READ_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_TIMER) == \
742 AON_PWR_REG01_PWR_EN_PD_COMM_TIMER));
743 }
744
745 /**
746 * @brief Enable the Communication Core Power, the Communication Core will be Powered Up.
747 *
748 * Register|BitsName
749 * --------|--------
750 * CALENDAR_TIMER_CTL | ISO_EN_PD_COMM_CORE
751 * CALENDAR_TIMER_CTL | PWR_EN_PD_COMM_CORE
752 *
753 * @retval None
754 */
ll_pwr_enable_comm_core_power(void)755 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_core_power(void)
756 {
757 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_CORE);
758 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_ISO_EN_PD_COMM_CORE);
759 }
760
761 /**
762 * @brief Disable the Communication Core Power, the Communication Core will be Powered Down.
763 *
764 * Register|BitsName
765 * --------|--------
766 * CALENDAR_TIMER_CTL | ISO_EN_PD_COMM_CORE
767 * CALENDAR_TIMER_CTL | PWR_EN_PD_COMM_CORE
768 *
769 * @retval None
770 */
ll_pwr_disable_comm_core_power(void)771 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_core_power(void)
772 {
773 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_CORE);
774 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_ISO_EN_PD_COMM_CORE);
775 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_CORE);
776 }
777
778 /**
779 * @brief Check if the Communication Core Power was enabled or disabled.
780 *
781 * Register|BitsName
782 * --------|--------
783 * CALENDAR_TIMER_CTL | ISO_EN_PD_COMM_CORE
784 * CALENDAR_TIMER_CTL | PWR_EN_PD_COMM_CORE
785 *
786 * @retval None
787 */
ll_pwr_is_enabled_comm_core_power(void)788 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_power(void)
789 {
790 return ((uint32_t)(READ_BITS(AON->PWR_RET01, AON_PWR_REG01_PWR_EN_PD_COMM_CORE) == \
791 AON_PWR_REG01_PWR_EN_PD_COMM_CORE));
792 }
793
794 /**
795 * @brief Select which timer value to read
796 *
797 * Register|BitsName
798 * --------|--------
799 * PAD_CTL1 | TIMER_READ_SEL
800 *
801 * @param select This parameter can be one of the following values:
802 * @arg @ref LL_PWR_TIMER_READ_SEL_CAL_TIMER
803 * @arg @ref LL_PWR_TIMER_READ_SEL_AON_WDT
804 * @arg @ref LL_PWR_TIMER_READ_SEL_SLP_TIMER
805 * @arg @ref LL_PWR_TIMER_READ_SEL_CAL_ALARM
806 * @retval None
807 */
ll_pwr_set_timer_read_select(uint32_t select)808 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_timer_read_select(uint32_t select)
809 {
810 GLOBAL_EXCEPTION_DISABLE();
811 MODIFY_REG(AON->AON_PAD_CTL1, AON_PAD_CTL1_TIMER_READ_SEL, select);
812 GLOBAL_EXCEPTION_ENABLE();
813 }
814
815 /**
816 * @brief Get which timer value was selected to read.
817 *
818 * Register|BitsName
819 * --------|--------
820 * PAD_CTL1 | TIMER_READ_SEL
821 *
822 * @retval Returned value can be one of the following values:
823 * @arg @ref LL_PWR_TIMER_READ_SEL_CAL_TIMER
824 * @arg @ref LL_PWR_TIMER_READ_SEL_AON_WDT
825 * @arg @ref LL_PWR_TIMER_READ_SEL_SLP_TIMER
826 * @arg @ref LL_PWR_TIMER_READ_SEL_CAL_ALARM
827 */
ll_pwr_get_timer_read_select(void)828 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_timer_read_select(void)
829 {
830 return ((uint32_t)READ_BITS(AON->AON_PAD_CTL1, AON_PAD_CTL1_TIMER_READ_SEL));
831 }
832
833 /**
834 * @brief Get current timer value based on the selection.
835 * @note Please read multiple times until get a stable value.
836 *
837 * Register|BitsName
838 * --------|--------
839 * PAD_CTL1 | TIMER_READ_SEL
840 *
841 * @retval Returned value can be one of the following values:
842 * @arg @ref LL_PWR_TIMER_READ_SEL_CAL_TIMER
843 * @arg @ref LL_PWR_TIMER_READ_SEL_AON_WDT
844 * @arg @ref LL_PWR_TIMER_READ_SEL_SLP_TIMER
845 * @arg @ref LL_PWR_TIMER_READ_SEL_CAL_ALARM
846 */
ll_pwr_get_timer_read_value(void)847 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_timer_read_value(void)
848 {
849 return ((uint32_t)READ_REG(AON->TIMER_VAL));
850 }
851
852 /**
853 * @brief Enable high frequency crystal oscillator sleep mode, and diable OSC.
854 *
855 * Register|BitsName
856 * --------|--------
857 * MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_OSC_SLEEP_EN
858 *
859 * @retval None
860 */
ll_pwr_enable_osc_sleep(void)861 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_osc_sleep(void)
862 {
863 GLOBAL_EXCEPTION_DISABLE();
864 SET_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_OSC_SLEEP_EN);
865 GLOBAL_EXCEPTION_ENABLE();
866 }
867
868
869 /**
870 * @brief Disable high frequency crystal oscillator sleep mode.
871 * @note Switch OSC from sleep mode into normal active mode.
872 *
873 * Register|BitsName
874 * --------|--------
875 * MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_OSC_SLEEP_EN
876 *
877 * @retval None
878 */
ll_pwr_disable_osc_sleep(void)879 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_osc_sleep(void)
880 {
881 GLOBAL_EXCEPTION_DISABLE();
882 CLEAR_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_OSC_SLEEP_EN);
883 GLOBAL_EXCEPTION_ENABLE();
884 }
885
886 /**
887 * @brief Check if the OSC sleep mode was enabled or disabled.
888 *
889 * Register|BitsName
890 * --------|--------
891 * MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_OSC_SLEEP_EN
892 *
893 * @retval State of bit (1 or 0).
894 */
ll_pwr_is_enabled_osc_sleep(void)895 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_osc_sleep(void)
896 {
897 return ((uint32_t)(READ_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_OSC_SLEEP_EN) == \
898 AON_COMM_DEEPSLCNTL_OSC_SLEEP_EN));
899 }
900
901 /**
902 * @brief Enable Radio sleep mode, and disable Radio module.
903 *
904 * Register|BitsName
905 * --------|--------
906 * MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_RADIO_SLEEP_EN
907 *
908 * @retval None
909 */
ll_pwr_enable_radio_sleep(void)910 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_radio_sleep(void)
911 {
912 GLOBAL_EXCEPTION_DISABLE();
913 SET_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_RADIO_SLEEP_EN);
914 GLOBAL_EXCEPTION_ENABLE();
915 }
916
917 /**
918 * @brief Disable Radio sleep mode.
919 * @note Switch Radio from sleep mode into normal active mode.
920 *
921 * Register|BitsName
922 * --------|--------
923 * MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_RADIO_SLEEP_EN
924 *
925 * @retval None
926 */
ll_pwr_disable_radio_sleep(void)927 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_radio_sleep(void)
928 {
929 GLOBAL_EXCEPTION_DISABLE();
930 CLEAR_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_RADIO_SLEEP_EN);
931 GLOBAL_EXCEPTION_ENABLE();
932 }
933
934 /**
935 * @brief Check if the Radio sleep mode was enabled or disabled.
936 *
937 * Register|BitsName
938 * --------|--------
939 * MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_RADIO_SLEEP_EN
940 *
941 * @retval State of bit (1 or 0).
942 */
ll_pwr_is_enabled_radio_sleep(void)943 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_radio_sleep(void)
944 {
945 return ((uint32_t)(READ_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_RADIO_SLEEP_EN) == \
946 AON_COMM_DEEPSLCNTL_RADIO_SLEEP_EN));
947 }
948
949 /**
950 * @brief Enable Communication Core Deep Sleep Mode.
951 * @note This bit is reset on DEEP_SLEEP_STAT falling edge.
952 *
953 * Register|BitsName
954 * --------|--------
955 * MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_DEEP_SLEEP_ON
956 *
957 * @retval None
958 */
ll_pwr_enable_comm_core_deep_sleep(void)959 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_core_deep_sleep(void)
960 {
961 GLOBAL_EXCEPTION_DISABLE();
962 SET_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_DEEP_SLEEP_ON);
963 GLOBAL_EXCEPTION_ENABLE();
964 }
965
966 /**
967 * @brief Disable Communication Core Deep Sleep Mode.
968 * @note Switch Communication Core from sleep mode into normal active mode.
969 *
970 * Register|BitsName
971 * --------|--------
972 * MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_DEEP_SLEEP_ON
973 *
974 * @retval None
975 */
ll_pwr_disable_comm_core_deep_sleep(void)976 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_core_deep_sleep(void)
977 {
978 GLOBAL_EXCEPTION_DISABLE();
979 CLEAR_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_DEEP_SLEEP_ON);
980 GLOBAL_EXCEPTION_ENABLE();
981 }
982
983 /**
984 * @brief Check if the Communication Core Deep Sleep Mode was enabled or disabled.
985 *
986 * Register|BitsName
987 * --------|--------
988 * MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_DEEP_SLEEP_ON
989 *
990 * @retval State of bit (1 or 0).
991 */
ll_pwr_is_enabled_comm_core_deep_sleep(void)992 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_deep_sleep(void)
993 {
994 return ((uint32_t)(READ_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_DEEP_SLEEP_ON) == \
995 AON_COMM_DEEPSLCNTL_DEEP_SLEEP_ON));
996 }
997
998 /**
999 * @brief Enable Wake Up Request from Software.
1000 * @note Applies when system is in Deep Sleep Mode. It wakes up the Communication Core
1001 * when written with a 1. No action happens if it is written with 0.
1002 *
1003 * Register|BitsName
1004 * --------|--------
1005 * MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_SOFT_WAKEUP_REQ
1006 *
1007 * @retval None
1008 */
ll_pwr_enable_comm_soft_wakeup_req(void)1009 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_soft_wakeup_req(void)
1010 {
1011 GLOBAL_EXCEPTION_DISABLE();
1012 SET_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_SOFT_WAKEUP_REQ);
1013 GLOBAL_EXCEPTION_ENABLE();
1014 }
1015
1016 /**
1017 * @brief Check if the Wake Up Request was enabled or disabled.
1018 * @note Resets at 0 means request action is performed.
1019 *
1020 * Register|BitsName
1021 * --------|--------
1022 * MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_SOFT_WAKEUP_REQ
1023 *
1024 * @retval State of bit (1 or 0).
1025 */
ll_pwr_is_enabled_soft_wakeup_req(void)1026 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_soft_wakeup_req(void)
1027 {
1028 return ((uint32_t)(READ_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_SOFT_WAKEUP_REQ) == \
1029 AON_COMM_DEEPSLCNTL_SOFT_WAKEUP_REQ));
1030 }
1031
1032 /**
1033 * @brief Enable Communication Core external wakeup.
1034 * @note After this configuration, Communication Core can be woken up by external wake-up
1035 *
1036 * Register|BitsName
1037 * --------|--------
1038 * MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_EXTWKUPDSB
1039 *
1040 * @retval None
1041 */
ll_pwr_enable_comm_core_ext_wakeup(void)1042 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_enable_comm_core_ext_wakeup(void)
1043 {
1044 GLOBAL_EXCEPTION_DISABLE();
1045 CLEAR_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_EXTWKUPDSB);
1046 GLOBAL_EXCEPTION_ENABLE();
1047 }
1048
1049 /**
1050 * @brief Disable Communication Core external wakeup.
1051 * @note After this configuration, Communication Core cannot be woken up by external wake-up
1052 *
1053 * Register|BitsName
1054 * --------|--------
1055 * MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_EXTWKUPDSB
1056 *
1057 * @retval None
1058 */
ll_pwr_disable_comm_core_ext_wakeup(void)1059 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_comm_core_ext_wakeup(void)
1060 {
1061 GLOBAL_EXCEPTION_DISABLE();
1062 SET_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_EXTWKUPDSB);
1063 GLOBAL_EXCEPTION_ENABLE();
1064 }
1065
1066 /**
1067 * @brief Check if the Communication Core external wakeup was enabled or disabled.
1068 *
1069 * Register|BitsName
1070 * --------|--------
1071 * MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_EXTWKUPDSB
1072 *
1073 * @retval State of bit (1 or 0).
1074 */
ll_pwr_is_enabled_comm_core_ext_wakeup(void)1075 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_enabled_comm_core_ext_wakeup(void)
1076 {
1077 return ((uint32_t)(READ_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_EXTWKUPDSB) == 0x0U));
1078 }
1079
1080 /**
1081 * @brief Set the time in low_power_clk clock cycles to spend in Deep Sleep Mode before waking-up the device.
1082 *
1083 * Register|BitsName
1084 * --------|--------
1085 * COMM_TMR_DEEPSLWKUP | AON_COMM_TMR_DEEPSLWKUP_DEEPSLTIME
1086 *
1087 * @param time 32 bit clock cycles loaded into the AON_COMM_TMR_DEEPSLWKUP_DEEPSLTIME
1088 * @retval None
1089 */
ll_pwr_set_comm_core_wakeup_time(uint32_t time)1090 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_comm_core_wakeup_time(uint32_t time)
1091 {
1092 WRITE_REG(AON->PWR_RET28, time);
1093 }
1094
1095 /**
1096 * @brief Get the time in low_power_clk clock cycles to spend in Deep Sleep Mode before waking-up the device.
1097 *
1098 * Register|BitsName
1099 * --------|--------
1100 * COMM_TMR_DEEPSLWKUP | AON_COMM_TMR_DEEPSLWKUP_DEEPSLTIME
1101 *
1102 * @retval Clock cycles to spend in Deep Sleep Mode before waking-up the device
1103 */
ll_pwr_get_comm_wakeup_time(void)1104 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_comm_wakeup_time(void)
1105 {
1106 return ((uint32_t)READ_REG(AON->PWR_RET28));
1107 }
1108
1109
1110 /**
1111 * @brief Get the actual duration of the last deep sleep phase measured in low_power_clk clock cycle.
1112 *
1113 * Register|BitsName
1114 * --------|--------
1115 * COMM_TMR_DEEPSLPSTAT | DEEPSLDUR
1116 *
1117 * @retval Sleep duration
1118 */
ll_pwr_get_comm_sleep_duration(void)1119 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_comm_sleep_duration(void)
1120 {
1121 return ((uint32_t)READ_REG(MCU_SUB->COMM_TMR_DEEPSLPSTAT));
1122 }
1123
1124 /**
1125 * @brief Set the wakeup timing in low_power_clk clock cycles to spend when waking-up the device.
1126 *
1127 * Register|BitsName
1128 * --------|--------
1129 * COMM_TMR_ENBPRESET | TWEXT
1130 * COMM_TMR_ENBPRESET | TWOSC
1131 * COMM_TMR_ENBPRESET | TWRM
1132 *
1133 * @param twext Time in low power oscillator cycles allowed for stabilization of the high frequency
1134 * oscillator following an external wake–up request (signal wakeup_req).
1135 * @param twosc Time in low power oscillator cycles allowed for stabilization of the high frequency
1136 * oscillator when the deep–sleep mode has been left due to sleep–timer expiry.
1137 * @param twrm Time in low power oscillator cycles allowed for the radio module to leave low–power mode.
1138 * @retval None
1139 */
ll_pwr_set_comm_wakeup_timing(uint32_t twext,uint32_t twosc,uint32_t twrm)1140 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_set_comm_wakeup_timing(uint32_t twext, uint32_t twosc, uint32_t twrm)
1141 {
1142 WRITE_REG(AON->PWR_RET29, (twext << AON_COMM_TMR_ENBPRESET_TWEXT_Pos) |
1143 (twosc << AON_COMM_TMR_ENBPRESET_TWOSC_Pos) |
1144 (twrm << AON_COMM_TMR_ENBPRESET_TWRM_Pos));
1145 }
1146
1147
1148 /**
1149 * @brief Read the wakeup timing in low_power_clk clock cycles to spend when waking-up the device.
1150 *
1151 * Register|BitsName
1152 * --------|--------
1153 * COMM_TMR_ENBPRESET | TWEXT
1154 * COMM_TMR_ENBPRESET | TWOSC
1155 * COMM_TMR_ENBPRESET | TWRM
1156 *
1157 * @retval COMM_TMR_ENBPRESET Register value
1158 */
ll_pwr_read_comm_wakeup_timing(void)1159 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_read_comm_wakeup_timing(void)
1160 {
1161 return ((uint32_t)READ_REG(AON->PWR_RET29));
1162 }
1163
1164 /**
1165 * @brief Read the Twosc of the wakeup timing in low_power_clk clock cycles to spend when waking-up the device.
1166 *
1167 * @retval TWOSC value
1168 */
ll_pwr_read_comm_wakeup_timing_twosc(void)1169 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_read_comm_wakeup_timing_twosc(void)
1170 {
1171 return ((((uint32_t)READ_REG(AON->PWR_RET29) & AON_COMM_TMR_ENBPRESET_TWOSC_Msk)) >> \
1172 AON_COMM_TMR_ENBPRESET_TWOSC_Pos);
1173 }
1174
1175
1176 /** @} */
1177
1178 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
1179 * @{
1180 */
1181
1182 /**
1183 * @brief Get the External Wake Up Status.
1184 * @note 0 means not waked up and 1 means waked up.
1185 *
1186 * Register|BitsName
1187 * --------|--------
1188 * SLP_EVENT | EXT_WKUP_STATUS
1189 *
1190 * @retval Returned value can be a combination of the following values:
1191 * @arg @ref LL_PWR_EXTWKUP_PIN0
1192 * @arg @ref LL_PWR_EXTWKUP_PIN1
1193 * @arg @ref LL_PWR_EXTWKUP_PIN2
1194 * @arg @ref LL_PWR_EXTWKUP_PIN3
1195 * @arg @ref LL_PWR_EXTWKUP_PIN4
1196 * @arg @ref LL_PWR_EXTWKUP_PIN5
1197 * @arg @ref LL_PWR_EXTWKUP_PIN_ALL
1198 */
ll_pwr_get_ext_wakeup_status(void)1199 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_get_ext_wakeup_status(void)
1200 {
1201 return ((uint32_t)(READ_BITS(AON->SLP_EVENT, AON_SLP_EVENT_EXT_WKUP_STATUS) >> \
1202 AON_SLP_EVENT_EXT_WKUP_STATUS_Pos) & \
1203 (uint32_t)(READ_BITS(AON->EXT_WKUP_CTL, LL_PWR_EXTWKUP_PIN_ALL)));
1204 }
1205
1206 /**
1207 * @brief Clear the External Wake Up Status.
1208 *
1209 * Register|BitsName
1210 * --------|--------
1211 * SLP_EVENT | EXT_WKUP_STATUS
1212 *
1213 * @param wakeup_pin This parameter can be a combination of the following values:
1214 * @arg @ref LL_PWR_EXTWKUP_PIN0
1215 * @arg @ref LL_PWR_EXTWKUP_PIN1
1216 * @arg @ref LL_PWR_EXTWKUP_PIN2
1217 * @arg @ref LL_PWR_EXTWKUP_PIN3
1218 * @arg @ref LL_PWR_EXTWKUP_PIN4
1219 * @arg @ref LL_PWR_EXTWKUP_PIN5
1220 * @arg @ref LL_PWR_EXTWKUP_PIN_ALL
1221 * @retval None
1222 */
ll_pwr_clear_ext_wakeup_status(uint32_t wakeup_pin)1223 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_clear_ext_wakeup_status(uint32_t wakeup_pin)
1224 {
1225 GLOBAL_EXCEPTION_DISABLE();
1226 WRITE_REG(AON->SLP_EVENT, ~(wakeup_pin << AON_SLP_EVENT_EXT_WKUP_STATUS_Pos));
1227 GLOBAL_EXCEPTION_ENABLE();
1228 }
1229
1230 /**
1231 * @brief Clear the Event that triggered the DeepSleep WakeUp.
1232 *
1233 * Register|BitsName
1234 * --------|--------
1235 * SLP_EVENT | SMCOSCEN_EVENT
1236 * SLP_EVENT | TIMER_EVENT
1237 * SLP_EVENT | EXT_WKUP_EVENT
1238 * SLP_EVENT | WATCHDOG_EVENT
1239 *
1240 * @param event This parameter can be a combination of the following values:
1241 * @arg @ref LL_PWR_WKUP_EVENT_BLE
1242 * @arg @ref LL_PWR_WKUP_EVENT_TIMER
1243 * @arg @ref LL_PWR_WKUP_EVENT_EXT
1244 * @arg @ref LL_PWR_WKUP_EVENT_BOD_FEDGE
1245 * @arg @ref LL_PWR_WKUP_EVENT_MSIO_COMP
1246 * @arg @ref LL_PWR_WKUP_EVENT_WDT
1247 * @arg @ref LL_PWR_WKUP_EVENT_CALENDAR
1248 * @retval None
1249 */
ll_pwr_clear_wakeup_event(uint32_t event)1250 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_clear_wakeup_event(uint32_t event)
1251 {
1252 WRITE_REG(AON->SLP_EVENT, ~(event & LL_PWR_WKUP_EVENT_ALL));
1253 }
1254
1255 /**
1256 * @brief Indicate if the Power State Controller is in busy state.
1257 * @note This is bit set 1 when the PSC_CMD_REQ[0] is set to 1, and will remain 1 until
1258 * the PSC_CMD_OPC has been transferred to the PSC.
1259 *
1260 * Register|BitsName
1261 * --------|--------
1262 * PSC_CMD | MCU_PWR_BUSY
1263 *
1264 * @retval State of bit (1 or 0).
1265 */
ll_pwr_is_active_flag_psc_cmd_busy(void)1266 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_active_flag_psc_cmd_busy(void)
1267 {
1268 return (READ_BITS(AON->PSC_CMD, AON_PSC_CMD_MCU_PWR_BUSY) == AON_PSC_CMD_MCU_PWR_BUSY);
1269 }
1270
1271 /**
1272 * @brief Indicate if the Communication Core is in Deep Sleep Mode.
1273 * @note When Communication Core is in Deep Sleep Mode, only low_power_clk is running.
1274 *
1275 * Register|BitsName
1276 * --------|--------
1277 * MSIO_PAD_CFG_1 | COMM_DEEPSLCNTL_DEEP_SLEEP_STAT
1278 *
1279 * @retval State of bit (1 or 0).
1280 */
ll_pwr_is_active_flag_comm_deep_sleep_stat(void)1281 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_pwr_is_active_flag_comm_deep_sleep_stat(void)
1282 {
1283 return (READ_BITS(AON->MSIO_PAD_CFG_1, AON_COMM_DEEPSLCNTL_DEEP_SLEEP_STAT) == AON_COMM_DEEPSLCNTL_DEEP_SLEEP_STAT);
1284 }
1285
1286 /**
1287 * @brief Disable cache function
1288 * @note The cache should be closed before chip go to deepsleep.
1289 *
1290 * Register|BitsName
1291 * --------|--------
1292 * CTRL0 |EN
1293 *
1294 * @retval None
1295 */
ll_pwr_disable_cache_module(void)1296 SECTION_RAM_CODE __STATIC_INLINE void ll_pwr_disable_cache_module(void)
1297 {
1298 SET_BITS(XQSPI->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIS);
1299 __NOP();
1300 __NOP();
1301 __NOP();
1302 __NOP();
1303 __NOP();
1304 __NOP();
1305 __NOP();
1306 __NOP();
1307 __NOP();
1308 }
1309
1310 /** @} */
1311
1312 /** @} */
1313 /** @} */
1314
1315 #endif /* defined(AON) */
1316
1317 #ifdef __cplusplus
1318 }
1319 #endif
1320
1321 #endif /* __GR55xx_LL_PWR_H__ */
1322
1323 /** @} */
1324
1325 /** @} */
1326
1327 /** @} */
1328