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Searched defs:orr (Results 1 – 21 of 21) sorted by relevance

/third_party/vixl/test/aarch64/
Dtest-assembler-neon-aarch64.cc10965 __ orr(q30.V16B(), q30.V16B(), q9.V16B()); in TEST() local
10969 __ orr(q30.V16B(), q30.V16B(), q9.V16B()); in TEST() local
10973 __ orr(q30.V16B(), q30.V16B(), q9.V16B()); in TEST() local
10977 __ orr(q30.V16B(), q30.V16B(), q9.V16B()); in TEST() local
10981 __ orr(q30.V16B(), q30.V16B(), q9.V16B()); in TEST() local
10985 __ orr(q30.V16B(), q30.V16B(), q9.V16B()); in TEST() local
10989 __ orr(q30.V16B(), q30.V16B(), q9.V16B()); in TEST() local
10993 __ orr(q30.V16B(), q30.V16B(), q9.V16B()); in TEST() local
10997 __ orr(q30.V16B(), q30.V16B(), q9.V16B()); in TEST() local
11001 __ orr(q30.V16B(), q30.V16B(), q9.V16B()); in TEST() local
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Dtest-trace-aarch64.cc268 __ orr(w6, w7, w8); in GenerateTestSequenceBase() local
269 __ orr(x9, x10, x11); in GenerateTestSequenceBase() local
1310 __ orr(v17.V16B(), v17.V16B(), v23.V16B()); in GenerateTestSequenceNEON() local
1311 __ orr(v8.V2S(), 0xe3); in GenerateTestSequenceNEON() local
1312 __ orr(v11.V4H(), 0x97, 8); in GenerateTestSequenceNEON() local
1313 __ orr(v7.V4S(), 0xab); in GenerateTestSequenceNEON() local
1314 __ orr(v8.V8B(), v4.V8B(), v3.V8B()); in GenerateTestSequenceNEON() local
1315 __ orr(v31.V8H(), 0xb0, 8); in GenerateTestSequenceNEON() local
Dtest-api-movprfx-aarch64.cc214 __ orr(z25.VnH(), p5.Merging(), z25.VnH(), z25.VnH()); in TEST() local
795 __ orr(z9.VnS(), p3.Merging(), z9.VnS(), z13.VnS()); in TEST() local
1516 __ orr(z27.VnD(), p2.Merging(), z27.VnD(), z17.VnD()); in TEST() local
Dtest-assembler-aarch64.cc455 TEST(orr) { in TEST() argument
7355 __ orr(xzr, x0, x6); in TEST() local
7356 __ orr(xzr, x6, xzr); in TEST() local
7357 __ orr(xzr, xzr, x6); in TEST() local
/third_party/node/deps/v8/src/regexp/arm/
Dregexp-macro-assembler-arm.cc276 __ orr(r3, r3, Operand(0x20)); // Convert capture character to lower-case. in CheckNotBackReferenceIgnoreCase() local
277 __ orr(r4, r4, Operand(0x20)); // Also convert input character. in CheckNotBackReferenceIgnoreCase() local
/third_party/vixl/test/aarch32/
Dtest-assembler-aarch32.cc688 __ orr(r0, r5, r6); in TEST() local
692 __ orr(r2, r2, 1); in TEST() local
703 __ orr(r2, r2, 1); in TEST() local
715 __ orr(r5, r5, 1); in TEST() local
5594 __ orr(r11, r11, 1); in TEST() local
/third_party/skia/fuzz/
DFuzzCanvas.cpp1234 SkRRect orr, irr; in fuzz_canvas() local
/third_party/vixl/src/aarch64/
Dassembler-sve-aarch64.cc122 void Assembler::orr(const ZRegister& zd, const ZRegister& zn, uint64_t imm) { in orr() function in vixl::aarch64::Assembler
157 void Assembler::orr(const ZRegister& zd, in orr() function in vixl::aarch64::Assembler
2414 void Assembler::orr(const ZRegister& zd, in orr() function in vixl::aarch64::Assembler
6221 void Assembler::orr(const PRegisterWithLaneSize& pd, in orr() function in vixl::aarch64::Assembler
Dassembler-aarch64.cc614 void Assembler::orr(const Register& rd, in orr() function in vixl::aarch64::Assembler
3974 void Assembler::orr(const VRegister& vd, const int imm8, const int left_shift) { in orr() function in vixl::aarch64::Assembler
Dlogic-aarch64.cc1024 LogicVRegister Simulator::orr(VectorFormat vform, in orr() function in vixl::aarch64::Simulator
3084 LogicVRegister Simulator::orr(VectorFormat vform, in orr() function in vixl::aarch64::Simulator
/third_party/node/deps/v8/src/builtins/arm/
Dbuiltins-arm.cc2956 __ orr(result_reg, result_reg, in Generate_DoubleToI() local
2958 __ orr(result_reg, double_low, Operand(result_reg, LSL, scratch)); in Generate_DoubleToI() local
/third_party/node/deps/v8/src/codegen/arm64/
Dassembler-arm64.cc933 void Assembler::orr(const Register& rd, const Register& rn, in orr() function in v8::internal::Assembler
3194 void Assembler::orr(const VRegister& vd, const int imm8, const int left_shift) { in orr() function in v8::internal::Assembler
/third_party/vixl/benchmarks/aarch32/
Dasm-disasm-speed-test.cc487 __ orr(r8, r8, r2); in Generate_3() local
500 __ orr(r8, r8, r3); in Generate_3() local
891 __ orr(r3, r3, 0x8000); in Generate_6() local
892 __ orr(r3, r3, 0x60); in Generate_6() local
2476 __ orr(r3, r3, 0x8000); in Generate_19() local
2478 __ orr(r3, r3, 0x60); in Generate_19() local
2854 __ orr(r8, r8, r1); in Generate_22() local
2864 __ orr(r8, r8, r3); in Generate_22() local
4269 __ orr(lt, r1, r1, 0x1); in Generate_32() local
/third_party/node/deps/v8/src/execution/arm64/
Dsimulator-logic-arm64.cc1001 LogicVRegister Simulator::orr(VectorFormat vform, LogicVRegister dst, in orr() function in v8::internal::Simulator
2051 LogicVRegister Simulator::orr(VectorFormat vform, LogicVRegister dst, in orr() function in v8::internal::Simulator
/third_party/node/deps/v8/src/codegen/arm/
Dassembler-arm.cc1626 void Assembler::orr(Register dst, Register src1, const Operand& src2, SBit s, in orr() function in v8::internal::Assembler
1631 void Assembler::orr(Register dst, Register src1, Register src2, SBit s, in orr() function in v8::internal::Assembler
/third_party/skia/tests/
DPathTest.cpp5072 SkRRect orr; in DEF_TEST() local
/third_party/vixl/src/aarch32/
Dassembler-aarch32.h2742 void orr(Register rd, Register rn, const Operand& operand) { in orr() function
2745 void orr(Condition cond, Register rd, Register rn, const Operand& operand) { in orr() function
2748 void orr(EncodingSize size, in orr() function
Dassembler-aarch32.cc7788 void Assembler::orr(Condition cond, in orr() function in vixl::aarch32::Assembler
Ddisasm-aarch32.cc2025 void Disassembler::orr(Condition cond, in orr() function in vixl::aarch32::Disassembler
/third_party/node/deps/v8/src/compiler/backend/arm/
Dcode-generator-arm.cc1120 __ orr(i.OutputRegister(), i.InputRegister(0), i.InputOperand2(1), in AssembleArchInstruction() local
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/
DIceAssemblerARM32.cpp1986 void AssemblerARM32::orr(const Operand *OpRd, const Operand *OpRn, in orr() function in Ice::ARM32::AssemblerARM32