| /third_party/ffmpeg/tests/checkasm/aarch64/ |
| D | checkasm.S | 151 .macro check_reg_neon reg1, reg2
164 .macro check_reg reg1, reg2
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| /third_party/libabigail/tests/data/test-abidiff-exit/ |
| D | test-decl-enum-v0.c | 5 void reg2(const enum disembodied_enum * foo) { (void)foo; } in reg2() function
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| D | test-decl-enum-v1.c | 5 void reg2(const enum disembodied_enum * foo) { (void)foo; } in reg2() function
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| D | test-decl-struct-v0.c | 5 void reg2(const struct disembodied * foo) { (void)foo; } in reg2() function
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| D | test-decl-struct-v1.c | 5 void reg2(const struct disembodied * foo) { (void)foo; } in reg2() function
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| D | test-member-size-v0.cc | 26 void reg2(U*) { } in reg2() function
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| D | test-member-size-v1.cc | 27 void reg2(U*) { } in reg2() function
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| /third_party/mesa3d/src/gallium/drivers/r600/sfn/tests/ |
| D | sfn_value_test.cpp | 58 Register reg2(3, 1, pin_fully); in TEST_F() local
82 Register reg2(1025, 2, pin_none); in TEST_F() local
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| /third_party/ffmpeg/tests/checkasm/arm/ |
| D | checkasm.S | 147 .macro check_reg reg1, reg2=
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| /third_party/node/deps/v8/src/interpreter/ |
| D | bytecode-register.cc | 105 bool Register::AreContiguous(Register reg1, Register reg2, Register reg3, in AreContiguous()
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| /third_party/ffmpeg/libavutil/mips/ |
| D | mmiutils.h | 101 #define MMI_LQ(reg1, reg2, addr, bias) \ argument
105 #define MMI_SQ(reg1, reg2, addr, bias) \ argument
192 #define MMI_LQ(reg1, reg2, addr, bias) \ argument
195 #define MMI_SQ(reg1, reg2, addr, bias) \ argument
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| /third_party/node/deps/openssl/openssl/crypto/aria/ |
| D | aria.c | 474 register uint32_t reg0, reg1, reg2, reg3; in ossl_aria_encrypt() local
541 register uint32_t reg0, reg1, reg2, reg3; in ossl_aria_set_encrypt_key() local
676 register uint32_t reg0, reg1, reg2, reg3; in ossl_aria_set_decrypt_key() local
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| /third_party/openssl/crypto/aria/ |
| D | aria.c | 474 register uint32_t reg0, reg1, reg2, reg3; in ossl_aria_encrypt() local
541 register uint32_t reg0, reg1, reg2, reg3; in ossl_aria_set_encrypt_key() local
676 register uint32_t reg0, reg1, reg2, reg3; in ossl_aria_set_decrypt_key() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64PBQPRegAlloc.cpp | 149 bool haveSameParity(unsigned reg1, unsigned reg2) { in haveSameParity()
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| /third_party/vixl/src/aarch64/ |
| D | macro-assembler-aarch64.cc | 3036 const Register& reg2, in Emit()
3050 const VRegister& reg2, in Emit()
3060 const CPURegister& reg2, in Emit()
3100 const Register& reg2, in Emit()
3110 const VRegister& reg2, in Emit()
3120 const CPURegister& reg2, in Emit()
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| /third_party/libbpf/src/ |
| D | gen_loader.c | 298 static void emit_debug(struct bpf_gen *gen, int reg1, int reg2, in emit_debug()
326 static void debug_regs(struct bpf_gen *gen, int reg1, int reg2, const char *fmt, ...) in debug_regs()
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| /third_party/mesa3d/src/intel/tools/ |
| D | aubinator_error_decode.c | 494 uint32_t reg, reg2; in read_data_file() local
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| /third_party/ffmpeg/libavcodec/mips/ |
| D | vp9_idct_msa.c | 967 v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; in vp9_idct16_1d_columns_addblk_msa() local
1070 v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; in vp9_idct16_1d_columns_msa() local
1634 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in vp9_idct8x32_column_even_process_store() local
1718 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in vp9_idct8x32_column_odd_process_store() local
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| D | h264pred_msa.c | 217 v4i32 reg0, reg1, reg2, reg3; in intra_predict_plane_16x16_msa() local
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| /third_party/vixl/src/aarch32/ |
| D | instructions-aarch32.h | 554 VRegisterList(VRegister reg1, VRegister reg2) in VRegisterList()
556 VRegisterList(VRegister reg1, VRegister reg2, VRegister reg3) in VRegisterList()
559 VRegisterList(VRegister reg1, VRegister reg2, VRegister reg3, VRegister reg4) in VRegisterList()
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| D | macro-assembler-aarch32.cc | 452 CPURegister reg2, in Printf()
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| /third_party/pcre2/pcre2/src/sljit/ |
| D | sljitNativeARM_T2_32.c | 72 #define IS_2_LO_REGS(reg1, reg2) \ argument
74 #define IS_3_LO_REGS(reg1, reg2, reg3) \ argument
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| /third_party/mesa3d/src/panfrost/bifrost/ |
| D | bifrost.h | 229 unsigned reg2 : 6; member
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| D | assembler-arm64.cc | 224 bool AreAliased(const CPURegister& reg1, const CPURegister& reg2, in AreAliased()
260 bool AreSameSizeAndType(const CPURegister& reg1, const CPURegister& reg2, in AreSameSizeAndType()
276 bool AreSameFormat(const VRegister& reg1, const VRegister& reg2, in AreSameFormat()
284 bool AreConsecutive(const VRegister& reg1, const VRegister& reg2, in AreConsecutive()
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| /third_party/ltp/tools/sparse/sparse-src/ |
| D | example.c | 925 struct hardreg *reg1, *reg2; in generate_commutative_binop() local
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