| /third_party/vixl/src/aarch64/ |
| D | assembler-sve-aarch64.cc | 50 void Assembler::adr(const ZRegister& zd, const SVEMemOperand& addr) { in adr()
100 void Assembler::and_(const ZRegister& zd, const ZRegister& zn, uint64_t imm) { in and_()
107 void Assembler::dupm(const ZRegister& zd, uint64_t imm) { in dupm()
115 void Assembler::eor(const ZRegister& zd, const ZRegister& zn, uint64_t imm) { in eor()
122 void Assembler::orr(const ZRegister& zd, const ZRegister& zn, uint64_t imm) { in orr()
130 void Assembler::and_(const ZRegister& zd, in and_()
139 void Assembler::bic(const ZRegister& zd, in bic()
148 void Assembler::eor(const ZRegister& zd, in eor()
157 void Assembler::orr(const ZRegister& zd, in orr()
178 void Assembler::asr(const ZRegister& zd, in asr()
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| D | macro-assembler-aarch64.h | 3612 void Abs(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) { in Abs()
3617 void Add(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) { in Add()
3622 void Add(const ZRegister& zd, const ZRegister& zn, IntegerOperand imm) { in Add()
3629 void Adr(const ZRegister& zd, const SVEMemOperand& addr) { in Adr()
3642 void And(const ZRegister& zd, const ZRegister& zn, uint64_t imm) { in And()
3652 void And(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) { in And()
3671 void Asr(const ZRegister& zd, in Asr()
3683 void Asr(const ZRegister& zd, const ZRegister& zn, int shift) { in Asr()
3688 void Asr(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) { in Asr()
3693 void Asrd(const ZRegister& zd, in Asrd()
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| D | macro-assembler-sve-aarch64.cc | 33 const ZRegister& zd, in AddSubHelper()
70 const ZRegister& zd, in TrySingleAddSub()
94 const ZRegister& zd, in IntWideImmHelper()
129 void MacroAssembler::Mul(const ZRegister& zd, in Mul()
138 void MacroAssembler::Smin(const ZRegister& zd, in Smin()
148 void MacroAssembler::Smax(const ZRegister& zd, in Smax()
158 void MacroAssembler::Umax(const ZRegister& zd, in Umax()
168 void MacroAssembler::Umin(const ZRegister& zd, in Umin()
363 void MacroAssembler::Cpy(const ZRegister& zd, in Cpy()
427 void MacroAssembler::Fcpy(const ZRegister& zd, in Fcpy()
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| D | operands-aarch64.h | 782 bool FitsInLane(const CPURegister& zd) const { in FitsInLane()
785 bool FitsInSignedLane(const CPURegister& zd) const { in FitsInSignedLane()
788 bool FitsInUnsignedLane(const CPURegister& zd) const { in FitsInUnsignedLane()
824 bool TryEncodeAsShiftedIntNForLane(const CPURegister& zd, T* imm) const { in TryEncodeAsShiftedIntNForLane()
864 bool TryEncodeAsShiftedIntNForLane(const CPURegister& zd, in TryEncodeAsShiftedIntNForLane()
876 bool TryEncodeAsIntNForLane(const CPURegister& zd, T* imm) const { in TryEncodeAsIntNForLane()
883 bool TryEncodeAsShiftedUintNForLane(const CPURegister& zd, T* imm) const { in TryEncodeAsShiftedUintNForLane()
901 bool TryEncodeAsShiftedUintNForLane(const CPURegister& zd, in TryEncodeAsShiftedUintNForLane()
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| D | simulator-aarch64.cc | 2059 SimVRegister& zd = ReadVRegister(instr->GetRd()); in Simulator() local
2071 SimVRegister& zd = ReadVRegister(instr->GetRd()); in Simulator() local
2098 SimVRegister& zd = ReadVRegister(instr->GetRd()); in Simulator() local
2143 SimVRegister& zd = ReadVRegister(instr->GetRd()); in Simulator() local
2173 SimVRegister& zd = ReadVRegister(instr->GetRd()); in Simulator() local
2256 SimVRegister& zd = ReadVRegister(instr->GetRd()); in Simulator() local
2276 SimVRegister& zd = ReadVRegister(instr->GetRd()); in Simulator() local
2305 SimVRegister& zd = ReadVRegister(instr->GetRd()); in Simulator() local
2326 SimVRegister& zd = ReadVRegister(instr->GetRd()); in Simulator() local
2350 SimVRegister& zd = ReadVRegister(instr->GetRd()); in Simulator() local
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| D | assembler-aarch64.h | 4234 void fcpy(const ZRegister& zd, const PRegisterM& pg, Float16 imm) { in fcpy()
4265 void fdup(const ZRegister& zd, Float16 imm) { in fdup()
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| D | logic-aarch64.cc | 7119 LogicVRegister zd, in SVEBitwiseLogicalUnpredicatedHelper()
7197 LogicVRegister zd, in SVEBitwiseImmHelper()
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| /third_party/ltp/tools/sparse/sparse-src/validation/ |
| D | div.c | 13 static int zd = INT_MIN % -1; variable
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| /third_party/vixl/test/aarch64/ |
| D | test-api-aarch64.cc | 845 void TestEncodable(T value, const ZRegister& zd, int64_t expected_imm) { in TestEncodable()
850 void TestUnencodable(T value, const ZRegister& zd) { in TestUnencodable()
857 bool TestImpl(T value, const ZRegister& zd, int64_t expected_imm) { in TestImpl()
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| D | test-assembler-sve-aarch64.cc | 380 ZRegister zd = z0.WithLaneSize(lane_size_in_bits); in MlaMlsHelper() local
5052 ZRegister zd = z0.WithLaneSize(lane_size_in_bits); in IntArithHelper() local
11630 int index_fn) { in SdotUdotHelper()
11646 ZRegister zd = z0.WithLaneSize(lane_size_in_bits); in SdotUdotHelper() local
12111 ZRegister zd = z29.WithLaneSize(lane_size_in_bits); in FPBinArithHelper() local
12297 ZRegister zd = z26.WithLaneSize(lane_size_in_bits); in FPBinArithHelper() local
12808 ZRegister zd = z26.WithLaneSize(lane_size_in_bits); in BitwiseShiftWideElementsHelper() local
16659 ZRegister zd = z0.WithLaneSize(lane_size_in_bits); in FPMulAccHelper() local
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| /third_party/vk-gl-cts/modules/gles2/functional/ |
| D | es2fDepthRangeTests.cpp | 105 inline float depthRangeTransform (const float zd, const float zNear, const float zFar) in depthRangeTransform()
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| /third_party/python/Objects/ |
| D | memoryobject.c | 1648 Py_ssize_t zd; in pylong_as_zd() local
1695 Py_ssize_t zd; in unpack_single() local
1785 Py_ssize_t zd; in pack_single() local
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