| /arkcompiler/runtime_core/static_core/compiler/docs/ |
| D | ir_builder.md | 10 form, without dead phi instructions, but it has various drawbacks, such as significant overhead, si…
18 - some instructions don't specify its type, f.e. `mov` instruction may produce int32 as well as flo…
21 IR ConstInst instructions.
39 3. Fixing the type uncertainties of the instructions.
43 1. Iterate over all bytecode instructions and make basic block for all target instructions, i.e. in…
51 2. If basic block is a loop header, create SafePoint and OsrSaveState instructions.
52 3. Create phi instructions for the live registers.
55 - create auxiliary instructions (SaveState, NullCheck, etc) if needed
63 **Fixing the type uncertainties of the instructions**
66 1. Split constants: for all constants that are used in instructions with different types, split con…
[all …]
|
| D | vn_doc.md | 5 …umbering sets special numbers(`vn`) to all instructions. If two instruction has equal VN, so the i…
6 At the case we move users from second instruction to first instructions(first instruction is domina…
10 Reducing the number of instructions.
18 All instructions have field `vn_`.
19 We pass through all instructions in PRO order. If the instruction has attribute NO_Cse, we set next…
20 For other instructions we save information: opcode, type, `vn` of instruction inputs, advanced prop…
21 Based on the collected information, we are looking for a equivalent instructions in the hash map.
23 1. If equivalent instructions were found:
25 …b. If all equivalent instructions do not dominate current instruction, we insert the instruction i…
26 2. If equivalent instructions weren't found, we set next `vn` to the current instruction field and …
[all …]
|
| D | escape_analysis.md | 14 …ithm initially marks all the allocations as virtual and iterates over instructions in the basic bl…
18 …virtual state (VirtualState) or implicit materialized state. Multiple instructions can share the s…
20 …truction it was originally created for and mapping between fields and instructions whose values we…
22 - avoid materialization on StoreObject/LoadObject instructions;
32 * set of phi instructions that should be inserted into each block;
39 * Allocates all required phi instructions;
41 * Replace all aliased instructions using alias mapping;
42 * Resolve inputs of all newly created phi instructions;
44 * Remove dead allocations, loads/stores and alias instructions.
78 materialize instructions associated with field
[all …]
|
| D | lse_doc.md | 4 …ion is to delete store instructions that store a value to memory that has been already written as …
8 Elimination of load and store instructions generally reduces the number of long latency memory inst…
18 …that two memory instructions access the same memory address. This can be done using alias analysi…
19 * `MUST_ALIAS` if the instructions definitely access the same memory address
20 * `NO_ALIAS` if the instructions definitely access different memory addresses.
21 * `MAY_ALIAS` if analysis can't say with confidence whether the instructions access the same memor…
27 …instructions write values on the heap, load instructions read values from the heap. But if a load …
33 Once a heap is initialized for a basic block we iterate over instructions and update heap by applyi…
36 …then the new stored value is written into heap. The values of memory instructions that `MUST_ALIA…
38 …we update heap value for this load with the result of this load. All instructions that `MUST_ALIA…
[all …]
|
| D | memory_barriers_doc.md | 5 We need to encode barriers after the instructions NewArray, NewObject, NewMultiArray so that if the…
11 Reducing the number of instructions and speed up execution.
19 There is instruction flag `MEM_BARRIER`. The flag is set to `true` for the instructions NewObject, …
21 We pass through all instructions in PRO order. If the instruction has flag `MEM_BARRIER` we add the…
29 Codegen checks the flag `MEM_BARRIER` for the instructions NewObject, NewArray and NewMultiArray an…
93 Instructions `2.ref NewArray`, `5.ref NewObject` and `10.ref NewObject` have flag `MEM_BARRIER` …
94 `7.void CallStatic` don't have the instructions `2.ref NewArray`, `5.ref NewObject` as inputs.
95 So the pass `OptimizeMemoryBarriers` will remove the flag from these instructions and skip in `10.r…
|
| D | scheduler_doc.md | 4 Rearrange adjacent instructions for better performance.
8 …instructions are executed on CPU they may stall the processor pipeline when input registers are no…
21 * It rearranges instructions only inside the basic block, but not between them
26 For each basic block we first scan instructions in reverse order marking barriers and calculating t…
27 Together with dependencies we calculate priority as a longest (critical) path to leaf instructions …
30 …. In initialization, `ready` is empty and `waiting` contains all leaf instructions (without incomi…
34 Next, we move all already available instructions (`ASAP` <= `cycle`) from `waiting` queue into `rea…
36 …t `ASAP` value for all dependent instructions and add some of them (which depend only on already s…
62 // Rearranges instructions in the basic block using list scheduling algorithm.
128 ... // Here we rearrange instructions in basic block according to sched_
[all …]
|
| D | peephole_doc.md | 6 Reducing the number of instructions.
14 Visit all instructions in PRO order.
24 * Putting constant input on second place for commutative instructions (ex. Add, Mul, ...)
25 * Grouping instructions (ex. b=a+2, c=b-4 -> c=a-2)
26 * Remove redundant instructions (ex. b=a+0, b=a&1)
27 * Replace instructions for equal but more cheap (ex. a*=4 - > a<<=2, b*=-1 -> b = -b )
28 * De Morgan rules for `and` and `or` instructions.
|
| D | code_sink_doc.md | 4 The optimization moves instructions into successor blocks, when possible, so that they are not exec…
39 …nstruction is dominated by a block that the instruction is sunk into. Instructions in a basic bloc…
41 Instructions that cannot sink:
43 * Instructions allocating memory
44 * Control flow instructions
45 * Instructions that can throw an exception
46 * Barrier instructions (calls, monitors, volatile, SafePoints, etc.)
47 * Store instructions
48 * Load instructions if they dominate in scope of current basic block:
53 To determine which load instruction can be sunk we keep a list of store instructions that have been…
[all …]
|
| /arkcompiler/runtime_core/compiler/docs/ |
| D | ir_builder.md | 10 form, without dead phi instructions, but it has various drawbacks, such as significant overhead, si…
18 - some instructions don't specify its type, f.e. `mov` instruction may produce int32 as well as flo…
21 IR ConstInst instructions.
39 3. Fixing the type uncertainties of the instructions.
43 1. Iterate over all bytecode instructions and make basic block for all target instructions, i.e. in…
51 2. If basic block is a loop header, create SafePoint and OsrSaveState instructions.
52 3. Create phi instructions for the live registers.
55 - create auxiliary instructions (SaveState, NullCheck, etc) if needed
63 **Fixing the type uncertainties of the instructions**
66 1. Split constants: for all constants that are used in instructions with different types, split con…
[all …]
|
| D | vn_doc.md | 5 …umbering sets special numbers(`vn`) to all instructions. If two instruction has equal VN, so the i…
6 At the case we move users from second instruction to first instructions(first instruction is domina…
10 Reducing the number of instructions.
18 All instructions have field `vn_`.
19 We pass through all instructions in PRO order. If the instruction has attribute NO_Cse, we set next…
20 For other instructions we save information: opcode, type, `vn` of instruction inputs, advanced prop…
21 Based on the collected information, we are looking for a equivalent instructions in the hash map.
23 1. If equivalent instructions were found:
25 …b. If all equivalent instructions do not dominate current instruction, we insert the instruction i…
26 2. If equivalent instructions weren't found, we set next `vn` to the current instruction field and …
[all …]
|
| /arkcompiler/runtime_core/isa/ |
| D | asserts.rb | 33 assert('Unique opcodes') { Panda.instructions.map(&:opcode).uniq? }
36 Panda.instructions.reject(&:prefix).size + Panda.prefixes.size <= 256
40 Panda.instructions.reject(&:prefix).sorted_by?(&:opcode_idx)
47 assert('All instructions for a prefix should fit one byte') do
49 … Panda.instructions.select { |insn| insn.prefix && (insn.prefix.name == prefix.name) }.size <= 256
54 Panda.instructions.map do |insn|
60 Panda.instructions.map do |insn|
85 uses = Panda.instructions.flat_map(&type.to_proc).uniq
93 uses = Panda.instructions.flat_map(&type.to_proc).uniq
99 assert('Format operands are parseable') { Panda.instructions.each(&:operands) }
[all …]
|
| /arkcompiler/runtime_core/static_core/isa/ |
| D | asserts.rb | 33 assert('Unique opcodes') { Panda.instructions.map(&:opcode).uniq? }
36 Panda.instructions.reject(&:prefix).size + Panda.prefixes.size <= 256
40 Panda.instructions.reject(&:prefix).sorted_by?(&:opcode_idx)
47 assert('All instructions for a prefix should fit one byte') do
49 … Panda.instructions.select { |insn| insn.prefix && (insn.prefix.name == prefix.name) }.size <= 256
54 Panda.instructions.map do |insn|
60 Panda.instructions.map do |insn|
85 uses = Panda.instructions.flat_map(&type.to_proc).uniq
93 uses = Panda.instructions.flat_map(&type.to_proc).uniq
99 assert('Format operands are parseable') { Panda.instructions.each(&:operands) }
[all …]
|
| /arkcompiler/runtime_core/docs/ |
| D | ir_format.md | 5 * Support all the features and instructions of Panda bytecode
7 * Compiler overhead about 100000 native instructions per a bytecode instruction(standard for JIT co…
63 * Common properties will be introduced for the instructions, making it easier to add new instructio…
71 Panda bytecode has more than 200 instructions. We need to convert all Bytecode instructions in IR i…
72 The specifics and properties of instructions should be taken into account in optimizations and code…
76 …zations. For this, need to support ARMv8-M Instruction Set(only those instructions that are needed)
80 IR contains high- and low-level instructions with a single interface.
82 At the second step, the instructions will be split on several low level instructions(close to assem…
87 Typically, an overhead is considered to be the average number of 'native' instructions(ARM) that ar…
93 The goal is overhead about 100000 native instructions per guest (standard for JIT compilers)
[all …]
|
| D | irtoc.md | 13 …ove the `IrConstructor`. It reads compiler's `instructions.yaml` file to get information about ins…
15 Each opcode in the IR instructions has corresponding token in the irtoc lang. For example, IR instr…
33 ### Pseudo instructions
34 Pseudo instructions are not a real IR instructions in terms of compiler, those instructions are nee…
37 Pseudo instructions are described like regular instructions in the `instructions.yaml` file, but in…
41 …e `var` holds the newly created instruction `Add` and it can be input for the further instructions.
|
| /arkcompiler/runtime_core/static_core/compiler/tests/ |
| D | iterators_test.cpp | 92 // Check InstForwardValidIterator with erasing instructions in Check()
120 // Check InstBackwardValidIterator with erasing instructions in Check()
154 void InitExpectData(std::vector<Inst *> &instructions) in InitExpectData() argument
160 for (auto inst : instructions) { in InitExpectData()
171 void PopulateBlock(BasicBlock *block, std::vector<Inst *> &instructions) in PopulateBlock() argument
173 for (auto inst : instructions) { in PopulateBlock()
197 std::vector<Inst *> instructions; in TEST_F() local
198 Check(instructions); in TEST_F()
210 std::vector<Inst *> instructions(IteratorsTest::INST_COUNT); in TEST_F() local
211 for (auto &inst : instructions) { in TEST_F()
[all …]
|
| /arkcompiler/runtime_core/compiler/tests/ |
| D | iterators_test.cpp | 92 // Check InstForwardValidIterator with erasing instructions in Check()
120 // Check InstBackwardValidIterator with erasing instructions in Check()
154 void InitExpectData(std::vector<Inst *> &instructions) in InitExpectData() argument
160 for (auto inst : instructions) { in InitExpectData()
171 void PopulateBlock(BasicBlock *block, std::vector<Inst *> &instructions) in PopulateBlock() argument
173 for (auto inst : instructions) { in PopulateBlock()
197 std::vector<Inst *> instructions; in TEST_F() local
198 Check(instructions); in TEST_F()
210 std::vector<Inst *> instructions(IteratorsTest::INST_COUNT); in TEST_F() local
211 for (auto &inst : instructions) { in TEST_F()
[all …]
|
| /arkcompiler/runtime_core/static_core/docs/ |
| D | ir_format.md | 5 * Support all the features and instructions of Panda bytecode
7 * Compiler overhead about 100000 native instructions per a bytecode instruction(standard for JIT co…
72 * Common properties will be introduced for the instructions, making it easier to add new instructio…
80 Panda bytecode has more than 200 instructions. We need to convert all Bytecode instructions in IR i…
81 The specifics and properties of instructions should be taken into account in optimizations and code…
85 …zations. For this, need to support ARMv8-M Instruction Set(only those instructions that are needed)
89 IR contains high- and low-level instructions with a single interface.
91 At the second step, the instructions will be split on several low level instructions(close to assem…
96 Typically, an overhead is considered to be the average number of 'native' instructions(ARM) that ar…
102 The goal is overhead about 100000 native instructions per guest (standard for JIT compilers)
[all …]
|
| D | irtoc.md | 13 …ove the `IrConstructor`. It reads compiler's `instructions.yaml` file to get information about ins…
15 Each opcode in the IR instructions has corresponding token in the irtoc lang. For example, IR instr…
33 ### Pseudo instructions
34 Pseudo instructions are not a real IR instructions in terms of compiler, those instructions are nee…
37 Pseudo instructions are described like regular instructions in the `instructions.yaml` file, but in…
41 …e `var` holds the newly created instruction `Add` and it can be input for the further instructions.
|
| /arkcompiler/runtime_core/static_core/irtoc/lang/ |
| D | basic_block.rb | 19 attr_reader :index, :function, :preds, :instructions accessor in BasicBlock
23 @instructions = []
33 @instructions[-1]
37 @instructions.empty?
41 !empty? && @instructions[-1].terminator?
47 @instructions.prepend(inst)
49 @instructions << inst
82 @instructions.each(&:emit_ir)
87 @instructions.each(&:generate_builder)
|
| D | instructions_data.rb | 19 @@instructions = {}
25 yaml_data['instructions'].each do |inst|
27 @@instructions[inst["opcode"].to_sym] = inst
31 @@instructions[inst["opcode"].to_sym] = inst
39 def self.instructions; @@instructions; end singletonMethod in InstructionsData
|
| /arkcompiler/runtime_core/static_core/plugins/ets/bytecode_optimizer/templates/ |
| D | ets_codegen_intrinsics_gen.inc.erb | 18 % instructions = Panda::instructions.select{ |b| b.namespace == "ets" && b.intrinsic_name }
19 % if instructions.first
20 % instructions = instructions.group_by(&:intrinsic_name)
25 % instructions.each do |intrinsic_name, group|
|
| /arkcompiler/runtime_core/static_core/verification/absint/tests/ |
| D | exec_context_test.cpp | 58 uint8_t instructions[128U]; in TEST_F() local
60 ExecContext execCtx {&instructions[0], &instructions[127U], &typeSystem}; in TEST_F()
62 std::array<const uint8_t *, 6> cp = {&instructions[8U], &instructions[17U], &instructions[23U], in TEST_F()
63 … &instructions[49U], &instructions[73U], &instructions[103U]}; in TEST_F()
94 const uint8_t *ep = &instructions[0]; in TEST_F()
|
| /arkcompiler/runtime_core/static_core/libllvmbackend/transforms/ |
| D | pipeline_irtoc.cfg | 45 instcombine, # Combine redundant instructions
60 … wrap-speculative-execution, # Speculatively execute instructions if target has divergent branches
64 instcombine, # Combine redundant instructions
81 instcombine, # Combine redundant instructions
95 instcombine, # Combine redundant instructions
108 instcombine # Combine redundant instructions
136 instcombine, # Combine redundant instructions
146 instcombine, # Combine redundant instructions
150 instcombine, # Combine redundant instructions
166 instsimplify, # Remove redundant instructions
|
| /arkcompiler/runtime_core/compiler/optimizer/templates/ |
| D | generate_ecma.inl.erb | 26 % instructions = Panda::instructions.select{|b| b.namespace == "ecmascript"}
27 % if instructions.first && instructions.first.intrinsic_name
28 % instructions = instructions.group_by(&:intrinsic_name)
30 % instructions = instructions.group_by(&:opcode)
32 % instructions.each do |intrinsic_name, group|
|
| /arkcompiler/runtime_core/tests/cts-generator/cts-template/ |
| D | monitor.yaml | 70 title: Monitor instructions
72 Monitor instructions are used to synchronize object access between threads. Each object
75 …These instructions take object reference in accumulator as input. If accumulator contains null then
91 instructions:
128 instructions:
166 instructions:
198 instructions:
238 instructions:
271 … - description: Check that a thread owns a monitor after several executed monitorexit instructions
288 …Check that a thread owns a monitor if amount of executed monitorexit instructions is less than amo…
[all …]
|