Searched full:simd (Results 1 – 25 of 2187) sorted by relevance
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77 sw::SIMD::Float sRGBtoLinear(sw::SIMD::Float c) in sRGBtoLinear()79 sw::SIMD::Float lc = c * sw::SIMD::Float(1.0f / 12.92f); in sRGBtoLinear()80 …sw::SIMD::Float ec = sw::power((c + sw::SIMD::Float(0.055f)) * sw::SIMD::Float(1.0f / 1.055f), sw:… in sRGBtoLinear()82 sw::SIMD::Int linear = CmpLT(c, sw::SIMD::Float(0.04045f)); in sRGBtoLinear()84 …return rr::As<sw::SIMD::Float>((linear & rr::As<sw::SIMD::Int>(lc)) | (~linear & rr::As<sw::SIMD::… in sRGBtoLinear()313 Array<SIMD::Float> out(4); in EmitImageSample()328 void SpirvShader::EmitImageSampleUnconditional(Array<SIMD::Float> &out, const ImageInstruction &ins… in EmitImageSampleUnconditional()362 void SpirvShader::callSamplerFunction(Pointer<Byte> samplerFunction, Array<SIMD::Float> &out, Point… in callSamplerFunction()364 Array<SIMD::Float> in(16); // Maximum 16 input parameter components. in callSamplerFunction()424 in[i] = As<SIMD::Float>(SIMD::Int(0)); in callSamplerFunction()[all …]
27 sw::SIMD::Float Interpolate(const sw::SIMD::Float &x, const sw::SIMD::Float &y, const sw::SIMD::Flo… in Interpolate()28 … const sw::SIMD::Float &A, const sw::SIMD::Float &B, const sw::SIMD::Float &C, in Interpolate()31 sw::SIMD::Float interpolant = C; in Interpolate()137 …dst.move(i, x + ((SIMD::Float(CmpLT(x, src.Float(i)) & SIMD::Int(1)) * SIMD::Float(2.0f)) - SIMD::… in EmitExtGLSLstd450()138 …SIMD::Float(CmpEQ(Frac(src.Float(i)), SIMD::Float(0.5f)) & SIMD::Int(1)) * SIMD::Float(Int4(x) & S… in EmitExtGLSLstd450()208 dst.move(i, CmpNLT(x.Float(i), edge.Float(i)) & As<SIMD::Int>(SIMD::Float(1.0f))); in EmitExtGLSLstd450()221 SIMD::Float(0.0f)), in EmitExtGLSLstd450()222 SIMD::Float(1.0f)); in EmitExtGLSLstd450()276 …auto neg = As<SIMD::Int>(CmpLT(src.Float(i), SIMD::Float(-0.0f))) & As<SIMD::Int>(SIMD::Float(-1.0… in EmitExtGLSLstd450()277 …auto pos = As<SIMD::Int>(CmpNLE(src.Float(i), SIMD::Float(+0.0f))) & As<SIMD::Int>(SIMD::Float(1.0… in EmitExtGLSLstd450()[all …]
86 // SIMD contains types that represent multiple scalars packed into a single87 // vector data type. Types in the SIMD namespace provide a semantic hint90 namespace SIMD { namespace92 // Width is the number of per-lane scalars packed into each SIMD vector.103 Pointer(rr::Pointer<Byte> base, rr::Int limit, SIMD::Int offset);104 Pointer(rr::Pointer<Byte> base, unsigned int limit, SIMD::Int offset);109 Pointer operator+(SIMD::Int i);110 Pointer operator*(SIMD::Int i);118 SIMD::Int offsets() const;120 SIMD::Int isInBounds(unsigned int accessSize, OutOfBoundsBehavior robustness) const;[all …]
24 // |TYPE| should be the type of the binary operation (as a SIMD::<ScalarType>).41 …auto mask = As<SIMD::UInt>(state->activeLaneMask()); // Considers helper invocations active. See … in BinaryOperation()43 SIMD::UInt v_uint = (value.UInt(i) & mask) | (As<SIMD::UInt>(identity) & ~mask); in BinaryOperation()81 …static_assert(SIMD::Width == 4, "EmitGroupNonUniform makes many assumptions that the SIMD vector w… in EmitGroupNonUniform()96 …SIMD::Int active = state->activeLaneMask(); // Considers helper invocations active. See b/1511370… in EmitGroupNonUniform()99 auto v0111 = SIMD::Int(0, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); in EmitGroupNonUniform()108 …dst.move(0, AndAll(predicate.UInt(0) | ~As<SIMD::UInt>(state->activeLaneMask()))); // Considers h… in EmitGroupNonUniform()115 …dst.move(0, OrAll(predicate.UInt(0) & As<SIMD::UInt>(state->activeLaneMask()))); // Considers hel… in EmitGroupNonUniform()122 auto res = SIMD::UInt(0xffffffff); in EmitGroupNonUniform()123 …SIMD::UInt active = As<SIMD::UInt>(state->activeLaneMask()); // Considers helper invocations acti… in EmitGroupNonUniform()[all …]
561 SIMD::UInt halfToFloatBits(SIMD::UInt halfBits) in halfToFloatBits()563 auto magic = SIMD::UInt(126 << 23); in halfToFloatBits()565 auto sign16 = halfBits & SIMD::UInt(0x8000); in halfToFloatBits()566 auto man16 = halfBits & SIMD::UInt(0x03FF); in halfToFloatBits()567 auto exp16 = halfBits & SIMD::UInt(0x7C00); in halfToFloatBits()569 auto isDnormOrZero = CmpEQ(exp16, SIMD::UInt(0)); in halfToFloatBits()570 auto isInfOrNaN = CmpEQ(exp16, SIMD::UInt(0x7C00)); in halfToFloatBits()574 auto exp32 = (exp16 + SIMD::UInt(0x1C000)) << 13; in halfToFloatBits()575 auto norm32 = (man32 | exp32) | (isInfOrNaN & SIMD::UInt(0x7F800000)); in halfToFloatBits()577 auto denorm32 = As<SIMD::UInt>(As<SIMD::Float>(magic + man16) - As<SIMD::Float>(magic)); in halfToFloatBits()[all …]
74 …:BuiltInNumWorkgroups, [&](const SpirvShader::BuiltinMapping &builtin, Array<SIMD::Float> &value) { in setWorkgroupBuiltins()78 As<SIMD::Float>(SIMD::Int(Extract(routine->numWorkgroups, component))); in setWorkgroupBuiltins()82 …v::BuiltInWorkgroupId, [&](const SpirvShader::BuiltinMapping &builtin, Array<SIMD::Float> &value) { in setWorkgroupBuiltins()86 As<SIMD::Float>(SIMD::Int(workgroupID[component])); in setWorkgroupBuiltins()90 …:BuiltInWorkgroupSize, [&](const SpirvShader::BuiltinMapping &builtin, Array<SIMD::Float> &value) { in setWorkgroupBuiltins()94 As<SIMD::Float>(SIMD::Int(Extract(routine->workgroupSize, component))); in setWorkgroupBuiltins()98 …::BuiltInNumSubgroups, [&](const SpirvShader::BuiltinMapping &builtin, Array<SIMD::Float> &value) { in setWorkgroupBuiltins()100 value[builtin.FirstComponent] = As<SIMD::Float>(SIMD::Int(routine->subgroupsPerWorkgroup)); in setWorkgroupBuiltins()103 …::BuiltInSubgroupSize, [&](const SpirvShader::BuiltinMapping &builtin, Array<SIMD::Float> &value) { in setWorkgroupBuiltins()105 value[builtin.FirstComponent] = As<SIMD::Float>(SIMD::Int(routine->invocationsPerSubgroup)); in setWorkgroupBuiltins()[all …]
48 SIMD::Float v = lhs.Float(i) * rhs.Float(0); in EmitMatrixTimesVector()68 SIMD::Float v = lhs.Float(0) * rhs.Float(i * lhs.componentCount); in EmitVectorTimesMatrix()94 SIMD::Float v = SIMD::Float(0); in EmitMatrixTimesMatrix()166 auto one = SIMD::UInt(1); in EmitUnaryOp()177 auto one = SIMD::UInt(1); in EmitUnaryOp()179 SIMD::UInt out = (v >> offset) & Bitmask32(count); in EmitUnaryOp()195 SIMD::UInt v = src.UInt(i); in EmitUnaryOp()196 v = ((v >> 1) & SIMD::UInt(0x55555555)) | ((v & SIMD::UInt(0x55555555)) << 1); in EmitUnaryOp()197 v = ((v >> 2) & SIMD::UInt(0x33333333)) | ((v & SIMD::UInt(0x33333333)) << 2); in EmitUnaryOp()198 v = ((v >> 4) & SIMD::UInt(0x0F0F0F0F)) | ((v & SIMD::UInt(0x0F0F0F0F)) << 4); in EmitUnaryOp()[all …]
92 routine.fragCoord[0] = SIMD::Float(Float(x)) + SIMD::Float(x0, x1, x0, x1); in setBuiltins()93 routine.fragCoord[1] = SIMD::Float(Float(y)) + SIMD::Float(y0, y0, y1, y1); in setBuiltins()97 routine.invocationsPerSubgroup = SIMD::Width; in setBuiltins()99 routine.windowSpacePosition[0] = x + SIMD::Int(0, 1, 0, 1); in setBuiltins()100 routine.windowSpacePosition[1] = y + SIMD::Int(0, 0, 1, 1); in setBuiltins()105 …SIMD::Float pointSizeInv = SIMD::Float(*Pointer<Float>(primitive + OFFSET(Primitive, pointSizeInv)… in setBuiltins()106 …routine.pointCoord[0] = SIMD::Float(0.5f) + pointSizeInv * (((SIMD::Float(Float(x)) + SIMD::Float(… in setBuiltins()107 …routine.pointCoord[1] = SIMD::Float(0.5f) + pointSizeInv * (((SIMD::Float(Float(y)) + SIMD::Float(… in setBuiltins()109 …spv::BuiltInViewIndex, [&](const SpirvShader::BuiltinMapping &builtin, Array<SIMD::Float> &value) { in setBuiltins()111 value[builtin.FirstComponent] = As<SIMD::Float>(SIMD::Int(routine.viewID)); in setBuiltins()[all …]
42 …spv::BuiltInViewIndex, [&](const SpirvShader::BuiltinMapping &builtin, Array<SIMD::Float> &value) { in VertexProgram()44 value[builtin.FirstComponent] = As<SIMD::Float>(SIMD::Int(routine.viewID)); in VertexProgram()47 …:BuiltInInstanceIndex, [&](const SpirvShader::BuiltinMapping &builtin, Array<SIMD::Float> &value) { in VertexProgram()50 value[builtin.FirstComponent] = As<SIMD::Float>(SIMD::Int(routine.instanceID)); in VertexProgram()53 …::BuiltInSubgroupSize, [&](const SpirvShader::BuiltinMapping &builtin, Array<SIMD::Float> &value) { in VertexProgram()55 value[builtin.FirstComponent] = As<SIMD::Float>(SIMD::Int(SIMD::Width)); in VertexProgram()71 routine.vertexIndex = *Pointer<SIMD::Int>(As<Pointer<SIMD::Int>>(batch)) + in program()72 SIMD::Int(*Pointer<Int>(data + OFFSET(DrawData, baseVertex))); in program()79 As<SIMD::Float>(routine.vertexIndex); in program()82 auto activeLaneMask = SIMD::Int(0xFFFFFFFF); in program()
98 …void move(uint32_t i, RValue<SIMD::Float> &&scalar) { emplace(i, scalar.value(), TypeHint::Float);… in move()99 void move(uint32_t i, RValue<SIMD::Int> &&scalar) { emplace(i, scalar.value(), TypeHint::Int); } in move()100 void move(uint32_t i, RValue<SIMD::UInt> &&scalar) { emplace(i, scalar.value(), TypeHint::UInt); } in move()102 …void move(uint32_t i, const RValue<SIMD::Float> &scalar) { emplace(i, scalar.value(), TypeHint::Fl… in move()103 …void move(uint32_t i, const RValue<SIMD::Int> &scalar) { emplace(i, scalar.value(), TypeHint::Int)… in move()104 …void move(uint32_t i, const RValue<SIMD::UInt> &scalar) { emplace(i, scalar.value(), TypeHint::UIn… in move()107 RValue<SIMD::Float> Float(uint32_t i) const in Float()111 return As<SIMD::Float>(scalar[i]); // TODO(b/128539387): RValue<SIMD::Float>(scalar) in Float()114 RValue<SIMD::Int> Int(uint32_t i) const in Int()118 return As<SIMD::Int>(scalar[i]); // TODO(b/128539387): RValue<SIMD::Int>(scalar) in Int()[all …]
131 …rr::Function<Void(Pointer<Byte>, Pointer<SIMD::Float>, Pointer<SIMD::Float>, Pointer<Byte>)> funct… in emitWriteRoutine()134 Pointer<SIMD::Float> coord = function.Arg<1>(); in emitWriteRoutine()135 Pointer<SIMD::Float> texelAndMask = function.Arg<2>(); in emitWriteRoutine()147 …rr::Function<Void(Pointer<Byte>, Pointer<SIMD::Float>, Pointer<SIMD::Float>, Pointer<Byte>)> funct… in emitSamplerRoutine()150 Pointer<SIMD::Float> in = function.Arg<1>(); in emitSamplerRoutine()151 Pointer<SIMD::Float> out = function.Arg<2>(); in emitSamplerRoutine()154 SIMD::Float uvwa[4]; in emitSamplerRoutine()155 SIMD::Float dRef; in emitSamplerRoutine()156 …SIMD::Float lodOrBias; // Explicit level-of-detail, or bias added to the implicit level-of-detail… in emitSamplerRoutine()160 SIMD::Int sampleId; in emitSamplerRoutine()[all …]
31 include_dirs = [ "simd/nasm/" ]34 include_dirs += [ "simd/i386/" ]36 "simd/i386/jccolor-avx2.asm",37 "simd/i386/jccolor-mmx.asm",38 "simd/i386/jccolor-sse2.asm",39 "simd/i386/jcgray-avx2.asm",40 "simd/i386/jcgray-mmx.asm",41 "simd/i386/jcgray-sse2.asm",42 "simd/i386/jchuff-sse2.asm",43 "simd/i386/jcphuff-sse2.asm",[all …]
pax_global_header libjpeg-turbo-2.1.1/ libjpeg-turbo-2.1.1/BUILDING. ...
78 "${target_gen_dir}/libjpeg-turbo-2.1.1/simd/arm/jcgray-neon.c",79 "${target_gen_dir}/libjpeg-turbo-2.1.1/simd/arm/jcphuff-neon.c",80 "${target_gen_dir}/libjpeg-turbo-2.1.1/simd/arm/jcsample-neon.c",81 "${target_gen_dir}/libjpeg-turbo-2.1.1/simd/arm/jdmerge-neon.c",82 "${target_gen_dir}/libjpeg-turbo-2.1.1/simd/arm/jdsample-neon.c",83 "${target_gen_dir}/libjpeg-turbo-2.1.1/simd/arm/jfdctfst-neon.c",84 "${target_gen_dir}/libjpeg-turbo-2.1.1/simd/arm/jidctred-neon.c",85 "${target_gen_dir}/libjpeg-turbo-2.1.1/simd/arm/jquanti-neon.c",90 "${target_gen_dir}/libjpeg-turbo-2.1.1/simd/arm/jccolor-neon.c",91 "${target_gen_dir}/libjpeg-turbo-2.1.1/simd/arm/jidctfst-neon.c",[all …]
182 /* Not using SIMD, so alignment is not needed */222 /* Not using SIMD, so alignment is not needed */268 * Based on the x86 SIMD extension for IJG JPEG library,287 diff --git a/simd/arm/aarch32/jsimd.c b/simd/arm/aarch32/jsimd.c289 --- a/simd/arm/aarch32/jsimd.c290 +++ b/simd/arm/aarch32/jsimd.c318 diff --git a/simd/arm/aarch64/jsimd.c b/simd/arm/aarch64/jsimd.c320 --- a/simd/arm/aarch64/jsimd.c321 +++ b/simd/arm/aarch64/jsimd.c330 * Based on the x86 SIMD extension for IJG JPEG library,[all …]
51 unsigned simd, in brw_simd_should_compile() argument58 assert(!test_bit(prog_data->prog_mask, simd)); in brw_simd_should_compile()61 const unsigned width = 8u << simd; in brw_simd_should_compile()69 if (test_bit(prog_data->prog_spilled, simd)) { in brw_simd_should_compile()71 mem_ctx, "SIMD%u skipped because would spill", width); in brw_simd_should_compile()83 mem_ctx, "SIMD%u skipped because required dispatch width is %u", in brw_simd_should_compile()88 if (simd > 0 && test_bit(prog_data->prog_mask, simd - 1) && in brw_simd_should_compile()91 mem_ctx, "SIMD%u skipped because workgroup size %u already fits in SIMD%u", in brw_simd_should_compile()98 mem_ctx, "SIMD%u can't fit all %u invocations in %u threads", in brw_simd_should_compile()122 if (unlikely(env_skip[simd])) { in brw_simd_should_compile()[all …]
101 "../externals/libjpeg-turbo/simd/arm/jccolor-neon.c",102 "../externals/libjpeg-turbo/simd/arm/jcgray-neon.c",103 "../externals/libjpeg-turbo/simd/arm/jcphuff-neon.c",104 "../externals/libjpeg-turbo/simd/arm/jcsample-neon.c",105 "../externals/libjpeg-turbo/simd/arm/jdcolor-neon.c",106 "../externals/libjpeg-turbo/simd/arm/jdmerge-neon.c",107 "../externals/libjpeg-turbo/simd/arm/jdsample-neon.c",108 "../externals/libjpeg-turbo/simd/arm/jfdctfst-neon.c",109 "../externals/libjpeg-turbo/simd/arm/jfdctint-neon.c",110 "../externals/libjpeg-turbo/simd/arm/jidctfst-neon.c",[all …]
63 single-instruction multiple-data (SIMD) processor. The set of shader74 non-compute shader invocations and execute them in a SIMD fashion. When83 where <condition> diverges between invocations, a SIMD implementation92 evaluting a condition across an entire SIMD invocation group using code145 multiple shader invocations for a single shader stage into a single SIMD185 For fragment shaders, invocations in a SIMD invocation group may include224 SIMD workgroup size and/or the "location" of a single invocation225 within a fixed-size SIMD workgroup?230 SIMD workgroups?243 workgroup and the SIMD invocation group across which conditions are[all …]
53 single-instruction multiple-data (SIMD) processor. The set of shader64 non-compute shader invocations and execute them in a SIMD fashion. When73 where <condition> diverges between invocations, a SIMD implementation82 evaluting a condition across an entire SIMD invocation group using code135 multiple shader invocations for a single shader stage into a single SIMD175 For fragment shaders, invocations in a SIMD invocation group may include214 SIMD work group size and/or the "location" of a single invocation215 within a fixed-size SIMD work group?220 SIMD work groups?233 group and the SIMD invocation group across which conditions are[all …]
11 // - Lines with "//GOOD" are compatible with WASM SIMD and are automatically compiled12 // into WASM SIMD operations by emscripten.14 // - Lines with "GOOD (FIXED)" are compatible with WASM SIMD but are NOT automatically15 // compiled into WASM SIMD operations by emscripten. Special WASM SIMD intrinsics have been16 // specified in skia/include/private/SkVx.h to tell emscripten how to compile them to WASM SIMD18 // - Lines with "//not available in wasm" do not have compatible WASM SIMD operations. Emscripten19 // compiles these operations into non-SIMD WASM.20 // - Lines with "//???" may be more complex and it is not clear if they have compatible WASM SIMD24 // 1. Reference https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md26 // to check if a WASM SIMD operation exists which correspond to any given line of code.[all …]
8 # textual representations of all wasm SIMD operations present in the compiled .wasm, and starts18 # - Chrome Canary 86.0.4186.0 with chrome://flags#enable-webassembly-simd enabled20 # build the file specified as the first argument with SIMD enabled.23 wasm2wat --enable-simd output/simd_test.wasm > output/simd_test.wat25 # The following lines output all SIMD operations produced in the output WASM.26 # Useful for checking that SIMD instructions are actually being used.30 echo "The following WASM SIMD operations were used in the compiled code:"35 or later and enable the chrome://flags#enable-webassembly-simd flag!"
29 __OMP_DIRECTIVE(simd)54 __OMP_DIRECTIVE_EXT(parallel_for_simd, "parallel for simd")57 __OMP_DIRECTIVE_EXT(for_simd, "for simd")61 __OMP_DIRECTIVE_EXT(declare_simd, "declare simd")63 __OMP_DIRECTIVE_EXT(taskloop_simd, "taskloop simd")69 "distribute parallel for simd")70 __OMP_DIRECTIVE_EXT(distribute_simd, "distribute simd")71 __OMP_DIRECTIVE_EXT(target_parallel_for_simd, "target parallel for simd")72 __OMP_DIRECTIVE_EXT(target_simd, "target simd")74 __OMP_DIRECTIVE_EXT(teams_distribute_simd, "teams distribute simd")[all …]
510 'base/simd/convert_rgb_to_yuv_c.cc',511 'base/simd/convert_rgb_to_yuv_sse2.cc',512 'base/simd/convert_rgb_to_yuv_ssse3.asm',513 'base/simd/convert_rgb_to_yuv_ssse3.cc',514 'base/simd/convert_rgb_to_yuv_ssse3.inc',515 'base/simd/convert_yuv_to_rgb_c.cc',516 'base/simd/convert_yuv_to_rgb_x86.cc',517 'base/simd/convert_yuv_to_rgb_mmx.asm',518 'base/simd/convert_yuv_to_rgb_mmx.inc',519 'base/simd/convert_yuv_to_rgb_sse.asm',[all …]