1 /* 2 * Copyright (C) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 17 */ 18 19 #ifndef _DRM_HAL_GFX_H__ 20 #define _DRM_HAL_GFX_H__ 21 22 #include "drm_hal_common.h" 23 #include "hi_osal.h" 24 25 #ifdef __cplusplus 26 #if __cplusplus 27 extern "C"{ 28 #endif 29 #endif /* __cplusplus */ 30 31 #define DRM_HAL_GFX_MAX_FORMAT_NUM 16 32 33 enum drm_hal_gfx_attr_type { 34 DRM_HAL_GFX_ATTR_SIZE, /* param is pointer to struct drm_hal_rect */ 35 DRM_HAL_GFX_ATTR_ALPHA, 36 DRM_HAL_GFX_ATTR_ZPOS, 37 DRM_HAL_GFX_ATTR_FORMAT, /* param is pointer to enum drm_hal_color_fmt */ 38 DRM_HAL_GFX_ATTR_CS, /* color space */ 39 DRM_HAL_GFX_ATTR_STRIDE, /* param is pointer to unsigned int */ 40 DRM_HAL_GFX_ATTR_BUFFER, /* buffer address */ 41 DRM_HAL_GFX_ATTR_MAX 42 }; 43 44 struct drm_hal_gfx_layer_capability { 45 int available; /* does this layer available for this SOC */ 46 int max_w; 47 int max_h; 48 enum drm_hal_color_fmt formats[DRM_HAL_GFX_MAX_FORMAT_NUM]; /* supported formats of this layer */ 49 int format_num; 50 enum drm_hal_disp_chn connected_disp_chn; /* which disp channel does this layer belongs to */ 51 }; 52 53 struct drm_hal_gfx_capability { 54 struct drm_hal_gfx_layer_capability layer_cap[DRM_HAL_GFX_MAX]; 55 }; 56 57 enum drm_hal_gfx_cb_type { 58 DRM_HAL_GFX_CB_INTR_0, 59 DRM_HAL_GFX_CB_INTR_90, 60 DRM_HAL_GFX_CB_INTR_100, 61 DRM_HAL_GFX_CB_INTR_MAX 62 }; 63 64 typedef int (*drm_hal_gfx_cb)(enum drm_hal_gfx_layer layer, enum drm_hal_gfx_cb_type type, void *para); 65 66 struct drm_hal_gfx_dev { 67 void (*deinit)(void); 68 int (*open)(enum drm_hal_gfx_layer layer); 69 int (*close)(enum drm_hal_gfx_layer layer); 70 int (*enable)(enum drm_hal_gfx_layer layer); 71 int (*disable)(enum drm_hal_gfx_layer layer); 72 int (*get_attr)(enum drm_hal_gfx_layer layer, enum drm_hal_gfx_attr_type type, const void *param); 73 int (*set_attr)(enum drm_hal_gfx_layer layer, enum drm_hal_gfx_attr_type type, const void *param); 74 int (*register_cb)(enum drm_hal_gfx_layer layer, enum drm_hal_gfx_cb_type type, drm_hal_gfx_cb cb); 75 int (*unregister_cb)(enum drm_hal_gfx_layer layer, enum drm_hal_gfx_cb_type type); 76 int (*refresh)(enum drm_hal_gfx_layer layer); 77 void *params; /* for internal use */ 78 osal_spinlock_t lock; 79 }; 80 81 #ifdef __cplusplus 82 #if __cplusplus 83 } 84 #endif 85 #endif /* __cplusplus */ 86 87 #endif /* _DRM_HAL_GFX_H__ */ 88 89