1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_xqspi.h
5 * @author BLE SDK Team
6 * @brief Header file containing functions prototypes of XQSPI LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_XQSPI XQSPI
47 * @brief XQSPI LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_LL_XQSPI_H__
53 #define __GR55xx_LL_XQSPI_H__
54
55 /* Includes ------------------------------------------------------------------*/
56 #include "gr55xx.h"
57
58 #ifdef __cplusplus
59 extern "C" {
60 #endif
61
62 #if defined (XQSPI)
63
64 /** @defgroup LL_XQSPI_DRIVER_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup XQSPI_LL_ES_INIT XQSPI Exported init structure
70 * @{
71 */
72
73 /**
74 * @brief XQSPI init structures definition
75 */
76 typedef struct _ll_xqspi_init_t {
77 uint32_t mode; /**< Specifies the work mode, XIP mode or QSPI mode.
78 This parameter can be a value of @ref XQSPI_LL_EC_MODE. */
79
80 uint32_t cache_mode; /**< Specifies the cache mode in XIP mode.
81 This parameter can be a value of @ref XQSPI_LL_EC_CACHE_MODE.
82 This feature can be
83 modified afterwards using
84 unitary function
85 @ref ll_xqspi_enable_cache(). */
86
87 uint32_t read_cmd; /**< Specifies the XQSPI read command in XIP mode.
88 This parameter can be a value of @ref XQSPI_LL_EC_XIP_READ_CMD.
89 This feature can be
90 modified afterwards using
91 unitary function
92 @ref ll_xqspi_set_xip_cmd(). */
93
94 uint32_t data_size; /**< Specifies the XQSPI data width, only in QSPI mode.
95 This parameter can be a value of @ref XQSPI_LL_EC_QSPI_DATASIZE.
96 This feature can be
97 modified afterwards using
98 unitary function
99 @ref ll_xqspi_set_qspi_datasize(). */
100
101 uint32_t data_order; /**< Specifies the XQSPI data order, MSB oe LSB, only in QSPI mode.
102 This parameter can be a value of @ref XQSPI_LL_EC_QSPI_DATAORDER.
103 This feature can be
104 modified afterwards using
105 unitary function
106 @ref ll_xqspi_set_qspi_data_order(). */
107
108 uint32_t clock_polarity; /**< Specifies the serial clock steady state.
109 This parameter can be a
110 value of @ref
111 XQSPI_LL_EC_QSPI_POLARITY
112 in XIP mode
113 or @ref XQSPI_LL_EC_QSPI_POLARITY in QSPI mode.
114 This feature can be modified afterwards using unitary function
115 @ref ll_xqspi_set_xip_cpol() or @ref ll_xqspi_set_qspi_cpol(). */
116
117 uint32_t clock_phase; /**< Specifies the clock active edge for the bit capture.
118 This parameter can be a
119 value of @ref
120 XQSPI_LL_EC_QSPI_PHASE in
121 XIP mode
122 or @ref XQSPI_LL_EC_QSPI_PHASE in QSPI mode.
123 This feature can be modified afterwards using unitary function
124 @ref ll_xqspi_set_xip_cpha() or @ref ll_xqspi_set_qspi_cpha(). */
125
126 uint32_t baud_rate; /**< Specifies the BaudRate be used to configure the transmit and
127 receive SCK clock.
128 This parameter can be a value of @ref XQSPI_LL_EC_QSPI_BAUD_REAT.
129 This feature can be modified afterwards using unitary function
130 @ref ll_xqspi_set_qspi_speed(). */
131 } ll_xqspi_init_t;
132
133 /** @} */
134
135 /** @} */
136
137 /**
138 * @defgroup XQSPI_LL_MACRO Defines
139 * @{
140 */
141
142 /* Exported constants --------------------------------------------------------*/
143 /** @defgroup XQSPI_LL_Exported_Constants XQSPI Exported Constants
144 * @{
145 */
146
147 /** @defgroup XQSPI_LL_EC_MODE XQSPI work mode
148 * @{
149 */
150 #define LL_XQSPI_MODE_XIP 0 /**< XIP mode */
151 #define LL_XQSPI_MODE_QSPI 1 /**< QSPI mode */
152 /** @} */
153
154 /** @defgroup XQSPI_LL_EC_XIP_READ_CMD XIP read command
155 * @{
156 */
157 #define LL_XQSPI_XIP_CMD_READ 0x03 /**< Read mode */
158 #define LL_XQSPI_XIP_CMD_FAST_READ 0x0B /**< Fast Read mode */
159 #define LL_XQSPI_XIP_CMD_DUAL_OUT_READ 0x3B /**< Dual-Out Fast Read mode */
160 #define LL_XQSPI_XIP_CMD_DUAL_IO_READ 0xBB /**< Dual-IO Fast Read mode */
161 #define LL_XQSPI_XIP_CMD_QUAD_OUT_READ 0x6B /**< Quad-Out Fast Read mode */
162 #define LL_XQSPI_XIP_CMD_QUAD_IO_READ 0xEB /**< Quad-IO Fast Read mode */
163 /** @} */
164
165 /** @defgroup XQSPI_LL_EC_XIP_SS Slave select
166 * @{
167 */
168 #define LL_XQSPI_XIP_SS0 (1UL << XQSPI_XIP_CFG_SS_Pos) /**< Slave select 0 */
169 #define LL_XQSPI_XIP_SS1 (2UL << XQSPI_XIP_CFG_SS_Pos) /**< Slave select 1 */
170 #define LL_XQSPI_XIP_SS2 (4UL << XQSPI_XIP_CFG_SS_Pos) /**< Slave select 2 */
171 #define LL_XQSPI_XIP_SS3 (8UL << XQSPI_XIP_CFG_SS_Pos) /**< Slave select 3 */
172 /** @} */
173
174 /** @defgroup XQSPI_LL_EC_XIP_ADDR_MODE Address bytes in command
175 * @{
176 */
177 #define LL_XQSPI_XIP_ADDR_3BYTES 0x00000000UL /**< Address command is 3 bytes */
178 #define LL_XQSPI_XIP_ADDR_4BYTES XQSPI_XIP_CFG_ADDR4 /**< Address command is 4 bytes */
179 /** @} */
180
181 /** @defgroup XQSPI_LL_EC_XIP_ENDIAN Read data endian mode
182 * @{
183 */
184 #define LL_XQSPI_XIP_ENDIAN_BIG 0x00000000UL /**< Read data in big endian */
185 #define LL_XQSPI_XIP_ENDIAN_LITTLE XQSPI_XIP_CFG_LE32 /**< Read data in little endian */
186 /** @} */
187
188 /** @defgroup XQSPI_LL_EC_CACHE_MODE XIP cache mode
189 * @{
190 */
191 #define LL_XQSPI_CACHE_DIS 0 /**< Cache OFF */
192 #define LL_XQSPI_CACHE_EN 1 /**< Cache ON */
193 /** @} */
194
195 /** @defgroup XQSPI_LL_EC_CACHE_FIFO_MODE Cache FIFO mode
196 * @{
197 */
198 #define LL_XQSPI_CACHE_FIFO_NORMAL 0x00000000UL /**< FIFO in normal mode */
199 #define LL_XQSPI_CACHE_FIFO_CLEAR XQSPI_CACHE_CTRL0_FIFO /**< FIFO in clear mode */
200 /** @} */
201
202 /** @defgroup XQSPI_LL_EC_CACHE_HITMISS_COUNTER_MODE Cache hit/miss counters mode
203 * @{
204 */
205 #define LL_XQSPI_CACHE_HITMISS_NORMAL 0x00000000UL /**< Hit/Miss counters in normal mode */
206 #define LL_XQSPI_CACHE_HITMISS_CLEAR XQSPI_CACHE_CTRL0_HITMISS /**< Hit/Miss counters in clear mode */
207 /** @} */
208
209 /** @defgroup XQSPI_LL_EC_QSPI_FLAG QSPI Flags Defines
210 * @brief Flags defines which can be used with LL_XQSPI_ReadReg function
211 * @{
212 */
213 #define LL_XQSPI_QSPI_STAT_RFTF XQSPI_QSPI_STAT_RXWMARK /**< Rx FIFO watermark flag */
214 #define LL_XQSPI_QSPI_STAT_RFF XQSPI_QSPI_STAT_RXFULL /**< Rx FIFO full flag */
215 #define LL_XQSPI_QSPI_STAT_RFE XQSPI_QSPI_STAT_RXEMPTY /**< Rx FIFO empty flag */
216 #define LL_XQSPI_QSPI_STAT_TFTF XQSPI_QSPI_STAT_TXWMARK /**< Tx FIFO watermark flag */
217 #define LL_XQSPI_QSPI_STAT_TFF XQSPI_QSPI_STAT_TXFULL /**< Tx FIFO full flag */
218 #define LL_XQSPI_QSPI_STAT_TFE XQSPI_QSPI_STAT_TXEMPTY /**< Tx FIFO empty flag */
219 #define LL_XQSPI_QSPI_STAT_BUSY XQSPI_QSPI_STAT_XFERIP /**< Busy flag */
220 /** @} */
221
222 /** @defgroup XQSPI_LL_EC_QSPI_IT QSPI interrupt Defines
223 * @brief Interrupt defines which can be used with LL_XQSPI_ReadReg and LL_XQSPI_WriteReg functions
224 * @{
225 */
226 #define LL_XQSPI_QSPI_IM_DONE XQSPI_QSPI_XFER_DPULSE_Msk /**< Transmite Done Interrupt enable */
227 #define LL_XQSPI_QSPI_IM_RFF XQSPI_QSPI_RX_FPULSE_Msk /**< Receive FIFO Full Interrupt enable */
228 #define LL_XQSPI_QSPI_IM_RFTF XQSPI_QSPI_RX_WPULSE_Msk /**< Receive FIFO Watermark Interrupt
229 enable */
230 #define LL_XQSPI_QSPI_IM_TFTF XQSPI_QSPI_TX_WPULSE_Msk /**< Transmit FIFO Watermark Interrupt
231 enable */
232 #define LL_XQSPI_QSPI_IM_TFE XQSPI_QSPI_TX_EPULSE_Msk /**< Transmit FIFO Empty Interrupt enable */
233
234 #define LL_XQSPI_QSPI_IS_DONE XQSPI_QSPI_XFER_DPULSE_Msk /**< Transmite Done Interrupt flag */
235 #define LL_XQSPI_QSPI_IS_RFF XQSPI_QSPI_RX_FPULSE_Msk /**< Receive FIFO Full Interrupt flag */
236 #define LL_XQSPI_QSPI_IS_RFTF XQSPI_QSPI_RX_WPULSE_Msk /**< Receive FIFO Watermark Interrupt flag */
237 #define LL_XQSPI_QSPI_IS_TFTF XQSPI_QSPI_TX_WPULSE_Msk /**< Transmit FIFO Watermark Interrupt
238 flag */
239 #define LL_XQSPI_QSPI_IS_TFE XQSPI_QSPI_TX_EPULSE_Msk /**< Transmit FIFO Empty Interrupt flag */
240 /** @} */
241
242 /** @defgroup XQSPI_LL_EC_QSPI_FIFO_WATERMARK QSPI FIFO Watermark
243 * @{
244 */
245 #define LL_XQSPI_QSPI_FIFO_WATERMARK_1_8 0UL /**< FIFO depth/8 */
246 #define LL_XQSPI_QSPI_FIFO_WATERMARK_1_4 1UL /**< FIFO depth/4 */
247 #define LL_XQSPI_QSPI_FIFO_WATERMARK_1_2 2UL /**< FIFO depth/2 */
248 #define LL_XQSPI_QSPI_FIFO_WATERMARK_3_4 3UL /**< FIFO depth*3/4 */
249 #define LL_XQSPI_QSPI_FIFO_DEPTH 16UL /**< FIFO full depth */
250 /** @} */
251
252 /** @defgroup XQSPI_LL_EC_QSPI_FRAMEFORMAT QSPI Frame Format
253 * @{
254 */
255 #define LL_XQSPI_QSPI_FRF_SPI 0x00000000UL /**< SPI frame format for
256 transfer */
257 #define LL_XQSPI_QSPI_FRF_DUALSPI (2UL << XQSPI_QSPI_AUXCTRL_QMODE_Pos) /**< Dual-SPI frame format
258 for transfer */
259 #define LL_XQSPI_QSPI_FRF_QUADSPI (3UL << XQSPI_QSPI_AUXCTRL_QMODE_Pos) /**< Quad-SPI frame format
260 for transfer */
261 /** @} */
262
263 /** @defgroup XQSPI_LL_EC_QSPI_DATAORDER QSPI Data Order
264 * @{
265 */
266 #define LL_XQSPI_QSPI_LSB 0x00000000UL /**< LSB first for transfer */
267 #define LL_XQSPI_QSPI_MSB XQSPI_QSPI_CTRL_MSB1ST /**< MSB first for transfer */
268 /** @} */
269
270 /** @defgroup XQSPI_LL_EC_QSPI_DATASIZE QSPI Datawidth
271 * @{
272 */
273 #define LL_XQSPI_QSPI_DATASIZE_4BIT 0x00000000UL /**< Data length for XQSPI
274 transfer: 4 bits */
275 #define LL_XQSPI_QSPI_DATASIZE_8BIT (1UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos) /**< Data length for XQSPI
276 transfer: 8 bits */
277 #define LL_XQSPI_QSPI_DATASIZE_12BIT (2UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos) /**< Data length for XQSPI
278 transfer: 12 bits */
279 #define LL_XQSPI_QSPI_DATASIZE_16BIT (3UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos) /**< Data length for XQSPI
280 transfer: 16 bits */
281 #define LL_XQSPI_QSPI_DATASIZE_20BIT (4UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos) /**< Data length for XQSPI
282 transfer: 20 bits */
283 #define LL_XQSPI_QSPI_DATASIZE_24BIT (5UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos) /**< Data length for XQSPI
284 transfer: 24 bits */
285 #define LL_XQSPI_QSPI_DATASIZE_28BIT (6UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos) /**< Data length for XQSPI
286 transfer: 28 bits */
287 #define LL_XQSPI_QSPI_DATASIZE_32BIT (7UL << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos) /**< Data length for XQSPI
288 transfer: 32 bits */
289 /** @} */
290
291 /** @defgroup XQSPI_LL_EC_QSPI_PHASE QSPI Clock Phase
292 * @{
293 */
294 #define LL_XQSPI_SCPHA_1EDGE 0 /**< First clock transition is the first data capture edge */
295 #define LL_XQSPI_SCPHA_2EDGE 1 /**< Second clock transition is the first data capture edge */
296 /** @} */
297
298 /** @defgroup XQSPI_LL_EC_QSPI_POLARITY QSPI Clock Polarity
299 * @{
300 */
301 #define LL_XQSPI_SCPOL_LOW 0 /**< Clock to 0 when idle */
302 #define LL_XQSPI_SCPOL_HIGH 1 /**< Clock to 1 when idle */
303 /** @} */
304
305 /** @defgroup XQSPI_LL_EC_QSPI_BAUD_REAT QSPI Buad Rate
306 * @{
307 */
308 #define LL_XQSPI_BAUD_RATE_64M 0x00000000UL /**< Clock to 64MHz */
309 #define LL_XQSPI_BAUD_RATE_48M (1UL << AON_PWR_REG01_XF_SCK_CLK_SEL_Pos) /**< Clock to 48MHz */
310 #define LL_XQSPI_BAUD_RATE_32M (2UL << AON_PWR_REG01_XF_SCK_CLK_SEL_Pos) /**< Clock to 32MHz */
311 #define LL_XQSPI_BAUD_RATE_24M (3UL << AON_PWR_REG01_XF_SCK_CLK_SEL_Pos) /**< Clock to 24MHz */
312 #define LL_XQSPI_BAUD_RATE_16M (4UL << AON_PWR_REG01_XF_SCK_CLK_SEL_Pos) /**< Clock to 16MHz */
313 /** @} */
314
315 /** @defgroup XQSPI_LL_EC_QSPI_PRESENT QSPI Present Bypass
316 * @{
317 */
318 #define LL_XQSPI_ENABLE_PRESENT 0 /**< Enable Present Bypass */
319 #define LL_XQSPI_DISABLE_PRESENT 1 /**< Disable Present Bypass */
320 /** @} */
321
322 /** @defgroup XQSPI_LL_EC_QSPI_FLASH_WRITE QSPI Flash write bits
323 * @{
324 */
325 #define LL_XQSPI_FLASH_WRITE_128BIT 0 /**< 128bits flash write */
326 #define LL_XQSPI_FLASH_WRITE_32BIT 1 /**< 32bits flash write */
327 /** @} */
328
329 /** @defgroup XQSPI_LL_EC_DEFAULT_CONFIG InitStrcut default configuartion
330 * @{
331 */
332
333 /**
334 * @brief LL XQSPI InitStrcut default configuartion
335 */
336 #define LL_XQSPI_DEFAULT_CONFIG \
337 { \
338 .mode = LL_XQSPI_MODE_QSPI, \
339 .cache_mode = LL_XQSPI_CACHE_EN, \
340 .read_cmd = LL_XQSPI_XIP_CMD_READ, \
341 .data_size = LL_XQSPI_QSPI_DATASIZE_8BIT, \
342 .data_order = LL_XQSPI_QSPI_MSB, \
343 .clock_polarity = LL_XQSPI_SCPOL_HIGH, \
344 .clock_phase = LL_XQSPI_SCPHA_2EDGE, \
345 .baud_rate = LL_XQSPI_BAUD_RATE_16M, \
346 }
347 /** @} */
348
349 /** @} */
350
351 /* Exported macro ------------------------------------------------------------*/
352 /** @defgroup XQSPI_LL_Exported_Macros XQSPI Exported Macros
353 * @{
354 */
355
356 /** @defgroup XQSPI_LL_EM_WRITE_READ Common Write and read registers Macros
357 * @{
358 */
359
360 /**
361 * @brief Write a value in XQSPI register
362 * @param __instance__ XQSPI instance
363 * @param __REG__ Register to be written
364 * @param __VALUE__ Value to be written in the register
365 * @retval None
366 */
367 #define LL_XQSPI_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
368
369 /**
370 * @brief Read a value in XQSPI register
371 * @param __instance__ XQSPI instance
372 * @param __REG__ Register to be read
373 * @retval Register value
374 */
375 #define LL_XQSPI_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
376
377 /** @} */
378
379 /** @} */
380
381 /** @} */
382
383 /* Exported functions --------------------------------------------------------*/
384 /** @defgroup XQSPI_LL_DRIVER_FUNCTIONS Functions
385 * @{
386 */
387
388 /** @defgroup XQSPI_LL_XQSPI_Configuration Cache driver functions
389 * @{
390 */
391
392 /**
393 * @brief Enable cache function
394 * @note This bit should not be changed when XIP is ongoing.
395 *
396 * Register|BitsName
397 * --------|--------
398 * CTRL0 |EN
399 *
400 * @param XQSPIx XQSPI instance
401 * @retval None
402 */
ll_xqspi_enable_cache(xqspi_regs_t * XQSPIx)403 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache(xqspi_regs_t *XQSPIx)
404 {
405 CLEAR_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIS);
406 __NOP();
407 __NOP();
408 __NOP();
409 __NOP();
410 __NOP();
411 __NOP();
412 __NOP();
413 __NOP();
414 __NOP();
415 __NOP();
416 __NOP();
417 __NOP();
418 __NOP();
419 __NOP();
420 __NOP();
421 __NOP();
422 __NOP();
423 __NOP();
424 __NOP();
425 __NOP();
426 __NOP();
427 __NOP();
428 __NOP();
429 __NOP();
430 __NOP();
431 __NOP();
432 __NOP();
433 }
434
435 /**
436 * @brief Disable cache function
437 * @note This bit should not be changed when XIP is ongoing.
438 *
439 * Register|BitsName
440 * --------|--------
441 * CTRL0 |EN
442 *
443 * @param XQSPIx XQSPI instance
444 * @retval None
445 */
ll_xqspi_disable_cache(xqspi_regs_t * XQSPIx)446 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache(xqspi_regs_t *XQSPIx)
447 {
448 SET_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIS);
449 __NOP();
450 __NOP();
451 __NOP();
452 __NOP();
453 __NOP();
454 __NOP();
455 __NOP();
456 __NOP();
457 __NOP();
458 __NOP();
459 __NOP();
460 __NOP();
461 __NOP();
462 __NOP();
463 __NOP();
464 __NOP();
465 __NOP();
466 __NOP();
467 __NOP();
468 __NOP();
469 __NOP();
470 __NOP();
471 __NOP();
472 __NOP();
473 __NOP();
474 __NOP();
475 __NOP();
476 }
477
478 /**
479 * @brief Check if cache function is enabled
480 *
481 * Register|BitsName
482 * --------|--------
483 * CTRL0 |EN
484 *
485 * @param XQSPIx XQSPI instance
486 * @retval State of bit (1 or 0).
487 */
ll_xqspi_is_enabled_cache(xqspi_regs_t * XQSPIx)488 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_cache(xqspi_regs_t *XQSPIx)
489 {
490 return (READ_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_DIS) != (XQSPI_CACHE_CTRL0_DIS));
491 }
492
493 /**
494 * @brief Enable tag memory flush
495 * @note This bit should not be changed when XIP is ongoing.
496 *
497 * Register|BitsName
498 * --------|--------
499 * CTRL0 |TAG
500 *
501 * @param XQSPIx XQSPI instance
502 * @retval None
503 */
ll_xqspi_enable_cache_flush(xqspi_regs_t * XQSPIx)504 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache_flush(xqspi_regs_t *XQSPIx)
505 {
506 SET_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_FLUSH);
507 }
508
509 /**
510 * @brief Disable tag memory flush
511 * @note This bit should not be changed when XIP is ongoing.
512 *
513 * Register|BitsName
514 * --------|--------
515 * CTRL0 |TAG
516 *
517 * @param XQSPIx XQSPI instance
518 * @retval None
519 */
ll_xqspi_disable_cache_flush(xqspi_regs_t * XQSPIx)520 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache_flush(xqspi_regs_t *XQSPIx)
521 {
522 CLEAR_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_FLUSH);
523 }
524
525 /**
526 * @brief Check if tag memory flush is enabled
527 *
528 * Register|BitsName
529 * --------|--------
530 * CTRL0 |TAG
531 *
532 * @param XQSPIx XQSPI instance
533 * @retval State of bit (1 or 0).
534 */
ll_xqspi_is_enabled_cache_flush(xqspi_regs_t * XQSPIx)535 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_cache_flush(xqspi_regs_t *XQSPIx)
536 {
537 return (READ_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_FLUSH) == (XQSPI_CACHE_CTRL0_FLUSH));
538 }
539
540 /**
541 * @brief Set FIFO mode
542 * @note This bit should not be changed when XIP is ongoing.
543 *
544 * Register|BitsName
545 * --------|--------
546 * CTRL0 |FIFO
547 *
548 * @param XQSPIx XQSPI instance
549 * @param mode This parameter can be one of the following values:
550 * @arg @ref LL_XQSPI_CACHE_FIFO_NORMAL
551 * @arg @ref LL_XQSPI_CACHE_FIFO_CLEAR
552 * @retval None
553 */
ll_xqspi_set_cache_fifo(xqspi_regs_t * XQSPIx,uint32_t mode)554 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cache_fifo(xqspi_regs_t *XQSPIx, uint32_t mode)
555 {
556 MODIFY_REG(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_FIFO, mode);
557 }
558
559 /**
560 * @brief Get FIFO mode
561 * @note This bit should not be changed when XIP is ongoing.
562 *
563 * Register|BitsName
564 * --------|--------
565 * CTRL0 |FIFO
566 *
567 * @param XQSPIx XQSPI instance
568 * @retval Returned Value can be one of the following values:
569 * @arg @ref LL_XQSPI_CACHE_FIFO_NORMAL
570 * @arg @ref LL_XQSPI_CACHE_FIFO_CLEAR
571 */
ll_xqspi_get_cache_fifo(xqspi_regs_t * XQSPIx)572 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_fifo(xqspi_regs_t *XQSPIx)
573 {
574 return (uint32_t)(READ_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_FIFO));
575 }
576
577 /**
578 * @brief Set HIT/MISS mode
579 * @note This bit should not be changed when XIP is ongoing.
580 *
581 * Register|BitsName
582 * --------|--------
583 * CTRL0 |HITMISS
584 *
585 * @param XQSPIx XQSPI instance
586 * @param mode This parameter can be one of the following values:
587 * @arg @ref LL_XQSPI_CACHE_HITMISS_NORMAL
588 * @arg @ref LL_XQSPI_CACHE_HITMISS_CLEAR
589 * @retval None
590 */
ll_xqspi_set_cache_hitmiss(xqspi_regs_t * XQSPIx,uint32_t mode)591 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cache_hitmiss(xqspi_regs_t *XQSPIx, uint32_t mode)
592 {
593 MODIFY_REG(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_HITMISS, mode);
594 }
595
596 /**
597 * @brief Get HIT/MISS mode
598 * @note This bit should not be changed when XIP is ongoing.
599 *
600 * Register|BitsName
601 * --------|--------
602 * CTRL0 |HITMISS
603 *
604 * @param XQSPIx XQSPI instance
605 * @retval Returned Value can be one of the following values:
606 * @arg @ref LL_XQSPI_CACHE_HITMISS_NORMAL
607 * @arg @ref LL_XQSPI_CACHE_HITMISS_CLEAR
608 */
ll_xqspi_get_cache_hitmiss(xqspi_regs_t * XQSPIx)609 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_hitmiss(xqspi_regs_t *XQSPIx)
610 {
611 return (uint32_t)(READ_BITS(XQSPIx->CACHE.CTRL0, XQSPI_CACHE_CTRL0_HITMISS));
612 }
613
614 /**
615 * @brief Set debugbus configurations signals
616 * @note These bits should not be changed when XIP is ongoing.
617 *
618 * Register|BitsName
619 * --------|--------
620 * CTRL1 |DBGBUS_SEL
621 *
622 * @param XQSPIx XQSPI instance
623 * @param sel This parameter can between: 0 ~ 0x7
624 * @retval None
625 */
ll_xqspi_set_cache_dbgbus(xqspi_regs_t * XQSPIx,uint32_t sel)626 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_cache_dbgbus(xqspi_regs_t *XQSPIx, uint32_t sel)
627 {
628 MODIFY_REG(XQSPIx->CACHE.CTRL1, XQSPI_CACHE_CTRL1_DBGBUS_SEL, sel << XQSPI_CACHE_CTRL1_DBGBUS_SEL_Pos);
629 }
630
631 /**
632 * @brief Get debugbus configurations signals
633 *
634 * Register|BitsName
635 * --------|--------
636 * CTRL1 |DBGBUS_SEL
637 *
638 * @param XQSPIx XQSPI instance
639 * @retval Returned Value can between: 0 ~ 0x7
640 */
ll_xqspi_get_cache_dbgbus(xqspi_regs_t * XQSPIx)641 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_dbgbus(xqspi_regs_t *XQSPIx)
642 {
643 return (uint32_t)(READ_BITS(XQSPIx->CACHE.CTRL1, XQSPI_CACHE_CTRL1_DBGBUS_SEL) >> \
644 XQSPI_CACHE_CTRL1_DBGBUS_SEL_Pos);
645 }
646
647 /**
648 * @brief Enable debug bus mux
649 * @note This bit should not be changed when XIP is ongoing.
650 *
651 * Register|BitsName
652 * --------|--------
653 * CTRL1 |DBGMUX_EN
654 *
655 * @param XQSPIx XQSPI instance
656 * @retval None
657 */
ll_xqspi_enable_cache_dbgmux(xqspi_regs_t * XQSPIx)658 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache_dbgmux(xqspi_regs_t *XQSPIx)
659 {
660 CLEAR_BITS(XQSPIx->CACHE.CTRL1, XQSPI_CACHE_CTRL1_DBGMUX_EN);
661 }
662
663 /**
664 * @brief Disable debug bus mux
665 * @note This bit should not be changed when XIP is ongoing.
666 *
667 * Register|BitsName
668 * --------|--------
669 * CTRL1 |DBGMUX_EN
670 *
671 * @param XQSPIx XQSPI instance
672 * @retval None
673 */
ll_xqspi_disable_cache_dbgmux(xqspi_regs_t * XQSPIx)674 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache_dbgmux(xqspi_regs_t *XQSPIx)
675 {
676 SET_BITS(XQSPIx->CACHE.CTRL1, XQSPI_CACHE_CTRL1_DBGMUX_EN);
677 }
678
679 /**
680 * @brief Check if debug bus mux is enabled
681 *
682 * Register|BitsName
683 * --------|--------
684 * CTRL1 |DBGMUX_EN
685 *
686 * @param XQSPIx XQSPI instance
687 * @retval State of bit (1 or 0).
688 */
ll_xqspi_is_enabled_cache_dbgmux(xqspi_regs_t * XQSPIx)689 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_cache_dbgmux(xqspi_regs_t *XQSPIx)
690 {
691 return (READ_BITS(XQSPIx->CACHE.CTRL1, XQSPI_CACHE_CTRL1_DBGMUX_EN) != (XQSPI_CACHE_CTRL1_DBGMUX_EN));
692 }
693
694 /**
695 * @brief Get hit counter
696 * @note This bit only be read.
697 *
698 * Register|BitsName
699 * --------|--------
700 * HIT_COUNT|HITCOUNT
701 *
702 * @param XQSPIx XQSPI instance
703 * @retval Returned Value can between: 0 ~ 0xFFFFFFFF
704 */
ll_xqspi_get_cache_hitcount(xqspi_regs_t * XQSPIx)705 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_hitcount(xqspi_regs_t *XQSPIx)
706 {
707 return (uint32_t)(READ_REG(XQSPIx->CACHE.HIT_COUNT));
708 }
709
710 /**
711 * @brief Get miss counter
712 * @note This bit only be read.
713 *
714 * Register|BitsName
715 * --------|--------
716 * MISS_COUNT|MISSCOUNT
717 *
718 * @param XQSPIx XQSPI instance
719 * @retval Returned Value can between: 0 ~ 0xFFFFFFFF
720 */
ll_xqspi_get_cache_misscount(xqspi_regs_t * XQSPIx)721 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_misscount(xqspi_regs_t *XQSPIx)
722 {
723 return (uint32_t)(READ_REG(XQSPIx->CACHE.MISS_COUNT));
724 }
725
726 /**
727 * @brief Get cache status
728 * @note This bit only be read.
729 *
730 * Register|BitsName
731 * --------|--------
732 * STAT |STAT
733 *
734 * @param XQSPIx XQSPI instance
735 * @retval Returned Value can between: 0 ~ 1
736 */
ll_xqspi_get_cache_flag(xqspi_regs_t * XQSPIx)737 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_cache_flag(xqspi_regs_t *XQSPIx)
738 {
739 return (uint32_t)(READ_BITS(XQSPIx->CACHE.STAT, XQSPI_CACHE_STAT));
740 }
741
742 /** @} */
743
744 /** @defgroup XQSPI_LL_XIP_Configuration XIP LL driver functions
745 * @{
746 */
747
748 /**
749 * @brief Set read command
750 * @note These bits should not be changed when XIP is ongoing.
751 *
752 * Register|BitsName
753 * --------|--------
754 * CTRL0 |CFG_CMD
755 *
756 * @param XQSPIx XQSPI instance
757 * @param cmd This parameter can be one of the following values:
758 * @arg @ref LL_XQSPI_XIP_CMD_READ
759 * @arg @ref LL_XQSPI_XIP_CMD_FAST_READ
760 * @arg @ref LL_XQSPI_XIP_CMD_DUAL_OUT_READ
761 * @arg @ref LL_XQSPI_XIP_CMD_DUAL_IO_READ
762 * @arg @ref LL_XQSPI_XIP_CMD_QUAD_OUT_READ
763 * @arg @ref LL_XQSPI_XIP_CMD_QUAD_IO_READ
764 * @retval None
765 */
ll_xqspi_set_xip_cmd(xqspi_regs_t * XQSPIx,uint32_t cmd)766 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_cmd(xqspi_regs_t *XQSPIx, uint32_t cmd)
767 {
768 MODIFY_REG(XQSPIx->XIP.CTRL0, XQSPI_XIP_CFG_CMD, cmd);
769 }
770
771 /**
772 * @brief Get read command
773 *
774 * Register|BitsName
775 * --------|--------
776 * CTRL0 |CFG_CMD
777 *
778 * @param XQSPIx XQSPI instance
779 * @retval Returned Value can be one of the following values:
780 * @arg @ref LL_XQSPI_XIP_CMD_READ
781 * @arg @ref LL_XQSPI_XIP_CMD_FAST_READ
782 * @arg @ref LL_XQSPI_XIP_CMD_DUAL_OUT_READ
783 * @arg @ref LL_XQSPI_XIP_CMD_DUAL_IO_READ
784 * @arg @ref LL_XQSPI_XIP_CMD_QUAD_OUT_READ
785 * @arg @ref LL_XQSPI_XIP_CMD_QUAD_IO_READ
786 */
ll_xqspi_get_xip_cmd(xqspi_regs_t * XQSPIx)787 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_cmd(xqspi_regs_t *XQSPIx)
788 {
789 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL0, XQSPI_XIP_CFG_CMD));
790 }
791
792 /**
793 * @brief Enable high performance mode
794 * @note This bit should not be changed when XIP is ongoing.
795 *
796 * Register|BitsName
797 * --------|--------
798 * CTRL1 |CFG_HPEN
799 *
800 * @param XQSPIx XQSPI instance
801 * @retval None
802 */
ll_xqspi_enable_xip_hp(xqspi_regs_t * XQSPIx)803 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_xip_hp(xqspi_regs_t *XQSPIx)
804 {
805 SET_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_HPEN);
806 }
807
808 /**
809 * @brief Disable high performance mode
810 * @note This bit should not be changed when XIP is ongoing.
811 *
812 * Register|BitsName
813 * --------|--------
814 * CTRL1 |CFG_HPEN
815 *
816 * @param XQSPIx XQSPI instance
817 * @retval None
818 */
ll_xqspi_disable_xip_hp(xqspi_regs_t * XQSPIx)819 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_xip_hp(xqspi_regs_t *XQSPIx)
820 {
821 CLEAR_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_HPEN);
822 }
823
824 /**
825 * @brief Check if high performance mode is enabled
826 *
827 * Register|BitsName
828 * --------|--------
829 * CTRL1 |CFG_HPEN
830 *
831 * @param XQSPIx XQSPI instance
832 * @retval State of bit (1 or 0).
833 */
ll_xqspi_is_enabled_xip_hp(xqspi_regs_t * XQSPIx)834 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_xip_hp(xqspi_regs_t *XQSPIx)
835 {
836 return (READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_HPEN) == (XQSPI_XIP_CFG_HPEN));
837 }
838
839 /**
840 * @brief Set slave select
841 * @note These bits should not be changed when XIP is ongoing.
842 *
843 * Register|BitsName
844 * --------|--------
845 * CTRL1 |CFG_SS
846 *
847 * @param XQSPIx XQSPI instance
848 * @param ss This parameter can be one or more of the following values:
849 * @arg @ref LL_XQSPI_XIP_SS0
850 * @arg @ref LL_XQSPI_XIP_SS1
851 * @arg @ref LL_XQSPI_XIP_SS2
852 * @arg @ref LL_XQSPI_XIP_SS3
853 * @retval None
854 */
ll_xqspi_set_xip_ss(xqspi_regs_t * XQSPIx,uint32_t ss)855 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_ss(xqspi_regs_t *XQSPIx, uint32_t ss)
856 {
857 MODIFY_REG(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_SS, ss);
858 }
859
860 /**
861 * @brief Get slave select
862 *
863 * Register|BitsName
864 * --------|--------
865 * CTRL1 |CFG_SS
866 *
867 * @param XQSPIx XQSPI instance
868 * @retval Returned Value can be one of the following values:
869 * @arg @ref LL_XQSPI_XIP_SS0
870 * @arg @ref LL_XQSPI_XIP_SS1
871 * @arg @ref LL_XQSPI_XIP_SS2
872 * @arg @ref LL_XQSPI_XIP_SS3
873 */
ll_xqspi_get_xip_ss(xqspi_regs_t * XQSPIx)874 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_ss(xqspi_regs_t *XQSPIx)
875 {
876 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_SS));
877 }
878
879 /**
880 * @brief Set clock phase
881 * @note This bit should not be changed when XIP is ongoing.
882 *
883 * Register|BitsName
884 * --------|--------
885 * CTRL1 |CFG_CPHA
886 *
887 * @param XQSPIx XQSPI instance
888 * @param cpha This parameter can be one or more of the following values:
889 * @arg @ref LL_XQSPI_SCPHA_1EDGE
890 * @arg @ref LL_XQSPI_SCPHA_2EDGE
891 * @retval None
892 */
ll_xqspi_set_xip_cpha(xqspi_regs_t * XQSPIx,uint32_t cpha)893 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_cpha(xqspi_regs_t *XQSPIx, uint32_t cpha)
894 {
895 MODIFY_REG(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_CPHA, cpha << XQSPI_XIP_CFG_CPHA_Pos);
896 }
897
898 /**
899 * @brief Get clock phase
900 *
901 * Register|BitsName
902 * --------|--------
903 * CTRL1 |CFG_CPHA
904 *
905 * @param XQSPIx XQSPI instance
906 * @retval Returned Value can be one of the following values:
907 * @arg @ref LL_XQSPI_SCPHA_1EDGE
908 * @arg @ref LL_XQSPI_SCPHA_2EDGE
909 */
ll_xqspi_get_xip_cpha(xqspi_regs_t * XQSPIx)910 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_cpha(xqspi_regs_t *XQSPIx)
911 {
912 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_CPHA) >> XQSPI_XIP_CFG_CPHA_Pos);
913 }
914
915 /**
916 * @brief Set clock polarity
917 * @note This bit should not be changed when XIP is ongoing.
918 *
919 * Register|BitsName
920 * --------|--------
921 * CTRL1 |CFG_CPOL
922 *
923 * @param XQSPIx XQSPI instance
924 * @param cpol This parameter can be one or more of the following values:
925 * @arg @ref LL_XQSPI_SCPOL_LOW
926 * @arg @ref LL_XQSPI_SCPOL_HIGH
927 * @retval None
928 */
ll_xqspi_set_xip_cpol(xqspi_regs_t * XQSPIx,uint32_t cpol)929 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_cpol(xqspi_regs_t *XQSPIx, uint32_t cpol)
930 {
931 MODIFY_REG(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_CPOL, cpol << XQSPI_XIP_CFG_CPOL_Pos);
932 }
933
934 /**
935 * @brief Get clock polarity
936 *
937 * Register|BitsName
938 * --------|--------
939 * CTRL1 |CFG_CPOL
940 *
941 * @param XQSPIx XQSPI instance
942 * @retval Returned Value can be one of the following values:
943 * @arg @ref LL_XQSPI_SCPOL_LOW
944 * @arg @ref LL_XQSPI_SCPOL_HIGH
945 */
ll_xqspi_get_xip_cpol(xqspi_regs_t * XQSPIx)946 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_cpol(xqspi_regs_t *XQSPIx)
947 {
948 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_CPOL) >> XQSPI_XIP_CFG_CPOL_Pos);
949 }
950
951 /**
952 * @brief Set address bytes in command
953 * @note This bit should not be changed when XIP is ongoing.
954 *
955 * Register|BitsName
956 * --------|--------
957 * CTRL1 |CFG_ADDR4
958 *
959 * @param XQSPIx XQSPI instance
960 * @param size This parameter can be one or more of the following values:
961 * @arg @ref LL_XQSPI_XIP_ADDR_3BYTES
962 * @arg @ref LL_XQSPI_XIP_ADDR_4BYTES
963 * @retval None
964 */
ll_xqspi_set_xip_addr_size(xqspi_regs_t * XQSPIx,uint32_t size)965 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_addr_size(xqspi_regs_t *XQSPIx, uint32_t size)
966 {
967 MODIFY_REG(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_ADDR4, size);
968 }
969
970 /**
971 * @brief Get address bytes in command
972 *
973 * Register|BitsName
974 * --------|--------
975 * CTRL1 |CFG_ADDR4
976 *
977 * @param XQSPIx XQSPI instance
978 * @retval Returned Value can be one of the following values:
979 * @arg @ref LL_XQSPI_XIP_ADDR_3BYTES
980 * @arg @ref LL_XQSPI_XIP_ADDR_4BYTES
981 */
ll_xqspi_get_xip_addr_size(xqspi_regs_t * XQSPIx)982 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_addr_size(xqspi_regs_t *XQSPIx)
983 {
984 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_ADDR4));
985 }
986
987 /**
988 * @brief Set endian in reading data
989 * @note This bit should not be changed when XIP is ongoing.
990 *
991 * Register|BitsName
992 * --------|--------
993 * CTRL1 |CFG_LE32
994 *
995 * @param XQSPIx XQSPI instance
996 * @param endian This parameter can be one or more of the following values:
997 * @arg @ref LL_XQSPI_XIP_ENDIAN_BIG
998 * @arg @ref LL_XQSPI_XIP_ENDIAN_LITTLE
999 * @retval None
1000 */
ll_xqspi_set_xip_endian(xqspi_regs_t * XQSPIx,uint32_t endian)1001 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_endian(xqspi_regs_t *XQSPIx, uint32_t endian)
1002 {
1003 MODIFY_REG(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_LE32, endian);
1004 }
1005
1006 /**
1007 * @brief Get endian in reading data
1008 *
1009 * Register|BitsName
1010 * --------|--------
1011 * CTRL1 |CFG_LE32
1012 *
1013 * @param XQSPIx XQSPI instance
1014 * @retval Returned Value can be one of the following values:
1015 * @arg @ref LL_XQSPI_XIP_ENDIAN_BIG
1016 * @arg @ref LL_XQSPI_XIP_ENDIAN_LITTLE
1017 */
ll_xqspi_get_xip_endian(xqspi_regs_t * XQSPIx)1018 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_endian(xqspi_regs_t *XQSPIx)
1019 {
1020 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL1, XQSPI_XIP_CFG_LE32));
1021 }
1022
1023 /**
1024 * @brief Set high performance command
1025 * @note These bits should not be changed when XIP is ongoing.
1026 *
1027 * Register|BitsName
1028 * --------|--------
1029 * CTRL2 |CFG_HPMODE
1030 *
1031 * @param XQSPIx XQSPI instance
1032 * @param cmd This value is specified by different QSPI FLASH
1033 * memory vendor to enter into its status register
1034 * to activate HP mode in dual I/O and Quad I/O
1035 * access. This parameter can between: 0 ~ 0xFF.
1036 * @retval None
1037 */
ll_xqspi_set_xip_hp_cmd(xqspi_regs_t * XQSPIx,uint32_t cmd)1038 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_hp_cmd(xqspi_regs_t *XQSPIx, uint32_t cmd)
1039 {
1040 MODIFY_REG(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_HPMODE, cmd << XQSPI_XIP_CFG_HPMODE_Pos);
1041 }
1042
1043 /**
1044 * @brief Get high performance command
1045 *
1046 * Register|BitsName
1047 * --------|--------
1048 * CTRL2 |CFG_HPMODE
1049 *
1050 * @param XQSPIx XQSPI instance
1051 * @retval Returned Value can between: 0 ~ 0xFF.
1052 */
ll_xqspi_get_xip_hp_cmd(xqspi_regs_t * XQSPIx)1053 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_hp_cmd(xqspi_regs_t *XQSPIx)
1054 {
1055 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_HPMODE) >> XQSPI_XIP_CFG_HPMODE_Pos);
1056 }
1057
1058 /**
1059 * @brief Set dummy cycles in command
1060 * @note These bits should not be changed when XIP is ongoing.
1061 * - Fast Read Dual I/O: dummycycles = 4 * cycles + 4
1062 * - Fast Read Quad I/O: dummycycles = 2 * cycles + 2
1063 * - Fast Read Dual Out: dummycycles = 8 * cycles
1064 * - Fast Read Quad Out: dummycycles = 8 * cycles
1065 *
1066 * Register|BitsName
1067 * --------|--------
1068 * CTRL2 |CFG_DUMMYCYCLES
1069 *
1070 * @param XQSPIx XQSPI instance
1071 * @param cycles This parameter can between: 0 ~ 0xF.
1072 * @retval None
1073 */
ll_xqspi_set_xip_dummycycles(xqspi_regs_t * XQSPIx,uint32_t cycles)1074 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_dummycycles(xqspi_regs_t *XQSPIx, uint32_t cycles)
1075 {
1076 MODIFY_REG(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_DUMMYCYCLES, cycles << XQSPI_XIP_CFG_DUMMYCYCLES_Pos);
1077 }
1078
1079 /**
1080 * @brief Get dummy cycles in command
1081 * @note - Fast Read Dual I/O: dummycycles = 4 * cycles + 4
1082 * - Fast Read Quad I/O: dummycycles = 2 * cycles + 2
1083 * - Fast Read Dual Out: dummycycles = 8 * cycles
1084 * - Fast Read Quad Out: dummycycles = 8 * cycles
1085 *
1086 * Register|BitsName
1087 * --------|--------
1088 * CTRL2 |CFG_DUMMYCYCLES
1089 *
1090 * @param XQSPIx XQSPI instance
1091 * @retval Returned Value can between: 0 ~ 0xF.
1092 */
ll_xqspi_get_xip_dummycycles(xqspi_regs_t * XQSPIx)1093 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_dummycycles(xqspi_regs_t *XQSPIx)
1094 {
1095 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_DUMMYCYCLES));
1096 }
1097
1098 /**
1099 * @brief Set dummy cycles in high performance end
1100 * @note These bits should not be changed when XIP is ongoing.
1101 *
1102 * Register|BitsName
1103 * --------|--------
1104 * CTRL2 |CFG_ENDDUMMY
1105 *
1106 * @param XQSPIx XQSPI instance
1107 * @param cycles This parameter can between: 0 ~ 3.
1108 * @retval None
1109 */
ll_xqspi_set_xip_dummy_hp(xqspi_regs_t * XQSPIx,uint32_t cycles)1110 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_xip_dummy_hp(xqspi_regs_t *XQSPIx, uint32_t cycles)
1111 {
1112 MODIFY_REG(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_ENDDUMMY, cycles << XQSPI_XIP_CFG_ENDDUMMY_Pos);
1113 }
1114
1115 /**
1116 * @brief Get dummy cycles in high performance end
1117 *
1118 * Register|BitsName
1119 * --------|--------
1120 * CTRL2 |CFG_ENDDUMMY
1121 *
1122 * @param XQSPIx XQSPI instance
1123 * @retval Returned Value can between: 0 ~ 3.
1124 */
ll_xqspi_get_xip_dummy_hp(xqspi_regs_t * XQSPIx)1125 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_dummy_hp(xqspi_regs_t *XQSPIx)
1126 {
1127 return (uint32_t)(READ_BITS(XQSPIx->XIP.CTRL2, XQSPI_XIP_CFG_ENDDUMMY) >> XQSPI_XIP_CFG_ENDDUMMY_Pos);
1128 }
1129
1130 /**
1131 * @brief Enable XIP mode
1132 *
1133 * Register|BitsName
1134 * --------|--------
1135 * CTRL3 |EN_REQ
1136 *
1137 * @param XQSPIx XQSPI instance
1138 * @retval None
1139 */
ll_xqspi_enable_xip(xqspi_regs_t * XQSPIx)1140 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_xip(xqspi_regs_t *XQSPIx)
1141 {
1142 SET_BITS(XQSPIx->XIP.CTRL3, XQSPI_XIP_EN_REQ);
1143 }
1144
1145 /**
1146 * @brief Disable XIP mode
1147 *
1148 * Register|BitsName
1149 * --------|--------
1150 * CTRL3 |EN_REQ
1151 *
1152 * @param XQSPIx XQSPI instance
1153 * @retval None
1154 */
ll_xqspi_disable_xip(xqspi_regs_t * XQSPIx)1155 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_xip(xqspi_regs_t *XQSPIx)
1156 {
1157 CLEAR_BITS(XQSPIx->XIP.CTRL3, XQSPI_XIP_EN_REQ);
1158 }
1159
1160 /**
1161 * @brief Check if XIP mode is enabled
1162 * @note This bit should not be changed when XIP is ongoing.
1163 *
1164 * Register|BitsName
1165 * --------|--------
1166 * CTRL3 |EN_REQ
1167 *
1168 * @param XQSPIx XQSPI instance
1169 * @retval State of bit (1 or 0).
1170 */
ll_xqspi_is_enabled_xip(xqspi_regs_t * XQSPIx)1171 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_xip(xqspi_regs_t *XQSPIx)
1172 {
1173 return (READ_BITS(XQSPIx->XIP.CTRL3, XQSPI_XIP_EN_REQ) == (XQSPI_XIP_EN_REQ));
1174 }
1175
1176 /**
1177 * @brief Get XIP status
1178 * @note This bit is read-only.
1179 *
1180 * Register|BitsName
1181 * --------|--------
1182 * STAT |EN_OUT
1183 *
1184 * @param XQSPIx XQSPI instance
1185 * @retval Returned Value can between: 0 ~ 1
1186 */
ll_xqspi_get_xip_flag(xqspi_regs_t * XQSPIx)1187 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_xip_flag(xqspi_regs_t *XQSPIx)
1188 {
1189 return (uint32_t)(READ_BITS(XQSPIx->XIP.STAT, XQSPI_XIP_EN_OUT));
1190 }
1191
1192 /**
1193 * @brief Check if XIP interrupt is enabled
1194 * @note This bit is read-only.
1195 *
1196 * Register|BitsName
1197 * --------|--------
1198 * INTEN |INT_EN
1199 *
1200 * @param XQSPIx XQSPI instance
1201 * @retval Returned Value can between: 0 ~ 1
1202 */
ll_xqspi_is_enabled_xip_it(xqspi_regs_t * XQSPIx)1203 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_xip_it(xqspi_regs_t *XQSPIx)
1204 {
1205 return (uint32_t)(READ_BITS(XQSPIx->XIP.INTEN, XQSPI_XIP_INT_EN));
1206 }
1207
1208 /**
1209 * @brief Get XIP interrupt flag
1210 * @note This bit is read-only.
1211 *
1212 * Register|BitsName
1213 * --------|--------
1214 * INTSTAT |INT_STAT
1215 *
1216 * @param XQSPIx XQSPI instance
1217 * @retval Returned Value can between: 0 ~ 1
1218 */
ll_xqspi_get_flag_xip_it(xqspi_regs_t * XQSPIx)1219 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_flag_xip_it(xqspi_regs_t *XQSPIx)
1220 {
1221 return (uint32_t)(READ_BITS(XQSPIx->XIP.INTSTAT, XQSPI_XIP_INT_STAT));
1222 }
1223
1224 /**
1225 * @brief Get XIP interrupt request
1226 * @note This bit is read-only.
1227 *
1228 * Register|BitsName
1229 * --------|--------
1230 * INTREQ |INT_REQ
1231 *
1232 * @param XQSPIx XQSPI instance
1233 * @retval Returned Value can between: 0 ~ 1
1234 */
ll_xqspi_get_req_xip_it(xqspi_regs_t * XQSPIx)1235 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_req_xip_it(xqspi_regs_t *XQSPIx)
1236 {
1237 return (uint32_t)(READ_BITS(XQSPIx->XIP.INTREQ, XQSPI_XIP_INT_REQ));
1238 }
1239
1240 /**
1241 * @brief Set XIP interrupt enable
1242 * @note This bit is write-only.
1243 *
1244 * Register|BitsName
1245 * --------|--------
1246 * INTSET |INT_SET
1247 *
1248 * @param XQSPIx XQSPI instance
1249 * @retval None
1250 */
ll_xqspi_enable_xip_it(xqspi_regs_t * XQSPIx)1251 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_xip_it(xqspi_regs_t *XQSPIx)
1252 {
1253 SET_BITS(XQSPIx->XIP.INTSET, XQSPI_XIP_INT_SET);
1254 }
1255
1256 /**
1257 * @brief Set XIP interrupt disable
1258 * @note This bit is write-only.
1259 *
1260 * Register|BitsName
1261 * --------|--------
1262 * INTCLR |INT_CLR
1263 *
1264 * @param XQSPIx XQSPI instance
1265 * @retval None
1266 */
ll_xqspi_disable_xip_it(xqspi_regs_t * XQSPIx)1267 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_xip_it(xqspi_regs_t *XQSPIx)
1268 {
1269 SET_BITS(XQSPIx->XIP.INTCLR, XQSPI_XIP_INT_CLR);
1270 }
1271
1272 /** @} */
1273
1274 /** @defgroup XQSPI_LL_QSPI_Configuration QSPI driver functions
1275 * @{
1276 */
1277
1278 /**
1279 * @brief Write 8-bit in the data register
1280 *
1281 * Register|BitsName
1282 * --------|--------
1283 * TX_DATA | DATA
1284 *
1285 * @param XQSPIx XQSPI instance
1286 * @param tx_data This parameter can between: 0x00 ~ 0xFF
1287 * @retval None
1288 */
ll_xqspi_qspi_transmit_data8(xqspi_regs_t * XQSPIx,uint8_t tx_data)1289 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_qspi_transmit_data8(xqspi_regs_t *XQSPIx, uint8_t tx_data)
1290 {
1291 *((__IOM uint8_t *)&XQSPIx->QSPI.TX_DATA) = tx_data;
1292 }
1293
1294 /**
1295 * @brief Write 16-bit in the data register
1296 *
1297 * Register|BitsName
1298 * --------|--------
1299 * TX_DATA | DATA
1300 *
1301 * @param XQSPIx XQSPI instance
1302 * @param tx_data This parameter can between: 0x00 ~ 0xFFFF
1303 * @retval None
1304 */
ll_xqspi_qspi_transmit_data16(xqspi_regs_t * XQSPIx,uint16_t tx_data)1305 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_qspi_transmit_data16(xqspi_regs_t *XQSPIx, uint16_t tx_data)
1306 {
1307 *((__IOM uint16_t *)&XQSPIx->QSPI.TX_DATA) = tx_data;
1308 }
1309
1310 /**
1311 * @brief Write 32-bit in the data register
1312 *
1313 * Register|BitsName
1314 * --------|--------
1315 * TX_DATA | DATA
1316 *
1317 * @param XQSPIx XQSPI instance
1318 * @param tx_data This parameter can between: 0x00 ~ 0xFFFFFFFF
1319 * @retval None
1320 */
ll_xqspi_qspi_transmit_data32(xqspi_regs_t * XQSPIx,uint32_t tx_data)1321 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_qspi_transmit_data32(xqspi_regs_t *XQSPIx, uint32_t tx_data)
1322 {
1323 *((__IOM uint32_t *)&XQSPIx->QSPI.TX_DATA) = tx_data;
1324 }
1325
1326 /**
1327 * @brief Read 8 bits in the data register
1328 *
1329 * Register|BitsName
1330 * --------|--------
1331 * RX_DATA | DATA
1332 *
1333 * @param XQSPIx XQSPI instance
1334 * @retval Returned Value between: 0x00 ~ 0xFF
1335 */
ll_xqspi_qspi_receive_data8(xqspi_regs_t * XQSPIx)1336 SECTION_RAM_CODE __STATIC_INLINE uint8_t ll_xqspi_qspi_receive_data8(xqspi_regs_t *XQSPIx)
1337 {
1338 return (uint8_t)(READ_REG(XQSPIx->QSPI.RX_DATA));
1339 }
1340
1341 /**
1342 * @brief Read 16 bits in the data register
1343 *
1344 * Register|BitsName
1345 * --------|--------
1346 * RX_DATA | DATA
1347 *
1348 * @param XQSPIx XQSPI instance
1349 * @retval Returned Value between: 0x00 ~ 0xFFFF
1350 */
ll_xqspi_qspi_receive_data16(xqspi_regs_t * XQSPIx)1351 SECTION_RAM_CODE __STATIC_INLINE uint16_t ll_xqspi_qspi_receive_data16(xqspi_regs_t *XQSPIx)
1352 {
1353 return (uint16_t)(READ_REG(XQSPIx->QSPI.RX_DATA));
1354 }
1355
1356 /**
1357 * @brief Read 32 bits in the data register
1358 *
1359 * Register|BitsName
1360 * --------|--------
1361 * RX_DATA | DATA
1362 *
1363 * @param XQSPIx XQSPI instance
1364 * @retval Returned Value between: 0x00 ~ 0xFFFFFFFF
1365 */
ll_xqspi_qspi_receive_data32(xqspi_regs_t * XQSPIx)1366 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_qspi_receive_data32(xqspi_regs_t *XQSPIx)
1367 {
1368 return (uint32_t)(READ_REG(XQSPIx->QSPI.RX_DATA));
1369 }
1370
1371 /**
1372 * @brief Set TX FIFO threshold level
1373 * @note FIFO maximum depth is 16 units.
1374 *
1375 * Register|BitsName
1376 * --------|--------
1377 * CTRL |TXWMARK
1378 *
1379 * @param XQSPIx XQSPI instance
1380 * @param threshold This parameter can be one of the following values:
1381 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_8
1382 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_4
1383 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_2
1384 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_3_4
1385 * @retval None
1386 */
ll_xqspi_set_qspi_tft(xqspi_regs_t * XQSPIx,uint32_t threshold)1387 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_tft(xqspi_regs_t *XQSPIx, uint32_t threshold)
1388 {
1389 MODIFY_REG(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_TXWMARK, threshold << XQSPI_QSPI_CTRL_TXWMARK_Pos);
1390 }
1391
1392 /**
1393 * @brief Get TX FIFO threshold level
1394 * @note FIFO maximum depth is 16 units.
1395 *
1396 * Register|BitsName
1397 * --------|--------
1398 * CTRL |TXWMARK
1399 *
1400 * @param XQSPIx XQSPI instance
1401 * @retval Returned Value can be one of the following values:
1402 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_8
1403 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_4
1404 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_2
1405 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_3_4
1406 */
ll_xqspi_get_qspi_tft(xqspi_regs_t * XQSPIx)1407 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_tft(xqspi_regs_t *XQSPIx)
1408 {
1409 return (uint32_t)(READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_TXWMARK) >> XQSPI_QSPI_CTRL_TXWMARK_Pos);
1410 }
1411
1412 /**
1413 * @brief Set RX FIFO threshold level
1414 * @note FIFO maximum depth is 16 units.
1415 *
1416 * Register|BitsName
1417 * --------|--------
1418 * CTRL |RXWMARK
1419 *
1420 * @param XQSPIx XQSPI instance
1421 * @param threshold This parameter can be one of the following values:
1422 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_8
1423 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_4
1424 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_2
1425 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_3_4
1426 * @retval None
1427 */
ll_xqspi_set_qspi_rft(xqspi_regs_t * XQSPIx,uint32_t threshold)1428 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_rft(xqspi_regs_t *XQSPIx, uint32_t threshold)
1429 {
1430 MODIFY_REG(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_RXWMARK, threshold << XQSPI_QSPI_CTRL_RXWMARK_Pos);
1431 }
1432
1433 /**
1434 * @brief Get RX FIFO threshold level
1435 * @note FIFO maximum depth is 16 units.
1436 *
1437 * Register|BitsName
1438 * --------|--------
1439 * CTRL |RXWMARK
1440 *
1441 * @param XQSPIx XQSPI instance
1442 * @retval Returned Value can be one of the following values:
1443 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_8
1444 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_4
1445 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_1_2
1446 * @arg @ref LL_XQSPI_QSPI_FIFO_WATERMARK_3_4
1447 */
ll_xqspi_get_qspi_rft(xqspi_regs_t * XQSPIx)1448 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_rft(xqspi_regs_t *XQSPIx)
1449 {
1450 return (uint32_t)(READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_RXWMARK) >> XQSPI_QSPI_CTRL_RXWMARK_Pos);
1451 }
1452
1453 /**
1454 * @brief Enable dummy cycles
1455 *
1456 * Register|BitsName
1457 * --------|--------
1458 * CTRL |MWAITEN
1459 *
1460 * @param XQSPIx XQSPI instance
1461 * @retval None
1462 */
ll_xqspi_enable_qspi_dummy(xqspi_regs_t * XQSPIx)1463 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_dummy(xqspi_regs_t *XQSPIx)
1464 {
1465 SET_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_MWAITEN);
1466 }
1467
1468 /**
1469 * @brief Disable dummy cycles
1470 *
1471 * Register|BitsName
1472 * --------|--------
1473 * CTRL |MWAITEN
1474 *
1475 * @param XQSPIx XQSPI instance
1476 * @retval None
1477 */
ll_xqspi_disable_qspi_dummy(xqspi_regs_t * XQSPIx)1478 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_dummy(xqspi_regs_t *XQSPIx)
1479 {
1480 CLEAR_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_MWAITEN);
1481 }
1482
1483 /**
1484 * @brief Check if dummy cycles is enabled
1485 *
1486 * Register|BitsName
1487 * --------|--------
1488 * CTRL |MWAITEN
1489 *
1490 * @param XQSPIx XQSPI instance
1491 * @retval State of bit (1 or 0).
1492 */
ll_xqspi_is_enabled_qspi_dummy(xqspi_regs_t * XQSPIx)1493 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_dummy(xqspi_regs_t *XQSPIx)
1494 {
1495 return (READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_MWAITEN) == (XQSPI_QSPI_CTRL_MWAITEN));
1496 }
1497
1498 /**
1499 * @brief Enable DMA mode
1500 *
1501 * Register|BitsName
1502 * --------|--------
1503 * CTRL |DMA
1504 *
1505 * @param XQSPIx XQSPI instance
1506 * @retval None
1507 */
ll_xqspi_enable_qspi_dma(xqspi_regs_t * XQSPIx)1508 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_dma(xqspi_regs_t *XQSPIx)
1509 {
1510 SET_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_DMA);
1511 }
1512
1513 /**
1514 * @brief Disable DMA mode
1515 *
1516 * Register|BitsName
1517 * --------|--------
1518 * CTRL |DMA
1519 *
1520 * @param XQSPIx XQSPI instance
1521 * @retval None
1522 */
ll_xqspi_disable_qspi_dma(xqspi_regs_t * XQSPIx)1523 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_dma(xqspi_regs_t *XQSPIx)
1524 {
1525 CLEAR_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_DMA);
1526 }
1527
1528 /**
1529 * @brief Check if DMA mode is enabled
1530 *
1531 * Register|BitsName
1532 * --------|--------
1533 * CTRL |DMA
1534 *
1535 * @param XQSPIx XQSPI instance
1536 * @retval State of bit (1 or 0).
1537 */
ll_xqspi_is_enabled_qspi_dma(xqspi_regs_t * XQSPIx)1538 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_dma(xqspi_regs_t *XQSPIx)
1539 {
1540 return (READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_DMA) == (XQSPI_QSPI_CTRL_DMA));
1541 }
1542
1543 /**
1544 * @brief Set clock polarity
1545 * @note This bit should not be changed when communication is ongoing.
1546 *
1547 * Register|BitsName
1548 * --------|--------
1549 * CTRL |CPOL
1550 *
1551 * @param XQSPIx XQSPI instance
1552 * @param cpol This parameter can be one of the following values:
1553 * @arg @ref LL_XQSPI_SCPOL_LOW
1554 * @arg @ref LL_XQSPI_SCPOL_HIGH
1555 * @retval None
1556 */
ll_xqspi_set_qspi_cpol(xqspi_regs_t * XQSPIx,uint32_t cpol)1557 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_cpol(xqspi_regs_t *XQSPIx, uint32_t cpol)
1558 {
1559 MODIFY_REG(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CPOL, cpol << XQSPI_QSPI_CTRL_CPOL_Pos);
1560 }
1561
1562 /**
1563 * @brief Get clock polarity
1564 *
1565 * Register|BitsName
1566 * --------|--------
1567 * CTRL |CPOL
1568 *
1569 * @param XQSPIx XQSPI instance
1570 * @retval Returned Value can be one of the following values:
1571 * @arg @ref LL_XQSPI_SCPOL_LOW
1572 * @arg @ref LL_XQSPI_SCPOL_HIGH
1573 */
ll_xqspi_get_qspi_cpol(xqspi_regs_t * XQSPIx)1574 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_cpol(xqspi_regs_t *XQSPIx)
1575 {
1576 return (uint32_t)(READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CPOL) >> XQSPI_QSPI_CTRL_CPOL_Pos);
1577 }
1578
1579 /**
1580 * @brief Set clock phase
1581 * @note This bit should not be changed when communication is ongoing.
1582 *
1583 * Register|BitsName
1584 * --------|--------
1585 * CTRL |CPHA
1586 *
1587 * @param XQSPIx XQSPI instance
1588 * @param cpha This parameter can be one of the following values:
1589 * @arg @ref LL_XQSPI_SCPHA_1EDGE
1590 * @arg @ref LL_XQSPI_SCPHA_2EDGE
1591 * @retval None
1592 */
ll_xqspi_set_qspi_cpha(xqspi_regs_t * XQSPIx,uint32_t cpha)1593 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_cpha(xqspi_regs_t *XQSPIx, uint32_t cpha)
1594 {
1595 MODIFY_REG(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CPHA, cpha << XQSPI_QSPI_CTRL_CPHA_Pos);
1596 }
1597
1598 /**
1599 * @brief Get clock phase
1600 *
1601 * Register|BitsName
1602 * --------|--------
1603 * CTRL |CPHA
1604 *
1605 * @param XQSPIx XQSPI instance
1606 * @retval Returned Value can be one of the following values:
1607 * @arg @ref LL_XQSPI_SCPHA_1EDGE
1608 * @arg @ref LL_XQSPI_SCPHA_2EDGE
1609 */
ll_xqspi_get_qspi_cpha(xqspi_regs_t * XQSPIx)1610 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_cpha(xqspi_regs_t *XQSPIx)
1611 {
1612 return (uint32_t)(READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CPHA) >> XQSPI_QSPI_CTRL_CPHA_Pos);
1613 }
1614
1615 /**
1616 * @brief Set serial data order
1617 *
1618 * Register|BitsName
1619 * --------|--------
1620 * CTRL |MSB1ST
1621 *
1622 * @param XQSPIx XQSPI instance
1623 * @param order This parameter can be one of the following values:
1624 * @arg @ref LL_XQSPI_QSPI_LSB
1625 * @arg @ref LL_XQSPI_QSPI_MSB
1626 * @retval None
1627 */
ll_xqspi_set_qspi_data_order(xqspi_regs_t * XQSPIx,uint32_t order)1628 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_data_order(xqspi_regs_t *XQSPIx, uint32_t order)
1629 {
1630 MODIFY_REG(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_MSB1ST, order);
1631 }
1632
1633 /**
1634 * @brief Get serial data order
1635 *
1636 * Register|BitsName
1637 * --------|--------
1638 * CTRL |MSB1ST
1639 *
1640 * @param XQSPIx XQSPI instance
1641 * @retval Returned Value can be one of the following values:
1642 * @arg @ref LL_XQSPI_QSPI_LSB
1643 * @arg @ref LL_XQSPI_QSPI_MSB
1644 */
ll_xqspi_get_qspi_data_order(xqspi_regs_t * XQSPIx)1645 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_data_order(xqspi_regs_t *XQSPIx)
1646 {
1647 return (uint32_t)(READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_MSB1ST));
1648 }
1649
1650 /**
1651 * @brief Enable continuous transfer mode
1652 *
1653 * Register|BitsName
1654 * --------|--------
1655 * CTRL |CONTXFER
1656 *
1657 * @param XQSPIx XQSPI instance
1658 * @retval None
1659 */
ll_xqspi_enable_qspi_contxfer(xqspi_regs_t * XQSPIx)1660 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_contxfer(xqspi_regs_t *XQSPIx)
1661 {
1662 SET_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CONTXFER);
1663 }
1664
1665 /**
1666 * @brief Disable continuous transfer mode
1667 *
1668 * Register|BitsName
1669 * --------|--------
1670 * CTRL |CONTXFER
1671 *
1672 * @param XQSPIx XQSPI instance
1673 * @retval None
1674 */
ll_xqspi_disable_qspi_contxfer(xqspi_regs_t * XQSPIx)1675 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_contxfer(xqspi_regs_t *XQSPIx)
1676 {
1677 CLEAR_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CONTXFER);
1678 }
1679
1680 /**
1681 * @brief Check if continuous transfer mode is enabled
1682 *
1683 * Register|BitsName
1684 * --------|--------
1685 * CTRL |CONTXFER
1686 *
1687 * @param XQSPIx XQSPI instance
1688 * @retval State of bit (1 or 0).
1689 */
ll_xqspi_is_enabled_qspi_contxfer(xqspi_regs_t * XQSPIx)1690 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_contxfer(xqspi_regs_t *XQSPIx)
1691 {
1692 return (READ_BITS(XQSPIx->QSPI.CTRL, XQSPI_QSPI_CTRL_CONTXFER) == (XQSPI_QSPI_CTRL_CONTXFER));
1693 }
1694
1695 /**
1696 * @brief Enable continuous transfer extend mode
1697 *
1698 * Register|BitsName
1699 * --------|--------
1700 * AUX_CTRL|CONTXFERX
1701 *
1702 * @param XQSPIx XQSPI instance
1703 * @retval None
1704 */
ll_xqspi_enable_qspi_contxfer_extend(xqspi_regs_t * XQSPIx)1705 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_contxfer_extend(xqspi_regs_t *XQSPIx)
1706 {
1707 SET_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_CONTXFERX);
1708 }
1709
1710 /**
1711 * @brief Disable continuous transfer extend mode
1712 *
1713 * Register|BitsName
1714 * --------|--------
1715 * AUX_CTRL|CONTXFERX
1716 *
1717 * @param XQSPIx XQSPI instance
1718 * @retval None
1719 */
ll_xqspi_disable_qspi_contxfer_extend(xqspi_regs_t * XQSPIx)1720 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_contxfer_extend(xqspi_regs_t *XQSPIx)
1721 {
1722 CLEAR_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_CONTXFERX);
1723 }
1724
1725 /**
1726 * @brief Check if continuous transfer extend mode is enabled
1727 *
1728 * Register|BitsName
1729 * --------|--------
1730 * AUX_CTRL|CONTXFERX
1731 *
1732 * @param XQSPIx XQSPI instance
1733 * @retval State of bit (1 or 0).
1734 */
ll_xqspi_is_enabled_qspi_contxfer_extend(xqspi_regs_t * XQSPIx)1735 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_contxfer_extend(xqspi_regs_t *XQSPIx)
1736 {
1737 return (READ_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_CONTXFERX) == (XQSPI_QSPI_AUXCTRL_CONTXFERX));
1738 }
1739
1740 /**
1741 * @brief Set data size
1742 * @note These bits should not be changed when communication is ongoing.
1743 *
1744 * Register|BitsName
1745 * --------|--------
1746 * AUX_CTRL|BITSIZE
1747 *
1748 * @param XQSPIx XQSPI instance
1749 * @param szie This parameter can be one of the following values:
1750 * @arg @ref LL_XQSPI_QSPI_DATASIZE_4BIT
1751 * @arg @ref LL_XQSPI_QSPI_DATASIZE_8BIT
1752 * @arg @ref LL_XQSPI_QSPI_DATASIZE_12BIT
1753 * @arg @ref LL_XQSPI_QSPI_DATASIZE_16BIT
1754 * @arg @ref LL_XQSPI_QSPI_DATASIZE_20BIT
1755 * @arg @ref LL_XQSPI_QSPI_DATASIZE_24BIT
1756 * @arg @ref LL_XQSPI_QSPI_DATASIZE_28BIT
1757 * @arg @ref LL_XQSPI_QSPI_DATASIZE_32BIT
1758 * @retval None
1759 */
ll_xqspi_set_qspi_datasize(xqspi_regs_t * XQSPIx,uint32_t szie)1760 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_datasize(xqspi_regs_t *XQSPIx, uint32_t szie)
1761 {
1762 MODIFY_REG(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_BITSIZE, szie);
1763 }
1764
1765 /**
1766 * @brief Get data size
1767 *
1768 * Register|BitsName
1769 * --------|--------
1770 * AUX_CTRL|BITSIZE
1771 *
1772 * @param XQSPIx XQSPI instance
1773 * @retval Returned Value can be one of the following values:
1774 * @arg @ref LL_XQSPI_QSPI_DATASIZE_4BIT
1775 * @arg @ref LL_XQSPI_QSPI_DATASIZE_8BIT
1776 * @arg @ref LL_XQSPI_QSPI_DATASIZE_12BIT
1777 * @arg @ref LL_XQSPI_QSPI_DATASIZE_16BIT
1778 * @arg @ref LL_XQSPI_QSPI_DATASIZE_20BIT
1779 * @arg @ref LL_XQSPI_QSPI_DATASIZE_24BIT
1780 * @arg @ref LL_XQSPI_QSPI_DATASIZE_28BIT
1781 * @arg @ref LL_XQSPI_QSPI_DATASIZE_32BIT
1782 */
ll_xqspi_get_qspi_datasize(xqspi_regs_t * XQSPIx)1783 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_datasize(xqspi_regs_t *XQSPIx)
1784 {
1785 return (uint32_t)(READ_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_BITSIZE));
1786 }
1787
1788 /**
1789 * @brief Enable inhibt data input to RX FIFO
1790 *
1791 * Register|BitsName
1792 * --------|--------
1793 * AUX_CTRL|INHIBITDIN
1794 *
1795 * @param XQSPIx XQSPI instance
1796 * @retval None
1797 */
ll_xqspi_enable_inhibt_rx(xqspi_regs_t * XQSPIx)1798 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_inhibt_rx(xqspi_regs_t *XQSPIx)
1799 {
1800 SET_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDIN);
1801 }
1802
1803 /**
1804 * @brief Disable inhibt data input to RX FIFO
1805 *
1806 * Register|BitsName
1807 * --------|--------
1808 * AUX_CTRL|INHIBITDIN
1809 *
1810 * @param XQSPIx XQSPI instance
1811 * @retval None
1812 */
ll_xqspi_disable_inhibt_rx(xqspi_regs_t * XQSPIx)1813 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_inhibt_rx(xqspi_regs_t *XQSPIx)
1814 {
1815 CLEAR_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDIN);
1816 }
1817
1818 /**
1819 * @brief Check if inhibt data input to RX FIFO is enabled
1820 *
1821 * Register|BitsName
1822 * --------|--------
1823 * AUX_CTRL|INHIBITDIN
1824 *
1825 * @param XQSPIx XQSPI instance
1826 * @retval State of bit (1 or 0).
1827 */
ll_xqspi_is_enabled_inhibt_rx(xqspi_regs_t * XQSPIx)1828 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_inhibt_rx(xqspi_regs_t *XQSPIx)
1829 {
1830 return (READ_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDIN) == XQSPI_QSPI_AUXCTRL_INHIBITDIN);
1831 }
1832
1833 /**
1834 * @brief Enable inhibt data output to TX FIFO
1835 *
1836 * Register|BitsName
1837 * --------|--------
1838 * AUX_CTRL|INHIBITDOUT
1839 *
1840 * @param XQSPIx XQSPI instance
1841 * @retval None
1842 */
ll_xqspi_enable_inhibt_tx(xqspi_regs_t * XQSPIx)1843 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_inhibt_tx(xqspi_regs_t *XQSPIx)
1844 {
1845 SET_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDOUT);
1846 }
1847
1848 /**
1849 * @brief Disable inhibt data output to TX FIFO
1850 *
1851 * Register|BitsName
1852 * --------|--------
1853 * AUX_CTRL|INHIBITDOUT
1854 *
1855 * @param XQSPIx XQSPI instance
1856 * @retval None
1857 */
ll_xqspi_disable_inhibt_tx(xqspi_regs_t * XQSPIx)1858 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_inhibt_tx(xqspi_regs_t *XQSPIx)
1859 {
1860 CLEAR_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDOUT);
1861 }
1862
1863 /**
1864 * @brief Check if inhibt data input to TX FIFO is enabled
1865 *
1866 * Register|BitsName
1867 * --------|--------
1868 * AUX_CTRL|INHIBITDOUT
1869 *
1870 * @param XQSPIx XQSPI instance
1871 * @retval State of bit (1 or 0).
1872 */
ll_xqspi_is_enabled_inhibt_tx(xqspi_regs_t * XQSPIx)1873 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_inhibt_tx(xqspi_regs_t *XQSPIx)
1874 {
1875 return (READ_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_INHIBITDOUT) == XQSPI_QSPI_AUXCTRL_INHIBITDOUT);
1876 }
1877
1878 /**
1879 * @brief Set frame format
1880 * @note These bits should not be changed when communication is ongoing.
1881 *
1882 * Register|BitsName
1883 * --------|--------
1884 * AUX_CTRL|QMODE
1885 *
1886 * @param XQSPIx XQSPI instance
1887 * @param format This parameter can be one of the following values:
1888 * @arg @ref LL_XQSPI_QSPI_FRF_SPI
1889 * @arg @ref LL_XQSPI_QSPI_FRF_DUALSPI
1890 * @arg @ref LL_XQSPI_QSPI_FRF_QUADSPI
1891 * @retval None
1892 */
ll_xqspi_set_qspi_frf(xqspi_regs_t * XQSPIx,uint32_t format)1893 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_frf(xqspi_regs_t *XQSPIx, uint32_t format)
1894 {
1895 MODIFY_REG(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_QMODE, format);
1896 }
1897
1898 /**
1899 * @brief Get frame format
1900 *
1901 * Register|BitsName
1902 * --------|--------
1903 * AUX_CTRL|QMODE
1904 *
1905 * @param XQSPIx XQSPI instance
1906 * @retval Returned Value can be one even value:
1907 * @arg @ref LL_XQSPI_QSPI_FRF_SPI
1908 * @arg @ref LL_XQSPI_QSPI_FRF_DUALSPI
1909 * @arg @ref LL_XQSPI_QSPI_FRF_QUADSPI
1910 */
ll_xqspi_get_qspi_frf(xqspi_regs_t * XQSPIx)1911 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_frf(xqspi_regs_t *XQSPIx)
1912 {
1913 return (uint32_t)(READ_BITS(XQSPIx->QSPI.AUX_CTRL, XQSPI_QSPI_AUXCTRL_QMODE));
1914 }
1915
1916 /**
1917 * @brief Get QSPI status
1918 *
1919 * Register|BitsName
1920 * --------|--------
1921 * STATUS | RXFULL RXWMARK RXEMPTY TXFULL TXWMARK TXEMPTY XFERIP
1922 *
1923 * @param XQSPIx XQSPI instance
1924 * @retval Returned Value can be one or combination of the following values:
1925 * @arg @ref LL_XQSPI_QSPI_STAT_RFTF
1926 * @arg @ref LL_XQSPI_QSPI_STAT_RFF
1927 * @arg @ref LL_XQSPI_QSPI_STAT_RFE
1928 * @arg @ref LL_XQSPI_QSPI_STAT_TFTF
1929 * @arg @ref LL_XQSPI_QSPI_STAT_TFF
1930 * @arg @ref LL_XQSPI_QSPI_STAT_TFE
1931 * @arg @ref LL_XQSPI_QSPI_STAT_BUSY
1932 */
ll_xqspi_get_qspi_status(xqspi_regs_t * XQSPIx)1933 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_status(xqspi_regs_t *XQSPIx)
1934 {
1935 return (uint32_t)(READ_REG(XQSPIx->QSPI.STAT));
1936 }
1937
1938 /**
1939 * @brief Check active flag
1940 *
1941 * Register|BitsName
1942 * --------|--------
1943 * STATUS | RXFULL RXWMARK RXEMPTY TXFULL TXWMARK TXEMPTY XFERIP
1944 *
1945 * @param XQSPIx XQSPI instance
1946 * @param flag This parameter can be one of the following values:
1947 * @arg @ref LL_XQSPI_QSPI_STAT_RFTF
1948 * @arg @ref LL_XQSPI_QSPI_STAT_RFF
1949 * @arg @ref LL_XQSPI_QSPI_STAT_RFE
1950 * @arg @ref LL_XQSPI_QSPI_STAT_TFTF
1951 * @arg @ref LL_XQSPI_QSPI_STAT_TFF
1952 * @arg @ref LL_XQSPI_QSPI_STAT_TFE
1953 * @arg @ref LL_XQSPI_QSPI_STAT_BUSY
1954 * @retval State of bit (1 or 0).
1955 */
ll_xqspi_is_active_qspi_flag(xqspi_regs_t * XQSPIx,uint32_t flag)1956 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_active_qspi_flag(xqspi_regs_t *XQSPIx, uint32_t flag)
1957 {
1958 return (READ_BITS(XQSPIx->QSPI.STAT, flag) == (flag));
1959 }
1960
1961 /**
1962 * @brief Enable slave select output
1963 *
1964 * Register|BitsName
1965 * --------|--------
1966 * SLAVE_SEL|OUT3 OUT2 OUT1 OUT0
1967 *
1968 * @param XQSPIx XQSPI instance
1969 * @param ssout This parameter can between: 0 ~ 0xFF
1970 * @retval None
1971 */
ll_xqspi_enable_qspi_ssout(xqspi_regs_t * XQSPIx,uint32_t ssout)1972 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_ssout(xqspi_regs_t *XQSPIx, uint32_t ssout)
1973 {
1974 SET_BITS(XQSPIx->QSPI.SLAVE_SEL, ssout);
1975 }
1976
1977 /**
1978 * @brief Disable slave select output
1979 *
1980 * Register|BitsName
1981 * --------|--------
1982 * SLAVE_SEL|OUT3 OUT2 OUT1 OUT0
1983 *
1984 * @param XQSPIx XQSPI instance
1985 * @param ssout This parameter can between: 0 ~ 0xFF
1986 * @retval None
1987 */
ll_xqspi_disable_qspi_ssout(xqspi_regs_t * XQSPIx,uint32_t ssout)1988 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_ssout(xqspi_regs_t *XQSPIx, uint32_t ssout)
1989 {
1990 CLEAR_BITS(XQSPIx->QSPI.SLAVE_SEL, ssout);
1991 }
1992
1993 /**
1994 * @brief Set slave select output polarity
1995 *
1996 * Register|BitsName
1997 * --------|--------
1998 * SLAVE_SEL_POL|POL3 POL2 POL1 POL0
1999 *
2000 * @param XQSPIx XQSPI instance
2001 * @param sspol This parameter can between: 0 ~ 0xFF
2002 * @retval None
2003 */
ll_xqspi_set_qspi_sspol(xqspi_regs_t * XQSPIx,uint32_t sspol)2004 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_sspol(xqspi_regs_t *XQSPIx, uint32_t sspol)
2005 {
2006 SET_BITS(XQSPIx->QSPI.SLAVE_SEL_POL, sspol);
2007 }
2008
2009 /**
2010 * @brief Get slave select output polarity
2011 *
2012 * Register|BitsName
2013 * --------|--------
2014 * SLAVE_SEL_POL|POL3 POL2 POL1 POL0
2015 *
2016 * @param XQSPIx XQSPI instance
2017 * @retval Returned Value can between: 0 ~ 0xFF
2018 */
ll_xqspi_get_qspi_sspol(xqspi_regs_t * XQSPIx)2019 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_sspol(xqspi_regs_t *XQSPIx)
2020 {
2021 return (uint32_t)(READ_REG(XQSPIx->QSPI.SLAVE_SEL_POL));
2022 }
2023
2024 /**
2025 * @brief Get FIFO Transmission Level
2026 *
2027 * Register|BitsName
2028 * --------|--------
2029 * TX_FIFO_LVL | TXFIFOLVL
2030 *
2031 * @param XQSPIx XQSPI instance
2032 * @retval Returned Value can between: 0 ~ 16
2033 */
ll_xqspi_get_qspi_tx_fifo_level(xqspi_regs_t * XQSPIx)2034 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_tx_fifo_level(xqspi_regs_t *XQSPIx)
2035 {
2036 return (uint32_t)(READ_BITS(XQSPIx->QSPI.TX_FIFO_LVL, XQSPI_QSPI_TXFIFOLVL));
2037 }
2038
2039 /**
2040 * @brief Get FIFO reception Level
2041 *
2042 * Register|BitsName
2043 * --------|--------
2044 * RX_FIFO_LVL | RXFIFOLVL
2045 *
2046 * @param XQSPIx XQSPI instance
2047 * @retval Returned Value can between: 0 ~ 16
2048 */
ll_xqspi_get_qspi_rx_fifo_level(xqspi_regs_t * XQSPIx)2049 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_rx_fifo_level(xqspi_regs_t *XQSPIx)
2050 {
2051 return (uint32_t)(READ_BITS(XQSPIx->QSPI.RX_FIFO_LVL, XQSPI_QSPI_RXFIFOLVL));
2052 }
2053
2054 /**
2055 * @brief Enable interrupt
2056 * @note This bit controls the generation of an interrupt when an event occurs.
2057 *
2058 * Register|BitsName
2059 * --------|--------
2060 * INTEN |INT_EN
2061 *
2062 * @param XQSPIx XQSPI instance
2063 * @param mask This parameter can be one of the following values:
2064 * @arg @ref LL_XQSPI_QSPI_IM_DONE
2065 * @arg @ref LL_XQSPI_QSPI_IM_RFF
2066 * @arg @ref LL_XQSPI_QSPI_IM_RFTF
2067 * @arg @ref LL_XQSPI_QSPI_IM_TFTF
2068 * @arg @ref LL_XQSPI_QSPI_IM_TFE
2069 * @retval None
2070 */
ll_xqspi_enable_qspi_it(xqspi_regs_t * XQSPIx,uint32_t mask)2071 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi_it(xqspi_regs_t *XQSPIx, uint32_t mask)
2072 {
2073 SET_BITS(XQSPIx->QSPI.INTEN, mask);
2074 }
2075
2076 /**
2077 * @brief Disable interrupt
2078 * @note This bit controls the generation of an interrupt when an event occurs.
2079 *
2080 * Register|BitsName
2081 * --------|--------
2082 * INTEN |INT_EN
2083 *
2084 * @param XQSPIx XQSPI instance
2085 * @param mask This parameter can be one of the following values:
2086 * @arg @ref LL_XQSPI_QSPI_IM_DONE
2087 * @arg @ref LL_XQSPI_QSPI_IM_RFF
2088 * @arg @ref LL_XQSPI_QSPI_IM_RFTF
2089 * @arg @ref LL_XQSPI_QSPI_IM_TFTF
2090 * @arg @ref LL_XQSPI_QSPI_IM_TFE
2091 * @retval None
2092 */
ll_xqspi_disable_qspi_it(xqspi_regs_t * XQSPIx,uint32_t mask)2093 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi_it(xqspi_regs_t *XQSPIx, uint32_t mask)
2094 {
2095 CLEAR_BITS(XQSPIx->QSPI.INTEN, mask);
2096 }
2097
2098 /**
2099 * @brief Check if interrupt is enabled
2100 *
2101 * Register|BitsName
2102 * --------|--------
2103 * INTEN |INT_EN
2104 *
2105 * @param XQSPIx XQSPI instance
2106 * @param mask This parameter can be one of the following values:
2107 * @arg @ref LL_XQSPI_QSPI_IM_DONE
2108 * @arg @ref LL_XQSPI_QSPI_IM_RFF
2109 * @arg @ref LL_XQSPI_QSPI_IM_RFTF
2110 * @arg @ref LL_XQSPI_QSPI_IM_TFTF
2111 * @arg @ref LL_XQSPI_QSPI_IM_TFE
2112 * @retval State of bit (1 or 0).
2113 */
ll_xqspi_is_enabled_qspi_it(xqspi_regs_t * XQSPIx,uint32_t mask)2114 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi_it(xqspi_regs_t *XQSPIx, uint32_t mask)
2115 {
2116 return (READ_BITS(XQSPIx->QSPI.INTEN, mask) == (mask));
2117 }
2118
2119 /**
2120 * @brief Get XQSPI interrupt flags
2121 *
2122 * Register|BitsName
2123 * --------|--------
2124 * INTSTAT |INT_STAT
2125 *
2126 * @param XQSPIx XQSPI instance
2127 * @retval Returned Value can be one or combination of the following values:
2128 * @arg @ref LL_XQSPI_QSPI_IS_DONE
2129 * @arg @ref LL_XQSPI_QSPI_IS_RFF
2130 * @arg @ref LL_XQSPI_QSPI_IS_RFTF
2131 * @arg @ref LL_XQSPI_QSPI_IS_TFTF
2132 * @arg @ref LL_XQSPI_QSPI_IS_TFE
2133 */
ll_xqspi_get_it_flag(xqspi_regs_t * XQSPIx)2134 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_it_flag(xqspi_regs_t *XQSPIx)
2135 {
2136 return (uint32_t)(READ_REG(XQSPIx->QSPI.INTSTAT));
2137 }
2138
2139 /**
2140 * @brief Check interrupt flag
2141 *
2142 * Register|BitsName
2143 * --------|--------
2144 * INTSTAT | XFER_DPULSE
2145 * INTSTAT | RX_FPULSE
2146 * INTSTAT | RX_WPULSE
2147 * INTSTAT | TX_WPULSE
2148 * INTSTAT | TX_EPULSE
2149 *
2150 * @param XQSPIx XQSPI instance
2151 * @param flag This parameter can be one of the following values:
2152 * @arg @ref LL_XQSPI_QSPI_IS_DONE
2153 * @arg @ref LL_XQSPI_QSPI_IS_RFF
2154 * @arg @ref LL_XQSPI_QSPI_IS_RFTF
2155 * @arg @ref LL_XQSPI_QSPI_IS_TFTF
2156 * @arg @ref LL_XQSPI_QSPI_IS_TFE
2157 * @retval State of bit (1 or 0).
2158 */
ll_xqspi_is_qspi_it_flag(xqspi_regs_t * XQSPIx,uint32_t flag)2159 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_qspi_it_flag(xqspi_regs_t *XQSPIx, uint32_t flag)
2160 {
2161 return (READ_BITS(XQSPIx->QSPI.INTSTAT, flag) == (flag));
2162 }
2163
2164 /**
2165 * @brief Clear interrupt flag
2166 * @note Clearing interrupt flag is done by writting INTCLR register
2167 *
2168 * Register|BitsName
2169 * --------|--------
2170 * INTCLR |INT_CLR
2171 *
2172 * @param XQSPIx XQSPI instance
2173 * @param flag This parameter can be one of the following values:
2174 * @arg @ref LL_XQSPI_QSPI_IM_DONE
2175 * @arg @ref LL_XQSPI_QSPI_IM_RFF
2176 * @arg @ref LL_XQSPI_QSPI_IM_RFTF
2177 * @arg @ref LL_XQSPI_QSPI_IM_TFTF
2178 * @arg @ref LL_XQSPI_QSPI_IM_TFE
2179 * @retval None
2180 */
ll_xqspi_clear_qspi_flag(xqspi_regs_t * XQSPIx,uint32_t flag)2181 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_clear_qspi_flag(xqspi_regs_t *XQSPIx, uint32_t flag)
2182 {
2183 WRITE_REG(XQSPIx->QSPI.INTCLR, flag);
2184 }
2185
2186 /**
2187 * @brief Set master inter-transfer delay
2188 *
2189 * Register|BitsName
2190 * --------|--------
2191 * MSTR_IT_DELAY | MWAIT
2192 *
2193 * @param XQSPIx XQSPI instance
2194 * @param wait This parameter can between: 0 ~ 255
2195 * @retval None
2196 */
ll_xqspi_set_qspi_wait(xqspi_regs_t * XQSPIx,uint32_t wait)2197 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_wait(xqspi_regs_t *XQSPIx, uint32_t wait)
2198 {
2199 MODIFY_REG(XQSPIx->QSPI.MSTR_IT_DELAY, XQSPI_QSPI_MWAIT_MWAIT, wait << XQSPI_QSPI_MWAIT_MWAIT_Pos);
2200 }
2201
2202 /**
2203 * @brief Get master inter-transfer delay
2204 *
2205 * Register|BitsName
2206 * --------|--------
2207 * MSTR_IT_DELAY | MWAIT
2208 *
2209 * @param XQSPIx XQSPI instance
2210 * @retval Returned Value can between: 0 ~ 255
2211 */
ll_xqspi_get_qspi_wait(xqspi_regs_t * XQSPIx)2212 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_wait(xqspi_regs_t *XQSPIx)
2213 {
2214 return (uint32_t)(READ_BITS(XQSPIx->QSPI.MSTR_IT_DELAY, XQSPI_QSPI_MWAIT_MWAIT) >> XQSPI_QSPI_MWAIT_MWAIT_Pos);
2215 }
2216
2217 /**
2218 * @brief Enable QSPI
2219 * @note This bit should not be enable when XIP is ongoing.
2220 *
2221 * Register|BitsName
2222 * --------|--------
2223 * SPIEN |EN
2224 *
2225 * @param XQSPIx XQSPI instance
2226 * @retval None
2227 */
ll_xqspi_enable_qspi(xqspi_regs_t * XQSPIx)2228 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_qspi(xqspi_regs_t *XQSPIx)
2229 {
2230 SET_BITS(XQSPIx->QSPI.SPIEN, XQSPI_QSPI_EN_EN);
2231 }
2232
2233 /**
2234 * @brief Disable QSPI
2235 *
2236 * Register|BitsName
2237 * --------|--------
2238 * SPIEN |EN
2239 *
2240 * @param XQSPIx XQSPI instance
2241 * @retval None
2242 */
ll_xqspi_disable_qspi(xqspi_regs_t * XQSPIx)2243 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_qspi(xqspi_regs_t *XQSPIx)
2244 {
2245 CLEAR_BITS(XQSPIx->QSPI.SPIEN, XQSPI_QSPI_EN_EN);
2246 }
2247
2248 /**
2249 * @brief Check if QSPI is enabled
2250 *
2251 * Register|BitsName
2252 * --------|--------
2253 * SPIEN |EN
2254 *
2255 * @param XQSPIx XQSPI instance
2256 * @retval State of bit (1 or 0).
2257 */
ll_xqspi_is_enabled_qspi(xqspi_regs_t * XQSPIx)2258 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enabled_qspi(xqspi_regs_t *XQSPIx)
2259 {
2260 return (READ_BITS(XQSPIx->QSPI.SPIEN, XQSPI_QSPI_EN_EN) == (XQSPI_QSPI_EN_EN));
2261 }
2262
2263 /**
2264 * @brief Set QSPI Flash write bits
2265 *
2266 * Register|BitsName
2267 * --------|--------
2268 * FLASH_WRITE |FLASH_WRITE
2269 *
2270 * @param XQSPIx XQSPI instance
2271 * @param bits This parameter can be one of the following values:
2272 * @arg @ref LL_XQSPI_FLASH_WRITE_128BIT
2273 * @arg @ref LL_XQSPI_FLASH_WRITE_32BIT
2274 * @retval None
2275 */
ll_xqspi_set_flash_write(xqspi_regs_t * XQSPIx,uint32_t bits)2276 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_flash_write(xqspi_regs_t *XQSPIx, uint32_t bits)
2277 {
2278 WRITE_REG(XQSPIx->QSPI.FLASH_WRITE, bits);
2279 }
2280
2281 /**
2282 * @brief Get QSPI Flash write bits
2283 *
2284 * Register|BitsName
2285 * --------|--------
2286 * FLASH_WRITE |FLASH_WRITE
2287 *
2288 * @param XQSPIx XQSPI instance
2289 * @retval Returned Value can be one of the following values:
2290 * @arg @ref LL_XQSPI_FLASH_WRITE_128BIT
2291 * @arg @ref LL_XQSPI_FLASH_WRITE_32BIT
2292 */
ll_xqspi_get_flash_write(xqspi_regs_t * XQSPIx)2293 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_flash_write(xqspi_regs_t *XQSPIx)
2294 {
2295 return READ_REG(XQSPIx->QSPI.FLASH_WRITE);
2296 }
2297
2298 /**
2299 * @brief Set QSPI Present Bypass
2300 *
2301 * Register|BitsName
2302 * --------|--------
2303 * BYPASS |BYPASS
2304 *
2305 * @param XQSPIx XQSPI instance
2306 * @param bypass This parameter can be one of the following values:
2307 * @arg @ref LL_XQSPI_ENABLE_PRESENT
2308 * @arg @ref LL_XQSPI_DISABLE_PRESENT
2309 * @retval None
2310 */
ll_xqspi_set_present_bypass(xqspi_regs_t * XQSPIx,uint32_t bypass)2311 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_present_bypass(xqspi_regs_t *XQSPIx, uint32_t bypass)
2312 {
2313 WRITE_REG(XQSPIx->QSPI.BYPASS, bypass);
2314 }
2315
2316 /**
2317 * @brief Get QSPI Present Bypass
2318 *
2319 * Register|BitsName
2320 * --------|--------
2321 * BYPASS |BYPASS
2322 *
2323 * @param XQSPIx XQSPI instance
2324 * @retval Returned Value can be one of the following values:
2325 * @arg @ref LL_XQSPI_ENABLE_PRESENT
2326 * @arg @ref LL_XQSPI_DISABLE_PRESENT
2327 */
ll_xqspi_get_present_bypass(xqspi_regs_t * XQSPIx)2328 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_present_bypass(xqspi_regs_t *XQSPIx)
2329 {
2330 return READ_REG(XQSPIx->QSPI.BYPASS);
2331 }
2332
2333 /**
2334 * @brief Enable exflash power
2335 * @note This bit should not be changed when XIP is ongoing.
2336 *
2337 * Register|BitsName
2338 * --------|--------
2339 * PWR_RET01 | EFLASH_PAD_EN
2340 *
2341 * @retval None
2342 */
ll_xqspi_enable_exflash_power(void)2343 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_exflash_power(void)
2344 {
2345 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_EFLASH_PAD_EN);
2346 }
2347
2348 /**
2349 * @brief Disable exflash power
2350 * @note This bit should not be changed when XIP is ongoing.
2351 *
2352 * Register|BitsName
2353 * --------|--------
2354 * PWR_RET01 | EFLASH_PAD_EN
2355 *
2356 * @retval None
2357 */
ll_xqspi_disable_exflash_power(void)2358 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_exflash_power(void)
2359 {
2360 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_EFLASH_PAD_EN);
2361 }
2362
2363 /**
2364 * @brief Check if exflash power is enabled
2365 *
2366 * Register|BitsName
2367 * --------|--------
2368 * PWR_RET01 | EFLASH_PAD_EN
2369 *
2370 * @retval State of bit (1 or 0).
2371 */
ll_xqspi_is_enable_exflash_power(void)2372 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enable_exflash_power(void)
2373 {
2374 return (READ_BITS(AON->PWR_RET01, AON_PWR_REG01_EFLASH_PAD_EN) == (AON_PWR_REG01_EFLASH_PAD_EN));
2375 }
2376
2377 /**
2378 * @brief Set XQSPI serial clock
2379 *
2380 * Register|BitsName
2381 * --------|--------
2382 * PWR_RET01 | XF_SCK_CLK_SEL
2383 *
2384 * @param speed This parameter can be one of the following values:
2385 * @arg @ref LL_XQSPI_BAUD_RATE_64M
2386 * @arg @ref LL_XQSPI_BAUD_RATE_48M
2387 * @arg @ref LL_XQSPI_BAUD_RATE_32M
2388 * @arg @ref LL_XQSPI_BAUD_RATE_24M
2389 * @arg @ref LL_XQSPI_BAUD_RATE_16M
2390 * @retval None
2391 */
ll_xqspi_set_qspi_speed(uint32_t speed)2392 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_set_qspi_speed(uint32_t speed)
2393 {
2394 MODIFY_REG(AON->PWR_RET01, AON_PWR_REG01_XF_SCK_CLK_SEL, speed);
2395 }
2396
2397 /**
2398 * @brief Get XQSPI serial clock
2399 *
2400 * Register|BitsName
2401 * --------|--------
2402 * PWR_RET01 | XF_SCK_CLK_SEL
2403 *
2404 * @retval Returned Value can be one of the following values:
2405 * @arg @ref LL_XQSPI_BAUD_RATE_64M
2406 * @arg @ref LL_XQSPI_BAUD_RATE_48M
2407 * @arg @ref LL_XQSPI_BAUD_RATE_32M
2408 * @arg @ref LL_XQSPI_BAUD_RATE_24M
2409 * @arg @ref LL_XQSPI_BAUD_RATE_16M
2410 */
ll_xqspi_get_qspi_speed(void)2411 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_get_qspi_speed(void)
2412 {
2413 return (uint32_t)(READ_BITS(AON->PWR_RET01, AON_PWR_REG01_XF_SCK_CLK_SEL));
2414 }
2415
2416 /**
2417 * @brief Enable cache data retention.
2418 * @note This bit should not be changed when XIP is ongoing..
2419 *
2420 * Register|BitsName
2421 * --------|--------
2422 * PWR_RET01 | XF_TAG_RET
2423 *
2424 * @retval None
2425 */
ll_xqspi_enable_cache_retention(void)2426 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_enable_cache_retention(void)
2427 {
2428 SET_BITS(AON->PWR_RET01, AON_PWR_REG01_XF_TAG_RET);
2429 }
2430
2431 /**
2432 * @brief Disable cache data retention.
2433 * @note This bit should not be changed when XIP is ongoing.
2434 *
2435 * Register|BitsName
2436 * --------|--------
2437 * PWR_RET01 | XF_TAG_RET
2438 *
2439 * @retval None
2440 */
ll_xqspi_disable_cache_retention(void)2441 SECTION_RAM_CODE __STATIC_INLINE void ll_xqspi_disable_cache_retention(void)
2442 {
2443 CLEAR_BITS(AON->PWR_RET01, AON_PWR_REG01_XF_TAG_RET);
2444 }
2445
2446 /**
2447 * @brief Check if tag memory retention is enabled
2448 *
2449 * Register|BitsName
2450 * --------|--------
2451 * PWR_RET01 | XF_TAG_RET
2452 *
2453 * @retval State of bit (1 or 0).
2454 */
ll_xqspi_is_enable_cache_retention(void)2455 SECTION_RAM_CODE __STATIC_INLINE uint32_t ll_xqspi_is_enable_cache_retention(void)
2456 {
2457 return (READ_BITS(AON->PWR_RET01, AON_PWR_REG01_XF_TAG_RET) == (AON_PWR_REG01_XF_TAG_RET));
2458 }
2459
2460 /** @} */
2461
2462 /** @defgroup XQSPI_LL_Init XQSPI Initialization and de-initialization functions
2463 * @{
2464 */
2465
2466 /**
2467 * @brief De-initialize XQSPI registers (Registers restored to their default values).
2468 * @param XQSPIx XQSPI instance
2469 * @retval An error_status_t enumeration value:
2470 * - SUCCESS: XQSPI registers are de-initialized
2471 * - ERROR: XQSPI registers are not de-initialized
2472 */
2473 error_status_t ll_xqspi_deinit(xqspi_regs_t *XQSPIx);
2474
2475 /**
2476 * @brief Initialize XQSPI registers according to the specified
2477 * parameters in default.
2478 * @param XQSPIx XQSPI instance
2479 * @param p_xqspi_init Pointer to a ll_xqspi_init_t structure that contains the configuration
2480 * information for the specified XQPSI peripheral.
2481 * @retval An error_status_t enumeration value:
2482 * - SUCCESS: XQSPI registers are initialized according to default
2483 * - ERROR: Problem occurred during XQSPI Registers initialization
2484 */
2485 error_status_t ll_xqspi_init(xqspi_regs_t *XQSPIx, ll_xqspi_init_t *p_xqspi_init);
2486
2487 /**
2488 * @brief Set each field of a @ref ll_xqspi_init_t type structure to default value.
2489 * @param p_xqspi_init Pointer to a @ref ll_xqspi_init_t structure
2490 * whose fields will be set to default values.
2491 * @retval None
2492 */
2493 void ll_xqspi_struct_init(ll_xqspi_init_t *p_xqspi_init);
2494
2495 /** @} */
2496
2497 /** @} */
2498
2499 #endif /* XQSPI */
2500
2501 #ifdef __cplusplus
2502 }
2503 #endif
2504
2505 #endif /* __GR55xx_LL_XQSPI_H__ */
2506
2507 /** @} */
2508
2509 /** @} */
2510
2511 /** @} */
2512