1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 /* 3 * include/linux/amlogic/aml_sd.h 4 * 5 * Copyright (C) 2016 Amlogic, Inc. All rights reserved. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 */ 18 19 #ifndef __AML_SD_H__ 20 #define __AML_SD_H__ 21 22 #include <linux/mmc/card.h> 23 #include <linux/interrupt.h> 24 /* unknown */ 25 #define CARD_TYPE_UNKNOWN 0 26 /* MMC card */ 27 #define CARD_TYPE_MMC 1 28 /* SD card */ 29 #define CARD_TYPE_SD 2 30 /* SDIO card */ 31 #define CARD_TYPE_SDIO 3 32 /* SD combo (IO+mem) card */ 33 #define CARD_TYPE_SD_COMBO 4 34 /* NON sdio device (means SD/MMC card) */ 35 #define CARD_TYPE_NON_SDIO 5 36 37 #define aml_card_type_unknown(c) ((c)->card_type == CARD_TYPE_UNKNOWN) 38 #define aml_card_type_mmc(c) ((c)->card_type == CARD_TYPE_MMC) 39 #define aml_card_type_sd(c) ((c)->card_type == CARD_TYPE_SD) 40 #define aml_card_type_sdio(c) ((c)->card_type == CARD_TYPE_SDIO) 41 #define aml_card_type_non_sdio(c) ((c)->card_type == CARD_TYPE_NON_SDIO) 42 43 /* flag is "@ML" */ 44 #define TUNED_FLAG 0x004C4D40 45 /* version is "V1" */ 46 #define TUNED_VERSION 0x00003156 47 /* magic is 0x00487e44 */ 48 #define TUNED_MAGIC 0x00487e44 49 50 struct mmc_phase { 51 unsigned int core_phase; 52 unsigned int tx_phase; 53 unsigned int rx_phase; 54 unsigned int tx_delay; 55 }; 56 57 struct para_e { 58 struct mmc_phase init; 59 struct mmc_phase hs; 60 struct mmc_phase hs2; 61 struct mmc_phase hs4; 62 }; 63 64 #define LATCHING_RXPHASE 0 65 #define LATCHING_TXPHASE 1 66 #define LATCHING_FIXADJ 2 67 68 struct meson_mmc_data { 69 unsigned int tx_delay_mask; 70 unsigned int rx_delay_mask; 71 unsigned int always_on; 72 unsigned int adjust; 73 u8 latching_mode; 74 }; 75 76 enum aml_host_bus_fsm { /* Host bus fsm status */ 77 BUS_FSM_IDLE, /* 0, idle */ 78 BUS_FSM_SND_CMD, /* 1, send cmd */ 79 BUS_FSM_CMD_DONE, /* 2, wait for cmd done */ 80 BUS_FSM_RESP_START, /* 3, resp start */ 81 BUS_FSM_RESP_DONE, /* 4, wait for resp done */ 82 BUS_FSM_DATA_START, /* 5, data start */ 83 BUS_FSM_DATA_DONE, /* 6, wait for data done */ 84 BUS_FSM_DESC_WRITE_BACK, /* 7, wait for desc write back */ 85 BUS_FSM_IRQ_SERVICE, /* 8, wait for irq service */ 86 }; 87 88 struct sd_emmc_desc { 89 u32 cmd_cfg; 90 u32 cmd_arg; 91 u32 cmd_data; 92 u32 cmd_resp; 93 }; 94 95 struct meson_mmc_hole { 96 u8 start; 97 u8 size; 98 }; 99 100 struct hs400_para { 101 unsigned int delay1; 102 unsigned int delay2; 103 unsigned int intf3; 104 unsigned int flag; 105 }; 106 107 struct hs200_para { 108 unsigned int adjust; 109 }; 110 111 struct hs_para { 112 unsigned int adjust; 113 }; 114 115 struct aml_tuning_para { 116 unsigned int chip_id[4]; 117 unsigned int magic; 118 unsigned int vddee; 119 struct hs400_para hs4[7]; 120 struct hs200_para hs2; 121 struct hs_para hs; 122 unsigned int version; 123 unsigned int busmode; 124 unsigned int update; 125 int temperature; 126 long long checksum; 127 }; 128 129 struct meson_host { 130 struct device *dev; 131 struct meson_mmc_data *data; 132 struct mmc_host *mmc; 133 struct mmc_command *cmd; 134 135 void __iomem *regs; 136 void __iomem *pin_mux_base; 137 void __iomem *clk_tree_base; 138 struct resource *res[3]; 139 struct clk *core_clk; 140 struct clk *tx_clk; 141 struct clk *mmc_clk; 142 struct clk *mux[2]; 143 struct clk *mux1_in; 144 struct clk *clk[3]; 145 unsigned long req_rate; 146 bool ddr; 147 148 bool dram_access_quirk; 149 150 struct pinctrl *pinctrl; 151 struct pinctrl_state *pins_default; 152 struct pinctrl_state *pins_clk_gate; 153 154 unsigned int bounce_buf_size; 155 void *bounce_buf; 156 dma_addr_t bounce_dma_addr; 157 struct sd_emmc_desc *descs; 158 dma_addr_t descs_dma_addr; 159 160 int irq; 161 162 bool vqmmc_enabled; 163 struct para_e sdmmc; 164 char is_tuning; 165 unsigned int delay_cell; 166 bool needs_pre_post_req; 167 int sd_sdio_switch_volat_done; 168 int irq_sdio_sleep; 169 int sdio_irqen; 170 unsigned int emmc_boot_base; 171 u32 pin_mux_val; 172 u32 clk_tree_val; 173 u32 host_clk_val; 174 int debug_flag; 175 unsigned int card_type; 176 unsigned int card_insert; 177 u8 fixadj_have_hole; 178 struct meson_mmc_hole hole[3]; 179 u8 fix_hole; 180 u64 align[10]; 181 char cmd_retune; 182 unsigned int win_start; 183 u8 *blk_test; 184 u8 *adj_win; 185 unsigned int cmd_c; 186 int cd_irq; 187 irqreturn_t (*cd_gpio_isr)(int irq, void *dev_id); 188 int is_uart; 189 int sd_uart_init; 190 int first_temp_index; 191 int cur_temp_index; 192 int compute_cmd_delay; 193 int compute_coef; 194 unsigned int save_para; 195 unsigned int src_clk_rate; 196 struct aml_tuning_para para; 197 int run_pxp_flag; 198 int nwr_cnt; 199 bool ignore_desc_busy; 200 bool use_intf3_tuning; 201 bool src_clk_cfg_done; 202 struct dentry *debugfs_root; 203 }; 204 205 int sdio_reset_comm(struct mmc_card *card); 206 void sdio_reinit(void); 207 const char *get_wifi_inf(void); 208 int sdio_get_vendor(void); 209 void aml_host_bus_fsm_show(struct mmc_host *mmc, int status); 210 211 #define DRIVER_NAME "meson-gx-mmc" 212 213 #define SD_EMMC_CLOCK 0x0 214 #define CLK_DIV_MASK GENMASK(5, 0) 215 #define CLK_SRC_MASK GENMASK(7, 6) 216 #define CLK_CORE_PHASE_MASK GENMASK(9, 8) 217 #define CLK_TX_PHASE_MASK GENMASK(11, 10) 218 #define CLK_RX_PHASE_MASK GENMASK(13, 12) 219 #define CLK_PHASE_0 0 220 #define CLK_PHASE_180 2 221 #define CLK_V2_TX_DELAY_MASK GENMASK(19, 16) 222 #define CLK_V2_RX_DELAY_MASK GENMASK(23, 20) 223 #define CLK_V2_ALWAYS_ON BIT(24) 224 225 #define CLK_V3_TX_DELAY_MASK GENMASK(21, 16) 226 #define CLK_V3_RX_DELAY_MASK GENMASK(27, 22) 227 #define CLK_V3_ALWAYS_ON BIT(28) 228 #define CFG_IRQ_SDIO_SLEEP BIT(29) 229 #define CFG_IRQ_SDIO_SLEEP_DS BIT(30) 230 231 #define CLK_TX_DELAY_MASK(h) ((h)->data->tx_delay_mask) 232 #define CLK_RX_DELAY_MASK(h) ((h)->data->rx_delay_mask) 233 #define CLK_ALWAYS_ON(h) ((h)->data->always_on) 234 235 #define SD_EMMC_DELAY 0x4 236 237 #define SD_EMMC_ADJUST 0x8 238 #define ADJUST_ADJ_DELAY_MASK GENMASK(21, 16) 239 #define ADJUST_DS_EN BIT(15) 240 #define ADJUST_ADJ_EN BIT(13) 241 242 #define SD_EMMC_DELAY1 0x4 243 #define SD_EMMC_DELAY2 0x8 244 #define SD_EMMC_V3_ADJUST 0xc 245 #define CALI_SEL_MASK GENMASK(11, 8) 246 #define CALI_ENABLE BIT(12) 247 #define CFG_ADJUST_ENABLE BIT(13) 248 #define CALI_RISE BIT(14) 249 #define DS_ENABLE BIT(15) 250 #define CLK_ADJUST_DELAY GENMASK(21, 16) 251 #define ADJ_AUTO BIT(22) 252 253 #define SD_EMMC_CALOUT 0x10 254 #define SD_EMMC_ADJ_IDX_LOG 0x20 255 #define SD_EMMC_CLKTEST_LOG 0x24 256 #define CLKTEST_TIMES_MASK GENMASK(30, 0) 257 #define CLKTEST_DONE BIT(31) 258 #define SD_EMMC_CLKTEST_OUT 0x28 259 #define SD_EMMC_EYETEST_LOG 0x2c 260 #define EYETEST_TIMES_MASK GENMASK(30, 0) 261 #define EYETEST_DONE BIT(31) 262 #define SD_EMMC_EYETEST_OUT0 0x30 263 #define SD_EMMC_EYETEST_OUT1 0x34 264 #define SD_EMMC_INTF3 0x38 265 #define CLKTEST_EXP_MASK GENMASK(4, 0) 266 #define CLKTEST_ON_M BIT(5) 267 #define EYETEST_EXP_MASK GENMASK(10, 6) 268 #define EYETEST_ON BIT(11) 269 #define DS_SHT_M_MASK GENMASK(17, 12) 270 #define DS_SHT_EXP_MASK GENMASK(21, 18) 271 #define SD_INTF3 BIT(22) 272 273 #define EYETEST_SEL BIT(26) 274 #define RESP_SEL BIT(27) 275 #define CFG_RX_SEL BIT(26) 276 #define CFG_RX_PN BIT(27) 277 #define RESP_OLD BIT(28) 278 #define RESP_PN BIT(29) 279 #define RESP_DS BIT(30) 280 281 #define SD_EMMC_START 0x40 282 #define START_DESC_INIT BIT(0) 283 #define START_DESC_BUSY BIT(1) 284 #define START_DESC_ADDR_MASK GENMASK(31, 2) 285 286 #define SD_EMMC_CFG 0x44 287 #define CFG_BUS_WIDTH_MASK GENMASK(1, 0) 288 #define CFG_BUS_WIDTH_1 0x0 289 #define CFG_BUS_WIDTH_4 0x1 290 #define CFG_BUS_WIDTH_8 0x2 291 #define CFG_DDR BIT(2) 292 #define CFG_BLK_LEN_MASK GENMASK(7, 4) 293 #define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8) 294 #define CFG_RC_CC_MASK GENMASK(15, 12) 295 #define CFG_STOP_CLOCK BIT(22) 296 #define CFG_CLK_ALWAYS_ON BIT(18) 297 #define CFG_CHK_DS BIT(20) 298 #define CFG_AUTO_CLK BIT(23) 299 #define CFG_ERR_ABORT BIT(27) 300 301 #define SD_EMMC_STATUS 0x48 302 #define STATUS_BUSY BIT(31) 303 #define STATUS_DESC_BUSY BIT(30) 304 #define STATUS_DATI GENMASK(23, 16) 305 306 #define SD_EMMC_IRQ_EN 0x4c 307 #define IRQ_RXD_ERR_MASK GENMASK(7, 0) 308 #define IRQ_TXD_ERR BIT(8) 309 #define IRQ_DESC_ERR BIT(9) 310 #define IRQ_RESP_ERR BIT(10) 311 #define IRQ_CRC_ERR (IRQ_RXD_ERR_MASK | IRQ_TXD_ERR | IRQ_DESC_ERR | IRQ_RESP_ERR) 312 #define IRQ_RESP_TIMEOUT BIT(11) 313 #define IRQ_DESC_TIMEOUT BIT(12) 314 #define IRQ_TIMEOUTS (IRQ_RESP_TIMEOUT | IRQ_DESC_TIMEOUT) 315 #define IRQ_END_OF_CHAIN BIT(13) 316 #define IRQ_RESP_STATUS BIT(14) 317 #define IRQ_SDIO BIT(15) 318 #define CFG_CMD_SETUP BIT(17) 319 #define BUS_FSM_MASK GENMASK(29, 26) 320 #define IRQ_EN_MASK (IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN | IRQ_RESP_STATUS | IRQ_SDIO) 321 322 #define SD_EMMC_CMD_CFG 0x50 323 #define SD_EMMC_CMD_ARG 0x54 324 #define SD_EMMC_CMD_DAT 0x58 325 #define SD_EMMC_CMD_RSP 0x5c 326 #define SD_EMMC_CMD_RSP1 0x60 327 #define SD_EMMC_CMD_RSP2 0x64 328 #define SD_EMMC_CMD_RSP3 0x68 329 330 #define SD_EMMC_RXD 0x94 331 #define SD_EMMC_TXD 0x94 332 #define SD_EMMC_LAST_REG SD_EMMC_TXD 333 334 #define SD_EMMC_SRAM_DESC_BUF_OFF 0x200 335 #define SD_EMMC_SRAM_DATA_BUF_LEN 1024 336 #define SD_EMMC_SRAM_DATA_BUF_OFF 0x400 337 #define SD_EMMC_MAX_SEGS 256 338 #define SD_EMMC_MAX_REQ_SIZE (128 * 1024) 339 340 #define SD_EMMC_CFG_BLK_SIZE 512 /* internal buffer max: 512 bytes */ 341 #define SD_EMMC_CFG_RESP_TIMEOUT 256 /* in clock cycles */ 342 #define SD_EMMC_CMD_TIMEOUT 1024 /* in ms */ 343 #define SD_EMMC_CMD_TIMEOUT_DATA 4096 /* in ms */ 344 #define SD_EMMC_CFG_CMD_GAP 16 /* in clock cycles */ 345 #define SD_EMMC_DESC_BUF_LEN PAGE_SIZE 346 347 #define SD_EMMC_PRE_REQ_DONE BIT(0) 348 #define SD_EMMC_DESC_CHAIN_MODE BIT(1) 349 350 #define MUX_CLK_NUM_PARENTS 2 351 352 #define CMD_CFG_LENGTH_MASK GENMASK(8, 0) 353 #define CMD_CFG_BLOCK_MODE BIT(9) 354 #define CMD_CFG_R1B BIT(10) 355 #define CMD_CFG_END_OF_CHAIN BIT(11) 356 #define CMD_CFG_TIMEOUT_MASK GENMASK(15, 12) 357 #define CMD_CFG_NO_RESP BIT(16) 358 #define CMD_CFG_NO_CMD BIT(17) 359 #define CMD_CFG_DATA_IO BIT(18) 360 #define CMD_CFG_DATA_WR BIT(19) 361 #define CMD_CFG_RESP_NOCRC BIT(20) 362 #define CMD_CFG_RESP_128 BIT(21) 363 #define CMD_CFG_RESP_NUM BIT(22) 364 #define CMD_CFG_DATA_NUM BIT(23) 365 #define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24) 366 #define CMD_CFG_ERROR BIT(30) 367 #define CMD_CFG_OWNER BIT(31) 368 369 #define CMD_DATA_MASK GENMASK(31, 2) 370 #define CMD_DATA_BIG_ENDIAN BIT(1) 371 #define CMD_DATA_SRAM BIT(0) 372 #define CMD_RESP_MASK GENMASK(31, 1) 373 #define CMD_RESP_SRAM BIT(0) 374 #define EMMC_SDIO_CLOCK_FELD 0Xffff 375 #define CALI_HS_50M_ADJUST 0 376 #define ERROR 1 377 #define FIXED 2 378 #define SZ_1M 0x00100000 379 #define MMC_PATTERN_NAME "pattern" 380 #define MMC_PATTERN_OFFSET ((SZ_1M * (36 + 3)) / 512) 381 #define MMC_MAGIC_NAME "magic" 382 #define MMC_MAGIC_OFFSET ((SZ_1M * (36 + 6)) / 512) 383 #define MMC_RANDOM_NAME "random" 384 #define MMC_RANDOM_OFFSET ((SZ_1M * (36 + 7)) / 512) 385 #define MMC_DTB_NAME "dtb" 386 #define MMC_DTB_OFFSET ((SZ_1M * (36 + 4)) / 512) 387 #define CALI_BLK_CNT 80 388 #define CALI_HS_50M_ADJUST 0 389 #define EMMC_SDIO_CLOCK_FELD 0Xffff 390 #define MMC_PM_TIMEOUT (2000) 391 #define ERROR 1 392 #define FIXED 2 393 #define RETUNING 3 394 #define DATA3_PINMUX_MASK GENMASK(15, 12) 395 396 #define TUNING_NUM_PER_POINT 40 397 #define MAX_TUNING_RETRY 4 398 #define AML_FIXED_ADJ_MAX 6 399 #define AML_FIXED_ADJ_MIN 5 400 #define AML_FIXADJ_STEP 4 401 #define ADJ_WIN_PRINT_MAXLEN 256 402 #define NO_FIXED_ADJ_MID BIT(31) 403 #define AML_MV_DLY2_NOMMC_CMD(x) ((x) << 24) 404 405 #define SD_EMMC_FIXED_ADJ_HS200 406 #define EMMC_CMD_WIN_MAX_SIZE 50 407 #define EMMC_CMD_WIN_FULL_SIZE 64 408 409 #define DBG_COMMON BIT(0) 410 #define DBG_HS200 BIT(1) 411 #define Print_dbg(dbg_level, fmt, args...) \ 412 do { \ 413 if ((dbg_level)&mmc_debug) \ 414 pr_info("[%s]" fmt, __func__, ##args); \ 415 } while (0) 416 417 /* delay_cell=70ps,1ns/delay_cell */ 418 #define DELAY_CELL_COUNTS 14 419 #endif /* __AML_SD_H__ */ 420