1 /* 2 * include/linux/amlogic/media/vout/vinfo.h 3 * 4 * Copyright (C) 2017 Amlogic, Inc. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 */ 17 18 #ifndef _VINFO_H_ 19 #define _VINFO_H_ 20 #include <linux/amlogic/media/vfm/video_common.h> 21 22 23 /* the MSB is represent vmode set by vmode_init */ 24 #define VMODE_INIT_BIT_MASK 0x8000 25 #define VMODE_MODE_BIT_MASK 0xff 26 #define VMODE_NULL_DISP_MAX 2 27 28 enum vmode_e { 29 VMODE_HDMI = 0, 30 VMODE_CVBS, 31 VMODE_LCD, 32 VMODE_NULL, /* null mode is used as temporary witch mode state */ 33 VMODE_INVALID, 34 VMODE_DUMMY_ENCP, 35 VMODE_DUMMY_ENCI, 36 VMODE_DUMMY_ENCL, 37 VMODE_MAX, 38 VMODE_INIT_NULL, 39 VMODE_MASK = 0xFF, 40 }; 41 42 enum viu_mux_e { 43 VIU_MUX_ENCL = 0, 44 VIU_MUX_ENCI, 45 VIU_MUX_ENCP, 46 VIU_MUX_MAX, 47 }; 48 49 enum vout_fr_adj_type_e { 50 VOUT_FR_ADJ_CLK = 0, 51 VOUT_FR_ADJ_HTOTAL, 52 VOUT_FR_ADJ_VTOTAL, 53 VOUT_FR_ADJ_COMBO, /* vtotal + htotal + clk */ 54 VOUT_FR_ADJ_HDMI, /* 50<->60: htotal; 60<->59.94: clk */ 55 VOUT_FR_ADJ_NONE, /* disable fr_adj */ 56 VOUT_FR_ADJ_MAX, 57 }; 58 59 enum vinfo_3d_e { 60 NON_3D = 0, 61 SS_3D, 62 FP_3D, 63 TB_3D, 64 }; 65 66 /*emp : extended metadata type*/ 67 #define VENDOR_SPECIFIC_EM_DATA 0x0 68 #define COMPRESS_VIDEO_TRAMSPORT 0x1 69 #define HDR_DYNAMIC_METADATA 0x2 70 #define VIDEO_TIMING_EXTENDED 0x3 71 72 #define SUPPORT_2020 0x01 73 74 /* master_display_info for display device */ 75 struct master_display_info_s { 76 u32 present_flag; 77 u32 features; /* feature bits bt2020/2084 */ 78 u32 primaries[3][2]; /* normalized 50000 in G,B,R order */ 79 u32 white_point[2]; /* normalized 50000 */ 80 u32 luminance[2]; /* max/min lumin, normalized 10000 */ 81 u32 max_content; /* Maximum Content Light Level */ 82 u32 max_frame_average; /* Maximum Frame-average Light Level */ 83 }; 84 /* 85 *hdr_dynamic_type 86 * 0x0001: type_1_hdr_metadata_version 87 * 0x0002: ts_103_433_spec_version 88 * 0x0003: itu_t_h265_spec_version 89 * 0x0004: type_4_hdr_metadata_version 90 */ 91 struct hdr_dynamic { 92 unsigned int type; 93 unsigned char support_flags; 94 unsigned int of_len; /*optional_fields length*/ 95 unsigned char optional_fields[28]; 96 }; 97 98 struct hdr10_plus_info { 99 uint32_t ieeeoui; 100 uint8_t length; 101 uint8_t application_version; 102 }; 103 104 struct hdr_info { 105 /* RX EDID hdr support types */ 106 u32 hdr_support; 107 unsigned char rawdata[7]; 108 /* 109 *dynamic_info[0] expresses type1's parameters certainly 110 *dynamic_info[1] expresses type2's parameters certainly 111 *dynamic_info[2] expresses type3's parameters certainly 112 *dynamic_info[3] expresses type4's parameters certainly 113 *if some types don't exist, the corresponding dynamic_info 114 *is zero instead of inexistence 115 */ 116 struct hdr_dynamic dynamic_info[4]; 117 struct hdr10_plus_info hdr10plus_info; 118 /*bit7:BT2020RGB bit6:BT2020YCC bit5:BT2020cYCC bit4:adobeRGB*/ 119 /*bit3:adobeYCC601 bit2:sYCC601 bit1:xvYCC709 bit0:xvYCC601*/ 120 u8 colorimetry_support; /* RX EDID colorimetry support types */ 121 u32 lumi_max; /* RX EDID Lumi Max value */ 122 u32 lumi_avg; /* RX EDID Lumi Avg value */ 123 u32 lumi_min; /* RX EDID Lumi Min value */ 124 }; 125 struct hdr10plus_para { 126 uint8_t application_version; 127 uint8_t targeted_max_lum; 128 uint8_t average_maxrgb; 129 uint8_t distribution_values[9]; 130 uint8_t num_bezier_curve_anchors; 131 uint32_t knee_point_x; 132 uint32_t knee_point_y; 133 uint8_t bezier_curve_anchors[9]; 134 uint8_t graphics_overlay_flag; 135 uint8_t no_delay_flag; 136 }; 137 138 enum eotf_type { 139 EOTF_T_NULL = 0, 140 EOTF_T_DOLBYVISION, 141 EOTF_T_HDR10, 142 EOTF_T_SDR, 143 EOTF_T_LL_MODE, 144 EOTF_T_MAX, 145 }; 146 147 enum mode_type { 148 YUV422_BIT12 = 0, 149 RGB_8BIT, 150 RGB_10_12BIT, 151 YUV444_10_12BIT, 152 }; 153 154 #define DV_IEEE_OUI 0x00D046 155 #define HDR10_PLUS_IEEE_OUI 0x90848B 156 #define HDR10_PLUS_DISABLE_VSIF 0 157 #define HDR10_PLUS_ENABLE_VSIF 1 158 #define HDR10_PLUS_ZERO_VSIF 2 159 160 161 /* Dolby Version VSIF parameter*/ 162 struct dv_vsif_para { 163 uint8_t ver; /* 0 or 1 or 2*/ 164 uint8_t length;/*ver1: 15 or 12*/ 165 uint8_t ver2_l11_flag; 166 union { 167 struct { 168 uint8_t low_latency:1; 169 uint8_t dobly_vision_signal:1; 170 uint8_t backlt_ctrl_MD_present:1; 171 uint8_t auxiliary_MD_present:1; 172 uint8_t eff_tmax_PQ_hi; 173 uint8_t eff_tmax_PQ_low; 174 uint8_t auxiliary_runmode; 175 uint8_t auxiliary_runversion; 176 uint8_t auxiliary_debug0; 177 } ver2; 178 struct { 179 uint8_t low_latency:1; 180 uint8_t dobly_vision_signal:1; 181 uint8_t backlt_ctrl_MD_present:1; 182 uint8_t auxiliary_MD_present:1; 183 uint8_t eff_tmax_PQ_hi; 184 uint8_t eff_tmax_PQ_low; 185 uint8_t auxiliary_runmode; 186 uint8_t auxiliary_runversion; 187 uint8_t auxiliary_debug0; 188 uint8_t content_type; 189 uint8_t content_sub_type; 190 uint8_t crf; 191 uint8_t intended_white_point; 192 uint8_t l11_byte2; 193 uint8_t l11_byte3; 194 } ver2_l11; 195 } vers; 196 }; 197 198 struct vsif_debug_save { 199 enum eotf_type type; 200 enum mode_type tunnel_mode; 201 struct dv_vsif_para data; 202 bool signal_sdr; 203 }; 204 205 struct emp_debug_save { 206 unsigned char data[128]; 207 unsigned int type; 208 unsigned int size; 209 }; 210 211 /* Dolby Version support information from EDID*/ 212 /* Refer to DV Spec version2.9 page26 to page39*/ 213 enum block_type { 214 ERROR_NULL = 0, 215 ERROR_LENGTH, 216 ERROR_OUI, 217 ERROR_VER, 218 CORRECT, 219 }; 220 221 struct dv_info { 222 unsigned char rawdata[27]; 223 enum block_type block_flag; 224 uint32_t ieeeoui; 225 uint8_t ver; /* 0 or 1 or 2*/ 226 uint8_t length;/*ver1: 15 or 12*/ 227 228 uint8_t sup_yuv422_12bit:1; 229 /* if as 0, then support RGB tunnel mode */ 230 uint8_t sup_2160p60hz:1; 231 /* if as 0, then support 2160p30hz */ 232 uint8_t sup_global_dimming:1; 233 uint8_t dv_emp_cap:1; 234 uint16_t Rx; 235 uint16_t Ry; 236 uint16_t Gx; 237 uint16_t Gy; 238 uint16_t Bx; 239 uint16_t By; 240 uint16_t Wx; 241 uint16_t Wy; 242 uint16_t tminPQ; 243 uint16_t tmaxPQ; 244 uint8_t dm_major_ver; 245 uint8_t dm_minor_ver; 246 uint8_t dm_version; 247 uint8_t tmaxLUM; 248 uint8_t colorimetry:1;/* ver1*/ 249 uint8_t tminLUM; 250 uint8_t low_latency;/* ver1_12 and 2*/ 251 uint8_t sup_backlight_control:1;/*only ver2*/ 252 uint8_t backlt_min_luma;/*only ver2*/ 253 uint8_t Interface;/*only ver2*/ 254 uint8_t sup_10b_12b_444;/*only ver2*/ 255 }; 256 257 struct vout_device_s { 258 const struct dv_info *dv_info; 259 void (*fresh_tx_hdr_pkt)(struct master_display_info_s *data); 260 void (*fresh_tx_vsif_pkt)(enum eotf_type type, 261 enum mode_type tunnel_mode, struct dv_vsif_para *data, 262 bool signal_sdr); 263 void (*fresh_tx_hdr10plus_pkt)(unsigned int flag, 264 struct hdr10plus_para *data); 265 void (*fresh_tx_emp_pkt)(unsigned char *data, unsigned int type, 266 unsigned int size); 267 }; 268 269 extern int send_dv_emp(enum eotf_type type, 270 enum mode_type tunnel_mode, 271 struct dv_vsif_para *vsif_data, 272 unsigned char *p_vsem, 273 int vsem_len, 274 bool signal_sdr); 275 276 struct vinfo_base_s { 277 enum vmode_e mode; 278 u32 width; 279 u32 height; 280 u32 field_height; 281 u32 aspect_ratio_num; 282 u32 aspect_ratio_den; 283 u32 sync_duration_num; 284 u32 sync_duration_den; 285 u32 screen_real_width; 286 u32 screen_real_height; 287 u32 video_clk; 288 enum color_fmt_e viu_color_fmt; 289 }; 290 291 #define LATENCY_INVALID_UNKNOWN 0 292 #define LATENCY_NOT_SUPPORT 0xffff 293 struct rx_av_latency { 294 unsigned int vLatency; 295 unsigned int aLatency; 296 unsigned int i_vLatency; 297 unsigned int i_aLatency; 298 }; 299 300 struct vinfo_s { 301 char *name; 302 enum vmode_e mode; 303 char ext_name[32]; 304 u32 width; 305 u32 height; 306 u32 field_height; 307 u32 aspect_ratio_num; 308 u32 aspect_ratio_den; 309 u32 screen_real_width; 310 u32 screen_real_height; 311 u32 sync_duration_num; 312 u32 sync_duration_den; 313 u32 video_clk; 314 u32 htotal; 315 u32 vtotal; 316 unsigned char hdmichecksum[10]; 317 enum vinfo_3d_e info_3d; 318 enum vout_fr_adj_type_e fr_adj_type; 319 enum color_fmt_e viu_color_fmt; 320 enum viu_mux_e viu_mux; 321 struct master_display_info_s master_display_info; 322 struct hdr_info hdr_info; 323 struct rx_av_latency rx_latency; 324 struct vout_device_s *vout_device; 325 }; 326 327 #ifdef CONFIG_AMLOGIC_MEDIA_FB 328 struct disp_rect_s { 329 int x; 330 int y; 331 int w; 332 int h; 333 }; 334 #endif 335 #endif /* _VINFO_H_ */ 336