• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1/*
2 * Copyright (C) 2022 Beken Corporation
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 *     http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 */
15
16
17#include "core_v5.h"
18
19#define MTIMER                     (0xE6000000)
20#define MTIMERCMP                  (0xE6000008)
21
22.global  arch_disable_irq
23.global  arch_enable_irq
24.global  arch_int_lock
25.global  arch_int_unlock
26.global  arch_int_restore
27.global  arch_fence
28.global  arch_atomic_clear
29.global  arch_atomic_set
30
31.global  riscv_get_mtimer
32.global  riscv_set_mtimercmp
33.global  riscv_get_cycle
34.global  riscv_get_instruct_cnt
35.global  arch_get_int_status
36
37//.section .text
38.section .itcm_sec_code, "ax"
39
40/*
41 * void arch_disable_irq(void);
42 */
43arch_disable_irq:
44    li      t0, (MSTATUS_MPIE | MSTATUS_MIE) // mpie | mie
45    csrrc   x0, mstatus, t0
46    ret
47
48/*
49 * void arch_enable_irq(void);
50 */
51arch_enable_irq:
52    csrsi  mstatus, MSTATUS_MIE
53    ret
54
55/*
56 * u32 arch_int_lock(void);
57 */
58arch_int_lock:
59    csrr    a0, mstatus           // return value
60    csrci    mstatus, MSTATUS_MIE
61    ret
62
63/*
64 * u32 arch_int_unlock(void);
65 */
66arch_int_unlock:
67    csrr    a0, mstatus           // return value
68    csrsi  mstatus, MSTATUS_MIE
69    ret
70
71/*
72 * void arch_int_restore(u32 int_flag);
73 */
74arch_int_restore:
75    csrw mstatus, a0
76    ret
77
78/*
79 * u32 arch_get_int_status(void);
80 */
81arch_get_int_status:
82    csrr    a0, mip           // return value
83    ret
84
85
86/*
87 * void arch_fence(void);
88 */
89arch_fence:
90    fence iorw, iorw
91    ret
92
93#if 0
94/*
95 * void arch_atomic_clear(u32 * lock_addr);
96 */
97arch_atomic_clear:
98    amoswap.w.rl x0, x0, (a0)
99    ret
100
101/*
102 * u32 arch_atomic_set(u32 * lock_addr);
103 */
104arch_atomic_set:
105    addi t0, x0, 1
106//swap_again:
107    amoswap.w.aq t0, t0, (a0)
108    c.mv  a0, t0
109//    bnez t0, swap_again
110    ret
111
112#endif
113
114/*
115 * u64 riscv_get_mtimer(void);
116 */
117riscv_get_mtimer:
118    li t0, MTIMER
119read_mtimer:
120    lw a1, 4(t0)
121    lw a0, 0(t0)
122    lw t1, 4(t0)
123    bne a1, t1, read_mtimer
124    ret
125
126/*
127 * void riscv_set_mtimercmp(u64 new_time);
128 */
129riscv_set_mtimercmp:
130    li t0, MTIMERCMP
131    li t1, -1
132    sw t1, 4(t0)
133    fence
134    sw a0, 0(t0)
135    sw a1, 4(t0)
136    ret
137
138/*
139 * u64 riscv_get_cycle(void);
140 */
141riscv_get_cycle:
142read_cycle:
143    csrrs a1, mcycleh, x0
144    csrrs a0, mcycle, x0
145    csrrs t0, mcycleh, x0
146    bne a1, t0, read_cycle
147    ret
148
149/*
150 * u64 riscv_get_instruct_cnt(void);
151 */
152riscv_get_instruct_cnt:
153read_instr_cnt:
154    csrrs a1, minstreth, x0
155    csrrs a0, minstret, x0
156    csrrs t0, minstreth, x0
157    bne a1, t0, read_instr_cnt
158    ret
159
160