1 // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _SOC_LEDC_REG_H_ 15 #define _SOC_LEDC_REG_H_ 16 17 18 #include "soc.h" 19 #define LEDC_HSCH0_CONF0_REG (DR_REG_LEDC_BASE + 0x0000) 20 /* LEDC_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ 21 /*description: This bit is clock gating control signal. when software config 22 LED_PWM internal registers it controls the register clock.*/ 23 #define LEDC_CLK_EN (BIT(31)) 24 #define LEDC_CLK_EN_M (BIT(31)) 25 #define LEDC_CLK_EN_V 0x1 26 #define LEDC_CLK_EN_S 31 27 /* LEDC_IDLE_LV_HSCH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */ 28 /*description: This bit is used to control the output value when high speed channel0 is off.*/ 29 #define LEDC_IDLE_LV_HSCH0 (BIT(3)) 30 #define LEDC_IDLE_LV_HSCH0_M (BIT(3)) 31 #define LEDC_IDLE_LV_HSCH0_V 0x1 32 #define LEDC_IDLE_LV_HSCH0_S 3 33 /* LEDC_SIG_OUT_EN_HSCH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */ 34 /*description: This is the output enable control bit for high speed channel0*/ 35 #define LEDC_SIG_OUT_EN_HSCH0 (BIT(2)) 36 #define LEDC_SIG_OUT_EN_HSCH0_M (BIT(2)) 37 #define LEDC_SIG_OUT_EN_HSCH0_V 0x1 38 #define LEDC_SIG_OUT_EN_HSCH0_S 2 39 /* LEDC_TIMER_SEL_HSCH0 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ 40 /*description: There are four high speed timers the two bits are used to select 41 one of them for high speed channel0. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ 42 #define LEDC_TIMER_SEL_HSCH0 0x00000003 43 #define LEDC_TIMER_SEL_HSCH0_M ((LEDC_TIMER_SEL_HSCH0_V)<<(LEDC_TIMER_SEL_HSCH0_S)) 44 #define LEDC_TIMER_SEL_HSCH0_V 0x3 45 #define LEDC_TIMER_SEL_HSCH0_S 0 46 47 #define LEDC_HSCH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x0004) 48 /* LEDC_HPOINT_HSCH0 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ 49 /*description: The output value changes to high when htimerx(x=[0 3]) selected 50 by high speed channel0 has reached reg_hpoint_hsch0[19:0]*/ 51 #define LEDC_HPOINT_HSCH0 0x000FFFFF 52 #define LEDC_HPOINT_HSCH0_M ((LEDC_HPOINT_HSCH0_V)<<(LEDC_HPOINT_HSCH0_S)) 53 #define LEDC_HPOINT_HSCH0_V 0xFFFFF 54 #define LEDC_HPOINT_HSCH0_S 0 55 56 #define LEDC_HSCH0_DUTY_REG (DR_REG_LEDC_BASE + 0x0008) 57 /* LEDC_DUTY_HSCH0 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ 58 /*description: The register is used to control output duty. When hstimerx(x=[0 59 3]) choosed by high speed channel0 has reached reg_lpoint_hsch0 the output signal changes to low. reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4]) (1) reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ 60 #define LEDC_DUTY_HSCH0 0x01FFFFFF 61 #define LEDC_DUTY_HSCH0_M ((LEDC_DUTY_HSCH0_V)<<(LEDC_DUTY_HSCH0_S)) 62 #define LEDC_DUTY_HSCH0_V 0x1FFFFFF 63 #define LEDC_DUTY_HSCH0_S 0 64 65 #define LEDC_HSCH0_CONF1_REG (DR_REG_LEDC_BASE + 0x000C) 66 /* LEDC_DUTY_START_HSCH0 : R/W ;bitpos:[31] ;default: 1'b0 ; */ 67 /*description: When reg_duty_num_hsch0 reg_duty_cycle_hsch0 and reg_duty_scale_hsch0 68 has been configured. these register won't take effect until set reg_duty_start_hsch0. this bit is automatically cleared by hardware.*/ 69 #define LEDC_DUTY_START_HSCH0 (BIT(31)) 70 #define LEDC_DUTY_START_HSCH0_M (BIT(31)) 71 #define LEDC_DUTY_START_HSCH0_V 0x1 72 #define LEDC_DUTY_START_HSCH0_S 31 73 /* LEDC_DUTY_INC_HSCH0 : R/W ;bitpos:[30] ;default: 1'b1 ; */ 74 /*description: This register is used to increase the duty of output signal or 75 decrease the duty of output signal for high speed channel0.*/ 76 #define LEDC_DUTY_INC_HSCH0 (BIT(30)) 77 #define LEDC_DUTY_INC_HSCH0_M (BIT(30)) 78 #define LEDC_DUTY_INC_HSCH0_V 0x1 79 #define LEDC_DUTY_INC_HSCH0_S 30 80 /* LEDC_DUTY_NUM_HSCH0 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ 81 /*description: This register is used to control the num of increased or decreased 82 times for high speed channel0.*/ 83 #define LEDC_DUTY_NUM_HSCH0 0x000003FF 84 #define LEDC_DUTY_NUM_HSCH0_M ((LEDC_DUTY_NUM_HSCH0_V)<<(LEDC_DUTY_NUM_HSCH0_S)) 85 #define LEDC_DUTY_NUM_HSCH0_V 0x3FF 86 #define LEDC_DUTY_NUM_HSCH0_S 20 87 /* LEDC_DUTY_CYCLE_HSCH0 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ 88 /*description: This register is used to increase or decrease the duty every 89 reg_duty_cycle_hsch0 cycles for high speed channel0.*/ 90 #define LEDC_DUTY_CYCLE_HSCH0 0x000003FF 91 #define LEDC_DUTY_CYCLE_HSCH0_M ((LEDC_DUTY_CYCLE_HSCH0_V)<<(LEDC_DUTY_CYCLE_HSCH0_S)) 92 #define LEDC_DUTY_CYCLE_HSCH0_V 0x3FF 93 #define LEDC_DUTY_CYCLE_HSCH0_S 10 94 /* LEDC_DUTY_SCALE_HSCH0 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ 95 /*description: This register controls the increase or decrease step scale for 96 high speed channel0.*/ 97 #define LEDC_DUTY_SCALE_HSCH0 0x000003FF 98 #define LEDC_DUTY_SCALE_HSCH0_M ((LEDC_DUTY_SCALE_HSCH0_V)<<(LEDC_DUTY_SCALE_HSCH0_S)) 99 #define LEDC_DUTY_SCALE_HSCH0_V 0x3FF 100 #define LEDC_DUTY_SCALE_HSCH0_S 0 101 102 #define LEDC_HSCH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0010) 103 /* LEDC_DUTY_HSCH0 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ 104 /*description: This register represents the current duty of the output signal 105 for high speed channel0.*/ 106 #define LEDC_DUTY_HSCH0 0x01FFFFFF 107 #define LEDC_DUTY_HSCH0_M ((LEDC_DUTY_HSCH0_V)<<(LEDC_DUTY_HSCH0_S)) 108 #define LEDC_DUTY_HSCH0_V 0x1FFFFFF 109 #define LEDC_DUTY_HSCH0_S 0 110 111 #define LEDC_HSCH1_CONF0_REG (DR_REG_LEDC_BASE + 0x0014) 112 /* LEDC_IDLE_LV_HSCH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ 113 /*description: This bit is used to control the output value when high speed channel1 is off.*/ 114 #define LEDC_IDLE_LV_HSCH1 (BIT(3)) 115 #define LEDC_IDLE_LV_HSCH1_M (BIT(3)) 116 #define LEDC_IDLE_LV_HSCH1_V 0x1 117 #define LEDC_IDLE_LV_HSCH1_S 3 118 /* LEDC_SIG_OUT_EN_HSCH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */ 119 /*description: This is the output enable control bit for high speed channel1*/ 120 #define LEDC_SIG_OUT_EN_HSCH1 (BIT(2)) 121 #define LEDC_SIG_OUT_EN_HSCH1_M (BIT(2)) 122 #define LEDC_SIG_OUT_EN_HSCH1_V 0x1 123 #define LEDC_SIG_OUT_EN_HSCH1_S 2 124 /* LEDC_TIMER_SEL_HSCH1 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ 125 /*description: There are four high speed timers the two bits are used to select 126 one of them for high speed channel1. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ 127 #define LEDC_TIMER_SEL_HSCH1 0x00000003 128 #define LEDC_TIMER_SEL_HSCH1_M ((LEDC_TIMER_SEL_HSCH1_V)<<(LEDC_TIMER_SEL_HSCH1_S)) 129 #define LEDC_TIMER_SEL_HSCH1_V 0x3 130 #define LEDC_TIMER_SEL_HSCH1_S 0 131 132 #define LEDC_HSCH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x0018) 133 /* LEDC_HPOINT_HSCH1 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ 134 /*description: The output value changes to high when htimerx(x=[0 3]) selected 135 by high speed channel1 has reached reg_hpoint_hsch1[19:0]*/ 136 #define LEDC_HPOINT_HSCH1 0x000FFFFF 137 #define LEDC_HPOINT_HSCH1_M ((LEDC_HPOINT_HSCH1_V)<<(LEDC_HPOINT_HSCH1_S)) 138 #define LEDC_HPOINT_HSCH1_V 0xFFFFF 139 #define LEDC_HPOINT_HSCH1_S 0 140 141 #define LEDC_HSCH1_DUTY_REG (DR_REG_LEDC_BASE + 0x001C) 142 /* LEDC_DUTY_HSCH1 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ 143 /*description: The register is used to control output duty. When hstimerx(x=[0 144 3]) choosed by high speed channel1 has reached reg_lpoint_hsch1 the output signal changes to low. reg_lpoint_hsch1=(reg_hpoint_hsch1[19:0]+reg_duty_hsch1[24:4]) (1) reg_lpoint_hsch1=(reg_hpoint_hsch1[19:0]+reg_duty_hsch1[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ 145 #define LEDC_DUTY_HSCH1 0x01FFFFFF 146 #define LEDC_DUTY_HSCH1_M ((LEDC_DUTY_HSCH1_V)<<(LEDC_DUTY_HSCH1_S)) 147 #define LEDC_DUTY_HSCH1_V 0x1FFFFFF 148 #define LEDC_DUTY_HSCH1_S 0 149 150 #define LEDC_HSCH1_CONF1_REG (DR_REG_LEDC_BASE + 0x0020) 151 /* LEDC_DUTY_START_HSCH1 : R/W ;bitpos:[31] ;default: 1'b0 ; */ 152 /*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 153 has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ 154 #define LEDC_DUTY_START_HSCH1 (BIT(31)) 155 #define LEDC_DUTY_START_HSCH1_M (BIT(31)) 156 #define LEDC_DUTY_START_HSCH1_V 0x1 157 #define LEDC_DUTY_START_HSCH1_S 31 158 /* LEDC_DUTY_INC_HSCH1 : R/W ;bitpos:[30] ;default: 1'b1 ; */ 159 /*description: This register is used to increase the duty of output signal or 160 decrease the duty of output signal for high speed channel1.*/ 161 #define LEDC_DUTY_INC_HSCH1 (BIT(30)) 162 #define LEDC_DUTY_INC_HSCH1_M (BIT(30)) 163 #define LEDC_DUTY_INC_HSCH1_V 0x1 164 #define LEDC_DUTY_INC_HSCH1_S 30 165 /* LEDC_DUTY_NUM_HSCH1 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ 166 /*description: This register is used to control the num of increased or decreased 167 times for high speed channel1.*/ 168 #define LEDC_DUTY_NUM_HSCH1 0x000003FF 169 #define LEDC_DUTY_NUM_HSCH1_M ((LEDC_DUTY_NUM_HSCH1_V)<<(LEDC_DUTY_NUM_HSCH1_S)) 170 #define LEDC_DUTY_NUM_HSCH1_V 0x3FF 171 #define LEDC_DUTY_NUM_HSCH1_S 20 172 /* LEDC_DUTY_CYCLE_HSCH1 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ 173 /*description: This register is used to increase or decrease the duty every 174 reg_duty_cycle_hsch1 cycles for high speed channel1.*/ 175 #define LEDC_DUTY_CYCLE_HSCH1 0x000003FF 176 #define LEDC_DUTY_CYCLE_HSCH1_M ((LEDC_DUTY_CYCLE_HSCH1_V)<<(LEDC_DUTY_CYCLE_HSCH1_S)) 177 #define LEDC_DUTY_CYCLE_HSCH1_V 0x3FF 178 #define LEDC_DUTY_CYCLE_HSCH1_S 10 179 /* LEDC_DUTY_SCALE_HSCH1 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ 180 /*description: This register controls the increase or decrease step scale for 181 high speed channel1.*/ 182 #define LEDC_DUTY_SCALE_HSCH1 0x000003FF 183 #define LEDC_DUTY_SCALE_HSCH1_M ((LEDC_DUTY_SCALE_HSCH1_V)<<(LEDC_DUTY_SCALE_HSCH1_S)) 184 #define LEDC_DUTY_SCALE_HSCH1_V 0x3FF 185 #define LEDC_DUTY_SCALE_HSCH1_S 0 186 187 #define LEDC_HSCH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0024) 188 /* LEDC_DUTY_HSCH1 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ 189 /*description: This register represents the current duty of the output signal 190 for high speed channel1.*/ 191 #define LEDC_DUTY_HSCH1 0x01FFFFFF 192 #define LEDC_DUTY_HSCH1_M ((LEDC_DUTY_HSCH1_V)<<(LEDC_DUTY_HSCH1_S)) 193 #define LEDC_DUTY_HSCH1_V 0x1FFFFFF 194 #define LEDC_DUTY_HSCH1_S 0 195 196 #define LEDC_HSCH2_CONF0_REG (DR_REG_LEDC_BASE + 0x0028) 197 /* LEDC_IDLE_LV_HSCH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */ 198 /*description: This bit is used to control the output value when high speed channel2 is off.*/ 199 #define LEDC_IDLE_LV_HSCH2 (BIT(3)) 200 #define LEDC_IDLE_LV_HSCH2_M (BIT(3)) 201 #define LEDC_IDLE_LV_HSCH2_V 0x1 202 #define LEDC_IDLE_LV_HSCH2_S 3 203 /* LEDC_SIG_OUT_EN_HSCH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */ 204 /*description: This is the output enable control bit for high speed channel2*/ 205 #define LEDC_SIG_OUT_EN_HSCH2 (BIT(2)) 206 #define LEDC_SIG_OUT_EN_HSCH2_M (BIT(2)) 207 #define LEDC_SIG_OUT_EN_HSCH2_V 0x1 208 #define LEDC_SIG_OUT_EN_HSCH2_S 2 209 /* LEDC_TIMER_SEL_HSCH2 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ 210 /*description: There are four high speed timers the two bits are used to select 211 one of them for high speed channel2. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ 212 #define LEDC_TIMER_SEL_HSCH2 0x00000003 213 #define LEDC_TIMER_SEL_HSCH2_M ((LEDC_TIMER_SEL_HSCH2_V)<<(LEDC_TIMER_SEL_HSCH2_S)) 214 #define LEDC_TIMER_SEL_HSCH2_V 0x3 215 #define LEDC_TIMER_SEL_HSCH2_S 0 216 217 #define LEDC_HSCH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x002C) 218 /* LEDC_HPOINT_HSCH2 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ 219 /*description: The output value changes to high when htimerx(x=[0 3]) selected 220 by high speed channel2 has reached reg_hpoint_hsch2[19:0]*/ 221 #define LEDC_HPOINT_HSCH2 0x000FFFFF 222 #define LEDC_HPOINT_HSCH2_M ((LEDC_HPOINT_HSCH2_V)<<(LEDC_HPOINT_HSCH2_S)) 223 #define LEDC_HPOINT_HSCH2_V 0xFFFFF 224 #define LEDC_HPOINT_HSCH2_S 0 225 226 #define LEDC_HSCH2_DUTY_REG (DR_REG_LEDC_BASE + 0x0030) 227 /* LEDC_DUTY_HSCH2 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ 228 /*description: The register is used to control output duty. When hstimerx(x=[0 229 3]) choosed by high speed channel2 has reached reg_lpoint_hsch2 the output signal changes to low. reg_lpoint_hsch2=(reg_hpoint_hsch2[19:0]+reg_duty_hsch2[24:4]) (1) reg_lpoint_hsch2=(reg_hpoint_hsch2[19:0]+reg_duty_hsch2[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ 230 #define LEDC_DUTY_HSCH2 0x01FFFFFF 231 #define LEDC_DUTY_HSCH2_M ((LEDC_DUTY_HSCH2_V)<<(LEDC_DUTY_HSCH2_S)) 232 #define LEDC_DUTY_HSCH2_V 0x1FFFFFF 233 #define LEDC_DUTY_HSCH2_S 0 234 235 #define LEDC_HSCH2_CONF1_REG (DR_REG_LEDC_BASE + 0x0034) 236 /* LEDC_DUTY_START_HSCH2 : R/W ;bitpos:[31] ;default: 1'b0 ; */ 237 /*description: When reg_duty_num_hsch2 reg_duty_cycle_hsch2 and reg_duty_scale_hsch2 238 has been configured. these register won't take effect until set reg_duty_start_hsch2. this bit is automatically cleared by hardware.*/ 239 #define LEDC_DUTY_START_HSCH2 (BIT(31)) 240 #define LEDC_DUTY_START_HSCH2_M (BIT(31)) 241 #define LEDC_DUTY_START_HSCH2_V 0x1 242 #define LEDC_DUTY_START_HSCH2_S 31 243 /* LEDC_DUTY_INC_HSCH2 : R/W ;bitpos:[30] ;default: 1'b1 ; */ 244 /*description: This register is used to increase the duty of output signal or 245 decrease the duty of output signal for high speed channel2.*/ 246 #define LEDC_DUTY_INC_HSCH2 (BIT(30)) 247 #define LEDC_DUTY_INC_HSCH2_M (BIT(30)) 248 #define LEDC_DUTY_INC_HSCH2_V 0x1 249 #define LEDC_DUTY_INC_HSCH2_S 30 250 /* LEDC_DUTY_NUM_HSCH2 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ 251 /*description: This register is used to control the num of increased or decreased 252 times for high speed channel2.*/ 253 #define LEDC_DUTY_NUM_HSCH2 0x000003FF 254 #define LEDC_DUTY_NUM_HSCH2_M ((LEDC_DUTY_NUM_HSCH2_V)<<(LEDC_DUTY_NUM_HSCH2_S)) 255 #define LEDC_DUTY_NUM_HSCH2_V 0x3FF 256 #define LEDC_DUTY_NUM_HSCH2_S 20 257 /* LEDC_DUTY_CYCLE_HSCH2 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ 258 /*description: This register is used to increase or decrease the duty every 259 reg_duty_cycle_hsch2 cycles for high speed channel2.*/ 260 #define LEDC_DUTY_CYCLE_HSCH2 0x000003FF 261 #define LEDC_DUTY_CYCLE_HSCH2_M ((LEDC_DUTY_CYCLE_HSCH2_V)<<(LEDC_DUTY_CYCLE_HSCH2_S)) 262 #define LEDC_DUTY_CYCLE_HSCH2_V 0x3FF 263 #define LEDC_DUTY_CYCLE_HSCH2_S 10 264 /* LEDC_DUTY_SCALE_HSCH2 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ 265 /*description: This register controls the increase or decrease step scale for 266 high speed channel2.*/ 267 #define LEDC_DUTY_SCALE_HSCH2 0x000003FF 268 #define LEDC_DUTY_SCALE_HSCH2_M ((LEDC_DUTY_SCALE_HSCH2_V)<<(LEDC_DUTY_SCALE_HSCH2_S)) 269 #define LEDC_DUTY_SCALE_HSCH2_V 0x3FF 270 #define LEDC_DUTY_SCALE_HSCH2_S 0 271 272 #define LEDC_HSCH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0038) 273 /* LEDC_DUTY_HSCH2 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ 274 /*description: This register represents the current duty of the output signal 275 for high speed channel2.*/ 276 #define LEDC_DUTY_HSCH2 0x01FFFFFF 277 #define LEDC_DUTY_HSCH2_M ((LEDC_DUTY_HSCH2_V)<<(LEDC_DUTY_HSCH2_S)) 278 #define LEDC_DUTY_HSCH2_V 0x1FFFFFF 279 #define LEDC_DUTY_HSCH2_S 0 280 281 #define LEDC_HSCH3_CONF0_REG (DR_REG_LEDC_BASE + 0x003C) 282 /* LEDC_IDLE_LV_HSCH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */ 283 /*description: This bit is used to control the output value when high speed channel3 is off.*/ 284 #define LEDC_IDLE_LV_HSCH3 (BIT(3)) 285 #define LEDC_IDLE_LV_HSCH3_M (BIT(3)) 286 #define LEDC_IDLE_LV_HSCH3_V 0x1 287 #define LEDC_IDLE_LV_HSCH3_S 3 288 /* LEDC_SIG_OUT_EN_HSCH3 : R/W ;bitpos:[2] ;default: 1'b0 ; */ 289 /*description: This is the output enable control bit for high speed channel3*/ 290 #define LEDC_SIG_OUT_EN_HSCH3 (BIT(2)) 291 #define LEDC_SIG_OUT_EN_HSCH3_M (BIT(2)) 292 #define LEDC_SIG_OUT_EN_HSCH3_V 0x1 293 #define LEDC_SIG_OUT_EN_HSCH3_S 2 294 /* LEDC_TIMER_SEL_HSCH3 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ 295 /*description: There are four high speed timers the two bits are used to select 296 one of them for high speed channel3. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ 297 #define LEDC_TIMER_SEL_HSCH3 0x00000003 298 #define LEDC_TIMER_SEL_HSCH3_M ((LEDC_TIMER_SEL_HSCH3_V)<<(LEDC_TIMER_SEL_HSCH3_S)) 299 #define LEDC_TIMER_SEL_HSCH3_V 0x3 300 #define LEDC_TIMER_SEL_HSCH3_S 0 301 302 #define LEDC_HSCH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x0040) 303 /* LEDC_HPOINT_HSCH3 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ 304 /*description: The output value changes to high when htimerx(x=[0 3]) selected 305 by high speed channel3 has reached reg_hpoint_hsch3[19:0]*/ 306 #define LEDC_HPOINT_HSCH3 0x000FFFFF 307 #define LEDC_HPOINT_HSCH3_M ((LEDC_HPOINT_HSCH3_V)<<(LEDC_HPOINT_HSCH3_S)) 308 #define LEDC_HPOINT_HSCH3_V 0xFFFFF 309 #define LEDC_HPOINT_HSCH3_S 0 310 311 #define LEDC_HSCH3_DUTY_REG (DR_REG_LEDC_BASE + 0x0044) 312 /* LEDC_DUTY_HSCH3 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ 313 /*description: The register is used to control output duty. When hstimerx(x=[0 314 3]) choosed by high speed channel3 has reached reg_lpoint_hsch3 the output signal changes to low. reg_lpoint_hsch3=(reg_hpoint_hsch3[19:0]+reg_duty_hsch3[24:4]) (1) reg_lpoint_hsch3=(reg_hpoint_hsch3[19:0]+reg_duty_hsch3[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ 315 #define LEDC_DUTY_HSCH3 0x01FFFFFF 316 #define LEDC_DUTY_HSCH3_M ((LEDC_DUTY_HSCH3_V)<<(LEDC_DUTY_HSCH3_S)) 317 #define LEDC_DUTY_HSCH3_V 0x1FFFFFF 318 #define LEDC_DUTY_HSCH3_S 0 319 320 #define LEDC_HSCH3_CONF1_REG (DR_REG_LEDC_BASE + 0x0048) 321 /* LEDC_DUTY_START_HSCH3 : R/W ;bitpos:[31] ;default: 1'b0 ; */ 322 /*description: When reg_duty_num_hsch3 reg_duty_cycle_hsch3 and reg_duty_scale_hsch3 323 has been configured. these register won't take effect until set reg_duty_start_hsch3. this bit is automatically cleared by hardware.*/ 324 #define LEDC_DUTY_START_HSCH3 (BIT(31)) 325 #define LEDC_DUTY_START_HSCH3_M (BIT(31)) 326 #define LEDC_DUTY_START_HSCH3_V 0x1 327 #define LEDC_DUTY_START_HSCH3_S 31 328 /* LEDC_DUTY_INC_HSCH3 : R/W ;bitpos:[30] ;default: 1'b1 ; */ 329 /*description: This register is used to increase the duty of output signal or 330 decrease the duty of output signal for high speed channel3.*/ 331 #define LEDC_DUTY_INC_HSCH3 (BIT(30)) 332 #define LEDC_DUTY_INC_HSCH3_M (BIT(30)) 333 #define LEDC_DUTY_INC_HSCH3_V 0x1 334 #define LEDC_DUTY_INC_HSCH3_S 30 335 /* LEDC_DUTY_NUM_HSCH3 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ 336 /*description: This register is used to control the num of increased or decreased 337 times for high speed channel3.*/ 338 #define LEDC_DUTY_NUM_HSCH3 0x000003FF 339 #define LEDC_DUTY_NUM_HSCH3_M ((LEDC_DUTY_NUM_HSCH3_V)<<(LEDC_DUTY_NUM_HSCH3_S)) 340 #define LEDC_DUTY_NUM_HSCH3_V 0x3FF 341 #define LEDC_DUTY_NUM_HSCH3_S 20 342 /* LEDC_DUTY_CYCLE_HSCH3 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ 343 /*description: This register is used to increase or decrease the duty every 344 reg_duty_cycle_hsch3 cycles for high speed channel3.*/ 345 #define LEDC_DUTY_CYCLE_HSCH3 0x000003FF 346 #define LEDC_DUTY_CYCLE_HSCH3_M ((LEDC_DUTY_CYCLE_HSCH3_V)<<(LEDC_DUTY_CYCLE_HSCH3_S)) 347 #define LEDC_DUTY_CYCLE_HSCH3_V 0x3FF 348 #define LEDC_DUTY_CYCLE_HSCH3_S 10 349 /* LEDC_DUTY_SCALE_HSCH3 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ 350 /*description: This register controls the increase or decrease step scale for 351 high speed channel3.*/ 352 #define LEDC_DUTY_SCALE_HSCH3 0x000003FF 353 #define LEDC_DUTY_SCALE_HSCH3_M ((LEDC_DUTY_SCALE_HSCH3_V)<<(LEDC_DUTY_SCALE_HSCH3_S)) 354 #define LEDC_DUTY_SCALE_HSCH3_V 0x3FF 355 #define LEDC_DUTY_SCALE_HSCH3_S 0 356 357 #define LEDC_HSCH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x004C) 358 /* LEDC_DUTY_HSCH3 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ 359 /*description: This register represents the current duty of the output signal 360 for high speed channel3.*/ 361 #define LEDC_DUTY_HSCH3 0x01FFFFFF 362 #define LEDC_DUTY_HSCH3_M ((LEDC_DUTY_HSCH3_V)<<(LEDC_DUTY_HSCH3_S)) 363 #define LEDC_DUTY_HSCH3_V 0x1FFFFFF 364 #define LEDC_DUTY_HSCH3_S 0 365 366 #define LEDC_HSCH4_CONF0_REG (DR_REG_LEDC_BASE + 0x0050) 367 /* LEDC_IDLE_LV_HSCH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */ 368 /*description: This bit is used to control the output value when high speed channel4 is off.*/ 369 #define LEDC_IDLE_LV_HSCH4 (BIT(3)) 370 #define LEDC_IDLE_LV_HSCH4_M (BIT(3)) 371 #define LEDC_IDLE_LV_HSCH4_V 0x1 372 #define LEDC_IDLE_LV_HSCH4_S 3 373 /* LEDC_SIG_OUT_EN_HSCH4 : R/W ;bitpos:[2] ;default: 1'b0 ; */ 374 /*description: This is the output enable control bit for high speed channel4*/ 375 #define LEDC_SIG_OUT_EN_HSCH4 (BIT(2)) 376 #define LEDC_SIG_OUT_EN_HSCH4_M (BIT(2)) 377 #define LEDC_SIG_OUT_EN_HSCH4_V 0x1 378 #define LEDC_SIG_OUT_EN_HSCH4_S 2 379 /* LEDC_TIMER_SEL_HSCH4 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ 380 /*description: There are four high speed timers the two bits are used to select 381 one of them for high speed channel4. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ 382 #define LEDC_TIMER_SEL_HSCH4 0x00000003 383 #define LEDC_TIMER_SEL_HSCH4_M ((LEDC_TIMER_SEL_HSCH4_V)<<(LEDC_TIMER_SEL_HSCH4_S)) 384 #define LEDC_TIMER_SEL_HSCH4_V 0x3 385 #define LEDC_TIMER_SEL_HSCH4_S 0 386 387 #define LEDC_HSCH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x0054) 388 /* LEDC_HPOINT_HSCH4 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ 389 /*description: The output value changes to high when htimerx(x=[0 3]) selected 390 by high speed channel4 has reached reg_hpoint_hsch4[19:0]*/ 391 #define LEDC_HPOINT_HSCH4 0x000FFFFF 392 #define LEDC_HPOINT_HSCH4_M ((LEDC_HPOINT_HSCH4_V)<<(LEDC_HPOINT_HSCH4_S)) 393 #define LEDC_HPOINT_HSCH4_V 0xFFFFF 394 #define LEDC_HPOINT_HSCH4_S 0 395 396 #define LEDC_HSCH4_DUTY_REG (DR_REG_LEDC_BASE + 0x0058) 397 /* LEDC_DUTY_HSCH4 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ 398 /*description: The register is used to control output duty. When hstimerx(x=[0 399 3]) choosed by high speed channel4 has reached reg_lpoint_hsch4 the output signal changes to low. reg_lpoint_hsch4=(reg_hpoint_hsch4[19:0]+reg_duty_hsch4[24:4]) (1) reg_lpoint_hsch4=(reg_hpoint_hsch4[19:0]+reg_duty_hsch4[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ 400 #define LEDC_DUTY_HSCH4 0x01FFFFFF 401 #define LEDC_DUTY_HSCH4_M ((LEDC_DUTY_HSCH4_V)<<(LEDC_DUTY_HSCH4_S)) 402 #define LEDC_DUTY_HSCH4_V 0x1FFFFFF 403 #define LEDC_DUTY_HSCH4_S 0 404 405 #define LEDC_HSCH4_CONF1_REG (DR_REG_LEDC_BASE + 0x005C) 406 /* LEDC_DUTY_START_HSCH4 : R/W ;bitpos:[31] ;default: 1'b0 ; */ 407 /*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 408 has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ 409 #define LEDC_DUTY_START_HSCH4 (BIT(31)) 410 #define LEDC_DUTY_START_HSCH4_M (BIT(31)) 411 #define LEDC_DUTY_START_HSCH4_V 0x1 412 #define LEDC_DUTY_START_HSCH4_S 31 413 /* LEDC_DUTY_INC_HSCH4 : R/W ;bitpos:[30] ;default: 1'b1 ; */ 414 /*description: This register is used to increase the duty of output signal or 415 decrease the duty of output signal for high speed channel4.*/ 416 #define LEDC_DUTY_INC_HSCH4 (BIT(30)) 417 #define LEDC_DUTY_INC_HSCH4_M (BIT(30)) 418 #define LEDC_DUTY_INC_HSCH4_V 0x1 419 #define LEDC_DUTY_INC_HSCH4_S 30 420 /* LEDC_DUTY_NUM_HSCH4 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ 421 /*description: This register is used to control the num of increased or decreased 422 times for high speed channel1.*/ 423 #define LEDC_DUTY_NUM_HSCH4 0x000003FF 424 #define LEDC_DUTY_NUM_HSCH4_M ((LEDC_DUTY_NUM_HSCH4_V)<<(LEDC_DUTY_NUM_HSCH4_S)) 425 #define LEDC_DUTY_NUM_HSCH4_V 0x3FF 426 #define LEDC_DUTY_NUM_HSCH4_S 20 427 /* LEDC_DUTY_CYCLE_HSCH4 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ 428 /*description: This register is used to increase or decrease the duty every 429 reg_duty_cycle_hsch4 cycles for high speed channel4.*/ 430 #define LEDC_DUTY_CYCLE_HSCH4 0x000003FF 431 #define LEDC_DUTY_CYCLE_HSCH4_M ((LEDC_DUTY_CYCLE_HSCH4_V)<<(LEDC_DUTY_CYCLE_HSCH4_S)) 432 #define LEDC_DUTY_CYCLE_HSCH4_V 0x3FF 433 #define LEDC_DUTY_CYCLE_HSCH4_S 10 434 /* LEDC_DUTY_SCALE_HSCH4 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ 435 /*description: This register controls the increase or decrease step scale for 436 high speed channel4.*/ 437 #define LEDC_DUTY_SCALE_HSCH4 0x000003FF 438 #define LEDC_DUTY_SCALE_HSCH4_M ((LEDC_DUTY_SCALE_HSCH4_V)<<(LEDC_DUTY_SCALE_HSCH4_S)) 439 #define LEDC_DUTY_SCALE_HSCH4_V 0x3FF 440 #define LEDC_DUTY_SCALE_HSCH4_S 0 441 442 #define LEDC_HSCH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0060) 443 /* LEDC_DUTY_HSCH4 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ 444 /*description: This register represents the current duty of the output signal 445 for high speed channel4.*/ 446 #define LEDC_DUTY_HSCH4 0x01FFFFFF 447 #define LEDC_DUTY_HSCH4_M ((LEDC_DUTY_HSCH4_V)<<(LEDC_DUTY_HSCH4_S)) 448 #define LEDC_DUTY_HSCH4_V 0x1FFFFFF 449 #define LEDC_DUTY_HSCH4_S 0 450 451 #define LEDC_HSCH5_CONF0_REG (DR_REG_LEDC_BASE + 0x0064) 452 /* LEDC_IDLE_LV_HSCH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */ 453 /*description: This bit is used to control the output value when high speed channel5 is off.*/ 454 #define LEDC_IDLE_LV_HSCH5 (BIT(3)) 455 #define LEDC_IDLE_LV_HSCH5_M (BIT(3)) 456 #define LEDC_IDLE_LV_HSCH5_V 0x1 457 #define LEDC_IDLE_LV_HSCH5_S 3 458 /* LEDC_SIG_OUT_EN_HSCH5 : R/W ;bitpos:[2] ;default: 1'b0 ; */ 459 /*description: This is the output enable control bit for high speed channel5.*/ 460 #define LEDC_SIG_OUT_EN_HSCH5 (BIT(2)) 461 #define LEDC_SIG_OUT_EN_HSCH5_M (BIT(2)) 462 #define LEDC_SIG_OUT_EN_HSCH5_V 0x1 463 #define LEDC_SIG_OUT_EN_HSCH5_S 2 464 /* LEDC_TIMER_SEL_HSCH5 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ 465 /*description: There are four high speed timers the two bits are used to select 466 one of them for high speed channel5. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ 467 #define LEDC_TIMER_SEL_HSCH5 0x00000003 468 #define LEDC_TIMER_SEL_HSCH5_M ((LEDC_TIMER_SEL_HSCH5_V)<<(LEDC_TIMER_SEL_HSCH5_S)) 469 #define LEDC_TIMER_SEL_HSCH5_V 0x3 470 #define LEDC_TIMER_SEL_HSCH5_S 0 471 472 #define LEDC_HSCH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x0068) 473 /* LEDC_HPOINT_HSCH5 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ 474 /*description: The output value changes to high when htimerx(x=[0 3]) selected 475 by high speed channel5 has reached reg_hpoint_hsch5[19:0]*/ 476 #define LEDC_HPOINT_HSCH5 0x000FFFFF 477 #define LEDC_HPOINT_HSCH5_M ((LEDC_HPOINT_HSCH5_V)<<(LEDC_HPOINT_HSCH5_S)) 478 #define LEDC_HPOINT_HSCH5_V 0xFFFFF 479 #define LEDC_HPOINT_HSCH5_S 0 480 481 #define LEDC_HSCH5_DUTY_REG (DR_REG_LEDC_BASE + 0x006C) 482 /* LEDC_DUTY_HSCH5 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ 483 /*description: The register is used to control output duty. When hstimerx(x=[0 484 3]) choosed by high speed channel5 has reached reg_lpoint_hsch5 the output signal changes to low. reg_lpoint_hsch5=(reg_hpoint_hsch5[19:0]+reg_duty_hsch5[24:4]) (1) reg_lpoint_hsch5=(reg_hpoint_hsch5[19:0]+reg_duty_hsch5[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ 485 #define LEDC_DUTY_HSCH5 0x01FFFFFF 486 #define LEDC_DUTY_HSCH5_M ((LEDC_DUTY_HSCH5_V)<<(LEDC_DUTY_HSCH5_S)) 487 #define LEDC_DUTY_HSCH5_V 0x1FFFFFF 488 #define LEDC_DUTY_HSCH5_S 0 489 490 #define LEDC_HSCH5_CONF1_REG (DR_REG_LEDC_BASE + 0x0070) 491 /* LEDC_DUTY_START_HSCH5 : R/W ;bitpos:[31] ;default: 1'b0 ; */ 492 /*description: When reg_duty_num_hsch5 reg_duty_cycle_hsch5 and reg_duty_scale_hsch5 493 has been configured. these register won't take effect until set reg_duty_start_hsch5. this bit is automatically cleared by hardware.*/ 494 #define LEDC_DUTY_START_HSCH5 (BIT(31)) 495 #define LEDC_DUTY_START_HSCH5_M (BIT(31)) 496 #define LEDC_DUTY_START_HSCH5_V 0x1 497 #define LEDC_DUTY_START_HSCH5_S 31 498 /* LEDC_DUTY_INC_HSCH5 : R/W ;bitpos:[30] ;default: 1'b1 ; */ 499 /*description: This register is used to increase the duty of output signal or 500 decrease the duty of output signal for high speed channel5.*/ 501 #define LEDC_DUTY_INC_HSCH5 (BIT(30)) 502 #define LEDC_DUTY_INC_HSCH5_M (BIT(30)) 503 #define LEDC_DUTY_INC_HSCH5_V 0x1 504 #define LEDC_DUTY_INC_HSCH5_S 30 505 /* LEDC_DUTY_NUM_HSCH5 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ 506 /*description: This register is used to control the num of increased or decreased 507 times for high speed channel5.*/ 508 #define LEDC_DUTY_NUM_HSCH5 0x000003FF 509 #define LEDC_DUTY_NUM_HSCH5_M ((LEDC_DUTY_NUM_HSCH5_V)<<(LEDC_DUTY_NUM_HSCH5_S)) 510 #define LEDC_DUTY_NUM_HSCH5_V 0x3FF 511 #define LEDC_DUTY_NUM_HSCH5_S 20 512 /* LEDC_DUTY_CYCLE_HSCH5 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ 513 /*description: This register is used to increase or decrease the duty every 514 reg_duty_cycle_hsch5 cycles for high speed channel5.*/ 515 #define LEDC_DUTY_CYCLE_HSCH5 0x000003FF 516 #define LEDC_DUTY_CYCLE_HSCH5_M ((LEDC_DUTY_CYCLE_HSCH5_V)<<(LEDC_DUTY_CYCLE_HSCH5_S)) 517 #define LEDC_DUTY_CYCLE_HSCH5_V 0x3FF 518 #define LEDC_DUTY_CYCLE_HSCH5_S 10 519 /* LEDC_DUTY_SCALE_HSCH5 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ 520 /*description: This register controls the increase or decrease step scale for 521 high speed channel5.*/ 522 #define LEDC_DUTY_SCALE_HSCH5 0x000003FF 523 #define LEDC_DUTY_SCALE_HSCH5_M ((LEDC_DUTY_SCALE_HSCH5_V)<<(LEDC_DUTY_SCALE_HSCH5_S)) 524 #define LEDC_DUTY_SCALE_HSCH5_V 0x3FF 525 #define LEDC_DUTY_SCALE_HSCH5_S 0 526 527 #define LEDC_HSCH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0074) 528 /* LEDC_DUTY_HSCH5 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ 529 /*description: This register represents the current duty of the output signal 530 for high speed channel5.*/ 531 #define LEDC_DUTY_HSCH5 0x01FFFFFF 532 #define LEDC_DUTY_HSCH5_M ((LEDC_DUTY_HSCH5_V)<<(LEDC_DUTY_HSCH5_S)) 533 #define LEDC_DUTY_HSCH5_V 0x1FFFFFF 534 #define LEDC_DUTY_HSCH5_S 0 535 536 #define LEDC_HSCH6_CONF0_REG (DR_REG_LEDC_BASE + 0x0078) 537 /* LEDC_IDLE_LV_HSCH6 : R/W ;bitpos:[3] ;default: 1'b0 ; */ 538 /*description: This bit is used to control the output value when high speed channel6 is off.*/ 539 #define LEDC_IDLE_LV_HSCH6 (BIT(3)) 540 #define LEDC_IDLE_LV_HSCH6_M (BIT(3)) 541 #define LEDC_IDLE_LV_HSCH6_V 0x1 542 #define LEDC_IDLE_LV_HSCH6_S 3 543 /* LEDC_SIG_OUT_EN_HSCH6 : R/W ;bitpos:[2] ;default: 1'b0 ; */ 544 /*description: This is the output enable control bit for high speed channel6*/ 545 #define LEDC_SIG_OUT_EN_HSCH6 (BIT(2)) 546 #define LEDC_SIG_OUT_EN_HSCH6_M (BIT(2)) 547 #define LEDC_SIG_OUT_EN_HSCH6_V 0x1 548 #define LEDC_SIG_OUT_EN_HSCH6_S 2 549 /* LEDC_TIMER_SEL_HSCH6 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ 550 /*description: There are four high speed timers the two bits are used to select 551 one of them for high speed channel6. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ 552 #define LEDC_TIMER_SEL_HSCH6 0x00000003 553 #define LEDC_TIMER_SEL_HSCH6_M ((LEDC_TIMER_SEL_HSCH6_V)<<(LEDC_TIMER_SEL_HSCH6_S)) 554 #define LEDC_TIMER_SEL_HSCH6_V 0x3 555 #define LEDC_TIMER_SEL_HSCH6_S 0 556 557 #define LEDC_HSCH6_HPOINT_REG (DR_REG_LEDC_BASE + 0x007C) 558 /* LEDC_HPOINT_HSCH6 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ 559 /*description: The output value changes to high when htimerx(x=[0 3]) selected 560 by high speed channel6 has reached reg_hpoint_hsch6[19:0]*/ 561 #define LEDC_HPOINT_HSCH6 0x000FFFFF 562 #define LEDC_HPOINT_HSCH6_M ((LEDC_HPOINT_HSCH6_V)<<(LEDC_HPOINT_HSCH6_S)) 563 #define LEDC_HPOINT_HSCH6_V 0xFFFFF 564 #define LEDC_HPOINT_HSCH6_S 0 565 566 #define LEDC_HSCH6_DUTY_REG (DR_REG_LEDC_BASE + 0x0080) 567 /* LEDC_DUTY_HSCH6 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ 568 /*description: The register is used to control output duty. When hstimerx(x=[0 569 3]) choosed by high speed channel6 has reached reg_lpoint_hsch6 the output signal changes to low. reg_lpoint_hsch6=(reg_hpoint_hsch6[19:0]+reg_duty_hsch6[24:4]) (1) reg_lpoint_hsch6=(reg_hpoint_hsch6[19:0]+reg_duty_hsch6[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ 570 #define LEDC_DUTY_HSCH6 0x01FFFFFF 571 #define LEDC_DUTY_HSCH6_M ((LEDC_DUTY_HSCH6_V)<<(LEDC_DUTY_HSCH6_S)) 572 #define LEDC_DUTY_HSCH6_V 0x1FFFFFF 573 #define LEDC_DUTY_HSCH6_S 0 574 575 #define LEDC_HSCH6_CONF1_REG (DR_REG_LEDC_BASE + 0x0084) 576 /* LEDC_DUTY_START_HSCH6 : R/W ;bitpos:[31] ;default: 1'b0 ; */ 577 /*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 578 has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ 579 #define LEDC_DUTY_START_HSCH6 (BIT(31)) 580 #define LEDC_DUTY_START_HSCH6_M (BIT(31)) 581 #define LEDC_DUTY_START_HSCH6_V 0x1 582 #define LEDC_DUTY_START_HSCH6_S 31 583 /* LEDC_DUTY_INC_HSCH6 : R/W ;bitpos:[30] ;default: 1'b1 ; */ 584 /*description: This register is used to increase the duty of output signal or 585 decrease the duty of output signal for high speed channel6.*/ 586 #define LEDC_DUTY_INC_HSCH6 (BIT(30)) 587 #define LEDC_DUTY_INC_HSCH6_M (BIT(30)) 588 #define LEDC_DUTY_INC_HSCH6_V 0x1 589 #define LEDC_DUTY_INC_HSCH6_S 30 590 /* LEDC_DUTY_NUM_HSCH6 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ 591 /*description: This register is used to control the num of increased or decreased 592 times for high speed channel6.*/ 593 #define LEDC_DUTY_NUM_HSCH6 0x000003FF 594 #define LEDC_DUTY_NUM_HSCH6_M ((LEDC_DUTY_NUM_HSCH6_V)<<(LEDC_DUTY_NUM_HSCH6_S)) 595 #define LEDC_DUTY_NUM_HSCH6_V 0x3FF 596 #define LEDC_DUTY_NUM_HSCH6_S 20 597 /* LEDC_DUTY_CYCLE_HSCH6 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ 598 /*description: This register is used to increase or decrease the duty every 599 reg_duty_cycle_hsch6 cycles for high speed channel6.*/ 600 #define LEDC_DUTY_CYCLE_HSCH6 0x000003FF 601 #define LEDC_DUTY_CYCLE_HSCH6_M ((LEDC_DUTY_CYCLE_HSCH6_V)<<(LEDC_DUTY_CYCLE_HSCH6_S)) 602 #define LEDC_DUTY_CYCLE_HSCH6_V 0x3FF 603 #define LEDC_DUTY_CYCLE_HSCH6_S 10 604 /* LEDC_DUTY_SCALE_HSCH6 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ 605 /*description: This register controls the increase or decrease step scale for 606 high speed channel6.*/ 607 #define LEDC_DUTY_SCALE_HSCH6 0x000003FF 608 #define LEDC_DUTY_SCALE_HSCH6_M ((LEDC_DUTY_SCALE_HSCH6_V)<<(LEDC_DUTY_SCALE_HSCH6_S)) 609 #define LEDC_DUTY_SCALE_HSCH6_V 0x3FF 610 #define LEDC_DUTY_SCALE_HSCH6_S 0 611 612 #define LEDC_HSCH6_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0088) 613 /* LEDC_DUTY_HSCH6 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ 614 /*description: This register represents the current duty of the output signal 615 for high speed channel6.*/ 616 #define LEDC_DUTY_HSCH6 0x01FFFFFF 617 #define LEDC_DUTY_HSCH6_M ((LEDC_DUTY_HSCH6_V)<<(LEDC_DUTY_HSCH6_S)) 618 #define LEDC_DUTY_HSCH6_V 0x1FFFFFF 619 #define LEDC_DUTY_HSCH6_S 0 620 621 #define LEDC_HSCH7_CONF0_REG (DR_REG_LEDC_BASE + 0x008C) 622 /* LEDC_IDLE_LV_HSCH7 : R/W ;bitpos:[3] ;default: 1'b0 ; */ 623 /*description: This bit is used to control the output value when high speed channel7 is off.*/ 624 #define LEDC_IDLE_LV_HSCH7 (BIT(3)) 625 #define LEDC_IDLE_LV_HSCH7_M (BIT(3)) 626 #define LEDC_IDLE_LV_HSCH7_V 0x1 627 #define LEDC_IDLE_LV_HSCH7_S 3 628 /* LEDC_SIG_OUT_EN_HSCH7 : R/W ;bitpos:[2] ;default: 1'b0 ; */ 629 /*description: This is the output enable control bit for high speed channel7.*/ 630 #define LEDC_SIG_OUT_EN_HSCH7 (BIT(2)) 631 #define LEDC_SIG_OUT_EN_HSCH7_M (BIT(2)) 632 #define LEDC_SIG_OUT_EN_HSCH7_V 0x1 633 #define LEDC_SIG_OUT_EN_HSCH7_S 2 634 /* LEDC_TIMER_SEL_HSCH7 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ 635 /*description: There are four high speed timers the two bits are used to select 636 one of them for high speed channel7. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ 637 #define LEDC_TIMER_SEL_HSCH7 0x00000003 638 #define LEDC_TIMER_SEL_HSCH7_M ((LEDC_TIMER_SEL_HSCH7_V)<<(LEDC_TIMER_SEL_HSCH7_S)) 639 #define LEDC_TIMER_SEL_HSCH7_V 0x3 640 #define LEDC_TIMER_SEL_HSCH7_S 0 641 642 #define LEDC_HSCH7_HPOINT_REG (DR_REG_LEDC_BASE + 0x0090) 643 /* LEDC_HPOINT_HSCH7 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ 644 /*description: The output value changes to high when htimerx(x=[0 3]) selected 645 by high speed channel7 has reached reg_hpoint_hsch7[19:0]*/ 646 #define LEDC_HPOINT_HSCH7 0x000FFFFF 647 #define LEDC_HPOINT_HSCH7_M ((LEDC_HPOINT_HSCH7_V)<<(LEDC_HPOINT_HSCH7_S)) 648 #define LEDC_HPOINT_HSCH7_V 0xFFFFF 649 #define LEDC_HPOINT_HSCH7_S 0 650 651 #define LEDC_HSCH7_DUTY_REG (DR_REG_LEDC_BASE + 0x0094) 652 /* LEDC_DUTY_HSCH7 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ 653 /*description: The register is used to control output duty. When hstimerx(x=[0 654 3]) choosed by high speed channel7 has reached reg_lpoint_hsch7 the output signal changes to low. reg_lpoint_hsch7=(reg_hpoint_hsch7[19:0]+reg_duty_hsch7[24:4]) (1) reg_lpoint_hsch7=(reg_hpoint_hsch7[19:0]+reg_duty_hsch7[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ 655 #define LEDC_DUTY_HSCH7 0x01FFFFFF 656 #define LEDC_DUTY_HSCH7_M ((LEDC_DUTY_HSCH7_V)<<(LEDC_DUTY_HSCH7_S)) 657 #define LEDC_DUTY_HSCH7_V 0x1FFFFFF 658 #define LEDC_DUTY_HSCH7_S 0 659 660 #define LEDC_HSCH7_CONF1_REG (DR_REG_LEDC_BASE + 0x0098) 661 /* LEDC_DUTY_START_HSCH7 : R/W ;bitpos:[31] ;default: 1'b0 ; */ 662 /*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 663 has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ 664 #define LEDC_DUTY_START_HSCH7 (BIT(31)) 665 #define LEDC_DUTY_START_HSCH7_M (BIT(31)) 666 #define LEDC_DUTY_START_HSCH7_V 0x1 667 #define LEDC_DUTY_START_HSCH7_S 31 668 /* LEDC_DUTY_INC_HSCH7 : R/W ;bitpos:[30] ;default: 1'b1 ; */ 669 /*description: This register is used to increase the duty of output signal or 670 decrease the duty of output signal for high speed channel6.*/ 671 #define LEDC_DUTY_INC_HSCH7 (BIT(30)) 672 #define LEDC_DUTY_INC_HSCH7_M (BIT(30)) 673 #define LEDC_DUTY_INC_HSCH7_V 0x1 674 #define LEDC_DUTY_INC_HSCH7_S 30 675 /* LEDC_DUTY_NUM_HSCH7 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ 676 /*description: This register is used to control the num of increased or decreased 677 times for high speed channel6.*/ 678 #define LEDC_DUTY_NUM_HSCH7 0x000003FF 679 #define LEDC_DUTY_NUM_HSCH7_M ((LEDC_DUTY_NUM_HSCH7_V)<<(LEDC_DUTY_NUM_HSCH7_S)) 680 #define LEDC_DUTY_NUM_HSCH7_V 0x3FF 681 #define LEDC_DUTY_NUM_HSCH7_S 20 682 /* LEDC_DUTY_CYCLE_HSCH7 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ 683 /*description: This register is used to increase or decrease the duty every 684 reg_duty_cycle_hsch7 cycles for high speed channel7.*/ 685 #define LEDC_DUTY_CYCLE_HSCH7 0x000003FF 686 #define LEDC_DUTY_CYCLE_HSCH7_M ((LEDC_DUTY_CYCLE_HSCH7_V)<<(LEDC_DUTY_CYCLE_HSCH7_S)) 687 #define LEDC_DUTY_CYCLE_HSCH7_V 0x3FF 688 #define LEDC_DUTY_CYCLE_HSCH7_S 10 689 /* LEDC_DUTY_SCALE_HSCH7 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ 690 /*description: This register controls the increase or decrease step scale for 691 high speed channel7.*/ 692 #define LEDC_DUTY_SCALE_HSCH7 0x000003FF 693 #define LEDC_DUTY_SCALE_HSCH7_M ((LEDC_DUTY_SCALE_HSCH7_V)<<(LEDC_DUTY_SCALE_HSCH7_S)) 694 #define LEDC_DUTY_SCALE_HSCH7_V 0x3FF 695 #define LEDC_DUTY_SCALE_HSCH7_S 0 696 697 #define LEDC_HSCH7_DUTY_R_REG (DR_REG_LEDC_BASE + 0x009C) 698 /* LEDC_DUTY_HSCH7 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ 699 /*description: This register represents the current duty of the output signal 700 for high speed channel7.*/ 701 #define LEDC_DUTY_HSCH7 0x01FFFFFF 702 #define LEDC_DUTY_HSCH7_M ((LEDC_DUTY_HSCH7_V)<<(LEDC_DUTY_HSCH7_S)) 703 #define LEDC_DUTY_HSCH7_V 0x1FFFFFF 704 #define LEDC_DUTY_HSCH7_S 0 705 706 #define LEDC_LSCH0_CONF0_REG (DR_REG_LEDC_BASE + 0x00A0) 707 /* LEDC_PARA_UP_LSCH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */ 708 /*description: This bit is used to update register LEDC_LSCH0_HPOINT and LEDC_LSCH0_DUTY 709 for low speed channel0.*/ 710 #define LEDC_PARA_UP_LSCH0 (BIT(4)) 711 #define LEDC_PARA_UP_LSCH0_M (BIT(4)) 712 #define LEDC_PARA_UP_LSCH0_V 0x1 713 #define LEDC_PARA_UP_LSCH0_S 4 714 /* LEDC_IDLE_LV_LSCH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */ 715 /*description: This bit is used to control the output value when low speed channel0 is off.*/ 716 #define LEDC_IDLE_LV_LSCH0 (BIT(3)) 717 #define LEDC_IDLE_LV_LSCH0_M (BIT(3)) 718 #define LEDC_IDLE_LV_LSCH0_V 0x1 719 #define LEDC_IDLE_LV_LSCH0_S 3 720 /* LEDC_SIG_OUT_EN_LSCH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */ 721 /*description: This is the output enable control bit for low speed channel0.*/ 722 #define LEDC_SIG_OUT_EN_LSCH0 (BIT(2)) 723 #define LEDC_SIG_OUT_EN_LSCH0_M (BIT(2)) 724 #define LEDC_SIG_OUT_EN_LSCH0_V 0x1 725 #define LEDC_SIG_OUT_EN_LSCH0_S 2 726 /* LEDC_TIMER_SEL_LSCH0 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ 727 /*description: There are four low speed timers the two bits are used to select 728 one of them for low speed channel0. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ 729 #define LEDC_TIMER_SEL_LSCH0 0x00000003 730 #define LEDC_TIMER_SEL_LSCH0_M ((LEDC_TIMER_SEL_LSCH0_V)<<(LEDC_TIMER_SEL_LSCH0_S)) 731 #define LEDC_TIMER_SEL_LSCH0_V 0x3 732 #define LEDC_TIMER_SEL_LSCH0_S 0 733 734 #define LEDC_LSCH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x00A4) 735 /* LEDC_HPOINT_LSCH0 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ 736 /*description: The output value changes to high when lstimerx(x=[0 3]) selected 737 by low speed channel0 has reached reg_hpoint_lsch0[19:0]*/ 738 #define LEDC_HPOINT_LSCH0 0x000FFFFF 739 #define LEDC_HPOINT_LSCH0_M ((LEDC_HPOINT_LSCH0_V)<<(LEDC_HPOINT_LSCH0_S)) 740 #define LEDC_HPOINT_LSCH0_V 0xFFFFF 741 #define LEDC_HPOINT_LSCH0_S 0 742 743 #define LEDC_LSCH0_DUTY_REG (DR_REG_LEDC_BASE + 0x00A8) 744 /* LEDC_DUTY_LSCH0 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ 745 /*description: The register is used to control output duty. When lstimerx(x=[0 746 3]) choosed by low speed channel0 has reached reg_lpoint_lsch0 the output signal changes to low. reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4]) (1) reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ 747 #define LEDC_DUTY_LSCH0 0x01FFFFFF 748 #define LEDC_DUTY_LSCH0_M ((LEDC_DUTY_LSCH0_V)<<(LEDC_DUTY_LSCH0_S)) 749 #define LEDC_DUTY_LSCH0_V 0x1FFFFFF 750 #define LEDC_DUTY_LSCH0_S 0 751 752 #define LEDC_LSCH0_CONF1_REG (DR_REG_LEDC_BASE + 0x00AC) 753 /* LEDC_DUTY_START_LSCH0 : R/W ;bitpos:[31] ;default: 1'b0 ; */ 754 /*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 755 has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ 756 #define LEDC_DUTY_START_LSCH0 (BIT(31)) 757 #define LEDC_DUTY_START_LSCH0_M (BIT(31)) 758 #define LEDC_DUTY_START_LSCH0_V 0x1 759 #define LEDC_DUTY_START_LSCH0_S 31 760 /* LEDC_DUTY_INC_LSCH0 : R/W ;bitpos:[30] ;default: 1'b1 ; */ 761 /*description: This register is used to increase the duty of output signal or 762 decrease the duty of output signal for low speed channel6.*/ 763 #define LEDC_DUTY_INC_LSCH0 (BIT(30)) 764 #define LEDC_DUTY_INC_LSCH0_M (BIT(30)) 765 #define LEDC_DUTY_INC_LSCH0_V 0x1 766 #define LEDC_DUTY_INC_LSCH0_S 30 767 /* LEDC_DUTY_NUM_LSCH0 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ 768 /*description: This register is used to control the num of increased or decreased 769 times for low speed channel6.*/ 770 #define LEDC_DUTY_NUM_LSCH0 0x000003FF 771 #define LEDC_DUTY_NUM_LSCH0_M ((LEDC_DUTY_NUM_LSCH0_V)<<(LEDC_DUTY_NUM_LSCH0_S)) 772 #define LEDC_DUTY_NUM_LSCH0_V 0x3FF 773 #define LEDC_DUTY_NUM_LSCH0_S 20 774 /* LEDC_DUTY_CYCLE_LSCH0 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ 775 /*description: This register is used to increase or decrease the duty every 776 reg_duty_cycle_lsch0 cycles for low speed channel0.*/ 777 #define LEDC_DUTY_CYCLE_LSCH0 0x000003FF 778 #define LEDC_DUTY_CYCLE_LSCH0_M ((LEDC_DUTY_CYCLE_LSCH0_V)<<(LEDC_DUTY_CYCLE_LSCH0_S)) 779 #define LEDC_DUTY_CYCLE_LSCH0_V 0x3FF 780 #define LEDC_DUTY_CYCLE_LSCH0_S 10 781 /* LEDC_DUTY_SCALE_LSCH0 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ 782 /*description: This register controls the increase or decrease step scale for 783 low speed channel0.*/ 784 #define LEDC_DUTY_SCALE_LSCH0 0x000003FF 785 #define LEDC_DUTY_SCALE_LSCH0_M ((LEDC_DUTY_SCALE_LSCH0_V)<<(LEDC_DUTY_SCALE_LSCH0_S)) 786 #define LEDC_DUTY_SCALE_LSCH0_V 0x3FF 787 #define LEDC_DUTY_SCALE_LSCH0_S 0 788 789 #define LEDC_LSCH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00B0) 790 /* LEDC_DUTY_LSCH0 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ 791 /*description: This register represents the current duty of the output signal 792 for low speed channel0.*/ 793 #define LEDC_DUTY_LSCH0 0x01FFFFFF 794 #define LEDC_DUTY_LSCH0_M ((LEDC_DUTY_LSCH0_V)<<(LEDC_DUTY_LSCH0_S)) 795 #define LEDC_DUTY_LSCH0_V 0x1FFFFFF 796 #define LEDC_DUTY_LSCH0_S 0 797 798 #define LEDC_LSCH1_CONF0_REG (DR_REG_LEDC_BASE + 0x00B4) 799 /* LEDC_PARA_UP_LSCH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */ 800 /*description: This bit is used to update register LEDC_LSCH1_HPOINT and LEDC_LSCH1_DUTY 801 for low speed channel1.*/ 802 #define LEDC_PARA_UP_LSCH1 (BIT(4)) 803 #define LEDC_PARA_UP_LSCH1_M (BIT(4)) 804 #define LEDC_PARA_UP_LSCH1_V 0x1 805 #define LEDC_PARA_UP_LSCH1_S 4 806 /* LEDC_IDLE_LV_LSCH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ 807 /*description: This bit is used to control the output value when low speed channel1 is off.*/ 808 #define LEDC_IDLE_LV_LSCH1 (BIT(3)) 809 #define LEDC_IDLE_LV_LSCH1_M (BIT(3)) 810 #define LEDC_IDLE_LV_LSCH1_V 0x1 811 #define LEDC_IDLE_LV_LSCH1_S 3 812 /* LEDC_SIG_OUT_EN_LSCH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */ 813 /*description: This is the output enable control bit for low speed channel1.*/ 814 #define LEDC_SIG_OUT_EN_LSCH1 (BIT(2)) 815 #define LEDC_SIG_OUT_EN_LSCH1_M (BIT(2)) 816 #define LEDC_SIG_OUT_EN_LSCH1_V 0x1 817 #define LEDC_SIG_OUT_EN_LSCH1_S 2 818 /* LEDC_TIMER_SEL_LSCH1 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ 819 /*description: There are four low speed timers the two bits are used to select 820 one of them for low speed channel1. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ 821 #define LEDC_TIMER_SEL_LSCH1 0x00000003 822 #define LEDC_TIMER_SEL_LSCH1_M ((LEDC_TIMER_SEL_LSCH1_V)<<(LEDC_TIMER_SEL_LSCH1_S)) 823 #define LEDC_TIMER_SEL_LSCH1_V 0x3 824 #define LEDC_TIMER_SEL_LSCH1_S 0 825 826 #define LEDC_LSCH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x00B8) 827 /* LEDC_HPOINT_LSCH1 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ 828 /*description: The output value changes to high when lstimerx(x=[0 3]) selected 829 by low speed channel1 has reached reg_hpoint_lsch1[19:0]*/ 830 #define LEDC_HPOINT_LSCH1 0x000FFFFF 831 #define LEDC_HPOINT_LSCH1_M ((LEDC_HPOINT_LSCH1_V)<<(LEDC_HPOINT_LSCH1_S)) 832 #define LEDC_HPOINT_LSCH1_V 0xFFFFF 833 #define LEDC_HPOINT_LSCH1_S 0 834 835 #define LEDC_LSCH1_DUTY_REG (DR_REG_LEDC_BASE + 0x00BC) 836 /* LEDC_DUTY_LSCH1 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ 837 /*description: The register is used to control output duty. When lstimerx(x=[0 838 3]) choosed by low speed channel1 has reached reg_lpoint_lsch1 the output signal changes to low. reg_lpoint_lsch1=(reg_hpoint_lsch1[19:0]+reg_duty_lsch1[24:4]) (1) reg_lpoint_lsch1=(reg_hpoint_lsch1[19:0]+reg_duty_lsch1[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ 839 #define LEDC_DUTY_LSCH1 0x01FFFFFF 840 #define LEDC_DUTY_LSCH1_M ((LEDC_DUTY_LSCH1_V)<<(LEDC_DUTY_LSCH1_S)) 841 #define LEDC_DUTY_LSCH1_V 0x1FFFFFF 842 #define LEDC_DUTY_LSCH1_S 0 843 844 #define LEDC_LSCH1_CONF1_REG (DR_REG_LEDC_BASE + 0x00C0) 845 /* LEDC_DUTY_START_LSCH1 : R/W ;bitpos:[31] ;default: 1'b0 ; */ 846 /*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 847 has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ 848 #define LEDC_DUTY_START_LSCH1 (BIT(31)) 849 #define LEDC_DUTY_START_LSCH1_M (BIT(31)) 850 #define LEDC_DUTY_START_LSCH1_V 0x1 851 #define LEDC_DUTY_START_LSCH1_S 31 852 /* LEDC_DUTY_INC_LSCH1 : R/W ;bitpos:[30] ;default: 1'b1 ; */ 853 /*description: This register is used to increase the duty of output signal or 854 decrease the duty of output signal for low speed channel1.*/ 855 #define LEDC_DUTY_INC_LSCH1 (BIT(30)) 856 #define LEDC_DUTY_INC_LSCH1_M (BIT(30)) 857 #define LEDC_DUTY_INC_LSCH1_V 0x1 858 #define LEDC_DUTY_INC_LSCH1_S 30 859 /* LEDC_DUTY_NUM_LSCH1 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ 860 /*description: This register is used to control the num of increased or decreased 861 times for low speed channel1.*/ 862 #define LEDC_DUTY_NUM_LSCH1 0x000003FF 863 #define LEDC_DUTY_NUM_LSCH1_M ((LEDC_DUTY_NUM_LSCH1_V)<<(LEDC_DUTY_NUM_LSCH1_S)) 864 #define LEDC_DUTY_NUM_LSCH1_V 0x3FF 865 #define LEDC_DUTY_NUM_LSCH1_S 20 866 /* LEDC_DUTY_CYCLE_LSCH1 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ 867 /*description: This register is used to increase or decrease the duty every 868 reg_duty_cycle_lsch1 cycles for low speed channel1.*/ 869 #define LEDC_DUTY_CYCLE_LSCH1 0x000003FF 870 #define LEDC_DUTY_CYCLE_LSCH1_M ((LEDC_DUTY_CYCLE_LSCH1_V)<<(LEDC_DUTY_CYCLE_LSCH1_S)) 871 #define LEDC_DUTY_CYCLE_LSCH1_V 0x3FF 872 #define LEDC_DUTY_CYCLE_LSCH1_S 10 873 /* LEDC_DUTY_SCALE_LSCH1 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ 874 /*description: This register controls the increase or decrease step scale for 875 low speed channel1.*/ 876 #define LEDC_DUTY_SCALE_LSCH1 0x000003FF 877 #define LEDC_DUTY_SCALE_LSCH1_M ((LEDC_DUTY_SCALE_LSCH1_V)<<(LEDC_DUTY_SCALE_LSCH1_S)) 878 #define LEDC_DUTY_SCALE_LSCH1_V 0x3FF 879 #define LEDC_DUTY_SCALE_LSCH1_S 0 880 881 #define LEDC_LSCH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00C4) 882 /* LEDC_DUTY_LSCH1 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ 883 /*description: This register represents the current duty of the output signal 884 for low speed channel1.*/ 885 #define LEDC_DUTY_LSCH1 0x01FFFFFF 886 #define LEDC_DUTY_LSCH1_M ((LEDC_DUTY_LSCH1_V)<<(LEDC_DUTY_LSCH1_S)) 887 #define LEDC_DUTY_LSCH1_V 0x1FFFFFF 888 #define LEDC_DUTY_LSCH1_S 0 889 890 #define LEDC_LSCH2_CONF0_REG (DR_REG_LEDC_BASE + 0x00C8) 891 /* LEDC_PARA_UP_LSCH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */ 892 /*description: This bit is used to update register LEDC_LSCH2_HPOINT and LEDC_LSCH2_DUTY 893 for low speed channel2.*/ 894 #define LEDC_PARA_UP_LSCH2 (BIT(4)) 895 #define LEDC_PARA_UP_LSCH2_M (BIT(4)) 896 #define LEDC_PARA_UP_LSCH2_V 0x1 897 #define LEDC_PARA_UP_LSCH2_S 4 898 /* LEDC_IDLE_LV_LSCH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */ 899 /*description: This bit is used to control the output value when low speed channel2 is off.*/ 900 #define LEDC_IDLE_LV_LSCH2 (BIT(3)) 901 #define LEDC_IDLE_LV_LSCH2_M (BIT(3)) 902 #define LEDC_IDLE_LV_LSCH2_V 0x1 903 #define LEDC_IDLE_LV_LSCH2_S 3 904 /* LEDC_SIG_OUT_EN_LSCH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */ 905 /*description: This is the output enable control bit for low speed channel2.*/ 906 #define LEDC_SIG_OUT_EN_LSCH2 (BIT(2)) 907 #define LEDC_SIG_OUT_EN_LSCH2_M (BIT(2)) 908 #define LEDC_SIG_OUT_EN_LSCH2_V 0x1 909 #define LEDC_SIG_OUT_EN_LSCH2_S 2 910 /* LEDC_TIMER_SEL_LSCH2 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ 911 /*description: There are four low speed timers the two bits are used to select 912 one of them for low speed channel2. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ 913 #define LEDC_TIMER_SEL_LSCH2 0x00000003 914 #define LEDC_TIMER_SEL_LSCH2_M ((LEDC_TIMER_SEL_LSCH2_V)<<(LEDC_TIMER_SEL_LSCH2_S)) 915 #define LEDC_TIMER_SEL_LSCH2_V 0x3 916 #define LEDC_TIMER_SEL_LSCH2_S 0 917 918 #define LEDC_LSCH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x00CC) 919 /* LEDC_HPOINT_LSCH2 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ 920 /*description: The output value changes to high when lstimerx(x=[0 3]) selected 921 by low speed channel2 has reached reg_hpoint_lsch2[19:0]*/ 922 #define LEDC_HPOINT_LSCH2 0x000FFFFF 923 #define LEDC_HPOINT_LSCH2_M ((LEDC_HPOINT_LSCH2_V)<<(LEDC_HPOINT_LSCH2_S)) 924 #define LEDC_HPOINT_LSCH2_V 0xFFFFF 925 #define LEDC_HPOINT_LSCH2_S 0 926 927 #define LEDC_LSCH2_DUTY_REG (DR_REG_LEDC_BASE + 0x00D0) 928 /* LEDC_DUTY_LSCH2 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ 929 /*description: The register is used to control output duty. When lstimerx(x=[0 930 3]) choosed by low speed channel2 has reached reg_lpoint_lsch2 the output signal changes to low. reg_lpoint_lsch2=(reg_hpoint_lsch2[19:0]+reg_duty_lsch2[24:4]) (1) reg_lpoint_lsch2=(reg_hpoint_lsch2[19:0]+reg_duty_lsch2[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ 931 #define LEDC_DUTY_LSCH2 0x01FFFFFF 932 #define LEDC_DUTY_LSCH2_M ((LEDC_DUTY_LSCH2_V)<<(LEDC_DUTY_LSCH2_S)) 933 #define LEDC_DUTY_LSCH2_V 0x1FFFFFF 934 #define LEDC_DUTY_LSCH2_S 0 935 936 #define LEDC_LSCH2_CONF1_REG (DR_REG_LEDC_BASE + 0x00D4) 937 /* LEDC_DUTY_START_LSCH2 : R/W ;bitpos:[31] ;default: 1'b0 ; */ 938 /*description: When reg_duty_num_hsch2 reg_duty_cycle_hsch2 and reg_duty_scale_hsch2 939 has been configured. these register won't take effect until set reg_duty_start_hsch2. this bit is automatically cleared by hardware.*/ 940 #define LEDC_DUTY_START_LSCH2 (BIT(31)) 941 #define LEDC_DUTY_START_LSCH2_M (BIT(31)) 942 #define LEDC_DUTY_START_LSCH2_V 0x1 943 #define LEDC_DUTY_START_LSCH2_S 31 944 /* LEDC_DUTY_INC_LSCH2 : R/W ;bitpos:[30] ;default: 1'b1 ; */ 945 /*description: This register is used to increase the duty of output signal or 946 decrease the duty of output signal for low speed channel2.*/ 947 #define LEDC_DUTY_INC_LSCH2 (BIT(30)) 948 #define LEDC_DUTY_INC_LSCH2_M (BIT(30)) 949 #define LEDC_DUTY_INC_LSCH2_V 0x1 950 #define LEDC_DUTY_INC_LSCH2_S 30 951 /* LEDC_DUTY_NUM_LSCH2 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ 952 /*description: This register is used to control the num of increased or decreased 953 times for low speed channel2.*/ 954 #define LEDC_DUTY_NUM_LSCH2 0x000003FF 955 #define LEDC_DUTY_NUM_LSCH2_M ((LEDC_DUTY_NUM_LSCH2_V)<<(LEDC_DUTY_NUM_LSCH2_S)) 956 #define LEDC_DUTY_NUM_LSCH2_V 0x3FF 957 #define LEDC_DUTY_NUM_LSCH2_S 20 958 /* LEDC_DUTY_CYCLE_LSCH2 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ 959 /*description: This register is used to increase or decrease the duty every 960 reg_duty_cycle_lsch2 cycles for low speed channel2.*/ 961 #define LEDC_DUTY_CYCLE_LSCH2 0x000003FF 962 #define LEDC_DUTY_CYCLE_LSCH2_M ((LEDC_DUTY_CYCLE_LSCH2_V)<<(LEDC_DUTY_CYCLE_LSCH2_S)) 963 #define LEDC_DUTY_CYCLE_LSCH2_V 0x3FF 964 #define LEDC_DUTY_CYCLE_LSCH2_S 10 965 /* LEDC_DUTY_SCALE_LSCH2 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ 966 /*description: This register controls the increase or decrease step scale for 967 low speed channel2.*/ 968 #define LEDC_DUTY_SCALE_LSCH2 0x000003FF 969 #define LEDC_DUTY_SCALE_LSCH2_M ((LEDC_DUTY_SCALE_LSCH2_V)<<(LEDC_DUTY_SCALE_LSCH2_S)) 970 #define LEDC_DUTY_SCALE_LSCH2_V 0x3FF 971 #define LEDC_DUTY_SCALE_LSCH2_S 0 972 973 #define LEDC_LSCH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00D8) 974 /* LEDC_DUTY_LSCH2 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ 975 /*description: This register represents the current duty of the output signal 976 for low speed channel2.*/ 977 #define LEDC_DUTY_LSCH2 0x01FFFFFF 978 #define LEDC_DUTY_LSCH2_M ((LEDC_DUTY_LSCH2_V)<<(LEDC_DUTY_LSCH2_S)) 979 #define LEDC_DUTY_LSCH2_V 0x1FFFFFF 980 #define LEDC_DUTY_LSCH2_S 0 981 982 #define LEDC_LSCH3_CONF0_REG (DR_REG_LEDC_BASE + 0x00DC) 983 /* LEDC_PARA_UP_LSCH3 : R/W ;bitpos:[4] ;default: 1'b0 ; */ 984 /*description: This bit is used to update register LEDC_LSCH3_HPOINT and LEDC_LSCH3_DUTY 985 for low speed channel3.*/ 986 #define LEDC_PARA_UP_LSCH3 (BIT(4)) 987 #define LEDC_PARA_UP_LSCH3_M (BIT(4)) 988 #define LEDC_PARA_UP_LSCH3_V 0x1 989 #define LEDC_PARA_UP_LSCH3_S 4 990 /* LEDC_IDLE_LV_LSCH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */ 991 /*description: This bit is used to control the output value when low speed channel3 is off.*/ 992 #define LEDC_IDLE_LV_LSCH3 (BIT(3)) 993 #define LEDC_IDLE_LV_LSCH3_M (BIT(3)) 994 #define LEDC_IDLE_LV_LSCH3_V 0x1 995 #define LEDC_IDLE_LV_LSCH3_S 3 996 /* LEDC_SIG_OUT_EN_LSCH3 : R/W ;bitpos:[2] ;default: 1'b0 ; */ 997 /*description: This is the output enable control bit for low speed channel3.*/ 998 #define LEDC_SIG_OUT_EN_LSCH3 (BIT(2)) 999 #define LEDC_SIG_OUT_EN_LSCH3_M (BIT(2)) 1000 #define LEDC_SIG_OUT_EN_LSCH3_V 0x1 1001 #define LEDC_SIG_OUT_EN_LSCH3_S 2 1002 /* LEDC_TIMER_SEL_LSCH3 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ 1003 /*description: There are four low speed timers the two bits are used to select 1004 one of them for low speed channel3. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ 1005 #define LEDC_TIMER_SEL_LSCH3 0x00000003 1006 #define LEDC_TIMER_SEL_LSCH3_M ((LEDC_TIMER_SEL_LSCH3_V)<<(LEDC_TIMER_SEL_LSCH3_S)) 1007 #define LEDC_TIMER_SEL_LSCH3_V 0x3 1008 #define LEDC_TIMER_SEL_LSCH3_S 0 1009 1010 #define LEDC_LSCH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x00E0) 1011 /* LEDC_HPOINT_LSCH3 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ 1012 /*description: The output value changes to high when lstimerx(x=[0 3]) selected 1013 by low speed channel3 has reached reg_hpoint_lsch3[19:0]*/ 1014 #define LEDC_HPOINT_LSCH3 0x000FFFFF 1015 #define LEDC_HPOINT_LSCH3_M ((LEDC_HPOINT_LSCH3_V)<<(LEDC_HPOINT_LSCH3_S)) 1016 #define LEDC_HPOINT_LSCH3_V 0xFFFFF 1017 #define LEDC_HPOINT_LSCH3_S 0 1018 1019 #define LEDC_LSCH3_DUTY_REG (DR_REG_LEDC_BASE + 0x00E4) 1020 /* LEDC_DUTY_LSCH3 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ 1021 /*description: The register is used to control output duty. When lstimerx(x=[0 1022 3]) choosed by low speed channel3 has reached reg_lpoint_lsch3 the output signal changes to low. reg_lpoint_lsch3=(reg_hpoint_lsch3[19:0]+reg_duty_lsch3[24:4]) (1) reg_lpoint_lsch3=(reg_hpoint_lsch3[19:0]+reg_duty_lsch3[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ 1023 #define LEDC_DUTY_LSCH3 0x01FFFFFF 1024 #define LEDC_DUTY_LSCH3_M ((LEDC_DUTY_LSCH3_V)<<(LEDC_DUTY_LSCH3_S)) 1025 #define LEDC_DUTY_LSCH3_V 0x1FFFFFF 1026 #define LEDC_DUTY_LSCH3_S 0 1027 1028 #define LEDC_LSCH3_CONF1_REG (DR_REG_LEDC_BASE + 0x00E8) 1029 /* LEDC_DUTY_START_LSCH3 : R/W ;bitpos:[31] ;default: 1'b0 ; */ 1030 /*description: When reg_duty_num_hsch3 reg_duty_cycle_hsch3 and reg_duty_scale_hsch3 1031 has been configured. these register won't take effect until set reg_duty_start_hsch3. this bit is automatically cleared by hardware.*/ 1032 #define LEDC_DUTY_START_LSCH3 (BIT(31)) 1033 #define LEDC_DUTY_START_LSCH3_M (BIT(31)) 1034 #define LEDC_DUTY_START_LSCH3_V 0x1 1035 #define LEDC_DUTY_START_LSCH3_S 31 1036 /* LEDC_DUTY_INC_LSCH3 : R/W ;bitpos:[30] ;default: 1'b1 ; */ 1037 /*description: This register is used to increase the duty of output signal or 1038 decrease the duty of output signal for low speed channel3.*/ 1039 #define LEDC_DUTY_INC_LSCH3 (BIT(30)) 1040 #define LEDC_DUTY_INC_LSCH3_M (BIT(30)) 1041 #define LEDC_DUTY_INC_LSCH3_V 0x1 1042 #define LEDC_DUTY_INC_LSCH3_S 30 1043 /* LEDC_DUTY_NUM_LSCH3 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ 1044 /*description: This register is used to control the num of increased or decreased 1045 times for low speed channel3.*/ 1046 #define LEDC_DUTY_NUM_LSCH3 0x000003FF 1047 #define LEDC_DUTY_NUM_LSCH3_M ((LEDC_DUTY_NUM_LSCH3_V)<<(LEDC_DUTY_NUM_LSCH3_S)) 1048 #define LEDC_DUTY_NUM_LSCH3_V 0x3FF 1049 #define LEDC_DUTY_NUM_LSCH3_S 20 1050 /* LEDC_DUTY_CYCLE_LSCH3 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ 1051 /*description: This register is used to increase or decrease the duty every 1052 reg_duty_cycle_lsch3 cycles for low speed channel3.*/ 1053 #define LEDC_DUTY_CYCLE_LSCH3 0x000003FF 1054 #define LEDC_DUTY_CYCLE_LSCH3_M ((LEDC_DUTY_CYCLE_LSCH3_V)<<(LEDC_DUTY_CYCLE_LSCH3_S)) 1055 #define LEDC_DUTY_CYCLE_LSCH3_V 0x3FF 1056 #define LEDC_DUTY_CYCLE_LSCH3_S 10 1057 /* LEDC_DUTY_SCALE_LSCH3 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ 1058 /*description: This register controls the increase or decrease step scale for 1059 low speed channel3.*/ 1060 #define LEDC_DUTY_SCALE_LSCH3 0x000003FF 1061 #define LEDC_DUTY_SCALE_LSCH3_M ((LEDC_DUTY_SCALE_LSCH3_V)<<(LEDC_DUTY_SCALE_LSCH3_S)) 1062 #define LEDC_DUTY_SCALE_LSCH3_V 0x3FF 1063 #define LEDC_DUTY_SCALE_LSCH3_S 0 1064 1065 #define LEDC_LSCH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00EC) 1066 /* LEDC_DUTY_LSCH3 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ 1067 /*description: This register represents the current duty of the output signal 1068 for low speed channel3.*/ 1069 #define LEDC_DUTY_LSCH3 0x01FFFFFF 1070 #define LEDC_DUTY_LSCH3_M ((LEDC_DUTY_LSCH3_V)<<(LEDC_DUTY_LSCH3_S)) 1071 #define LEDC_DUTY_LSCH3_V 0x1FFFFFF 1072 #define LEDC_DUTY_LSCH3_S 0 1073 1074 #define LEDC_LSCH4_CONF0_REG (DR_REG_LEDC_BASE + 0x00F0) 1075 /* LEDC_PARA_UP_LSCH4 : R/W ;bitpos:[4] ;default: 1'b0 ; */ 1076 /*description: This bit is used to update register LEDC_LSCH4_HPOINT and LEDC_LSCH4_DUTY 1077 for low speed channel4.*/ 1078 #define LEDC_PARA_UP_LSCH4 (BIT(4)) 1079 #define LEDC_PARA_UP_LSCH4_M (BIT(4)) 1080 #define LEDC_PARA_UP_LSCH4_V 0x1 1081 #define LEDC_PARA_UP_LSCH4_S 4 1082 /* LEDC_IDLE_LV_LSCH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */ 1083 /*description: This bit is used to control the output value when low speed channel4 is off.*/ 1084 #define LEDC_IDLE_LV_LSCH4 (BIT(3)) 1085 #define LEDC_IDLE_LV_LSCH4_M (BIT(3)) 1086 #define LEDC_IDLE_LV_LSCH4_V 0x1 1087 #define LEDC_IDLE_LV_LSCH4_S 3 1088 /* LEDC_SIG_OUT_EN_LSCH4 : R/W ;bitpos:[2] ;default: 1'b0 ; */ 1089 /*description: This is the output enable control bit for low speed channel4.*/ 1090 #define LEDC_SIG_OUT_EN_LSCH4 (BIT(2)) 1091 #define LEDC_SIG_OUT_EN_LSCH4_M (BIT(2)) 1092 #define LEDC_SIG_OUT_EN_LSCH4_V 0x1 1093 #define LEDC_SIG_OUT_EN_LSCH4_S 2 1094 /* LEDC_TIMER_SEL_LSCH4 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ 1095 /*description: There are four low speed timers the two bits are used to select 1096 one of them for low speed channel4. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ 1097 #define LEDC_TIMER_SEL_LSCH4 0x00000003 1098 #define LEDC_TIMER_SEL_LSCH4_M ((LEDC_TIMER_SEL_LSCH4_V)<<(LEDC_TIMER_SEL_LSCH4_S)) 1099 #define LEDC_TIMER_SEL_LSCH4_V 0x3 1100 #define LEDC_TIMER_SEL_LSCH4_S 0 1101 1102 #define LEDC_LSCH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x00F4) 1103 /* LEDC_HPOINT_LSCH4 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ 1104 /*description: The output value changes to high when lstimerx(x=[0 3]) selected 1105 by low speed channel4 has reached reg_hpoint_lsch4[19:0]*/ 1106 #define LEDC_HPOINT_LSCH4 0x000FFFFF 1107 #define LEDC_HPOINT_LSCH4_M ((LEDC_HPOINT_LSCH4_V)<<(LEDC_HPOINT_LSCH4_S)) 1108 #define LEDC_HPOINT_LSCH4_V 0xFFFFF 1109 #define LEDC_HPOINT_LSCH4_S 0 1110 1111 #define LEDC_LSCH4_DUTY_REG (DR_REG_LEDC_BASE + 0x00F8) 1112 /* LEDC_DUTY_LSCH4 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ 1113 /*description: The register is used to control output duty. When lstimerx(x=[0 1114 3]) choosed by low speed channel4 has reached reg_lpoint_lsch4 the output signal changes to low. reg_lpoint_lsch4=(reg_hpoint_lsch4[19:0]+reg_duty_lsch4[24:4]) (1) reg_lpoint_lsch4=(reg_hpoint_lsch4[19:0]+reg_duty_lsch4[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ 1115 #define LEDC_DUTY_LSCH4 0x01FFFFFF 1116 #define LEDC_DUTY_LSCH4_M ((LEDC_DUTY_LSCH4_V)<<(LEDC_DUTY_LSCH4_S)) 1117 #define LEDC_DUTY_LSCH4_V 0x1FFFFFF 1118 #define LEDC_DUTY_LSCH4_S 0 1119 1120 #define LEDC_LSCH4_CONF1_REG (DR_REG_LEDC_BASE + 0x00FC) 1121 /* LEDC_DUTY_START_LSCH4 : R/W ;bitpos:[31] ;default: 1'b0 ; */ 1122 /*description: When reg_duty_num_hsch4 reg_duty_cycle_hsch4 and reg_duty_scale_hsch4 1123 has been configured. these register won't take effect until set reg_duty_start_hsch4. this bit is automatically cleared by hardware.*/ 1124 #define LEDC_DUTY_START_LSCH4 (BIT(31)) 1125 #define LEDC_DUTY_START_LSCH4_M (BIT(31)) 1126 #define LEDC_DUTY_START_LSCH4_V 0x1 1127 #define LEDC_DUTY_START_LSCH4_S 31 1128 /* LEDC_DUTY_INC_LSCH4 : R/W ;bitpos:[30] ;default: 1'b1 ; */ 1129 /*description: This register is used to increase the duty of output signal or 1130 decrease the duty of output signal for low speed channel4.*/ 1131 #define LEDC_DUTY_INC_LSCH4 (BIT(30)) 1132 #define LEDC_DUTY_INC_LSCH4_M (BIT(30)) 1133 #define LEDC_DUTY_INC_LSCH4_V 0x1 1134 #define LEDC_DUTY_INC_LSCH4_S 30 1135 /* LEDC_DUTY_NUM_LSCH4 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ 1136 /*description: This register is used to control the num of increased or decreased 1137 times for low speed channel4.*/ 1138 #define LEDC_DUTY_NUM_LSCH4 0x000003FF 1139 #define LEDC_DUTY_NUM_LSCH4_M ((LEDC_DUTY_NUM_LSCH4_V)<<(LEDC_DUTY_NUM_LSCH4_S)) 1140 #define LEDC_DUTY_NUM_LSCH4_V 0x3FF 1141 #define LEDC_DUTY_NUM_LSCH4_S 20 1142 /* LEDC_DUTY_CYCLE_LSCH4 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ 1143 /*description: This register is used to increase or decrease the duty every 1144 reg_duty_cycle_lsch4 cycles for low speed channel4.*/ 1145 #define LEDC_DUTY_CYCLE_LSCH4 0x000003FF 1146 #define LEDC_DUTY_CYCLE_LSCH4_M ((LEDC_DUTY_CYCLE_LSCH4_V)<<(LEDC_DUTY_CYCLE_LSCH4_S)) 1147 #define LEDC_DUTY_CYCLE_LSCH4_V 0x3FF 1148 #define LEDC_DUTY_CYCLE_LSCH4_S 10 1149 /* LEDC_DUTY_SCALE_LSCH4 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ 1150 /*description: This register controls the increase or decrease step scale for 1151 low speed channel4.*/ 1152 #define LEDC_DUTY_SCALE_LSCH4 0x000003FF 1153 #define LEDC_DUTY_SCALE_LSCH4_M ((LEDC_DUTY_SCALE_LSCH4_V)<<(LEDC_DUTY_SCALE_LSCH4_S)) 1154 #define LEDC_DUTY_SCALE_LSCH4_V 0x3FF 1155 #define LEDC_DUTY_SCALE_LSCH4_S 0 1156 1157 #define LEDC_LSCH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0100) 1158 /* LEDC_DUTY_LSCH4 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ 1159 /*description: This register represents the current duty of the output signal 1160 for low speed channel4.*/ 1161 #define LEDC_DUTY_LSCH4 0x01FFFFFF 1162 #define LEDC_DUTY_LSCH4_M ((LEDC_DUTY_LSCH4_V)<<(LEDC_DUTY_LSCH4_S)) 1163 #define LEDC_DUTY_LSCH4_V 0x1FFFFFF 1164 #define LEDC_DUTY_LSCH4_S 0 1165 1166 #define LEDC_LSCH5_CONF0_REG (DR_REG_LEDC_BASE + 0x0104) 1167 /* LEDC_PARA_UP_LSCH5 : R/W ;bitpos:[4] ;default: 1'b0 ; */ 1168 /*description: This bit is used to update register LEDC_LSCH5_HPOINT and LEDC_LSCH5_DUTY 1169 for low speed channel5.*/ 1170 #define LEDC_PARA_UP_LSCH5 (BIT(4)) 1171 #define LEDC_PARA_UP_LSCH5_M (BIT(4)) 1172 #define LEDC_PARA_UP_LSCH5_V 0x1 1173 #define LEDC_PARA_UP_LSCH5_S 4 1174 /* LEDC_IDLE_LV_LSCH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */ 1175 /*description: This bit is used to control the output value when low speed channel5 is off.*/ 1176 #define LEDC_IDLE_LV_LSCH5 (BIT(3)) 1177 #define LEDC_IDLE_LV_LSCH5_M (BIT(3)) 1178 #define LEDC_IDLE_LV_LSCH5_V 0x1 1179 #define LEDC_IDLE_LV_LSCH5_S 3 1180 /* LEDC_SIG_OUT_EN_LSCH5 : R/W ;bitpos:[2] ;default: 1'b0 ; */ 1181 /*description: This is the output enable control bit for low speed channel5.*/ 1182 #define LEDC_SIG_OUT_EN_LSCH5 (BIT(2)) 1183 #define LEDC_SIG_OUT_EN_LSCH5_M (BIT(2)) 1184 #define LEDC_SIG_OUT_EN_LSCH5_V 0x1 1185 #define LEDC_SIG_OUT_EN_LSCH5_S 2 1186 /* LEDC_TIMER_SEL_LSCH5 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ 1187 /*description: There are four low speed timers the two bits are used to select 1188 one of them for low speed channel5. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ 1189 #define LEDC_TIMER_SEL_LSCH5 0x00000003 1190 #define LEDC_TIMER_SEL_LSCH5_M ((LEDC_TIMER_SEL_LSCH5_V)<<(LEDC_TIMER_SEL_LSCH5_S)) 1191 #define LEDC_TIMER_SEL_LSCH5_V 0x3 1192 #define LEDC_TIMER_SEL_LSCH5_S 0 1193 1194 #define LEDC_LSCH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x0108) 1195 /* LEDC_HPOINT_LSCH5 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ 1196 /*description: The output value changes to high when lstimerx(x=[0 3]) selected 1197 by low speed channel5 has reached reg_hpoint_lsch5[19:0]*/ 1198 #define LEDC_HPOINT_LSCH5 0x000FFFFF 1199 #define LEDC_HPOINT_LSCH5_M ((LEDC_HPOINT_LSCH5_V)<<(LEDC_HPOINT_LSCH5_S)) 1200 #define LEDC_HPOINT_LSCH5_V 0xFFFFF 1201 #define LEDC_HPOINT_LSCH5_S 0 1202 1203 #define LEDC_LSCH5_DUTY_REG (DR_REG_LEDC_BASE + 0x010C) 1204 /* LEDC_DUTY_LSCH5 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ 1205 /*description: The register is used to control output duty. When lstimerx(x=[0 1206 3]) choosed by low speed channel5 has reached reg_lpoint_lsch5 the output signal changes to low. reg_lpoint_lsch5=(reg_hpoint_lsch5[19:0]+reg_duty_lsch5[24:4]) (1) reg_lpoint_lsch5=(reg_hpoint_lsch5[19:0]+reg_duty_lsch5[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ 1207 #define LEDC_DUTY_LSCH5 0x01FFFFFF 1208 #define LEDC_DUTY_LSCH5_M ((LEDC_DUTY_LSCH5_V)<<(LEDC_DUTY_LSCH5_S)) 1209 #define LEDC_DUTY_LSCH5_V 0x1FFFFFF 1210 #define LEDC_DUTY_LSCH5_S 0 1211 1212 #define LEDC_LSCH5_CONF1_REG (DR_REG_LEDC_BASE + 0x0110) 1213 /* LEDC_DUTY_START_LSCH5 : R/W ;bitpos:[31] ;default: 1'b0 ; */ 1214 /*description: When reg_duty_num_hsch4 reg_duty_cycle_hsch4 and reg_duty_scale_hsch4 1215 has been configured. these register won't take effect until set reg_duty_start_hsch4. this bit is automatically cleared by hardware.*/ 1216 #define LEDC_DUTY_START_LSCH5 (BIT(31)) 1217 #define LEDC_DUTY_START_LSCH5_M (BIT(31)) 1218 #define LEDC_DUTY_START_LSCH5_V 0x1 1219 #define LEDC_DUTY_START_LSCH5_S 31 1220 /* LEDC_DUTY_INC_LSCH5 : R/W ;bitpos:[30] ;default: 1'b1 ; */ 1221 /*description: This register is used to increase the duty of output signal or 1222 decrease the duty of output signal for low speed channel5.*/ 1223 #define LEDC_DUTY_INC_LSCH5 (BIT(30)) 1224 #define LEDC_DUTY_INC_LSCH5_M (BIT(30)) 1225 #define LEDC_DUTY_INC_LSCH5_V 0x1 1226 #define LEDC_DUTY_INC_LSCH5_S 30 1227 /* LEDC_DUTY_NUM_LSCH5 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ 1228 /*description: This register is used to control the num of increased or decreased 1229 times for low speed channel5.*/ 1230 #define LEDC_DUTY_NUM_LSCH5 0x000003FF 1231 #define LEDC_DUTY_NUM_LSCH5_M ((LEDC_DUTY_NUM_LSCH5_V)<<(LEDC_DUTY_NUM_LSCH5_S)) 1232 #define LEDC_DUTY_NUM_LSCH5_V 0x3FF 1233 #define LEDC_DUTY_NUM_LSCH5_S 20 1234 /* LEDC_DUTY_CYCLE_LSCH5 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ 1235 /*description: This register is used to increase or decrease the duty every 1236 reg_duty_cycle_lsch5 cycles for low speed channel4.*/ 1237 #define LEDC_DUTY_CYCLE_LSCH5 0x000003FF 1238 #define LEDC_DUTY_CYCLE_LSCH5_M ((LEDC_DUTY_CYCLE_LSCH5_V)<<(LEDC_DUTY_CYCLE_LSCH5_S)) 1239 #define LEDC_DUTY_CYCLE_LSCH5_V 0x3FF 1240 #define LEDC_DUTY_CYCLE_LSCH5_S 10 1241 /* LEDC_DUTY_SCALE_LSCH5 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ 1242 /*description: This register controls the increase or decrease step scale for 1243 low speed channel5.*/ 1244 #define LEDC_DUTY_SCALE_LSCH5 0x000003FF 1245 #define LEDC_DUTY_SCALE_LSCH5_M ((LEDC_DUTY_SCALE_LSCH5_V)<<(LEDC_DUTY_SCALE_LSCH5_S)) 1246 #define LEDC_DUTY_SCALE_LSCH5_V 0x3FF 1247 #define LEDC_DUTY_SCALE_LSCH5_S 0 1248 1249 #define LEDC_LSCH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0114) 1250 /* LEDC_DUTY_LSCH5 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ 1251 /*description: This register represents the current duty of the output signal 1252 for low speed channel5.*/ 1253 #define LEDC_DUTY_LSCH5 0x01FFFFFF 1254 #define LEDC_DUTY_LSCH5_M ((LEDC_DUTY_LSCH5_V)<<(LEDC_DUTY_LSCH5_S)) 1255 #define LEDC_DUTY_LSCH5_V 0x1FFFFFF 1256 #define LEDC_DUTY_LSCH5_S 0 1257 1258 #define LEDC_LSCH6_CONF0_REG (DR_REG_LEDC_BASE + 0x0118) 1259 /* LEDC_PARA_UP_LSCH6 : R/W ;bitpos:[4] ;default: 1'b0 ; */ 1260 /*description: This bit is used to update register LEDC_LSCH6_HPOINT and LEDC_LSCH6_DUTY 1261 for low speed channel6.*/ 1262 #define LEDC_PARA_UP_LSCH6 (BIT(4)) 1263 #define LEDC_PARA_UP_LSCH6_M (BIT(4)) 1264 #define LEDC_PARA_UP_LSCH6_V 0x1 1265 #define LEDC_PARA_UP_LSCH6_S 4 1266 /* LEDC_IDLE_LV_LSCH6 : R/W ;bitpos:[3] ;default: 1'b0 ; */ 1267 /*description: This bit is used to control the output value when low speed channel6 is off.*/ 1268 #define LEDC_IDLE_LV_LSCH6 (BIT(3)) 1269 #define LEDC_IDLE_LV_LSCH6_M (BIT(3)) 1270 #define LEDC_IDLE_LV_LSCH6_V 0x1 1271 #define LEDC_IDLE_LV_LSCH6_S 3 1272 /* LEDC_SIG_OUT_EN_LSCH6 : R/W ;bitpos:[2] ;default: 1'b0 ; */ 1273 /*description: This is the output enable control bit for low speed channel6.*/ 1274 #define LEDC_SIG_OUT_EN_LSCH6 (BIT(2)) 1275 #define LEDC_SIG_OUT_EN_LSCH6_M (BIT(2)) 1276 #define LEDC_SIG_OUT_EN_LSCH6_V 0x1 1277 #define LEDC_SIG_OUT_EN_LSCH6_S 2 1278 /* LEDC_TIMER_SEL_LSCH6 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ 1279 /*description: There are four low speed timers the two bits are used to select 1280 one of them for low speed channel6. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ 1281 #define LEDC_TIMER_SEL_LSCH6 0x00000003 1282 #define LEDC_TIMER_SEL_LSCH6_M ((LEDC_TIMER_SEL_LSCH6_V)<<(LEDC_TIMER_SEL_LSCH6_S)) 1283 #define LEDC_TIMER_SEL_LSCH6_V 0x3 1284 #define LEDC_TIMER_SEL_LSCH6_S 0 1285 1286 #define LEDC_LSCH6_HPOINT_REG (DR_REG_LEDC_BASE + 0x011C) 1287 /* LEDC_HPOINT_LSCH6 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ 1288 /*description: The output value changes to high when lstimerx(x=[0 3]) selected 1289 by low speed channel6 has reached reg_hpoint_lsch6[19:0]*/ 1290 #define LEDC_HPOINT_LSCH6 0x000FFFFF 1291 #define LEDC_HPOINT_LSCH6_M ((LEDC_HPOINT_LSCH6_V)<<(LEDC_HPOINT_LSCH6_S)) 1292 #define LEDC_HPOINT_LSCH6_V 0xFFFFF 1293 #define LEDC_HPOINT_LSCH6_S 0 1294 1295 #define LEDC_LSCH6_DUTY_REG (DR_REG_LEDC_BASE + 0x0120) 1296 /* LEDC_DUTY_LSCH6 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ 1297 /*description: The register is used to control output duty. When lstimerx(x=[0 1298 3]) choosed by low speed channel6 has reached reg_lpoint_lsch6 the output signal changes to low. reg_lpoint_lsch6=(reg_hpoint_lsch6[19:0]+reg_duty_lsch6[24:4]) (1) reg_lpoint_lsch6=(reg_hpoint_lsch6[19:0]+reg_duty_lsch6[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ 1299 #define LEDC_DUTY_LSCH6 0x01FFFFFF 1300 #define LEDC_DUTY_LSCH6_M ((LEDC_DUTY_LSCH6_V)<<(LEDC_DUTY_LSCH6_S)) 1301 #define LEDC_DUTY_LSCH6_V 0x1FFFFFF 1302 #define LEDC_DUTY_LSCH6_S 0 1303 1304 #define LEDC_LSCH6_CONF1_REG (DR_REG_LEDC_BASE + 0x0124) 1305 /* LEDC_DUTY_START_LSCH6 : R/W ;bitpos:[31] ;default: 1'b0 ; */ 1306 /*description: When reg_duty_num_hsch6 reg_duty_cycle_hsch6 and reg_duty_scale_hsch6 1307 has been configured. these register won't take effect until set reg_duty_start_hsch6. this bit is automatically cleared by hardware.*/ 1308 #define LEDC_DUTY_START_LSCH6 (BIT(31)) 1309 #define LEDC_DUTY_START_LSCH6_M (BIT(31)) 1310 #define LEDC_DUTY_START_LSCH6_V 0x1 1311 #define LEDC_DUTY_START_LSCH6_S 31 1312 /* LEDC_DUTY_INC_LSCH6 : R/W ;bitpos:[30] ;default: 1'b1 ; */ 1313 /*description: This register is used to increase the duty of output signal or 1314 decrease the duty of output signal for low speed channel6.*/ 1315 #define LEDC_DUTY_INC_LSCH6 (BIT(30)) 1316 #define LEDC_DUTY_INC_LSCH6_M (BIT(30)) 1317 #define LEDC_DUTY_INC_LSCH6_V 0x1 1318 #define LEDC_DUTY_INC_LSCH6_S 30 1319 /* LEDC_DUTY_NUM_LSCH6 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ 1320 /*description: This register is used to control the num of increased or decreased 1321 times for low speed channel6.*/ 1322 #define LEDC_DUTY_NUM_LSCH6 0x000003FF 1323 #define LEDC_DUTY_NUM_LSCH6_M ((LEDC_DUTY_NUM_LSCH6_V)<<(LEDC_DUTY_NUM_LSCH6_S)) 1324 #define LEDC_DUTY_NUM_LSCH6_V 0x3FF 1325 #define LEDC_DUTY_NUM_LSCH6_S 20 1326 /* LEDC_DUTY_CYCLE_LSCH6 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ 1327 /*description: This register is used to increase or decrease the duty every 1328 reg_duty_cycle_lsch6 cycles for low speed channel6.*/ 1329 #define LEDC_DUTY_CYCLE_LSCH6 0x000003FF 1330 #define LEDC_DUTY_CYCLE_LSCH6_M ((LEDC_DUTY_CYCLE_LSCH6_V)<<(LEDC_DUTY_CYCLE_LSCH6_S)) 1331 #define LEDC_DUTY_CYCLE_LSCH6_V 0x3FF 1332 #define LEDC_DUTY_CYCLE_LSCH6_S 10 1333 /* LEDC_DUTY_SCALE_LSCH6 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ 1334 /*description: This register controls the increase or decrease step scale for 1335 low speed channel6.*/ 1336 #define LEDC_DUTY_SCALE_LSCH6 0x000003FF 1337 #define LEDC_DUTY_SCALE_LSCH6_M ((LEDC_DUTY_SCALE_LSCH6_V)<<(LEDC_DUTY_SCALE_LSCH6_S)) 1338 #define LEDC_DUTY_SCALE_LSCH6_V 0x3FF 1339 #define LEDC_DUTY_SCALE_LSCH6_S 0 1340 1341 #define LEDC_LSCH6_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0128) 1342 /* LEDC_DUTY_LSCH6 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ 1343 /*description: This register represents the current duty of the output signal 1344 for low speed channel6.*/ 1345 #define LEDC_DUTY_LSCH6 0x01FFFFFF 1346 #define LEDC_DUTY_LSCH6_M ((LEDC_DUTY_LSCH6_V)<<(LEDC_DUTY_LSCH6_S)) 1347 #define LEDC_DUTY_LSCH6_V 0x1FFFFFF 1348 #define LEDC_DUTY_LSCH6_S 0 1349 1350 #define LEDC_LSCH7_CONF0_REG (DR_REG_LEDC_BASE + 0x012C) 1351 /* LEDC_PARA_UP_LSCH7 : R/W ;bitpos:[4] ;default: 1'b0 ; */ 1352 /*description: This bit is used to update register LEDC_LSCH7_HPOINT and LEDC_LSCH7_DUTY 1353 for low speed channel7.*/ 1354 #define LEDC_PARA_UP_LSCH7 (BIT(4)) 1355 #define LEDC_PARA_UP_LSCH7_M (BIT(4)) 1356 #define LEDC_PARA_UP_LSCH7_V 0x1 1357 #define LEDC_PARA_UP_LSCH7_S 4 1358 /* LEDC_IDLE_LV_LSCH7 : R/W ;bitpos:[3] ;default: 1'b0 ; */ 1359 /*description: This bit is used to control the output value when low speed channel7 is off.*/ 1360 #define LEDC_IDLE_LV_LSCH7 (BIT(3)) 1361 #define LEDC_IDLE_LV_LSCH7_M (BIT(3)) 1362 #define LEDC_IDLE_LV_LSCH7_V 0x1 1363 #define LEDC_IDLE_LV_LSCH7_S 3 1364 /* LEDC_SIG_OUT_EN_LSCH7 : R/W ;bitpos:[2] ;default: 1'b0 ; */ 1365 /*description: This is the output enable control bit for low speed channel7.*/ 1366 #define LEDC_SIG_OUT_EN_LSCH7 (BIT(2)) 1367 #define LEDC_SIG_OUT_EN_LSCH7_M (BIT(2)) 1368 #define LEDC_SIG_OUT_EN_LSCH7_V 0x1 1369 #define LEDC_SIG_OUT_EN_LSCH7_S 2 1370 /* LEDC_TIMER_SEL_LSCH7 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ 1371 /*description: There are four low speed timers the two bits are used to select 1372 one of them for low speed channel7. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ 1373 #define LEDC_TIMER_SEL_LSCH7 0x00000003 1374 #define LEDC_TIMER_SEL_LSCH7_M ((LEDC_TIMER_SEL_LSCH7_V)<<(LEDC_TIMER_SEL_LSCH7_S)) 1375 #define LEDC_TIMER_SEL_LSCH7_V 0x3 1376 #define LEDC_TIMER_SEL_LSCH7_S 0 1377 1378 #define LEDC_LSCH7_HPOINT_REG (DR_REG_LEDC_BASE + 0x0130) 1379 /* LEDC_HPOINT_LSCH7 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ 1380 /*description: The output value changes to high when lstimerx(x=[0 3]) selected 1381 by low speed channel7 has reached reg_hpoint_lsch7[19:0]*/ 1382 #define LEDC_HPOINT_LSCH7 0x000FFFFF 1383 #define LEDC_HPOINT_LSCH7_M ((LEDC_HPOINT_LSCH7_V)<<(LEDC_HPOINT_LSCH7_S)) 1384 #define LEDC_HPOINT_LSCH7_V 0xFFFFF 1385 #define LEDC_HPOINT_LSCH7_S 0 1386 1387 #define LEDC_LSCH7_DUTY_REG (DR_REG_LEDC_BASE + 0x0134) 1388 /* LEDC_DUTY_LSCH7 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ 1389 /*description: The register is used to control output duty. When lstimerx(x=[0 1390 3]) choosed by low speed channel7 has reached reg_lpoint_lsch7 the output signal changes to low. reg_lpoint_lsch7=(reg_hpoint_lsch7[19:0]+reg_duty_lsch7[24:4]) (1) reg_lpoint_lsch7=(reg_hpoint_lsch7[19:0]+reg_duty_lsch7[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ 1391 #define LEDC_DUTY_LSCH7 0x01FFFFFF 1392 #define LEDC_DUTY_LSCH7_M ((LEDC_DUTY_LSCH7_V)<<(LEDC_DUTY_LSCH7_S)) 1393 #define LEDC_DUTY_LSCH7_V 0x1FFFFFF 1394 #define LEDC_DUTY_LSCH7_S 0 1395 1396 #define LEDC_LSCH7_CONF1_REG (DR_REG_LEDC_BASE + 0x0138) 1397 /* LEDC_DUTY_START_LSCH7 : R/W ;bitpos:[31] ;default: 1'b0 ; */ 1398 /*description: When reg_duty_num_hsch4 reg_duty_cycle_hsch4 and reg_duty_scale_hsch4 1399 has been configured. these register won't take effect until set reg_duty_start_hsch4. this bit is automatically cleared by hardware.*/ 1400 #define LEDC_DUTY_START_LSCH7 (BIT(31)) 1401 #define LEDC_DUTY_START_LSCH7_M (BIT(31)) 1402 #define LEDC_DUTY_START_LSCH7_V 0x1 1403 #define LEDC_DUTY_START_LSCH7_S 31 1404 /* LEDC_DUTY_INC_LSCH7 : R/W ;bitpos:[30] ;default: 1'b1 ; */ 1405 /*description: This register is used to increase the duty of output signal or 1406 decrease the duty of output signal for low speed channel4.*/ 1407 #define LEDC_DUTY_INC_LSCH7 (BIT(30)) 1408 #define LEDC_DUTY_INC_LSCH7_M (BIT(30)) 1409 #define LEDC_DUTY_INC_LSCH7_V 0x1 1410 #define LEDC_DUTY_INC_LSCH7_S 30 1411 /* LEDC_DUTY_NUM_LSCH7 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ 1412 /*description: This register is used to control the num of increased or decreased 1413 times for low speed channel4.*/ 1414 #define LEDC_DUTY_NUM_LSCH7 0x000003FF 1415 #define LEDC_DUTY_NUM_LSCH7_M ((LEDC_DUTY_NUM_LSCH7_V)<<(LEDC_DUTY_NUM_LSCH7_S)) 1416 #define LEDC_DUTY_NUM_LSCH7_V 0x3FF 1417 #define LEDC_DUTY_NUM_LSCH7_S 20 1418 /* LEDC_DUTY_CYCLE_LSCH7 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ 1419 /*description: This register is used to increase or decrease the duty every 1420 reg_duty_cycle_lsch7 cycles for low speed channel7.*/ 1421 #define LEDC_DUTY_CYCLE_LSCH7 0x000003FF 1422 #define LEDC_DUTY_CYCLE_LSCH7_M ((LEDC_DUTY_CYCLE_LSCH7_V)<<(LEDC_DUTY_CYCLE_LSCH7_S)) 1423 #define LEDC_DUTY_CYCLE_LSCH7_V 0x3FF 1424 #define LEDC_DUTY_CYCLE_LSCH7_S 10 1425 /* LEDC_DUTY_SCALE_LSCH7 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ 1426 /*description: This register controls the increase or decrease step scale for 1427 low speed channel7.*/ 1428 #define LEDC_DUTY_SCALE_LSCH7 0x000003FF 1429 #define LEDC_DUTY_SCALE_LSCH7_M ((LEDC_DUTY_SCALE_LSCH7_V)<<(LEDC_DUTY_SCALE_LSCH7_S)) 1430 #define LEDC_DUTY_SCALE_LSCH7_V 0x3FF 1431 #define LEDC_DUTY_SCALE_LSCH7_S 0 1432 1433 #define LEDC_LSCH7_DUTY_R_REG (DR_REG_LEDC_BASE + 0x013C) 1434 /* LEDC_DUTY_LSCH7 : RO ;bitpos:[24:0] ;default: 25'h0 ; */ 1435 /*description: This register represents the current duty of the output signal 1436 for low speed channel7.*/ 1437 #define LEDC_DUTY_LSCH7 0x01FFFFFF 1438 #define LEDC_DUTY_LSCH7_M ((LEDC_DUTY_LSCH7_V)<<(LEDC_DUTY_LSCH7_S)) 1439 #define LEDC_DUTY_LSCH7_V 0x1FFFFFF 1440 #define LEDC_DUTY_LSCH7_S 0 1441 1442 #define LEDC_HSTIMER0_CONF_REG (DR_REG_LEDC_BASE + 0x0140) 1443 /* LEDC_TICK_SEL_HSTIMER0 : R/W ;bitpos:[25] ;default: 1'b0 ; */ 1444 /*description: This bit is used to choose apb_clk or ref_tick for high speed 1445 timer0. 1'b1:apb_clk 0:ref_tick*/ 1446 #define LEDC_TICK_SEL_HSTIMER0 (BIT(25)) 1447 #define LEDC_TICK_SEL_HSTIMER0_M (BIT(25)) 1448 #define LEDC_TICK_SEL_HSTIMER0_V 0x1 1449 #define LEDC_TICK_SEL_HSTIMER0_S 25 1450 /* LEDC_HSTIMER0_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ 1451 /*description: This bit is used to reset high speed timer0 the counter will be 0 after reset.*/ 1452 #define LEDC_HSTIMER0_RST (BIT(24)) 1453 #define LEDC_HSTIMER0_RST_M (BIT(24)) 1454 #define LEDC_HSTIMER0_RST_V 0x1 1455 #define LEDC_HSTIMER0_RST_S 24 1456 /* LEDC_HSTIMER0_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ 1457 /*description: This bit is used to pause the counter in high speed timer0*/ 1458 #define LEDC_HSTIMER0_PAUSE (BIT(23)) 1459 #define LEDC_HSTIMER0_PAUSE_M (BIT(23)) 1460 #define LEDC_HSTIMER0_PAUSE_V 0x1 1461 #define LEDC_HSTIMER0_PAUSE_S 23 1462 /* LEDC_DIV_NUM_HSTIMER0 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ 1463 /*description: This register is used to configure parameter for divider in high 1464 speed timer0 the least significant eight bits represent the decimal part.*/ 1465 #define LEDC_DIV_NUM_HSTIMER0 0x0003FFFF 1466 #define LEDC_DIV_NUM_HSTIMER0_M ((LEDC_DIV_NUM_HSTIMER0_V)<<(LEDC_DIV_NUM_HSTIMER0_S)) 1467 #define LEDC_DIV_NUM_HSTIMER0_V 0x3FFFF 1468 #define LEDC_DIV_NUM_HSTIMER0_S 5 1469 /* LEDC_HSTIMER0_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ 1470 /*description: This register controls the range of the counter in high speed 1471 timer0. the counter range is [0 2**reg_hstimer0_lim] the max bit width for counter is 20.*/ 1472 #define LEDC_HSTIMER0_DUTY_RES 0x0000001F 1473 #define LEDC_HSTIMER0_DUTY_RES_M ((LEDC_HSTIMER0_DUTY_RES_V)<<(LEDC_HSTIMER0_DUTY_RES_S)) 1474 #define LEDC_HSTIMER0_DUTY_RES_V 0x1F 1475 #define LEDC_HSTIMER0_DUTY_RES_S 0 1476 // Keep the definitions below to be compatible with previous version 1477 #define LEDC_HSTIMER0_LIM LEDC_HSTIMER0_DUTY_RES 1478 #define LEDC_HSTIMER0_LIM_M LEDC_HSTIMER0_DUTY_RES_M 1479 #define LEDC_HSTIMER0_LIM_V LEDC_HSTIMER0_DUTY_RES_V 1480 #define LEDC_HSTIMER0_LIM_S LEDC_HSTIMER0_DUTY_RES_S 1481 1482 #define LEDC_HSTIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0x0144) 1483 /* LEDC_HSTIMER0_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ 1484 /*description: software can read this register to get the current counter value 1485 in high speed timer0*/ 1486 #define LEDC_HSTIMER0_CNT 0x000FFFFF 1487 #define LEDC_HSTIMER0_CNT_M ((LEDC_HSTIMER0_CNT_V)<<(LEDC_HSTIMER0_CNT_S)) 1488 #define LEDC_HSTIMER0_CNT_V 0xFFFFF 1489 #define LEDC_HSTIMER0_CNT_S 0 1490 1491 #define LEDC_HSTIMER1_CONF_REG (DR_REG_LEDC_BASE + 0x0148) 1492 /* LEDC_TICK_SEL_HSTIMER1 : R/W ;bitpos:[25] ;default: 1'b0 ; */ 1493 /*description: This bit is used to choose apb_clk or ref_tick for high speed 1494 timer1. 1'b1:apb_clk 0:ref_tick*/ 1495 #define LEDC_TICK_SEL_HSTIMER1 (BIT(25)) 1496 #define LEDC_TICK_SEL_HSTIMER1_M (BIT(25)) 1497 #define LEDC_TICK_SEL_HSTIMER1_V 0x1 1498 #define LEDC_TICK_SEL_HSTIMER1_S 25 1499 /* LEDC_HSTIMER1_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ 1500 /*description: This bit is used to reset high speed timer1 the counter will be 0 after reset.*/ 1501 #define LEDC_HSTIMER1_RST (BIT(24)) 1502 #define LEDC_HSTIMER1_RST_M (BIT(24)) 1503 #define LEDC_HSTIMER1_RST_V 0x1 1504 #define LEDC_HSTIMER1_RST_S 24 1505 /* LEDC_HSTIMER1_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ 1506 /*description: This bit is used to pause the counter in high speed timer1*/ 1507 #define LEDC_HSTIMER1_PAUSE (BIT(23)) 1508 #define LEDC_HSTIMER1_PAUSE_M (BIT(23)) 1509 #define LEDC_HSTIMER1_PAUSE_V 0x1 1510 #define LEDC_HSTIMER1_PAUSE_S 23 1511 /* LEDC_DIV_NUM_HSTIMER1 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ 1512 /*description: This register is used to configure parameter for divider in high 1513 speed timer1 the least significant eight bits represent the decimal part.*/ 1514 #define LEDC_DIV_NUM_HSTIMER1 0x0003FFFF 1515 #define LEDC_DIV_NUM_HSTIMER1_M ((LEDC_DIV_NUM_HSTIMER1_V)<<(LEDC_DIV_NUM_HSTIMER1_S)) 1516 #define LEDC_DIV_NUM_HSTIMER1_V 0x3FFFF 1517 #define LEDC_DIV_NUM_HSTIMER1_S 5 1518 /* LEDC_HSTIMER1_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ 1519 /*description: This register controls the range of the counter in high speed 1520 timer1. the counter range is [0 2**reg_hstimer1_lim] the max bit width for counter is 20.*/ 1521 #define LEDC_HSTIMER1_DUTY_RES 0x0000001F 1522 #define LEDC_HSTIMER1_DUTY_RES_M ((LEDC_HSTIMER1_DUTY_RES_V)<<(LEDC_HSTIMER1_DUTY_RES_S)) 1523 #define LEDC_HSTIMER1_DUTY_RES_V 0x1F 1524 #define LEDC_HSTIMER1_DUTY_RES_S 0 1525 // Keep the definitions below to be compatible with previous version 1526 #define LEDC_HSTIMER1_LIM LEDC_HSTIMER1_DUTY_RES 1527 #define LEDC_HSTIMER1_LIM_M LEDC_HSTIMER1_DUTY_RES_M 1528 #define LEDC_HSTIMER1_LIM_V LEDC_HSTIMER1_DUTY_RES_V 1529 #define LEDC_HSTIMER1_LIM_S LEDC_HSTIMER1_DUTY_RES_S 1530 1531 #define LEDC_HSTIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0x014C) 1532 /* LEDC_HSTIMER1_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ 1533 /*description: software can read this register to get the current counter value 1534 in high speed timer1.*/ 1535 #define LEDC_HSTIMER1_CNT 0x000FFFFF 1536 #define LEDC_HSTIMER1_CNT_M ((LEDC_HSTIMER1_CNT_V)<<(LEDC_HSTIMER1_CNT_S)) 1537 #define LEDC_HSTIMER1_CNT_V 0xFFFFF 1538 #define LEDC_HSTIMER1_CNT_S 0 1539 1540 #define LEDC_HSTIMER2_CONF_REG (DR_REG_LEDC_BASE + 0x0150) 1541 /* LEDC_TICK_SEL_HSTIMER2 : R/W ;bitpos:[25] ;default: 1'b0 ; */ 1542 /*description: This bit is used to choose apb_clk or ref_tick for high speed 1543 timer2. 1'b1:apb_clk 0:ref_tick*/ 1544 #define LEDC_TICK_SEL_HSTIMER2 (BIT(25)) 1545 #define LEDC_TICK_SEL_HSTIMER2_M (BIT(25)) 1546 #define LEDC_TICK_SEL_HSTIMER2_V 0x1 1547 #define LEDC_TICK_SEL_HSTIMER2_S 25 1548 /* LEDC_HSTIMER2_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ 1549 /*description: This bit is used to reset high speed timer2 the counter will be 0 after reset.*/ 1550 #define LEDC_HSTIMER2_RST (BIT(24)) 1551 #define LEDC_HSTIMER2_RST_M (BIT(24)) 1552 #define LEDC_HSTIMER2_RST_V 0x1 1553 #define LEDC_HSTIMER2_RST_S 24 1554 /* LEDC_HSTIMER2_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ 1555 /*description: This bit is used to pause the counter in high speed timer2*/ 1556 #define LEDC_HSTIMER2_PAUSE (BIT(23)) 1557 #define LEDC_HSTIMER2_PAUSE_M (BIT(23)) 1558 #define LEDC_HSTIMER2_PAUSE_V 0x1 1559 #define LEDC_HSTIMER2_PAUSE_S 23 1560 /* LEDC_DIV_NUM_HSTIMER2 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ 1561 /*description: This register is used to configure parameter for divider in high 1562 speed timer2 the least significant eight bits represent the decimal part.*/ 1563 #define LEDC_DIV_NUM_HSTIMER2 0x0003FFFF 1564 #define LEDC_DIV_NUM_HSTIMER2_M ((LEDC_DIV_NUM_HSTIMER2_V)<<(LEDC_DIV_NUM_HSTIMER2_S)) 1565 #define LEDC_DIV_NUM_HSTIMER2_V 0x3FFFF 1566 #define LEDC_DIV_NUM_HSTIMER2_S 5 1567 /* LEDC_HSTIMER2_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ 1568 /*description: This register controls the range of the counter in high speed 1569 timer2. the counter range is [0 2**reg_hstimer2_lim] the max bit width for counter is 20.*/ 1570 #define LEDC_HSTIMER2_DUTY_RES 0x0000001F 1571 #define LEDC_HSTIMER2_DUTY_RES_M ((LEDC_HSTIMER2_DUTY_RES_V)<<(LEDC_HSTIMER2_DUTY_RES_S)) 1572 #define LEDC_HSTIMER2_DUTY_RES_V 0x1F 1573 #define LEDC_HSTIMER2_DUTY_RES_S 0 1574 // Keep the definitions below to be compatible with previous version 1575 #define LEDC_HSTIMER2_LIM LEDC_HSTIMER2_DUTY_RES 1576 #define LEDC_HSTIMER2_LIM_M LEDC_HSTIMER2_DUTY_RES_M 1577 #define LEDC_HSTIMER2_LIM_V LEDC_HSTIMER2_DUTY_RES_V 1578 #define LEDC_HSTIMER2_LIM_S LEDC_HSTIMER2_DUTY_RES_S 1579 1580 #define LEDC_HSTIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0x0154) 1581 /* LEDC_HSTIMER2_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ 1582 /*description: software can read this register to get the current counter value 1583 in high speed timer2*/ 1584 #define LEDC_HSTIMER2_CNT 0x000FFFFF 1585 #define LEDC_HSTIMER2_CNT_M ((LEDC_HSTIMER2_CNT_V)<<(LEDC_HSTIMER2_CNT_S)) 1586 #define LEDC_HSTIMER2_CNT_V 0xFFFFF 1587 #define LEDC_HSTIMER2_CNT_S 0 1588 1589 #define LEDC_HSTIMER3_CONF_REG (DR_REG_LEDC_BASE + 0x0158) 1590 /* LEDC_TICK_SEL_HSTIMER3 : R/W ;bitpos:[25] ;default: 1'b0 ; */ 1591 /*description: This bit is used to choose apb_clk or ref_tick for high speed 1592 timer3. 1'b1:apb_clk 0:ref_tick*/ 1593 #define LEDC_TICK_SEL_HSTIMER3 (BIT(25)) 1594 #define LEDC_TICK_SEL_HSTIMER3_M (BIT(25)) 1595 #define LEDC_TICK_SEL_HSTIMER3_V 0x1 1596 #define LEDC_TICK_SEL_HSTIMER3_S 25 1597 /* LEDC_HSTIMER3_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ 1598 /*description: This bit is used to reset high speed timer3 the counter will be 0 after reset.*/ 1599 #define LEDC_HSTIMER3_RST (BIT(24)) 1600 #define LEDC_HSTIMER3_RST_M (BIT(24)) 1601 #define LEDC_HSTIMER3_RST_V 0x1 1602 #define LEDC_HSTIMER3_RST_S 24 1603 /* LEDC_HSTIMER3_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ 1604 /*description: This bit is used to pause the counter in high speed timer3*/ 1605 #define LEDC_HSTIMER3_PAUSE (BIT(23)) 1606 #define LEDC_HSTIMER3_PAUSE_M (BIT(23)) 1607 #define LEDC_HSTIMER3_PAUSE_V 0x1 1608 #define LEDC_HSTIMER3_PAUSE_S 23 1609 /* LEDC_DIV_NUM_HSTIMER3 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ 1610 /*description: This register is used to configure parameter for divider in high 1611 speed timer3 the least significant eight bits represent the decimal part.*/ 1612 #define LEDC_DIV_NUM_HSTIMER3 0x0003FFFF 1613 #define LEDC_DIV_NUM_HSTIMER3_M ((LEDC_DIV_NUM_HSTIMER3_V)<<(LEDC_DIV_NUM_HSTIMER3_S)) 1614 #define LEDC_DIV_NUM_HSTIMER3_V 0x3FFFF 1615 #define LEDC_DIV_NUM_HSTIMER3_S 5 1616 /* LEDC_HSTIMER3_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ 1617 /*description: This register controls the range of the counter in high speed 1618 timer3. the counter range is [0 2**reg_hstimer3_lim] the max bit width for counter is 20.*/ 1619 #define LEDC_HSTIMER3_DUTY_RES 0x0000001F 1620 #define LEDC_HSTIMER3_DUTY_RES_M ((LEDC_HSTIMER3_DUTY_RES_V)<<(LEDC_HSTIMER3_DUTY_RES_S)) 1621 #define LEDC_HSTIMER3_DUTY_RES_V 0x1F 1622 #define LEDC_HSTIMER3_DUTY_RES_S 0 1623 // Keep the definitions below to be compatible with previous version 1624 #define LEDC_HSTIMER3_LIM LEDC_HSTIMER3_DUTY_RES 1625 #define LEDC_HSTIMER3_LIM_M LEDC_HSTIMER3_DUTY_RES_M 1626 #define LEDC_HSTIMER3_LIM_V LEDC_HSTIMER3_DUTY_RES_V 1627 #define LEDC_HSTIMER3_LIM_S LEDC_HSTIMER3_DUTY_RES_S 1628 1629 #define LEDC_HSTIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0x015C) 1630 /* LEDC_HSTIMER3_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ 1631 /*description: software can read this register to get the current counter value 1632 in high speed timer3*/ 1633 #define LEDC_HSTIMER3_CNT 0x000FFFFF 1634 #define LEDC_HSTIMER3_CNT_M ((LEDC_HSTIMER3_CNT_V)<<(LEDC_HSTIMER3_CNT_S)) 1635 #define LEDC_HSTIMER3_CNT_V 0xFFFFF 1636 #define LEDC_HSTIMER3_CNT_S 0 1637 1638 #define LEDC_LSTIMER0_CONF_REG (DR_REG_LEDC_BASE + 0x0160) 1639 /* LEDC_LSTIMER0_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */ 1640 /*description: Set this bit to update reg_div_num_lstime0 and reg_lstimer0_lim.*/ 1641 #define LEDC_LSTIMER0_PARA_UP (BIT(26)) 1642 #define LEDC_LSTIMER0_PARA_UP_M (BIT(26)) 1643 #define LEDC_LSTIMER0_PARA_UP_V 0x1 1644 #define LEDC_LSTIMER0_PARA_UP_S 26 1645 /* LEDC_TICK_SEL_LSTIMER0 : R/W ;bitpos:[25] ;default: 1'b0 ; */ 1646 /*description: This bit is used to choose slow_clk or ref_tick for low speed 1647 timer0. 1'b1:slow_clk 0:ref_tick*/ 1648 #define LEDC_TICK_SEL_LSTIMER0 (BIT(25)) 1649 #define LEDC_TICK_SEL_LSTIMER0_M (BIT(25)) 1650 #define LEDC_TICK_SEL_LSTIMER0_V 0x1 1651 #define LEDC_TICK_SEL_LSTIMER0_S 25 1652 /* LEDC_LSTIMER0_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ 1653 /*description: This bit is used to reset low speed timer0 the counter will be 0 after reset.*/ 1654 #define LEDC_LSTIMER0_RST (BIT(24)) 1655 #define LEDC_LSTIMER0_RST_M (BIT(24)) 1656 #define LEDC_LSTIMER0_RST_V 0x1 1657 #define LEDC_LSTIMER0_RST_S 24 1658 /* LEDC_LSTIMER0_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ 1659 /*description: This bit is used to pause the counter in low speed timer0.*/ 1660 #define LEDC_LSTIMER0_PAUSE (BIT(23)) 1661 #define LEDC_LSTIMER0_PAUSE_M (BIT(23)) 1662 #define LEDC_LSTIMER0_PAUSE_V 0x1 1663 #define LEDC_LSTIMER0_PAUSE_S 23 1664 /* LEDC_DIV_NUM_LSTIMER0 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ 1665 /*description: This register is used to configure parameter for divider in low 1666 speed timer0 the least significant eight bits represent the decimal part.*/ 1667 #define LEDC_DIV_NUM_LSTIMER0 0x0003FFFF 1668 #define LEDC_DIV_NUM_LSTIMER0_M ((LEDC_DIV_NUM_LSTIMER0_V)<<(LEDC_DIV_NUM_LSTIMER0_S)) 1669 #define LEDC_DIV_NUM_LSTIMER0_V 0x3FFFF 1670 #define LEDC_DIV_NUM_LSTIMER0_S 5 1671 /* LEDC_LSTIMER0_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ 1672 /*description: This register controls the range of the counter in low speed 1673 timer0. the counter range is [0 2**reg_lstimer0_lim] the max bit width for counter is 20.*/ 1674 #define LEDC_LSTIMER0_DUTY_RES 0x0000001F 1675 #define LEDC_LSTIMER0_DUTY_RES_M ((LEDC_LSTIMER0_DUTY_RES_V)<<(LEDC_LSTIMER0_DUTY_RES_S)) 1676 #define LEDC_LSTIMER0_DUTY_RES_V 0x1F 1677 #define LEDC_LSTIMER0_DUTY_RES_S 0 1678 // Keep the definitions below to be compatible with previous version 1679 #define LEDC_LSTIMER0_LIM LEDC_LSTIMER0_DUTY_RES 1680 #define LEDC_LSTIMER0_LIM_M LEDC_LSTIMER0_DUTY_RES_M 1681 #define LEDC_LSTIMER0_LIM_V LEDC_LSTIMER0_DUTY_RES_V 1682 #define LEDC_LSTIMER0_LIM_S LEDC_LSTIMER0_DUTY_RES_S 1683 1684 #define LEDC_LSTIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0x0164) 1685 /* LEDC_LSTIMER0_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ 1686 /*description: software can read this register to get the current counter value 1687 in low speed timer0.*/ 1688 #define LEDC_LSTIMER0_CNT 0x000FFFFF 1689 #define LEDC_LSTIMER0_CNT_M ((LEDC_LSTIMER0_CNT_V)<<(LEDC_LSTIMER0_CNT_S)) 1690 #define LEDC_LSTIMER0_CNT_V 0xFFFFF 1691 #define LEDC_LSTIMER0_CNT_S 0 1692 1693 #define LEDC_LSTIMER1_CONF_REG (DR_REG_LEDC_BASE + 0x0168) 1694 /* LEDC_LSTIMER1_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */ 1695 /*description: Set this bit to update reg_div_num_lstime1 and reg_lstimer1_lim.*/ 1696 #define LEDC_LSTIMER1_PARA_UP (BIT(26)) 1697 #define LEDC_LSTIMER1_PARA_UP_M (BIT(26)) 1698 #define LEDC_LSTIMER1_PARA_UP_V 0x1 1699 #define LEDC_LSTIMER1_PARA_UP_S 26 1700 /* LEDC_TICK_SEL_LSTIMER1 : R/W ;bitpos:[25] ;default: 1'b0 ; */ 1701 /*description: This bit is used to choose slow_clk or ref_tick for low speed 1702 timer1. 1'b1:slow_clk 0:ref_tick*/ 1703 #define LEDC_TICK_SEL_LSTIMER1 (BIT(25)) 1704 #define LEDC_TICK_SEL_LSTIMER1_M (BIT(25)) 1705 #define LEDC_TICK_SEL_LSTIMER1_V 0x1 1706 #define LEDC_TICK_SEL_LSTIMER1_S 25 1707 /* LEDC_LSTIMER1_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ 1708 /*description: This bit is used to reset low speed timer1 the counter will be 0 after reset.*/ 1709 #define LEDC_LSTIMER1_RST (BIT(24)) 1710 #define LEDC_LSTIMER1_RST_M (BIT(24)) 1711 #define LEDC_LSTIMER1_RST_V 0x1 1712 #define LEDC_LSTIMER1_RST_S 24 1713 /* LEDC_LSTIMER1_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ 1714 /*description: This bit is used to pause the counter in low speed timer1.*/ 1715 #define LEDC_LSTIMER1_PAUSE (BIT(23)) 1716 #define LEDC_LSTIMER1_PAUSE_M (BIT(23)) 1717 #define LEDC_LSTIMER1_PAUSE_V 0x1 1718 #define LEDC_LSTIMER1_PAUSE_S 23 1719 /* LEDC_DIV_NUM_LSTIMER1 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ 1720 /*description: This register is used to configure parameter for divider in low 1721 speed timer1 the least significant eight bits represent the decimal part.*/ 1722 #define LEDC_DIV_NUM_LSTIMER1 0x0003FFFF 1723 #define LEDC_DIV_NUM_LSTIMER1_M ((LEDC_DIV_NUM_LSTIMER1_V)<<(LEDC_DIV_NUM_LSTIMER1_S)) 1724 #define LEDC_DIV_NUM_LSTIMER1_V 0x3FFFF 1725 #define LEDC_DIV_NUM_LSTIMER1_S 5 1726 /* LEDC_LSTIMER1_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ 1727 /*description: This register controls the range of the counter in low speed 1728 timer1. the counter range is [0 2**reg_lstimer1_lim] the max bit width for counter is 20.*/ 1729 #define LEDC_LSTIMER1_DUTY_RES 0x0000001F 1730 #define LEDC_LSTIMER1_DUTY_RES_M ((LEDC_LSTIMER1_DUTY_RES_V)<<(LEDC_LSTIMER1_DUTY_RES_S)) 1731 #define LEDC_LSTIMER1_DUTY_RES_V 0x1F 1732 #define LEDC_LSTIMER1_DUTY_RES_S 0 1733 // Keep the definitions below to be compatible with previous version 1734 #define LEDC_LSTIMER1_LIM LEDC_LSTIMER1_DUTY_RES 1735 #define LEDC_LSTIMER1_LIM_M LEDC_LSTIMER1_DUTY_RES_M 1736 #define LEDC_LSTIMER1_LIM_V LEDC_LSTIMER1_DUTY_RES_V 1737 #define LEDC_LSTIMER1_LIM_S LEDC_LSTIMER1_DUTY_RES_S 1738 1739 #define LEDC_LSTIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0x016C) 1740 /* LEDC_LSTIMER1_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ 1741 /*description: software can read this register to get the current counter value 1742 in low speed timer1.*/ 1743 #define LEDC_LSTIMER1_CNT 0x000FFFFF 1744 #define LEDC_LSTIMER1_CNT_M ((LEDC_LSTIMER1_CNT_V)<<(LEDC_LSTIMER1_CNT_S)) 1745 #define LEDC_LSTIMER1_CNT_V 0xFFFFF 1746 #define LEDC_LSTIMER1_CNT_S 0 1747 1748 #define LEDC_LSTIMER2_CONF_REG (DR_REG_LEDC_BASE + 0x0170) 1749 /* LEDC_LSTIMER2_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */ 1750 /*description: Set this bit to update reg_div_num_lstime2 and reg_lstimer2_lim.*/ 1751 #define LEDC_LSTIMER2_PARA_UP (BIT(26)) 1752 #define LEDC_LSTIMER2_PARA_UP_M (BIT(26)) 1753 #define LEDC_LSTIMER2_PARA_UP_V 0x1 1754 #define LEDC_LSTIMER2_PARA_UP_S 26 1755 /* LEDC_TICK_SEL_LSTIMER2 : R/W ;bitpos:[25] ;default: 1'b0 ; */ 1756 /*description: This bit is used to choose slow_clk or ref_tick for low speed 1757 timer2. 1'b1:slow_clk 0:ref_tick*/ 1758 #define LEDC_TICK_SEL_LSTIMER2 (BIT(25)) 1759 #define LEDC_TICK_SEL_LSTIMER2_M (BIT(25)) 1760 #define LEDC_TICK_SEL_LSTIMER2_V 0x1 1761 #define LEDC_TICK_SEL_LSTIMER2_S 25 1762 /* LEDC_LSTIMER2_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ 1763 /*description: This bit is used to reset low speed timer2 the counter will be 0 after reset.*/ 1764 #define LEDC_LSTIMER2_RST (BIT(24)) 1765 #define LEDC_LSTIMER2_RST_M (BIT(24)) 1766 #define LEDC_LSTIMER2_RST_V 0x1 1767 #define LEDC_LSTIMER2_RST_S 24 1768 /* LEDC_LSTIMER2_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ 1769 /*description: This bit is used to pause the counter in low speed timer2.*/ 1770 #define LEDC_LSTIMER2_PAUSE (BIT(23)) 1771 #define LEDC_LSTIMER2_PAUSE_M (BIT(23)) 1772 #define LEDC_LSTIMER2_PAUSE_V 0x1 1773 #define LEDC_LSTIMER2_PAUSE_S 23 1774 /* LEDC_DIV_NUM_LSTIMER2 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ 1775 /*description: This register is used to configure parameter for divider in low 1776 speed timer2 the least significant eight bits represent the decimal part.*/ 1777 #define LEDC_DIV_NUM_LSTIMER2 0x0003FFFF 1778 #define LEDC_DIV_NUM_LSTIMER2_M ((LEDC_DIV_NUM_LSTIMER2_V)<<(LEDC_DIV_NUM_LSTIMER2_S)) 1779 #define LEDC_DIV_NUM_LSTIMER2_V 0x3FFFF 1780 #define LEDC_DIV_NUM_LSTIMER2_S 5 1781 /* LEDC_LSTIMER2_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ 1782 /*description: This register controls the range of the counter in low speed 1783 timer2. the counter range is [0 2**reg_lstimer2_lim] the max bit width for counter is 20.*/ 1784 #define LEDC_LSTIMER2_DUTY_RES 0x0000001F 1785 #define LEDC_LSTIMER2_DUTY_RES_M ((LEDC_LSTIMER2_DUTY_RES_V)<<(LEDC_LSTIMER2_DUTY_RES_S)) 1786 #define LEDC_LSTIMER2_DUTY_RES_V 0x1F 1787 #define LEDC_LSTIMER2_DUTY_RES_S 0 1788 // Keep the definitions below to be compatible with previous version 1789 #define LEDC_LSTIMER2_LIM LEDC_LSTIMER2_DUTY_RES 1790 #define LEDC_LSTIMER2_LIM_M LEDC_LSTIMER2_DUTY_RES_M 1791 #define LEDC_LSTIMER2_LIM_V LEDC_LSTIMER2_DUTY_RES_V 1792 #define LEDC_LSTIMER2_LIM_S LEDC_LSTIMER2_DUTY_RES_S 1793 1794 #define LEDC_LSTIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0x0174) 1795 /* LEDC_LSTIMER2_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ 1796 /*description: software can read this register to get the current counter value 1797 in low speed timer2.*/ 1798 #define LEDC_LSTIMER2_CNT 0x000FFFFF 1799 #define LEDC_LSTIMER2_CNT_M ((LEDC_LSTIMER2_CNT_V)<<(LEDC_LSTIMER2_CNT_S)) 1800 #define LEDC_LSTIMER2_CNT_V 0xFFFFF 1801 #define LEDC_LSTIMER2_CNT_S 0 1802 1803 #define LEDC_LSTIMER3_CONF_REG (DR_REG_LEDC_BASE + 0x0178) 1804 /* LEDC_LSTIMER3_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */ 1805 /*description: Set this bit to update reg_div_num_lstime3 and reg_lstimer3_lim.*/ 1806 #define LEDC_LSTIMER3_PARA_UP (BIT(26)) 1807 #define LEDC_LSTIMER3_PARA_UP_M (BIT(26)) 1808 #define LEDC_LSTIMER3_PARA_UP_V 0x1 1809 #define LEDC_LSTIMER3_PARA_UP_S 26 1810 /* LEDC_TICK_SEL_LSTIMER3 : R/W ;bitpos:[25] ;default: 1'b0 ; */ 1811 /*description: This bit is used to choose slow_clk or ref_tick for low speed 1812 timer3. 1'b1:slow_clk 0:ref_tick*/ 1813 #define LEDC_TICK_SEL_LSTIMER3 (BIT(25)) 1814 #define LEDC_TICK_SEL_LSTIMER3_M (BIT(25)) 1815 #define LEDC_TICK_SEL_LSTIMER3_V 0x1 1816 #define LEDC_TICK_SEL_LSTIMER3_S 25 1817 /* LEDC_LSTIMER3_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */ 1818 /*description: This bit is used to reset low speed timer3 the counter will be 0 after reset.*/ 1819 #define LEDC_LSTIMER3_RST (BIT(24)) 1820 #define LEDC_LSTIMER3_RST_M (BIT(24)) 1821 #define LEDC_LSTIMER3_RST_V 0x1 1822 #define LEDC_LSTIMER3_RST_S 24 1823 /* LEDC_LSTIMER3_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */ 1824 /*description: This bit is used to pause the counter in low speed timer3.*/ 1825 #define LEDC_LSTIMER3_PAUSE (BIT(23)) 1826 #define LEDC_LSTIMER3_PAUSE_M (BIT(23)) 1827 #define LEDC_LSTIMER3_PAUSE_V 0x1 1828 #define LEDC_LSTIMER3_PAUSE_S 23 1829 /* LEDC_DIV_NUM_LSTIMER3 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */ 1830 /*description: This register is used to configure parameter for divider in low 1831 speed timer3 the least significant eight bits represent the decimal part.*/ 1832 #define LEDC_DIV_NUM_LSTIMER3 0x0003FFFF 1833 #define LEDC_DIV_NUM_LSTIMER3_M ((LEDC_DIV_NUM_LSTIMER3_V)<<(LEDC_DIV_NUM_LSTIMER3_S)) 1834 #define LEDC_DIV_NUM_LSTIMER3_V 0x3FFFF 1835 #define LEDC_DIV_NUM_LSTIMER3_S 5 1836 /* LEDC_LSTIMER3_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ 1837 /*description: This register controls the range of the counter in low speed 1838 timer3. the counter range is [0 2**reg_lstimer3_lim] the max bit width for counter is 20.*/ 1839 #define LEDC_LSTIMER3_DUTY_RES 0x0000001F 1840 #define LEDC_LSTIMER3_DUTY_RES_M ((LEDC_LSTIMER3_DUTY_RES_V)<<(LEDC_LSTIMER3_DUTY_RES_S)) 1841 #define LEDC_LSTIMER3_DUTY_RES_V 0x1F 1842 #define LEDC_LSTIMER3_DUTY_RES_S 0 1843 // Keep the definitions below to be compatible with previous version 1844 #define LEDC_LSTIMER3_LIM LEDC_LSTIMER3_DUTY_RES 1845 #define LEDC_LSTIMER3_LIM_M LEDC_LSTIMER3_DUTY_RES_M 1846 #define LEDC_LSTIMER3_LIM_V LEDC_LSTIMER3_DUTY_RES_V 1847 #define LEDC_LSTIMER3_LIM_S LEDC_LSTIMER3_DUTY_RES_S 1848 1849 #define LEDC_LSTIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0x017C) 1850 /* LEDC_LSTIMER3_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */ 1851 /*description: software can read this register to get the current counter value 1852 in low speed timer3.*/ 1853 #define LEDC_LSTIMER3_CNT 0x000FFFFF 1854 #define LEDC_LSTIMER3_CNT_M ((LEDC_LSTIMER3_CNT_V)<<(LEDC_LSTIMER3_CNT_S)) 1855 #define LEDC_LSTIMER3_CNT_V 0xFFFFF 1856 #define LEDC_LSTIMER3_CNT_S 0 1857 1858 #define LEDC_INT_RAW_REG (DR_REG_LEDC_BASE + 0x0180) 1859 /* LEDC_DUTY_CHNG_END_LSCH7_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */ 1860 /*description: The interrupt raw bit for low speed channel 7 duty change done.*/ 1861 #define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW (BIT(23)) 1862 #define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_M (BIT(23)) 1863 #define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_V 0x1 1864 #define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_S 23 1865 /* LEDC_DUTY_CHNG_END_LSCH6_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */ 1866 /*description: The interrupt raw bit for low speed channel 6 duty change done.*/ 1867 #define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW (BIT(22)) 1868 #define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_M (BIT(22)) 1869 #define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_V 0x1 1870 #define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_S 22 1871 /* LEDC_DUTY_CHNG_END_LSCH5_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */ 1872 /*description: The interrupt raw bit for low speed channel 5 duty change done.*/ 1873 #define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW (BIT(21)) 1874 #define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_M (BIT(21)) 1875 #define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_V 0x1 1876 #define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_S 21 1877 /* LEDC_DUTY_CHNG_END_LSCH4_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */ 1878 /*description: The interrupt raw bit for low speed channel 4 duty change done.*/ 1879 #define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW (BIT(20)) 1880 #define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_M (BIT(20)) 1881 #define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_V 0x1 1882 #define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_S 20 1883 /* LEDC_DUTY_CHNG_END_LSCH3_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */ 1884 /*description: The interrupt raw bit for low speed channel 3 duty change done.*/ 1885 #define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW (BIT(19)) 1886 #define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_M (BIT(19)) 1887 #define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_V 0x1 1888 #define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_S 19 1889 /* LEDC_DUTY_CHNG_END_LSCH2_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ 1890 /*description: The interrupt raw bit for low speed channel 2 duty change done.*/ 1891 #define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW (BIT(18)) 1892 #define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_M (BIT(18)) 1893 #define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_V 0x1 1894 #define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_S 18 1895 /* LEDC_DUTY_CHNG_END_LSCH1_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ 1896 /*description: The interrupt raw bit for low speed channel 1 duty change done.*/ 1897 #define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW (BIT(17)) 1898 #define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_M (BIT(17)) 1899 #define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_V 0x1 1900 #define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_S 17 1901 /* LEDC_DUTY_CHNG_END_LSCH0_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ 1902 /*description: The interrupt raw bit for low speed channel 0 duty change done.*/ 1903 #define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW (BIT(16)) 1904 #define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_M (BIT(16)) 1905 #define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_V 0x1 1906 #define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_S 16 1907 /* LEDC_DUTY_CHNG_END_HSCH7_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ 1908 /*description: The interrupt raw bit for high speed channel 7 duty change done.*/ 1909 #define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW (BIT(15)) 1910 #define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW_M (BIT(15)) 1911 #define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW_V 0x1 1912 #define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW_S 15 1913 /* LEDC_DUTY_CHNG_END_HSCH6_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ 1914 /*description: The interrupt raw bit for high speed channel 6 duty change done.*/ 1915 #define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW (BIT(14)) 1916 #define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW_M (BIT(14)) 1917 #define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW_V 0x1 1918 #define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW_S 14 1919 /* LEDC_DUTY_CHNG_END_HSCH5_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ 1920 /*description: The interrupt raw bit for high speed channel 5 duty change done.*/ 1921 #define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW (BIT(13)) 1922 #define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW_M (BIT(13)) 1923 #define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW_V 0x1 1924 #define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW_S 13 1925 /* LEDC_DUTY_CHNG_END_HSCH4_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ 1926 /*description: The interrupt raw bit for high speed channel 4 duty change done.*/ 1927 #define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW (BIT(12)) 1928 #define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW_M (BIT(12)) 1929 #define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW_V 0x1 1930 #define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW_S 12 1931 /* LEDC_DUTY_CHNG_END_HSCH3_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ 1932 /*description: The interrupt raw bit for high speed channel 3 duty change done.*/ 1933 #define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW (BIT(11)) 1934 #define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW_M (BIT(11)) 1935 #define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW_V 0x1 1936 #define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW_S 11 1937 /* LEDC_DUTY_CHNG_END_HSCH2_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ 1938 /*description: The interrupt raw bit for high speed channel 2 duty change done.*/ 1939 #define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW (BIT(10)) 1940 #define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW_M (BIT(10)) 1941 #define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW_V 0x1 1942 #define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW_S 10 1943 /* LEDC_DUTY_CHNG_END_HSCH1_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ 1944 /*description: The interrupt raw bit for high speed channel 1 duty change done.*/ 1945 #define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW (BIT(9)) 1946 #define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW_M (BIT(9)) 1947 #define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW_V 0x1 1948 #define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW_S 9 1949 /* LEDC_DUTY_CHNG_END_HSCH0_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ 1950 /*description: The interrupt raw bit for high speed channel 0 duty change done.*/ 1951 #define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW (BIT(8)) 1952 #define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW_M (BIT(8)) 1953 #define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW_V 0x1 1954 #define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW_S 8 1955 /* LEDC_LSTIMER3_OVF_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ 1956 /*description: The interrupt raw bit for low speed channel3 counter overflow.*/ 1957 #define LEDC_LSTIMER3_OVF_INT_RAW (BIT(7)) 1958 #define LEDC_LSTIMER3_OVF_INT_RAW_M (BIT(7)) 1959 #define LEDC_LSTIMER3_OVF_INT_RAW_V 0x1 1960 #define LEDC_LSTIMER3_OVF_INT_RAW_S 7 1961 /* LEDC_LSTIMER2_OVF_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ 1962 /*description: The interrupt raw bit for low speed channel2 counter overflow.*/ 1963 #define LEDC_LSTIMER2_OVF_INT_RAW (BIT(6)) 1964 #define LEDC_LSTIMER2_OVF_INT_RAW_M (BIT(6)) 1965 #define LEDC_LSTIMER2_OVF_INT_RAW_V 0x1 1966 #define LEDC_LSTIMER2_OVF_INT_RAW_S 6 1967 /* LEDC_LSTIMER1_OVF_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ 1968 /*description: The interrupt raw bit for low speed channel1 counter overflow.*/ 1969 #define LEDC_LSTIMER1_OVF_INT_RAW (BIT(5)) 1970 #define LEDC_LSTIMER1_OVF_INT_RAW_M (BIT(5)) 1971 #define LEDC_LSTIMER1_OVF_INT_RAW_V 0x1 1972 #define LEDC_LSTIMER1_OVF_INT_RAW_S 5 1973 /* LEDC_LSTIMER0_OVF_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ 1974 /*description: The interrupt raw bit for low speed channel0 counter overflow.*/ 1975 #define LEDC_LSTIMER0_OVF_INT_RAW (BIT(4)) 1976 #define LEDC_LSTIMER0_OVF_INT_RAW_M (BIT(4)) 1977 #define LEDC_LSTIMER0_OVF_INT_RAW_V 0x1 1978 #define LEDC_LSTIMER0_OVF_INT_RAW_S 4 1979 /* LEDC_HSTIMER3_OVF_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ 1980 /*description: The interrupt raw bit for high speed channel3 counter overflow.*/ 1981 #define LEDC_HSTIMER3_OVF_INT_RAW (BIT(3)) 1982 #define LEDC_HSTIMER3_OVF_INT_RAW_M (BIT(3)) 1983 #define LEDC_HSTIMER3_OVF_INT_RAW_V 0x1 1984 #define LEDC_HSTIMER3_OVF_INT_RAW_S 3 1985 /* LEDC_HSTIMER2_OVF_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ 1986 /*description: The interrupt raw bit for high speed channel2 counter overflow.*/ 1987 #define LEDC_HSTIMER2_OVF_INT_RAW (BIT(2)) 1988 #define LEDC_HSTIMER2_OVF_INT_RAW_M (BIT(2)) 1989 #define LEDC_HSTIMER2_OVF_INT_RAW_V 0x1 1990 #define LEDC_HSTIMER2_OVF_INT_RAW_S 2 1991 /* LEDC_HSTIMER1_OVF_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ 1992 /*description: The interrupt raw bit for high speed channel1 counter overflow.*/ 1993 #define LEDC_HSTIMER1_OVF_INT_RAW (BIT(1)) 1994 #define LEDC_HSTIMER1_OVF_INT_RAW_M (BIT(1)) 1995 #define LEDC_HSTIMER1_OVF_INT_RAW_V 0x1 1996 #define LEDC_HSTIMER1_OVF_INT_RAW_S 1 1997 /* LEDC_HSTIMER0_OVF_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ 1998 /*description: The interrupt raw bit for high speed channel0 counter overflow.*/ 1999 #define LEDC_HSTIMER0_OVF_INT_RAW (BIT(0)) 2000 #define LEDC_HSTIMER0_OVF_INT_RAW_M (BIT(0)) 2001 #define LEDC_HSTIMER0_OVF_INT_RAW_V 0x1 2002 #define LEDC_HSTIMER0_OVF_INT_RAW_S 0 2003 2004 #define LEDC_INT_ST_REG (DR_REG_LEDC_BASE + 0x0184) 2005 /* LEDC_DUTY_CHNG_END_LSCH7_INT_ST : RO ;bitpos:[23] ;default: 1'h0 ; */ 2006 /*description: The interrupt status bit for low speed channel 7 duty change done event*/ 2007 #define LEDC_DUTY_CHNG_END_LSCH7_INT_ST (BIT(23)) 2008 #define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_M (BIT(23)) 2009 #define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_V 0x1 2010 #define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_S 23 2011 /* LEDC_DUTY_CHNG_END_LSCH6_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */ 2012 /*description: The interrupt status bit for low speed channel 6 duty change done event.*/ 2013 #define LEDC_DUTY_CHNG_END_LSCH6_INT_ST (BIT(22)) 2014 #define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_M (BIT(22)) 2015 #define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_V 0x1 2016 #define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_S 22 2017 /* LEDC_DUTY_CHNG_END_LSCH5_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */ 2018 /*description: The interrupt status bit for low speed channel 5 duty change done event.*/ 2019 #define LEDC_DUTY_CHNG_END_LSCH5_INT_ST (BIT(21)) 2020 #define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_M (BIT(21)) 2021 #define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_V 0x1 2022 #define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_S 21 2023 /* LEDC_DUTY_CHNG_END_LSCH4_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ 2024 /*description: The interrupt status bit for low speed channel 4 duty change done event.*/ 2025 #define LEDC_DUTY_CHNG_END_LSCH4_INT_ST (BIT(20)) 2026 #define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_M (BIT(20)) 2027 #define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_V 0x1 2028 #define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_S 20 2029 /* LEDC_DUTY_CHNG_END_LSCH3_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ 2030 /*description: The interrupt status bit for low speed channel 3 duty change done event.*/ 2031 #define LEDC_DUTY_CHNG_END_LSCH3_INT_ST (BIT(19)) 2032 #define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_M (BIT(19)) 2033 #define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_V 0x1 2034 #define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_S 19 2035 /* LEDC_DUTY_CHNG_END_LSCH2_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ 2036 /*description: The interrupt status bit for low speed channel 2 duty change done event.*/ 2037 #define LEDC_DUTY_CHNG_END_LSCH2_INT_ST (BIT(18)) 2038 #define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_M (BIT(18)) 2039 #define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_V 0x1 2040 #define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_S 18 2041 /* LEDC_DUTY_CHNG_END_LSCH1_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ 2042 /*description: The interrupt status bit for low speed channel 1 duty change done event.*/ 2043 #define LEDC_DUTY_CHNG_END_LSCH1_INT_ST (BIT(17)) 2044 #define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_M (BIT(17)) 2045 #define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_V 0x1 2046 #define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_S 17 2047 /* LEDC_DUTY_CHNG_END_LSCH0_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ 2048 /*description: The interrupt status bit for low speed channel 0 duty change done event.*/ 2049 #define LEDC_DUTY_CHNG_END_LSCH0_INT_ST (BIT(16)) 2050 #define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_M (BIT(16)) 2051 #define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_V 0x1 2052 #define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_S 16 2053 /* LEDC_DUTY_CHNG_END_HSCH7_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ 2054 /*description: The interrupt status bit for high speed channel 7 duty change done event.*/ 2055 #define LEDC_DUTY_CHNG_END_HSCH7_INT_ST (BIT(15)) 2056 #define LEDC_DUTY_CHNG_END_HSCH7_INT_ST_M (BIT(15)) 2057 #define LEDC_DUTY_CHNG_END_HSCH7_INT_ST_V 0x1 2058 #define LEDC_DUTY_CHNG_END_HSCH7_INT_ST_S 15 2059 /* LEDC_DUTY_CHNG_END_HSCH6_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ 2060 /*description: The interrupt status bit for high speed channel 6 duty change done event.*/ 2061 #define LEDC_DUTY_CHNG_END_HSCH6_INT_ST (BIT(14)) 2062 #define LEDC_DUTY_CHNG_END_HSCH6_INT_ST_M (BIT(14)) 2063 #define LEDC_DUTY_CHNG_END_HSCH6_INT_ST_V 0x1 2064 #define LEDC_DUTY_CHNG_END_HSCH6_INT_ST_S 14 2065 /* LEDC_DUTY_CHNG_END_HSCH5_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ 2066 /*description: The interrupt status bit for high speed channel 5 duty change done event.*/ 2067 #define LEDC_DUTY_CHNG_END_HSCH5_INT_ST (BIT(13)) 2068 #define LEDC_DUTY_CHNG_END_HSCH5_INT_ST_M (BIT(13)) 2069 #define LEDC_DUTY_CHNG_END_HSCH5_INT_ST_V 0x1 2070 #define LEDC_DUTY_CHNG_END_HSCH5_INT_ST_S 13 2071 /* LEDC_DUTY_CHNG_END_HSCH4_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ 2072 /*description: The interrupt status bit for high speed channel 4 duty change done event.*/ 2073 #define LEDC_DUTY_CHNG_END_HSCH4_INT_ST (BIT(12)) 2074 #define LEDC_DUTY_CHNG_END_HSCH4_INT_ST_M (BIT(12)) 2075 #define LEDC_DUTY_CHNG_END_HSCH4_INT_ST_V 0x1 2076 #define LEDC_DUTY_CHNG_END_HSCH4_INT_ST_S 12 2077 /* LEDC_DUTY_CHNG_END_HSCH3_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ 2078 /*description: The interrupt status bit for high speed channel 3 duty change done event.*/ 2079 #define LEDC_DUTY_CHNG_END_HSCH3_INT_ST (BIT(11)) 2080 #define LEDC_DUTY_CHNG_END_HSCH3_INT_ST_M (BIT(11)) 2081 #define LEDC_DUTY_CHNG_END_HSCH3_INT_ST_V 0x1 2082 #define LEDC_DUTY_CHNG_END_HSCH3_INT_ST_S 11 2083 /* LEDC_DUTY_CHNG_END_HSCH2_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ 2084 /*description: The interrupt status bit for high speed channel 2 duty change done event.*/ 2085 #define LEDC_DUTY_CHNG_END_HSCH2_INT_ST (BIT(10)) 2086 #define LEDC_DUTY_CHNG_END_HSCH2_INT_ST_M (BIT(10)) 2087 #define LEDC_DUTY_CHNG_END_HSCH2_INT_ST_V 0x1 2088 #define LEDC_DUTY_CHNG_END_HSCH2_INT_ST_S 10 2089 /* LEDC_DUTY_CHNG_END_HSCH1_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ 2090 /*description: The interrupt status bit for high speed channel 1 duty change done event.*/ 2091 #define LEDC_DUTY_CHNG_END_HSCH1_INT_ST (BIT(9)) 2092 #define LEDC_DUTY_CHNG_END_HSCH1_INT_ST_M (BIT(9)) 2093 #define LEDC_DUTY_CHNG_END_HSCH1_INT_ST_V 0x1 2094 #define LEDC_DUTY_CHNG_END_HSCH1_INT_ST_S 9 2095 /* LEDC_DUTY_CHNG_END_HSCH0_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ 2096 /*description: The interrupt status bit for high speed channel 0 duty change done event.*/ 2097 #define LEDC_DUTY_CHNG_END_HSCH0_INT_ST (BIT(8)) 2098 #define LEDC_DUTY_CHNG_END_HSCH0_INT_ST_M (BIT(8)) 2099 #define LEDC_DUTY_CHNG_END_HSCH0_INT_ST_V 0x1 2100 #define LEDC_DUTY_CHNG_END_HSCH0_INT_ST_S 8 2101 /* LEDC_LSTIMER3_OVF_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ 2102 /*description: The interrupt status bit for low speed channel3 counter overflow event.*/ 2103 #define LEDC_LSTIMER3_OVF_INT_ST (BIT(7)) 2104 #define LEDC_LSTIMER3_OVF_INT_ST_M (BIT(7)) 2105 #define LEDC_LSTIMER3_OVF_INT_ST_V 0x1 2106 #define LEDC_LSTIMER3_OVF_INT_ST_S 7 2107 /* LEDC_LSTIMER2_OVF_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ 2108 /*description: The interrupt status bit for low speed channel2 counter overflow event.*/ 2109 #define LEDC_LSTIMER2_OVF_INT_ST (BIT(6)) 2110 #define LEDC_LSTIMER2_OVF_INT_ST_M (BIT(6)) 2111 #define LEDC_LSTIMER2_OVF_INT_ST_V 0x1 2112 #define LEDC_LSTIMER2_OVF_INT_ST_S 6 2113 /* LEDC_LSTIMER1_OVF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ 2114 /*description: The interrupt status bit for low speed channel1 counter overflow event.*/ 2115 #define LEDC_LSTIMER1_OVF_INT_ST (BIT(5)) 2116 #define LEDC_LSTIMER1_OVF_INT_ST_M (BIT(5)) 2117 #define LEDC_LSTIMER1_OVF_INT_ST_V 0x1 2118 #define LEDC_LSTIMER1_OVF_INT_ST_S 5 2119 /* LEDC_LSTIMER0_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ 2120 /*description: The interrupt status bit for low speed channel0 counter overflow event.*/ 2121 #define LEDC_LSTIMER0_OVF_INT_ST (BIT(4)) 2122 #define LEDC_LSTIMER0_OVF_INT_ST_M (BIT(4)) 2123 #define LEDC_LSTIMER0_OVF_INT_ST_V 0x1 2124 #define LEDC_LSTIMER0_OVF_INT_ST_S 4 2125 /* LEDC_HSTIMER3_OVF_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ 2126 /*description: The interrupt status bit for high speed channel3 counter overflow event.*/ 2127 #define LEDC_HSTIMER3_OVF_INT_ST (BIT(3)) 2128 #define LEDC_HSTIMER3_OVF_INT_ST_M (BIT(3)) 2129 #define LEDC_HSTIMER3_OVF_INT_ST_V 0x1 2130 #define LEDC_HSTIMER3_OVF_INT_ST_S 3 2131 /* LEDC_HSTIMER2_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ 2132 /*description: The interrupt status bit for high speed channel2 counter overflow event.*/ 2133 #define LEDC_HSTIMER2_OVF_INT_ST (BIT(2)) 2134 #define LEDC_HSTIMER2_OVF_INT_ST_M (BIT(2)) 2135 #define LEDC_HSTIMER2_OVF_INT_ST_V 0x1 2136 #define LEDC_HSTIMER2_OVF_INT_ST_S 2 2137 /* LEDC_HSTIMER1_OVF_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ 2138 /*description: The interrupt status bit for high speed channel1 counter overflow event.*/ 2139 #define LEDC_HSTIMER1_OVF_INT_ST (BIT(1)) 2140 #define LEDC_HSTIMER1_OVF_INT_ST_M (BIT(1)) 2141 #define LEDC_HSTIMER1_OVF_INT_ST_V 0x1 2142 #define LEDC_HSTIMER1_OVF_INT_ST_S 1 2143 /* LEDC_HSTIMER0_OVF_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ 2144 /*description: The interrupt status bit for high speed channel0 counter overflow event.*/ 2145 #define LEDC_HSTIMER0_OVF_INT_ST (BIT(0)) 2146 #define LEDC_HSTIMER0_OVF_INT_ST_M (BIT(0)) 2147 #define LEDC_HSTIMER0_OVF_INT_ST_V 0x1 2148 #define LEDC_HSTIMER0_OVF_INT_ST_S 0 2149 2150 #define LEDC_INT_ENA_REG (DR_REG_LEDC_BASE + 0x0188) 2151 /* LEDC_DUTY_CHNG_END_LSCH7_INT_ENA : R/W ;bitpos:[23] ;default: 1'h0 ; */ 2152 /*description: The interrupt enable bit for low speed channel 7 duty change done interrupt.*/ 2153 #define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA (BIT(23)) 2154 #define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_M (BIT(23)) 2155 #define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_V 0x1 2156 #define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_S 23 2157 /* LEDC_DUTY_CHNG_END_LSCH6_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */ 2158 /*description: The interrupt enable bit for low speed channel 6 duty change done interrupt.*/ 2159 #define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA (BIT(22)) 2160 #define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_M (BIT(22)) 2161 #define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_V 0x1 2162 #define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_S 22 2163 /* LEDC_DUTY_CHNG_END_LSCH5_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */ 2164 /*description: The interrupt enable bit for low speed channel 5 duty change done interrupt.*/ 2165 #define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA (BIT(21)) 2166 #define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_M (BIT(21)) 2167 #define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_V 0x1 2168 #define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_S 21 2169 /* LEDC_DUTY_CHNG_END_LSCH4_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ 2170 /*description: The interrupt enable bit for low speed channel 4 duty change done interrupt.*/ 2171 #define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA (BIT(20)) 2172 #define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_M (BIT(20)) 2173 #define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_V 0x1 2174 #define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_S 20 2175 /* LEDC_DUTY_CHNG_END_LSCH3_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ 2176 /*description: The interrupt enable bit for low speed channel 3 duty change done interrupt.*/ 2177 #define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA (BIT(19)) 2178 #define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_M (BIT(19)) 2179 #define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_V 0x1 2180 #define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_S 19 2181 /* LEDC_DUTY_CHNG_END_LSCH2_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ 2182 /*description: The interrupt enable bit for low speed channel 2 duty change done interrupt.*/ 2183 #define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA (BIT(18)) 2184 #define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_M (BIT(18)) 2185 #define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_V 0x1 2186 #define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_S 18 2187 /* LEDC_DUTY_CHNG_END_LSCH1_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ 2188 /*description: The interrupt enable bit for low speed channel 1 duty change done interrupt.*/ 2189 #define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA (BIT(17)) 2190 #define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_M (BIT(17)) 2191 #define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_V 0x1 2192 #define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_S 17 2193 /* LEDC_DUTY_CHNG_END_LSCH0_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ 2194 /*description: The interrupt enable bit for low speed channel 0 duty change done interrupt.*/ 2195 #define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA (BIT(16)) 2196 #define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_M (BIT(16)) 2197 #define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_V 0x1 2198 #define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S 16 2199 /* LEDC_DUTY_CHNG_END_HSCH7_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ 2200 /*description: The interrupt enable bit for high speed channel 7 duty change done interrupt.*/ 2201 #define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA (BIT(15)) 2202 #define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA_M (BIT(15)) 2203 #define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA_V 0x1 2204 #define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA_S 15 2205 /* LEDC_DUTY_CHNG_END_HSCH6_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ 2206 /*description: The interrupt enable bit for high speed channel 6 duty change done interrupt.*/ 2207 #define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA (BIT(14)) 2208 #define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA_M (BIT(14)) 2209 #define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA_V 0x1 2210 #define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA_S 14 2211 /* LEDC_DUTY_CHNG_END_HSCH5_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ 2212 /*description: The interrupt enable bit for high speed channel 5 duty change done interrupt.*/ 2213 #define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA (BIT(13)) 2214 #define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA_M (BIT(13)) 2215 #define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA_V 0x1 2216 #define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA_S 13 2217 /* LEDC_DUTY_CHNG_END_HSCH4_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ 2218 /*description: The interrupt enable bit for high speed channel 4 duty change done interrupt.*/ 2219 #define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA (BIT(12)) 2220 #define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA_M (BIT(12)) 2221 #define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA_V 0x1 2222 #define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA_S 12 2223 /* LEDC_DUTY_CHNG_END_HSCH3_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ 2224 /*description: The interrupt enable bit for high speed channel 3 duty change done interrupt.*/ 2225 #define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA (BIT(11)) 2226 #define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA_M (BIT(11)) 2227 #define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA_V 0x1 2228 #define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA_S 11 2229 /* LEDC_DUTY_CHNG_END_HSCH2_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ 2230 /*description: The interrupt enable bit for high speed channel 2 duty change done interrupt.*/ 2231 #define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA (BIT(10)) 2232 #define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA_M (BIT(10)) 2233 #define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA_V 0x1 2234 #define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA_S 10 2235 /* LEDC_DUTY_CHNG_END_HSCH1_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ 2236 /*description: The interrupt enable bit for high speed channel 1 duty change done interrupt.*/ 2237 #define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA (BIT(9)) 2238 #define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA_M (BIT(9)) 2239 #define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA_V 0x1 2240 #define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA_S 9 2241 /* LEDC_DUTY_CHNG_END_HSCH0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ 2242 /*description: The interrupt enable bit for high speed channel 0 duty change done interrupt.*/ 2243 #define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA (BIT(8)) 2244 #define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_M (BIT(8)) 2245 #define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_V 0x1 2246 #define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_S 8 2247 /* LEDC_LSTIMER3_OVF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ 2248 /*description: The interrupt enable bit for low speed channel3 counter overflow interrupt.*/ 2249 #define LEDC_LSTIMER3_OVF_INT_ENA (BIT(7)) 2250 #define LEDC_LSTIMER3_OVF_INT_ENA_M (BIT(7)) 2251 #define LEDC_LSTIMER3_OVF_INT_ENA_V 0x1 2252 #define LEDC_LSTIMER3_OVF_INT_ENA_S 7 2253 /* LEDC_LSTIMER2_OVF_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ 2254 /*description: The interrupt enable bit for low speed channel2 counter overflow interrupt.*/ 2255 #define LEDC_LSTIMER2_OVF_INT_ENA (BIT(6)) 2256 #define LEDC_LSTIMER2_OVF_INT_ENA_M (BIT(6)) 2257 #define LEDC_LSTIMER2_OVF_INT_ENA_V 0x1 2258 #define LEDC_LSTIMER2_OVF_INT_ENA_S 6 2259 /* LEDC_LSTIMER1_OVF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ 2260 /*description: The interrupt enable bit for low speed channel1 counter overflow interrupt.*/ 2261 #define LEDC_LSTIMER1_OVF_INT_ENA (BIT(5)) 2262 #define LEDC_LSTIMER1_OVF_INT_ENA_M (BIT(5)) 2263 #define LEDC_LSTIMER1_OVF_INT_ENA_V 0x1 2264 #define LEDC_LSTIMER1_OVF_INT_ENA_S 5 2265 /* LEDC_LSTIMER0_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ 2266 /*description: The interrupt enable bit for low speed channel0 counter overflow interrupt.*/ 2267 #define LEDC_LSTIMER0_OVF_INT_ENA (BIT(4)) 2268 #define LEDC_LSTIMER0_OVF_INT_ENA_M (BIT(4)) 2269 #define LEDC_LSTIMER0_OVF_INT_ENA_V 0x1 2270 #define LEDC_LSTIMER0_OVF_INT_ENA_S 4 2271 /* LEDC_HSTIMER3_OVF_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ 2272 /*description: The interrupt enable bit for high speed channel3 counter overflow interrupt.*/ 2273 #define LEDC_HSTIMER3_OVF_INT_ENA (BIT(3)) 2274 #define LEDC_HSTIMER3_OVF_INT_ENA_M (BIT(3)) 2275 #define LEDC_HSTIMER3_OVF_INT_ENA_V 0x1 2276 #define LEDC_HSTIMER3_OVF_INT_ENA_S 3 2277 /* LEDC_HSTIMER2_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ 2278 /*description: The interrupt enable bit for high speed channel2 counter overflow interrupt.*/ 2279 #define LEDC_HSTIMER2_OVF_INT_ENA (BIT(2)) 2280 #define LEDC_HSTIMER2_OVF_INT_ENA_M (BIT(2)) 2281 #define LEDC_HSTIMER2_OVF_INT_ENA_V 0x1 2282 #define LEDC_HSTIMER2_OVF_INT_ENA_S 2 2283 /* LEDC_HSTIMER1_OVF_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 2284 /*description: The interrupt enable bit for high speed channel1 counter overflow interrupt.*/ 2285 #define LEDC_HSTIMER1_OVF_INT_ENA (BIT(1)) 2286 #define LEDC_HSTIMER1_OVF_INT_ENA_M (BIT(1)) 2287 #define LEDC_HSTIMER1_OVF_INT_ENA_V 0x1 2288 #define LEDC_HSTIMER1_OVF_INT_ENA_S 1 2289 /* LEDC_HSTIMER0_OVF_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 2290 /*description: The interrupt enable bit for high speed channel0 counter overflow interrupt.*/ 2291 #define LEDC_HSTIMER0_OVF_INT_ENA (BIT(0)) 2292 #define LEDC_HSTIMER0_OVF_INT_ENA_M (BIT(0)) 2293 #define LEDC_HSTIMER0_OVF_INT_ENA_V 0x1 2294 #define LEDC_HSTIMER0_OVF_INT_ENA_S 0 2295 2296 #define LEDC_INT_CLR_REG (DR_REG_LEDC_BASE + 0x018C) 2297 /* LEDC_DUTY_CHNG_END_LSCH7_INT_CLR : WO ;bitpos:[23] ;default: 1'h0 ; */ 2298 /*description: Set this bit to clear low speed channel 7 duty change done interrupt.*/ 2299 #define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR (BIT(23)) 2300 #define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_M (BIT(23)) 2301 #define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_V 0x1 2302 #define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_S 23 2303 /* LEDC_DUTY_CHNG_END_LSCH6_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */ 2304 /*description: Set this bit to clear low speed channel 6 duty change done interrupt.*/ 2305 #define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR (BIT(22)) 2306 #define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_M (BIT(22)) 2307 #define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_V 0x1 2308 #define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_S 22 2309 /* LEDC_DUTY_CHNG_END_LSCH5_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */ 2310 /*description: Set this bit to clear low speed channel 5 duty change done interrupt.*/ 2311 #define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR (BIT(21)) 2312 #define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_M (BIT(21)) 2313 #define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_V 0x1 2314 #define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_S 21 2315 /* LEDC_DUTY_CHNG_END_LSCH4_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */ 2316 /*description: Set this bit to clear low speed channel 4 duty change done interrupt.*/ 2317 #define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR (BIT(20)) 2318 #define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_M (BIT(20)) 2319 #define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_V 0x1 2320 #define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_S 20 2321 /* LEDC_DUTY_CHNG_END_LSCH3_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ 2322 /*description: Set this bit to clear low speed channel 3 duty change done interrupt.*/ 2323 #define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR (BIT(19)) 2324 #define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_M (BIT(19)) 2325 #define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_V 0x1 2326 #define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_S 19 2327 /* LEDC_DUTY_CHNG_END_LSCH2_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ 2328 /*description: Set this bit to clear low speed channel 2 duty change done interrupt.*/ 2329 #define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR (BIT(18)) 2330 #define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_M (BIT(18)) 2331 #define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_V 0x1 2332 #define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_S 18 2333 /* LEDC_DUTY_CHNG_END_LSCH1_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ 2334 /*description: Set this bit to clear low speed channel 1 duty change done interrupt.*/ 2335 #define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR (BIT(17)) 2336 #define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_M (BIT(17)) 2337 #define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_V 0x1 2338 #define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_S 17 2339 /* LEDC_DUTY_CHNG_END_LSCH0_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ 2340 /*description: Set this bit to clear low speed channel 0 duty change done interrupt.*/ 2341 #define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR (BIT(16)) 2342 #define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_M (BIT(16)) 2343 #define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_V 0x1 2344 #define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_S 16 2345 /* LEDC_DUTY_CHNG_END_HSCH7_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ 2346 /*description: Set this bit to clear high speed channel 7 duty change done interrupt.*/ 2347 #define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR (BIT(15)) 2348 #define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR_M (BIT(15)) 2349 #define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR_V 0x1 2350 #define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR_S 15 2351 /* LEDC_DUTY_CHNG_END_HSCH6_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ 2352 /*description: Set this bit to clear high speed channel 6 duty change done interrupt.*/ 2353 #define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR (BIT(14)) 2354 #define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR_M (BIT(14)) 2355 #define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR_V 0x1 2356 #define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR_S 14 2357 /* LEDC_DUTY_CHNG_END_HSCH5_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ 2358 /*description: Set this bit to clear high speed channel 5 duty change done interrupt.*/ 2359 #define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR (BIT(13)) 2360 #define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR_M (BIT(13)) 2361 #define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR_V 0x1 2362 #define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR_S 13 2363 /* LEDC_DUTY_CHNG_END_HSCH4_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ 2364 /*description: Set this bit to clear high speed channel 4 duty change done interrupt.*/ 2365 #define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR (BIT(12)) 2366 #define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR_M (BIT(12)) 2367 #define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR_V 0x1 2368 #define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR_S 12 2369 /* LEDC_DUTY_CHNG_END_HSCH3_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ 2370 /*description: Set this bit to clear high speed channel 3 duty change done interrupt.*/ 2371 #define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR (BIT(11)) 2372 #define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR_M (BIT(11)) 2373 #define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR_V 0x1 2374 #define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR_S 11 2375 /* LEDC_DUTY_CHNG_END_HSCH2_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ 2376 /*description: Set this bit to clear high speed channel 2 duty change done interrupt.*/ 2377 #define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR (BIT(10)) 2378 #define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR_M (BIT(10)) 2379 #define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR_V 0x1 2380 #define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR_S 10 2381 /* LEDC_DUTY_CHNG_END_HSCH1_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ 2382 /*description: Set this bit to clear high speed channel 1 duty change done interrupt.*/ 2383 #define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR (BIT(9)) 2384 #define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR_M (BIT(9)) 2385 #define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR_V 0x1 2386 #define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR_S 9 2387 /* LEDC_DUTY_CHNG_END_HSCH0_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ 2388 /*description: Set this bit to clear high speed channel 0 duty change done interrupt.*/ 2389 #define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR (BIT(8)) 2390 #define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR_M (BIT(8)) 2391 #define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR_V 0x1 2392 #define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR_S 8 2393 /* LEDC_LSTIMER3_OVF_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ 2394 /*description: Set this bit to clear low speed channel3 counter overflow interrupt.*/ 2395 #define LEDC_LSTIMER3_OVF_INT_CLR (BIT(7)) 2396 #define LEDC_LSTIMER3_OVF_INT_CLR_M (BIT(7)) 2397 #define LEDC_LSTIMER3_OVF_INT_CLR_V 0x1 2398 #define LEDC_LSTIMER3_OVF_INT_CLR_S 7 2399 /* LEDC_LSTIMER2_OVF_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ 2400 /*description: Set this bit to clear low speed channel2 counter overflow interrupt.*/ 2401 #define LEDC_LSTIMER2_OVF_INT_CLR (BIT(6)) 2402 #define LEDC_LSTIMER2_OVF_INT_CLR_M (BIT(6)) 2403 #define LEDC_LSTIMER2_OVF_INT_CLR_V 0x1 2404 #define LEDC_LSTIMER2_OVF_INT_CLR_S 6 2405 /* LEDC_LSTIMER1_OVF_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ 2406 /*description: Set this bit to clear low speed channel1 counter overflow interrupt.*/ 2407 #define LEDC_LSTIMER1_OVF_INT_CLR (BIT(5)) 2408 #define LEDC_LSTIMER1_OVF_INT_CLR_M (BIT(5)) 2409 #define LEDC_LSTIMER1_OVF_INT_CLR_V 0x1 2410 #define LEDC_LSTIMER1_OVF_INT_CLR_S 5 2411 /* LEDC_LSTIMER0_OVF_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ 2412 /*description: Set this bit to clear low speed channel0 counter overflow interrupt.*/ 2413 #define LEDC_LSTIMER0_OVF_INT_CLR (BIT(4)) 2414 #define LEDC_LSTIMER0_OVF_INT_CLR_M (BIT(4)) 2415 #define LEDC_LSTIMER0_OVF_INT_CLR_V 0x1 2416 #define LEDC_LSTIMER0_OVF_INT_CLR_S 4 2417 /* LEDC_HSTIMER3_OVF_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ 2418 /*description: Set this bit to clear high speed channel3 counter overflow interrupt.*/ 2419 #define LEDC_HSTIMER3_OVF_INT_CLR (BIT(3)) 2420 #define LEDC_HSTIMER3_OVF_INT_CLR_M (BIT(3)) 2421 #define LEDC_HSTIMER3_OVF_INT_CLR_V 0x1 2422 #define LEDC_HSTIMER3_OVF_INT_CLR_S 3 2423 /* LEDC_HSTIMER2_OVF_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ 2424 /*description: Set this bit to clear high speed channel2 counter overflow interrupt.*/ 2425 #define LEDC_HSTIMER2_OVF_INT_CLR (BIT(2)) 2426 #define LEDC_HSTIMER2_OVF_INT_CLR_M (BIT(2)) 2427 #define LEDC_HSTIMER2_OVF_INT_CLR_V 0x1 2428 #define LEDC_HSTIMER2_OVF_INT_CLR_S 2 2429 /* LEDC_HSTIMER1_OVF_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ 2430 /*description: Set this bit to clear high speed channel1 counter overflow interrupt.*/ 2431 #define LEDC_HSTIMER1_OVF_INT_CLR (BIT(1)) 2432 #define LEDC_HSTIMER1_OVF_INT_CLR_M (BIT(1)) 2433 #define LEDC_HSTIMER1_OVF_INT_CLR_V 0x1 2434 #define LEDC_HSTIMER1_OVF_INT_CLR_S 1 2435 /* LEDC_HSTIMER0_OVF_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ 2436 /*description: Set this bit to clear high speed channel0 counter overflow interrupt.*/ 2437 #define LEDC_HSTIMER0_OVF_INT_CLR (BIT(0)) 2438 #define LEDC_HSTIMER0_OVF_INT_CLR_M (BIT(0)) 2439 #define LEDC_HSTIMER0_OVF_INT_CLR_V 0x1 2440 #define LEDC_HSTIMER0_OVF_INT_CLR_S 0 2441 2442 #define LEDC_CONF_REG (DR_REG_LEDC_BASE + 0x0190) 2443 /* LEDC_APB_CLK_SEL : R/W ;bitpos:[0] ;default: 1'b0 ; */ 2444 /*description: This bit is used to set the frequency of slow_clk. 1'b1:80mhz 1'b0:8mhz*/ 2445 #define LEDC_APB_CLK_SEL (BIT(0)) 2446 #define LEDC_APB_CLK_SEL_M (BIT(0)) 2447 #define LEDC_APB_CLK_SEL_V 0x1 2448 #define LEDC_APB_CLK_SEL_S 0 2449 2450 #define LEDC_DATE_REG (DR_REG_LEDC_BASE + 0x01FC) 2451 /* LEDC_DATE : R/W ;bitpos:[31:0] ;default: 32'h16031700 ; */ 2452 /*description: This register represents the version .*/ 2453 #define LEDC_DATE 0xFFFFFFFF 2454 #define LEDC_DATE_M ((LEDC_DATE_V)<<(LEDC_DATE_S)) 2455 #define LEDC_DATE_V 0xFFFFFFFF 2456 #define LEDC_DATE_S 0 2457 2458 2459 2460 2461 #endif /*_SOC_LEDC_REG_H_ */ 2462