1 /* 2 * include/linux/amlogic/media/frame_provider/tvin/tvin.h 3 * 4 * Copyright (C) 2017 Amlogic, Inc. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 */ 17 18 #ifndef __TVIN_H 19 #define __TVIN_H 20 21 #include <linux/types.h> 22 #include <linux/amlogic/media/amvecm/cm.h> 23 24 enum { 25 MEMP_VDIN_WITHOUT_3D = 0, 26 MEMP_VDIN_WITH_3D, 27 MEMP_DCDR_WITHOUT_3D, 28 MEMP_DCDR_WITH_3D, 29 MEMP_ATV_WITHOUT_3D, 30 MEMP_ATV_WITH_3D, 31 }; 32 33 /* *********************************************************************** */ 34 35 /* * TVIN general definition/enum/struct *********************************** */ 36 37 /* ************************************************************************ */ 38 39 /* tvin input port select */ 40 enum tvin_port_e { 41 TVIN_PORT_NULL = 0x00000000, 42 TVIN_PORT_MPEG0 = 0x00000100, 43 TVIN_PORT_BT656 = 0x00000200, 44 TVIN_PORT_BT601, 45 TVIN_PORT_CAMERA, 46 TVIN_PORT_BT656_HDMI, 47 TVIN_PORT_BT601_HDMI, 48 TVIN_PORT_CVBS0 = 0x00001000, 49 TVIN_PORT_CVBS1, 50 TVIN_PORT_CVBS2, 51 TVIN_PORT_CVBS3, 52 TVIN_PORT_HDMI0 = 0x00004000, 53 TVIN_PORT_HDMI1, 54 TVIN_PORT_HDMI2, 55 TVIN_PORT_HDMI3, 56 TVIN_PORT_HDMI4, 57 TVIN_PORT_HDMI5, 58 TVIN_PORT_HDMI6, 59 TVIN_PORT_HDMI7, 60 TVIN_PORT_DVIN0 = 0x00008000, 61 TVIN_PORT_VIU1 = 0x0000a000, 62 TVIN_PORT_VIU1_VIDEO, 63 TVIN_PORT_VIU1_WB0_VD1, 64 TVIN_PORT_VIU1_WB0_VD2, 65 TVIN_PORT_VIU1_WB0_OSD1, 66 TVIN_PORT_VIU1_WB0_OSD2, 67 TVIN_PORT_VIU1_WB0_VPP, 68 TVIN_PORT_VIU1_WB0_POST_BLEND, 69 TVIN_PORT_VIU1_WB1_VD1, 70 TVIN_PORT_VIU1_WB1_VD2, 71 TVIN_PORT_VIU1_WB1_OSD1, 72 TVIN_PORT_VIU1_WB1_OSD2, 73 TVIN_PORT_VIU1_WB1_VPP, 74 TVIN_PORT_VIU1_WB1_POST_BLEND, 75 TVIN_PORT_VIU2 = 0x0000C000, 76 TVIN_PORT_VIU2_VIDEO, 77 TVIN_PORT_VIU2_WB0_VD1, 78 TVIN_PORT_VIU2_WB0_VD2, 79 TVIN_PORT_VIU2_WB0_OSD1, 80 TVIN_PORT_VIU2_WB0_OSD2, 81 TVIN_PORT_VIU2_WB0_VPP, 82 TVIN_PORT_VIU2_WB0_POST_BLEND, 83 TVIN_PORT_VIU2_WB1_VD1, 84 TVIN_PORT_VIU2_WB1_VD2, 85 TVIN_PORT_VIU2_WB1_OSD1, 86 TVIN_PORT_VIU2_WB1_OSD2, 87 TVIN_PORT_VIU2_WB1_VPP, 88 TVIN_PORT_VIU2_WB1_POST_BLEND, 89 TVIN_PORT_MIPI = 0x00010000, 90 TVIN_PORT_ISP = 0x00020000, 91 TVIN_PORT_MAX = 0x80000000, 92 }; 93 94 const char *tvin_port_str(enum tvin_port_e port); 95 96 /* tvin signal format table */ 97 enum tvin_sig_fmt_e { 98 TVIN_SIG_FMT_NULL = 0, 99 /* HDMI Formats */ 100 TVIN_SIG_FMT_HDMI_640X480P_60HZ = 0x401, 101 TVIN_SIG_FMT_HDMI_720X480P_60HZ = 0x402, 102 TVIN_SIG_FMT_HDMI_1280X720P_60HZ = 0x403, 103 TVIN_SIG_FMT_HDMI_1920X1080I_60HZ = 0x404, 104 TVIN_SIG_FMT_HDMI_1440X480I_60HZ = 0x405, 105 TVIN_SIG_FMT_HDMI_1440X240P_60HZ = 0x406, 106 TVIN_SIG_FMT_HDMI_2880X480I_60HZ = 0x407, 107 TVIN_SIG_FMT_HDMI_2880X240P_60HZ = 0x408, 108 TVIN_SIG_FMT_HDMI_1440X480P_60HZ = 0x409, 109 TVIN_SIG_FMT_HDMI_1920X1080P_60HZ = 0x40a, 110 TVIN_SIG_FMT_HDMI_720X576P_50HZ = 0x40b, 111 TVIN_SIG_FMT_HDMI_1280X720P_50HZ = 0x40c, 112 TVIN_SIG_FMT_HDMI_1920X1080I_50HZ_A = 0x40d, 113 TVIN_SIG_FMT_HDMI_1440X576I_50HZ = 0x40e, 114 TVIN_SIG_FMT_HDMI_1440X288P_50HZ = 0x40f, 115 TVIN_SIG_FMT_HDMI_2880X576I_50HZ = 0x410, 116 TVIN_SIG_FMT_HDMI_2880X288P_50HZ = 0x411, 117 TVIN_SIG_FMT_HDMI_1440X576P_50HZ = 0x412, 118 TVIN_SIG_FMT_HDMI_1920X1080P_50HZ = 0x413, 119 TVIN_SIG_FMT_HDMI_1920X1080P_24HZ = 0x414, 120 TVIN_SIG_FMT_HDMI_1920X1080P_25HZ = 0x415, 121 TVIN_SIG_FMT_HDMI_1920X1080P_30HZ = 0x416, 122 TVIN_SIG_FMT_HDMI_2880X480P_60HZ = 0x417, 123 TVIN_SIG_FMT_HDMI_2880X576P_50HZ = 0x418, 124 TVIN_SIG_FMT_HDMI_1920X1080I_50HZ_B = 0x419, 125 TVIN_SIG_FMT_HDMI_1920X1080I_100HZ = 0x41a, 126 TVIN_SIG_FMT_HDMI_1280X720P_100HZ = 0x41b, 127 TVIN_SIG_FMT_HDMI_720X576P_100HZ = 0x41c, 128 TVIN_SIG_FMT_HDMI_1440X576I_100HZ = 0x41d, 129 TVIN_SIG_FMT_HDMI_1920X1080I_120HZ = 0x41e, 130 TVIN_SIG_FMT_HDMI_1280X720P_120HZ = 0x41f, 131 TVIN_SIG_FMT_HDMI_720X480P_120HZ = 0x420, 132 TVIN_SIG_FMT_HDMI_1440X480I_120HZ = 0x421, 133 TVIN_SIG_FMT_HDMI_720X576P_200HZ = 0x422, 134 TVIN_SIG_FMT_HDMI_1440X576I_200HZ = 0x423, 135 TVIN_SIG_FMT_HDMI_720X480P_240HZ = 0x424, 136 TVIN_SIG_FMT_HDMI_1440X480I_240HZ = 0x425, 137 TVIN_SIG_FMT_HDMI_1280X720P_24HZ = 0x426, 138 TVIN_SIG_FMT_HDMI_1280X720P_25HZ = 0x427, 139 TVIN_SIG_FMT_HDMI_1280X720P_30HZ = 0x428, 140 TVIN_SIG_FMT_HDMI_1920X1080P_120HZ = 0x429, 141 TVIN_SIG_FMT_HDMI_1920X1080P_100HZ = 0x42a, 142 TVIN_SIG_FMT_HDMI_1280X720P_60HZ_FRAME_PACKING = 0x42b, 143 TVIN_SIG_FMT_HDMI_1280X720P_50HZ_FRAME_PACKING = 0x42c, 144 TVIN_SIG_FMT_HDMI_1280X720P_24HZ_FRAME_PACKING = 0x42d, 145 TVIN_SIG_FMT_HDMI_1280X720P_30HZ_FRAME_PACKING = 0x42e, 146 TVIN_SIG_FMT_HDMI_1920X1080I_60HZ_FRAME_PACKING = 0x42f, 147 TVIN_SIG_FMT_HDMI_1920X1080I_50HZ_FRAME_PACKING = 0x430, 148 TVIN_SIG_FMT_HDMI_1920X1080P_24HZ_FRAME_PACKING = 0x431, 149 TVIN_SIG_FMT_HDMI_1920X1080P_30HZ_FRAME_PACKING = 0x432, 150 TVIN_SIG_FMT_HDMI_800X600_00HZ = 0x433, 151 TVIN_SIG_FMT_HDMI_1024X768_00HZ = 0x434, 152 TVIN_SIG_FMT_HDMI_720X400_00HZ = 0x435, 153 TVIN_SIG_FMT_HDMI_1280X768_00HZ = 0x436, 154 TVIN_SIG_FMT_HDMI_1280X800_00HZ = 0x437, 155 TVIN_SIG_FMT_HDMI_1280X960_00HZ = 0x438, 156 TVIN_SIG_FMT_HDMI_1280X1024_00HZ = 0x439, 157 TVIN_SIG_FMT_HDMI_1360X768_00HZ = 0x43a, 158 TVIN_SIG_FMT_HDMI_1366X768_00HZ = 0x43b, 159 TVIN_SIG_FMT_HDMI_1600X1200_00HZ = 0x43c, 160 TVIN_SIG_FMT_HDMI_1920X1200_00HZ = 0x43d, 161 TVIN_SIG_FMT_HDMI_1440X900_00HZ = 0x43e, 162 TVIN_SIG_FMT_HDMI_1400X1050_00HZ = 0x43f, 163 TVIN_SIG_FMT_HDMI_1680X1050_00HZ = 0x440, 164 /* for alternative and 4k2k */ 165 TVIN_SIG_FMT_HDMI_1920X1080I_60HZ_ALTERNATIVE = 0x441, 166 TVIN_SIG_FMT_HDMI_1920X1080I_50HZ_ALTERNATIVE = 0x442, 167 TVIN_SIG_FMT_HDMI_1920X1080P_24HZ_ALTERNATIVE = 0x443, 168 TVIN_SIG_FMT_HDMI_1920X1080P_30HZ_ALTERNATIVE = 0x444, 169 TVIN_SIG_FMT_HDMI_3840_2160_00HZ = 0x445, 170 TVIN_SIG_FMT_HDMI_4096_2160_00HZ = 0x446, 171 TVIN_SIG_FMT_HDMI_1600X900_60HZ = 0x447, 172 TVIN_SIG_FMT_HDMI_RESERVE8 = 0x448, 173 TVIN_SIG_FMT_HDMI_RESERVE9 = 0x449, 174 TVIN_SIG_FMT_HDMI_RESERVE10 = 0x44a, 175 TVIN_SIG_FMT_HDMI_RESERVE11 = 0x44b, 176 TVIN_SIG_FMT_HDMI_720X480P_60HZ_FRAME_PACKING = 0x44c, 177 TVIN_SIG_FMT_HDMI_720X576P_50HZ_FRAME_PACKING = 0x44d, 178 TVIN_SIG_FMT_HDMI_640X480P_72HZ = 0x44e, 179 TVIN_SIG_FMT_HDMI_640X480P_75HZ = 0x44f, 180 TVIN_SIG_FMT_HDMI_MAX = 0x450, 181 TVIN_SIG_FMT_HDMI_THRESHOLD = 0x600, 182 /* Video Formats */ 183 TVIN_SIG_FMT_CVBS_NTSC_M = 0x601, 184 TVIN_SIG_FMT_CVBS_NTSC_443 = 0x602, 185 TVIN_SIG_FMT_CVBS_PAL_I = 0x603, 186 TVIN_SIG_FMT_CVBS_PAL_M = 0x604, 187 TVIN_SIG_FMT_CVBS_PAL_60 = 0x605, 188 TVIN_SIG_FMT_CVBS_PAL_CN = 0x606, 189 TVIN_SIG_FMT_CVBS_SECAM = 0x607, 190 TVIN_SIG_FMT_CVBS_NTSC_50 = 0x608, 191 TVIN_SIG_FMT_CVBS_MAX = 0x609, 192 TVIN_SIG_FMT_CVBS_THRESHOLD = 0x800, 193 /* 656 Formats */ 194 TVIN_SIG_FMT_BT656IN_576I_50HZ = 0x801, 195 TVIN_SIG_FMT_BT656IN_480I_60HZ = 0x802, 196 /* 601 Formats */ 197 TVIN_SIG_FMT_BT601IN_576I_50HZ = 0x803, 198 TVIN_SIG_FMT_BT601IN_480I_60HZ = 0x804, 199 /* Camera Formats */ 200 TVIN_SIG_FMT_CAMERA_640X480P_30HZ = 0x805, 201 TVIN_SIG_FMT_CAMERA_800X600P_30HZ = 0x806, 202 TVIN_SIG_FMT_CAMERA_1024X768P_30HZ = 0x807, 203 TVIN_SIG_FMT_CAMERA_1920X1080P_30HZ = 0x808, 204 TVIN_SIG_FMT_CAMERA_1280X720P_30HZ = 0x809, 205 TVIN_SIG_FMT_BT601_MAX = 0x80a, 206 TVIN_SIG_FMT_BT601_THRESHOLD = 0xa00, 207 TVIN_SIG_FMT_MAX, 208 }; 209 210 /* tvin signal status */ 211 enum tvin_sig_status_e { 212 TVIN_SIG_STATUS_NULL = 0, 213 /* processing status from init to */ 214 /*the finding of the 1st confirmed status */ 215 216 TVIN_SIG_STATUS_NOSIG, /* no signal - physically no signal */ 217 TVIN_SIG_STATUS_UNSTABLE, /* unstable - physically bad signal */ 218 TVIN_SIG_STATUS_NOTSUP, 219 /* not supported - physically good signal & not supported */ 220 221 TVIN_SIG_STATUS_STABLE, 222 /* stable - physically good signal & supported */ 223 }; 224 225 const char *tvin_sig_status_str(enum tvin_sig_status_e status); 226 227 /* tvin parameters */ 228 #define TVIN_PARM_FLAG_CAP 0x00000001 229 230 /* tvin_parm_t.flag[ 0]: 1/enable or 0/disable frame capture function */ 231 232 #define TVIN_PARM_FLAG_CAL 0x00000002 233 234 /* tvin_parm_t.flag[ 1]: 1/enable or 0/disable adc calibration */ 235 236 /*used for processing 3d in ppmgr set this flag*/ 237 /*to drop one field and send real height in vframe*/ 238 #define TVIN_PARM_FLAG_2D_TO_3D 0x00000004 239 240 /* tvin_parm_t.flag[ 2]: 1/enable or 0/disable 2D->3D mode */ 241 242 enum tvin_trans_fmt { 243 TVIN_TFMT_2D = 0, 244 TVIN_TFMT_3D_LRH_OLOR, 245 /* 1 Primary: Side-by-Side(Half) Odd/Left picture, Odd/Right p */ 246 247 TVIN_TFMT_3D_LRH_OLER, 248 /* 2 Primary: Side-by-Side(Half) Odd/Left picture, Even/Right picture */ 249 250 TVIN_TFMT_3D_LRH_ELOR, 251 /* 3 Primary: Side-by-Side(Half) Even/Left picture, Odd/Right picture */ 252 253 TVIN_TFMT_3D_LRH_ELER, 254 /* 4 Primary: Side-by-Side(Half) Even/Left picture, Even/Right picture*/ 255 256 TVIN_TFMT_3D_TB, /* 5 Primary: Top-and-Bottom */ 257 TVIN_TFMT_3D_FP, /* 6 Primary: Frame Packing */ 258 TVIN_TFMT_3D_FA, /* 7 Secondary: Field Alternative */ 259 TVIN_TFMT_3D_LA, /* 8 Secondary: Line Alternative */ 260 TVIN_TFMT_3D_LRF, /* 9 Secondary: Side-by-Side(Full) */ 261 TVIN_TFMT_3D_LD, /* 10 Secondary: L+depth */ 262 TVIN_TFMT_3D_LDGD, /* 11 Secondary: L+depth+Graphics+Graphics-depth */ 263 /* normal 3D format */ 264 TVIN_TFMT_3D_DET_TB, /* 12 */ 265 TVIN_TFMT_3D_DET_LR, /* 13 */ 266 TVIN_TFMT_3D_DET_INTERLACE, /* 14 */ 267 TVIN_TFMT_3D_DET_CHESSBOARD, /* 15 */ 268 }; 269 270 const char *tvin_trans_fmt_str(enum tvin_trans_fmt trans_fmt); 271 272 enum tvin_color_fmt_e { 273 TVIN_RGB444 = 0, 274 TVIN_YUV422, /* 1 */ 275 TVIN_YUV444, /* 2 */ 276 TVIN_YUYV422, /* 3 */ 277 TVIN_YVYU422, /* 4 */ 278 TVIN_UYVY422, /* 5 */ 279 TVIN_VYUY422, /* 6 */ 280 TVIN_NV12, /* 7 */ 281 TVIN_NV21, /* 8 */ 282 TVIN_BGGR, /* 9 raw data */ 283 TVIN_RGGB, /* 10 raw data */ 284 TVIN_GBRG, /* 11 raw data */ 285 TVIN_GRBG, /* 12 raw data */ 286 TVIN_COLOR_FMT_MAX, 287 }; 288 289 enum tvin_color_fmt_range_e { 290 TVIN_FMT_RANGE_NULL = 0, /* depend on vedio fromat */ 291 TVIN_RGB_FULL, /* 1 */ 292 TVIN_RGB_LIMIT, /* 2 */ 293 TVIN_YUV_FULL, /* 3 */ 294 TVIN_YUV_LIMIT, /* 4 */ 295 TVIN_COLOR_FMT_RANGE_MAX, 296 }; 297 298 const char *tvin_trans_color_range_str( 299 enum tvin_color_fmt_range_e color_range); 300 301 enum tvin_force_color_range_e { 302 COLOR_RANGE_AUTO = 0, 303 COLOR_RANGE_FULL, 304 COLOR_RANGE_LIMIT, 305 COLOR_RANGE_NULL, 306 }; 307 308 const char *tvin_trans_force_range_str( 309 enum tvin_force_color_range_e force_range); 310 311 const char *tvin_color_fmt_str(enum tvin_color_fmt_e color_fmt); 312 enum tvin_scan_mode_e { 313 TVIN_SCAN_MODE_NULL = 0, 314 TVIN_SCAN_MODE_PROGRESSIVE, 315 TVIN_SCAN_MODE_INTERLACED, 316 }; 317 318 struct tvin_info_s { 319 enum tvin_trans_fmt trans_fmt; 320 enum tvin_sig_fmt_e fmt; 321 enum tvin_sig_status_e status; 322 enum tvin_color_fmt_e cfmt; 323 unsigned int fps; 324 unsigned int is_dvi; 325 326 /* 327 * bit 30: is_dv 328 * bit 29: present_flag 329 * bit 28-26: video_format 330 * "component", "PAL", "NTSC", "SECAM", "MAC", "unspecified" 331 * bit 25: range "limited", "full_range" 332 * bit 24: color_description_present_flag 333 * bit 23-16: color_primaries 334 * "unknown", "bt709", "undef", "bt601", "bt470m", "bt470bg", 335 * "smpte170m", "smpte240m", "film", "bt2020" 336 * bit 15-8: transfer_characteristic 337 * "unknown", "bt709", "undef", "bt601", "bt470m", "bt470bg", 338 * "smpte170m", "smpte240m", "linear", "log100", "log316", 339 * "iec61966-2-4", "bt1361e", "iec61966-2-1", "bt2020-10", 340 * "bt2020-12", "smpte-st-2084", "smpte-st-428" 341 * bit 7-0: matrix_coefficient 342 * "GBR", "bt709", "undef", "bt601", "fcc", "bt470bg", 343 * "smpte170m", "smpte240m", "YCgCo", "bt2020nc", "bt2020c" 344 */ 345 unsigned int signal_type; 346 }; 347 348 struct tvin_frontend_info_s { 349 enum tvin_scan_mode_e scan_mode; 350 enum tvin_color_fmt_e cfmt; 351 unsigned int fps; 352 unsigned int width; 353 unsigned int height; 354 unsigned int colordepth; 355 }; 356 357 struct tvin_buf_info_s { 358 unsigned int vf_size; 359 unsigned int buf_count; 360 unsigned int buf_width; 361 unsigned int buf_height; 362 unsigned int buf_size; 363 unsigned int wr_list_size; 364 }; 365 366 struct tvin_video_buf_s { 367 unsigned int index; 368 unsigned int reserved; 369 }; 370 371 /* hs=he=vs=ve=0 is to disable Cut Window */ 372 struct tvin_cutwin_s { 373 unsigned short hs; 374 unsigned short he; 375 unsigned short vs; 376 unsigned short ve; 377 }; 378 379 struct tvin_parm_s { 380 int index; /* index of frontend for vdin */ 381 enum tvin_port_e port; /* must set port in IOCTL */ 382 struct tvin_info_s info; 383 unsigned int hist_pow; 384 unsigned int luma_sum; 385 unsigned int pixel_sum; 386 unsigned short histgram[64]; 387 unsigned int flag; 388 unsigned short dest_width; /* for vdin horizontal scale down */ 389 unsigned short dest_height; /* for vdin vertical scale down */ 390 bool h_reverse; /* for vdin horizontal reverse */ 391 bool v_reverse; /* for vdin vertical reverse */ 392 unsigned int reserved; 393 }; 394 395 /* ************************************************************************* */ 396 397 /* *** AFE module definition/enum/struct *********************************** */ 398 399 /* ************************************************************************* */ 400 struct tvafe_vga_parm_s { 401 signed short clk_step; /* clock < 0, tune down clock freq */ 402 /* clock > 0, tune up clock freq */ 403 unsigned short phase; /* phase is 0~31, it is absolute value */ 404 signed short hpos_step; /* hpos_step < 0, shift display to left */ 405 /* hpos_step > 0, shift display to right */ 406 signed short vpos_step; /* vpos_step < 0, shift display to top */ 407 /* vpos_step > 0, shift display to bottom */ 408 unsigned int vga_in_clean; /* flage for vga clean screen */ 409 }; 410 411 enum tvafe_cvbs_video_e { 412 TVAFE_CVBS_VIDEO_HV_UNLOCKED = 0, 413 TVAFE_CVBS_VIDEO_H_LOCKED, 414 TVAFE_CVBS_VIDEO_V_LOCKED, 415 TVAFE_CVBS_VIDEO_HV_LOCKED, 416 }; 417 418 /* for pin selection */ 419 enum tvafe_adc_pin_e { 420 TVAFE_ADC_PIN_NULL = 0, 421 /*(MESON_CPU_TYPE > MESON_CPU_TYPE_MESONG9TV) */ 422 TVAFE_CVBS_IN0 = 1, 423 TVAFE_CVBS_IN1 = 2, 424 TVAFE_CVBS_IN2 = 3, 425 TVAFE_CVBS_IN3 = 4, /*as atvdemod to tvafe */ 426 TVAFE_ADC_PIN_MAX, 427 }; 428 429 enum tvafe_src_sig_e { 430 /* TODO Only M8 first */ 431 432 /*#if (MESON_CPU_TYPE == MESON_CPU_TYPE_MESONG9TV) */ 433 CVBS_IN0 = 0, 434 CVBS_IN1, 435 CVBS_IN2, 436 CVBS_IN3, 437 TVAFE_SRC_SIG_MAX_NUM, 438 }; 439 440 struct tvafe_pin_mux_s { 441 enum tvafe_adc_pin_e pin[TVAFE_SRC_SIG_MAX_NUM]; 442 }; 443 444 /* ************************************************************************* */ 445 446 /* *** IOCTL command definition ******************************************* */ 447 448 /* ************************************************************************* */ 449 450 #define _TM_T 'T' 451 452 /* GENERAL */ 453 #define TVIN_IOC_OPEN _IOW(_TM_T, 0x01, struct tvin_parm_s) 454 #define TVIN_IOC_START_DEC _IOW(_TM_T, 0x02, struct tvin_parm_s) 455 #define TVIN_IOC_STOP_DEC _IO(_TM_T, 0x03) 456 #define TVIN_IOC_CLOSE _IO(_TM_T, 0x04) 457 #define TVIN_IOC_G_PARM _IOR(_TM_T, 0x05, struct tvin_parm_s) 458 #define TVIN_IOC_S_PARM _IOW(_TM_T, 0x06, struct tvin_parm_s) 459 #define TVIN_IOC_G_SIG_INFO _IOR(_TM_T, 0x07, struct tvin_info_s) 460 #define TVIN_IOC_G_BUF_INFO _IOR(_TM_T, 0x08, struct tvin_buf_info_s) 461 #define TVIN_IOC_START_GET_BUF _IO(_TM_T, 0x09) 462 #define TVIN_IOC_GET_BUF _IOR(_TM_T, 0x10, struct tvin_video_buf_s) 463 #define TVIN_IOC_PAUSE_DEC _IO(_TM_T, 0x41) 464 #define TVIN_IOC_RESUME_DEC _IO(_TM_T, 0x42) 465 #define TVIN_IOC_VF_REG _IO(_TM_T, 0x43) 466 #define TVIN_IOC_VF_UNREG _IO(_TM_T, 0x44) 467 #define TVIN_IOC_FREEZE_VF _IO(_TM_T, 0x45) 468 #define TVIN_IOC_UNFREEZE_VF _IO(_TM_T, 0x46) 469 #define TVIN_IOC_SNOWON _IO(_TM_T, 0x47) 470 #define TVIN_IOC_SNOWOFF _IO(_TM_T, 0x48) 471 #define TVIN_IOC_GET_COLOR_RANGE _IOR(_TM_T, 0X49,\ 472 enum tvin_force_color_range_e) 473 #define TVIN_IOC_SET_COLOR_RANGE _IOW(_TM_T, 0X4a,\ 474 enum tvin_force_color_range_e) 475 #define TVIN_IOC_GAME_MODE _IOW(_TM_T, 0x4b, unsigned int) 476 #define TVIN_IOC_SET_AUTO_RATIO_EN _IOW(_TM_T, 0x4c, unsigned int) 477 #define TVIN_IOC_GET_LATENCY_MODE _IOR(_TM_T, 0x4d,\ 478 struct tvin_latency_s) 479 #define TVIN_IOC_G_FRONTEND_INFO _IOR(_TM_T, 0x4e,\ 480 struct tvin_frontend_info_s) 481 #define TVIN_IOC_S_CANVAS_ADDR _IOW(_TM_T, 0x4f,\ 482 struct vdin_set_canvas_s) 483 #define TVIN_IOC_S_PC_MODE _IOW(_TM_T, 0x50, unsigned int) 484 #define TVIN_IOC_S_FRAME_WR_EN _IOW(_TM_T, 0x51, unsigned int) 485 #define TVIN_IOC_G_INPUT_TIMING _IOW(_TM_T, 0x52, struct tvin_format_s) 486 487 488 #define TVIN_IOC_S_CANVAS_RECOVERY _IO(_TM_T, 0x0a) 489 /* TVAFE */ 490 #define TVIN_IOC_S_AFE_VGA_PARM _IOW(_TM_T, 0x16, struct tvafe_vga_parm_s) 491 #define TVIN_IOC_G_AFE_VGA_PARM _IOR(_TM_T, 0x17, struct tvafe_vga_parm_s) 492 #define TVIN_IOC_S_AFE_VGA_AUTO _IO(_TM_T, 0x18) 493 #define TVIN_IOC_G_AFE_CVBS_LOCK _IOR(_TM_T, 0x1a, enum tvafe_cvbs_video_e) 494 #define TVIN_IOC_S_AFE_CVBS_STD _IOW(_TM_T, 0x1b, enum tvin_sig_fmt_e) 495 #define TVIN_IOC_CALLMASTER_SET _IOW(_TM_T, 0x1c, enum tvin_port_e) 496 #define TVIN_IOC_CALLMASTER_GET _IO(_TM_T, 0x1d) 497 #define TVIN_IOC_G_AFE_CVBS_STD _IOW(_TM_T, 0x1e, enum tvin_sig_fmt_e) 498 #define TVIN_IOC_LOAD_REG _IOW(_TM_T, 0x20, struct am_regs_s) 499 #define TVIN_IOC_S_AFE_SONWON _IO(_TM_T, 0x22) 500 #define TVIN_IOC_S_AFE_SONWOFF _IO(_TM_T, 0x23) 501 #define TVIN_IOC_G_VDIN_HIST _IOW(_TM_T, 0x24, struct vdin_hist_s) 502 #define TVIN_IOC_S_VDIN_V4L2START _IOW(_TM_T, 0x25, struct vdin_v4l2_param_s) 503 #define TVIN_IOC_S_VDIN_V4L2STOP _IO(_TM_T, 0x26) 504 #define TVIN_IOC_S_AFE_SONWCFG _IOW(_TM_T, 0x27, unsigned int) 505 #define TVIN_IOC_S_DV_DESCRAMBLE _IOW(_TM_T, 0x28, unsigned int) 506 #define TVIN_IOC_S_AFE_ATV_SEARCH _IOW(_TM_T, 0x29, unsigned int) 507 508 /* 509 *function defined applied for other driver 510 */ 511 512 struct dfe_adcpll_para { 513 unsigned int adcpllctl; 514 unsigned int demodctl; 515 unsigned int atsc; 516 }; 517 518 struct rx_audio_stat_s { 519 /*audio packets received*/ 520 int aud_rcv_packet; 521 /*audio stable status*/ 522 bool aud_stb_flag; 523 /*audio sample rate*/ 524 int aud_sr; 525 /**audio channel count*/ 526 /*0: refer to stream header,*/ 527 /*1: 2ch, 2: 3ch, 3: 4ch, 4: 5ch,*/ 528 /*5: 6ch, 6: 7ch, 7: 8ch*/ 529 int aud_channel_cnt; 530 /**audio coding type*/ 531 /*0: refer to stream header, 1: IEC60958 PCM,*/ 532 /*2: AC-3, 3: MPEG1 (Layers 1 and 2),*/ 533 /*4: MP3 (MPEG1 Layer 3), 5: MPEG2 (multichannel),*/ 534 /*6: AAC, 7: DTS, 8: ATRAC, 9: One Bit Audio,*/ 535 /*10: Dolby Digital Plus, 11: DTS-HD,*/ 536 /*12: MAT (MLP), 13: DST, 14: WMA Pro*/ 537 int aud_type; 538 /* indicate if audio fifo start threshold is crossed */ 539 bool afifo_thres_pass; 540 /* 541 * 0 [ch1 ch2] 542 * 1,2,3 [ch1 ch2 ch3 ch4] 543 * 4,8 [ch1 ch2 ch5 ch6] 544 * 5,6,7,9,10,11 [ch1 ch2 ch3 ch4 ch5 ch6] 545 * 12,16,24,28 [ch1 ch2 ch5 ch6 ch7 ch8] 546 * 20 [ch1 ch2 ch7 ch8] 547 * 21,22,23[ch1 ch2 ch3 ch4 ch7 ch8] 548 * all others [all of 8ch] 549 */ 550 int aud_alloc; 551 }; 552 553 extern void adc_pll_down(void); 554 /*ADC_EN_ATV_DEMOD 0x1*/ 555 /*ADC_EN_TVAFE 0x2*/ 556 /*ADC_EN_DTV_DEMOD 0x4*/ 557 /*ADC_EN_DTV_DEMODPLL 0x8*/ 558 extern int adc_set_pll_cntl(bool on, unsigned int module_sel, void *pDtvPara); 559 extern void tvafe_set_ddemod_default(void);/* add for dtv demod*/ 560 extern void rx_get_audio_status(struct rx_audio_stat_s *aud_sts); 561 562 void rx_set_atmos_flag(bool en); 563 extern bool rx_get_atmos_flag(void); 564 u_char rx_edid_get_aud_sad(u_char *sad_data); 565 bool rx_edid_set_aud_sad(u_char *sad, u_char len); 566 #endif 567