Searched refs:code_properties (Results 1 – 7 of 7) sorted by relevance
1236 Out.code_properties |= AMD_CODE_PROPERTY_IS_PTR64; in getAmdKernelCode()1239 Out.code_properties |= AMD_CODE_PROPERTY_IS_DYNAMIC_CALLSTACK; in getAmdKernelCode()1241 AMD_HSA_BITS_SET(Out.code_properties, in getAmdKernelCode()1246 Out.code_properties |= in getAmdKernelCode()1251 Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR; in getAmdKernelCode()1254 Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR; in getAmdKernelCode()1257 Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR; in getAmdKernelCode()1260 Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID; in getAmdKernelCode()1263 Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT; in getAmdKernelCode()1266 Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR; in getAmdKernelCode()[all …]
566 uint32_t code_properties; member
25 printBitField<FLD_T(code_properties),\30 parseBitField<FLD_T(code_properties),\
510 Header.code_properties |= AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32; in initDefaultAMDKernelCodeT()
461 uint32_t code_properties; member
606 AMD_HSA_BITS_GET(code_object->code_properties, AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE); in setup_scratch_rsrc_user_sgprs()653 if (AMD_HSA_BITS_GET(code_object->code_properties, in si_setup_user_sgprs_co_v2()663 if (AMD_HSA_BITS_GET(code_object->code_properties, AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR)) { in si_setup_user_sgprs_co_v2()705 if (AMD_HSA_BITS_GET(code_object->code_properties, in si_setup_user_sgprs_co_v2()714 if (code_object->code_properties & workgroup_count_masks[i]) { in si_setup_user_sgprs_co_v2()
4055 if (Header.code_properties & AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32) { in ParseAMDKernelCodeTValue()