| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
| D | MipsGenMCPseudoLowering.inc | 17 TmpInst.setOpcode(Mips::AND_V);
33 TmpInst.setOpcode(Mips::AND_V);
49 TmpInst.setOpcode(Mips::AND_V);
65 TmpInst.setOpcode(Mips::BEQ);
79 TmpInst.setOpcode(Mips::BGEZAL);
91 TmpInst.setOpcode(Mips::BGEZAL_MM);
103 TmpInst.setOpcode(Mips::BSEL_V);
122 TmpInst.setOpcode(Mips::BSEL_V);
141 TmpInst.setOpcode(Mips::BSEL_V);
160 TmpInst.setOpcode(Mips::BSEL_V);
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCDuplexInfo.cpp | 715 Result.setOpcode(Hexagon::SA1_inc); in deriveSubInst()
721 Result.setOpcode(Hexagon::SA1_dec); in deriveSubInst()
728 Result.setOpcode(Hexagon::SA1_addsp); in deriveSubInst()
734 Result.setOpcode(Hexagon::SA1_addi); in deriveSubInst()
740 Result.setOpcode(Hexagon::SA1_addrx); in deriveSubInst()
746 Result.setOpcode(Hexagon::SS2_allocframe); in deriveSubInst()
751 Result.setOpcode(Hexagon::SA1_zxtb); in deriveSubInst()
756 Result.setOpcode(Hexagon::SA1_and1); in deriveSubInst()
762 Result.setOpcode(Hexagon::SA1_cmpeqi); in deriveSubInst()
771 Result.setOpcode(Hexagon::SA1_combine1i); in deriveSubInst()
[all …]
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| D | HexagonMCCompound.cpp | 213 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
226 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
240 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
253 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
266 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
284 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
302 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
313 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
324 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/Disassembler/ |
| D | XCoreDisassembler.cpp | 280 Inst.setOpcode(XCore::STW_2rus); in Decode2OpInstructionFail()
283 Inst.setOpcode(XCore::LDW_2rus); in Decode2OpInstructionFail()
286 Inst.setOpcode(XCore::ADD_3r); in Decode2OpInstructionFail()
289 Inst.setOpcode(XCore::SUB_3r); in Decode2OpInstructionFail()
292 Inst.setOpcode(XCore::SHL_3r); in Decode2OpInstructionFail()
295 Inst.setOpcode(XCore::SHR_3r); in Decode2OpInstructionFail()
298 Inst.setOpcode(XCore::EQ_3r); in Decode2OpInstructionFail()
301 Inst.setOpcode(XCore::AND_3r); in Decode2OpInstructionFail()
304 Inst.setOpcode(XCore::OR_3r); in Decode2OpInstructionFail()
307 Inst.setOpcode(XCore::LDW_3r); in Decode2OpInstructionFail()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonAsmPrinter.cpp | 249 T.setOpcode(Inst.getOpcode()); in ScaleVectorOffset()
278 Inst.setOpcode(Hexagon::A2_addi); in HexagonProcessInstruction()
292 Inst.setOpcode(Hexagon::A2_paddif); in HexagonProcessInstruction()
299 Inst.setOpcode(Hexagon::A2_paddit); in HexagonProcessInstruction()
306 Inst.setOpcode(Hexagon::A2_paddifnew); in HexagonProcessInstruction()
313 Inst.setOpcode(Hexagon::A2_padditnew); in HexagonProcessInstruction()
320 Inst.setOpcode(Hexagon::A2_andir); in HexagonProcessInstruction()
336 TmpInst.setOpcode(Hexagon::L2_loadrdgp); in HexagonProcessInstruction()
352 TmpInst.setOpcode(Hexagon::L2_loadrigp); in HexagonProcessInstruction()
365 MappedInst.setOpcode(Hexagon::C2_or); in HexagonProcessInstruction()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenMCPseudoLowering.inc | 17 TmpInst.setOpcode(ARM::Bcc);
30 TmpInst.setOpcode(ARM::LDMIA_UPD);
55 TmpInst.setOpcode(ARM::MLA);
82 TmpInst.setOpcode(ARM::MOVr);
99 TmpInst.setOpcode(ARM::MUL);
123 TmpInst.setOpcode(ARM::SMLAL);
156 TmpInst.setOpcode(ARM::SMULL);
183 TmpInst.setOpcode(ARM::Bcc);
196 TmpInst.setOpcode(ARM::BX);
206 TmpInst.setOpcode(ARM::MOVr);
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 163 MCB.setOpcode(Hexagon::BUNDLE); in HexagonAsmParser()
533 NewInst.setOpcode(MCI.getOpcode()); in canonicalizeImmediates()
1226 TmpInst.setOpcode(opCode); in makeCombineInst()
1314 Inst.setOpcode(Hexagon::A2_addi); in processInstruction()
1348 Inst.setOpcode(Hexagon::C2_cmpgti); in processInstruction()
1362 TmpInst.setOpcode(Hexagon::C2_cmpeq); in processInstruction()
1372 Inst.setOpcode(Hexagon::C2_cmpgtui); in processInstruction()
1388 Inst.setOpcode(Hexagon::A2_combinew); in processInstruction()
1403 Inst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrpt) in processInstruction()
1419 Inst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrptnew) in processInstruction()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/AsmParser/ |
| D | PPCAsmParser.cpp | 721 TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ? in ProcessInstruction()
733 TmpInst.setOpcode(PPC::DCBT); in ProcessInstruction()
743 TmpInst.setOpcode(PPC::DCBTST); in ProcessInstruction()
760 TmpInst.setOpcode(PPC::DCBF); in ProcessInstruction()
769 TmpInst.setOpcode(PPC::LA); in ProcessInstruction()
778 TmpInst.setOpcode(PPC::ADDI); in ProcessInstruction()
787 TmpInst.setOpcode(PPC::ADDIS); in ProcessInstruction()
796 TmpInst.setOpcode(PPC::ADDIC); in ProcessInstruction()
805 TmpInst.setOpcode(PPC::ADDIC_rec); in ProcessInstruction()
817 TmpInst.setOpcode(Opcode == PPC::EXTLWI ? PPC::RLWINM : PPC::RLWINM_rec); in ProcessInstruction()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 681 MI.setOpcode(Mips::BOVC); in DecodeAddiGroupBranch()
684 MI.setOpcode(Mips::BEQC); in DecodeAddiGroupBranch()
687 MI.setOpcode(Mips::BEQZALC); in DecodeAddiGroupBranch()
709 MI.setOpcode(Mips::BOVC_MMR6); in DecodePOP35GroupBranchMMR6()
716 MI.setOpcode(Mips::BEQC_MMR6); in DecodePOP35GroupBranchMMR6()
723 MI.setOpcode(Mips::BEQZALC_MMR6); in DecodePOP35GroupBranchMMR6()
754 MI.setOpcode(Mips::BNVC); in DecodeDaddiGroupBranch()
757 MI.setOpcode(Mips::BNEC); in DecodeDaddiGroupBranch()
760 MI.setOpcode(Mips::BNEZALC); in DecodeDaddiGroupBranch()
782 MI.setOpcode(Mips::BNVC_MMR6); in DecodePOP37GroupBranchMMR6()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 2228 Inst.setOpcode(ARM::RFEDA); in DecodeMemMultipleWritebackInstruction()
2231 Inst.setOpcode(ARM::RFEDA_UPD); in DecodeMemMultipleWritebackInstruction()
2234 Inst.setOpcode(ARM::RFEDB); in DecodeMemMultipleWritebackInstruction()
2237 Inst.setOpcode(ARM::RFEDB_UPD); in DecodeMemMultipleWritebackInstruction()
2240 Inst.setOpcode(ARM::RFEIA); in DecodeMemMultipleWritebackInstruction()
2243 Inst.setOpcode(ARM::RFEIA_UPD); in DecodeMemMultipleWritebackInstruction()
2246 Inst.setOpcode(ARM::RFEIB); in DecodeMemMultipleWritebackInstruction()
2249 Inst.setOpcode(ARM::RFEIB_UPD); in DecodeMemMultipleWritebackInstruction()
2252 Inst.setOpcode(ARM::SRSDA); in DecodeMemMultipleWritebackInstruction()
2255 Inst.setOpcode(ARM::SRSDA_UPD); in DecodeMemMultipleWritebackInstruction()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64AsmPrinter.cpp | 952 MOVI.setOpcode(AArch64::MOVIv2d_ns); in EmitFMov0()
961 FMov.setOpcode(AArch64::FMOVWHr); in EmitFMov0()
966 FMov.setOpcode(AArch64::FMOVWSr); in EmitFMov0()
971 FMov.setOpcode(AArch64::FMOVXDr); in EmitFMov0()
1036 MovZ.setOpcode(AArch64::MOVZXi); in EmitInstruction()
1043 MovK.setOpcode(AArch64::MOVKXi); in EmitInstruction()
1057 TmpInst.setOpcode(AArch64::MOVIv16b_ns); in EmitInstruction()
1095 TmpInst.setOpcode(AArch64::BR); in EmitInstruction()
1104 TmpInst.setOpcode(AArch64::B); in EmitInstruction()
1127 Adrp.setOpcode(AArch64::ADRP); in EmitInstruction()
[all …]
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| D | AArch64MCInstLower.cpp | 297 OutMI.setOpcode(MI->getOpcode()); in Lower()
308 OutMI.setOpcode(AArch64::RET); in Lower()
313 OutMI.setOpcode(AArch64::RET); in Lower()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/Disassembler/ |
| D | HexagonDisassembler.cpp | 173 MI.setOpcode(Hexagon::BUNDLE); in getInstruction()
202 MI.setOpcode(Hexagon::S6_allocframe_to_raw); in remapInstruction()
210 MI.setOpcode(L6_deallocframe_map_to_raw); in remapInstruction()
218 MI.setOpcode(L6_return_map_to_raw); in remapInstruction()
226 MI.setOpcode(L4_return_map_to_raw_t); in remapInstruction()
234 MI.setOpcode(L4_return_map_to_raw_f); in remapInstruction()
242 MI.setOpcode(L4_return_map_to_raw_tnew_pt); in remapInstruction()
250 MI.setOpcode(L4_return_map_to_raw_fnew_pt); in remapInstruction()
258 MI.setOpcode(L4_return_map_to_raw_tnew_pnt); in remapInstruction()
266 MI.setOpcode(L4_return_map_to_raw_fnew_pnt); in remapInstruction()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsTargetStreamer.cpp | 169 TmpInst.setOpcode(Opcode); in emitR()
178 TmpInst.setOpcode(Opcode); in emitRX()
198 TmpInst.setOpcode(Opcode); in emitII()
209 TmpInst.setOpcode(Opcode); in emitRRX()
227 TmpInst.setOpcode(Opcode); in emitRRRX()
247 TmpInst.setOpcode(Opcode); in emitRRIII()
1134 TmpInst.setOpcode(Mips::LUi); in emitDirectiveCpLoad()
1146 TmpInst.setOpcode(Mips::ADDiu); in emitDirectiveCpLoad()
1159 TmpInst.setOpcode(Mips::ADDu); in emitDirectiveCpLoad()
1262 Inst.setOpcode(Mips::OR); in emitDirectiveCpreturn()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/MCTargetDesc/ |
| D | RISCVAsmBackend.cpp | 88 Res.setOpcode(RISCV::BEQ); in relaxInstruction()
95 Res.setOpcode(RISCV::BNE); in relaxInstruction()
102 Res.setOpcode(RISCV::JAL); in relaxInstruction()
108 Res.setOpcode(RISCV::JAL); in relaxInstruction()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 245 ITInst.setOpcode(ARM::t2IT); in flushPendingInstructions()
5585 case ARM::tBcc: Inst.setOpcode(ARM::tB); break; in cvtThumbBranches()
5586 case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break; in cvtThumbBranches()
5595 Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc); in cvtThumbBranches()
5599 Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc); in cvtThumbBranches()
5610 Inst.setOpcode(ARM::t2B); in cvtThumbBranches()
5617 Inst.setOpcode(ARM::t2Bcc); in cvtThumbBranches()
8257 TmpInst.setOpcode(Opcode); in processInstruction()
8277 TmpInst.setOpcode(Opcode); in processInstruction()
8295 TmpInst.setOpcode(Opcode); in processInstruction()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsAsmPrinter.cpp | 123 TmpInst0.setOpcode(Mips::JALR64); in emitPseudoIndirectBranch()
128 TmpInst0.setOpcode(Mips::JRC16_MMR6); in emitPseudoIndirectBranch()
130 TmpInst0.setOpcode(Mips::JALR); in emitPseudoIndirectBranch()
135 TmpInst0.setOpcode(Mips::JR_MM); in emitPseudoIndirectBranch()
138 TmpInst0.setOpcode(Mips::JR); in emitPseudoIndirectBranch()
860 I.setOpcode(Mips::JAL); in EmitJal()
869 I.setOpcode(Opcode); in EmitInstrReg()
888 I.setOpcode(Opcode); in EmitInstrRegReg()
898 I.setOpcode(Opcode); in EmitInstrRegRegReg()
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| D | MipsMCInstLower.cpp | 216 OutMI.setOpcode(Mips::LUi); in lowerLongBranchLUi()
254 OutMI.setOpcode(Opcode); in lowerLongBranchADDiu()
319 OutMI.setOpcode(MI->getOpcode()); in Lower()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 309 Inst.setOpcode(Opcode); in SimplifyShortImmForm()
337 Inst.setOpcode(NewOpcode); in SimplifyMOVSX()
388 Inst.setOpcode(Opcode); in SimplifyShortMoveForm()
466 OutMI.setOpcode(MI->getOpcode()); in Lower()
519 OutMI.setOpcode(NewOpc); in Lower()
533 OutMI.setOpcode(NewOpc); in Lower()
635 OutMI.setOpcode(NewOpc); in Lower()
707 OutMI.setOpcode(NewOpc); in Lower()
727 OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget())); in Lower()
734 OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget())); in Lower()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstrInfo.cpp | 37 NopInst.setOpcode(ARM::HINT); in getNoop()
42 NopInst.setOpcode(ARM::MOVr); in getNoop()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCAsmPrinter.cpp | 653 TmpInst.setOpcode(PPC::LWZ); in EmitInstruction()
670 TmpInst.setOpcode(PPC::ADD4); in EmitInstruction()
685 TmpInst.setOpcode(PPC::LWZ); in EmitInstruction()
743 TmpInst.setOpcode(PPC::LD); in EmitInstruction()
772 TmpInst.setOpcode(PPC::ADDIS); in EmitInstruction()
802 TmpInst.setOpcode(PPC::LWZ); in EmitInstruction()
833 TmpInst.setOpcode(PPC::ADDIS8); in EmitInstruction()
873 TmpInst.setOpcode(PPC::LD); in EmitInstruction()
905 TmpInst.setOpcode(PPC::ADDI8); in EmitInstruction()
943 TmpInst.setOpcode(IsPPC64 ? PPC::LD : PPC::LWZ); in EmitInstruction()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUMCInstLower.cpp | 188 OutMI.setOpcode(TII->pseudoToMCOpcode(AMDGPU::S_SWAPPC_B64)); in lower()
207 OutMI.setOpcode(MCOpcode); in lower()
376 OutMI.setOpcode(MI->getOpcode()); in lower()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/ |
| D | MCInstBuilder.h | 27 Inst.setOpcode(Opcode); in MCInstBuilder()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/VE/ |
| D | VEMCInstLower.cpp | 60 OutMI.setOpcode(MI->getOpcode()); in LowerVEMachineInstrToMCInst()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/ |
| D | BPFMCInstLower.cpp | 48 OutMI.setOpcode(MI->getOpcode()); in Lower()
|