Lines Matching +full:4 +full:kb +full:- +full:page
8 Linux kernel. The architecture allows up to 4 levels of translation
9 tables with a 4KB page size and up to 3 levels with a 64KB page size.
11 AArch64 Linux uses either 3 levels or 4 levels of translation tables
12 with the 4KB page configuration, allowing 39-bit (512GB) or 48-bit
14 64KB pages, only 2 levels of translation tables, allowing 42-bit (4TB)
18 only available when running with a 64KB page size and expands the
24 mappings while the user pgd contains only user (non-global) mappings.
29 AArch64 Linux memory layout with 4KB pages + 4 levels (48-bit)::
32 -----------------------------------------------------------------------
40 fffffdfffe5f9000 fffffdfffe9fffff 4124KB fixed mappings
48 AArch64 Linux memory layout with 64KB pages + 3 levels (52-bit with HW support)::
51 -----------------------------------------------------------------------
52 0000000000000000 000fffffffffffff 4PB user
60 fffffc1ffe590000 fffffc1ffe9fffff 4544KB fixed mappings
68 Translation table lookup with 4KB pages::
70 +--------+--------+--------+--------+--------+--------+--------+--------+
72 +--------+--------+--------+--------+--------+--------+--------+--------+
75 | | | | | [11:0] in-page offset
76 | | | | +-> [20:12] L3 index
77 | | | +-----------> [29:21] L2 index
78 | | +---------------------> [38:30] L1 index
79 | +-------------------------------> [47:39] L0 index
80 +-------------------------------------------------> [63] TTBR0/1
83 Translation table lookup with 64KB pages::
85 +--------+--------+--------+--------+--------+--------+--------+--------+
87 +--------+--------+--------+--------+--------+--------+--------+--------+
90 | | | | [15:0] in-page offset
91 | | | +----------> [28:16] L3 index
92 | | +--------------------------> [41:29] L2 index
93 | +-------------------------------> [47:42] L1 index (48-bit)
94 | [51:42] L1 index (52-bit)
95 +-------------------------------------------------> [63] TTBR0/1
102 GICv2 gets mapped next to the HYP idmap page, as do vectors when
108 52-bit VA support in the kernel
109 -------------------------------
110 If the ARMv8.2-LVA optional feature is present, and we are running
111 with a 64KB page size; then it is possible to use 52-bits of address
113 binary that supports 52-bit must also be able to fall back to 48-bit
117 higher addresses such that they are invariant to 48/52-bit VAs. Due
120 kernel VA space for both 48/52-bit. (Switching from 48-bit to 52-bit,
125 is kept constant at 0xFFF0000000000000 (corresponding to 52-bit),
130 As a single binary will need to support both 48-bit and 52-bit VA
131 spaces, the VMEMMAP must be sized large enough for 52-bit VAs and
149 52-bit userspace VAs
150 --------------------
152 VA space maximum size of 48-bits, the kernel will, by default,
153 return virtual addresses to userspace from a 48-bit range.
155 Software can "opt-in" to receiving VAs from a 52-bit space by
156 specifying an mmap hint parameter that is larger than 48-bit.
160 .. code-block:: c
165 from a 52-bit space by enabling the following kernel config options:
167 .. code-block:: sh