Lines Matching +full:mmp +full:- +full:timer
1 # SPDX-License-Identifier: GPL-2.0
132 The ARM series is a line of low-power-consumption RISC chip designs
134 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
135 manufactured, but legacy ARM-based PC hardware remains popular in
245 Patch phys-to-virt and virt-to-phys translation functions at
249 This can only be used with non-XIP MMU kernels where the base
295 bool "MMU-based Paged Memory Management Support"
298 Select if you want MMU-based virtualised addressing space
337 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
350 bool "EBSA-110"
359 from Digital. It has limited hardware on-board, including an
364 bool "EP93xx-based"
392 bool "IOP32x-based"
405 bool "IXP4xx-based"
441 bool "PXA2xx/PXA3xx-based"
478 On the Acorn Risc-PC, Linux can support the internal IDE disk and
479 CD-ROM interface, serial and parallel port, and the floppy drive.
482 bool "SA1100-based"
580 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
609 # This is sorted alphabetically by mach-* pathname. However, plat-*
611 # plat- suffix) or along side the corresponding mach-* source.
613 source "arch/arm/mach-actions/Kconfig"
615 source "arch/arm/mach-alpine/Kconfig"
617 source "arch/arm/mach-artpec/Kconfig"
619 source "arch/arm/mach-asm9260/Kconfig"
621 source "arch/arm/mach-aspeed/Kconfig"
623 source "arch/arm/mach-at91/Kconfig"
625 source "arch/arm/mach-axxia/Kconfig"
627 source "arch/arm/mach-bcm/Kconfig"
629 source "arch/arm/mach-berlin/Kconfig"
631 source "arch/arm/mach-clps711x/Kconfig"
633 source "arch/arm/mach-cns3xxx/Kconfig"
635 source "arch/arm/mach-davinci/Kconfig"
637 source "arch/arm/mach-digicolor/Kconfig"
639 source "arch/arm/mach-dove/Kconfig"
641 source "arch/arm/mach-ep93xx/Kconfig"
643 source "arch/arm/mach-exynos/Kconfig"
645 source "arch/arm/mach-footbridge/Kconfig"
647 source "arch/arm/mach-gemini/Kconfig"
649 source "arch/arm/mach-highbank/Kconfig"
651 source "arch/arm/mach-hisi/Kconfig"
653 source "arch/arm/mach-imx/Kconfig"
655 source "arch/arm/mach-integrator/Kconfig"
657 source "arch/arm/mach-iop32x/Kconfig"
659 source "arch/arm/mach-ixp4xx/Kconfig"
661 source "arch/arm/mach-keystone/Kconfig"
663 source "arch/arm/mach-lpc32xx/Kconfig"
665 source "arch/arm/mach-mediatek/Kconfig"
667 source "arch/arm/mach-meson/Kconfig"
669 source "arch/arm/mach-milbeaut/Kconfig"
671 source "arch/arm/mach-mmp/Kconfig"
673 source "arch/arm/mach-moxart/Kconfig"
675 source "arch/arm/mach-mstar/Kconfig"
677 source "arch/arm/mach-mv78xx0/Kconfig"
679 source "arch/arm/mach-mvebu/Kconfig"
681 source "arch/arm/mach-mxs/Kconfig"
683 source "arch/arm/mach-nomadik/Kconfig"
685 source "arch/arm/mach-npcm/Kconfig"
687 source "arch/arm/mach-nspire/Kconfig"
689 source "arch/arm/plat-omap/Kconfig"
691 source "arch/arm/mach-omap1/Kconfig"
693 source "arch/arm/mach-omap2/Kconfig"
695 source "arch/arm/mach-orion5x/Kconfig"
697 source "arch/arm/mach-oxnas/Kconfig"
699 source "arch/arm/mach-picoxcell/Kconfig"
701 source "arch/arm/mach-prima2/Kconfig"
703 source "arch/arm/mach-pxa/Kconfig"
704 source "arch/arm/plat-pxa/Kconfig"
706 source "arch/arm/mach-qcom/Kconfig"
708 source "arch/arm/mach-rda/Kconfig"
710 source "arch/arm/mach-realtek/Kconfig"
712 source "arch/arm/mach-realview/Kconfig"
714 source "arch/arm/mach-rockchip/Kconfig"
716 source "arch/arm/mach-s3c/Kconfig"
718 source "arch/arm/mach-s5pv210/Kconfig"
720 source "arch/arm/mach-sa1100/Kconfig"
722 source "arch/arm/mach-shmobile/Kconfig"
724 source "arch/arm/mach-socfpga/Kconfig"
726 source "arch/arm/mach-spear/Kconfig"
728 source "arch/arm/mach-sti/Kconfig"
730 source "arch/arm/mach-stm32/Kconfig"
732 source "arch/arm/mach-sunxi/Kconfig"
734 source "arch/arm/mach-tango/Kconfig"
736 source "arch/arm/mach-tegra/Kconfig"
738 source "arch/arm/mach-u300/Kconfig"
740 source "arch/arm/mach-uniphier/Kconfig"
742 source "arch/arm/mach-ux500/Kconfig"
744 source "arch/arm/mach-versatile/Kconfig"
746 source "arch/arm/mach-vexpress/Kconfig"
748 source "arch/arm/mach-vt8500/Kconfig"
750 source "arch/arm/mach-zx/Kconfig"
752 source "arch/arm/mach-zynq/Kconfig"
754 # ARMv7-M architecture
771 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
780 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
781 with a range of available cores like Cortex-M3/M4/M7.
822 source "arch/arm/Kconfig-nommu"
840 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
843 Executing a SWP instruction to read-only memory does not set bit 11
861 This option enables the workaround for the 430973 Cortex-A8
864 same virtual address, whether due to self-modifying code or virtual
865 to physical address re-mapping, Cortex-A8 does not recover from the
866 stale interworking branch prediction. This results in Cortex-A8
871 available in non-secure mode.
878 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
885 register may not be available in non-secure mode.
892 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
896 workaround disables the write-allocate mode for the L2 cache via the
898 may not be available in non-secure mode.
905 This option enables the workaround for the 742230 Cortex-A9
909 the diagnostic register of the Cortex-A9 which causes the DMB
918 This option enables the workaround for the 742231 Cortex-A9
920 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
925 register of the Cortex-A9 which reduces the linefill issuing
933 This option enables the workaround for the 643719 Cortex-A9 (prior to
943 This option enables the workaround for the 720789 Cortex-A9 (prior to
956 This option enables the workaround for the 743622 Cortex-A9
958 optimisation in the Cortex-A9 Store Buffer may lead to data
960 register of the Cortex-A9 which disables the Store Buffer
970 This option enables the workaround for the 751472 Cortex-A9 (prior
980 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
983 can populate the micro-TLB with a stale entry which may be hit with
991 This option enables the workaround for the 754327 Cortex-A9 (prior to
999 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1004 hit-under-miss enabled). It sets the undocumented bit 31 in
1006 register, thus disabling hit-under-miss without putting the
1015 affecting Cortex-A9 MPCore with two or more processors (all
1028 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1035 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1038 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1048 This option enables the workaround for the 773022 Cortex-A15
1058 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1060 - Cortex-A12 852422: Execution of a sequence of instructions might
1062 any Cortex-A12 cores yet.
1071 This option enables the workaround for the 821420 Cortex-A12
1075 deadlock when the VMOV instructions are issued out-of-order.
1081 This option enables the workaround for the 825619 Cortex-A12
1084 and Device/Strongly-Ordered loads and stores might cause deadlock
1090 This option enables the workaround for the 857271 Cortex-A12
1098 This option enables the workaround for the 852421 Cortex-A17
1108 - Cortex-A17 852423: Execution of a sequence of instructions might
1110 any Cortex-A17 cores yet.
1111 This is identical to Cortex-A12 erratum 852422. It is a separate
1119 This option enables the workaround for the 857272 Cortex-A17 erratum.
1121 This is identical to Cortex-A12 erratum 857271. It is a separate
1164 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
1174 This option should be selected by machines which have an SMP-
1177 The only effect of this option is to make the SMP-related
1181 bool "Symmetric Multi-Processing"
1192 If you say N here, the kernel will run on uni- and multiprocessor
1198 See also <file:Documentation/x86/i386/IO-APIC.rst>,
1199 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
1200 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1209 SMP kernels contain instructions which fail on non-SMP processors.
1226 bool "Multi-core scheduler support"
1229 Multi-core scheduler support improves the CPU scheduler's decision
1230 making when dealing with multi-core CPU chips at a cost of slightly
1247 bool "Architected timer support"
1251 This option enables support for the ARM architected timer
1256 This options enables support for the ARM timer and watchdog unit
1259 bool "Multi-Cluster Power Management"
1263 for (multi-)cluster based systems, such as big.LITTLE based
1339 int "Maximum number of CPUs (2-32)"
1345 bool "Support for hot-pluggable CPUs"
1358 implementing the PSCI specification for CPU-centric power
1392 prompt "Timer frequency"
1428 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1434 Thumb-2 mode.
1525 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1533 user-space 2nd level page tables to reside in high memory.
1536 bool "Enable use of CPU domains to implement privileged no-access"
1542 use-after-free bugs becoming an exploitable privilege escalation
1546 CPUs with low-vector mappings use a best-efforts implementation.
1579 Disabling this is usually safe for small single-platform
1606 address divisible by 4. On 32-bit ARM processors, these non-aligned
1609 correct operation of some network protocols. With an IP-only
1618 cores where a 8-word STM instruction give significantly higher
1625 However, if the CPU data cache is using a write-allocate mode,
1730 The physical address at which the ROM-able zImage is to be
1732 ROM-able zImage formats normally set this to a suitable
1742 for the ROM-able zImage which must be available while the
1745 Platforms which normally make use of ROM-able zImage formats
1797 Uses the command-line options passed by the boot loader instead of
1804 The command-line arguments provided by the boot loader will be
1815 architectures, you should supply some command-line options at build
1826 Uses the command-line options passed by the boot loader. If
1833 The command-line arguments provided by the boot loader will be
1842 command-line options your boot loader passes to the kernel.
1846 bool "Kernel Execute-In-Place from ROM"
1849 Execute-In-Place allows the kernel to run from non-volatile storage
1852 to RAM. Read-write sections, such as the data section and stack,
1914 loaded in the main kernel with kexec-tools into a specially
1919 For more details see Documentation/admin-guide/kdump/kdump.rst
1926 will be determined at run-time by masking the current IP with
1943 by UEFI firmware (such as non-volatile variables, realtime
1958 continue to boot on existing non-UEFI platforms.
1964 to be enabled much earlier than we do on ARM, which is non-trivial.
1987 your machine has an FPA or floating point co-processor podule.
1996 Say Y to include 80-bit support in the kernel floating-point
1997 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1998 Note that gcc does not generate 80-bit operations by default,
2011 It is very simple, and approximately 3-6 times faster than NWFPE.
2019 bool "VFP-format floating point maths"
2025 Please see <file:Documentation/arm/vfp/release-notes.rst> for