Lines Matching +full:imx28 +full:- +full:i2c
1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include "imx6sl-pinfunc.h"
7 #include <dt-bindings/clock/imx6sl-clock.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 * pre-existing /chosen node to be available to insert the
50 #address-cells = <1>;
51 #size-cells = <0>;
54 compatible = "arm,cortex-a9";
57 next-level-cache = <&L2>;
58 operating-points = <
64 fsl,soc-operating-points = <
65 /* ARM kHz SOC-PU uV */
70 clock-latency = <61036>; /* two CLK32 periods */
71 #cooling-cells = <2>;
75 clock-names = "arm", "pll2_pfd2_396m", "step",
77 arm-supply = <®_arm>;
78 pu-supply = <®_pu>;
79 soc-supply = <®_soc>;
80 nvmem-cells = <&cpu_speed_grade>;
81 nvmem-cell-names = "speed_grade";
87 compatible = "fixed-clock";
88 #clock-cells = <0>;
89 clock-frequency = <32768>;
93 compatible = "fixed-clock";
94 #clock-cells = <0>;
95 clock-frequency = <24000000>;
100 compatible = "arm,cortex-a9-pmu";
101 interrupt-parent = <&gpc>;
106 compatible = "usb-nop-xceiv";
107 #phy-cells = <0>;
111 #address-cells = <1>;
112 #size-cells = <1>;
113 compatible = "simple-bus";
114 interrupt-parent = <&gpc>;
118 compatible = "mmio-sram";
121 #address-cells = <1>;
122 #size-cells = <1>;
126 intc: interrupt-controller@a01000 {
127 compatible = "arm,cortex-a9-gic";
128 #interrupt-cells = <3>;
129 interrupt-controller;
132 interrupt-parent = <&intc>;
135 L2: cache-controller@a02000 {
136 compatible = "arm,pl310-cache";
139 cache-unified;
140 cache-level = <2>;
141 arm,tag-latency = <4 2 3>;
142 arm,data-latency = <4 2 3>;
146 compatible = "fsl,aips-bus", "simple-bus";
147 #address-cells = <1>;
148 #size-cells = <1>;
152 spba: spba-bus@2000000 {
153 compatible = "fsl,spba-bus", "simple-bus";
154 #address-cells = <1>;
155 #size-cells = <1>;
160 compatible = "fsl,imx6sl-spdif",
161 "fsl,imx35-spdif";
166 dma-names = "rx", "tx";
172 clock-names = "core", "rxtx0",
181 #address-cells = <1>;
182 #size-cells = <0>;
183 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
188 clock-names = "ipg", "per";
193 #address-cells = <1>;
194 #size-cells = <0>;
195 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
200 clock-names = "ipg", "per";
205 #address-cells = <1>;
206 #size-cells = <0>;
207 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
212 clock-names = "ipg", "per";
217 #address-cells = <1>;
218 #size-cells = <0>;
219 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
224 clock-names = "ipg", "per";
229 compatible = "fsl,imx6sl-uart",
230 "fsl,imx6q-uart", "fsl,imx21-uart";
235 clock-names = "ipg", "per";
237 dma-names = "rx", "tx";
242 compatible = "fsl,imx6sl-uart",
243 "fsl,imx6q-uart", "fsl,imx21-uart";
248 clock-names = "ipg", "per";
250 dma-names = "rx", "tx";
255 compatible = "fsl,imx6sl-uart",
256 "fsl,imx6q-uart", "fsl,imx21-uart";
261 clock-names = "ipg", "per";
263 dma-names = "rx", "tx";
268 #sound-dai-cells = <0>;
269 compatible = "fsl,imx6sl-ssi",
270 "fsl,imx51-ssi";
275 clock-names = "ipg", "baud";
278 dma-names = "rx", "tx";
279 fsl,fifo-depth = <15>;
284 #sound-dai-cells = <0>;
285 compatible = "fsl,imx6sl-ssi",
286 "fsl,imx51-ssi";
291 clock-names = "ipg", "baud";
294 dma-names = "rx", "tx";
295 fsl,fifo-depth = <15>;
300 #sound-dai-cells = <0>;
301 compatible = "fsl,imx6sl-ssi",
302 "fsl,imx51-ssi";
307 clock-names = "ipg", "baud";
310 dma-names = "rx", "tx";
311 fsl,fifo-depth = <15>;
316 compatible = "fsl,imx6sl-uart",
317 "fsl,imx6q-uart", "fsl,imx21-uart";
322 clock-names = "ipg", "per";
324 dma-names = "rx", "tx";
329 compatible = "fsl,imx6sl-uart",
330 "fsl,imx6q-uart", "fsl,imx21-uart";
335 clock-names = "ipg", "per";
337 dma-names = "rx", "tx";
343 #pwm-cells = <3>;
344 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
349 clock-names = "ipg", "per";
353 #pwm-cells = <3>;
354 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
359 clock-names = "ipg", "per";
363 #pwm-cells = <3>;
364 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
369 clock-names = "ipg", "per";
373 #pwm-cells = <3>;
374 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
379 clock-names = "ipg", "per";
383 compatible = "fsl,imx6sl-gpt";
388 clock-names = "ipg", "per";
392 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
396 gpio-controller;
397 #gpio-cells = <2>;
398 interrupt-controller;
399 #interrupt-cells = <2>;
400 gpio-ranges = <&iomuxc 0 22 1>, <&iomuxc 1 20 2>,
409 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
413 gpio-controller;
414 #gpio-cells = <2>;
415 interrupt-controller;
416 #interrupt-cells = <2>;
417 gpio-ranges = <&iomuxc 0 53 3>, <&iomuxc 3 72 2>,
427 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
431 gpio-controller;
432 #gpio-cells = <2>;
433 interrupt-controller;
434 #interrupt-cells = <2>;
435 gpio-ranges = <&iomuxc 0 112 8>, <&iomuxc 8 121 4>,
446 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
450 gpio-controller;
451 #gpio-cells = <2>;
452 interrupt-controller;
453 #interrupt-cells = <2>;
454 gpio-ranges = <&iomuxc 0 95 1>, <&iomuxc 1 103 1>,
472 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
476 gpio-controller;
477 #gpio-cells = <2>;
478 interrupt-controller;
479 #interrupt-cells = <2>;
480 gpio-ranges = <&iomuxc 0 158 1>, <&iomuxc 1 151 1>,
494 compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
502 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
509 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
516 clks: clock-controller@20c4000 {
517 compatible = "fsl,imx6sl-ccm";
521 #clock-cells = <1>;
525 compatible = "fsl,imx6sl-anatop",
526 "fsl,imx6q-anatop",
527 "syscon", "simple-mfd";
533 reg_vdd1p1: regulator-1p1 {
534 compatible = "fsl,anatop-regulator";
535 regulator-name = "vdd1p1";
536 regulator-min-microvolt = <1000000>;
537 regulator-max-microvolt = <1200000>;
538 regulator-always-on;
539 anatop-reg-offset = <0x110>;
540 anatop-vol-bit-shift = <8>;
541 anatop-vol-bit-width = <5>;
542 anatop-min-bit-val = <4>;
543 anatop-min-voltage = <800000>;
544 anatop-max-voltage = <1375000>;
545 anatop-enable-bit = <0>;
548 reg_vdd3p0: regulator-3p0 {
549 compatible = "fsl,anatop-regulator";
550 regulator-name = "vdd3p0";
551 regulator-min-microvolt = <2800000>;
552 regulator-max-microvolt = <3150000>;
553 regulator-always-on;
554 anatop-reg-offset = <0x120>;
555 anatop-vol-bit-shift = <8>;
556 anatop-vol-bit-width = <5>;
557 anatop-min-bit-val = <0>;
558 anatop-min-voltage = <2625000>;
559 anatop-max-voltage = <3400000>;
560 anatop-enable-bit = <0>;
563 reg_vdd2p5: regulator-2p5 {
564 compatible = "fsl,anatop-regulator";
565 regulator-name = "vdd2p5";
566 regulator-min-microvolt = <2250000>;
567 regulator-max-microvolt = <2750000>;
568 regulator-always-on;
569 anatop-reg-offset = <0x130>;
570 anatop-vol-bit-shift = <8>;
571 anatop-vol-bit-width = <5>;
572 anatop-min-bit-val = <0>;
573 anatop-min-voltage = <2100000>;
574 anatop-max-voltage = <2850000>;
575 anatop-enable-bit = <0>;
578 reg_arm: regulator-vddcore {
579 compatible = "fsl,anatop-regulator";
580 regulator-name = "vddarm";
581 regulator-min-microvolt = <725000>;
582 regulator-max-microvolt = <1450000>;
583 regulator-always-on;
584 anatop-reg-offset = <0x140>;
585 anatop-vol-bit-shift = <0>;
586 anatop-vol-bit-width = <5>;
587 anatop-delay-reg-offset = <0x170>;
588 anatop-delay-bit-shift = <24>;
589 anatop-delay-bit-width = <2>;
590 anatop-min-bit-val = <1>;
591 anatop-min-voltage = <725000>;
592 anatop-max-voltage = <1450000>;
595 reg_pu: regulator-vddpu {
596 compatible = "fsl,anatop-regulator";
597 regulator-name = "vddpu";
598 regulator-min-microvolt = <725000>;
599 regulator-max-microvolt = <1450000>;
600 anatop-reg-offset = <0x140>;
601 anatop-vol-bit-shift = <9>;
602 anatop-vol-bit-width = <5>;
603 anatop-delay-reg-offset = <0x170>;
604 anatop-delay-bit-shift = <26>;
605 anatop-delay-bit-width = <2>;
606 anatop-min-bit-val = <1>;
607 anatop-min-voltage = <725000>;
608 anatop-max-voltage = <1450000>;
611 reg_soc: regulator-vddsoc {
612 compatible = "fsl,anatop-regulator";
613 regulator-name = "vddsoc";
614 regulator-min-microvolt = <725000>;
615 regulator-max-microvolt = <1450000>;
616 regulator-always-on;
617 anatop-reg-offset = <0x140>;
618 anatop-vol-bit-shift = <18>;
619 anatop-vol-bit-width = <5>;
620 anatop-delay-reg-offset = <0x170>;
621 anatop-delay-bit-shift = <28>;
622 anatop-delay-bit-width = <2>;
623 anatop-min-bit-val = <1>;
624 anatop-min-voltage = <725000>;
625 anatop-max-voltage = <1450000>;
629 compatible = "fsl,imx6q-tempmon";
631 interrupt-parent = <&gpc>;
633 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
634 nvmem-cell-names = "calib", "temp_grade";
640 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
648 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
656 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
659 snvs_rtc: snvs-rtc-lp {
660 compatible = "fsl,sec-v4.0-mon-rtc-lp";
667 snvs_poweroff: snvs-poweroff {
668 compatible = "syscon-poweroff";
687 src: reset-controller@20d8000 {
688 compatible = "fsl,imx6sl-src", "fsl,imx51-src";
692 #reset-cells = <1>;
696 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
698 interrupt-controller;
699 #interrupt-cells = <3>;
701 interrupt-parent = <&intc>;
703 clock-names = "ipg";
706 #address-cells = <1>;
707 #size-cells = <0>;
709 power-domain@0 {
711 #power-domain-cells = <0>;
714 pd_pu: power-domain@1 {
716 #power-domain-cells = <0>;
717 power-supply = <®_pu>;
722 pd_disp: power-domain@2 {
724 #power-domain-cells = <0>;
734 gpr: iomuxc-gpr@20e0000 {
735 compatible = "fsl,imx6sl-iomuxc-gpr",
736 "fsl,imx6q-iomuxc-gpr", "syscon";
741 compatible = "fsl,imx6sl-iomuxc";
755 sdma: dma-controller@20ec000 {
756 compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma";
761 clock-names = "ipg", "ahb";
762 #dma-cells = <3>;
764 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
778 compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif";
784 clock-names = "pix", "axi", "disp_axi";
786 power-domains = <&pd_disp>;
790 compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp";
799 compatible = "fsl,aips-bus", "simple-bus";
800 #address-cells = <1>;
801 #size-cells = <1>;
806 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
812 ahb-burst-config = <0x0>;
813 tx-burst-size-dword = <0x10>;
814 rx-burst-size-dword = <0x10>;
819 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
825 ahb-burst-config = <0x0>;
826 tx-burst-size-dword = <0x10>;
827 rx-burst-size-dword = <0x10>;
832 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
840 ahb-burst-config = <0x0>;
841 tx-burst-size-dword = <0x10>;
842 rx-burst-size-dword = <0x10>;
847 #index-cells = <1>;
848 compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
854 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
859 clock-names = "ipg", "ahb";
864 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
870 clock-names = "ipg", "ahb", "per";
871 bus-width = <4>;
876 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
882 clock-names = "ipg", "ahb", "per";
883 bus-width = <4>;
888 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
894 clock-names = "ipg", "ahb", "per";
895 bus-width = <4>;
900 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
906 clock-names = "ipg", "ahb", "per";
907 bus-width = <4>;
911 i2c1: i2c@21a0000 {
912 #address-cells = <1>;
913 #size-cells = <0>;
914 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
921 i2c2: i2c@21a4000 {
922 #address-cells = <1>;
923 #size-cells = <0>;
924 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
931 i2c3: i2c@21a8000 {
932 #address-cells = <1>;
933 #size-cells = <0>;
934 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
941 memory-controller@21b0000 {
942 compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
948 compatible = "fsl,imx6sl-rngb", "fsl,imx25-rngb";
955 #address-cells = <2>;
956 #size-cells = <1>;
959 fsl,weim-cs-gpr = <&gpr>;
964 compatible = "fsl,imx6sl-ocotp", "syscon";
967 #address-cells = <1>;
968 #size-cells = <1>;
970 cpu_speed_grade: speed-grade@10 {
978 tempmon_temp_grade: temp-grade@20 {
984 compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
996 clock-names = "bus", "core";
997 power-domains = <&pd_pu>;
1006 clock-names = "bus", "core";
1007 power-domains = <&pd_pu>;