Lines Matching +full:interrupt +full:- +full:clk
1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2015-2019 Vladimir Zapolskiy <vz@mleia.com>
9 #include <dt-bindings/clock/lpc32xx-clock.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
16 interrupt-parent = <&mic>;
19 #address-cells = <1>;
20 #size-cells = <0>;
23 compatible = "arm,arm926ej-s";
31 compatible = "fixed-clock";
32 #clock-cells = <0>;
33 clock-frequency = <32768>;
34 clock-output-names = "xtal_32k";
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
40 clock-frequency = <13000000>;
41 clock-output-names = "xtal";
46 #address-cells = <1>;
47 #size-cells = <1>;
48 compatible = "simple-bus";
54 compatible = "mmio-sram";
57 #address-cells = <1>;
58 #size-cells = <1>;
66 compatible = "nxp,lpc3220-slc";
68 clocks = <&clk LPC32XX_CLK_SLC>;
73 compatible = "nxp,lpc3220-mlc";
76 clocks = <&clk LPC32XX_CLK_MLC>;
84 clocks = <&clk LPC32XX_CLK_DMA>;
85 clock-names = "apb_pclk";
89 #address-cells = <1>;
90 #size-cells = <1>;
91 compatible = "simple-bus";
98 compatible = "nxp,ohci-nxp", "usb-ohci";
100 interrupt-parent = <&sic1>;
107 compatible = "nxp,lpc3220-udc";
109 interrupt-parent = <&sic1>;
119 compatible = "nxp,pnx-i2c";
121 interrupt-parent = <&sic1>;
124 #address-cells = <1>;
125 #size-cells = <0>;
129 usbclk: clock-controller@f00 {
130 compatible = "nxp,lpc3220-usb-clk";
132 #clock-cells = <1>;
140 clocks = <&clk LPC32XX_CLK_LCD>, <&clk LPC32XX_CLK_LCD>;
141 clock-names = "clcdclk", "apb_pclk";
146 compatible = "nxp,lpc-eth";
149 clocks = <&clk LPC32XX_CLK_MAC>;
153 emc: memory-controller@31080000 {
156 clocks = <&clk LPC32XX_CLK_DDRAM>, <&clk LPC32XX_CLK_DDRAM>;
157 clock-names = "mpmcclk", "apb_pclk";
158 #address-cells = <1>;
159 #size-cells = <1>;
169 #address-cells = <1>;
170 #size-cells = <1>;
171 compatible = "simple-bus";
182 clocks = <&clk LPC32XX_CLK_SSP0>;
183 clock-names = "apb_pclk";
184 #address-cells = <1>;
185 #size-cells = <0>;
190 compatible = "nxp,lpc3220-spi";
192 clocks = <&clk LPC32XX_CLK_SPI1>;
193 #address-cells = <1>;
194 #size-cells = <0>;
206 clocks = <&clk LPC32XX_CLK_SSP1>;
207 clock-names = "apb_pclk";
208 #address-cells = <1>;
209 #size-cells = <0>;
214 compatible = "nxp,lpc3220-spi";
216 clocks = <&clk LPC32XX_CLK_SPI2>;
217 #address-cells = <1>;
218 #size-cells = <0>;
223 compatible = "nxp,lpc3220-i2s";
233 clocks = <&clk LPC32XX_CLK_SD>;
234 clock-names = "apb_pclk";
239 compatible = "nxp,lpc3220-i2s";
247 compatible = "nxp,lpc3220-uart";
250 reg-shift = <2>;
251 clocks = <&clk LPC32XX_CLK_UART5>;
256 compatible = "nxp,lpc3220-uart";
259 reg-shift = <2>;
260 clocks = <&clk LPC32XX_CLK_UART3>;
265 compatible = "nxp,lpc3220-uart";
268 reg-shift = <2>;
269 clocks = <&clk LPC32XX_CLK_UART4>;
274 compatible = "nxp,lpc3220-uart";
277 reg-shift = <2>;
278 clocks = <&clk LPC32XX_CLK_UART6>;
283 compatible = "nxp,pnx-i2c";
285 interrupt-parent = <&sic1>;
287 #address-cells = <1>;
288 #size-cells = <0>;
290 clocks = <&clk LPC32XX_CLK_I2C1>;
294 compatible = "nxp,pnx-i2c";
296 interrupt-parent = <&sic1>;
298 #address-cells = <1>;
299 #size-cells = <0>;
301 clocks = <&clk LPC32XX_CLK_I2C2>;
305 compatible = "nxp,lpc3220-motor-pwm";
308 #pwm-cells = <2>;
313 #address-cells = <1>;
314 #size-cells = <1>;
315 compatible = "simple-bus";
320 compatible = "simple-bus";
322 #address-cells = <1>;
323 #size-cells = <1>;
325 clk: clock-controller@0 { label
326 compatible = "nxp,lpc3220-clk";
328 #clock-cells = <1>;
331 clock-names = "xtal_32k", "xtal";
335 mic: interrupt-controller@40008000 {
336 compatible = "nxp,lpc3220-mic";
338 interrupt-controller;
339 #interrupt-cells = <2>;
342 sic1: interrupt-controller@4000c000 {
343 compatible = "nxp,lpc3220-sic";
345 interrupt-controller;
346 #interrupt-cells = <2>;
348 interrupt-parent = <&mic>;
353 sic2: interrupt-controller@40010000 {
354 compatible = "nxp,lpc3220-sic";
356 interrupt-controller;
357 #interrupt-cells = <2>;
359 interrupt-parent = <&mic>;
365 compatible = "nxp,lpc3220-hsuart";
372 compatible = "nxp,lpc3220-hsuart";
379 compatible = "nxp,lpc3220-hsuart";
386 compatible = "nxp,lpc3220-rtc";
388 interrupt-parent = <&sic1>;
390 clocks = <&clk LPC32XX_CLK_RTC>;
394 compatible = "nxp,lpc3220-gpio";
396 gpio-controller;
397 #gpio-cells = <3>; /* bank, pin, flags */
401 compatible = "nxp,lpc3220-timer";
404 clocks = <&clk LPC32XX_CLK_TIMER4>;
405 clock-names = "timerclk";
410 compatible = "nxp,lpc3220-timer";
413 clocks = <&clk LPC32XX_CLK_TIMER5>;
414 clock-names = "timerclk";
419 compatible = "nxp,pnx4008-wdt";
421 clocks = <&clk LPC32XX_CLK_WDOG>;
425 compatible = "nxp,lpc3220-timer";
427 clocks = <&clk LPC32XX_CLK_TIMER0>;
428 clock-names = "timerclk";
440 compatible = "nxp,lpc3220-adc";
442 interrupt-parent = <&sic1>;
444 clocks = <&clk LPC32XX_CLK_ADC>;
449 compatible = "nxp,lpc3220-tsc";
451 interrupt-parent = <&sic1>;
453 clocks = <&clk LPC32XX_CLK_ADC>;
458 compatible = "nxp,lpc3220-timer";
461 clocks = <&clk LPC32XX_CLK_TIMER1>;
462 clock-names = "timerclk";
466 compatible = "nxp,lpc3220-key";
468 clocks = <&clk LPC32XX_CLK_KEY>;
469 interrupt-parent = <&sic1>;
475 compatible = "nxp,lpc3220-timer";
478 clocks = <&clk LPC32XX_CLK_TIMER2>;
479 clock-names = "timerclk";
484 compatible = "nxp,lpc3220-pwm";
486 clocks = <&clk LPC32XX_CLK_PWM1>;
487 assigned-clocks = <&clk LPC32XX_CLK_PWM1>;
488 assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>;
493 compatible = "nxp,lpc3220-pwm";
495 clocks = <&clk LPC32XX_CLK_PWM2>;
496 assigned-clocks = <&clk LPC32XX_CLK_PWM2>;
497 assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>;
502 compatible = "nxp,lpc3220-timer";
505 clocks = <&clk LPC32XX_CLK_TIMER3>;
506 clock-names = "timerclk";