Lines Matching +full:armv6 +full:- +full:capable
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/kernel/entry-armv.S
6 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
9 * Low-level vector interface routines
20 #include <asm/glue-df.h>
21 #include <asm/glue-pf.h>
24 #include <mach/entry-macro.S>
31 #include <asm/uaccess-asm.h>
33 #include "entry-header.S"
34 #include <asm/entry-macro-multi.S>
66 @ Call the processor-specific abort handler:
68 @ r2 - pt_regs
69 @ r4 - aborted context pc
70 @ r5 - aborted context psr
91 ARM( stmib sp, {r1 - lr} )
92 THUMB( stmia sp, {r0 - r12} )
121 @ common_invalid - generic code for failed exception (re-entrant version of handlers)
126 ldmia r0, {r4 - r6}
128 mov r7, #-1 @ "" "" "" ""
130 stmia r0, {r5 - r7} @ lr_<exception>,
149 UNWIND(.save {r0 - pc} )
150 sub sp, sp, #(SVC_REGS_SIZE + \stack_hole - 4)
160 stmia sp, {r1 - r12}
162 ldmia r0, {r3 - r5}
163 add r7, sp, #S_SP - 4 @ here for interlock avoidance
164 mov r6, #-1 @ "" "" "" ""
165 add r2, sp, #(SVC_REGS_SIZE + \stack_hole - 4)
167 str r3, [sp, #-4]! @ save the "real" r0 copied
175 @ r2 - sp_svc
176 @ r3 - lr_svc
177 @ r4 - lr_<exception>, already fixed up for correct return/restart
178 @ r5 - spsr_<exception>
179 @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
181 stmia r7, {r2 - r6}
319 stmfd sp!, {r1 - r2}
324 ldmfd sp!, {r1 - r2}
341 * EABI note: sp_svc is always 64-bit aligned here, so should PT_REGS_SIZE
352 ARM( stmib sp, {r1 - r12} )
353 THUMB( stmia sp, {r0 - r12} )
358 ldmia r0, {r3 - r5}
360 mov r6, #-1 @ "" "" "" ""
370 @ r4 - lr_<exception>, already fixed up for correct return/restart
371 @ r5 - spsr_<exception>
372 @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
376 stmia r0, {r4 - r6}
378 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC )
447 @ r2 = regs->ARM_pc, which is either 2 or 4 bytes ahead of the
449 @ r3 = regs->ARM_cpsr
464 sub r4, r2, #4 @ ARM instr at LR - 4
470 @ r0 = 32-bit ARM instruction which caused the exception
471 @ r2 = PC value for the following instruction (:= regs->ARM_pc)
473 @ lr = 32-bit undefined instruction function
479 sub r4, r2, #2 @ First half of thumb instr at LR - 2
482 * Thumb-2 instruction handling. Note that because pre-v6 and >= v6 platforms
488 /* If the target CPU may not be Thumb-2-capable, a run-time check is needed: */
512 @ r0 = the two 16-bit Thumb instructions which caused the exception
513 @ r2 = PC value for the following Thumb instruction (:= regs->ARM_pc)
514 @ r4 = PC value for the first 16-bit Thumb instruction
522 .arch armv6
546 * Check whether the instruction is a co-processor instruction.
547 * If yes, we need to call the relevant co-processor handler.
549 * Note that we don't do a full check here for the co-processor
552 * co-processor instructions. However, we have to watch out
556 * NEON instructions are co-processor instructions, so we have
563 * r0 = instruction opcode (32-bit ARM or two 16-bit Thumb)
571 @ Fall-through from Thumb-2 __und_usr
596 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2
749 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack
750 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack
782 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously
783 THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously
794 * Each segment is 32-byte aligned and will be moved to the top of the high
812 .if (. - \sym) & 3
813 .rept 4 - (. - \sym) & 3
817 .rept (\size - (. - \sym)) / 4
879 sub r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64)))
881 rsbscs r8, r8, #(2b - 1b)
891 mov r0, #-1
937 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
939 rsbscs r8, r8, #(2b - 1b)
946 mov r0, #-1
960 /* beware -- each __kuser slot must be 8 instructions max */
969 ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init
978 .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
997 * SP points to a minimal amount of processor-private memory, the address
1079 .set vector_fiq_offset, .Lvector_fiq - . + 0x1000
1189 *-----------------------------------------------------------------------------
1191 * (they're not supposed to happen, and won't happen in 32-bit data mode).
1199 *-----------------------------------------------------------------------------