68  * Configures GPIOs 126, 127 and 129 to 1.8V mode instead of 3.0V
165 	u32 v;  in am35xx_enable_emac_int()  local
167 	v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);  in am35xx_enable_emac_int()
168 	v |= (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR |  in am35xx_enable_emac_int()
170 	omap_ctrl_writel(v, AM35XX_CONTROL_LVL_INTR_CLEAR);  in am35xx_enable_emac_int()
176 	u32 v;  in am35xx_disable_emac_int()  local
178 	v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);  in am35xx_disable_emac_int()
179 	v |= (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR);  in am35xx_disable_emac_int()
180 	omap_ctrl_writel(v, AM35XX_CONTROL_LVL_INTR_CLEAR);  in am35xx_disable_emac_int()
191 	u32 v;  in am35xx_emac_reset()  local
193 	v = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);  in am35xx_emac_reset()
194 	v &= ~AM35XX_CPGMACSS_SW_RST;  in am35xx_emac_reset()
195 	omap_ctrl_writel(v, AM35XX_CONTROL_IP_SW_RESET);  in am35xx_emac_reset()
485 	OF_DEV_AUXDATA("ti,omap2-iommu", 0x480bd400, "480bd400.mmu",
488 		       "480cb000.smartreflex", &omap_sr_pdata[OMAP_SR_CORE]),
490 		       "480c9000.smartreflex", &omap_sr_pdata[OMAP_SR_MPU]),
492 	OF_DEV_AUXDATA("ti,omap3-hsmmc", 0x480b4000, "480b4000.mmc", &mmc_pdata[1]),
523 	OF_DEV_AUXDATA("ti,dra7-hsmmc", 0x480b4000, "480b4000.mmc",
525 	OF_DEV_AUXDATA("ti,dra7-hsmmc", 0x480ad000, "480ad000.mmc",