Lines Matching +full:5 +full:d
30 * the cache line size of the I and D cache
49 mov r2, #(16 << 5)
57 sub r2, r2, #(1 << 5)
87 .align 5
91 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
94 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
109 .align 5
133 .align 5
149 2: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way
152 subs r1, r1, #(1 << 5) @ next set
171 .align 5
177 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
180 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
200 .align 5
216 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
228 * Ensure no D cache aliasing occurs, either with itself or
234 .align 5
237 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
246 .align 5
252 mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
253 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
273 .align 5
277 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
279 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
280 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
287 .align 5
291 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
293 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
298 mcr p15, 5, r0, c15, c14, 0 @ D inv range start
299 mcr p15, 5, r1, c15, c14, 1 @ D inv range top
313 .align 5
316 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
323 .align 5
330 mcr p15, 5, r0, c15, c13, 0 @ D clean range start
331 mcr p15, 5, r1, c15, c13, 1 @ D clean range top
344 .align 5
347 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
354 .align 5
361 mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
362 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
432 .align 5
439 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
462 .align 5
479 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
490 .align 5
495 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
519 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
520 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
533 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
536 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4